Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 12:27:11.685355 lava-dispatcher, installed at version: 2023.01
2 12:27:11.685534 start: 0 validate
3 12:27:11.685641 Start time: 2023-06-06 12:27:11.685634+00:00 (UTC)
4 12:27:11.686709 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image exists
5 12:27:12.117355 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 12:27:12.296858 cmd: ['docker', 'pull', 'kernelci/qemu']
7 12:27:12.297080 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 12:27:12.454769 >> Using default tag: latest
9 12:27:13.639947 >> latest: Pulling from kernelci/qemu
10 12:27:13.671903 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 12:27:13.672133 >> Status: Image is up to date for kernelci/qemu:latest
12 12:27:13.713504 >> docker.io/kernelci/qemu:latest
13 12:27:13.717635 Returned 0 in 1 seconds
14 12:27:13.854078 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 12:27:13.854560 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 12:27:15.654198 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 12:27:15.654641 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 12:27:16.806536 Returned 0 in 2 seconds
19 12:27:16.907854 validate duration: 5.22
21 12:27:16.908315 start: 1 deployimages (timeout 00:03:00) [common]
22 12:27:16.908452 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 12:27:16.908819 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p
24 12:27:16.909017 makedir: /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin
25 12:27:16.909175 makedir: /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/tests
26 12:27:16.909329 makedir: /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/results
27 12:27:16.909486 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-add-keys
28 12:27:16.909696 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-add-sources
29 12:27:16.909886 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-background-process-start
30 12:27:16.910071 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-background-process-stop
31 12:27:16.910253 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-common-functions
32 12:27:16.910431 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-echo-ipv4
33 12:27:16.910612 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-install-packages
34 12:27:16.910794 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-installed-packages
35 12:27:16.910972 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-os-build
36 12:27:16.911152 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-probe-channel
37 12:27:16.911329 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-probe-ip
38 12:27:16.911507 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-target-ip
39 12:27:16.911683 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-target-mac
40 12:27:16.911861 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-target-storage
41 12:27:16.912043 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-case
42 12:27:16.912220 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-event
43 12:27:16.912400 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-feedback
44 12:27:16.912578 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-raise
45 12:27:16.912761 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-reference
46 12:27:16.912937 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-runner
47 12:27:16.913113 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-set
48 12:27:16.913288 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-test-shell
49 12:27:16.913471 Updating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-install-packages (oe)
50 12:27:16.913715 Updating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/bin/lava-installed-packages (oe)
51 12:27:16.913910 Creating /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/environment
52 12:27:16.914068 LAVA metadata
53 12:27:16.914173 - LAVA_JOB_ID=568971
54 12:27:16.914273 - LAVA_DISPATCHER_IP=172.27.0.2
55 12:27:16.914421 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 12:27:16.914524 skipped lava-vland-overlay
57 12:27:16.914637 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 12:27:16.914758 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 12:27:16.914855 skipped lava-multinode-overlay
60 12:27:16.914963 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 12:27:16.915082 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 12:27:16.915197 Loading test definitions
63 12:27:16.915334 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 12:27:16.915447 Using /lava-568971 at stage 0
65 12:27:16.915901 uuid=568971_1.1.3.1 testdef=None
66 12:27:16.916038 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 12:27:16.916165 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 12:27:16.916837 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 12:27:16.917192 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 12:27:16.918030 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 12:27:16.918390 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 12:27:16.919176 runner path: /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/0/tests/0_timesync-off test_uuid 568971_1.1.3.1
75 12:27:16.919391 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 12:27:16.919744 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 12:27:16.919849 Using /lava-568971 at stage 0
79 12:27:16.919993 Fetching tests from https://github.com/kernelci/test-definitions.git
80 12:27:16.920107 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/0/tests/1_kselftest-arm64_qemu'
81 12:27:21.693985 Running '/usr/bin/git checkout kernelci.org
82 12:27:21.834461 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 12:27:21.835539 uuid=568971_1.1.3.5 testdef=None
84 12:27:21.835769 end: 1.1.3.5 git-repo-action (duration 00:00:05) [common]
86 12:27:21.836240 start: 1.1.3.6 test-overlay (timeout 00:02:55) [common]
87 12:27:21.837894 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 12:27:21.838368 start: 1.1.3.7 test-install-overlay (timeout 00:02:55) [common]
90 12:27:21.840503 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 12:27:21.841005 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:55) [common]
93 12:27:21.843107 runner path: /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/0/tests/1_kselftest-arm64_qemu test_uuid 568971_1.1.3.5
94 12:27:21.843276 BOARD='qemu_arm64-virt-gicv3'
95 12:27:21.843397 BRANCH='cip'
96 12:27:21.843517 SKIPFILE='/dev/null'
97 12:27:21.843636 SKIP_INSTALL='True'
98 12:27:21.843749 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
99 12:27:21.843866 TST_CASENAME=''
100 12:27:21.843981 TST_CMDFILES='arm64'
101 12:27:21.844245 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 12:27:21.844691 Creating lava-test-runner.conf files
104 12:27:21.844815 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/568971/lava-overlay-ml43nb8p/lava-568971/0 for stage 0
105 12:27:21.844989 - 0_timesync-off
106 12:27:21.845123 - 1_kselftest-arm64_qemu
107 12:27:21.845307 end: 1.1.3 test-definition (duration 00:00:05) [common]
108 12:27:21.845471 start: 1.1.4 compress-overlay (timeout 00:02:55) [common]
109 12:27:30.480318 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 12:27:30.480510 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:46) [common]
111 12:27:30.480602 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 12:27:30.480704 end: 1.1 lava-overlay (duration 00:00:14) [common]
113 12:27:30.480793 start: 1.2 apply-overlay-guest (timeout 00:02:46) [common]
114 12:27:30.480869 Overlay: /var/lib/lava/dispatcher/tmp/568971/compress-overlay-pn5n55k7/overlay-1.1.4.tar.gz
115 12:27:45.352430 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 12:27:45.352984 start: 1.3 deploy-device-env (timeout 00:02:32) [common]
118 12:27:45.353098 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 12:27:45.353216 start: 1.4 download-retry (timeout 00:02:32) [common]
120 12:27:45.353336 start: 1.4.1 http-download (timeout 00:02:32) [common]
121 12:27:45.353563 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
122 12:27:45.353658 saving as /var/lib/lava/dispatcher/tmp/568971/deployimages-ngcjgsyl/kernel/Image
123 12:27:45.353737 total size: 45746688 (43MB)
124 12:27:45.353823 No compression specified
125 12:27:45.710441 progress 0% (0MB)
126 12:27:46.779659 progress 5% (2MB)
127 12:27:47.139650 progress 10% (4MB)
128 12:27:47.324442 progress 15% (6MB)
129 12:27:47.685974 progress 20% (8MB)
130 12:27:47.864403 progress 25% (10MB)
131 12:27:48.047472 progress 30% (13MB)
132 12:27:48.394167 progress 35% (15MB)
133 12:27:48.577183 progress 40% (17MB)
134 12:27:48.759968 progress 45% (19MB)
135 12:27:49.104334 progress 50% (21MB)
136 12:27:49.292608 progress 55% (24MB)
137 12:27:49.474961 progress 60% (26MB)
138 12:27:49.660160 progress 65% (28MB)
139 12:27:50.000355 progress 70% (30MB)
140 12:27:50.183198 progress 75% (32MB)
141 12:27:50.363707 progress 80% (34MB)
142 12:27:50.545254 progress 85% (37MB)
143 12:27:50.880264 progress 90% (39MB)
144 12:27:51.069022 progress 95% (41MB)
145 12:27:51.253404 progress 100% (43MB)
146 12:27:51.253743 43MB downloaded in 5.90s (7.39MB/s)
147 12:27:51.254043 end: 1.4.1 http-download (duration 00:00:06) [common]
149 12:27:51.254575 end: 1.4 download-retry (duration 00:00:06) [common]
150 12:27:51.254746 start: 1.5 download-retry (timeout 00:02:26) [common]
151 12:27:51.254912 start: 1.5.1 http-download (timeout 00:02:26) [common]
152 12:27:51.255148 Not decompressing ramdisk as can be used compressed.
153 12:27:51.255322 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 12:27:51.255455 saving as /var/lib/lava/dispatcher/tmp/568971/deployimages-ngcjgsyl/ramdisk/rootfs.cpio.gz
155 12:27:51.255583 total size: 88976554 (84MB)
156 12:27:51.255710 No compression specified
157 12:27:51.435071 progress 0% (0MB)
158 12:27:51.804067 progress 5% (4MB)
159 12:27:52.349086 progress 10% (8MB)
160 12:27:53.036127 progress 15% (12MB)
161 12:27:53.569213 progress 20% (17MB)
162 12:27:53.958271 progress 25% (21MB)
163 12:27:54.485019 progress 30% (25MB)
164 12:27:55.020932 progress 35% (29MB)
165 12:27:55.552382 progress 40% (33MB)
166 12:27:56.074968 progress 45% (38MB)
167 12:27:56.605626 progress 50% (42MB)
168 12:27:56.999502 progress 55% (46MB)
169 12:27:57.527841 progress 60% (50MB)
170 12:27:58.037386 progress 65% (55MB)
171 12:27:58.433670 progress 70% (59MB)
172 12:27:58.953478 progress 75% (63MB)
173 12:27:59.486458 progress 80% (67MB)
174 12:27:59.995137 progress 85% (72MB)
175 12:28:00.389878 progress 90% (76MB)
176 12:28:00.915842 progress 95% (80MB)
177 12:28:01.444821 progress 100% (84MB)
178 12:28:01.445213 84MB downloaded in 10.19s (8.33MB/s)
179 12:28:01.445514 end: 1.5.1 http-download (duration 00:00:10) [common]
181 12:28:01.446108 end: 1.5 download-retry (duration 00:00:10) [common]
182 12:28:01.446304 end: 1 deployimages (duration 00:00:45) [common]
183 12:28:01.446505 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 12:28:01.446744 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 12:28:01.446959 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 12:28:01.447364 Extending command line for qcow2 test overlay
187 12:28:01.448011 Pulling docker image
188 12:28:01.448190 cmd: ['docker', 'pull', 'kernelci/qemu']
189 12:28:01.448350 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 12:28:01.616007 >> Using default tag: latest
191 12:28:02.769464 >> latest: Pulling from kernelci/qemu
192 12:28:02.801510 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 12:28:02.801772 >> Status: Image is up to date for kernelci/qemu:latest
194 12:28:02.834891 >> docker.io/kernelci/qemu:latest
195 12:28:02.837697 Returned 0 in 1 seconds
196 12:28:02.972574 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-568971-2.1.1-uyxkyom7uy --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/568971/deployimages-ngcjgsyl/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/568971/deployimages-ngcjgsyl/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/568971/apply-overlay-guest-fh7pxi7w/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 12:28:03.104165 started a shell command
198 12:28:03.104743 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 12:28:03.104893 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 12:28:03.105035 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 12:28:03.105168 Setting prompt string to ['Linux version [0-9]']
202 12:28:03.105278 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 12:28:06.806357 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 12:28:06.808091 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
205 12:28:06.808217 [ 0.000000] random: crng init done
206 12:28:06.808309 [ 0.000000] Machine model: linux,dummy-virt
207 12:28:06.808392 [ 0.000000] efi: UEFI not found.
208 12:28:06.808473 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
209 12:28:06.808558 [ 0.000000] printk: bootconsole [pl11] enabled
210 12:28:06.808953 start: 2.2.1 login-action (timeout 00:04:55) [common]
211 12:28:06.809161 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
212 12:28:06.809358 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
213 12:28:06.809521 Using line separator: #'\n'#
214 12:28:06.809656 No login prompt set.
215 12:28:06.809795 Parsing kernel messages
216 12:28:06.809915 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
217 12:28:06.810141 [login-action] Waiting for messages, (timeout 00:04:55)
218 12:28:06.811477 [ 0.000000] NUMA: No NUMA configuration found
219 12:28:06.811889 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 12:28:06.812317 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf3a00-0x7fdf5fff]
221 12:28:06.814584 [ 0.000000] Zone ranges:
222 12:28:06.815541 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 12:28:06.815647 [ 0.000000] DMA32 empty
224 12:28:06.815732 [ 0.000000] Normal empty
225 12:28:06.815828 [ 0.000000] Movable zone start for each node
226 12:28:06.815911 [ 0.000000] Early memory node ranges
227 12:28:06.816005 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 12:28:06.816295 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 12:28:06.831826 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 12:28:06.832637 [ 0.000000] psci: probing for conduit method from DT.
231 12:28:06.832945 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 12:28:06.833280 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 12:28:06.833382 [ 0.000000] psci: Trusted OS migration not required
234 12:28:06.833477 [ 0.000000] psci: SMC Calling Convention v1.0
235 12:28:06.835678 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
236 12:28:06.836105 [ 0.000000] pcpu-alloc: s45224 r8192 d32600 u86016 alloc=21*4096
237 12:28:06.836307 [ 0.000000] pcpu-alloc: [0] 0
238 12:28:06.837829 [ 0.000000] Detected PIPT I-cache on CPU0
239 12:28:06.843674 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 12:28:06.844323 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 12:28:06.844443 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 12:28:06.844746 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 12:28:06.844852 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 12:28:06.845154 [ 0.000000] CPU features: detected: Spectre-v4
245 12:28:06.848792 [ 0.000000] alternatives: applying boot alternatives
246 12:28:06.851648 [ 0.000000] Fallback order for Node 0: 0
247 12:28:06.852011 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 12:28:06.852104 [ 0.000000] Policy zone: DMA
249 12:28:06.852406 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 12:28:06.854957 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 12:28:06.857700 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 12:28:06.858038 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 12:28:06.858369 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 12:28:06.868165 <6>[ 0.000000] Memory: 862480K/1048576K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 153328K reserved, 32768K cma-reserved)
255 12:28:06.873703 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 12:28:06.880449 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 12:28:06.881037 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 12:28:06.881216 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 12:28:06.881387 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 12:28:06.881584 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 12:28:06.881768 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 12:28:06.881955 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 12:28:06.882485 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 12:28:06.889396 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 12:28:06.889723 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 12:28:06.891177 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 12:28:06.891517 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 12:28:06.892405 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 12:28:06.896778 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 12:28:06.897779 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43030000 (indirect, esz 8, psz 64K, shr 1)
271 12:28:06.898029 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43040000 (flat, esz 8, psz 64K, shr 1)
272 12:28:06.898644 <6>[ 0.000000] GICv3: using LPI property table @0x0000000043050000
273 12:28:06.899560 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043060000
274 12:28:06.900633 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 12:28:06.909239 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 12:28:06.909575 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 12:28:06.910314 <6>[ 0.000077] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 12:28:06.928242 <6>[ 0.015308] Console: colour dummy device 80x25
279 12:28:06.932299 <6>[ 0.021480] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 12:28:06.932766 <6>[ 0.022648] pid_max: default: 32768 minimum: 301
281 12:28:06.934070 <6>[ 0.023932] LSM: Security Framework initializing
282 12:28:06.938433 <6>[ 0.028234] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 12:28:06.938607 <6>[ 0.028522] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 12:28:06.971892 <4>[ 0.061781] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 12:28:06.978314 <6>[ 0.068119] cblist_init_generic: Setting adjustable number of callback queues.
286 12:28:06.978520 <6>[ 0.068480] cblist_init_generic: Setting shift to 0 and lim to 1.
287 12:28:06.979207 <6>[ 0.069129] cblist_init_generic: Setting shift to 0 and lim to 1.
288 12:28:06.980829 <6>[ 0.070914] rcu: Hierarchical SRCU implementation.
289 12:28:06.981183 <6>[ 0.071087] rcu: Max phase no-delay instances is 1000.
290 12:28:06.987008 <6>[ 0.076804] Platform MSI: its@8080000 domain created
291 12:28:06.987750 <6>[ 0.077451] PCI/MSI: /intc@8000000/its@8080000 domain created
292 12:28:06.988135 <6>[ 0.078070] fsl-mc MSI: its@8080000 domain created
293 12:28:06.991376 <6>[ 0.081229] EFI services will not be available.
294 12:28:06.992155 <6>[ 0.082251] smp: Bringing up secondary CPUs ...
295 12:28:06.992502 <6>[ 0.082465] smp: Brought up 1 node, 1 CPU
296 12:28:06.992624 <6>[ 0.082614] SMP: Total of 1 processors activated.
297 12:28:06.992955 <6>[ 0.082988] CPU features: detected: Branch Target Identification
298 12:28:06.993299 <6>[ 0.083192] CPU features: detected: 32-bit EL0 Support
299 12:28:06.993391 <6>[ 0.083376] CPU features: detected: 32-bit EL1 Support
300 12:28:06.993488 <6>[ 0.083509] CPU features: detected: ARMv8.4 Translation Table Level
301 12:28:06.993871 <6>[ 0.083710] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 12:28:06.994300 <6>[ 0.084194] CPU features: detected: Common not Private translations
303 12:28:06.994685 <6>[ 0.084405] CPU features: detected: CRC32 instructions
304 12:28:06.994885 <6>[ 0.084576] CPU features: detected: E0PD
305 12:28:06.995172 <6>[ 0.084800] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 12:28:06.995380 <6>[ 0.085027] CPU features: detected: RCpc load-acquire (LDAPR)
307 12:28:06.995674 <6>[ 0.085241] CPU features: detected: LSE atomic instructions
308 12:28:06.995857 <6>[ 0.085453] CPU features: detected: Privileged Access Never
309 12:28:06.996024 <6>[ 0.085614] CPU features: detected: RAS Extension Support
310 12:28:06.996221 <6>[ 0.085788] CPU features: detected: Random Number Generator
311 12:28:06.996382 <6>[ 0.085960] CPU features: detected: Speculation barrier (SB)
312 12:28:06.996540 <6>[ 0.086149] CPU features: detected: Stage-2 Force Write-Back
313 12:28:06.996743 <6>[ 0.086367] CPU features: detected: TLB range maintenance instructions
314 12:28:06.996917 <6>[ 0.086632] CPU features: detected: Scalable Matrix Extension
315 12:28:06.997120 <6>[ 0.086814] CPU features: detected: FA64
316 12:28:06.997271 <6>[ 0.086953] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 12:28:06.997417 <6>[ 0.087180] CPU features: detected: Scalable Vector Extension
318 12:28:07.009773 <6>[ 0.096961] SVE: maximum available vector length 256 bytes per vector
319 12:28:07.010334 <6>[ 0.100206] SVE: default vector length 64 bytes per vector
320 12:28:07.012288 <6>[ 0.102120] SME: minimum available vector length 16 bytes per vector
321 12:28:07.012397 <6>[ 0.102302] SME: maximum available vector length 256 bytes per vector
322 12:28:07.012504 <6>[ 0.102486] SME: default vector length 32 bytes per vector
323 12:28:07.013054 <6>[ 0.102940] CPU: All CPU(s) started at EL1
324 12:28:07.013441 <6>[ 0.103304] alternatives: applying system-wide alternatives
325 12:28:07.067852 <6>[ 0.157662] devtmpfs: initialized
326 12:28:07.088006 <6>[ 0.177779] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 12:28:07.089437 <6>[ 0.179450] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 12:28:07.094939 <6>[ 0.184711] pinctrl core: initialized pinctrl subsystem
329 12:28:07.106143 <6>[ 0.196109] DMI not present or invalid.
330 12:28:07.115602 <6>[ 0.205551] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 12:28:07.127568 <6>[ 0.217151] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 12:28:07.128026 <6>[ 0.218042] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 12:28:07.128730 <6>[ 0.218494] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 12:28:07.128963 <6>[ 0.218949] audit: initializing netlink subsys (disabled)
335 12:28:07.134760 <5>[ 0.224503] audit: type=2000 audit(0.188:1): state=initialized audit_enabled=0 res=1
336 12:28:07.137185 <6>[ 0.226963] thermal_sys: Registered thermal governor 'step_wise'
337 12:28:07.137900 <6>[ 0.227034] thermal_sys: Registered thermal governor 'power_allocator'
338 12:28:07.138016 <6>[ 0.227768] cpuidle: using governor menu
339 12:28:07.139033 <6>[ 0.228846] NET: Registered PF_QIPCRTR protocol family
340 12:28:07.142023 <6>[ 0.231833] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
341 12:28:07.142496 <6>[ 0.232492] ASID allocator initialised with 65536 entries
342 12:28:07.148391 <6>[ 0.238410] Serial: AMBA PL011 UART driver
343 12:28:07.197381 <6>[ 0.287024] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
344 12:28:07.198768 <6>[ 0.288721] printk: console [ttyAMA0] enabled
345 12:28:07.199113 <6>[ 0.288721] printk: console [ttyAMA0] enabled
346 12:28:07.199229 <6>[ 0.289272] printk: bootconsole [pl11] disabled
347 12:28:07.199340 <6>[ 0.289272] printk: bootconsole [pl11] disabled
348 12:28:07.210183 <6>[ 0.300219] KASLR enabled
349 12:28:07.246466 <6>[ 0.336354] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
350 12:28:07.247104 <6>[ 0.336598] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
351 12:28:07.247288 <6>[ 0.336817] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
352 12:28:07.247466 <6>[ 0.337015] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
353 12:28:07.247671 <6>[ 0.337183] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
354 12:28:07.247833 <6>[ 0.337428] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
355 12:28:07.247961 <6>[ 0.337633] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
356 12:28:07.248109 <6>[ 0.337824] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
357 12:28:07.257658 <6>[ 0.347628] ACPI: Interpreter disabled.
358 12:28:07.265847 <6>[ 0.355798] iommu: Default domain type: Translated
359 12:28:07.266289 <6>[ 0.356056] iommu: DMA domain TLB invalidation policy: strict mode
360 12:28:07.268095 <5>[ 0.357842] SCSI subsystem initialized
361 12:28:07.269010 <7>[ 0.358830] libata version 3.00 loaded.
362 12:28:07.270351 <6>[ 0.360251] usbcore: registered new interface driver usbfs
363 12:28:07.270738 <6>[ 0.360665] usbcore: registered new interface driver hub
364 12:28:07.271252 <6>[ 0.361042] usbcore: registered new device driver usb
365 12:28:07.274670 <6>[ 0.364495] pps_core: LinuxPPS API ver. 1 registered
366 12:28:07.274807 <6>[ 0.364663] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
367 12:28:07.275162 <6>[ 0.365036] PTP clock support registered
368 12:28:07.275640 <6>[ 0.365691] EDAC MC: Ver: 3.0.0
369 12:28:07.282062 <6>[ 0.372058] FPGA manager framework
370 12:28:07.282937 <6>[ 0.372971] Advanced Linux Sound Architecture Driver Initialized.
371 12:28:07.292798 <6>[ 0.382771] vgaarb: loaded
372 12:28:07.296924 <6>[ 0.386750] clocksource: Switched to clocksource arch_sys_counter
373 12:28:07.299508 <5>[ 0.389568] VFS: Disk quotas dquot_6.6.0
374 12:28:07.299982 <6>[ 0.389913] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
375 12:28:07.302436 <6>[ 0.392274] pnp: PnP ACPI: disabled
376 12:28:07.319856 <6>[ 0.409806] NET: Registered PF_INET protocol family
377 12:28:07.322409 <6>[ 0.412085] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
378 12:28:07.327023 <6>[ 0.416837] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
379 12:28:07.327251 <6>[ 0.417191] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
380 12:28:07.327591 <6>[ 0.417446] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
381 12:28:07.327915 <6>[ 0.417859] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
382 12:28:07.328498 <6>[ 0.418394] TCP: Hash tables configured (established 8192 bind 8192)
383 12:28:07.329666 <6>[ 0.419663] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
384 12:28:07.330217 <6>[ 0.420083] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
385 12:28:07.331404 <6>[ 0.421266] NET: Registered PF_UNIX/PF_LOCAL protocol family
386 12:28:07.334364 <6>[ 0.424210] RPC: Registered named UNIX socket transport module.
387 12:28:07.334517 <6>[ 0.424445] RPC: Registered udp transport module.
388 12:28:07.334631 <6>[ 0.424607] RPC: Registered tcp transport module.
389 12:28:07.334978 <6>[ 0.424773] RPC: Registered tcp NFSv4.1 backchannel transport module.
390 12:28:07.335099 <6>[ 0.425083] PCI: CLS 0 bytes, default 64
391 12:28:07.339003 <6>[ 0.429111] Unpacking initramfs...
392 12:28:07.350915 <6>[ 0.440798] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
393 12:28:07.351630 <6>[ 0.441693] kvm [1]: HYP mode not available
394 12:28:07.360409 <5>[ 0.450367] Initialise system trusted keyrings
395 12:28:07.365399 <6>[ 0.455191] workingset: timestamp_bits=42 max_order=18 bucket_order=0
396 12:28:07.404858 <6>[ 0.494779] squashfs: version 4.0 (2009/01/31) Phillip Lougher
397 12:28:07.410118 <5>[ 0.499925] NFS: Registering the id_resolver key type
398 12:28:07.410302 <5>[ 0.500344] Key type id_resolver registered
399 12:28:07.410634 <5>[ 0.500515] Key type id_legacy registered
400 12:28:07.411319 <6>[ 0.501070] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
401 12:28:07.411533 <6>[ 0.501376] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
402 12:28:07.416598 <6>[ 0.506640] 9p: Installing v9fs 9p2000 file system support
403 12:28:07.481170 <5>[ 0.571092] Key type asymmetric registered
404 12:28:07.481801 <5>[ 0.571320] Asymmetric key parser 'x509' registered
405 12:28:07.481969 <6>[ 0.571762] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
406 12:28:07.482156 <6>[ 0.572091] io scheduler mq-deadline registered
407 12:28:07.482337 <6>[ 0.572310] io scheduler kyber registered
408 12:28:07.550478 <6>[ 0.640283] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
409 12:28:07.565644 <6>[ 0.655494] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
410 12:28:07.566698 <6>[ 0.656424] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
411 12:28:07.567400 <6>[ 0.657169] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
412 12:28:07.567629 <6>[ 0.657501] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
413 12:28:07.568475 <4>[ 0.658209] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
414 12:28:07.573589 <6>[ 0.663067] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
415 12:28:07.574910 <6>[ 0.664719] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
416 12:28:07.575193 <6>[ 0.665179] pci_bus 0000:00: root bus resource [bus 00-ff]
417 12:28:07.575681 <6>[ 0.665445] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
418 12:28:07.575880 <6>[ 0.665685] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
419 12:28:07.576094 <6>[ 0.665891] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
420 12:28:07.581818 <6>[ 0.671539] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
421 12:28:07.589652 <6>[ 0.679369] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
422 12:28:07.589905 <6>[ 0.679860] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
423 12:28:07.590242 <6>[ 0.680106] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
424 12:28:07.590577 <6>[ 0.680380] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
425 12:28:07.590689 <6>[ 0.680686] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
426 12:28:07.591530 <6>[ 0.681364] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
427 12:28:07.591662 <6>[ 0.681573] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
428 12:28:07.592017 <6>[ 0.681767] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
429 12:28:07.592151 <6>[ 0.682048] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
430 12:28:07.599392 <6>[ 0.689111] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
431 12:28:07.599863 <6>[ 0.689668] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
432 12:28:07.600221 <6>[ 0.690060] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
433 12:28:07.600581 <6>[ 0.690386] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
434 12:28:07.604917 <6>[ 0.694672] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
435 12:28:07.605151 <6>[ 0.694909] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
436 12:28:07.605240 <6>[ 0.695124] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
437 12:28:07.621166 <6>[ 0.711153] EINJ: ACPI disabled.
438 12:28:07.711921 <6>[ 0.801821] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
439 12:28:07.719852 <6>[ 0.809496] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
440 12:28:07.753870 <6>[ 0.843776] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
441 12:28:07.768897 <6>[ 0.858828] SuperH (H)SCI(F) driver initialized
442 12:28:07.770580 <6>[ 0.860410] msm_serial: driver initialized
443 12:28:07.803811 <4>[ 0.893731] cacheinfo: Unable to detect cache hierarchy for CPU 0
444 12:28:07.836373 <6>[ 0.926285] loop: module loaded
445 12:28:07.841367 <6>[ 0.931321] virtio_blk virtio1: 1/0/0 default/read/poll queues
446 12:28:07.858350 <5>[ 0.948240] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
447 12:28:07.887107 <6>[ 0.977052] megasas: 07.719.03.00-rc1
448 12:28:07.906494 <5>[ 0.996146] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
449 12:28:07.908119 <6>[ 0.997944] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
450 12:28:07.912830 <6>[ 1.002823] Intel/Sharp Extended Query Table at 0x0031
451 12:28:07.913611 <6>[ 1.003625] Using buffer write method
452 12:28:07.914185 <7>[ 1.004065] erase region 0: offset=0x0,size=0x40000,blocks=256
453 12:28:07.914513 <5>[ 1.004465] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
454 12:28:07.915397 <6>[ 1.005165] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
455 12:28:07.915591 <6>[ 1.005513] Intel/Sharp Extended Query Table at 0x0031
456 12:28:07.916201 <6>[ 1.006088] Using buffer write method
457 12:28:07.916312 <7>[ 1.006219] erase region 0: offset=0x0,size=0x40000,blocks=256
458 12:28:07.920533 <5>[ 1.010638] Concatenating MTD devices:
459 12:28:07.920885 <5>[ 1.010781] (0): \"0.flash\"
460 12:28:07.920991 <5>[ 1.010884] (1): \"0.flash\"
461 12:28:07.921092 <5>[ 1.010969] into device \"0.flash\"
462 12:28:12.689977 <6>[ 5.779848] Freeing initrd memory: 86888K
463 12:28:12.814081 <6>[ 5.903952] tun: Universal TUN/TAP device driver, 1.6
464 12:28:12.823807 <6>[ 5.913802] thunder_xcv, ver 1.0
465 12:28:12.824321 <6>[ 5.914078] thunder_bgx, ver 1.0
466 12:28:12.824502 <6>[ 5.914291] nicpf, ver 1.0
467 12:28:12.827783 <6>[ 5.917500] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
468 12:28:12.828049 <6>[ 5.917718] hns3: Copyright (c) 2017 Huawei Corporation.
469 12:28:12.828231 <6>[ 5.918127] hclge is initializing
470 12:28:12.828399 <6>[ 5.918360] e1000: Intel(R) PRO/1000 Network Driver
471 12:28:12.828867 <6>[ 5.918613] e1000: Copyright (c) 1999-2006 Intel Corporation.
472 12:28:12.829078 <6>[ 5.918942] e1000e: Intel(R) PRO/1000 Network Driver
473 12:28:12.829235 <6>[ 5.919080] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
474 12:28:12.829433 <6>[ 5.919372] igb: Intel(R) Gigabit Ethernet Network Driver
475 12:28:12.829592 <6>[ 5.919532] igb: Copyright (c) 2007-2014 Intel Corporation.
476 12:28:12.829802 <6>[ 5.919803] igbvf: Intel(R) Gigabit Virtual Function Network Driver
477 12:28:12.830035 <6>[ 5.919988] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
478 12:28:12.830838 <6>[ 5.920913] sky2: driver version 1.30
479 12:28:12.834289 <6>[ 5.924329] VFIO - User Level meta-driver version: 0.3
480 12:28:12.843270 <6>[ 5.933265] usbcore: registered new interface driver usb-storage
481 12:28:12.844148 <6>[ 5.934010] usbcore: registered new device driver onboard-usb-hub
482 12:28:12.853283 <6>[ 5.943249] rtc-pl031 9010000.pl031: registered as rtc0
483 12:28:12.854444 <6>[ 5.944036] rtc-pl031 9010000.pl031: setting system clock to 2023-06-06T12:28:12 UTC (1686054492)
484 12:28:12.857791 <6>[ 5.947631] i2c_dev: i2c /dev entries driver
485 12:28:12.875988 <6>[ 5.965933] sdhci: Secure Digital Host Controller Interface driver
486 12:28:12.876484 <6>[ 5.966126] sdhci: Copyright(c) Pierre Ossman
487 12:28:12.878207 <6>[ 5.968079] Synopsys Designware Multimedia Card Interface Driver
488 12:28:12.880535 <6>[ 5.970411] sdhci-pltfm: SDHCI platform and OF driver helper
489 12:28:12.885944 <6>[ 5.975805] ledtrig-cpu: registered to indicate activity on CPUs
490 12:28:12.891739 <6>[ 5.981545] usbcore: registered new interface driver usbhid
491 12:28:12.891898 <6>[ 5.981732] usbhid: USB HID core driver
492 12:28:12.915521 <6>[ 6.005454] NET: Registered PF_PACKET protocol family
493 12:28:12.916788 <6>[ 6.006659] 9pnet: Installing 9P2000 support
494 12:28:12.917151 <5>[ 6.007047] Key type dns_resolver registered
495 12:28:12.918552 <6>[ 6.008431] registered taskstats version 1
496 12:28:12.918898 <5>[ 6.008798] Loading compiled-in X.509 certificates
497 12:28:12.939946 <6>[ 6.029826] input: gpio-keys as /devices/platform/gpio-keys/input/input0
498 12:28:12.947372 <6>[ 6.037368] ALSA device list:
499 12:28:12.947844 <6>[ 6.037557] No soundcards found.
500 12:28:12.950352 <6>[ 6.040403] uart-pl011 9000000.pl011: no DMA platform data
501 12:28:13.008092 <6>[ 6.097987] Freeing unused kernel memory: 8384K
502 12:28:13.009348 <6>[ 6.099170] Run /init as init process
503 12:28:13.009458 <7>[ 6.099305] with arguments:
504 12:28:13.009546 <7>[ 6.099405] /init
505 12:28:13.009628 <7>[ 6.099480] verbose
506 12:28:13.009736 <7>[ 6.099557] with environment:
507 12:28:13.009820 <7>[ 6.099648] HOME=/
508 12:28:13.009902 <7>[ 6.099718] TERM=linux
509 12:28:13.150806 <30>[ 6.240326] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
510 12:28:13.151615 <31>[ 6.241659] systemd[1]: No virtualization found in DMI
511 12:28:13.153210 <31>[ 6.242991] systemd[1]: UML virtualization not found in /proc/cpuinfo.
512 12:28:13.153595 <31>[ 6.243333] systemd[1]: No virtualization found in CPUID
513 12:28:13.153827 <31>[ 6.243645] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
514 12:28:13.154982 <31>[ 6.244803] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
515 12:28:13.155213 <31>[ 6.245242] systemd[1]: Found VM virtualization qemu
516 12:28:13.155558 <30>[ 6.245554] systemd[1]: Detected virtualization qemu.
517 12:28:13.155969 <30>[ 6.245920] systemd[1]: Detected architecture arm64.
518 12:28:13.156441 <31>[ 6.246292] systemd[1]: Detected initialized system, this is not the first boot.
519 12:28:13.160891
520 12:28:13.161418 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
521 12:28:13.161580
522 12:28:13.163415 <30>[ 6.253170] systemd[1]: Set hostname to <debian-bullseye-arm64>.
523 12:28:13.183184 <31>[ 6.273078] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
524 12:28:13.184695 <31>[ 6.274315] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
525 12:28:13.185555 <31>[ 6.275358] systemd[1]: Successfully brought loopback interface up
526 12:28:13.190162 <31>[ 6.280164] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
527 12:28:13.202854 <31>[ 6.292789] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
528 12:28:13.203319 <31>[ 6.293106] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
529 12:28:13.261472 <31>[ 6.350942] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
530 12:28:13.263570 <31>[ 6.353225] systemd[1]: Controller 'cpu' supported: yes
531 12:28:13.263796 <31>[ 6.353528] systemd[1]: Controller 'cpuacct' supported: no
532 12:28:13.263996 <31>[ 6.353759] systemd[1]: Controller 'cpuset' supported: yes
533 12:28:13.264159 <31>[ 6.353978] systemd[1]: Controller 'io' supported: yes
534 12:28:13.264359 <31>[ 6.354206] systemd[1]: Controller 'blkio' supported: no
535 12:28:13.264720 <31>[ 6.354441] systemd[1]: Controller 'memory' supported: yes
536 12:28:13.265213 <31>[ 6.355163] systemd[1]: Controller 'devices' supported: no
537 12:28:13.265438 <31>[ 6.355422] systemd[1]: Controller 'pids' supported: yes
538 12:28:13.265956 <31>[ 6.355652] systemd[1]: Controller 'bpf-firewall' supported: yes
539 12:28:13.266115 <31>[ 6.355920] systemd[1]: Controller 'bpf-devices' supported: yes
540 12:28:13.267840 <31>[ 6.357616] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
541 12:28:13.268419 <31>[ 6.358156] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
542 12:28:13.269762 <31>[ 6.359521] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
543 12:28:13.281725 <31>[ 6.371574] systemd[1]: Enabling (yes) showing of status (commandline).
544 12:28:13.295098 <31>[ 6.384675] systemd[1]: Successfully forked off '(sd-executor)' as PID 98.
545 12:28:13.312086 <31>[ 6.401951] systemd[98]: Successfully forked off '(direxec)' as PID 99.
546 12:28:13.314916 <31>[ 6.404831] systemd[98]: Successfully forked off '(direxec)' as PID 100.
547 12:28:13.325710 <31>[ 6.415666] systemd[98]: Successfully forked off '(direxec)' as PID 101.
548 12:28:13.327972 <31>[ 6.417771] systemd[98]: Successfully forked off '(direxec)' as PID 102.
549 12:28:13.346394 <31>[ 6.436286] systemd[98]: Successfully forked off '(direxec)' as PID 103.
550 12:28:13.517071 <31>[ 6.606925] systemd-getty-generator[101]: Automatically adding serial getty for /dev/ttyAMA0.
551 12:28:13.518579 <31>[ 6.608373] systemd-getty-generator[101]: SELinux enabled state cached to: disabled
552 12:28:13.522580 <31>[ 6.612345] systemd-bless-boot-generator[99]: Skipping generator, not an EFI boot.
553 12:28:13.525944 <31>[ 6.615773] systemd-fstab-generator[100]: Parsing /etc/fstab...
554 12:28:13.527980 <31>[ 6.617726] systemd-fstab-generator[100]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
555 12:28:13.543085 <31>[ 6.632691] systemd-fstab-generator[100]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
556 12:28:13.548342 <31>[ 6.638107] systemd-fstab-generator[100]: SELinux enabled state cached to: disabled
557 12:28:13.555083 <31>[ 6.644898] systemd[98]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
558 12:28:13.555511 <31>[ 6.645420] systemd[98]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
559 12:28:13.556005 <31>[ 6.645773] systemd[98]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
560 12:28:13.556251 <31>[ 6.646208] systemd[98]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
561 12:28:13.557218 <31>[ 6.646960] systemd[98]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
562 12:28:13.560102 <31>[ 6.649920] systemd[1]: (sd-executor) succeeded.
563 12:28:13.561785 <31>[ 6.651618] systemd[1]: Looking for unit files in (higher priority first):
564 12:28:13.562001 <31>[ 6.651879] systemd[1]: /etc/systemd/system.control
565 12:28:13.562192 <31>[ 6.652083] systemd[1]: /run/systemd/system.control
566 12:28:13.562382 <31>[ 6.652267] systemd[1]: /run/systemd/transient
567 12:28:13.562567 <31>[ 6.652452] systemd[1]: /run/systemd/generator.early
568 12:28:13.562750 <31>[ 6.652656] systemd[1]: /etc/systemd/system
569 12:28:13.562925 <31>[ 6.652830] systemd[1]: /etc/systemd/system.attached
570 12:28:13.563102 <31>[ 6.653050] systemd[1]: /run/systemd/system
571 12:28:13.563269 <31>[ 6.653232] systemd[1]: /run/systemd/system.attached
572 12:28:13.563449 <31>[ 6.653402] systemd[1]: /run/systemd/generator
573 12:28:13.563624 <31>[ 6.653571] systemd[1]: /usr/local/lib/systemd/system
574 12:28:13.563795 <31>[ 6.653754] systemd[1]: /lib/systemd/system
575 12:28:13.563968 <31>[ 6.653936] systemd[1]: /usr/lib/systemd/system
576 12:28:13.564113 <31>[ 6.654090] systemd[1]: /run/systemd/generator.late
577 12:28:13.602186 <31>[ 6.692032] systemd[1]: Modification times have changed, need to update cache.
578 12:28:13.603975 <31>[ 6.693744] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
579 12:28:13.605592 <31>[ 6.695366] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
580 12:28:13.606412 <31>[ 6.696134] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
581 12:28:13.607348 <31>[ 6.697106] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
582 12:28:13.608195 <31>[ 6.697933] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
583 12:28:13.608429 <31>[ 6.698284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
584 12:28:13.609259 <31>[ 6.699034] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
585 12:28:13.609490 <31>[ 6.699424] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
586 12:28:13.609752 <31>[ 6.699676] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
587 12:28:13.610347 <31>[ 6.699977] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
588 12:28:13.610564 <31>[ 6.700412] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
589 12:28:13.611435 <31>[ 6.701177] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
590 12:28:13.611654 <31>[ 6.701547] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
591 12:28:13.612154 <31>[ 6.701923] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
592 12:28:13.613200 <31>[ 6.702993] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
593 12:28:13.613768 <31>[ 6.703428] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
594 12:28:13.613976 <31>[ 6.703743] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
595 12:28:13.614501 <31>[ 6.704140] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
596 12:28:13.614680 <31>[ 6.704510] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
597 12:28:13.615491 <31>[ 6.705137] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
598 12:28:13.615674 <31>[ 6.705465] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
599 12:28:13.616166 <31>[ 6.706084] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
600 12:28:13.616656 <31>[ 6.706391] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
601 12:28:13.617191 <31>[ 6.706978] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
602 12:28:13.617573 <31>[ 6.707328] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
603 12:28:13.618043 <31>[ 6.707742] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
604 12:28:13.618238 <31>[ 6.708073] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
605 12:28:13.619023 <31>[ 6.708745] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
606 12:28:13.619694 <31>[ 6.709488] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
607 12:28:13.619914 <31>[ 6.709886] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
608 12:28:13.620441 <31>[ 6.710141] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
609 12:28:13.621213 <31>[ 6.710887] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
610 12:28:13.621466 <31>[ 6.711289] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
611 12:28:13.621733 <31>[ 6.711627] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
612 12:28:13.622219 <31>[ 6.712008] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
613 12:28:13.622433 <31>[ 6.712303] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
614 12:28:13.622707 <31>[ 6.712613] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
615 12:28:13.623093 <31>[ 6.712946] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
616 12:28:13.623685 <31>[ 6.713256] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
617 12:28:13.623865 <31>[ 6.713597] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
618 12:28:13.624088 <31>[ 6.713893] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
619 12:28:13.624302 <31>[ 6.714180] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
620 12:28:13.624528 <31>[ 6.714428] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
621 12:28:13.625487 <31>[ 6.715126] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
622 12:28:13.625667 <31>[ 6.715397] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
623 12:28:13.626360 <31>[ 6.716047] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
624 12:28:13.626570 <31>[ 6.716380] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
625 12:28:13.627403 <31>[ 6.717055] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
626 12:28:13.627637 <31>[ 6.717441] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
627 12:28:13.628243 <31>[ 6.717942] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
628 12:28:13.628482 <31>[ 6.718264] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
629 12:28:13.629634 <31>[ 6.719274] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
630 12:28:13.630867 <31>[ 6.720456] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
631 12:28:13.630993 <31>[ 6.720888] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
632 12:28:13.631366 <31>[ 6.721206] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
633 12:28:13.631736 <31>[ 6.721493] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
634 12:28:13.632333 <31>[ 6.722138] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
635 12:28:13.632943 <31>[ 6.722791] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
636 12:28:13.633358 <31>[ 6.723179] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
637 12:28:13.634099 <31>[ 6.723860] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
638 12:28:13.634500 <31>[ 6.724206] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
639 12:28:13.634860 <31>[ 6.724505] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
640 12:28:13.634961 <31>[ 6.724832] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
641 12:28:13.635279 <31>[ 6.725182] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
642 12:28:13.635686 <31>[ 6.725553] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
643 12:28:13.636043 <31>[ 6.725856] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
644 12:28:13.636407 <31>[ 6.726194] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
645 12:28:13.637071 <31>[ 6.726802] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
646 12:28:13.637456 <31>[ 6.727151] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
647 12:28:13.637844 <31>[ 6.727454] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
648 12:28:13.637962 <31>[ 6.727822] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
649 12:28:13.638312 <31>[ 6.728163] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
650 12:28:13.638650 <31>[ 6.728557] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
651 12:28:13.638986 <31>[ 6.728909] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
652 12:28:13.639606 <31>[ 6.729507] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
653 12:28:13.639947 <31>[ 6.729852] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
654 12:28:13.640546 <31>[ 6.730162] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
655 12:28:13.642334 <31>[ 6.731755] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
656 12:28:13.643055 <31>[ 6.732533] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
657 12:28:13.643444 <31>[ 6.733097] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
658 12:28:13.644091 <31>[ 6.733675] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
659 12:28:13.644809 <31>[ 6.734405] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
660 12:28:13.645887 <31>[ 6.735640] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
661 12:28:13.646541 <31>[ 6.736133] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
662 12:28:13.646743 <31>[ 6.736505] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
663 12:28:13.647252 <31>[ 6.736899] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
664 12:28:13.647428 <31>[ 6.737273] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
665 12:28:13.647947 <31>[ 6.737637] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
666 12:28:13.648140 <31>[ 6.737991] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
667 12:28:13.648626 <31>[ 6.738341] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
668 12:28:13.649173 <31>[ 6.739030] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
669 12:28:13.649664 <31>[ 6.739446] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
670 12:28:13.650147 <31>[ 6.739851] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
671 12:28:13.650269 <31>[ 6.740188] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
672 12:28:13.650814 <31>[ 6.740556] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
673 12:28:13.651175 <31>[ 6.740915] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
674 12:28:13.651687 <31>[ 6.741262] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
675 12:28:13.652193 <31>[ 6.741849] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
676 12:28:13.652578 <31>[ 6.742278] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
677 12:28:13.653340 <31>[ 6.743072] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
678 12:28:13.654637 <31>[ 6.744205] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
679 12:28:13.654762 <31>[ 6.744682] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
680 12:28:13.655389 <31>[ 6.745022] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
681 12:28:13.655512 <31>[ 6.745422] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
682 12:28:13.655820 <31>[ 6.745707] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
683 12:28:13.656190 <31>[ 6.746042] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
684 12:28:13.656518 <31>[ 6.746331] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
685 12:28:13.657151 <31>[ 6.747025] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
686 12:28:13.657544 <31>[ 6.747398] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
687 12:28:13.657925 <31>[ 6.747763] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
688 12:28:13.658318 <31>[ 6.748157] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
689 12:28:13.658661 <31>[ 6.748555] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
690 12:28:13.659040 <31>[ 6.748873] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
691 12:28:13.659380 <31>[ 6.749177] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
692 12:28:13.659741 <31>[ 6.749512] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
693 12:28:13.659882 <31>[ 6.749797] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
694 12:28:13.660288 <31>[ 6.750083] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
695 12:28:13.660660 <31>[ 6.750379] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
696 12:28:13.661254 <31>[ 6.751117] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
697 12:28:13.661678 <31>[ 6.751439] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
698 12:28:13.661802 <31>[ 6.751707] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
699 12:28:13.662382 <31>[ 6.752092] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
700 12:28:13.662488 <31>[ 6.752429] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
701 12:28:13.662803 <31>[ 6.752732] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
702 12:28:13.663116 <31>[ 6.753060] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
703 12:28:13.663654 <31>[ 6.753377] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
704 12:28:13.663754 <31>[ 6.753699] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
705 12:28:13.664063 <31>[ 6.753956] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
706 12:28:13.664387 <31>[ 6.754276] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
707 12:28:13.664979 <31>[ 6.754762] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
708 12:28:13.665532 <31>[ 6.755353] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
709 12:28:13.665882 <31>[ 6.755682] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
710 12:28:13.666754 <31>[ 6.756447] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
711 12:28:13.666874 <31>[ 6.756784] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
712 12:28:13.667219 <31>[ 6.757060] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
713 12:28:13.667538 <31>[ 6.757376] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
714 12:28:13.667849 <31>[ 6.757649] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
715 12:28:13.668159 <31>[ 6.757921] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
716 12:28:13.668497 <31>[ 6.758237] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
717 12:28:13.669189 <31>[ 6.758599] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
718 12:28:13.669326 <31>[ 6.759346] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
719 12:28:13.669682 <31>[ 6.759609] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
720 12:28:13.670036 <31>[ 6.759889] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
721 12:28:13.670649 <31>[ 6.760459] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
722 12:28:13.671015 <31>[ 6.760878] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
723 12:28:13.671369 <31>[ 6.761189] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
724 12:28:13.671717 <31>[ 6.761532] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
725 12:28:13.672121 <31>[ 6.761879] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
726 12:28:13.672470 <31>[ 6.762217] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
727 12:28:13.673116 <31>[ 6.762938] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
728 12:28:13.673477 <31>[ 6.763274] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
729 12:28:14.098234 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
730 12:28:14.103127 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
731 12:28:14.108022 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
732 12:28:14.112200 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
733 12:28:14.116087 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
734 12:28:14.117851 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
735 12:28:14.120110 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
736 12:28:14.121632 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
737 12:28:14.122304 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
738 12:28:14.123120 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
739 12:28:14.123925 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
740 12:28:14.127643 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
741 12:28:14.132032 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
742 12:28:14.135102 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
743 12:28:14.137666 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
744 12:28:14.140045 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
745 12:28:14.142827 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
746 12:28:14.145082 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
747 12:28:14.174677 Mounting [0;1;39mHuge Pages File System[0m...
748 12:28:14.209857 Mounting [0;1;39mPOSIX Message Queue File System[0m...
749 12:28:14.249760 Mounting [0;1;39mKernel Debug File System[0m...
750 12:28:14.303029 Starting [0;1;39mLoad Kernel Module configfs[0m...
751 12:28:14.350347 Starting [0;1;39mLoad Kernel Module drm[0m...
752 12:28:14.410370 Starting [0;1;39mJournal Service[0m...
753 12:28:14.442545 Starting [0;1;39mLoad Kernel Modules[0m...
754 12:28:14.486337 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
755 12:28:14.542192 Starting [0;1;39mColdplug All udev Devices[0m...
756 12:28:14.648773 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
757 12:28:14.659180 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
758 12:28:14.677034 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
759 12:28:14.730149 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
760 12:28:14.785663 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
761 12:28:14.811840 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
762 12:28:14.897943 Mounting [0;1;39mKernel Configuration File System[0m...
763 12:28:15.022192 Starting [0;1;39mApply Kernel Variables[0m...
764 12:28:15.091743 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
765 12:28:15.160219 <47>[ 8.250060] systemd-journald[109]: SELinux enabled state cached to: disabled
766 12:28:15.178123 <47>[ 8.267946] systemd-journald[109]: Auditing in kernel turned off.
767 12:28:15.194854 <47>[ 8.284656] systemd-journald[109]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
768 12:28:15.241728 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
769 12:28:15.242583 See 'systemctl status systemd-remount-fs.service' for details.
770 12:28:15.263848 <47>[ 8.353428] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
771 12:28:15.275838 <47>[ 8.365355] systemd-journald[109]: Fixed min_use=3.8M max_use=19.3M max_size=2.4M min_size=512.0K keep_free=9.6M n_max_files=100
772 12:28:15.285983 <47>[ 8.375912] systemd-journald[109]: Reserving 333 entries in field hash table.
773 12:28:15.290882 Starting [0;1;39mLoad/Save Random Seed[0m...
774 12:28:15.323361 <47>[ 8.413262] systemd-journald[109]: Reserving 4408 entries in data hash table.
775 12:28:15.340155 <47>[ 8.430054] systemd-journald[109]: Vacuuming...
776 12:28:15.344151 <47>[ 8.433734] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
777 12:28:15.344771 <47>[ 8.434803] systemd-journald[109]: Flushing /dev/kmsg...
778 12:28:15.358301 Starting [0;1;39mCreate System Users[0m...
779 12:28:15.397517 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
780 12:28:15.521830 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
781 12:28:15.713983 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
782 12:28:15.758489 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
783 12:28:15.952619 <47>[ 9.042270] systemd-journald[109]: systemd-journald running as PID 109 for the system.
784 12:28:15.975640 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
785 12:28:15.980917 <47>[ 9.070875] systemd-journald[109]: Sent READY=1 notification.
786 12:28:15.981380 <47>[ 9.071306] systemd-journald[109]: Sent WATCHDOG=1 notification.
787 12:28:16.016067 <47>[ 9.105932] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
788 12:28:16.030947 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
789 12:28:16.039550 <47>[ 9.129188] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
790 12:28:16.055033 <47>[ 9.144682] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
791 12:28:16.077547 <47>[ 9.162431] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
792 12:28:16.080221 <47>[ 9.170038] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
793 12:28:16.082255 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
794 12:28:16.099838 <47>[ 9.189754] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
795 12:28:16.109861 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
796 12:28:16.114007 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
797 12:28:16.118738 <47>[ 9.208510] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
798 12:28:16.151007 <47>[ 9.240845] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
799 12:28:16.167842 <47>[ 9.257478] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
800 12:28:16.179042 <47>[ 9.268759] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
801 12:28:16.189813 <47>[ 9.279466] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
802 12:28:16.192005 <47>[ 9.281821] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
803 12:28:16.208111 <47>[ 9.297808] systemd-journald[109]: n/a: New incoming connection.
804 12:28:16.208621 <47>[ 9.298404] systemd-journald[109]: varlink-21: varlink: setting state idle-server
805 12:28:16.218725 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
806 12:28:16.222509 <47>[ 9.312183] systemd-journald[109]: varlink-21: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
807 12:28:16.224321 <47>[ 9.314114] systemd-journald[109]: varlink-21: varlink: changing state idle-server → processing-method
808 12:28:16.237304 <46>[ 9.327146] systemd-journald[109]: Received client request to flush runtime journal.
809 12:28:16.238025 <47>[ 9.327794] systemd-journald[109]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
810 12:28:16.238883 <47>[ 9.328719] systemd-journald[109]: Vacuuming...
811 12:28:16.239646 <47>[ 9.329316] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
812 12:28:16.253512 <47>[ 9.343422] systemd-journald[109]: varlink-21: Sending message: {\"parameters\":{}}
813 12:28:16.254241 <47>[ 9.343768] systemd-journald[109]: varlink-21: varlink: changing state processing-method → processed-method
814 12:28:16.254506 <47>[ 9.344322] systemd-journald[109]: varlink-21: varlink: changing state processed-method → idle-server
815 12:28:16.271923 <47>[ 9.361535] systemd-journald[109]: varlink-21: varlink: changing state idle-server → pending-disconnect
816 12:28:16.272177 <47>[ 9.361999] systemd-journald[109]: varlink-21: varlink: changing state pending-disconnect → processing-disconnect
817 12:28:16.272546 <47>[ 9.362349] systemd-journald[109]: varlink-21: varlink: changing state processing-disconnect → disconnected
818 12:28:16.283279 <47>[ 9.372895] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
819 12:28:16.287590 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
820 12:28:16.304509 <47>[ 9.393961] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
821 12:28:16.318640 <47>[ 9.408450] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
822 12:28:16.354529 Starting [0;1;39mCreate Volatile Files and Directories[0m...
823 12:28:16.359417 <47>[ 9.449322] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
824 12:28:16.840049 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
825 12:28:16.939096 Starting [0;1;39mNetwork Service[0m...
826 12:28:16.971063 <47>[ 10.060639] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
827 12:28:16.973669 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
828 12:28:17.078550 Starting [0;1;39mNetwork Time Synchronization[0m...
829 12:28:17.087307 <47>[ 10.176958] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
830 12:28:17.167232 <47>[ 10.257095] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
831 12:28:17.174539 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
832 12:28:17.698419 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
833 12:28:18.869055 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
834 12:28:18.891139 <47>[ 11.980462] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3308 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
835 12:28:18.891673 <47>[ 11.981329] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
836 12:28:18.892013 <47>[ 11.981914] systemd-journald[109]: Rotating...
837 12:28:18.913921 <47>[ 12.003257] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
838 12:28:18.917791 <47>[ 12.005469] systemd-journald[109]: Reserving 333 entries in field hash table.
839 12:28:18.975075 <47>[ 12.064812] systemd-journald[109]: Reserving 4408 entries in data hash table.
840 12:28:18.995370 <47>[ 12.085175] systemd-journald[109]: Vacuuming...
841 12:28:19.037026 Starting [0;1;39mNetwork Name Resolution[0m...
842 12:28:19.042883 <47>[ 12.132494] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
843 12:28:19.108312 <47>[ 12.195340] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
844 12:28:19.529911 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
845 12:28:19.532519 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
846 12:28:19.542196 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
847 12:28:20.048621 <47>[ 13.137342] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
848 12:28:21.599911 [[0m[0;31m* [0m] (1 of 3) A start job is running for…g All udev Devices (7s / no limit)
849 12:28:21.633432 M[K[[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
850 12:28:21.646258 [K[[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
851 12:28:21.672619 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
852 12:28:21.693383 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
853 12:28:21.704693 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
854 12:28:21.713471 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
855 12:28:21.745825 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
856 12:28:21.746678 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
857 12:28:21.747486 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
858 12:28:21.827041 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
859 12:28:21.847919 <47>[ 14.937409] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
860 12:28:21.987939 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...<47>[ 15.077658] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
861 12:28:21.988434
862 12:28:22.238696 Starting [0;1;39mUser Login Management[0m...
863 12:28:22.247378 <47>[ 15.337230] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
864 12:28:22.263601 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
865 12:28:22.302819 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
866 12:28:22.310102 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
867 12:28:22.402694 Starting [0;1;39mPermit User Sessions[0m...
868 12:28:22.437598 <47>[ 15.527242] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
869 12:28:22.765984 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
870 12:28:22.847533 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
871 12:28:23.086388 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
872 12:28:23.612830 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
873 12:28:25.891689 [[0;1;31m*[0m[0;31m* [0m] A start job is running for /dev/ttyAMA0 (11s / 1min 30s)
874 12:28:26.480372 M[K[[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
875 12:28:26.555409 [K[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
876 12:28:26.578798 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
877 12:28:26.596160 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
878 12:28:26.612372 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
879 12:28:26.667493 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
880 12:28:26.680381 <47>[ 19.770009] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
881 12:28:26.903694 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
882 12:28:26.946030 <47>[ 20.035574] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
883 12:28:26.951376 <47>[ 20.041286] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
884 12:28:26.971859 <6>[ 20.061674] virtio_net virtio0 enp0s1: renamed from eth0
885 12:28:27.050530
886 12:28:27.050838 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
887 12:28:27.051032
888 12:28:27.051491 debian-bullseye-arm64 login: root (automatic login)
889 12:28:27.051639
890 12:28:27.307754 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
891 12:28:27.308523
892 12:28:27.309100 The programs included with the Debian GNU/Linux system are free software;
893 12:28:27.309267 the exact distribution terms for each program are described in the
894 12:28:27.309395 individual files in /usr/share/doc/*/copyright.
895 12:28:27.309517
896 12:28:27.309634 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
897 12:28:27.309762 permitted by applicable law.
898 12:28:27.956329 <47>[ 21.046165] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
899 12:28:28.124716 <47>[ 21.214159] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
900 12:28:28.145379 <47>[ 21.234825] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
901 12:28:28.145778 <47>[ 21.235360] systemd-journald[109]: Rotating...
902 12:28:28.147697 <47>[ 21.237346] systemd-journald[109]: Reserving 333 entries in field hash table.
903 12:28:28.185777 <47>[ 21.275623] systemd-journald[109]: Reserving 4408 entries in data hash table.
904 12:28:28.200444 <47>[ 21.290339] systemd-journald[109]: Vacuuming...
905 12:28:28.201967 <47>[ 21.291720] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
906 12:28:28.291388 <47>[ 21.381269] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
907 12:28:30.064730 <47>[ 23.154221] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
908 12:28:30.605724 Matched prompt #10: / #
910 12:28:30.606316 Setting prompt string to ['/ #']
911 12:28:30.606500 end: 2.2.1 login-action (duration 00:00:24) [common]
913 12:28:30.606917 end: 2.2 auto-login-action (duration 00:00:28) [common]
914 12:28:30.607094 start: 2.3 expect-shell-connection (timeout 00:04:31) [common]
915 12:28:30.607235 Setting prompt string to ['/ #']
916 12:28:30.607361 Forcing a shell prompt, looking for ['/ #']
918 12:28:30.657925 / #
919 12:28:30.658252 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
920 12:28:30.658438 Waiting using forced prompt support (timeout 00:02:30)
921 12:28:30.660485
922 12:28:30.669039 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
923 12:28:30.669330 start: 2.4 export-device-env (timeout 00:04:31) [common]
924 12:28:30.669516 end: 2.4 export-device-env (duration 00:00:00) [common]
925 12:28:30.669697 end: 2 boot-image-retry (duration 00:00:29) [common]
926 12:28:30.669860 start: 3 lava-test-retry (timeout 00:08:46) [common]
927 12:28:30.670019 start: 3.1 lava-test-shell (timeout 00:08:46) [common]
928 12:28:30.670159 Using namespace: common
930 12:28:30.771062 / # #
931 12:28:30.771390 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
932 12:28:30.771909 #
934 12:28:30.880226 / # mkdir /lava-568971
935 12:28:30.881011 mkdir /lava-568971
937 12:28:31.008691 / # mount /dev/disk/by-uuid/3f163c6f-7536-4eba-a6dc-f7fd550ae72d -t ext2 /lava-568971
938 12:28:31.009721 mount /dev/disk/by-uuid/3f163c6f-7536-4eba-a6dc-f7fd550ae72d -t ext2 /lava-568971
939 12:28:31.050338 <4>[ 24.139853] ext2 filesystem being mounted at /lava-568971 supports timestamps until 2038 (0x7fffffff)
941 12:28:31.194307 / # ls -la /lava-568971/bin/lava-test-runner
942 12:28:31.195436 ls -la /lava-568971/bin/lava-test-runner
943 12:28:31.238784 -rwxr-xr-x 1 root root 1039 Jun 6 12:27 /lava-568971/bin/lava-test-runner
944 12:28:31.251016 Using /lava-568971
946 12:28:31.352049 / # export SHELL=/bin/sh
947 12:28:31.353163 export SHELL=/bin/sh
949 12:28:31.462265 / # . /lava-568971/environment
950 12:28:31.463245 . /lava-568971/environment
952 12:28:31.574822 / # /lava-568971/bin/lava-test-runner /lava-568971/0
953 12:28:31.575125 Test shell timeout: 10s (minimum of the action and connection timeout)
954 12:28:31.575951 /lava-568971/bin/lava-test-runner /lava-568971/0
955 12:28:31.748712 + export TESTRUN_ID=0_timesync-off
956 12:28:31.748975 + cd /lava-568971/0/tests/0_timesync-off
957 12:28:31.750747 + cat uuid
958 12:28:31.759771 + UUID=568971_1.1.3.1
959 12:28:31.759903 + set +x
960 12:28:31.760200 <LAVA_SIGNAL_STARTRUN 0_timesync-off 568971_1.1.3.1>
961 12:28:31.760512 Received signal: <STARTRUN> 0_timesync-off 568971_1.1.3.1
962 12:28:31.760626 Starting test lava.0_timesync-off (568971_1.1.3.1)
963 12:28:31.760739 Skipping test definition patterns.
964 12:28:31.760880 + systemctl stop systemd-timesyncd
965 12:28:32.035935 + set +x
966 12:28:32.036234 <LAVA_SIGNAL_ENDRUN 0_timesync-off 568971_1.1.3.1>
967 12:28:32.036558 Received signal: <ENDRUN> 0_timesync-off 568971_1.1.3.1
968 12:28:32.036769 Ending use of test pattern.
969 12:28:32.036911 Ending test lava.0_timesync-off (568971_1.1.3.1), duration 0.28
971 12:28:32.083619 + export TESTRUN_ID=1_kselftest-arm64_qemu
972 12:28:32.083879 + cd /lava-568971/0/tests/1_kselftest-arm64_qemu
973 12:28:32.086154 + cat uuid
974 12:28:32.094708 + UUID=568971_1.1.3.5
975 12:28:32.094950 + set +x
976 12:28:32.095258 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 568971_1.1.3.5>
977 12:28:32.095565 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 568971_1.1.3.5
978 12:28:32.095667 Starting test lava.1_kselftest-arm64_qemu (568971_1.1.3.5)
979 12:28:32.095787 Skipping test definition patterns.
980 12:28:32.095938 + cd ./automated/linux/kselftest/
981 12:28:32.100957 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
982 12:28:32.204785 INFO: install_deps skipped
983 12:28:32.239529 --2023-06-06 12:28:31-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
984 12:28:32.270373 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
985 12:28:32.469770 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
986 12:28:32.663852 HTTP request sent, awaiting response... 200 OK
987 12:28:32.666826 Length: 2699740 (2.6M) [application/octet-stream]
988 12:28:32.668532 Saving to: 'kselftest.tar.xz'
989 12:28:32.670209
990 12:28:34.074795 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 142KB/s kselftest.tar.xz 6%[> ] 170.35K 235KB/s kselftest.tar.xz 21%[===> ] 566.38K 613KB/s kselftest.tar.xz 41%[=======> ] 1.07M 974KB/s kselftest.tar.xz 54%[=========> ] 1.41M 1.06MB/s kselftest.tar.xz 100%[===================>] 2.57M 1.77MB/s in 1.5s
991 12:28:34.075087
992 12:28:34.081169 2023-06-06 12:28:33 (1.77 MB/s) - 'kselftest.tar.xz' saved [2699740/2699740]
993 12:28:34.081455
994 12:28:37.288029 skiplist:
995 12:28:37.288287 ========================================
996 12:28:37.289010 ========================================
997 12:28:37.344407 arm64:tags_test
998 12:28:37.344656 arm64:run_tags_test.sh
999 12:28:37.344742 arm64:fake_sigreturn_bad_magic
1000 12:28:37.345028 arm64:fake_sigreturn_bad_size
1001 12:28:37.345127 arm64:fake_sigreturn_bad_size_for_magic0
1002 12:28:37.345212 arm64:fake_sigreturn_duplicated_fpsimd
1003 12:28:37.345305 arm64:fake_sigreturn_misaligned_sp
1004 12:28:37.345387 arm64:fake_sigreturn_missing_fpsimd
1005 12:28:37.345466 arm64:fake_sigreturn_sme_change_vl
1006 12:28:37.345545 arm64:fake_sigreturn_sve_change_vl
1007 12:28:37.345644 arm64:mangle_pstate_invalid_compat_toggle
1008 12:28:37.345734 arm64:mangle_pstate_invalid_daif_bits
1009 12:28:37.345814 arm64:mangle_pstate_invalid_mode_el1h
1010 12:28:37.345906 arm64:mangle_pstate_invalid_mode_el1t
1011 12:28:37.345986 arm64:mangle_pstate_invalid_mode_el2h
1012 12:28:37.346082 arm64:mangle_pstate_invalid_mode_el2t
1013 12:28:37.346170 arm64:mangle_pstate_invalid_mode_el3h
1014 12:28:37.346249 arm64:mangle_pstate_invalid_mode_el3t
1015 12:28:37.346349 arm64:sme_trap_no_sm
1016 12:28:37.346438 arm64:sme_trap_non_streaming
1017 12:28:37.346528 arm64:sme_trap_za
1018 12:28:37.346615 arm64:sme_vl
1019 12:28:37.346718 arm64:ssve_regs
1020 12:28:37.346806 arm64:sve_regs
1021 12:28:37.346891 arm64:sve_vl
1022 12:28:37.346976 arm64:za_no_regs
1023 12:28:37.347061 arm64:za_regs
1024 12:28:37.347147 arm64:pac
1025 12:28:37.347239 arm64:fp-stress
1026 12:28:37.347345 arm64:sve-ptrace
1027 12:28:37.347433 arm64:sve-probe-vls
1028 12:28:37.347522 arm64:vec-syscfg
1029 12:28:37.347606 arm64:za-fork
1030 12:28:37.347690 arm64:za-ptrace
1031 12:28:37.347775 arm64:check_buffer_fill
1032 12:28:37.347858 arm64:check_child_memory
1033 12:28:37.347942 arm64:check_gcr_el1_cswitch
1034 12:28:37.348026 arm64:check_ksm_options
1035 12:28:37.348110 arm64:check_mmap_options
1036 12:28:37.348194 arm64:check_prctl
1037 12:28:37.348277 arm64:check_tags_inclusion
1038 12:28:37.348361 arm64:check_user_mem
1039 12:28:37.348457 arm64:btitest
1040 12:28:37.348537 arm64:nobtitest
1041 12:28:37.348610 arm64:hwcap
1042 12:28:37.348681 arm64:ptrace
1043 12:28:37.348751 arm64:syscall-abi
1044 12:28:37.348821 arm64:tpidr2
1045 12:28:37.361580 ============== Tests to run ===============
1046 12:28:37.367017 arm64:tags_test
1047 12:28:37.367261 arm64:run_tags_test.sh
1048 12:28:37.367361 arm64:fake_sigreturn_bad_magic
1049 12:28:37.367653 arm64:fake_sigreturn_bad_size
1050 12:28:37.367758 arm64:fake_sigreturn_bad_size_for_magic0
1051 12:28:37.367848 arm64:fake_sigreturn_duplicated_fpsimd
1052 12:28:37.367939 arm64:fake_sigreturn_misaligned_sp
1053 12:28:37.368024 arm64:fake_sigreturn_missing_fpsimd
1054 12:28:37.368111 arm64:fake_sigreturn_sme_change_vl
1055 12:28:37.368196 arm64:fake_sigreturn_sve_change_vl
1056 12:28:37.368299 arm64:mangle_pstate_invalid_compat_toggle
1057 12:28:37.368387 arm64:mangle_pstate_invalid_daif_bits
1058 12:28:37.368474 arm64:mangle_pstate_invalid_mode_el1h
1059 12:28:37.368560 arm64:mangle_pstate_invalid_mode_el1t
1060 12:28:37.368646 arm64:mangle_pstate_invalid_mode_el2h
1061 12:28:37.368732 arm64:mangle_pstate_invalid_mode_el2t
1062 12:28:37.368838 arm64:mangle_pstate_invalid_mode_el3h
1063 12:28:37.368927 arm64:mangle_pstate_invalid_mode_el3t
1064 12:28:37.369014 arm64:sme_trap_no_sm
1065 12:28:37.369100 arm64:sme_trap_non_streaming
1066 12:28:37.369187 arm64:sme_trap_za
1067 12:28:37.369273 arm64:sme_vl
1068 12:28:37.369359 arm64:ssve_regs
1069 12:28:37.369444 arm64:sve_regs
1070 12:28:37.369550 arm64:sve_vl
1071 12:28:37.369642 arm64:za_no_regs
1072 12:28:37.369737 arm64:za_regs
1073 12:28:37.369824 arm64:pac
1074 12:28:37.369909 arm64:fp-stress
1075 12:28:37.369995 arm64:sve-ptrace
1076 12:28:37.370080 arm64:sve-probe-vls
1077 12:28:37.370167 arm64:vec-syscfg
1078 12:28:37.370253 arm64:za-fork
1079 12:28:37.370337 arm64:za-ptrace
1080 12:28:37.370419 arm64:check_buffer_fill
1081 12:28:37.370520 arm64:check_child_memory
1082 12:28:37.370612 arm64:check_gcr_el1_cswitch
1083 12:28:37.370696 arm64:check_ksm_options
1084 12:28:37.370779 arm64:check_mmap_options
1085 12:28:37.370866 arm64:check_prctl
1086 12:28:37.370950 arm64:check_tags_inclusion
1087 12:28:37.371033 arm64:check_user_mem
1088 12:28:37.371111 arm64:btitest
1089 12:28:37.371189 arm64:nobtitest
1090 12:28:37.371268 arm64:hwcap
1091 12:28:37.371347 arm64:ptrace
1092 12:28:37.371428 arm64:syscall-abi
1093 12:28:37.371511 arm64:tpidr2
1094 12:28:37.373189 ===========End Tests to run ===============
1095 12:28:38.462754 <12>[ 31.552666] kselftest: Running tests in arm64
1096 12:28:38.496244 TAP version 13
1097 12:28:38.517166 1..48
1098 12:28:38.574108 # selftests: arm64: tags_test
1099 12:28:38.635480 ok 1 selftests: arm64: tags_test
1100 12:28:38.690620 # selftests: arm64: run_tags_test.sh
1101 12:28:38.751268 # --------------------
1102 12:28:38.751520 # running tags test
1103 12:28:38.751614 # --------------------
1104 12:28:38.751704 # [PASS]
1105 12:28:38.758795 ok 2 selftests: arm64: run_tags_test.sh
1106 12:28:38.814111 # selftests: arm64: fake_sigreturn_bad_magic
1107 12:28:38.872895 # Registered handlers for all signals.
1108 12:28:38.873124 # Detected MINSTKSIGSZ:10000
1109 12:28:38.873219 # Testcase initialized.
1110 12:28:38.873360 # uc context validated.
1111 12:28:38.873442 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1112 12:28:38.873515 # Handled SIG_COPYCTX
1113 12:28:38.873584 # Available space:3536
1114 12:28:38.873681 # Using badly built context - ERR: BAD MAGIC !
1115 12:28:38.873757 # SIG_OK -- SP:0xFFFFE53576C0 si_addr@:0xffffe53576c0 si_code:2 token@:0xffffe5356460 offset:-4704
1116 12:28:38.873829 # ==>> completed. PASS(1)
1117 12:28:38.873913 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1118 12:28:38.873998 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE5356460
1119 12:28:38.884634 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1120 12:28:38.937988 # selftests: arm64: fake_sigreturn_bad_size
1121 12:28:38.998564 # Registered handlers for all signals.
1122 12:28:38.998870 # Detected MINSTKSIGSZ:10000
1123 12:28:38.999057 # Testcase initialized.
1124 12:28:38.999210 # uc context validated.
1125 12:28:38.999589 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1126 12:28:38.999733 # Handled SIG_COPYCTX
1127 12:28:38.999881 # Available space:3536
1128 12:28:39.000026 # uc context validated.
1129 12:28:39.000169 # Using badly built context - ERR: Bad size for esr_context
1130 12:28:39.000319 # SIG_OK -- SP:0xFFFFEF90C8C0 si_addr@:0xffffef90c8c0 si_code:2 token@:0xffffef90b660 offset:-4704
1131 12:28:39.000463 # ==>> completed. PASS(1)
1132 12:28:39.000606 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1133 12:28:39.000753 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEF90B660
1134 12:28:39.007109 ok 4 selftests: arm64: fake_sigreturn_bad_size
1135 12:28:39.063743 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1136 12:28:39.129909 # Registered handlers for all signals.
1137 12:28:39.130162 # Detected MINSTKSIGSZ:10000
1138 12:28:39.130449 # Testcase initialized.
1139 12:28:39.130555 # uc context validated.
1140 12:28:39.130644 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1141 12:28:39.130731 # Handled SIG_COPYCTX
1142 12:28:39.130815 # Available space:3536
1143 12:28:39.130924 # Using badly built context - ERR: Bad size for terminator
1144 12:28:39.131012 # SIG_OK -- SP:0xFFFFF50B1380 si_addr@:0xfffff50b1380 si_code:2 token@:0xfffff50b0120 offset:-4704
1145 12:28:39.131098 # ==>> completed. PASS(1)
1146 12:28:39.131199 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1147 12:28:39.131287 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF50B0120
1148 12:28:39.141201 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1149 12:28:39.195482 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1150 12:28:39.250497 # Registered handlers for all signals.
1151 12:28:39.250752 # Detected MINSTKSIGSZ:10000
1152 12:28:39.251060 # Testcase initialized.
1153 12:28:39.251168 # uc context validated.
1154 12:28:39.251258 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1155 12:28:39.251344 # Handled SIG_COPYCTX
1156 12:28:39.251431 # Available space:3536
1157 12:28:39.251533 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1158 12:28:39.251622 # SIG_OK -- SP:0xFFFFDC7EF230 si_addr@:0xffffdc7ef230 si_code:2 token@:0xffffdc7edfd0 offset:-4704
1159 12:28:39.251709 # ==>> completed. PASS(1)
1160 12:28:39.251811 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1161 12:28:39.251901 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDC7EDFD0
1162 12:28:39.260482 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1163 12:28:39.311289 # selftests: arm64: fake_sigreturn_misaligned_sp
1164 12:28:39.370510 # Registered handlers for all signals.
1165 12:28:39.370839 # Detected MINSTKSIGSZ:10000
1166 12:28:39.371025 # Testcase initialized.
1167 12:28:39.371167 # uc context validated.
1168 12:28:39.371289 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1169 12:28:39.371440 # Handled SIG_COPYCTX
1170 12:28:39.371564 # SIG_OK -- SP:0xFFFFF64A8DD3 si_addr@:0xfffff64a8dd3 si_code:2 token@:0xfffff64a8dd3 offset:0
1171 12:28:39.371689 # ==>> completed. PASS(1)
1172 12:28:39.371808 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1173 12:28:39.371927 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF64A8DD3
1174 12:28:39.379605 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1175 12:28:39.429626 # selftests: arm64: fake_sigreturn_missing_fpsimd
1176 12:28:39.485068 # Registered handlers for all signals.
1177 12:28:39.485393 # Detected MINSTKSIGSZ:10000
1178 12:28:39.485563 # Testcase initialized.
1179 12:28:39.485958 # uc context validated.
1180 12:28:39.486068 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1181 12:28:39.486161 # Handled SIG_COPYCTX
1182 12:28:39.486249 # Mangling template header. Spare space:4096
1183 12:28:39.486336 # Using badly built context - ERR: Missing FPSIMD
1184 12:28:39.486423 # SIG_OK -- SP:0xFFFFC314A250 si_addr@:0xffffc314a250 si_code:2 token@:0xffffc3148ff0 offset:-4704
1185 12:28:39.486512 # ==>> completed. PASS(1)
1186 12:28:39.486599 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1187 12:28:39.486705 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC3148FF0
1188 12:28:39.494999 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1189 12:28:39.547263 # selftests: arm64: fake_sigreturn_sme_change_vl
1190 12:28:39.606738 # Registered handlers for all signals.
1191 12:28:39.607206 # Detected MINSTKSIGSZ:10000
1192 12:28:39.607307 # Required Features: [ SME ] supported
1193 12:28:39.607396 # Incompatible Features: [] absent
1194 12:28:39.607484 # Testcase initialized.
1195 12:28:39.607570 # uc context validated.
1196 12:28:39.607655 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1197 12:28:39.607743 # Handled SIG_COPYCTX
1198 12:28:39.607833 # Attempting to change VL from 16 to 256
1199 12:28:39.607938 # SIG_OK -- SP:0xFFFFF05D4940 si_addr@:0xfffff05d4940 si_code:2 token@:0xfffff05d36e0 offset:-4704
1200 12:28:39.608029 # ==>> completed. PASS(1)
1201 12:28:39.608124 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1202 12:28:39.608212 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF05D36E0
1203 12:28:39.618151 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1204 12:28:39.667844 # selftests: arm64: fake_sigreturn_sve_change_vl
1205 12:28:39.724580 # Registered handlers for all signals.
1206 12:28:39.725042 # Detected MINSTKSIGSZ:10000
1207 12:28:39.725144 # Required Features: [ SVE ] supported
1208 12:28:39.725227 # Incompatible Features: [] absent
1209 12:28:39.725317 # Testcase initialized.
1210 12:28:39.725399 # uc context validated.
1211 12:28:39.725481 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1212 12:28:39.725561 # Handled SIG_COPYCTX
1213 12:28:39.725644 # Attempting to change VL from 16 to 256
1214 12:28:39.725757 # SIG_OK -- SP:0xFFFFDD989F50 si_addr@:0xffffdd989f50 si_code:2 token@:0xffffdd988cf0 offset:-4704
1215 12:28:39.725841 # ==>> completed. PASS(1)
1216 12:28:39.725920 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1217 12:28:39.725998 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDD988CF0
1218 12:28:39.734255 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1219 12:28:39.784954 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1220 12:28:39.839288 # Registered handlers for all signals.
1221 12:28:39.839543 # Detected MINSTKSIGSZ:10000
1222 12:28:39.839638 # Testcase initialized.
1223 12:28:39.839944 # uc context validated.
1224 12:28:39.840056 # Handled SIG_TRIG
1225 12:28:39.840147 # SIG_OK -- SP:0xFFFFD2A70980 si_addr@:0xffffd2a70980 si_code:2 token@:(nil) offset:-281474215905664
1226 12:28:39.840242 # ==>> completed. PASS(1)
1227 12:28:39.840327 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1228 12:28:39.848571 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1229 12:28:39.900717 # selftests: arm64: mangle_pstate_invalid_daif_bits
1230 12:28:39.954421 # Registered handlers for all signals.
1231 12:28:39.954672 # Detected MINSTKSIGSZ:10000
1232 12:28:39.954991 # Testcase initialized.
1233 12:28:39.955099 # uc context validated.
1234 12:28:39.955190 # Handled SIG_TRIG
1235 12:28:39.955270 # SIG_OK -- SP:0xFFFFEB4DEFA0 si_addr@:0xffffeb4defa0 si_code:2 token@:(nil) offset:-281474629496736
1236 12:28:39.955352 # ==>> completed. PASS(1)
1237 12:28:39.956849 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1238 12:28:39.963822 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1239 12:28:40.014928 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1240 12:28:40.068187 # Registered handlers for all signals.
1241 12:28:40.068441 # Detected MINSTKSIGSZ:10000
1242 12:28:40.068535 # Testcase initialized.
1243 12:28:40.068847 # uc context validated.
1244 12:28:40.068955 # Handled SIG_TRIG
1245 12:28:40.069047 # SIG_OK -- SP:0xFFFFFD4C6E60 si_addr@:0xfffffd4c6e60 si_code:2 token@:(nil) offset:-281474931388000
1246 12:28:40.069144 # ==>> completed. PASS(1)
1247 12:28:40.069232 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1248 12:28:40.078104 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1249 12:28:40.129287 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1250 12:28:40.183252 # Registered handlers for all signals.
1251 12:28:40.183634 # Detected MINSTKSIGSZ:10000
1252 12:28:40.183847 # Testcase initialized.
1253 12:28:40.184254 # uc context validated.
1254 12:28:40.184418 # Handled SIG_TRIG
1255 12:28:40.184591 # SIG_OK -- SP:0xFFFFD7A11940 si_addr@:0xffffd7a11940 si_code:2 token@:(nil) offset:-281474299402560
1256 12:28:40.184742 # ==>> completed. PASS(1)
1257 12:28:40.185582 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1258 12:28:40.192541 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1259 12:28:40.247674 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1260 12:28:40.304138 # Registered handlers for all signals.
1261 12:28:40.304662 # Detected MINSTKSIGSZ:10000
1262 12:28:40.304816 # Testcase initialized.
1263 12:28:40.304925 # uc context validated.
1264 12:28:40.305024 # Handled SIG_TRIG
1265 12:28:40.305119 # SIG_OK -- SP:0xFFFFEED1AF20 si_addr@:0xffffeed1af20 si_code:2 token@:(nil) offset:-281474688462624
1266 12:28:40.305218 # ==>> completed. PASS(1)
1267 12:28:40.305369 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1268 12:28:40.312048 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1269 12:28:40.363362 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1270 12:28:40.416411 # Registered handlers for all signals.
1271 12:28:40.416769 # Detected MINSTKSIGSZ:10000
1272 12:28:40.417151 # Testcase initialized.
1273 12:28:40.417290 # uc context validated.
1274 12:28:40.417409 # Handled SIG_TRIG
1275 12:28:40.419092 # SIG_OK -- SP:0xFFFFD930B0C0 si_addr@:0xffffd930b0c0 si_code:2 token@:(nil) offset:-281474325590208
1276 12:28:40.419212 # ==>> completed. PASS(1)
1277 12:28:40.419500 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1278 12:28:40.426612 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1279 12:28:40.478987 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1280 12:28:40.533974 # Registered handlers for all signals.
1281 12:28:40.534318 # Detected MINSTKSIGSZ:10000
1282 12:28:40.534763 # Testcase initialized.
1283 12:28:40.534923 # uc context validated.
1284 12:28:40.535052 # Handled SIG_TRIG
1285 12:28:40.535174 # SIG_OK -- SP:0xFFFFD2A74F90 si_addr@:0xffffd2a74f90 si_code:2 token@:(nil) offset:-281474215923600
1286 12:28:40.535293 # ==>> completed. PASS(1)
1287 12:28:40.535428 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1288 12:28:40.544343 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1289 12:28:40.597337 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1290 12:28:40.649969 # Registered handlers for all signals.
1291 12:28:40.650291 # Detected MINSTKSIGSZ:10000
1292 12:28:40.650586 # Testcase initialized.
1293 12:28:40.650682 # uc context validated.
1294 12:28:40.650759 # Handled SIG_TRIG
1295 12:28:40.650838 # SIG_OK -- SP:0xFFFFEB6B1910 si_addr@:0xffffeb6b1910 si_code:2 token@:(nil) offset:-281474631407888
1296 12:28:40.650915 # ==>> completed. PASS(1)
1297 12:28:40.651003 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1298 12:28:40.658317 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1299 12:28:40.711794 # selftests: arm64: sme_trap_no_sm
1300 12:28:40.829951 # Registered handlers for all signals.
1301 12:28:40.830359 # Detected MINSTKSIGSZ:10000
1302 12:28:40.830446 # Required Features: [ SME ] supported
1303 12:28:40.830524 # Incompatible Features: [] absent
1304 12:28:40.830612 # Testcase initialized.
1305 12:28:40.830945 # SIG_OK -- SP:0xFFFFCCA9D600 si_addr@:0xaaaacbca2514 si_code:1 token@:(nil) offset:-187650540184852
1306 12:28:40.831041 # ==>> completed. PASS(1)
1307 12:28:40.831304 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1308 12:28:40.844686 ok 19 selftests: arm64: sme_trap_no_sm
1309 12:28:40.948814 # selftests: arm64: sme_trap_non_streaming
1310 12:28:41.064961 # Registered handlers for all signals.
1311 12:28:41.065502 # Detected MINSTKSIGSZ:10000
1312 12:28:41.065682 # Required Features: [] NOT supported
1313 12:28:41.065879 # Incompatible Features: [] supported
1314 12:28:41.066064 # ==>> completed. SKIP.
1315 12:28:41.066250 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1316 12:28:41.075535 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1317 12:28:41.131808 # selftests: arm64: sme_trap_za
1318 12:28:41.186395 # Registered handlers for all signals.
1319 12:28:41.186636 # Detected MINSTKSIGSZ:10000
1320 12:28:41.186719 # Testcase initialized.
1321 12:28:41.189189 # SIG_OK -- SP:0xFFFFE6491D60 si_addr@:0xaaaac6032510 si_code:1 token@:(nil) offset:-187650443257104
1322 12:28:41.189329 # ==>> completed. PASS(1)
1323 12:28:41.189603 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1324 12:28:41.197120 ok 21 selftests: arm64: sme_trap_za
1325 12:28:41.250489 # selftests: arm64: sme_vl
1326 12:28:41.306119 # Registered handlers for all signals.
1327 12:28:41.306363 # Detected MINSTKSIGSZ:10000
1328 12:28:41.306462 # Required Features: [ SME ] supported
1329 12:28:41.306574 # Incompatible Features: [] absent
1330 12:28:41.306664 # Testcase initialized.
1331 12:28:41.306753 # uc context validated.
1332 12:28:41.306839 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1333 12:28:41.306928 # Handled SIG_COPYCTX
1334 12:28:41.307017 # got expected VL 32
1335 12:28:41.307119 # ==>> completed. PASS(1)
1336 12:28:41.307204 # # SME VL :: Check that we get the right SME VL reported
1337 12:28:41.318319 ok 22 selftests: arm64: sme_vl
1338 12:28:41.373150 # selftests: arm64: ssve_regs
1339 12:28:41.576120 # Registered handlers for all signals.
1340 12:28:41.576565 # Detected MINSTKSIGSZ:10000
1341 12:28:41.576676 # Required Features: [ SME FA64 ] supported
1342 12:28:41.576771 # Incompatible Features: [] absent
1343 12:28:41.576857 # Testcase initialized.
1344 12:28:41.576945 # Testing VL 256
1345 12:28:41.577031 # Validating EXTRA...
1346 12:28:41.577135 # uc context validated.
1347 12:28:41.577220 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1348 12:28:41.577305 # Handled SIG_COPYCTX
1349 12:28:41.577389 # Got expected size 8752 and VL 256
1350 12:28:41.577474 # Testing VL 128
1351 12:28:41.577559 # Validating EXTRA...
1352 12:28:41.577644 # uc context validated.
1353 12:28:41.577753 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1354 12:28:41.577837 # Handled SIG_COPYCTX
1355 12:28:41.577922 # Got expected size 4384 and VL 128
1356 12:28:41.578004 # Testing VL 64
1357 12:28:41.578086 # uc context validated.
1358 12:28:41.578186 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1359 12:28:41.587208 # Handled SIG_COPYCTX
1360 12:28:41.587448 # Got expected size 2208 and VL 64
1361 12:28:41.587541 # Testing VL 32
1362 12:28:41.587823 # uc context validated.
1363 12:28:41.587931 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1364 12:28:41.588022 # Handled SIG_COPYCTX
1365 12:28:41.588112 # Got expected size 1120 and VL 32
1366 12:28:41.588200 # Testing VL 16
1367 12:28:41.588286 # uc context validated.
1368 12:28:41.588369 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1369 12:28:41.588455 # Handled SIG_COPYCTX
1370 12:28:41.588562 # Got expected size 576 and VL 16
1371 12:28:41.588656 # ==>> completed. PASS(1)
1372 12:28:41.588744 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1373 12:28:41.588849 ok 23 selftests: arm64: ssve_regs
1374 12:28:41.640795 # selftests: arm64: sve_regs
1375 12:28:42.084109 # Registered handlers for all signals.
1376 12:28:42.085889 # Detected MINSTKSIGSZ:10000
1377 12:28:42.086037 # Required Features: [ SVE ] supported
1378 12:28:42.086134 # Incompatible Features: [] absent
1379 12:28:42.086238 # Testcase initialized.
1380 12:28:42.086331 # Testing VL 256
1381 12:28:42.086418 # Validating EXTRA...
1382 12:28:42.086751 # uc context validated.
1383 12:28:42.086940 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1384 12:28:42.087116 # Handled SIG_COPYCTX
1385 12:28:42.087284 # Got expected size 8752 and VL 256
1386 12:28:42.087459 # Testing VL 240
1387 12:28:42.087631 # Validating EXTRA...
1388 12:28:42.087796 # uc context validated.
1389 12:28:42.087982 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1390 12:28:42.088114 # Handled SIG_COPYCTX
1391 12:28:42.088232 # Got expected size 8208 and VL 240
1392 12:28:42.088350 # Testing VL 224
1393 12:28:42.088472 # Validating EXTRA...
1394 12:28:42.088590 # uc context validated.
1395 12:28:42.088706 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1396 12:28:42.088825 # Handled SIG_COPYCTX
1397 12:28:42.088940 # Got expected size 7664 and VL 224
1398 12:28:42.089058 # Testing VL 208
1399 12:28:42.089174 # Validating EXTRA...
1400 12:28:42.089291 # uc context validated.
1401 12:28:42.089408 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1402 12:28:42.089524 # Handled SIG_COPYCTX
1403 12:28:42.089641 # Got expected size 7120 and VL 208
1404 12:28:42.089817 # Testing VL 192
1405 12:28:42.089952 # Validating EXTRA...
1406 12:28:42.090071 # uc context validated.
1407 12:28:42.090185 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1408 12:28:42.095384 # Handled SIG_COPYCTX
1409 12:28:42.095632 # Got expected size 6576 and VL 192
1410 12:28:42.096019 # Testing VL 176
1411 12:28:42.096127 # Validating EXTRA...
1412 12:28:42.096221 # uc context validated.
1413 12:28:42.096312 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1414 12:28:42.096401 # Handled SIG_COPYCTX
1415 12:28:42.096492 # Got expected size 6032 and VL 176
1416 12:28:42.096582 # Testing VL 160
1417 12:28:42.096667 # Validating EXTRA...
1418 12:28:42.096749 # uc context validated.
1419 12:28:42.096852 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1420 12:28:42.096941 # Handled SIG_COPYCTX
1421 12:28:42.097026 # Got expected size 5488 and VL 160
1422 12:28:42.097112 # Testing VL 144
1423 12:28:42.097196 # Validating EXTRA...
1424 12:28:42.097280 # uc context validated.
1425 12:28:42.097381 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1426 12:28:42.097473 # Handled SIG_COPYCTX
1427 12:28:42.097562 # Got expected size 4944 and VL 144
1428 12:28:42.097655 # Testing VL 128
1429 12:28:42.097742 # Validating EXTRA...
1430 12:28:42.097826 # uc context validated.
1431 12:28:42.097926 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1432 12:28:42.098014 # Handled SIG_COPYCTX
1433 12:28:42.098098 # Got expected size 4384 and VL 128
1434 12:28:42.098184 # Testing VL 112
1435 12:28:42.098269 # Validating EXTRA...
1436 12:28:42.098353 # uc context validated.
1437 12:28:42.098453 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1438 12:28:42.098543 # Handled SIG_COPYCTX
1439 12:28:42.098632 # Got expected size 3840 and VL 112
1440 12:28:42.098718 # Testing VL 96
1441 12:28:42.098803 # uc context validated.
1442 12:28:42.098910 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1443 12:28:42.099000 # Handled SIG_COPYCTX
1444 12:28:42.099087 # Got expected size 3296 and VL 96
1445 12:28:42.099190 # Testing VL 80
1446 12:28:42.099279 # uc context validated.
1447 12:28:42.099365 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1448 12:28:42.099450 # Handled SIG_COPYCTX
1449 12:28:42.099551 # Got expected size 2752 and VL 80
1450 12:28:42.099639 # Testing VL 64
1451 12:28:42.099728 # uc context validated.
1452 12:28:42.099803 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1453 12:28:42.099879 # Handled SIG_COPYCTX
1454 12:28:42.099943 # Got expected size 2208 and VL 64
1455 12:28:42.108335 # Testing VL 48
1456 12:28:42.108580 # uc context validated.
1457 12:28:42.108666 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1458 12:28:42.108961 # Handled SIG_COPYCTX
1459 12:28:42.109058 # Got expected size 1664 and VL 48
1460 12:28:42.109136 # Testing VL 32
1461 12:28:42.109214 # uc context validated.
1462 12:28:42.109292 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1463 12:28:42.109377 # Handled SIG_COPYCTX
1464 12:28:42.109461 # Got expected size 1120 and VL 32
1465 12:28:42.109543 # Testing VL 16
1466 12:28:42.109621 # uc context validated.
1467 12:28:42.109707 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1468 12:28:42.109784 # Handled SIG_COPYCTX
1469 12:28:42.109879 # Got expected size 576 and VL 16
1470 12:28:42.109963 # ==>> completed. PASS(1)
1471 12:28:42.110042 # # SVE registers :: Check that we get the right SVE registers reported
1472 12:28:42.110127 ok 24 selftests: arm64: sve_regs
1473 12:28:42.158322 # selftests: arm64: sve_vl
1474 12:28:42.215263 # Registered handlers for all signals.
1475 12:28:42.215515 # Detected MINSTKSIGSZ:10000
1476 12:28:42.215802 # Required Features: [ SVE ] supported
1477 12:28:42.215913 # Incompatible Features: [] absent
1478 12:28:42.216007 # Testcase initialized.
1479 12:28:42.216094 # uc context validated.
1480 12:28:42.216179 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1481 12:28:42.216267 # Handled SIG_COPYCTX
1482 12:28:42.216360 # got expected VL 64
1483 12:28:42.216446 # ==>> completed. PASS(1)
1484 12:28:42.216549 # # SVE VL :: Check that we get the right SVE VL reported
1485 12:28:42.223303 ok 25 selftests: arm64: sve_vl
1486 12:28:42.278555 # selftests: arm64: za_no_regs
1487 12:28:42.344768 # Registered handlers for all signals.
1488 12:28:42.345075 # Detected MINSTKSIGSZ:10000
1489 12:28:42.345246 # Required Features: [ SME ] supported
1490 12:28:42.345643 # Incompatible Features: [] absent
1491 12:28:42.345816 # Testcase initialized.
1492 12:28:42.345973 # Testing VL 256
1493 12:28:42.346135 # uc context validated.
1494 12:28:42.346266 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1495 12:28:42.346394 # Handled SIG_COPYCTX
1496 12:28:42.346519 # Got expected size 16 and VL 256
1497 12:28:42.346645 # Testing VL 128
1498 12:28:42.346768 # uc context validated.
1499 12:28:42.347530 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1500 12:28:42.347684 # Handled SIG_COPYCTX
1501 12:28:42.348023 # Got expected size 16 and VL 128
1502 12:28:42.348162 # Testing VL 64
1503 12:28:42.348288 # uc context validated.
1504 12:28:42.348417 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1505 12:28:42.348545 # Handled SIG_COPYCTX
1506 12:28:42.348670 # Got expected size 16 and VL 64
1507 12:28:42.348825 # Testing VL 32
1508 12:28:42.348956 # uc context validated.
1509 12:28:42.349080 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1510 12:28:42.349200 # Handled SIG_COPYCTX
1511 12:28:42.349316 # Got expected size 16 and VL 32
1512 12:28:42.349479 # Testing VL 16
1513 12:28:42.349617 # uc context validated.
1514 12:28:42.349788 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1515 12:28:42.349927 # Handled SIG_COPYCTX
1516 12:28:42.350093 # Got expected size 16 and VL 16
1517 12:28:42.350248 # ==>> completed. PASS(1)
1518 12:28:42.350368 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1519 12:28:42.358484 ok 26 selftests: arm64: za_no_regs
1520 12:28:42.432458 # selftests: arm64: za_regs
1521 12:28:42.637610 # Registered handlers for all signals.
1522 12:28:42.638238 # Detected MINSTKSIGSZ:10000
1523 12:28:42.638351 # Required Features: [ SME ] supported
1524 12:28:42.638439 # Incompatible Features: [] absent
1525 12:28:42.638522 # Testcase initialized.
1526 12:28:42.638612 # Testing VL 256
1527 12:28:42.638695 # Validating EXTRA...
1528 12:28:42.638773 # uc context validated.
1529 12:28:42.638846 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1530 12:28:42.638919 # Handled SIG_COPYCTX
1531 12:28:42.639014 # Got expected size 65552 and VL 256
1532 12:28:42.640398 # Testing VL 128
1533 12:28:42.640762 # Validating EXTRA...
1534 12:28:42.640855 # uc context validated.
1535 12:28:42.640929 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1536 12:28:42.641016 # Handled SIG_COPYCTX
1537 12:28:42.641091 # Got expected size 16400 and VL 128
1538 12:28:42.641179 # Testing VL 64
1539 12:28:42.641251 # Validating EXTRA...
1540 12:28:42.641321 # uc context validated.
1541 12:28:42.641405 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1542 12:28:42.641481 # Handled SIG_COPYCTX
1543 12:28:42.641570 # Got expected size 4112 and VL 64
1544 12:28:42.641651 # Testing VL 32
1545 12:28:42.641736 # uc context validated.
1546 12:28:42.641821 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1547 12:28:42.642106 # Handled SIG_COPYCTX
1548 12:28:42.642202 # Got expected size 1040 and VL 32
1549 12:28:42.642464 # Testing VL 16
1550 12:28:42.642633 # uc context validated.
1551 12:28:42.649775 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1552 12:28:42.650086 # Handled SIG_COPYCTX
1553 12:28:42.650274 # Got expected size 272 and VL 16
1554 12:28:42.650671 # ==>> completed. PASS(1)
1555 12:28:42.650812 # # ZA register :: Check that we get the right ZA registers reported
1556 12:28:42.650935 ok 27 selftests: arm64: za_regs
1557 12:28:42.704436 # selftests: arm64: pac
1558 12:28:42.873025 # TAP version 13
1559 12:28:42.873271 # 1..7
1560 12:28:42.873366 # # Starting 7 tests from 1 test cases.
1561 12:28:42.873687 # # RUN global.corrupt_pac ...
1562 12:28:42.873795 # # OK global.corrupt_pac
1563 12:28:42.873886 # ok 1 global.corrupt_pac
1564 12:28:42.873970 # # RUN global.pac_instructions_not_nop ...
1565 12:28:42.874056 # # OK global.pac_instructions_not_nop
1566 12:28:42.874141 # ok 2 global.pac_instructions_not_nop
1567 12:28:42.874226 # # RUN global.pac_instructions_not_nop_generic ...
1568 12:28:42.874332 # # OK global.pac_instructions_not_nop_generic
1569 12:28:42.874423 # ok 3 global.pac_instructions_not_nop_generic
1570 12:28:42.874512 # # RUN global.single_thread_different_keys ...
1571 12:28:42.874599 # # OK global.single_thread_different_keys
1572 12:28:42.874703 # ok 4 global.single_thread_different_keys
1573 12:28:42.874792 # # RUN global.exec_changed_keys ...
1574 12:28:42.874879 # # OK global.exec_changed_keys
1575 12:28:42.874985 # ok 5 global.exec_changed_keys
1576 12:28:42.875077 # # RUN global.context_switch_keep_keys ...
1577 12:28:42.875178 # # OK global.context_switch_keep_keys
1578 12:28:42.875280 # ok 6 global.context_switch_keep_keys
1579 12:28:42.875385 # # RUN global.context_switch_keep_keys_generic ...
1580 12:28:42.875828 # # OK global.context_switch_keep_keys_generic
1581 12:28:42.875934 # ok 7 global.context_switch_keep_keys_generic
1582 12:28:42.876020 # # PASSED: 7 / 7 tests passed.
1583 12:28:42.876124 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1584 12:28:42.884880 ok 28 selftests: arm64: pac
1585 12:28:42.935945 # selftests: arm64: fp-stress
1586 12:28:59.118602 # TAP version 13
1587 12:28:59.118935 # 1..27
1588 12:28:59.119141 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1589 12:28:59.119283 # # Will run for 10s
1590 12:28:59.119402 # # Started FPSIMD-0-0
1591 12:28:59.119518 # # Started SVE-VL-256-0
1592 12:28:59.119631 # # Started SVE-VL-240-0
1593 12:28:59.119769 # # Started SVE-VL-224-0
1594 12:28:59.119914 # # Started SVE-VL-208-0
1595 12:28:59.120352 # # Started SVE-VL-192-0
1596 12:28:59.120530 # # Started SVE-VL-176-0
1597 12:28:59.120676 # # Started SVE-VL-160-0
1598 12:28:59.120808 # # Started SVE-VL-144-0
1599 12:28:59.120940 # # Started SVE-VL-128-0
1600 12:28:59.121122 # # Started SVE-VL-112-0
1601 12:28:59.121319 # # Started SVE-VL-96-0
1602 12:28:59.121516 # # Started SVE-VL-80-0
1603 12:28:59.121732 # # Started SVE-VL-64-0
1604 12:28:59.121905 # # Started SVE-VL-48-0
1605 12:28:59.122076 # # Started SVE-VL-32-0
1606 12:28:59.122248 # # Started SVE-VL-16-0
1607 12:28:59.122423 # # Started SSVE-VL-256-0
1608 12:28:59.122596 # # Started ZA-VL-256-0
1609 12:28:59.122763 # # Started SSVE-VL-128-0
1610 12:28:59.122933 # # Started ZA-VL-128-0
1611 12:28:59.123108 # # Started SSVE-VL-64-0
1612 12:28:59.123346 # # Started ZA-VL-64-0
1613 12:28:59.123532 # # Started SSVE-VL-32-0
1614 12:28:59.123707 # # Started ZA-VL-32-0
1615 12:28:59.123880 # # Started SSVE-VL-16-0
1616 12:28:59.124042 # # Started ZA-VL-16-0
1617 12:28:59.124220 # # SVE-VL-256-0: Vector length: 2048 bits
1618 12:28:59.124382 # # SVE-VL-256-0: PID: 913
1619 12:28:59.124552 # # FPSIMD-0-0: Vector length: 128 bits
1620 12:28:59.124679 # # FPSIMD-0-0: PID: 912
1621 12:28:59.124795 # # SVE-VL-240-0: Vector length: 1920 bits
1622 12:28:59.124909 # # SVE-VL-240-0: PID: 914
1623 12:28:59.125023 # # SVE-VL-192-0: Vector length: 1536 bits
1624 12:28:59.125137 # # SVE-VL-192-0: PID: 917
1625 12:28:59.125280 # # SVE-VL-160-0: Vector length: 1280 bits
1626 12:28:59.125427 # # SVE-VL-160-0: PID: 919
1627 12:28:59.125580 # # SVE-VL-176-0: Vector length: 1408 bits
1628 12:28:59.125746 # # SVE-VL-176-0: PID: 918
1629 12:28:59.125886 # # SVE-VL-144-0: Vector length: 1152 bits
1630 12:28:59.126044 # # SVE-VL-144-0: PID: 920
1631 12:28:59.126210 # # SVE-VL-224-0: Vector length: 1792 bits
1632 12:28:59.126332 # # SVE-VL-224-0: PID: 915
1633 12:28:59.126446 # # SVE-VL-96-0: Vector length: 768 bits
1634 12:28:59.126558 # # SVE-VL-96-0: PID: 923
1635 12:28:59.126671 # # SVE-VL-64-0: Vector length: 512 bits
1636 12:28:59.126784 # # SVE-VL-64-0: PID: 925
1637 12:28:59.126896 # # SVE-VL-16-0: Vector length: 128 bits
1638 12:28:59.127008 # # SVE-VL-16-0: PID: 928
1639 12:28:59.127119 # # SVE-VL-128-0: Vector length: 1024 bits
1640 12:28:59.127231 # # SVE-VL-128-0: PID: 921
1641 12:28:59.132467 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1642 12:28:59.133012 # # SSVE-VL-64-0: PID: 933
1643 12:28:59.133221 # # SVE-VL-48-0: Vector length: 384 bits
1644 12:28:59.133397 # # SVE-VL-48-0: PID: 926
1645 12:28:59.133570 # # SVE-VL-112-0: Vector length: 896 bits
1646 12:28:59.133762 # # SVE-VL-112-0: PID: 922
1647 12:28:59.133943 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1648 12:28:59.134160 # # SVE-VL-208-0: Vector length: 1664 bits
1649 12:28:59.134341 # # SVE-VL-208-0: PID: 916
1650 12:28:59.134512 # # ZA-VL-128-0: PID: 932
1651 12:28:59.134705 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1652 12:28:59.134917 # # ZA-VL-64-0: PID: 934
1653 12:28:59.135094 # # SVE-VL-32-0: Vector length: 256 bits
1654 12:28:59.135268 # # SVE-VL-32-0: PID: 927
1655 12:28:59.135416 # # SVE-VL-80-0: Vector length: 640 bits
1656 12:28:59.135532 # # SVE-VL-80-0: PID: 924
1657 12:28:59.135676 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1658 12:28:59.135799 # # ZA-VL-16-0: PID: 938
1659 12:28:59.135919 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1660 12:28:59.136033 # # SSVE-VL-32-0: PID: 935
1661 12:28:59.136144 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1662 12:28:59.136257 # # SSVE-VL-256-0: PID: 929
1663 12:28:59.136373 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1664 12:28:59.136515 # # SSVE-VL-16-0: PID: 937
1665 12:28:59.136636 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1666 12:28:59.136753 # # SSVE-VL-128-0: PID: 931
1667 12:28:59.136867 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1668 12:28:59.138773 # # ZA-VL-32-0: PID: 936
1669 12:28:59.138984 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1670 12:28:59.139193 # # ZA-VL-256-0: PID: 930
1671 12:28:59.139337 # # Finishing up...
1672 12:28:59.139460 # ok 1 FPSIMD-0-0
1673 12:28:59.139579 # ok 2 SVE-VL-256-0
1674 12:28:59.139696 # ok 3 SVE-VL-240-0
1675 12:28:59.139812 # ok 4 SVE-VL-224-0
1676 12:28:59.139930 # ok 5 SVE-VL-208-0
1677 12:28:59.140087 # ok 6 SVE-VL-192-0
1678 12:28:59.140221 # ok 7 SVE-VL-176-0
1679 12:28:59.140352 # ok 8 SVE-VL-160-0
1680 12:28:59.140496 # ok 9 SVE-VL-144-0
1681 12:28:59.156546 # ok 10 SVE-VL-128-0
1682 12:28:59.156779 # ok 11 SVE-VL-112-0
1683 12:28:59.156871 # ok 12 SVE-VL-96-0
1684 12:28:59.156970 # ok 13 SVE-VL-80-0
1685 12:28:59.157056 # ok 14 SVE-VL-64-0
1686 12:28:59.157161 # ok 15 SVE-VL-48-0
1687 12:28:59.157252 # ok 16 SVE-VL-32-0
1688 12:28:59.157338 # ok 17 SVE-VL-16-0
1689 12:28:59.157425 # ok 18 SSVE-VL-256-0
1690 12:28:59.157511 # ok 19 ZA-VL-256-0
1691 12:28:59.157597 # ok 20 SSVE-VL-128-0
1692 12:28:59.157692 # ok 21 ZA-VL-128-0
1693 12:28:59.157779 # ok 22 SSVE-VL-64-0
1694 12:28:59.157865 # ok 23 ZA-VL-64-0
1695 12:28:59.157956 # ok 24 SSVE-VL-32-0
1696 12:28:59.158062 # ok 25 ZA-VL-32-0
1697 12:28:59.158152 # ok 26 SSVE-VL-16-0
1698 12:28:59.158239 # ok 27 ZA-VL-16-0
1699 12:28:59.158325 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=4949, signals=9
1700 12:28:59.158413 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=8002, signals=9
1701 12:28:59.158500 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=10365, signals=9
1702 12:28:59.158604 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=988, signals=9
1703 12:28:59.158695 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=6754, signals=9
1704 12:28:59.158783 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=614, signals=9
1705 12:28:59.158891 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=6224, signals=9
1706 12:28:59.158996 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=99, signals=7
1707 12:28:59.159103 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3167, signals=9
1708 12:28:59.166265 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=7164, signals=9
1709 12:28:59.261747 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2513, signals=9
1710 12:28:59.262066 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=4732, signals=9
1711 12:28:59.262234 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3331, signals=9
1712 12:28:59.262435 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=12736, signals=9
1713 12:28:59.262595 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=3399, signals=9
1714 12:28:59.262761 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2401, signals=9
1715 12:28:59.262926 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2024, signals=9
1716 12:28:59.263124 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=4119, signals=9
1717 12:28:59.263266 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3723, signals=9
1718 12:28:59.263385 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2443, signals=9
1719 12:28:59.263500 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1253, signals=9
1720 12:28:59.263615 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2293, signals=9
1721 12:28:59.263728 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=3458, signals=9
1722 12:28:59.301208 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1373, signals=9
1723 12:28:59.301537 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=2878, signals=9
1724 12:28:59.301930 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6640, signals=9
1725 12:28:59.302066 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=3334, signals=9
1726 12:28:59.302186 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1727 12:28:59.312856 ok 29 selftests: arm64: fp-stress
1728 12:28:59.525228 # selftests: arm64: sve-ptrace
1729 12:28:59.678770 # TAP version 13
1730 12:28:59.679048 # 1..4104
1731 12:28:59.679469 # # Parent is 955, child is 956
1732 12:28:59.679672 # ok 1 SVE FPSIMD set via SVE: 0
1733 12:28:59.679901 # ok 2 SVE get_fpsimd() gave same state
1734 12:28:59.680093 # ok 3 SVE SVE_PT_VL_INHERIT set
1735 12:28:59.680305 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1736 12:28:59.680479 # ok 5 Set SVE VL 16
1737 12:28:59.680651 # ok 6 Set and get SVE data for VL 16
1738 12:28:59.680814 # ok 7 Set and get FPSIMD data for SVE VL 16
1739 12:28:59.680978 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1740 12:28:59.681140 # ok 9 Set SVE VL 32
1741 12:28:59.681303 # ok 10 Set and get SVE data for VL 32
1742 12:28:59.681465 # ok 11 Set and get FPSIMD data for SVE VL 32
1743 12:28:59.681628 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1744 12:28:59.681802 # ok 13 Set SVE VL 48
1745 12:28:59.681967 # ok 14 Set and get SVE data for VL 48
1746 12:28:59.682178 # ok 15 Set and get FPSIMD data for SVE VL 48
1747 12:28:59.682348 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1748 12:28:59.682514 # ok 17 Set SVE VL 64
1749 12:28:59.682675 # ok 18 Set and get SVE data for VL 64
1750 12:28:59.682801 # ok 19 Set and get FPSIMD data for SVE VL 64
1751 12:28:59.682922 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1752 12:28:59.683037 # ok 21 Set SVE VL 80
1753 12:28:59.683155 # ok 22 Set and get SVE data for VL 80
1754 12:28:59.683272 # ok 23 Set and get FPSIMD data for SVE VL 80
1755 12:28:59.683388 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1756 12:28:59.683504 # ok 25 Set SVE VL 96
1757 12:28:59.683621 # ok 26 Set and get SVE data for VL 96
1758 12:28:59.683737 # ok 27 Set and get FPSIMD data for SVE VL 96
1759 12:28:59.683852 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1760 12:28:59.683969 # ok 29 Set SVE VL 112
1761 12:28:59.684084 # ok 30 Set and get SVE data for VL 112
1762 12:28:59.684198 # ok 31 Set and get FPSIMD data for SVE VL 112
1763 12:28:59.684313 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1764 12:28:59.684458 # ok 33 Set SVE VL 128
1765 12:28:59.684580 # ok 34 Set and get SVE data for VL 128
1766 12:28:59.684696 # ok 35 Set and get FPSIMD data for SVE VL 128
1767 12:28:59.684812 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1768 12:28:59.684928 # ok 37 Set SVE VL 144
1769 12:28:59.685861 # ok 38 Set and get SVE data for VL 144
1770 12:28:59.686254 # ok 39 Set and get FPSIMD data for SVE VL 144
1771 12:28:59.686454 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1772 12:28:59.686609 # ok 41 Set SVE VL 160
1773 12:28:59.686733 # ok 42 Set and get SVE data for VL 160
1774 12:28:59.686878 # ok 43 Set and get FPSIMD data for SVE VL 160
1775 12:28:59.687000 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1776 12:28:59.687118 # ok 45 Set SVE VL 176
1777 12:28:59.687261 # ok 46 Set and get SVE data for VL 176
1778 12:28:59.687446 # ok 47 Set and get FPSIMD data for SVE VL 176
1779 12:28:59.687614 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1780 12:28:59.687801 # ok 49 Set SVE VL 192
1781 12:28:59.687963 # ok 50 Set and get SVE data for VL 192
1782 12:28:59.688163 # ok 51 Set and get FPSIMD data for SVE VL 192
1783 12:28:59.688366 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1784 12:28:59.688558 # ok 53 Set SVE VL 208
1785 12:28:59.688746 # ok 54 Set and get SVE data for VL 208
1786 12:28:59.688954 # ok 55 Set and get FPSIMD data for SVE VL 208
1787 12:28:59.689147 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1788 12:28:59.689311 # ok 57 Set SVE VL 224
1789 12:28:59.689505 # ok 58 Set and get SVE data for VL 224
1790 12:28:59.690053 # ok 59 Set and get FPSIMD data for SVE VL 224
1791 12:28:59.690247 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1792 12:28:59.690418 # ok 61 Set SVE VL 240
1793 12:28:59.690593 # ok 62 Set and get SVE data for VL 240
1794 12:28:59.690741 # ok 63 Set and get FPSIMD data for SVE VL 240
1795 12:28:59.690882 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1796 12:28:59.691024 # ok 65 Set SVE VL 256
1797 12:28:59.691163 # ok 66 Set and get SVE data for VL 256
1798 12:28:59.691302 # ok 67 Set and get FPSIMD data for SVE VL 256
1799 12:28:59.691441 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1800 12:28:59.691624 # ok 69 Set SVE VL 272
1801 12:28:59.691759 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1802 12:28:59.691902 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1803 12:28:59.692079 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1804 12:28:59.692258 # ok 73 Set SVE VL 288
1805 12:28:59.692407 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1806 12:28:59.692526 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1807 12:28:59.692640 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1808 12:28:59.692755 # ok 77 Set SVE VL 304
1809 12:28:59.692869 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1810 12:28:59.692989 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1811 12:28:59.698244 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1812 12:28:59.698501 # ok 81 Set SVE VL 320
1813 12:28:59.698893 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1814 12:28:59.699035 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1815 12:28:59.699180 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1816 12:28:59.699321 # ok 85 Set SVE VL 336
1817 12:28:59.702210 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1818 12:28:59.702672 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1819 12:28:59.702828 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1820 12:28:59.702979 # ok 89 Set SVE VL 352
1821 12:28:59.703121 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1822 12:28:59.703310 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1823 12:28:59.703465 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1824 12:28:59.703639 # ok 93 Set SVE VL 368
1825 12:28:59.703778 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1826 12:28:59.703919 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1827 12:28:59.704123 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1828 12:28:59.704279 # ok 97 Set SVE VL 384
1829 12:28:59.704404 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1830 12:28:59.704529 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1831 12:28:59.704669 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1832 12:28:59.704788 # ok 101 Set SVE VL 400
1833 12:28:59.705366 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1834 12:28:59.705791 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1835 12:28:59.705979 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1836 12:28:59.706152 # ok 105 Set SVE VL 416
1837 12:28:59.706312 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1838 12:28:59.706508 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1839 12:28:59.706662 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1840 12:28:59.706783 # ok 109 Set SVE VL 432
1841 12:28:59.706897 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1842 12:28:59.707008 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1843 12:28:59.707119 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1844 12:28:59.707228 # ok 113 Set SVE VL 448
1845 12:28:59.707362 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1846 12:28:59.707478 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1847 12:28:59.713985 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1848 12:28:59.714248 # ok 117 Set SVE VL 464
1849 12:28:59.714656 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1850 12:28:59.714829 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1851 12:28:59.714957 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1852 12:28:59.715079 # ok 121 Set SVE VL 480
1853 12:28:59.715198 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1854 12:28:59.715357 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1855 12:28:59.715550 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1856 12:28:59.715721 # ok 125 Set SVE VL 496
1857 12:28:59.715895 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1858 12:28:59.716160 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1859 12:28:59.716366 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1860 12:28:59.716586 # ok 129 Set SVE VL 512
1861 12:28:59.716755 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1862 12:28:59.716912 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1863 12:28:59.717103 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1864 12:28:59.717295 # ok 133 Set SVE VL 528
1865 12:28:59.717482 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1866 12:28:59.717929 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1867 12:28:59.718141 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1868 12:28:59.718358 # ok 137 Set SVE VL 544
1869 12:28:59.718585 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1870 12:28:59.718760 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1871 12:28:59.718889 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1872 12:28:59.719009 # ok 141 Set SVE VL 560
1873 12:28:59.719123 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1874 12:28:59.719283 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1875 12:28:59.719408 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1876 12:28:59.719524 # ok 145 Set SVE VL 576
1877 12:28:59.719636 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1878 12:28:59.719749 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1879 12:28:59.719862 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1880 12:28:59.719976 # ok 149 Set SVE VL 592
1881 12:28:59.720088 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1882 12:28:59.720200 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1883 12:28:59.720312 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1884 12:28:59.720424 # ok 153 Set SVE VL 608
1885 12:28:59.720536 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1886 12:28:59.720648 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1887 12:28:59.720760 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1888 12:28:59.720873 # ok 157 Set SVE VL 624
1889 12:28:59.720986 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1890 12:28:59.725920 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1891 12:28:59.726286 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1892 12:28:59.726396 # ok 161 Set SVE VL 640
1893 12:28:59.726486 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1894 12:28:59.726573 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1895 12:28:59.726658 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1896 12:28:59.726760 # ok 165 Set SVE VL 656
1897 12:28:59.726848 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1898 12:28:59.726933 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1899 12:28:59.727239 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1900 12:28:59.727344 # ok 169 Set SVE VL 672
1901 12:28:59.727447 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1902 12:28:59.727551 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1903 12:28:59.727637 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1904 12:28:59.727723 # ok 173 Set SVE VL 688
1905 12:28:59.727824 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1906 12:28:59.727912 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1907 12:28:59.728003 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1908 12:28:59.728099 # ok 177 Set SVE VL 704
1909 12:28:59.728174 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1910 12:28:59.728245 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1911 12:28:59.728328 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1912 12:28:59.728400 # ok 181 Set SVE VL 720
1913 12:28:59.728483 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1914 12:28:59.728566 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1915 12:28:59.728843 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1916 12:28:59.728936 # ok 185 Set SVE VL 736
1917 12:28:59.729023 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1918 12:28:59.729109 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1919 12:28:59.729195 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1920 12:28:59.729268 # ok 189 Set SVE VL 752
1921 12:28:59.729350 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1922 12:28:59.729627 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1923 12:28:59.729726 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1924 12:28:59.729812 # ok 193 Set SVE VL 768
1925 12:28:59.729884 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1926 12:28:59.729972 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1927 12:28:59.730251 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1928 12:28:59.730350 # ok 197 Set SVE VL 784
1929 12:28:59.730439 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1930 12:28:59.730517 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1931 12:28:59.730605 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1932 12:28:59.730680 # ok 201 Set SVE VL 800
1933 12:28:59.737887 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1934 12:28:59.738206 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1935 12:28:59.738651 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1936 12:28:59.738808 # ok 205 Set SVE VL 816
1937 12:28:59.738932 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1938 12:28:59.739068 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1939 12:28:59.739232 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1940 12:28:59.739403 # ok 209 Set SVE VL 832
1941 12:28:59.739606 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1942 12:28:59.739821 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1943 12:28:59.740073 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1944 12:28:59.740274 # ok 213 Set SVE VL 848
1945 12:28:59.740450 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1946 12:28:59.740624 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1947 12:28:59.740800 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1948 12:28:59.740950 # ok 217 Set SVE VL 864
1949 12:28:59.741085 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1950 12:28:59.741322 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1951 12:28:59.741523 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1952 12:28:59.741689 # ok 221 Set SVE VL 880
1953 12:28:59.741830 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1954 12:28:59.741969 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1955 12:28:59.742132 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1956 12:28:59.742260 # ok 225 Set SVE VL 896
1957 12:28:59.742379 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1958 12:28:59.742495 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1959 12:28:59.742608 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1960 12:28:59.742722 # ok 229 Set SVE VL 912
1961 12:28:59.742837 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1962 12:28:59.742959 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1963 12:28:59.743134 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1964 12:28:59.743326 # ok 233 Set SVE VL 928
1965 12:28:59.743462 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1966 12:28:59.743604 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1967 12:28:59.743746 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1968 12:28:59.743887 # ok 237 Set SVE VL 944
1969 12:28:59.744053 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1970 12:28:59.744227 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1971 12:28:59.744373 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1972 12:28:59.744513 # ok 241 Set SVE VL 960
1973 12:28:59.744654 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1974 12:28:59.744794 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1975 12:28:59.744935 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1976 12:28:59.745079 # ok 245 Set SVE VL 976
1977 12:28:59.750024 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1978 12:28:59.750545 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1979 12:28:59.750720 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1980 12:28:59.750876 # ok 249 Set SVE VL 992
1981 12:28:59.751030 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1982 12:28:59.751212 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1983 12:28:59.751367 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1984 12:28:59.751542 # ok 253 Set SVE VL 1008
1985 12:28:59.751692 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1986 12:28:59.751868 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1987 12:28:59.752020 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1988 12:28:59.752167 # ok 257 Set SVE VL 1024
1989 12:28:59.752314 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1990 12:28:59.752489 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1991 12:28:59.752641 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1992 12:28:59.752788 # ok 261 Set SVE VL 1040
1993 12:28:59.752934 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1994 12:28:59.753084 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1995 12:28:59.753264 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1996 12:28:59.753416 # ok 265 Set SVE VL 1056
1997 12:28:59.753564 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1998 12:28:59.754210 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1999 12:28:59.754386 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
2000 12:28:59.754543 # ok 269 Set SVE VL 1072
2001 12:28:59.754694 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
2002 12:28:59.754882 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
2003 12:28:59.755043 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2004 12:28:59.755193 # ok 273 Set SVE VL 1088
2005 12:28:59.755343 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2006 12:28:59.755493 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2007 12:28:59.755642 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2008 12:28:59.755792 # ok 277 Set SVE VL 1104
2009 12:28:59.755941 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2010 12:28:59.756089 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2011 12:28:59.756239 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2012 12:28:59.756388 # ok 281 Set SVE VL 1120
2013 12:28:59.761067 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2014 12:28:59.761305 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2015 12:28:59.761692 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2016 12:28:59.761791 # ok 285 Set SVE VL 1136
2017 12:28:59.761872 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2018 12:28:59.761953 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2019 12:28:59.762029 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2020 12:28:59.762100 # ok 289 Set SVE VL 1152
2021 12:28:59.762170 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2022 12:28:59.762254 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2023 12:28:59.762330 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2024 12:28:59.771531 # ok 293 Set SVE VL 1168
2025 12:28:59.771817 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2026 12:28:59.772247 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2027 12:28:59.772441 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2028 12:28:59.772608 # ok 297 Set SVE VL 1184
2029 12:28:59.772762 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2030 12:28:59.772914 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2031 12:28:59.773065 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2032 12:28:59.773251 # ok 301 Set SVE VL 1200
2033 12:28:59.773412 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2034 12:28:59.773574 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2035 12:28:59.773751 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2036 12:28:59.773915 # ok 305 Set SVE VL 1216
2037 12:28:59.774076 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2038 12:28:59.774226 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2039 12:28:59.774384 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2040 12:28:59.774547 # ok 309 Set SVE VL 1232
2041 12:28:59.774705 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2042 12:28:59.774827 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2043 12:28:59.774943 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2044 12:28:59.775061 # ok 313 Set SVE VL 1248
2045 12:28:59.775173 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2046 12:28:59.775286 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2047 12:28:59.775400 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2048 12:28:59.775513 # ok 317 Set SVE VL 1264
2049 12:28:59.775627 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2050 12:28:59.775741 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2051 12:28:59.775854 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2052 12:28:59.775966 # ok 321 Set SVE VL 1280
2053 12:28:59.776080 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2054 12:28:59.779940 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2055 12:28:59.780155 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2056 12:28:59.780576 # ok 325 Set SVE VL 1296
2057 12:28:59.780780 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2058 12:28:59.780969 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2059 12:28:59.781174 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2060 12:28:59.781423 # ok 329 Set SVE VL 1312
2061 12:28:59.781606 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2062 12:28:59.781774 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2063 12:28:59.781995 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2064 12:28:59.782171 # ok 333 Set SVE VL 1328
2065 12:28:59.782320 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2066 12:28:59.782493 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2067 12:28:59.782647 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2068 12:28:59.782766 # ok 337 Set SVE VL 1344
2069 12:28:59.782880 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2070 12:28:59.782994 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2071 12:28:59.783109 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2072 12:28:59.783220 # ok 341 Set SVE VL 1360
2073 12:28:59.783331 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2074 12:28:59.783472 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2075 12:28:59.783594 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2076 12:28:59.783710 # ok 345 Set SVE VL 1376
2077 12:28:59.783823 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2078 12:28:59.783936 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2079 12:28:59.784049 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2080 12:28:59.784165 # ok 349 Set SVE VL 1392
2081 12:28:59.784277 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2082 12:28:59.787374 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2083 12:28:59.787967 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2084 12:28:59.788153 # ok 353 Set SVE VL 1408
2085 12:28:59.788324 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2086 12:28:59.788487 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2087 12:28:59.788634 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2088 12:28:59.788780 # ok 357 Set SVE VL 1424
2089 12:28:59.788961 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2090 12:28:59.789120 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2091 12:28:59.789273 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2092 12:28:59.789433 # ok 361 Set SVE VL 1440
2093 12:28:59.789581 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2094 12:28:59.789765 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2095 12:28:59.789937 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2096 12:28:59.790065 # ok 365 Set SVE VL 1456
2097 12:28:59.790222 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2098 12:28:59.790380 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2099 12:28:59.790520 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2100 12:28:59.790641 # ok 369 Set SVE VL 1472
2101 12:28:59.790754 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2102 12:28:59.790871 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2103 12:28:59.790987 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2104 12:28:59.791103 # ok 373 Set SVE VL 1488
2105 12:28:59.791219 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2106 12:28:59.791333 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2107 12:28:59.791449 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2108 12:28:59.791590 # ok 377 Set SVE VL 1504
2109 12:28:59.791710 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2110 12:28:59.791826 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2111 12:28:59.795196 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2112 12:28:59.795637 # ok 381 Set SVE VL 1520
2113 12:28:59.795745 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2114 12:28:59.795834 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2115 12:28:59.795920 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2116 12:28:59.796025 # ok 385 Set SVE VL 1536
2117 12:28:59.796110 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2118 12:28:59.796192 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2119 12:28:59.796288 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2120 12:28:59.796376 # ok 389 Set SVE VL 1552
2121 12:28:59.796460 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2122 12:28:59.796563 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2123 12:28:59.796652 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2124 12:28:59.796754 # ok 393 Set SVE VL 1568
2125 12:28:59.796842 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2126 12:28:59.796944 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2127 12:28:59.797235 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2128 12:28:59.797328 # ok 397 Set SVE VL 1584
2129 12:28:59.797430 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2130 12:28:59.797528 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2131 12:28:59.797622 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2132 12:28:59.797901 # ok 401 Set SVE VL 1600
2133 12:28:59.797996 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2134 12:28:59.798102 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2135 12:28:59.798205 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2136 12:28:59.798493 # ok 405 Set SVE VL 1616
2137 12:28:59.798585 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2138 12:28:59.798696 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2139 12:28:59.803322 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2140 12:28:59.803629 # ok 409 Set SVE VL 1632
2141 12:28:59.803843 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2142 12:28:59.804067 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2143 12:28:59.804280 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2144 12:28:59.804440 # ok 413 Set SVE VL 1648
2145 12:28:59.804613 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2146 12:28:59.804774 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2147 12:28:59.804962 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2148 12:28:59.805127 # ok 417 Set SVE VL 1664
2149 12:28:59.805309 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2150 12:28:59.805477 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2151 12:28:59.805673 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2152 12:28:59.805841 # ok 421 Set SVE VL 1680
2153 12:28:59.806010 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2154 12:28:59.806175 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2155 12:28:59.806368 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2156 12:28:59.806533 # ok 425 Set SVE VL 1696
2157 12:28:59.806655 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2158 12:28:59.806770 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2159 12:28:59.806885 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2160 12:28:59.807000 # ok 429 Set SVE VL 1712
2161 12:28:59.807140 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2162 12:28:59.811225 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2163 12:28:59.811699 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2164 12:28:59.811856 # ok 433 Set SVE VL 1728
2165 12:28:59.812005 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2166 12:28:59.812150 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2167 12:28:59.812506 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2168 12:28:59.812609 # ok 437 Set SVE VL 1744
2169 12:28:59.812693 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2170 12:28:59.812771 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2171 12:28:59.812848 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2172 12:28:59.812925 # ok 441 Set SVE VL 1760
2173 12:28:59.813001 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2174 12:28:59.813095 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2175 12:28:59.813174 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2176 12:28:59.813251 # ok 445 Set SVE VL 1776
2177 12:28:59.813327 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2178 12:28:59.813403 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2179 12:28:59.813494 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2180 12:28:59.813573 # ok 449 Set SVE VL 1792
2181 12:28:59.813657 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2182 12:28:59.813734 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2183 12:28:59.813810 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2184 12:28:59.813901 # ok 453 Set SVE VL 1808
2185 12:28:59.813978 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2186 12:28:59.814068 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2187 12:28:59.814146 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2188 12:28:59.814222 # ok 457 Set SVE VL 1824
2189 12:28:59.814311 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2190 12:28:59.814388 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2191 12:28:59.814464 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2192 12:28:59.814553 # ok 461 Set SVE VL 1840
2193 12:28:59.814631 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2194 12:28:59.819303 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2195 12:28:59.819759 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2196 12:28:59.819968 # ok 465 Set SVE VL 1856
2197 12:28:59.820139 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2198 12:28:59.820303 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2199 12:28:59.820497 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2200 12:28:59.820662 # ok 469 Set SVE VL 1872
2201 12:28:59.820820 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2202 12:28:59.820979 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2203 12:28:59.821137 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2204 12:28:59.821298 # ok 473 Set SVE VL 1888
2205 12:28:59.821486 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2206 12:28:59.821664 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2207 12:28:59.821828 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2208 12:28:59.821989 # ok 477 Set SVE VL 1904
2209 12:28:59.822149 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2210 12:28:59.822311 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2211 12:28:59.843294 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2212 12:28:59.843760 # ok 481 Set SVE VL 1920
2213 12:28:59.843872 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2214 12:28:59.844009 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2215 12:28:59.844106 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2216 12:28:59.844183 # ok 485 Set SVE VL 1936
2217 12:28:59.844275 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2218 12:28:59.844351 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2219 12:28:59.844425 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2220 12:28:59.844512 # ok 489 Set SVE VL 1952
2221 12:28:59.844584 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2222 12:28:59.844653 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2223 12:28:59.844735 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2224 12:28:59.844807 # ok 493 Set SVE VL 1968
2225 12:28:59.844889 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2226 12:28:59.844972 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2227 12:28:59.845055 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2228 12:28:59.845137 # ok 497 Set SVE VL 1984
2229 12:28:59.845413 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2230 12:28:59.845505 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2231 12:28:59.845592 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2232 12:28:59.845744 # ok 501 Set SVE VL 2000
2233 12:28:59.845825 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2234 12:28:59.846104 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2235 12:28:59.846199 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2236 12:28:59.846291 # ok 505 Set SVE VL 2016
2237 12:28:59.846362 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2238 12:28:59.846445 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2239 12:28:59.847152 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2240 12:28:59.847261 # ok 509 Set SVE VL 2032
2241 12:28:59.847554 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2242 12:28:59.847649 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2243 12:28:59.847730 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2244 12:28:59.847822 # ok 513 Set SVE VL 2048
2245 12:28:59.847899 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2246 12:28:59.847995 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2247 12:28:59.848088 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2248 12:28:59.848177 # ok 517 Set SVE VL 2064
2249 12:28:59.848262 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2250 12:28:59.848357 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2251 12:28:59.848446 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2252 12:28:59.848721 # ok 521 Set SVE VL 2080
2253 12:28:59.848804 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2254 12:28:59.848893 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2255 12:28:59.849158 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2256 12:28:59.849242 # ok 525 Set SVE VL 2096
2257 12:28:59.849332 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2258 12:28:59.849418 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2259 12:28:59.849686 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2260 12:28:59.849781 # ok 529 Set SVE VL 2112
2261 12:28:59.849883 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2262 12:28:59.849987 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2263 12:28:59.850075 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2264 12:28:59.850179 # ok 533 Set SVE VL 2128
2265 12:28:59.850267 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2266 12:28:59.850369 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2267 12:28:59.850656 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2268 12:28:59.853467 # ok 537 Set SVE VL 2144
2269 12:28:59.853760 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2270 12:28:59.853864 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2271 12:28:59.853972 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2272 12:28:59.854064 # ok 541 Set SVE VL 2160
2273 12:28:59.854351 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2274 12:28:59.854441 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2275 12:28:59.854527 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2276 12:28:59.854969 # ok 545 Set SVE VL 2176
2277 12:28:59.855254 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2278 12:28:59.855345 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2279 12:28:59.855467 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2280 12:28:59.855552 # ok 549 Set SVE VL 2192
2281 12:28:59.855646 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2282 12:28:59.855718 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2283 12:28:59.855809 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2284 12:28:59.855881 # ok 553 Set SVE VL 2208
2285 12:28:59.855971 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2286 12:28:59.856056 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2287 12:28:59.856142 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2288 12:28:59.856232 # ok 557 Set SVE VL 2224
2289 12:28:59.856511 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2290 12:28:59.856594 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2291 12:28:59.856688 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2292 12:28:59.856760 # ok 561 Set SVE VL 2240
2293 12:28:59.856850 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2294 12:28:59.856936 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2295 12:28:59.857049 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2296 12:28:59.857133 # ok 565 Set SVE VL 2256
2297 12:28:59.857227 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2298 12:28:59.857314 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2299 12:28:59.857580 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2300 12:28:59.858122 # ok 569 Set SVE VL 2272
2301 12:28:59.858201 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2302 12:28:59.858302 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2303 12:28:59.858407 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2304 12:28:59.858502 # ok 573 Set SVE VL 2288
2305 12:28:59.858590 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2306 12:28:59.858674 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2307 12:28:59.858779 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2308 12:28:59.858866 # ok 577 Set SVE VL 2304
2309 12:28:59.858951 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2310 12:28:59.859055 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2311 12:28:59.859139 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2312 12:28:59.859225 # ok 581 Set SVE VL 2320
2313 12:28:59.859326 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2314 12:28:59.859421 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2315 12:28:59.859511 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2316 12:28:59.859616 # ok 585 Set SVE VL 2336
2317 12:28:59.859690 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2318 12:28:59.859996 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2319 12:28:59.860093 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2320 12:28:59.860172 # ok 589 Set SVE VL 2352
2321 12:28:59.860261 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2322 12:28:59.860338 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2323 12:28:59.860430 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2324 12:28:59.860522 # ok 593 Set SVE VL 2368
2325 12:28:59.860631 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2326 12:28:59.860927 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2327 12:28:59.861025 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2328 12:28:59.861108 # ok 597 Set SVE VL 2384
2329 12:28:59.861203 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2330 12:28:59.861286 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2331 12:28:59.861382 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2332 12:28:59.861464 # ok 601 Set SVE VL 2400
2333 12:28:59.861587 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2334 12:28:59.861694 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2335 12:28:59.861801 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2336 12:28:59.861884 # ok 605 Set SVE VL 2416
2337 12:28:59.861968 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2338 12:28:59.862059 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2339 12:28:59.862144 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2340 12:28:59.862230 # ok 609 Set SVE VL 2432
2341 12:28:59.862537 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2342 12:28:59.862766 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2343 12:28:59.862851 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2344 12:28:59.862944 # ok 613 Set SVE VL 2448
2345 12:28:59.863030 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2346 12:28:59.863305 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2347 12:28:59.863400 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2348 12:28:59.863475 # ok 617 Set SVE VL 2464
2349 12:28:59.863565 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2350 12:28:59.863646 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2351 12:28:59.863741 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2352 12:28:59.863808 # ok 621 Set SVE VL 2480
2353 12:28:59.864077 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2354 12:28:59.864170 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2355 12:28:59.864266 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2356 12:28:59.864350 # ok 625 Set SVE VL 2496
2357 12:28:59.864441 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2358 12:28:59.864520 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2359 12:28:59.864600 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2360 12:28:59.864678 # ok 629 Set SVE VL 2512
2361 12:28:59.864772 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2362 12:28:59.864862 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2363 12:28:59.864957 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2364 12:28:59.865036 # ok 633 Set SVE VL 2528
2365 12:28:59.865308 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2366 12:28:59.865402 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2367 12:28:59.865495 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2368 12:28:59.865573 # ok 637 Set SVE VL 2544
2369 12:28:59.865663 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2370 12:28:59.866090 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2371 12:28:59.866217 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2372 12:28:59.866326 # ok 641 Set SVE VL 2560
2373 12:28:59.866427 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2374 12:28:59.866517 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2375 12:28:59.866609 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2376 12:28:59.866694 # ok 645 Set SVE VL 2576
2377 12:28:59.866774 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2378 12:28:59.866870 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2379 12:28:59.866952 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2380 12:28:59.867035 # ok 649 Set SVE VL 2592
2381 12:28:59.867129 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2382 12:28:59.867212 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2383 12:28:59.867310 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2384 12:28:59.867393 # ok 653 Set SVE VL 2608
2385 12:28:59.867487 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2386 12:28:59.867586 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2387 12:28:59.867688 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2388 12:28:59.867787 # ok 657 Set SVE VL 2624
2389 12:28:59.867872 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2390 12:28:59.867969 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2391 12:28:59.868070 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2392 12:28:59.868169 # ok 661 Set SVE VL 2640
2393 12:28:59.868267 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2394 12:28:59.868364 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2395 12:28:59.868461 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2396 12:28:59.868546 # ok 665 Set SVE VL 2656
2397 12:28:59.868633 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2398 12:28:59.876417 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2399 12:28:59.877022 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2400 12:28:59.877223 # ok 669 Set SVE VL 2672
2401 12:28:59.877371 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2402 12:28:59.877559 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2403 12:28:59.877782 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2404 12:28:59.877974 # ok 673 Set SVE VL 2688
2405 12:28:59.878144 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2406 12:28:59.878352 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2407 12:28:59.878517 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2408 12:28:59.878641 # ok 677 Set SVE VL 2704
2409 12:28:59.878759 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2410 12:28:59.878896 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2411 12:28:59.879084 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2412 12:28:59.879290 # ok 681 Set SVE VL 2720
2413 12:28:59.879468 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2414 12:28:59.879630 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2415 12:28:59.879792 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2416 12:28:59.879955 # ok 685 Set SVE VL 2736
2417 12:28:59.880116 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2418 12:28:59.880282 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2419 12:28:59.880496 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2420 12:28:59.880659 # ok 689 Set SVE VL 2752
2421 12:28:59.880823 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2422 12:28:59.880989 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2423 12:28:59.881152 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2424 12:28:59.881316 # ok 693 Set SVE VL 2768
2425 12:28:59.881480 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2426 12:28:59.881642 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2427 12:28:59.881815 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2428 12:28:59.881981 # ok 697 Set SVE VL 2784
2429 12:28:59.882145 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2430 12:28:59.882308 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2431 12:28:59.882468 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2432 12:28:59.882620 # ok 701 Set SVE VL 2800
2433 12:28:59.882783 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2434 12:28:59.882948 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2435 12:28:59.883154 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2436 12:28:59.883329 # ok 705 Set SVE VL 2816
2437 12:28:59.883500 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2438 12:28:59.883668 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2439 12:28:59.883835 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2440 12:28:59.884001 # ok 709 Set SVE VL 2832
2441 12:28:59.884167 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2442 12:28:59.884334 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2443 12:28:59.884695 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2444 12:28:59.884815 # ok 713 Set SVE VL 2848
2445 12:28:59.884911 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2446 12:28:59.885000 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2447 12:28:59.885090 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2448 12:28:59.885177 # ok 717 Set SVE VL 2864
2449 12:28:59.885262 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2450 12:28:59.885347 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2451 12:28:59.885432 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2452 12:28:59.885517 # ok 721 Set SVE VL 2880
2453 12:28:59.885601 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2454 12:28:59.885850 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2455 12:28:59.885935 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2456 12:28:59.886010 # ok 725 Set SVE VL 2896
2457 12:28:59.886087 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2458 12:28:59.886161 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2459 12:28:59.886234 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2460 12:28:59.886307 # ok 729 Set SVE VL 2912
2461 12:28:59.886386 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2462 12:28:59.886585 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2463 12:28:59.886664 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2464 12:28:59.886736 # ok 733 Set SVE VL 2928
2465 12:28:59.886806 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2466 12:28:59.886878 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2467 12:28:59.886951 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2468 12:28:59.887024 # ok 737 Set SVE VL 2944
2469 12:28:59.887098 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2470 12:28:59.887171 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2471 12:28:59.887243 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2472 12:28:59.887318 # ok 741 Set SVE VL 2960
2473 12:28:59.887394 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2474 12:28:59.887473 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2475 12:28:59.887547 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2476 12:28:59.887618 # ok 745 Set SVE VL 2976
2477 12:28:59.887689 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2478 12:28:59.887763 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2479 12:28:59.887840 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2480 12:28:59.888271 # ok 749 Set SVE VL 2992
2481 12:28:59.888374 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2482 12:28:59.888461 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2483 12:28:59.888545 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2484 12:28:59.888633 # ok 753 Set SVE VL 3008
2485 12:28:59.888719 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2486 12:28:59.888804 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2487 12:28:59.889106 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2488 12:28:59.889219 # ok 757 Set SVE VL 3024
2489 12:28:59.889310 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2490 12:28:59.889397 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2491 12:28:59.889481 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2492 12:28:59.889565 # ok 761 Set SVE VL 3040
2493 12:28:59.889770 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2494 12:28:59.889852 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2495 12:28:59.889925 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2496 12:28:59.889996 # ok 765 Set SVE VL 3056
2497 12:28:59.890066 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2498 12:28:59.890136 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2499 12:28:59.890206 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2500 12:28:59.890275 # ok 769 Set SVE VL 3072
2501 12:28:59.890347 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2502 12:28:59.890422 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2503 12:28:59.890492 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2504 12:28:59.890563 # ok 773 Set SVE VL 3088
2505 12:28:59.890631 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2506 12:28:59.890702 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2507 12:28:59.890772 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2508 12:28:59.890842 # ok 777 Set SVE VL 3104
2509 12:28:59.890911 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2510 12:28:59.891258 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2511 12:28:59.891339 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2512 12:28:59.891411 # ok 781 Set SVE VL 3120
2513 12:28:59.891481 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2514 12:28:59.891550 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2515 12:28:59.891620 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2516 12:28:59.891690 # ok 785 Set SVE VL 3136
2517 12:28:59.891760 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2518 12:28:59.891831 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2519 12:28:59.891928 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2520 12:28:59.892012 # ok 789 Set SVE VL 3152
2521 12:28:59.892097 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2522 12:28:59.892183 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2523 12:28:59.892269 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2524 12:28:59.892356 # ok 793 Set SVE VL 3168
2525 12:28:59.892446 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2526 12:28:59.892531 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2527 12:28:59.892615 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2528 12:28:59.892699 # ok 797 Set SVE VL 3184
2529 12:28:59.892783 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2530 12:28:59.893247 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2531 12:28:59.893355 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2532 12:28:59.893443 # ok 801 Set SVE VL 3200
2533 12:28:59.893528 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2534 12:28:59.893613 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2535 12:28:59.893816 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2536 12:28:59.893895 # ok 805 Set SVE VL 3216
2537 12:28:59.893967 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2538 12:28:59.894039 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2539 12:28:59.894110 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2540 12:28:59.894180 # ok 809 Set SVE VL 3232
2541 12:28:59.894251 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2542 12:28:59.894322 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2543 12:28:59.894394 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2544 12:28:59.894464 # ok 813 Set SVE VL 3248
2545 12:28:59.894533 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2546 12:28:59.894604 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2547 12:28:59.894674 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2548 12:28:59.894744 # ok 817 Set SVE VL 3264
2549 12:28:59.895031 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2550 12:28:59.895137 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2551 12:28:59.895213 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2552 12:28:59.895282 # ok 821 Set SVE VL 3280
2553 12:28:59.895352 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2554 12:28:59.895429 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2555 12:28:59.895498 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2556 12:28:59.895568 # ok 825 Set SVE VL 3296
2557 12:28:59.895638 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2558 12:28:59.895708 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2559 12:28:59.895778 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2560 12:28:59.895851 # ok 829 Set SVE VL 3312
2561 12:28:59.895924 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2562 12:28:59.896017 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2563 12:28:59.896095 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2564 12:28:59.896168 # ok 833 Set SVE VL 3328
2565 12:28:59.896243 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2566 12:28:59.896316 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2567 12:28:59.896387 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2568 12:28:59.896461 # ok 837 Set SVE VL 3344
2569 12:28:59.896546 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2570 12:28:59.896620 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2571 12:28:59.896693 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2572 12:28:59.896765 # ok 841 Set SVE VL 3360
2573 12:28:59.896852 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2574 12:28:59.897395 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2575 12:28:59.897501 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2576 12:28:59.897589 # ok 845 Set SVE VL 3376
2577 12:28:59.897775 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2578 12:28:59.897855 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2579 12:28:59.897927 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2580 12:28:59.898005 # ok 849 Set SVE VL 3392
2581 12:28:59.898092 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2582 12:28:59.898167 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2583 12:28:59.898239 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2584 12:28:59.898309 # ok 853 Set SVE VL 3408
2585 12:28:59.898385 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2586 12:28:59.904939 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2587 12:28:59.905426 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2588 12:28:59.905534 # ok 857 Set SVE VL 3424
2589 12:28:59.905670 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2590 12:28:59.905763 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2591 12:28:59.905837 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2592 12:28:59.905925 # ok 861 Set SVE VL 3440
2593 12:28:59.905998 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2594 12:28:59.906070 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2595 12:28:59.906140 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2596 12:28:59.906211 # ok 865 Set SVE VL 3456
2597 12:28:59.906296 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2598 12:28:59.906369 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2599 12:28:59.906445 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2600 12:28:59.906528 # ok 869 Set SVE VL 3472
2601 12:28:59.906965 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2602 12:28:59.907252 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2603 12:28:59.907344 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2604 12:28:59.907420 # ok 873 Set SVE VL 3488
2605 12:28:59.907504 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2606 12:28:59.907575 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2607 12:28:59.907658 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2608 12:28:59.907740 # ok 877 Set SVE VL 3504
2609 12:28:59.907827 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2610 12:28:59.907917 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2611 12:28:59.908006 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2612 12:28:59.908094 # ok 881 Set SVE VL 3520
2613 12:28:59.908182 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2614 12:28:59.908469 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2615 12:28:59.908566 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2616 12:28:59.908656 # ok 885 Set SVE VL 3536
2617 12:28:59.908744 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2618 12:28:59.908841 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2619 12:28:59.909122 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2620 12:28:59.909220 # ok 889 Set SVE VL 3552
2621 12:28:59.909310 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2622 12:28:59.909397 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2623 12:28:59.909484 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2624 12:28:59.909769 # ok 893 Set SVE VL 3568
2625 12:28:59.909860 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2626 12:28:59.909946 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2627 12:28:59.910283 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2628 12:28:59.910416 # ok 897 Set SVE VL 3584
2629 12:28:59.910508 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2630 12:28:59.910759 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2631 12:28:59.910866 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2632 12:28:59.910941 # ok 901 Set SVE VL 3600
2633 12:28:59.911221 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2634 12:28:59.911310 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2635 12:28:59.911396 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2636 12:28:59.911471 # ok 905 Set SVE VL 3616
2637 12:28:59.911554 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2638 12:28:59.911638 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2639 12:28:59.911722 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2640 12:28:59.912034 # ok 909 Set SVE VL 3632
2641 12:28:59.912128 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2642 12:28:59.912213 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2643 12:28:59.912298 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2644 12:28:59.912370 # ok 913 Set SVE VL 3648
2645 12:28:59.912452 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2646 12:28:59.912794 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2647 12:28:59.912895 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2648 12:28:59.912976 # ok 917 Set SVE VL 3664
2649 12:28:59.913068 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2650 12:28:59.913141 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2651 12:28:59.913222 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2652 12:28:59.913294 # ok 921 Set SVE VL 3680
2653 12:28:59.913597 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2654 12:28:59.913749 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2655 12:28:59.913829 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2656 12:28:59.913918 # ok 925 Set SVE VL 3696
2657 12:28:59.913991 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2658 12:28:59.914075 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2659 12:28:59.914159 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2660 12:28:59.914246 # ok 929 Set SVE VL 3712
2661 12:28:59.914521 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2662 12:28:59.914952 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2663 12:28:59.915154 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2664 12:28:59.915240 # ok 933 Set SVE VL 3728
2665 12:28:59.915319 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2666 12:28:59.915381 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2667 12:28:59.915440 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2668 12:28:59.915498 # ok 937 Set SVE VL 3744
2669 12:28:59.915567 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2670 12:28:59.915627 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2671 12:28:59.915696 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2672 12:28:59.915767 # ok 941 Set SVE VL 3760
2673 12:28:59.915843 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2674 12:28:59.916111 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2675 12:28:59.916208 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2676 12:28:59.916306 # ok 945 Set SVE VL 3776
2677 12:28:59.916389 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2678 12:28:59.916482 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2679 12:28:59.916767 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2680 12:28:59.916874 # ok 949 Set SVE VL 3792
2681 12:28:59.916955 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2682 12:28:59.917055 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2683 12:28:59.917176 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2684 12:28:59.917311 # ok 953 Set SVE VL 3808
2685 12:28:59.917411 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2686 12:28:59.917547 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2687 12:28:59.917682 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2688 12:28:59.918023 # ok 957 Set SVE VL 3824
2689 12:28:59.918122 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2690 12:28:59.918206 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2691 12:28:59.918303 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2692 12:28:59.918385 # ok 961 Set SVE VL 3840
2693 12:28:59.918482 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2694 12:28:59.918575 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2695 12:28:59.918876 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2696 12:28:59.918996 # ok 965 Set SVE VL 3856
2697 12:28:59.919332 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2698 12:28:59.919441 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2699 12:28:59.919534 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2700 12:28:59.919622 # ok 969 Set SVE VL 3872
2701 12:28:59.919726 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2702 12:28:59.919817 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2703 12:28:59.919920 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2704 12:28:59.920008 # ok 973 Set SVE VL 3888
2705 12:28:59.920110 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2706 12:28:59.920199 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2707 12:28:59.920303 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2708 12:28:59.920411 # ok 977 Set SVE VL 3904
2709 12:28:59.920543 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2710 12:28:59.920870 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2711 12:28:59.920990 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2712 12:28:59.921324 # ok 981 Set SVE VL 3920
2713 12:28:59.921536 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2714 12:28:59.921992 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2715 12:28:59.922114 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2716 12:28:59.922210 # ok 985 Set SVE VL 3936
2717 12:28:59.922313 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2718 12:28:59.922400 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2719 12:28:59.922462 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2720 12:28:59.922529 # ok 989 Set SVE VL 3952
2721 12:28:59.924177 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2722 12:28:59.924270 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2723 12:28:59.924363 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2724 12:28:59.924441 # ok 993 Set SVE VL 3968
2725 12:28:59.924519 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2726 12:28:59.924596 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2727 12:28:59.924672 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2728 12:28:59.924751 # ok 997 Set SVE VL 3984
2729 12:28:59.924830 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2730 12:28:59.924915 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2731 12:28:59.925002 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2732 12:28:59.925098 # ok 1001 Set SVE VL 4000
2733 12:28:59.925183 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2734 12:28:59.925286 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2735 12:28:59.925392 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2736 12:28:59.925472 # ok 1005 Set SVE VL 4016
2737 12:28:59.925536 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2738 12:28:59.925620 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2739 12:28:59.925729 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2740 12:28:59.926011 # ok 1009 Set SVE VL 4032
2741 12:28:59.926107 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2742 12:28:59.926190 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2743 12:28:59.926305 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2744 12:28:59.926401 # ok 1013 Set SVE VL 4048
2745 12:28:59.926464 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2746 12:28:59.926523 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2747 12:28:59.926595 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2748 12:28:59.926655 # ok 1017 Set SVE VL 4064
2749 12:28:59.926716 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2750 12:28:59.926778 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2751 12:28:59.926837 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2752 12:28:59.926895 # ok 1021 Set SVE VL 4080
2753 12:28:59.926953 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2754 12:28:59.927020 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2755 12:28:59.927090 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2756 12:28:59.927155 # ok 1025 Set SVE VL 4096
2757 12:28:59.927238 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2758 12:28:59.927318 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2759 12:28:59.927388 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2760 12:28:59.927450 # ok 1029 Set SVE VL 4112
2761 12:28:59.927530 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2762 12:28:59.927619 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2763 12:28:59.927714 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2764 12:28:59.927793 # ok 1033 Set SVE VL 4128
2765 12:28:59.927872 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2766 12:28:59.927938 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2767 12:28:59.927998 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2768 12:28:59.928060 # ok 1037 Set SVE VL 4144
2769 12:28:59.928119 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2770 12:28:59.928178 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2771 12:28:59.928236 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2772 12:28:59.938554 # ok 1041 Set SVE VL 4160
2773 12:28:59.938828 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2774 12:28:59.938955 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2775 12:28:59.939099 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2776 12:28:59.939328 # ok 1045 Set SVE VL 4176
2777 12:28:59.939525 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2778 12:28:59.939723 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2779 12:28:59.939891 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2780 12:28:59.940059 # ok 1049 Set SVE VL 4192
2781 12:28:59.940256 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2782 12:28:59.940419 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2783 12:28:59.940591 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2784 12:28:59.940773 # ok 1053 Set SVE VL 4208
2785 12:28:59.941060 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2786 12:28:59.941297 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2787 12:28:59.941509 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2788 12:28:59.941822 # ok 1057 Set SVE VL 4224
2789 12:28:59.942029 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2790 12:28:59.942254 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2791 12:28:59.942499 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2792 12:28:59.942691 # ok 1061 Set SVE VL 4240
2793 12:28:59.942877 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2794 12:28:59.943084 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2795 12:28:59.943260 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2796 12:28:59.943460 # ok 1065 Set SVE VL 4256
2797 12:28:59.943637 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2798 12:28:59.943830 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2799 12:28:59.944022 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2800 12:28:59.944181 # ok 1069 Set SVE VL 4272
2801 12:28:59.944343 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2802 12:28:59.944502 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2803 12:28:59.944736 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2804 12:28:59.944953 # ok 1073 Set SVE VL 4288
2805 12:28:59.945157 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2806 12:28:59.945362 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2807 12:28:59.945571 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2808 12:28:59.945772 # ok 1077 Set SVE VL 4304
2809 12:28:59.945975 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2810 12:28:59.946183 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2811 12:28:59.946367 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2812 12:28:59.946559 # ok 1081 Set SVE VL 4320
2813 12:28:59.946760 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2814 12:28:59.946929 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2815 12:28:59.947343 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2816 12:28:59.947444 # ok 1085 Set SVE VL 4336
2817 12:28:59.947536 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2818 12:28:59.947633 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2819 12:28:59.947729 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2820 12:28:59.947814 # ok 1089 Set SVE VL 4352
2821 12:28:59.947896 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2822 12:28:59.947979 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2823 12:28:59.948060 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2824 12:28:59.948140 # ok 1093 Set SVE VL 4368
2825 12:28:59.948232 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2826 12:28:59.948334 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2827 12:28:59.948436 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2828 12:28:59.948538 # ok 1097 Set SVE VL 4384
2829 12:28:59.948641 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2830 12:28:59.948737 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2831 12:28:59.948831 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2832 12:28:59.948923 # ok 1101 Set SVE VL 4400
2833 12:28:59.949004 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2834 12:28:59.949073 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2835 12:28:59.949174 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2836 12:28:59.949260 # ok 1105 Set SVE VL 4416
2837 12:28:59.949338 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2838 12:28:59.949415 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2839 12:28:59.949500 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2840 12:28:59.949612 # ok 1109 Set SVE VL 4432
2841 12:28:59.949718 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2842 12:28:59.949798 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2843 12:28:59.949890 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2844 12:28:59.950010 # ok 1113 Set SVE VL 4448
2845 12:28:59.950117 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2846 12:28:59.950218 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2847 12:28:59.950313 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2848 12:28:59.950416 # ok 1117 Set SVE VL 4464
2849 12:28:59.950500 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2850 12:28:59.950568 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2851 12:28:59.950627 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2852 12:28:59.950709 # ok 1121 Set SVE VL 4480
2853 12:28:59.950811 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2854 12:28:59.950916 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2855 12:28:59.951006 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2856 12:28:59.951082 # ok 1125 Set SVE VL 4496
2857 12:28:59.951157 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2858 12:28:59.951456 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2859 12:28:59.951550 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2860 12:28:59.951622 # ok 1129 Set SVE VL 4512
2861 12:28:59.951682 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2862 12:28:59.951754 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2863 12:28:59.951825 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2864 12:28:59.951889 # ok 1133 Set SVE VL 4528
2865 12:28:59.952005 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2866 12:28:59.952102 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2867 12:28:59.952176 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2868 12:28:59.952262 # ok 1137 Set SVE VL 4544
2869 12:28:59.952365 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2870 12:28:59.952473 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2871 12:28:59.952594 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2872 12:28:59.952685 # ok 1141 Set SVE VL 4560
2873 12:28:59.952785 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2874 12:28:59.952890 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2875 12:28:59.952993 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2876 12:28:59.953100 # ok 1145 Set SVE VL 4576
2877 12:28:59.953206 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2878 12:28:59.953326 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2879 12:28:59.953416 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2880 12:28:59.953497 # ok 1149 Set SVE VL 4592
2881 12:28:59.953579 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2882 12:28:59.953685 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2883 12:28:59.953770 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2884 12:28:59.953850 # ok 1153 Set SVE VL 4608
2885 12:28:59.953929 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2886 12:28:59.954001 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2887 12:28:59.954075 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2888 12:28:59.954152 # ok 1157 Set SVE VL 4624
2889 12:28:59.954223 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2890 12:28:59.954290 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2891 12:28:59.954365 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2892 12:28:59.954437 # ok 1161 Set SVE VL 4640
2893 12:28:59.954504 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2894 12:28:59.954591 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2895 12:28:59.954689 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2896 12:28:59.954794 # ok 1165 Set SVE VL 4656
2897 12:28:59.954898 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2898 12:28:59.954998 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2899 12:28:59.955098 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2900 12:28:59.955193 # ok 1169 Set SVE VL 4672
2901 12:28:59.955581 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2902 12:28:59.955794 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2903 12:28:59.956009 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2904 12:28:59.956229 # ok 1173 Set SVE VL 4688
2905 12:28:59.956411 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2906 12:28:59.956603 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2907 12:28:59.956826 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2908 12:28:59.957012 # ok 1177 Set SVE VL 4704
2909 12:28:59.957183 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2910 12:28:59.957365 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2911 12:28:59.957622 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2912 12:28:59.957838 # ok 1181 Set SVE VL 4720
2913 12:28:59.958035 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2914 12:28:59.958201 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2915 12:28:59.958394 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2916 12:28:59.958523 # ok 1185 Set SVE VL 4736
2917 12:28:59.958629 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2918 12:28:59.958786 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2919 12:28:59.958917 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2920 12:28:59.959047 # ok 1189 Set SVE VL 4752
2921 12:28:59.959202 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2922 12:28:59.959354 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2923 12:28:59.959524 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2924 12:28:59.959690 # ok 1193 Set SVE VL 4768
2925 12:28:59.959826 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2926 12:28:59.959938 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2927 12:28:59.960049 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2928 12:28:59.960174 # ok 1197 Set SVE VL 4784
2929 12:28:59.960300 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2930 12:28:59.960432 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2931 12:28:59.960583 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2932 12:28:59.960680 # ok 1201 Set SVE VL 4800
2933 12:28:59.960768 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2934 12:28:59.960856 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2935 12:28:59.960944 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2936 12:28:59.961031 # ok 1205 Set SVE VL 4816
2937 12:28:59.961118 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2938 12:28:59.961205 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2939 12:28:59.961293 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2940 12:28:59.961380 # ok 1209 Set SVE VL 4832
2941 12:28:59.961467 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2942 12:28:59.961554 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2943 12:28:59.961865 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2944 12:28:59.961963 # ok 1213 Set SVE VL 4848
2945 12:28:59.962049 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2946 12:28:59.962134 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2947 12:28:59.962219 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2948 12:28:59.962305 # ok 1217 Set SVE VL 4864
2949 12:28:59.962390 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2950 12:28:59.962475 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2951 12:28:59.962541 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2952 12:28:59.962599 # ok 1221 Set SVE VL 4880
2953 12:28:59.962656 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2954 12:28:59.962713 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2955 12:28:59.976331 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2956 12:28:59.976619 # ok 1225 Set SVE VL 4896
2957 12:28:59.976768 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2958 12:28:59.976937 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2959 12:28:59.977102 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2960 12:28:59.977273 # ok 1229 Set SVE VL 4912
2961 12:28:59.977430 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2962 12:28:59.977589 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2963 12:28:59.977785 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2964 12:28:59.977950 # ok 1233 Set SVE VL 4928
2965 12:28:59.978115 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2966 12:28:59.978285 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2967 12:28:59.978415 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2968 12:28:59.978512 # ok 1237 Set SVE VL 4944
2969 12:28:59.978604 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2970 12:28:59.978711 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2971 12:28:59.978802 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2972 12:28:59.978887 # ok 1241 Set SVE VL 4960
2973 12:28:59.978971 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2974 12:28:59.979056 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2975 12:28:59.981467 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2976 12:28:59.981865 # ok 1245 Set SVE VL 4976
2977 12:28:59.981980 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2978 12:28:59.982078 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2979 12:28:59.982191 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2980 12:28:59.982329 # ok 1249 Set SVE VL 4992
2981 12:28:59.982420 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2982 12:28:59.982508 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2983 12:28:59.983530 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2984 12:28:59.983680 # ok 1253 Set SVE VL 5008
2985 12:28:59.984013 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2986 12:28:59.984149 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2987 12:28:59.984267 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2988 12:28:59.984428 # ok 1257 Set SVE VL 5024
2989 12:28:59.984598 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2990 12:28:59.984743 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2991 12:28:59.984911 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2992 12:28:59.985087 # ok 1261 Set SVE VL 5040
2993 12:28:59.985193 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2994 12:28:59.985282 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2995 12:28:59.985370 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2996 12:28:59.985458 # ok 1265 Set SVE VL 5056
2997 12:28:59.985817 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2998 12:28:59.985997 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2999 12:28:59.986134 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
3000 12:28:59.986256 # ok 1269 Set SVE VL 5072
3001 12:28:59.986374 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
3002 12:28:59.986512 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
3003 12:28:59.986636 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3004 12:28:59.987011 # ok 1273 Set SVE VL 5088
3005 12:28:59.987160 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3006 12:28:59.987287 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3007 12:28:59.987412 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3008 12:28:59.987540 # ok 1277 Set SVE VL 5104
3009 12:28:59.987742 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3010 12:28:59.987883 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3011 12:28:59.988013 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3012 12:28:59.988139 # ok 1281 Set SVE VL 5120
3013 12:28:59.988288 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3014 12:28:59.988419 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3015 12:28:59.988573 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3016 12:28:59.988705 # ok 1285 Set SVE VL 5136
3017 12:28:59.988855 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3018 12:28:59.989008 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3019 12:28:59.989161 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3020 12:28:59.989317 # ok 1289 Set SVE VL 5152
3021 12:28:59.989480 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3022 12:28:59.989852 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3023 12:28:59.989971 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3024 12:28:59.990072 # ok 1293 Set SVE VL 5168
3025 12:28:59.990160 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3026 12:28:59.990621 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3027 12:28:59.990732 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3028 12:28:59.990803 # ok 1297 Set SVE VL 5184
3029 12:28:59.990892 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3030 12:28:59.991176 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3031 12:28:59.991275 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3032 12:28:59.991382 # ok 1301 Set SVE VL 5200
3033 12:28:59.991465 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3034 12:28:59.991571 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3035 12:28:59.991678 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3036 12:28:59.991762 # ok 1305 Set SVE VL 5216
3037 12:28:59.991854 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3038 12:28:59.991935 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3039 12:28:59.992026 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3040 12:28:59.992311 # ok 1309 Set SVE VL 5232
3041 12:28:59.992403 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3042 12:28:59.992495 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3043 12:28:59.992614 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3044 12:28:59.992707 # ok 1313 Set SVE VL 5248
3045 12:28:59.992808 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3046 12:28:59.992922 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3047 12:28:59.993012 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3048 12:28:59.993112 # ok 1317 Set SVE VL 5264
3049 12:28:59.993208 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3050 12:28:59.993314 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3051 12:28:59.993418 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3052 12:28:59.993521 # ok 1321 Set SVE VL 5280
3053 12:28:59.993672 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3054 12:28:59.993781 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3055 12:28:59.993865 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3056 12:28:59.993963 # ok 1325 Set SVE VL 5296
3057 12:28:59.994053 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3058 12:28:59.994331 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3059 12:28:59.994410 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3060 12:28:59.994505 # ok 1329 Set SVE VL 5312
3061 12:28:59.994788 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3062 12:28:59.994890 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3063 12:28:59.995007 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3064 12:28:59.995102 # ok 1333 Set SVE VL 5328
3065 12:28:59.995203 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3066 12:28:59.995309 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3067 12:28:59.995429 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3068 12:28:59.995547 # ok 1337 Set SVE VL 5344
3069 12:28:59.995661 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3070 12:28:59.995773 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3071 12:28:59.995891 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3072 12:28:59.996070 # ok 1341 Set SVE VL 5360
3073 12:28:59.996191 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3074 12:28:59.996284 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3075 12:28:59.996579 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3076 12:28:59.996679 # ok 1345 Set SVE VL 5376
3077 12:28:59.996762 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3078 12:28:59.996855 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3079 12:28:59.997765 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3080 12:28:59.997879 # ok 1349 Set SVE VL 5392
3081 12:28:59.997971 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3082 12:28:59.998080 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3083 12:28:59.998167 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3084 12:28:59.998280 # ok 1353 Set SVE VL 5408
3085 12:28:59.998377 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3086 12:28:59.998475 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3087 12:28:59.998634 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3088 12:28:59.998821 # ok 1357 Set SVE VL 5424
3089 12:28:59.998998 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3090 12:28:59.999180 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3091 12:28:59.999592 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3092 12:28:59.999782 # ok 1361 Set SVE VL 5440
3093 12:28:59.999948 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3094 12:29:00.000091 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3095 12:29:00.000246 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3096 12:29:00.000430 # ok 1365 Set SVE VL 5456
3097 12:29:00.000623 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3098 12:29:00.000791 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3099 12:29:00.000932 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3100 12:29:00.001125 # ok 1369 Set SVE VL 5472
3101 12:29:00.001299 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3102 12:29:00.001448 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3103 12:29:00.001620 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3104 12:29:00.001811 # ok 1373 Set SVE VL 5488
3105 12:29:00.001946 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3106 12:29:00.002071 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3107 12:29:00.002195 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3108 12:29:00.002317 # ok 1377 Set SVE VL 5504
3109 12:29:00.002420 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3110 12:29:00.002527 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3111 12:29:00.002611 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3112 12:29:00.002719 # ok 1381 Set SVE VL 5520
3113 12:29:00.002812 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3114 12:29:00.002895 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3115 12:29:00.002981 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3116 12:29:00.003065 # ok 1385 Set SVE VL 5536
3117 12:29:00.003150 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3118 12:29:00.003254 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3119 12:29:00.003347 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3120 12:29:00.003469 # ok 1389 Set SVE VL 5552
3121 12:29:00.003582 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3122 12:29:00.003693 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3123 12:29:00.003788 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3124 12:29:00.003879 # ok 1393 Set SVE VL 5568
3125 12:29:00.003949 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3126 12:29:00.004010 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3127 12:29:00.004072 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3128 12:29:00.004149 # ok 1397 Set SVE VL 5584
3129 12:29:00.004214 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3130 12:29:00.004274 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3131 12:29:00.004333 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3132 12:29:00.004393 # ok 1401 Set SVE VL 5600
3133 12:29:00.004653 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3134 12:29:00.004721 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3135 12:29:00.004783 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3136 12:29:00.004843 # ok 1405 Set SVE VL 5616
3137 12:29:00.004903 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3138 12:29:00.040415 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3139 12:29:00.040857 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3140 12:29:00.040964 # ok 1409 Set SVE VL 5632
3141 12:29:00.041067 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3142 12:29:00.041176 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3143 12:29:00.041281 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3144 12:29:00.041371 # ok 1413 Set SVE VL 5648
3145 12:29:00.041472 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3146 12:29:00.041587 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3147 12:29:00.041680 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3148 12:29:00.041758 # ok 1417 Set SVE VL 5664
3149 12:29:00.041853 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3150 12:29:00.041942 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3151 12:29:00.042055 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3152 12:29:00.042149 # ok 1421 Set SVE VL 5680
3153 12:29:00.042279 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3154 12:29:00.045283 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3155 12:29:00.045717 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3156 12:29:00.045821 # ok 1425 Set SVE VL 5696
3157 12:29:00.045914 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3158 12:29:00.046209 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3159 12:29:00.046315 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3160 12:29:00.046405 # ok 1429 Set SVE VL 5712
3161 12:29:00.046493 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3162 12:29:00.046580 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3163 12:29:00.046683 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3164 12:29:00.046773 # ok 1433 Set SVE VL 5728
3165 12:29:00.048040 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3166 12:29:00.048149 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3167 12:29:00.048241 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3168 12:29:00.048331 # ok 1437 Set SVE VL 5744
3169 12:29:00.048618 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3170 12:29:00.048724 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3171 12:29:00.048827 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3172 12:29:00.048927 # ok 1441 Set SVE VL 5760
3173 12:29:00.049011 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3174 12:29:00.049120 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3175 12:29:00.049216 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3176 12:29:00.049320 # ok 1445 Set SVE VL 5776
3177 12:29:00.049434 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3178 12:29:00.049515 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3179 12:29:00.049596 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3180 12:29:00.049676 # ok 1449 Set SVE VL 5792
3181 12:29:00.049757 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3182 12:29:00.050029 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3183 12:29:00.050129 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3184 12:29:00.050227 # ok 1453 Set SVE VL 5808
3185 12:29:00.050308 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3186 12:29:00.051344 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3187 12:29:00.051683 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3188 12:29:00.051862 # ok 1457 Set SVE VL 5824
3189 12:29:00.052045 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3190 12:29:00.052229 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3191 12:29:00.052380 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3192 12:29:00.052530 # ok 1461 Set SVE VL 5840
3193 12:29:00.052658 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3194 12:29:00.052828 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3195 12:29:00.052987 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3196 12:29:00.053159 # ok 1465 Set SVE VL 5856
3197 12:29:00.053319 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3198 12:29:00.053452 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3199 12:29:00.053622 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3200 12:29:00.053833 # ok 1469 Set SVE VL 5872
3201 12:29:00.054038 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3202 12:29:00.054207 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3203 12:29:00.054336 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3204 12:29:00.054453 # ok 1473 Set SVE VL 5888
3205 12:29:00.054568 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3206 12:29:00.054684 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3207 12:29:00.054800 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3208 12:29:00.054915 # ok 1477 Set SVE VL 5904
3209 12:29:00.055030 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3210 12:29:00.055172 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3211 12:29:00.055672 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3212 12:29:00.055877 # ok 1481 Set SVE VL 5920
3213 12:29:00.056133 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3214 12:29:00.056346 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3215 12:29:00.056498 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3216 12:29:00.056633 # ok 1485 Set SVE VL 5936
3217 12:29:00.056848 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3218 12:29:00.057083 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3219 12:29:00.057267 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3220 12:29:00.057429 # ok 1489 Set SVE VL 5952
3221 12:29:00.057595 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3222 12:29:00.057766 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3223 12:29:00.057924 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3224 12:29:00.058074 # ok 1493 Set SVE VL 5968
3225 12:29:00.058214 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3226 12:29:00.058370 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3227 12:29:00.058493 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3228 12:29:00.058609 # ok 1497 Set SVE VL 5984
3229 12:29:00.058723 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3230 12:29:00.058839 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3231 12:29:00.058953 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3232 12:29:00.059067 # ok 1501 Set SVE VL 6000
3233 12:29:00.059183 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3234 12:29:00.059308 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3235 12:29:00.059425 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3236 12:29:00.059610 # ok 1505 Set SVE VL 6016
3237 12:29:00.059816 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3238 12:29:00.059988 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3239 12:29:00.060149 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3240 12:29:00.060336 # ok 1509 Set SVE VL 6032
3241 12:29:00.060479 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3242 12:29:00.060655 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3243 12:29:00.060816 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3244 12:29:00.060963 # ok 1513 Set SVE VL 6048
3245 12:29:00.061122 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3246 12:29:00.061282 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3247 12:29:00.061441 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3248 12:29:00.061600 # ok 1517 Set SVE VL 6064
3249 12:29:00.061833 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3250 12:29:00.062068 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3251 12:29:00.062259 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3252 12:29:00.062445 # ok 1521 Set SVE VL 6080
3253 12:29:00.062631 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3254 12:29:00.063073 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3255 12:29:00.063275 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3256 12:29:00.063454 # ok 1525 Set SVE VL 6096
3257 12:29:00.063616 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3258 12:29:00.063749 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3259 12:29:00.063875 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3260 12:29:00.064004 # ok 1529 Set SVE VL 6112
3261 12:29:00.064123 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3262 12:29:00.064255 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3263 12:29:00.064394 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3264 12:29:00.064562 # ok 1533 Set SVE VL 6128
3265 12:29:00.064693 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3266 12:29:00.064857 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3267 12:29:00.065021 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3268 12:29:00.065173 # ok 1537 Set SVE VL 6144
3269 12:29:00.065321 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3270 12:29:00.065460 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3271 12:29:00.065592 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3272 12:29:00.065742 # ok 1541 Set SVE VL 6160
3273 12:29:00.065864 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3274 12:29:00.065992 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3275 12:29:00.066112 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3276 12:29:00.066254 # ok 1545 Set SVE VL 6176
3277 12:29:00.066355 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3278 12:29:00.066473 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3279 12:29:00.066566 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3280 12:29:00.066642 # ok 1549 Set SVE VL 6192
3281 12:29:00.066702 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3282 12:29:00.066765 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3283 12:29:00.066843 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3284 12:29:00.066923 # ok 1553 Set SVE VL 6208
3285 12:29:00.067000 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3286 12:29:00.067073 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3287 12:29:00.067168 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3288 12:29:00.067244 # ok 1557 Set SVE VL 6224
3289 12:29:00.067313 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3290 12:29:00.067390 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3291 12:29:00.067476 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3292 12:29:00.067555 # ok 1561 Set SVE VL 6240
3293 12:29:00.067646 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3294 12:29:00.067767 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3295 12:29:00.067873 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3296 12:29:00.067965 # ok 1565 Set SVE VL 6256
3297 12:29:00.068300 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3298 12:29:00.068415 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3299 12:29:00.068525 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3300 12:29:00.068625 # ok 1569 Set SVE VL 6272
3301 12:29:00.068735 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3302 12:29:00.068841 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3303 12:29:00.068937 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3304 12:29:00.069044 # ok 1573 Set SVE VL 6288
3305 12:29:00.069140 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3306 12:29:00.069231 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3307 12:29:00.069320 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3308 12:29:00.069432 # ok 1577 Set SVE VL 6304
3309 12:29:00.069535 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3310 12:29:00.069621 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3311 12:29:00.069720 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3312 12:29:00.069787 # ok 1581 Set SVE VL 6320
3313 12:29:00.069848 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3314 12:29:00.069911 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3315 12:29:00.069973 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3316 12:29:00.070034 # ok 1585 Set SVE VL 6336
3317 12:29:00.070095 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3318 12:29:00.070155 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3319 12:29:00.070231 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3320 12:29:00.070296 # ok 1589 Set SVE VL 6352
3321 12:29:00.072950 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3322 12:29:00.073208 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3323 12:29:00.073304 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3324 12:29:00.073412 # ok 1593 Set SVE VL 6368
3325 12:29:00.073505 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3326 12:29:00.073593 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3327 12:29:00.073696 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3328 12:29:00.073802 # ok 1597 Set SVE VL 6384
3329 12:29:00.073896 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3330 12:29:00.074002 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3331 12:29:00.074091 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3332 12:29:00.074191 # ok 1601 Set SVE VL 6400
3333 12:29:00.074818 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3334 12:29:00.075126 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3335 12:29:00.075233 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3336 12:29:00.075323 # ok 1605 Set SVE VL 6416
3337 12:29:00.075427 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3338 12:29:00.075516 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3339 12:29:00.075618 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3340 12:29:00.075708 # ok 1609 Set SVE VL 6432
3341 12:29:00.075794 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3342 12:29:00.075895 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3343 12:29:00.075996 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3344 12:29:00.076083 # ok 1613 Set SVE VL 6448
3345 12:29:00.076184 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3346 12:29:00.076271 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3347 12:29:00.076373 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3348 12:29:00.076461 # ok 1617 Set SVE VL 6464
3349 12:29:00.076561 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3350 12:29:00.076648 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3351 12:29:00.076748 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3352 12:29:00.076835 # ok 1621 Set SVE VL 6480
3353 12:29:00.076920 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3354 12:29:00.077020 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3355 12:29:00.077123 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3356 12:29:00.077210 # ok 1625 Set SVE VL 6496
3357 12:29:00.077295 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3358 12:29:00.077395 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3359 12:29:00.077482 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3360 12:29:00.077567 # ok 1629 Set SVE VL 6512
3361 12:29:00.077676 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3362 12:29:00.077755 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3363 12:29:00.077840 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3364 12:29:00.077913 # ok 1633 Set SVE VL 6528
3365 12:29:00.078205 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3366 12:29:00.078389 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3367 12:29:00.078597 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3368 12:29:00.078775 # ok 1637 Set SVE VL 6544
3369 12:29:00.078942 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3370 12:29:00.079139 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3371 12:29:00.079306 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3372 12:29:00.079455 # ok 1641 Set SVE VL 6560
3373 12:29:00.079605 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3374 12:29:00.079737 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3375 12:29:00.079848 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3376 12:29:00.079957 # ok 1645 Set SVE VL 6576
3377 12:29:00.080055 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3378 12:29:00.080143 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3379 12:29:00.080233 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3380 12:29:00.080343 # ok 1649 Set SVE VL 6592
3381 12:29:00.080469 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3382 12:29:00.080583 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3383 12:29:00.080684 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3384 12:29:00.080790 # ok 1653 Set SVE VL 6608
3385 12:29:00.080888 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3386 12:29:00.080993 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3387 12:29:00.081096 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3388 12:29:00.081234 # ok 1657 Set SVE VL 6624
3389 12:29:00.081346 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3390 12:29:00.081465 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3391 12:29:00.081583 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3392 12:29:00.082244 # ok 1661 Set SVE VL 6640
3393 12:29:00.082358 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3394 12:29:00.082448 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3395 12:29:00.082546 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3396 12:29:00.082672 # ok 1665 Set SVE VL 6656
3397 12:29:00.082781 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3398 12:29:00.082867 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3399 12:29:00.082953 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3400 12:29:00.083039 # ok 1669 Set SVE VL 6672
3401 12:29:00.083123 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3402 12:29:00.083200 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3403 12:29:00.083265 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3404 12:29:00.083330 # ok 1673 Set SVE VL 6688
3405 12:29:00.083405 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3406 12:29:00.083473 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3407 12:29:00.083554 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3408 12:29:00.083882 # ok 1677 Set SVE VL 6704
3409 12:29:00.083984 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3410 12:29:00.084064 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3411 12:29:00.084147 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3412 12:29:00.084246 # ok 1681 Set SVE VL 6720
3413 12:29:00.084333 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3414 12:29:00.084417 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3415 12:29:00.084499 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3416 12:29:00.084583 # ok 1685 Set SVE VL 6736
3417 12:29:00.084688 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3418 12:29:00.084772 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3419 12:29:00.084859 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3420 12:29:00.084943 # ok 1689 Set SVE VL 6752
3421 12:29:00.085023 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3422 12:29:00.085131 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3423 12:29:00.085225 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3424 12:29:00.085325 # ok 1693 Set SVE VL 6768
3425 12:29:00.085410 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3426 12:29:00.085492 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3427 12:29:00.085574 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3428 12:29:00.085661 # ok 1697 Set SVE VL 6784
3429 12:29:00.085758 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3430 12:29:00.085842 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3431 12:29:00.085938 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3432 12:29:00.086023 # ok 1701 Set SVE VL 6800
3433 12:29:00.086118 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3434 12:29:00.086569 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3435 12:29:00.086670 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3436 12:29:00.086750 # ok 1705 Set SVE VL 6816
3437 12:29:00.086847 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3438 12:29:00.086929 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3439 12:29:00.087034 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3440 12:29:00.087141 # ok 1709 Set SVE VL 6832
3441 12:29:00.087248 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3442 12:29:00.087329 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3443 12:29:00.087436 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3444 12:29:00.087537 # ok 1713 Set SVE VL 6848
3445 12:29:00.087676 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3446 12:29:00.087794 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3447 12:29:00.087906 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3448 12:29:00.087991 # ok 1717 Set SVE VL 6864
3449 12:29:00.088074 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3450 12:29:00.088158 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3451 12:29:00.088253 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3452 12:29:00.088640 # ok 1721 Set SVE VL 6880
3453 12:29:00.088738 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3454 12:29:00.088812 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3455 12:29:00.088904 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3456 12:29:00.088975 # ok 1725 Set SVE VL 6896
3457 12:29:00.089059 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3458 12:29:00.089139 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3459 12:29:00.089204 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3460 12:29:00.089297 # ok 1729 Set SVE VL 6912
3461 12:29:00.089391 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3462 12:29:00.089490 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3463 12:29:00.089797 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3464 12:29:00.089892 # ok 1733 Set SVE VL 6928
3465 12:29:00.089986 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3466 12:29:00.090073 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3467 12:29:00.090163 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3468 12:29:00.090249 # ok 1737 Set SVE VL 6944
3469 12:29:00.090527 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3470 12:29:00.090621 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3471 12:29:00.090908 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3472 12:29:00.091006 # ok 1741 Set SVE VL 6960
3473 12:29:00.091100 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3474 12:29:00.091193 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3475 12:29:00.091285 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3476 12:29:00.091571 # ok 1745 Set SVE VL 6976
3477 12:29:00.091672 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3478 12:29:00.091794 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3479 12:29:00.091906 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3480 12:29:00.092038 # ok 1749 Set SVE VL 6992
3481 12:29:00.092175 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3482 12:29:00.092282 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3483 12:29:00.092415 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3484 12:29:00.092541 # ok 1753 Set SVE VL 7008
3485 12:29:00.092644 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3486 12:29:00.092784 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3487 12:29:00.092879 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3488 12:29:00.092960 # ok 1757 Set SVE VL 7024
3489 12:29:00.093053 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3490 12:29:00.093133 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3491 12:29:00.093206 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3492 12:29:00.093283 # ok 1761 Set SVE VL 7040
3493 12:29:00.093375 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3494 12:29:00.093456 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3495 12:29:00.093550 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3496 12:29:00.093658 # ok 1765 Set SVE VL 7056
3497 12:29:00.093781 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3498 12:29:00.093883 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3499 12:29:00.093993 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3500 12:29:00.094100 # ok 1769 Set SVE VL 7072
3501 12:29:00.094186 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3502 12:29:00.094252 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3503 12:29:00.094319 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3504 12:29:00.096624 # ok 1773 Set SVE VL 7088
3505 12:29:00.096999 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3506 12:29:00.097107 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3507 12:29:00.097202 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3508 12:29:00.097279 # ok 1777 Set SVE VL 7104
3509 12:29:00.097349 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3510 12:29:00.097433 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3511 12:29:00.097518 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3512 12:29:00.097656 # ok 1781 Set SVE VL 7120
3513 12:29:00.097751 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3514 12:29:00.097840 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3515 12:29:00.097914 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3516 12:29:00.097999 # ok 1785 Set SVE VL 7136
3517 12:29:00.098083 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3518 12:29:00.098298 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3519 12:29:00.098391 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3520 12:29:00.098477 # ok 1789 Set SVE VL 7152
3521 12:29:00.098550 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3522 12:29:00.098632 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3523 12:29:00.098915 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3524 12:29:00.099007 # ok 1793 Set SVE VL 7168
3525 12:29:00.099091 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3526 12:29:00.099177 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3527 12:29:00.099277 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3528 12:29:00.099955 # ok 1797 Set SVE VL 7184
3529 12:29:00.100242 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3530 12:29:00.100337 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3531 12:29:00.100428 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3532 12:29:00.100506 # ok 1801 Set SVE VL 7200
3533 12:29:00.100594 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3534 12:29:00.100675 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3535 12:29:00.100768 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3536 12:29:00.100856 # ok 1805 Set SVE VL 7216
3537 12:29:00.100942 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3538 12:29:00.101039 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3539 12:29:00.101361 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3540 12:29:00.101547 # ok 1809 Set SVE VL 7232
3541 12:29:00.101747 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3542 12:29:00.101973 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3543 12:29:00.102165 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3544 12:29:00.102341 # ok 1813 Set SVE VL 7248
3545 12:29:00.102550 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3546 12:29:00.102718 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3547 12:29:00.102821 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3548 12:29:00.102954 # ok 1817 Set SVE VL 7264
3549 12:29:00.103079 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3550 12:29:00.103202 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3551 12:29:00.103321 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3552 12:29:00.103451 # ok 1821 Set SVE VL 7280
3553 12:29:00.103612 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3554 12:29:00.103739 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3555 12:29:00.103853 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3556 12:29:00.103962 # ok 1825 Set SVE VL 7296
3557 12:29:00.104088 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3558 12:29:00.104197 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3559 12:29:00.104303 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3560 12:29:00.104414 # ok 1829 Set SVE VL 7312
3561 12:29:00.104533 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3562 12:29:00.104625 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3563 12:29:00.104775 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3564 12:29:00.104898 # ok 1833 Set SVE VL 7328
3565 12:29:00.105022 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3566 12:29:00.105135 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3567 12:29:00.105252 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3568 12:29:00.105367 # ok 1837 Set SVE VL 7344
3569 12:29:00.105481 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3570 12:29:00.105602 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3571 12:29:00.106386 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3572 12:29:00.106556 # ok 1841 Set SVE VL 7360
3573 12:29:00.106680 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3574 12:29:00.106757 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3575 12:29:00.106841 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3576 12:29:00.106943 # ok 1845 Set SVE VL 7376
3577 12:29:00.107033 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3578 12:29:00.107113 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3579 12:29:00.107188 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3580 12:29:00.107265 # ok 1849 Set SVE VL 7392
3581 12:29:00.107330 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3582 12:29:00.107643 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3583 12:29:00.107740 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3584 12:29:00.107851 # ok 1853 Set SVE VL 7408
3585 12:29:00.107943 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3586 12:29:00.108037 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3587 12:29:00.108145 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3588 12:29:00.108239 # ok 1857 Set SVE VL 7424
3589 12:29:00.108326 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3590 12:29:00.108414 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3591 12:29:00.108495 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3592 12:29:00.108591 # ok 1861 Set SVE VL 7440
3593 12:29:00.108701 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3594 12:29:00.108812 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3595 12:29:00.108939 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3596 12:29:00.109033 # ok 1865 Set SVE VL 7456
3597 12:29:00.109147 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3598 12:29:00.109245 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3599 12:29:00.109317 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3600 12:29:00.109378 # ok 1869 Set SVE VL 7472
3601 12:29:00.109437 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3602 12:29:00.109497 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3603 12:29:00.109556 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3604 12:29:00.109614 # ok 1873 Set SVE VL 7488
3605 12:29:00.109705 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3606 12:29:00.109787 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3607 12:29:00.109851 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3608 12:29:00.109911 # ok 1877 Set SVE VL 7504
3609 12:29:00.109970 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3610 12:29:00.110029 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3611 12:29:00.110088 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3612 12:29:00.110158 # ok 1881 Set SVE VL 7520
3613 12:29:00.110219 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3614 12:29:00.110293 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3615 12:29:00.110555 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3616 12:29:00.110634 # ok 1885 Set SVE VL 7536
3617 12:29:00.110708 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3618 12:29:00.110780 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3619 12:29:00.110852 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3620 12:29:00.110923 # ok 1889 Set SVE VL 7552
3621 12:29:00.111173 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3622 12:29:00.111249 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3623 12:29:00.111494 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3624 12:29:00.111560 # ok 1893 Set SVE VL 7568
3625 12:29:00.111632 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3626 12:29:00.111720 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3627 12:29:00.111814 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3628 12:29:00.112083 # ok 1897 Set SVE VL 7584
3629 12:29:00.112175 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3630 12:29:00.112266 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3631 12:29:00.112342 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3632 12:29:00.112422 # ok 1901 Set SVE VL 7600
3633 12:29:00.112497 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3634 12:29:00.112781 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3635 12:29:00.112892 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3636 12:29:00.112975 # ok 1905 Set SVE VL 7616
3637 12:29:00.113061 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3638 12:29:00.113162 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3639 12:29:00.113269 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3640 12:29:00.113372 # ok 1909 Set SVE VL 7632
3641 12:29:00.113681 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3642 12:29:00.113786 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3643 12:29:00.114071 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3644 12:29:00.114158 # ok 1913 Set SVE VL 7648
3645 12:29:00.114240 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3646 12:29:00.114503 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3647 12:29:00.114616 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3648 12:29:00.114697 # ok 1917 Set SVE VL 7664
3649 12:29:00.114994 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3650 12:29:00.115093 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3651 12:29:00.115213 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3652 12:29:00.115287 # ok 1921 Set SVE VL 7680
3653 12:29:00.115368 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3654 12:29:00.115646 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3655 12:29:00.115738 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3656 12:29:00.115808 # ok 1925 Set SVE VL 7696
3657 12:29:00.115882 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3658 12:29:00.115954 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3659 12:29:00.116046 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3660 12:29:00.116127 # ok 1929 Set SVE VL 7712
3661 12:29:00.116216 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3662 12:29:00.116485 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3663 12:29:00.116580 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3664 12:29:00.116658 # ok 1933 Set SVE VL 7728
3665 12:29:00.116749 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3666 12:29:00.116842 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3667 12:29:00.117146 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3668 12:29:00.117244 # ok 1937 Set SVE VL 7744
3669 12:29:00.117327 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3670 12:29:00.117402 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3671 12:29:00.117474 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3672 12:29:00.117546 # ok 1941 Set SVE VL 7760
3673 12:29:00.117621 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3674 12:29:00.117731 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3675 12:29:00.117813 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3676 12:29:00.117876 # ok 1945 Set SVE VL 7776
3677 12:29:00.117947 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3678 12:29:00.118230 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3679 12:29:00.118501 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3680 12:29:00.118578 # ok 1949 Set SVE VL 7792
3681 12:29:00.118650 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3682 12:29:00.118731 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3683 12:29:00.118803 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3684 12:29:00.119060 # ok 1953 Set SVE VL 7808
3685 12:29:00.119139 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3686 12:29:00.119200 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3687 12:29:00.121504 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3688 12:29:00.121620 # ok 1957 Set SVE VL 7824
3689 12:29:00.121746 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3690 12:29:00.121839 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3691 12:29:00.121944 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3692 12:29:00.122035 # ok 1961 Set SVE VL 7840
3693 12:29:00.122185 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3694 12:29:00.122864 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3695 12:29:00.123160 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3696 12:29:00.123266 # ok 1965 Set SVE VL 7856
3697 12:29:00.123353 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3698 12:29:00.123452 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3699 12:29:00.123556 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3700 12:29:00.123644 # ok 1969 Set SVE VL 7872
3701 12:29:00.123746 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3702 12:29:00.124050 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3703 12:29:00.124153 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3704 12:29:00.124254 # ok 1973 Set SVE VL 7888
3705 12:29:00.124357 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3706 12:29:00.124460 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3707 12:29:00.124762 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3708 12:29:00.124873 # ok 1977 Set SVE VL 7904
3709 12:29:00.124961 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3710 12:29:00.125063 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3711 12:29:00.125153 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3712 12:29:00.125255 # ok 1981 Set SVE VL 7920
3713 12:29:00.125356 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3714 12:29:00.125459 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3715 12:29:00.125756 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3716 12:29:00.125859 # ok 1985 Set SVE VL 7936
3717 12:29:00.125961 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3718 12:29:00.126061 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3719 12:29:00.126164 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3720 12:29:00.126464 # ok 1989 Set SVE VL 7952
3721 12:29:00.126589 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3722 12:29:00.126693 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3723 12:29:00.126998 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3724 12:29:00.127099 # ok 1993 Set SVE VL 7968
3725 12:29:00.127200 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3726 12:29:00.127300 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3727 12:29:00.127623 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3728 12:29:00.127823 # ok 1997 Set SVE VL 7984
3729 12:29:00.128024 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3730 12:29:00.128179 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3731 12:29:00.128310 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3732 12:29:00.128470 # ok 2001 Set SVE VL 8000
3733 12:29:00.128672 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3734 12:29:00.128840 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3735 12:29:00.129019 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3736 12:29:00.129216 # ok 2005 Set SVE VL 8016
3737 12:29:00.129440 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3738 12:29:00.129714 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3739 12:29:00.129950 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3740 12:29:00.130169 # ok 2009 Set SVE VL 8032
3741 12:29:00.130373 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3742 12:29:00.130563 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3743 12:29:00.130777 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3744 12:29:00.130950 # ok 2013 Set SVE VL 8048
3745 12:29:00.131108 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3746 12:29:00.131284 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3747 12:29:00.131441 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3748 12:29:00.131607 # ok 2017 Set SVE VL 8064
3749 12:29:00.131794 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3750 12:29:00.131966 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3751 12:29:00.132160 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3752 12:29:00.132307 # ok 2021 Set SVE VL 8080
3753 12:29:00.132469 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3754 12:29:00.132679 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3755 12:29:00.132858 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3756 12:29:00.133027 # ok 2025 Set SVE VL 8096
3757 12:29:00.133196 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3758 12:29:00.133366 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3759 12:29:00.133512 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3760 12:29:00.133715 # ok 2029 Set SVE VL 8112
3761 12:29:00.133898 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3762 12:29:00.134073 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3763 12:29:00.134236 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3764 12:29:00.134343 # ok 2033 Set SVE VL 8128
3765 12:29:00.134510 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3766 12:29:00.134672 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3767 12:29:00.134799 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3768 12:29:00.134911 # ok 2037 Set SVE VL 8144
3769 12:29:00.135024 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3770 12:29:00.135375 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3771 12:29:00.135484 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3772 12:29:00.135593 # ok 2041 Set SVE VL 8160
3773 12:29:00.135730 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3774 12:29:00.135856 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3775 12:29:00.135981 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3776 12:29:00.136091 # ok 2045 Set SVE VL 8176
3777 12:29:00.136211 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3778 12:29:00.136330 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3779 12:29:00.136441 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3780 12:29:00.136542 # ok 2049 Set SVE VL 8192
3781 12:29:00.136649 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3782 12:29:00.136759 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3783 12:29:00.136872 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3784 12:29:00.136950 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3785 12:29:00.137060 # ok 2054 Streaming SVE get_fpsimd() gave same state
3786 12:29:00.137170 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3787 12:29:00.137268 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3788 12:29:00.137349 # ok 2057 Set Streaming SVE VL 16
3789 12:29:00.137430 # ok 2058 Set and get Streaming SVE data for VL 16
3790 12:29:00.137533 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3791 12:29:00.137619 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3792 12:29:00.137704 # ok 2061 Set Streaming SVE VL 32
3793 12:29:00.137787 # ok 2062 Set and get Streaming SVE data for VL 32
3794 12:29:00.137858 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3795 12:29:00.137933 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3796 12:29:00.138011 # ok 2065 Set Streaming SVE VL 48
3797 12:29:00.138081 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3798 12:29:00.138147 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3799 12:29:00.138218 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3800 12:29:00.138281 # ok 2069 Set Streaming SVE VL 64
3801 12:29:00.138354 # ok 2070 Set and get Streaming SVE data for VL 64
3802 12:29:00.138431 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3803 12:29:00.138509 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3804 12:29:00.138589 # ok 2073 Set Streaming SVE VL 80
3805 12:29:00.138686 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3806 12:29:00.138768 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3807 12:29:00.138851 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3808 12:29:00.138939 # ok 2077 Set Streaming SVE VL 96
3809 12:29:00.139024 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3810 12:29:00.139312 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3811 12:29:00.139413 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3812 12:29:00.139497 # ok 2081 Set Streaming SVE VL 112
3813 12:29:00.139580 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3814 12:29:00.139659 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3815 12:29:00.139743 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3816 12:29:00.139829 # ok 2085 Set Streaming SVE VL 128
3817 12:29:00.139931 # ok 2086 Set and get Streaming SVE data for VL 128
3818 12:29:00.140016 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3819 12:29:00.140093 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3820 12:29:00.140164 # ok 2089 Set Streaming SVE VL 144
3821 12:29:00.140264 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3822 12:29:00.140344 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3823 12:29:00.140427 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3824 12:29:00.140509 # ok 2093 Set Streaming SVE VL 160
3825 12:29:00.140604 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3826 12:29:00.140899 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3827 12:29:00.141003 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3828 12:29:00.141092 # ok 2097 Set Streaming SVE VL 176
3829 12:29:00.141190 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3830 12:29:00.141274 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3831 12:29:00.141552 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3832 12:29:00.141661 # ok 2101 Set Streaming SVE VL 192
3833 12:29:00.141784 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3834 12:29:00.141906 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3835 12:29:00.142000 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3836 12:29:00.142086 # ok 2105 Set Streaming SVE VL 208
3837 12:29:00.142545 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3838 12:29:00.142641 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3839 12:29:00.142723 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3840 12:29:00.142801 # ok 2109 Set Streaming SVE VL 224
3841 12:29:00.142881 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3842 12:29:00.142963 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3843 12:29:00.143242 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3844 12:29:00.143350 # ok 2113 Set Streaming SVE VL 240
3845 12:29:00.143456 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3846 12:29:00.143545 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3847 12:29:00.143644 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3848 12:29:00.143726 # ok 2117 Set Streaming SVE VL 256
3849 12:29:00.143820 # ok 2118 Set and get Streaming SVE data for VL 256
3850 12:29:00.143929 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3851 12:29:00.144059 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3852 12:29:00.144178 # ok 2121 Set Streaming SVE VL 272
3853 12:29:00.144281 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3854 12:29:00.144577 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3855 12:29:00.144683 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3856 12:29:00.144788 # ok 2125 Set Streaming SVE VL 288
3857 12:29:00.147890 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3858 12:29:00.148428 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3859 12:29:00.148579 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3860 12:29:00.148728 # ok 2129 Set Streaming SVE VL 304
3861 12:29:00.148844 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3862 12:29:00.148965 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3863 12:29:00.149089 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3864 12:29:00.149190 # ok 2133 Set Streaming SVE VL 320
3865 12:29:00.149315 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3866 12:29:00.149426 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3867 12:29:00.149510 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3868 12:29:00.149585 # ok 2137 Set Streaming SVE VL 336
3869 12:29:00.149695 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3870 12:29:00.149788 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3871 12:29:00.149904 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3872 12:29:00.150005 # ok 2141 Set Streaming SVE VL 352
3873 12:29:00.150112 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3874 12:29:00.150239 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3875 12:29:00.150785 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3876 12:29:00.151092 # ok 2145 Set Streaming SVE VL 368
3877 12:29:00.151194 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3878 12:29:00.151296 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3879 12:29:00.151398 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3880 12:29:00.151500 # ok 2149 Set Streaming SVE VL 384
3881 12:29:00.151798 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3882 12:29:00.151896 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3883 12:29:00.151997 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3884 12:29:00.152102 # ok 2153 Set Streaming SVE VL 400
3885 12:29:00.152226 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3886 12:29:00.152336 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3887 12:29:00.152628 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3888 12:29:00.152708 # ok 2157 Set Streaming SVE VL 416
3889 12:29:00.152771 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3890 12:29:00.152851 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3891 12:29:00.152919 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3892 12:29:00.153005 # ok 2161 Set Streaming SVE VL 432
3893 12:29:00.153101 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3894 12:29:00.153382 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3895 12:29:00.153467 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3896 12:29:00.153705 # ok 2165 Set Streaming SVE VL 448
3897 12:29:00.153812 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3898 12:29:00.153912 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3899 12:29:00.154015 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3900 12:29:00.154133 # ok 2169 Set Streaming SVE VL 464
3901 12:29:00.154437 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3902 12:29:00.154570 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3903 12:29:00.154884 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3904 12:29:00.154986 # ok 2173 Set Streaming SVE VL 480
3905 12:29:00.155091 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3906 12:29:00.155180 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3907 12:29:00.155480 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3908 12:29:00.155583 # ok 2177 Set Streaming SVE VL 496
3909 12:29:00.155685 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3910 12:29:00.155784 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3911 12:29:00.156082 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3912 12:29:00.156182 # ok 2181 Set Streaming SVE VL 512
3913 12:29:00.156282 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3914 12:29:00.156382 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3915 12:29:00.156681 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3916 12:29:00.156783 # ok 2185 Set Streaming SVE VL 528
3917 12:29:00.156886 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3918 12:29:00.156988 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3919 12:29:00.157285 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3920 12:29:00.157387 # ok 2189 Set Streaming SVE VL 544
3921 12:29:00.157694 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3922 12:29:00.157791 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3923 12:29:00.157895 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3924 12:29:00.158016 # ok 2193 Set Streaming SVE VL 560
3925 12:29:00.158119 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3926 12:29:00.158225 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3927 12:29:00.158522 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3928 12:29:00.158623 # ok 2197 Set Streaming SVE VL 576
3929 12:29:00.158726 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3930 12:29:00.158828 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3931 12:29:00.159150 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3932 12:29:00.159251 # ok 2201 Set Streaming SVE VL 592
3933 12:29:00.159355 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3934 12:29:00.159460 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3935 12:29:00.159820 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3936 12:29:00.159926 # ok 2205 Set Streaming SVE VL 608
3937 12:29:00.160040 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3938 12:29:00.160120 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3939 12:29:00.160208 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3940 12:29:00.160301 # ok 2209 Set Streaming SVE VL 624
3941 12:29:00.160387 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3942 12:29:00.160482 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3943 12:29:00.160787 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3944 12:29:00.160883 # ok 2213 Set Streaming SVE VL 640
3945 12:29:00.160975 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3946 12:29:00.161066 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3947 12:29:00.161140 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3948 12:29:00.161227 # ok 2217 Set Streaming SVE VL 656
3949 12:29:00.161309 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3950 12:29:00.161407 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3951 12:29:00.161521 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3952 12:29:00.161660 # ok 2221 Set Streaming SVE VL 672
3953 12:29:00.161773 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3954 12:29:00.161867 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3955 12:29:00.162160 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3956 12:29:00.162258 # ok 2225 Set Streaming SVE VL 688
3957 12:29:00.162535 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3958 12:29:00.162636 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3959 12:29:00.162755 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3960 12:29:00.162832 # ok 2229 Set Streaming SVE VL 704
3961 12:29:00.162904 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3962 12:29:00.162984 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3963 12:29:00.163255 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3964 12:29:00.163352 # ok 2233 Set Streaming SVE VL 720
3965 12:29:00.163446 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3966 12:29:00.163512 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3967 12:29:00.163584 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3968 12:29:00.163650 # ok 2237 Set Streaming SVE VL 736
3969 12:29:00.163723 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3970 12:29:00.163809 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3971 12:29:00.164089 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3972 12:29:00.164168 # ok 2241 Set Streaming SVE VL 752
3973 12:29:00.164241 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3974 12:29:00.164313 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3975 12:29:00.164384 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3976 12:29:00.164456 # ok 2245 Set Streaming SVE VL 768
3977 12:29:00.164533 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3978 12:29:00.164798 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3979 12:29:00.164886 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3980 12:29:00.164967 # ok 2249 Set Streaming SVE VL 784
3981 12:29:00.165218 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3982 12:29:00.165288 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3983 12:29:00.165375 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3984 12:29:00.165450 # ok 2253 Set Streaming SVE VL 800
3985 12:29:00.165528 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3986 12:29:00.165614 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3987 12:29:00.165707 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3988 12:29:00.166002 # ok 2257 Set Streaming SVE VL 816
3989 12:29:00.166113 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3990 12:29:00.166201 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3991 12:29:00.166485 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3992 12:29:00.166573 # ok 2261 Set Streaming SVE VL 832
3993 12:29:00.166648 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3994 12:29:00.166741 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3995 12:29:00.166828 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3996 12:29:00.166917 # ok 2265 Set Streaming SVE VL 848
3997 12:29:00.167004 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3998 12:29:00.167101 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3999 12:29:00.167381 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
4000 12:29:00.167460 # ok 2269 Set Streaming SVE VL 864
4001 12:29:00.167544 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
4002 12:29:00.167631 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
4003 12:29:00.167739 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4004 12:29:00.167836 # ok 2273 Set Streaming SVE VL 880
4005 12:29:00.167935 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4006 12:29:00.168227 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4007 12:29:00.168326 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4008 12:29:00.168392 # ok 2277 Set Streaming SVE VL 896
4009 12:29:00.168463 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4010 12:29:00.173861 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4011 12:29:00.174084 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4012 12:29:00.174163 # ok 2281 Set Streaming SVE VL 912
4013 12:29:00.174236 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4014 12:29:00.174318 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4015 12:29:00.174389 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4016 12:29:00.174457 # ok 2285 Set Streaming SVE VL 928
4017 12:29:00.174518 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4018 12:29:00.174578 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4019 12:29:00.174639 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4020 12:29:00.174699 # ok 2289 Set Streaming SVE VL 944
4021 12:29:00.174759 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4022 12:29:00.174820 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4023 12:29:00.174886 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4024 12:29:00.175173 # ok 2293 Set Streaming SVE VL 960
4025 12:29:00.175267 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4026 12:29:00.175335 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4027 12:29:00.175402 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4028 12:29:00.175479 # ok 2297 Set Streaming SVE VL 976
4029 12:29:00.175573 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4030 12:29:00.175654 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4031 12:29:00.175733 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4032 12:29:00.175811 # ok 2301 Set Streaming SVE VL 992
4033 12:29:00.175904 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4034 12:29:00.175982 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4035 12:29:00.176065 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4036 12:29:00.176149 # ok 2305 Set Streaming SVE VL 1008
4037 12:29:00.176245 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4038 12:29:00.176353 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4039 12:29:00.176474 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4040 12:29:00.176574 # ok 2309 Set Streaming SVE VL 1024
4041 12:29:00.176662 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4042 12:29:00.176749 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4043 12:29:00.177029 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4044 12:29:00.177112 # ok 2313 Set Streaming SVE VL 1040
4045 12:29:00.177207 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4046 12:29:00.177294 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4047 12:29:00.177561 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4048 12:29:00.177633 # ok 2317 Set Streaming SVE VL 1056
4049 12:29:00.177750 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4050 12:29:00.177838 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4051 12:29:00.177925 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4052 12:29:00.178010 # ok 2321 Set Streaming SVE VL 1072
4053 12:29:00.178325 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4054 12:29:00.178587 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4055 12:29:00.178659 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4056 12:29:00.178751 # ok 2325 Set Streaming SVE VL 1088
4057 12:29:00.178839 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4058 12:29:00.178911 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4059 12:29:00.179002 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4060 12:29:00.179073 # ok 2329 Set Streaming SVE VL 1104
4061 12:29:00.179186 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4062 12:29:00.179293 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4063 12:29:00.179618 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4064 12:29:00.179714 # ok 2333 Set Streaming SVE VL 1120
4065 12:29:00.179821 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4066 12:29:00.179909 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4067 12:29:00.179996 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4068 12:29:00.180093 # ok 2337 Set Streaming SVE VL 1136
4069 12:29:00.180186 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4070 12:29:00.180459 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4071 12:29:00.180556 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4072 12:29:00.180645 # ok 2341 Set Streaming SVE VL 1152
4073 12:29:00.180909 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4074 12:29:00.180994 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4075 12:29:00.181081 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4076 12:29:00.181167 # ok 2345 Set Streaming SVE VL 1168
4077 12:29:00.181441 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4078 12:29:00.181538 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4079 12:29:00.181627 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4080 12:29:00.181725 # ok 2349 Set Streaming SVE VL 1184
4081 12:29:00.182003 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4082 12:29:00.182098 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4083 12:29:00.182407 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4084 12:29:00.182685 # ok 2353 Set Streaming SVE VL 1200
4085 12:29:00.182768 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4086 12:29:00.182846 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4087 12:29:00.182934 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4088 12:29:00.183189 # ok 2357 Set Streaming SVE VL 1216
4089 12:29:00.183259 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4090 12:29:00.183333 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4091 12:29:00.183609 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4092 12:29:00.183686 # ok 2361 Set Streaming SVE VL 1232
4093 12:29:00.183759 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4094 12:29:00.183846 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4095 12:29:00.184115 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4096 12:29:00.184195 # ok 2365 Set Streaming SVE VL 1248
4097 12:29:00.184287 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4098 12:29:00.184572 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4099 12:29:00.184695 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4100 12:29:00.184785 # ok 2369 Set Streaming SVE VL 1264
4101 12:29:00.184885 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4102 12:29:00.184969 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4103 12:29:00.185050 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4104 12:29:00.185131 # ok 2373 Set Streaming SVE VL 1280
4105 12:29:00.185230 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4106 12:29:00.185529 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4107 12:29:00.185644 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4108 12:29:00.185747 # ok 2377 Set Streaming SVE VL 1296
4109 12:29:00.185850 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4110 12:29:00.185939 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4111 12:29:00.186040 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4112 12:29:00.186142 # ok 2381 Set Streaming SVE VL 1312
4113 12:29:00.186427 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4114 12:29:00.186537 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4115 12:29:00.186819 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4116 12:29:00.186916 # ok 2385 Set Streaming SVE VL 1328
4117 12:29:00.187007 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4118 12:29:00.187095 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4119 12:29:00.187266 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4120 12:29:00.187375 # ok 2389 Set Streaming SVE VL 1344
4121 12:29:00.187465 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4122 12:29:00.187748 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4123 12:29:00.187861 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4124 12:29:00.187961 # ok 2393 Set Streaming SVE VL 1360
4125 12:29:00.188251 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4126 12:29:00.188357 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4127 12:29:00.188463 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4128 12:29:00.188567 # ok 2397 Set Streaming SVE VL 1376
4129 12:29:00.188862 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4130 12:29:00.188955 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4131 12:29:00.189058 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4132 12:29:00.189147 # ok 2401 Set Streaming SVE VL 1392
4133 12:29:00.189251 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4134 12:29:00.189551 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4135 12:29:00.189665 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4136 12:29:00.189761 # ok 2405 Set Streaming SVE VL 1408
4137 12:29:00.189839 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4138 12:29:00.189926 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4139 12:29:00.190207 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4140 12:29:00.190316 # ok 2409 Set Streaming SVE VL 1424
4141 12:29:00.190409 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4142 12:29:00.190498 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4143 12:29:00.190813 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4144 12:29:00.190917 # ok 2413 Set Streaming SVE VL 1440
4145 12:29:00.191025 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4146 12:29:00.191112 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4147 12:29:00.191212 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4148 12:29:00.191525 # ok 2417 Set Streaming SVE VL 1456
4149 12:29:00.191629 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4150 12:29:00.191735 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4151 12:29:00.192041 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4152 12:29:00.192147 # ok 2421 Set Streaming SVE VL 1472
4153 12:29:00.192250 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4154 12:29:00.192354 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4155 12:29:00.192652 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4156 12:29:00.192757 # ok 2425 Set Streaming SVE VL 1488
4157 12:29:00.192859 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4158 12:29:00.193057 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4159 12:29:00.193175 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4160 12:29:00.195886 # ok 2429 Set Streaming SVE VL 1504
4161 12:29:00.196066 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4162 12:29:00.196140 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4163 12:29:00.196254 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4164 12:29:00.196343 # ok 2433 Set Streaming SVE VL 1520
4165 12:29:00.196431 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4166 12:29:00.196700 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4167 12:29:00.196775 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4168 12:29:00.196867 # ok 2437 Set Streaming SVE VL 1536
4169 12:29:00.196953 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4170 12:29:00.197039 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4171 12:29:00.197150 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4172 12:29:00.197235 # ok 2441 Set Streaming SVE VL 1552
4173 12:29:00.197530 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4174 12:29:00.197629 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4175 12:29:00.197760 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4176 12:29:00.197863 # ok 2445 Set Streaming SVE VL 1568
4177 12:29:00.197983 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4178 12:29:00.198101 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4179 12:29:00.198665 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4180 12:29:00.198964 # ok 2449 Set Streaming SVE VL 1584
4181 12:29:00.199068 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4182 12:29:00.199180 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4183 12:29:00.199270 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4184 12:29:00.199369 # ok 2453 Set Streaming SVE VL 1600
4185 12:29:00.199453 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4186 12:29:00.199548 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4187 12:29:00.199644 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4188 12:29:00.199738 # ok 2457 Set Streaming SVE VL 1616
4189 12:29:00.199832 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4190 12:29:00.200122 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4191 12:29:00.200221 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4192 12:29:00.200303 # ok 2461 Set Streaming SVE VL 1632
4193 12:29:00.200400 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4194 12:29:00.200484 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4195 12:29:00.200581 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4196 12:29:00.200661 # ok 2465 Set Streaming SVE VL 1648
4197 12:29:00.200916 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4198 12:29:00.200987 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4199 12:29:00.201063 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4200 12:29:00.201140 # ok 2469 Set Streaming SVE VL 1664
4201 12:29:00.201244 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4202 12:29:00.201368 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4203 12:29:00.201671 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4204 12:29:00.201772 # ok 2473 Set Streaming SVE VL 1680
4205 12:29:00.201875 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4206 12:29:00.201960 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4207 12:29:00.202442 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4208 12:29:00.202541 # ok 2477 Set Streaming SVE VL 1696
4209 12:29:00.202665 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4210 12:29:00.202782 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4211 12:29:00.202892 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4212 12:29:00.202992 # ok 2481 Set Streaming SVE VL 1712
4213 12:29:00.203114 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4214 12:29:00.203415 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4215 12:29:00.203503 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4216 12:29:00.203602 # ok 2485 Set Streaming SVE VL 1728
4217 12:29:00.203874 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4218 12:29:00.203958 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4219 12:29:00.204053 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4220 12:29:00.204155 # ok 2489 Set Streaming SVE VL 1744
4221 12:29:00.204431 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4222 12:29:00.204710 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4223 12:29:00.204807 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4224 12:29:00.204910 # ok 2493 Set Streaming SVE VL 1760
4225 12:29:00.205019 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4226 12:29:00.205110 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4227 12:29:00.205391 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4228 12:29:00.205482 # ok 2497 Set Streaming SVE VL 1776
4229 12:29:00.205738 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4230 12:29:00.205817 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4231 12:29:00.205894 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4232 12:29:00.205972 # ok 2501 Set Streaming SVE VL 1792
4233 12:29:00.206260 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4234 12:29:00.206371 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4235 12:29:00.206672 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4236 12:29:00.206754 # ok 2505 Set Streaming SVE VL 1808
4237 12:29:00.206866 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4238 12:29:00.206969 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4239 12:29:00.207063 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4240 12:29:00.207173 # ok 2509 Set Streaming SVE VL 1824
4241 12:29:00.207273 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4242 12:29:00.207547 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4243 12:29:00.207658 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4244 12:29:00.207957 # ok 2513 Set Streaming SVE VL 1840
4245 12:29:00.208051 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4246 12:29:00.208136 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4247 12:29:00.208235 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4248 12:29:00.208326 # ok 2517 Set Streaming SVE VL 1856
4249 12:29:00.208415 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4250 12:29:00.208498 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4251 12:29:00.208775 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4252 12:29:00.208882 # ok 2521 Set Streaming SVE VL 1872
4253 12:29:00.208995 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4254 12:29:00.209301 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4255 12:29:00.209413 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4256 12:29:00.209515 # ok 2525 Set Streaming SVE VL 1888
4257 12:29:00.209611 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4258 12:29:00.209893 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4259 12:29:00.210015 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4260 12:29:00.210099 # ok 2529 Set Streaming SVE VL 1904
4261 12:29:00.210962 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4262 12:29:00.211268 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4263 12:29:00.211364 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4264 12:29:00.211466 # ok 2533 Set Streaming SVE VL 1920
4265 12:29:00.211766 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4266 12:29:00.211873 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4267 12:29:00.211979 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4268 12:29:00.212085 # ok 2537 Set Streaming SVE VL 1936
4269 12:29:00.212193 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4270 12:29:00.212488 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4271 12:29:00.212589 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4272 12:29:00.212695 # ok 2541 Set Streaming SVE VL 1952
4273 12:29:00.212992 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4274 12:29:00.213074 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4275 12:29:00.213149 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4276 12:29:00.213237 # ok 2545 Set Streaming SVE VL 1968
4277 12:29:00.213516 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4278 12:29:00.213600 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4279 12:29:00.213713 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4280 12:29:00.213793 # ok 2549 Set Streaming SVE VL 1984
4281 12:29:00.214060 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4282 12:29:00.214146 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4283 12:29:00.214743 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4284 12:29:00.215031 # ok 2553 Set Streaming SVE VL 2000
4285 12:29:00.215123 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4286 12:29:00.215218 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4287 12:29:00.215317 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4288 12:29:00.215421 # ok 2557 Set Streaming SVE VL 2016
4289 12:29:00.215516 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4290 12:29:00.215840 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4291 12:29:00.215943 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4292 12:29:00.216039 # ok 2561 Set Streaming SVE VL 2032
4293 12:29:00.216139 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4294 12:29:00.216241 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4295 12:29:00.216340 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4296 12:29:00.216621 # ok 2565 Set Streaming SVE VL 2048
4297 12:29:00.216734 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4298 12:29:00.216827 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4299 12:29:00.217102 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4300 12:29:00.217203 # ok 2569 Set Streaming SVE VL 2064
4301 12:29:00.217297 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4302 12:29:00.217390 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4303 12:29:00.217489 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4304 12:29:00.217596 # ok 2573 Set Streaming SVE VL 2080
4305 12:29:00.217705 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4306 12:29:00.217810 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4307 12:29:00.217913 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4308 12:29:00.218018 # ok 2577 Set Streaming SVE VL 2096
4309 12:29:00.218312 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4310 12:29:00.221066 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4311 12:29:00.221282 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4312 12:29:00.221366 # ok 2581 Set Streaming SVE VL 2112
4313 12:29:00.221457 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4314 12:29:00.221698 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4315 12:29:00.221802 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4316 12:29:00.221893 # ok 2585 Set Streaming SVE VL 2128
4317 12:29:00.222000 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4318 12:29:00.222097 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4319 12:29:00.222923 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4320 12:29:00.223029 # ok 2589 Set Streaming SVE VL 2144
4321 12:29:00.223131 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4322 12:29:00.223221 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4323 12:29:00.223316 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4324 12:29:00.223413 # ok 2593 Set Streaming SVE VL 2160
4325 12:29:00.223535 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4326 12:29:00.223644 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4327 12:29:00.223767 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4328 12:29:00.223846 # ok 2597 Set Streaming SVE VL 2176
4329 12:29:00.223943 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4330 12:29:00.224227 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4331 12:29:00.224321 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4332 12:29:00.224419 # ok 2601 Set Streaming SVE VL 2192
4333 12:29:00.224502 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4334 12:29:00.224599 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4335 12:29:00.224671 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4336 12:29:00.224740 # ok 2605 Set Streaming SVE VL 2208
4337 12:29:00.224826 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4338 12:29:00.224916 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4339 12:29:00.225014 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4340 12:29:00.225112 # ok 2609 Set Streaming SVE VL 2224
4341 12:29:00.225206 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4342 12:29:00.225299 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4343 12:29:00.225387 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4344 12:29:00.225471 # ok 2613 Set Streaming SVE VL 2240
4345 12:29:00.225749 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4346 12:29:00.225840 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4347 12:29:00.225937 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4348 12:29:00.226014 # ok 2617 Set Streaming SVE VL 2256
4349 12:29:00.226290 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4350 12:29:00.226400 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4351 12:29:00.226682 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4352 12:29:00.226770 # ok 2621 Set Streaming SVE VL 2272
4353 12:29:00.226868 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4354 12:29:00.226953 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4355 12:29:00.227047 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4356 12:29:00.227333 # ok 2625 Set Streaming SVE VL 2288
4357 12:29:00.227431 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4358 12:29:00.227525 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4359 12:29:00.227625 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4360 12:29:00.227711 # ok 2629 Set Streaming SVE VL 2304
4361 12:29:00.227806 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4362 12:29:00.228106 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4363 12:29:00.228210 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4364 12:29:00.228339 # ok 2633 Set Streaming SVE VL 2320
4365 12:29:00.228421 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4366 12:29:00.228505 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4367 12:29:00.228793 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4368 12:29:00.228883 # ok 2637 Set Streaming SVE VL 2336
4369 12:29:00.228958 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4370 12:29:00.229066 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4371 12:29:00.229251 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4372 12:29:00.229366 # ok 2641 Set Streaming SVE VL 2352
4373 12:29:00.229465 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4374 12:29:00.229563 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4375 12:29:00.229880 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4376 12:29:00.229976 # ok 2645 Set Streaming SVE VL 2368
4377 12:29:00.230064 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4378 12:29:00.230349 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4379 12:29:00.230465 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4380 12:29:00.230589 # ok 2649 Set Streaming SVE VL 2384
4381 12:29:00.230690 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4382 12:29:00.230978 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4383 12:29:00.231095 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4384 12:29:00.231220 # ok 2653 Set Streaming SVE VL 2400
4385 12:29:00.231331 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4386 12:29:00.231431 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4387 12:29:00.231525 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4388 12:29:00.231602 # ok 2657 Set Streaming SVE VL 2416
4389 12:29:00.231725 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4390 12:29:00.231836 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4391 12:29:00.232113 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4392 12:29:00.232221 # ok 2661 Set Streaming SVE VL 2432
4393 12:29:00.232324 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4394 12:29:00.232624 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4395 12:29:00.232729 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4396 12:29:00.232829 # ok 2665 Set Streaming SVE VL 2448
4397 12:29:00.232931 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4398 12:29:00.233231 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4399 12:29:00.233349 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4400 12:29:00.233449 # ok 2669 Set Streaming SVE VL 2464
4401 12:29:00.233754 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4402 12:29:00.233871 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4403 12:29:00.233974 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4404 12:29:00.234369 # ok 2673 Set Streaming SVE VL 2480
4405 12:29:00.234485 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4406 12:29:00.234804 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4407 12:29:00.234909 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4408 12:29:00.235017 # ok 2677 Set Streaming SVE VL 2496
4409 12:29:00.235312 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4410 12:29:00.235414 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4411 12:29:00.235545 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4412 12:29:00.235642 # ok 2681 Set Streaming SVE VL 2512
4413 12:29:00.235759 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4414 12:29:00.235873 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4415 12:29:00.235976 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4416 12:29:00.236084 # ok 2685 Set Streaming SVE VL 2528
4417 12:29:00.236382 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4418 12:29:00.236480 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4419 12:29:00.236569 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4420 12:29:00.236657 # ok 2689 Set Streaming SVE VL 2544
4421 12:29:00.236742 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4422 12:29:00.237028 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4423 12:29:00.237123 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4424 12:29:00.237213 # ok 2693 Set Streaming SVE VL 2560
4425 12:29:00.237304 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4426 12:29:00.237405 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4427 12:29:00.237690 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4428 12:29:00.237778 # ok 2697 Set Streaming SVE VL 2576
4429 12:29:00.237868 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4430 12:29:00.237957 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4431 12:29:00.238046 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4432 12:29:00.238360 # ok 2701 Set Streaming SVE VL 2592
4433 12:29:00.238466 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4434 12:29:00.238759 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4435 12:29:00.238866 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4436 12:29:00.238976 # ok 2705 Set Streaming SVE VL 2608
4437 12:29:00.239080 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4438 12:29:00.239187 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4439 12:29:00.239289 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4440 12:29:00.239391 # ok 2709 Set Streaming SVE VL 2624
4441 12:29:00.239492 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4442 12:29:00.239598 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4443 12:29:00.239928 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4444 12:29:00.240039 # ok 2713 Set Streaming SVE VL 2640
4445 12:29:00.240141 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4446 12:29:00.240243 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4447 12:29:00.240344 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4448 12:29:00.240445 # ok 2717 Set Streaming SVE VL 2656
4449 12:29:00.240547 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4450 12:29:00.240648 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4451 12:29:00.240946 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4452 12:29:00.241052 # ok 2721 Set Streaming SVE VL 2672
4453 12:29:00.241156 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4454 12:29:00.241262 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4455 12:29:00.241352 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4456 12:29:00.241455 # ok 2725 Set Streaming SVE VL 2688
4457 12:29:00.241559 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4458 12:29:00.241669 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4459 12:29:00.244296 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4460 12:29:00.244450 # ok 2729 Set Streaming SVE VL 2704
4461 12:29:00.244548 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4462 12:29:00.244633 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4463 12:29:00.244728 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4464 12:29:00.244821 # ok 2733 Set Streaming SVE VL 2720
4465 12:29:00.244911 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4466 12:29:00.245172 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4467 12:29:00.245257 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4468 12:29:00.245339 # ok 2737 Set Streaming SVE VL 2736
4469 12:29:00.245407 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4470 12:29:00.245493 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4471 12:29:00.245806 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4472 12:29:00.245904 # ok 2741 Set Streaming SVE VL 2752
4473 12:29:00.246015 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4474 12:29:00.246554 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4475 12:29:00.246833 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4476 12:29:00.246942 # ok 2745 Set Streaming SVE VL 2768
4477 12:29:00.247053 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4478 12:29:00.247138 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4479 12:29:00.247225 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4480 12:29:00.247316 # ok 2749 Set Streaming SVE VL 2784
4481 12:29:00.247411 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4482 12:29:00.247543 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4483 12:29:00.247848 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4484 12:29:00.247955 # ok 2753 Set Streaming SVE VL 2800
4485 12:29:00.248065 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4486 12:29:00.248165 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4487 12:29:00.248268 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4488 12:29:00.248566 # ok 2757 Set Streaming SVE VL 2816
4489 12:29:00.248669 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4490 12:29:00.248770 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4491 12:29:00.249066 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4492 12:29:00.249161 # ok 2761 Set Streaming SVE VL 2832
4493 12:29:00.249256 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4494 12:29:00.249340 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4495 12:29:00.249432 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4496 12:29:00.249523 # ok 2765 Set Streaming SVE VL 2848
4497 12:29:00.249790 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4498 12:29:00.249899 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4499 12:29:00.250184 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4500 12:29:00.250292 # ok 2769 Set Streaming SVE VL 2864
4501 12:29:00.250384 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4502 12:29:00.250688 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4503 12:29:00.250784 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4504 12:29:00.250864 # ok 2773 Set Streaming SVE VL 2880
4505 12:29:00.250956 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4506 12:29:00.251253 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4507 12:29:00.251353 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4508 12:29:00.251446 # ok 2777 Set Streaming SVE VL 2896
4509 12:29:00.251554 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4510 12:29:00.251662 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4511 12:29:00.251759 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4512 12:29:00.251857 # ok 2781 Set Streaming SVE VL 2912
4513 12:29:00.252003 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4514 12:29:00.252125 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4515 12:29:00.252452 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4516 12:29:00.252620 # ok 2785 Set Streaming SVE VL 2928
4517 12:29:00.252717 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4518 12:29:00.252822 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4519 12:29:00.253127 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4520 12:29:00.253226 # ok 2789 Set Streaming SVE VL 2944
4521 12:29:00.253329 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4522 12:29:00.253431 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4523 12:29:00.253694 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4524 12:29:00.253797 # ok 2793 Set Streaming SVE VL 2960
4525 12:29:00.253906 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4526 12:29:00.254207 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4527 12:29:00.254325 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4528 12:29:00.254427 # ok 2797 Set Streaming SVE VL 2976
4529 12:29:00.254734 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4530 12:29:00.254851 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4531 12:29:00.254957 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4532 12:29:00.255073 # ok 2801 Set Streaming SVE VL 2992
4533 12:29:00.255371 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4534 12:29:00.255490 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4535 12:29:00.255802 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4536 12:29:00.255905 # ok 2805 Set Streaming SVE VL 3008
4537 12:29:00.256008 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4538 12:29:00.256114 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4539 12:29:00.256418 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4540 12:29:00.256521 # ok 2809 Set Streaming SVE VL 3024
4541 12:29:00.256621 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4542 12:29:00.256721 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4543 12:29:00.257014 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4544 12:29:00.257125 # ok 2813 Set Streaming SVE VL 3040
4545 12:29:00.257224 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4546 12:29:00.257323 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4547 12:29:00.257653 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4548 12:29:00.257745 # ok 2817 Set Streaming SVE VL 3056
4549 12:29:00.258031 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4550 12:29:00.258128 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4551 12:29:00.258221 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4552 12:29:00.258310 # ok 2821 Set Streaming SVE VL 3072
4553 12:29:00.258603 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4554 12:29:00.258709 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4555 12:29:00.258816 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4556 12:29:00.258924 # ok 2825 Set Streaming SVE VL 3088
4557 12:29:00.259226 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4558 12:29:00.259344 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4559 12:29:00.259448 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4560 12:29:00.259552 # ok 2829 Set Streaming SVE VL 3104
4561 12:29:00.259651 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4562 12:29:00.259945 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4563 12:29:00.260263 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4564 12:29:00.260365 # ok 2833 Set Streaming SVE VL 3120
4565 12:29:00.260468 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4566 12:29:00.260552 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4567 12:29:00.260846 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4568 12:29:00.260950 # ok 2837 Set Streaming SVE VL 3136
4569 12:29:00.261056 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4570 12:29:00.261162 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4571 12:29:00.261473 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4572 12:29:00.261576 # ok 2841 Set Streaming SVE VL 3152
4573 12:29:00.261682 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4574 12:29:00.261976 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4575 12:29:00.262078 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4576 12:29:00.262376 # ok 2845 Set Streaming SVE VL 3168
4577 12:29:00.262488 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4578 12:29:00.262806 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4579 12:29:00.262900 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4580 12:29:00.262979 # ok 2849 Set Streaming SVE VL 3184
4581 12:29:00.263069 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4582 12:29:00.263145 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4583 12:29:00.263257 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4584 12:29:00.263349 # ok 2853 Set Streaming SVE VL 3200
4585 12:29:00.263453 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4586 12:29:00.263751 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4587 12:29:00.263849 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4588 12:29:00.263968 # ok 2857 Set Streaming SVE VL 3216
4589 12:29:00.264054 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4590 12:29:00.264154 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4591 12:29:00.264449 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4592 12:29:00.264545 # ok 2861 Set Streaming SVE VL 3232
4593 12:29:00.264640 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4594 12:29:00.264736 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4595 12:29:00.265014 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4596 12:29:00.265101 # ok 2865 Set Streaming SVE VL 3248
4597 12:29:00.265194 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4598 12:29:00.265464 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4599 12:29:00.265750 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4600 12:29:00.265853 # ok 2869 Set Streaming SVE VL 3264
4601 12:29:00.265948 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4602 12:29:00.266053 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4603 12:29:00.266392 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4604 12:29:00.266682 # ok 2873 Set Streaming SVE VL 3280
4605 12:29:00.266770 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4606 12:29:00.266864 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4607 12:29:00.266947 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4608 12:29:00.267045 # ok 2877 Set Streaming SVE VL 3296
4609 12:29:00.272689 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4610 12:29:00.272880 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4611 12:29:00.273821 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4612 12:29:00.273919 # ok 2881 Set Streaming SVE VL 3312
4613 12:29:00.274012 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4614 12:29:00.274100 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4615 12:29:00.274167 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4616 12:29:00.274228 # ok 2885 Set Streaming SVE VL 3328
4617 12:29:00.274287 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4618 12:29:00.274348 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4619 12:29:00.274407 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4620 12:29:00.274466 # ok 2889 Set Streaming SVE VL 3344
4621 12:29:00.274552 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4622 12:29:00.274619 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4623 12:29:00.274864 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4624 12:29:00.274930 # ok 2893 Set Streaming SVE VL 3360
4625 12:29:00.285877 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4626 12:29:00.286117 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4627 12:29:00.286200 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4628 12:29:00.286274 # ok 2897 Set Streaming SVE VL 3376
4629 12:29:00.286348 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4630 12:29:00.286419 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4631 12:29:00.286492 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4632 12:29:00.286564 # ok 2901 Set Streaming SVE VL 3392
4633 12:29:00.286636 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4634 12:29:00.286708 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4635 12:29:00.286780 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4636 12:29:00.286853 # ok 2905 Set Streaming SVE VL 3408
4637 12:29:00.286925 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4638 12:29:00.286996 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4639 12:29:00.287071 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4640 12:29:00.287159 # ok 2909 Set Streaming SVE VL 3424
4641 12:29:00.287237 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4642 12:29:00.296708 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4643 12:29:00.297169 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4644 12:29:00.297275 # ok 2913 Set Streaming SVE VL 3440
4645 12:29:00.297366 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4646 12:29:00.297452 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4647 12:29:00.297556 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4648 12:29:00.297643 # ok 2917 Set Streaming SVE VL 3456
4649 12:29:00.297741 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4650 12:29:00.297841 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4651 12:29:00.297941 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4652 12:29:00.298047 # ok 2921 Set Streaming SVE VL 3472
4653 12:29:00.305782 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4654 12:29:00.306074 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4655 12:29:00.306360 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4656 12:29:00.306431 # ok 2925 Set Streaming SVE VL 3488
4657 12:29:00.307702 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4658 12:29:00.308032 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4659 12:29:00.308139 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4660 12:29:00.308240 # ok 2929 Set Streaming SVE VL 3504
4661 12:29:00.308326 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4662 12:29:00.308425 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4663 12:29:00.308727 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4664 12:29:00.308827 # ok 2933 Set Streaming SVE VL 3520
4665 12:29:00.308927 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4666 12:29:00.309276 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4667 12:29:00.309375 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4668 12:29:00.309474 # ok 2937 Set Streaming SVE VL 3536
4669 12:29:00.309558 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4670 12:29:00.309680 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4671 12:29:00.309967 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4672 12:29:00.310067 # ok 2941 Set Streaming SVE VL 3552
4673 12:29:00.315468 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4674 12:29:00.315941 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4675 12:29:00.316043 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4676 12:29:00.316131 # ok 2945 Set Streaming SVE VL 3568
4677 12:29:00.316224 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4678 12:29:00.316329 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4679 12:29:00.316420 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4680 12:29:00.316525 # ok 2949 Set Streaming SVE VL 3584
4681 12:29:00.316627 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4682 12:29:00.316732 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4683 12:29:00.317037 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4684 12:29:00.317157 # ok 2953 Set Streaming SVE VL 3600
4685 12:29:00.317459 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4686 12:29:00.317561 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4687 12:29:00.317675 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4688 12:29:00.317779 # ok 2957 Set Streaming SVE VL 3616
4689 12:29:00.317882 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4690 12:29:00.323421 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4691 12:29:00.323904 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4692 12:29:00.324009 # ok 2961 Set Streaming SVE VL 3632
4693 12:29:00.324099 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4694 12:29:00.324191 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4695 12:29:00.324294 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4696 12:29:00.324382 # ok 2965 Set Streaming SVE VL 3648
4697 12:29:00.324471 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4698 12:29:00.324774 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4699 12:29:00.324877 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4700 12:29:00.324965 # ok 2969 Set Streaming SVE VL 3664
4701 12:29:00.325068 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4702 12:29:00.325171 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4703 12:29:00.325474 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4704 12:29:00.325574 # ok 2973 Set Streaming SVE VL 3680
4705 12:29:00.325684 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4706 12:29:00.325786 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4707 12:29:00.326076 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4708 12:29:00.331814 # ok 2977 Set Streaming SVE VL 3696
4709 12:29:00.332276 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4710 12:29:00.332373 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4711 12:29:00.332463 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4712 12:29:00.332551 # ok 2981 Set Streaming SVE VL 3712
4713 12:29:00.332848 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4714 12:29:00.333149 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4715 12:29:00.333250 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4716 12:29:00.333550 # ok 2985 Set Streaming SVE VL 3728
4717 12:29:00.333660 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4718 12:29:00.333962 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4719 12:29:00.339422 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4720 12:29:00.339680 # ok 2989 Set Streaming SVE VL 3744
4721 12:29:00.339966 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4722 12:29:00.340071 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4723 12:29:00.340151 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4724 12:29:00.340424 # ok 2993 Set Streaming SVE VL 3760
4725 12:29:00.340514 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4726 12:29:00.340587 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4727 12:29:00.340658 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4728 12:29:00.340727 # ok 2997 Set Streaming SVE VL 3776
4729 12:29:00.340812 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4730 12:29:00.340885 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4731 12:29:00.340968 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4732 12:29:00.341040 # ok 3001 Set Streaming SVE VL 3792
4733 12:29:00.341123 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4734 12:29:00.341401 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4735 12:29:00.341492 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4736 12:29:00.341578 # ok 3005 Set Streaming SVE VL 3808
4737 12:29:00.341681 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4738 12:29:00.342092 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4739 12:29:00.347205 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4740 12:29:00.347592 # ok 3009 Set Streaming SVE VL 3824
4741 12:29:00.347698 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4742 12:29:00.347802 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4743 12:29:00.347906 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4744 12:29:00.347995 # ok 3013 Set Streaming SVE VL 3840
4745 12:29:00.348085 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4746 12:29:00.348365 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4747 12:29:00.348461 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4748 12:29:00.348540 # ok 3017 Set Streaming SVE VL 3856
4749 12:29:00.348783 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4750 12:29:00.348848 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4751 12:29:00.348946 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4752 12:29:00.349044 # ok 3021 Set Streaming SVE VL 3872
4753 12:29:00.349145 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4754 12:29:00.349414 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4755 12:29:00.349549 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4756 12:29:00.349668 # ok 3025 Set Streaming SVE VL 3888
4757 12:29:00.349769 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4758 12:29:00.356241 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4759 12:29:00.356469 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4760 12:29:00.356577 # ok 3029 Set Streaming SVE VL 3904
4761 12:29:00.356661 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4762 12:29:00.356738 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4763 12:29:00.356834 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4764 12:29:00.356903 # ok 3033 Set Streaming SVE VL 3920
4765 12:29:00.356974 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4766 12:29:00.357072 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4767 12:29:00.357347 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4768 12:29:00.357420 # ok 3037 Set Streaming SVE VL 3936
4769 12:29:00.357497 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4770 12:29:00.357615 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4771 12:29:00.357946 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4772 12:29:00.358029 # ok 3041 Set Streaming SVE VL 3952
4773 12:29:00.359757 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4774 12:29:00.360031 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4775 12:29:00.360137 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4776 12:29:00.360238 # ok 3045 Set Streaming SVE VL 3968
4777 12:29:00.360334 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4778 12:29:00.360429 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4779 12:29:00.360765 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4780 12:29:00.360861 # ok 3049 Set Streaming SVE VL 3984
4781 12:29:00.360954 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4782 12:29:00.361032 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4783 12:29:00.361118 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4784 12:29:00.361196 # ok 3053 Set Streaming SVE VL 4000
4785 12:29:00.361286 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4786 12:29:00.361593 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4787 12:29:00.361717 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4788 12:29:00.361833 # ok 3057 Set Streaming SVE VL 4016
4789 12:29:00.361930 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4790 12:29:00.367971 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4791 12:29:00.368410 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4792 12:29:00.368516 # ok 3061 Set Streaming SVE VL 4032
4793 12:29:00.368597 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4794 12:29:00.368670 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4795 12:29:00.368761 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4796 12:29:00.368830 # ok 3065 Set Streaming SVE VL 4048
4797 12:29:00.368902 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4798 12:29:00.369178 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4799 12:29:00.369273 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4800 12:29:00.369373 # ok 3069 Set Streaming SVE VL 4064
4801 12:29:00.369654 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4802 12:29:00.369742 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4803 12:29:00.369836 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4804 12:29:00.370073 # ok 3073 Set Streaming SVE VL 4080
4805 12:29:00.375699 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4806 12:29:00.376109 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4807 12:29:00.376192 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4808 12:29:00.376267 # ok 3077 Set Streaming SVE VL 4096
4809 12:29:00.376333 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4810 12:29:00.376428 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4811 12:29:00.376524 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4812 12:29:00.376604 # ok 3081 Set Streaming SVE VL 4112
4813 12:29:00.376858 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4814 12:29:00.376938 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4815 12:29:00.377207 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4816 12:29:00.377289 # ok 3085 Set Streaming SVE VL 4128
4817 12:29:00.377363 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4818 12:29:00.377604 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4819 12:29:00.377710 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4820 12:29:00.377786 # ok 3089 Set Streaming SVE VL 4144
4821 12:29:00.378033 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4822 12:29:00.383749 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4823 12:29:00.384066 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4824 12:29:00.384174 # ok 3093 Set Streaming SVE VL 4160
4825 12:29:00.384289 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4826 12:29:00.384576 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4827 12:29:00.384668 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4828 12:29:00.384753 # ok 3097 Set Streaming SVE VL 4176
4829 12:29:00.384835 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4830 12:29:00.384935 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4831 12:29:00.385187 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4832 12:29:00.385280 # ok 3101 Set Streaming SVE VL 4192
4833 12:29:00.385374 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4834 12:29:00.385622 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4835 12:29:00.385735 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4836 12:29:00.385831 # ok 3105 Set Streaming SVE VL 4208
4837 12:29:00.386113 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4838 12:29:00.386193 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4839 12:29:00.391812 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4840 12:29:00.391985 # ok 3109 Set Streaming SVE VL 4224
4841 12:29:00.392137 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4842 12:29:00.392260 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4843 12:29:00.392520 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4844 12:29:00.392594 # ok 3113 Set Streaming SVE VL 4240
4845 12:29:00.392687 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4846 12:29:00.392954 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4847 12:29:00.393040 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4848 12:29:00.393128 # ok 3117 Set Streaming SVE VL 4256
4849 12:29:00.393394 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4850 12:29:00.393480 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4851 12:29:00.393737 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4852 12:29:00.393824 # ok 3121 Set Streaming SVE VL 4272
4853 12:29:00.393913 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4854 12:29:00.399687 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4855 12:29:00.399987 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4856 12:29:00.400097 # ok 3125 Set Streaming SVE VL 4288
4857 12:29:00.400197 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4858 12:29:00.400276 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4859 12:29:00.400352 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4860 12:29:00.400429 # ok 3129 Set Streaming SVE VL 4304
4861 12:29:00.400534 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4862 12:29:00.400860 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4863 12:29:00.400988 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4864 12:29:00.401097 # ok 3133 Set Streaming SVE VL 4320
4865 12:29:00.401200 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4866 12:29:00.401289 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4867 12:29:00.401551 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4868 12:29:00.401652 # ok 3137 Set Streaming SVE VL 4336
4869 12:29:00.401742 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4870 12:29:00.405811 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4871 12:29:00.407182 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4872 12:29:00.407508 # ok 3141 Set Streaming SVE VL 4352
4873 12:29:00.407600 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4874 12:29:00.407699 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4875 12:29:00.407780 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4876 12:29:00.407859 # ok 3145 Set Streaming SVE VL 4368
4877 12:29:00.408126 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4878 12:29:00.408217 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4879 12:29:00.408491 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4880 12:29:00.408566 # ok 3149 Set Streaming SVE VL 4384
4881 12:29:00.408657 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4882 12:29:00.408916 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4883 12:29:00.409006 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4884 12:29:00.409091 # ok 3153 Set Streaming SVE VL 4400
4885 12:29:00.409353 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4886 12:29:00.409642 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4887 12:29:00.409764 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4888 12:29:00.409854 # ok 3157 Set Streaming SVE VL 4416
4889 12:29:00.409942 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4890 12:29:00.410033 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4891 12:29:00.410333 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4892 12:29:00.415470 # ok 3161 Set Streaming SVE VL 4432
4893 12:29:00.415848 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4894 12:29:00.415953 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4895 12:29:00.416043 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4896 12:29:00.416132 # ok 3165 Set Streaming SVE VL 4448
4897 12:29:00.416208 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4898 12:29:00.416293 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4899 12:29:00.416578 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4900 12:29:00.416676 # ok 3169 Set Streaming SVE VL 4464
4901 12:29:00.416763 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4902 12:29:00.416868 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4903 12:29:00.416990 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4904 12:29:00.417079 # ok 3173 Set Streaming SVE VL 4480
4905 12:29:00.417180 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4906 12:29:00.417287 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4907 12:29:00.417600 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4908 12:29:00.425164 # ok 3177 Set Streaming SVE VL 4496
4909 12:29:00.425371 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4910 12:29:00.425480 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4911 12:29:00.425569 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4912 12:29:00.425695 # ok 3181 Set Streaming SVE VL 4512
4913 12:29:00.425814 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4914 12:29:00.431244 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4915 12:29:00.431598 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4916 12:29:00.431687 # ok 3185 Set Streaming SVE VL 4528
4917 12:29:00.431959 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4918 12:29:00.432070 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4919 12:29:00.432368 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4920 12:29:00.432468 # ok 3189 Set Streaming SVE VL 4544
4921 12:29:00.432759 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4922 12:29:00.432853 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4923 12:29:00.432946 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4924 12:29:00.433032 # ok 3193 Set Streaming SVE VL 4560
4925 12:29:00.433311 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4926 12:29:00.433429 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4927 12:29:00.433691 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4928 12:29:00.433798 # ok 3197 Set Streaming SVE VL 4576
4929 12:29:00.434100 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4930 12:29:00.437546 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4931 12:29:00.437908 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4932 12:29:00.438011 # ok 3201 Set Streaming SVE VL 4592
4933 12:29:00.438123 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4934 12:29:00.448145 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4935 12:29:00.448419 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4936 12:29:00.448653 # ok 3205 Set Streaming SVE VL 4608
4937 12:29:00.448834 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4938 12:29:00.449027 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4939 12:29:00.449224 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4940 12:29:00.449489 # ok 3209 Set Streaming SVE VL 4624
4941 12:29:00.449692 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4942 12:29:00.449892 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4943 12:29:00.450041 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4944 12:29:00.450164 # ok 3213 Set Streaming SVE VL 4640
4945 12:29:00.450280 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4946 12:29:00.450421 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4947 12:29:00.450541 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4948 12:29:00.450656 # ok 3217 Set Streaming SVE VL 4656
4949 12:29:00.455823 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4950 12:29:00.456234 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4951 12:29:00.456407 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4952 12:29:00.456602 # ok 3221 Set Streaming SVE VL 4672
4953 12:29:00.456830 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4954 12:29:00.457021 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4955 12:29:00.457212 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4956 12:29:00.457415 # ok 3225 Set Streaming SVE VL 4688
4957 12:29:00.457631 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4958 12:29:00.457818 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4959 12:29:00.457991 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4960 12:29:00.458139 # ok 3229 Set Streaming SVE VL 4704
4961 12:29:00.458281 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4962 12:29:00.458425 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4963 12:29:00.458603 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4964 12:29:00.458741 # ok 3233 Set Streaming SVE VL 4720
4965 12:29:00.459134 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4966 12:29:00.459358 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4967 12:29:00.459550 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4968 12:29:00.459704 # ok 3237 Set Streaming SVE VL 4736
4969 12:29:00.459870 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4970 12:29:00.460062 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4971 12:29:00.460246 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4972 12:29:00.460399 # ok 3241 Set Streaming SVE VL 4752
4973 12:29:00.460556 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4974 12:29:00.460693 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4975 12:29:00.460820 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4976 12:29:00.460948 # ok 3245 Set Streaming SVE VL 4768
4977 12:29:00.461071 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4978 12:29:00.461223 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4979 12:29:00.461356 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4980 12:29:00.461483 # ok 3249 Set Streaming SVE VL 4784
4981 12:29:00.461607 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4982 12:29:00.461754 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4983 12:29:00.461967 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4984 12:29:00.462106 # ok 3253 Set Streaming SVE VL 4800
4985 12:29:00.462247 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4986 12:29:00.462392 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4987 12:29:00.470936 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4988 12:29:00.471494 # ok 3257 Set Streaming SVE VL 4816
4989 12:29:00.471707 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4990 12:29:00.471906 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4991 12:29:00.472126 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4992 12:29:00.472349 # ok 3261 Set Streaming SVE VL 4832
4993 12:29:00.472596 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4994 12:29:00.472790 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4995 12:29:00.472966 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4996 12:29:00.473131 # ok 3265 Set Streaming SVE VL 4848
4997 12:29:00.473298 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4998 12:29:00.473476 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4999 12:29:00.473656 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
5000 12:29:00.473841 # ok 3269 Set Streaming SVE VL 4864
5001 12:29:00.474028 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
5002 12:29:00.474172 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
5003 12:29:00.474293 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5004 12:29:00.474410 # ok 3273 Set Streaming SVE VL 4880
5005 12:29:00.474528 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5006 12:29:00.474643 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5007 12:29:00.474759 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5008 12:29:00.474871 # ok 3277 Set Streaming SVE VL 4896
5009 12:29:00.474986 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5010 12:29:00.475100 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5011 12:29:00.487057 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5012 12:29:00.487331 # ok 3281 Set Streaming SVE VL 4912
5013 12:29:00.487747 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5014 12:29:00.487940 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5015 12:29:00.488135 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5016 12:29:00.488328 # ok 3285 Set Streaming SVE VL 4928
5017 12:29:00.488522 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5018 12:29:00.488695 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5019 12:29:00.488878 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5020 12:29:00.489004 # ok 3289 Set Streaming SVE VL 4944
5021 12:29:00.489120 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5022 12:29:00.489235 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5023 12:29:00.489349 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5024 12:29:00.489467 # ok 3293 Set Streaming SVE VL 4960
5025 12:29:00.489582 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5026 12:29:00.489755 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5027 12:29:00.489956 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5028 12:29:00.503271 # ok 3297 Set Streaming SVE VL 4976
5029 12:29:00.503563 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5030 12:29:00.504049 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5031 12:29:00.504265 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5032 12:29:00.504441 # ok 3301 Set Streaming SVE VL 4992
5033 12:29:00.504601 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5034 12:29:00.504762 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5035 12:29:00.504924 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5036 12:29:00.505109 # ok 3305 Set Streaming SVE VL 5008
5037 12:29:00.505273 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5038 12:29:00.505427 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5039 12:29:00.505581 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5040 12:29:00.505753 # ok 3309 Set Streaming SVE VL 5024
5041 12:29:00.505910 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5042 12:29:00.506058 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5043 12:29:00.506202 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5044 12:29:00.506381 # ok 3313 Set Streaming SVE VL 5040
5045 12:29:00.506512 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5046 12:29:00.506624 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5047 12:29:00.506734 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5048 12:29:00.509834 # ok 3317 Set Streaming SVE VL 5056
5049 12:29:00.519269 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5050 12:29:00.519796 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5051 12:29:00.520025 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5052 12:29:00.520188 # ok 3321 Set Streaming SVE VL 5072
5053 12:29:00.520332 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5054 12:29:00.520507 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5055 12:29:00.520633 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5056 12:29:00.520750 # ok 3325 Set Streaming SVE VL 5088
5057 12:29:00.520866 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5058 12:29:00.521509 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5059 12:29:00.521779 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5060 12:29:00.521965 # ok 3329 Set Streaming SVE VL 5104
5061 12:29:00.522092 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5062 12:29:00.539132 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5063 12:29:00.539429 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5064 12:29:00.539868 # ok 3333 Set Streaming SVE VL 5120
5065 12:29:00.540057 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5066 12:29:00.540216 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5067 12:29:00.540376 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5068 12:29:00.540534 # ok 3337 Set Streaming SVE VL 5136
5069 12:29:00.540683 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5070 12:29:00.540879 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5071 12:29:00.541023 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5072 12:29:00.541176 # ok 3341 Set Streaming SVE VL 5152
5073 12:29:00.541334 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5074 12:29:00.541493 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5075 12:29:00.541659 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5076 12:29:00.541819 # ok 3345 Set Streaming SVE VL 5168
5077 12:29:00.541938 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5078 12:29:00.542052 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5079 12:29:00.542194 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5080 12:29:00.542329 # ok 3349 Set Streaming SVE VL 5184
5081 12:29:00.542448 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5082 12:29:00.542566 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5083 12:29:00.542680 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5084 12:29:00.542793 # ok 3353 Set Streaming SVE VL 5200
5085 12:29:00.551914 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5086 12:29:00.552259 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5087 12:29:00.552355 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5088 12:29:00.552438 # ok 3357 Set Streaming SVE VL 5216
5089 12:29:00.552513 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5090 12:29:00.552605 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5091 12:29:00.552682 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5092 12:29:00.552769 # ok 3361 Set Streaming SVE VL 5232
5093 12:29:00.552860 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5094 12:29:00.552947 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5095 12:29:00.553248 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5096 12:29:00.553341 # ok 3365 Set Streaming SVE VL 5248
5097 12:29:00.553416 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5098 12:29:00.553506 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5099 12:29:00.553593 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5100 12:29:00.553702 # ok 3369 Set Streaming SVE VL 5264
5101 12:29:00.553788 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5102 12:29:00.553887 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5103 12:29:00.556957 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5104 12:29:00.557407 # ok 3373 Set Streaming SVE VL 5280
5105 12:29:00.557602 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5106 12:29:00.557768 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5107 12:29:00.557912 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5108 12:29:00.558055 # ok 3377 Set Streaming SVE VL 5296
5109 12:29:00.558174 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5110 12:29:00.558289 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5111 12:29:00.561827 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5112 12:29:00.561986 # ok 3381 Set Streaming SVE VL 5312
5113 12:29:00.567644 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5114 12:29:00.568103 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5115 12:29:00.568304 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5116 12:29:00.568454 # ok 3385 Set Streaming SVE VL 5328
5117 12:29:00.568623 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5118 12:29:00.568815 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5119 12:29:00.568981 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5120 12:29:00.569150 # ok 3389 Set Streaming SVE VL 5344
5121 12:29:00.569290 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5122 12:29:00.569420 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5123 12:29:00.569594 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5124 12:29:00.569812 # ok 3393 Set Streaming SVE VL 5360
5125 12:29:00.570002 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5126 12:29:00.570176 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5127 12:29:00.570319 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5128 12:29:00.570462 # ok 3397 Set Streaming SVE VL 5376
5129 12:29:00.570637 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5130 12:29:00.572459 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5131 12:29:00.572863 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5132 12:29:00.573042 # ok 3401 Set Streaming SVE VL 5392
5133 12:29:00.573234 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5134 12:29:00.573390 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5135 12:29:00.573632 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5136 12:29:00.573830 # ok 3405 Set Streaming SVE VL 5408
5137 12:29:00.573969 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5138 12:29:00.574112 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5139 12:29:00.581496 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5140 12:29:00.582032 # ok 3409 Set Streaming SVE VL 5424
5141 12:29:00.582176 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5142 12:29:00.584122 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5143 12:29:00.584498 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5144 12:29:00.584638 # ok 3413 Set Streaming SVE VL 5440
5145 12:29:00.584746 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5146 12:29:00.584876 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5147 12:29:00.584999 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5148 12:29:00.585149 # ok 3417 Set Streaming SVE VL 5456
5149 12:29:00.585330 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5150 12:29:00.585480 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5151 12:29:00.585697 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5152 12:29:00.585849 # ok 3421 Set Streaming SVE VL 5472
5153 12:29:00.585987 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5154 12:29:00.586091 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5155 12:29:00.588207 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5156 12:29:00.588594 # ok 3425 Set Streaming SVE VL 5488
5157 12:29:00.588791 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5158 12:29:00.588988 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5159 12:29:00.589158 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5160 12:29:00.589296 # ok 3429 Set Streaming SVE VL 5504
5161 12:29:00.589453 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5162 12:29:00.589597 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5163 12:29:00.589821 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5164 12:29:00.589976 # ok 3433 Set Streaming SVE VL 5520
5165 12:29:00.590101 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5166 12:29:00.590240 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5167 12:29:00.599503 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5168 12:29:00.599792 # ok 3437 Set Streaming SVE VL 5536
5169 12:29:00.600216 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5170 12:29:00.600316 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5171 12:29:00.600405 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5172 12:29:00.600501 # ok 3441 Set Streaming SVE VL 5552
5173 12:29:00.600580 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5174 12:29:00.600680 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5175 12:29:00.600758 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5176 12:29:00.600841 # ok 3445 Set Streaming SVE VL 5568
5177 12:29:00.600939 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5178 12:29:00.601039 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5179 12:29:00.601380 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5180 12:29:00.601590 # ok 3449 Set Streaming SVE VL 5584
5181 12:29:00.601932 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5182 12:29:00.602068 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5183 12:29:00.602186 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5184 12:29:00.605386 # ok 3453 Set Streaming SVE VL 5600
5185 12:29:00.605858 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5186 12:29:00.606019 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5187 12:29:00.607131 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5188 12:29:00.607583 # ok 3457 Set Streaming SVE VL 5616
5189 12:29:00.607778 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5190 12:29:00.607988 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5191 12:29:00.608202 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5192 12:29:00.608455 # ok 3461 Set Streaming SVE VL 5632
5193 12:29:00.608662 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5194 12:29:00.608878 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5195 12:29:00.609088 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5196 12:29:00.609289 # ok 3465 Set Streaming SVE VL 5648
5197 12:29:00.609472 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5198 12:29:00.609598 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5199 12:29:00.609828 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5200 12:29:00.610026 # ok 3469 Set Streaming SVE VL 5664
5201 12:29:00.610173 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5202 12:29:00.610318 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5203 12:29:00.610461 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5204 12:29:00.610603 # ok 3473 Set Streaming SVE VL 5680
5205 12:29:00.610743 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5206 12:29:00.610886 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5207 12:29:00.616776 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5208 12:29:00.616932 # ok 3477 Set Streaming SVE VL 5696
5209 12:29:00.617038 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5210 12:29:00.617129 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5211 12:29:00.617237 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5212 12:29:00.617342 # ok 3481 Set Streaming SVE VL 5712
5213 12:29:00.617644 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5214 12:29:00.617773 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5215 12:29:00.617877 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5216 12:29:00.623367 # ok 3485 Set Streaming SVE VL 5728
5217 12:29:00.623686 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5218 12:29:00.623850 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5219 12:29:00.624047 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5220 12:29:00.624235 # ok 3489 Set Streaming SVE VL 5744
5221 12:29:00.624402 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5222 12:29:00.624561 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5223 12:29:00.624682 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5224 12:29:00.624836 # ok 3493 Set Streaming SVE VL 5760
5225 12:29:00.624979 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5226 12:29:00.625117 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5227 12:29:00.625253 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5228 12:29:00.625446 # ok 3497 Set Streaming SVE VL 5776
5229 12:29:00.625619 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5230 12:29:00.625782 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5231 12:29:00.625905 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5232 12:29:00.626044 # ok 3501 Set Streaming SVE VL 5792
5233 12:29:00.626163 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5234 12:29:00.631321 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5235 12:29:00.631808 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5236 12:29:00.631977 # ok 3505 Set Streaming SVE VL 5808
5237 12:29:00.632182 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5238 12:29:00.632439 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5239 12:29:00.632664 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5240 12:29:00.632867 # ok 3509 Set Streaming SVE VL 5824
5241 12:29:00.633048 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5242 12:29:00.633180 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5243 12:29:00.633335 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5244 12:29:00.633469 # ok 3513 Set Streaming SVE VL 5840
5245 12:29:00.633605 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5246 12:29:00.633769 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5247 12:29:00.633889 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5248 12:29:00.634003 # ok 3517 Set Streaming SVE VL 5856
5249 12:29:00.634142 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5250 12:29:00.634261 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5251 12:29:00.634375 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5252 12:29:00.639504 # ok 3521 Set Streaming SVE VL 5872
5253 12:29:00.639979 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5254 12:29:00.640143 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5255 12:29:00.640290 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5256 12:29:00.640476 # ok 3525 Set Streaming SVE VL 5888
5257 12:29:00.640675 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5258 12:29:00.640854 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5259 12:29:00.641013 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5260 12:29:00.641178 # ok 3529 Set Streaming SVE VL 5904
5261 12:29:00.641349 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5262 12:29:00.641560 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5263 12:29:00.641738 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5264 12:29:00.641866 # ok 3533 Set Streaming SVE VL 5920
5265 12:29:00.641980 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5266 12:29:00.642093 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5267 12:29:00.642206 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5268 12:29:00.642342 # ok 3537 Set Streaming SVE VL 5936
5269 12:29:00.642692 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5270 12:29:00.642801 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5271 12:29:00.642904 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5272 12:29:00.643006 # ok 3541 Set Streaming SVE VL 5952
5273 12:29:00.643107 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5274 12:29:00.643210 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5275 12:29:00.643321 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5276 12:29:00.643626 # ok 3545 Set Streaming SVE VL 5968
5277 12:29:00.643739 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5278 12:29:00.643845 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5279 12:29:00.643947 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5280 12:29:00.644067 # ok 3549 Set Streaming SVE VL 5984
5281 12:29:00.644167 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5282 12:29:00.644449 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5283 12:29:00.644552 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5284 12:29:00.644639 # ok 3553 Set Streaming SVE VL 6000
5285 12:29:00.644925 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5286 12:29:00.645017 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5287 12:29:00.645107 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5288 12:29:00.645193 # ok 3557 Set Streaming SVE VL 6016
5289 12:29:00.645507 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5290 12:29:00.645697 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5291 12:29:00.645854 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5292 12:29:00.655572 # ok 3561 Set Streaming SVE VL 6032
5293 12:29:00.655902 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5294 12:29:00.656362 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5295 12:29:00.656568 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5296 12:29:00.656742 # ok 3565 Set Streaming SVE VL 6048
5297 12:29:00.656916 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5298 12:29:00.657066 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5299 12:29:00.657243 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5300 12:29:00.657407 # ok 3569 Set Streaming SVE VL 6064
5301 12:29:00.657559 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5302 12:29:00.657728 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5303 12:29:00.657901 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5304 12:29:00.658045 # ok 3573 Set Streaming SVE VL 6080
5305 12:29:00.658227 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5306 12:29:00.658363 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5307 12:29:00.658506 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5308 12:29:00.663297 # ok 3577 Set Streaming SVE VL 6096
5309 12:29:00.663843 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5310 12:29:00.664045 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5311 12:29:00.664207 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5312 12:29:00.664362 # ok 3581 Set Streaming SVE VL 6112
5313 12:29:00.664503 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5314 12:29:00.664671 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5315 12:29:00.664806 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5316 12:29:00.664963 # ok 3585 Set Streaming SVE VL 6128
5317 12:29:00.665119 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5318 12:29:00.665287 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5319 12:29:00.665526 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5320 12:29:00.665734 # ok 3589 Set Streaming SVE VL 6144
5321 12:29:00.665905 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5322 12:29:00.666034 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5323 12:29:00.666151 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5324 12:29:00.666264 # ok 3593 Set Streaming SVE VL 6160
5325 12:29:00.666376 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5326 12:29:00.666563 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5327 12:29:00.672280 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5328 12:29:00.672618 # ok 3597 Set Streaming SVE VL 6176
5329 12:29:00.673063 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5330 12:29:00.673258 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5331 12:29:00.673426 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5332 12:29:00.673588 # ok 3601 Set Streaming SVE VL 6192
5333 12:29:00.673756 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5334 12:29:00.673909 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5335 12:29:00.674029 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5336 12:29:00.674143 # ok 3605 Set Streaming SVE VL 6208
5337 12:29:00.674256 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5338 12:29:00.674370 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5339 12:29:00.679091 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5340 12:29:00.679616 # ok 3609 Set Streaming SVE VL 6224
5341 12:29:00.679758 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5342 12:29:00.679889 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5343 12:29:00.680013 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5344 12:29:00.680140 # ok 3613 Set Streaming SVE VL 6240
5345 12:29:00.680327 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5346 12:29:00.680502 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5347 12:29:00.680715 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5348 12:29:00.680874 # ok 3617 Set Streaming SVE VL 6256
5349 12:29:00.680997 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5350 12:29:00.681153 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5351 12:29:00.681278 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5352 12:29:00.681394 # ok 3621 Set Streaming SVE VL 6272
5353 12:29:00.681509 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5354 12:29:00.681673 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5355 12:29:00.681809 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5356 12:29:00.681924 # ok 3625 Set Streaming SVE VL 6288
5357 12:29:00.696082 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5358 12:29:00.696703 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5359 12:29:00.696927 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5360 12:29:00.697152 # ok 3629 Set Streaming SVE VL 6304
5361 12:29:00.697358 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5362 12:29:00.697539 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5363 12:29:00.697788 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5364 12:29:00.697953 # ok 3633 Set Streaming SVE VL 6320
5365 12:29:00.698097 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5366 12:29:00.698241 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5367 12:29:00.698383 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5368 12:29:00.698527 # ok 3637 Set Streaming SVE VL 6336
5369 12:29:00.698669 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5370 12:29:00.698810 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5371 12:29:00.703381 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5372 12:29:00.703762 # ok 3641 Set Streaming SVE VL 6352
5373 12:29:00.703952 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5374 12:29:00.704168 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5375 12:29:00.704337 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5376 12:29:00.704522 # ok 3645 Set Streaming SVE VL 6368
5377 12:29:00.704707 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5378 12:29:00.704888 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5379 12:29:00.705054 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5380 12:29:00.705231 # ok 3649 Set Streaming SVE VL 6384
5381 12:29:00.705386 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5382 12:29:00.705534 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5383 12:29:00.705731 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5384 12:29:00.705861 # ok 3653 Set Streaming SVE VL 6400
5385 12:29:00.705976 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5386 12:29:00.706090 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5387 12:29:00.706204 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5388 12:29:00.706316 # ok 3657 Set Streaming SVE VL 6416
5389 12:29:00.710581 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5390 12:29:00.711081 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5391 12:29:00.711275 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5392 12:29:00.711436 # ok 3661 Set Streaming SVE VL 6432
5393 12:29:00.711622 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5394 12:29:00.711778 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5395 12:29:00.711935 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5396 12:29:00.712133 # ok 3665 Set Streaming SVE VL 6448
5397 12:29:00.712303 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5398 12:29:00.712528 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5399 12:29:00.712729 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5400 12:29:00.712905 # ok 3669 Set Streaming SVE VL 6464
5401 12:29:00.713080 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5402 12:29:00.713210 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5403 12:29:00.713323 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5404 12:29:00.713435 # ok 3673 Set Streaming SVE VL 6480
5405 12:29:00.713592 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5406 12:29:00.713843 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5407 12:29:00.714045 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5408 12:29:00.714232 # ok 3677 Set Streaming SVE VL 6496
5409 12:29:00.714406 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5410 12:29:00.714548 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5411 12:29:00.714689 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5412 12:29:00.714831 # ok 3681 Set Streaming SVE VL 6512
5413 12:29:00.714971 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5414 12:29:00.718926 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5415 12:29:00.719462 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5416 12:29:00.719567 # ok 3685 Set Streaming SVE VL 6528
5417 12:29:00.719648 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5418 12:29:00.719723 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5419 12:29:00.719799 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5420 12:29:00.719895 # ok 3689 Set Streaming SVE VL 6544
5421 12:29:00.719970 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5422 12:29:00.720042 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5423 12:29:00.720142 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5424 12:29:00.720222 # ok 3693 Set Streaming SVE VL 6560
5425 12:29:00.720310 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5426 12:29:00.720401 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5427 12:29:00.720681 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5428 12:29:00.720844 # ok 3697 Set Streaming SVE VL 6576
5429 12:29:00.721018 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5430 12:29:00.721162 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5431 12:29:00.721319 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5432 12:29:00.721450 # ok 3701 Set Streaming SVE VL 6592
5433 12:29:00.721601 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5434 12:29:00.721782 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5435 12:29:00.726597 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5436 12:29:00.727160 # ok 3705 Set Streaming SVE VL 6608
5437 12:29:00.727368 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5438 12:29:00.727568 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5439 12:29:00.727764 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5440 12:29:00.727996 # ok 3709 Set Streaming SVE VL 6624
5441 12:29:00.728194 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5442 12:29:00.728386 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5443 12:29:00.728591 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5444 12:29:00.728747 # ok 3713 Set Streaming SVE VL 6640
5445 12:29:00.728910 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5446 12:29:00.729098 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5447 12:29:00.729302 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5448 12:29:00.729482 # ok 3717 Set Streaming SVE VL 6656
5449 12:29:00.729687 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5450 12:29:00.729836 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5451 12:29:00.729962 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5452 12:29:00.730078 # ok 3721 Set Streaming SVE VL 6672
5453 12:29:00.730192 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5454 12:29:00.730306 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5455 12:29:00.730420 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5456 12:29:00.730535 # ok 3725 Set Streaming SVE VL 6688
5457 12:29:00.730679 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5458 12:29:00.730802 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5459 12:29:00.740920 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5460 12:29:00.741248 # ok 3729 Set Streaming SVE VL 6704
5461 12:29:00.741460 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5462 12:29:00.741863 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5463 12:29:00.742023 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5464 12:29:00.742146 # ok 3733 Set Streaming SVE VL 6720
5465 12:29:00.742366 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5466 12:29:00.742603 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5467 12:29:00.742790 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5468 12:29:00.742986 # ok 3737 Set Streaming SVE VL 6736
5469 12:29:00.743149 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5470 12:29:00.743306 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5471 12:29:00.743491 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5472 12:29:00.743648 # ok 3741 Set Streaming SVE VL 6752
5473 12:29:00.743828 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5474 12:29:00.743982 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5475 12:29:00.744149 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5476 12:29:00.744298 # ok 3745 Set Streaming SVE VL 6768
5477 12:29:00.744466 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5478 12:29:00.744871 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5479 12:29:00.745094 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5480 12:29:00.745278 # ok 3749 Set Streaming SVE VL 6784
5481 12:29:00.745492 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5482 12:29:00.745675 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5483 12:29:00.752616 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5484 12:29:00.753138 # ok 3753 Set Streaming SVE VL 6800
5485 12:29:00.753324 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5486 12:29:00.753490 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5487 12:29:00.753655 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5488 12:29:00.753786 # ok 3757 Set Streaming SVE VL 6816
5489 12:29:00.753931 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5490 12:29:00.754054 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5491 12:29:00.754204 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5492 12:29:00.754363 # ok 3761 Set Streaming SVE VL 6832
5493 12:29:00.754554 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5494 12:29:00.754719 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5495 12:29:00.754897 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5496 12:29:00.755037 # ok 3765 Set Streaming SVE VL 6848
5497 12:29:00.755164 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5498 12:29:00.755322 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5499 12:29:00.755464 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5500 12:29:00.755632 # ok 3769 Set Streaming SVE VL 6864
5501 12:29:00.755828 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5502 12:29:00.756011 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5503 12:29:00.756179 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5504 12:29:00.756309 # ok 3773 Set Streaming SVE VL 6880
5505 12:29:00.756449 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5506 12:29:00.757224 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5507 12:29:00.757633 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5508 12:29:00.757802 # ok 3777 Set Streaming SVE VL 6896
5509 12:29:00.757974 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5510 12:29:00.771313 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5511 12:29:00.771645 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5512 12:29:00.772113 # ok 3781 Set Streaming SVE VL 6912
5513 12:29:00.772306 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5514 12:29:00.772479 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5515 12:29:00.772667 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5516 12:29:00.772838 # ok 3785 Set Streaming SVE VL 6928
5517 12:29:00.772987 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5518 12:29:00.773181 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5519 12:29:00.773332 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5520 12:29:00.773498 # ok 3789 Set Streaming SVE VL 6944
5521 12:29:00.773711 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5522 12:29:00.773919 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5523 12:29:00.774154 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5524 12:29:00.774312 # ok 3793 Set Streaming SVE VL 6960
5525 12:29:00.774458 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5526 12:29:00.774600 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5527 12:29:00.774740 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5528 12:29:00.774879 # ok 3797 Set Streaming SVE VL 6976
5529 12:29:00.775023 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5530 12:29:00.782606 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5531 12:29:00.783153 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5532 12:29:00.783308 # ok 3801 Set Streaming SVE VL 6992
5533 12:29:00.783455 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5534 12:29:00.783599 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5535 12:29:00.783775 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5536 12:29:00.783910 # ok 3805 Set Streaming SVE VL 7008
5537 12:29:00.784054 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5538 12:29:00.784196 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5539 12:29:00.784337 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5540 12:29:00.784512 # ok 3809 Set Streaming SVE VL 7024
5541 12:29:00.784647 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5542 12:29:00.784787 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5543 12:29:00.784928 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5544 12:29:00.785072 # ok 3813 Set Streaming SVE VL 7040
5545 12:29:00.785248 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5546 12:29:00.785382 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5547 12:29:00.785523 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5548 12:29:00.785678 # ok 3817 Set Streaming SVE VL 7056
5549 12:29:00.785821 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5550 12:29:00.785962 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5551 12:29:00.786138 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5552 12:29:00.786273 # ok 3821 Set Streaming SVE VL 7072
5553 12:29:00.794664 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5554 12:29:00.795240 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5555 12:29:00.795451 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5556 12:29:00.795624 # ok 3825 Set Streaming SVE VL 7088
5557 12:29:00.795838 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5558 12:29:00.796084 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5559 12:29:00.796293 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5560 12:29:00.796493 # ok 3829 Set Streaming SVE VL 7104
5561 12:29:00.796692 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5562 12:29:00.796903 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5563 12:29:00.797099 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5564 12:29:00.797252 # ok 3833 Set Streaming SVE VL 7120
5565 12:29:00.797433 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5566 12:29:00.797675 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5567 12:29:00.797860 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5568 12:29:00.797999 # ok 3837 Set Streaming SVE VL 7136
5569 12:29:00.798116 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5570 12:29:00.798229 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5571 12:29:00.798341 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5572 12:29:00.798453 # ok 3841 Set Streaming SVE VL 7152
5573 12:29:00.798566 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5574 12:29:00.798679 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5575 12:29:00.798792 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5576 12:29:00.798906 # ok 3845 Set Streaming SVE VL 7168
5577 12:29:00.799019 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5578 12:29:00.803993 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5579 12:29:00.804555 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5580 12:29:00.804791 # ok 3849 Set Streaming SVE VL 7184
5581 12:29:00.805030 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5582 12:29:00.805239 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5583 12:29:00.805429 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5584 12:29:00.805587 # ok 3853 Set Streaming SVE VL 7200
5585 12:29:00.805797 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5586 12:29:00.805926 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5587 12:29:00.806046 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5588 12:29:00.806159 # ok 3857 Set Streaming SVE VL 7216
5589 12:29:00.806271 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5590 12:29:00.806382 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5591 12:29:00.806495 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5592 12:29:00.806608 # ok 3861 Set Streaming SVE VL 7232
5593 12:29:00.806719 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5594 12:29:00.814533 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5595 12:29:00.815144 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5596 12:29:00.815385 # ok 3865 Set Streaming SVE VL 7248
5597 12:29:00.815617 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5598 12:29:00.815825 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5599 12:29:00.815988 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5600 12:29:00.816192 # ok 3869 Set Streaming SVE VL 7264
5601 12:29:00.816330 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5602 12:29:00.816456 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5603 12:29:00.816583 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5604 12:29:00.816707 # ok 3873 Set Streaming SVE VL 7280
5605 12:29:00.816828 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5606 12:29:00.816950 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5607 12:29:00.817104 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5608 12:29:00.817231 # ok 3877 Set Streaming SVE VL 7296
5609 12:29:00.817356 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5610 12:29:00.817496 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5611 12:29:00.817642 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5612 12:29:00.817817 # ok 3881 Set Streaming SVE VL 7312
5613 12:29:00.817939 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5614 12:29:00.818088 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5615 12:29:00.818211 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5616 12:29:00.818328 # ok 3885 Set Streaming SVE VL 7328
5617 12:29:00.818442 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5618 12:29:00.826745 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5619 12:29:00.827332 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5620 12:29:00.827517 # ok 3889 Set Streaming SVE VL 7344
5621 12:29:00.827720 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5622 12:29:00.827923 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5623 12:29:00.828190 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5624 12:29:00.828449 # ok 3893 Set Streaming SVE VL 7360
5625 12:29:00.828644 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5626 12:29:00.828860 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5627 12:29:00.829055 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5628 12:29:00.829252 # ok 3897 Set Streaming SVE VL 7376
5629 12:29:00.829420 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5630 12:29:00.829591 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5631 12:29:00.829815 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5632 12:29:00.829953 # ok 3901 Set Streaming SVE VL 7392
5633 12:29:00.830072 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5634 12:29:00.830187 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5635 12:29:00.830299 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5636 12:29:00.830411 # ok 3905 Set Streaming SVE VL 7408
5637 12:29:00.830522 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5638 12:29:00.830635 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5639 12:29:00.830746 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5640 12:29:00.830857 # ok 3909 Set Streaming SVE VL 7424
5641 12:29:00.830968 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5642 12:29:00.837986 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5643 12:29:00.840184 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5644 12:29:00.840518 # ok 3913 Set Streaming SVE VL 7440
5645 12:29:00.840722 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5646 12:29:00.840899 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5647 12:29:00.841064 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5648 12:29:00.841205 # ok 3917 Set Streaming SVE VL 7456
5649 12:29:00.841377 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5650 12:29:00.841500 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5651 12:29:00.841615 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5652 12:29:00.841744 # ok 3921 Set Streaming SVE VL 7472
5653 12:29:00.841860 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5654 12:29:00.841975 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5655 12:29:00.842090 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5656 12:29:00.882807 # ok 3925 Set Streaming SVE VL 7488
5657 12:29:00.883356 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5658 12:29:00.883463 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5659 12:29:00.883554 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5660 12:29:00.883640 # ok 3929 Set Streaming SVE VL 7504
5661 12:29:00.883726 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5662 12:29:00.883829 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5663 12:29:00.883918 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5664 12:29:00.884003 # ok 3933 Set Streaming SVE VL 7520
5665 12:29:00.884090 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5666 12:29:00.884198 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5667 12:29:00.884284 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5668 12:29:00.884385 # ok 3937 Set Streaming SVE VL 7536
5669 12:29:00.884486 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5670 12:29:00.884786 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5671 12:29:00.884885 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5672 12:29:00.884987 # ok 3941 Set Streaming SVE VL 7552
5673 12:29:00.885273 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5674 12:29:00.885374 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5675 12:29:00.885481 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5676 12:29:00.885582 # ok 3945 Set Streaming SVE VL 7568
5677 12:29:00.885682 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5678 12:29:00.885961 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5679 12:29:00.900214 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5680 12:29:00.900464 # ok 3949 Set Streaming SVE VL 7584
5681 12:29:00.900766 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5682 12:29:00.900864 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5683 12:29:00.900956 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5684 12:29:00.901060 # ok 3953 Set Streaming SVE VL 7600
5685 12:29:00.901145 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5686 12:29:00.901234 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5687 12:29:00.901319 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5688 12:29:00.901419 # ok 3957 Set Streaming SVE VL 7616
5689 12:29:00.901509 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5690 12:29:00.902541 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5691 12:29:00.902842 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5692 12:29:00.902939 # ok 3961 Set Streaming SVE VL 7632
5693 12:29:00.903026 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5694 12:29:00.903127 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5695 12:29:00.903417 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5696 12:29:00.903507 # ok 3965 Set Streaming SVE VL 7648
5697 12:29:00.903607 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5698 12:29:00.903882 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5699 12:29:00.903974 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5700 12:29:00.904059 # ok 3969 Set Streaming SVE VL 7664
5701 12:29:00.904163 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5702 12:29:00.904253 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5703 12:29:00.904536 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5704 12:29:00.904641 # ok 3973 Set Streaming SVE VL 7680
5705 12:29:00.904727 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5706 12:29:00.905002 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5707 12:29:00.905093 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5708 12:29:00.905183 # ok 3977 Set Streaming SVE VL 7696
5709 12:29:00.905281 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5710 12:29:00.905368 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5711 12:29:00.905488 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5712 12:29:00.909753 # ok 3981 Set Streaming SVE VL 7712
5713 12:29:00.910065 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5714 12:29:00.910151 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5715 12:29:00.910232 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5716 12:29:00.910325 # ok 3985 Set Streaming SVE VL 7728
5717 12:29:00.910433 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5718 12:29:00.910525 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5719 12:29:00.910786 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5720 12:29:00.910858 # ok 3989 Set Streaming SVE VL 7744
5721 12:29:00.910926 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5722 12:29:00.911001 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5723 12:29:00.911079 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5724 12:29:00.911146 # ok 3993 Set Streaming SVE VL 7760
5725 12:29:00.911221 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5726 12:29:00.911329 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5727 12:29:00.911656 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5728 12:29:00.911743 # ok 3997 Set Streaming SVE VL 7776
5729 12:29:00.911866 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5730 12:29:00.911970 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5731 12:29:00.912075 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5732 12:29:00.912152 # ok 4001 Set Streaming SVE VL 7792
5733 12:29:00.912408 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5734 12:29:00.912487 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5735 12:29:00.912561 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5736 12:29:00.912624 # ok 4005 Set Streaming SVE VL 7808
5737 12:29:00.912697 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5738 12:29:00.912964 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5739 12:29:00.913045 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5740 12:29:00.913110 # ok 4009 Set Streaming SVE VL 7824
5741 12:29:00.913183 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5742 12:29:00.913270 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5743 12:29:00.916748 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5744 12:29:00.917045 # ok 4013 Set Streaming SVE VL 7840
5745 12:29:00.917139 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5746 12:29:00.917216 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5747 12:29:00.917304 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5748 12:29:00.917392 # ok 4017 Set Streaming SVE VL 7856
5749 12:29:00.917479 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5750 12:29:00.917552 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5751 12:29:00.919593 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5752 12:29:00.919916 # ok 4021 Set Streaming SVE VL 7872
5753 12:29:00.920083 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5754 12:29:00.920216 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5755 12:29:00.920372 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5756 12:29:00.920503 # ok 4025 Set Streaming SVE VL 7888
5757 12:29:00.920628 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5758 12:29:00.920752 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5759 12:29:00.920906 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5760 12:29:00.921037 # ok 4029 Set Streaming SVE VL 7904
5761 12:29:00.921166 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5762 12:29:00.921294 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5763 12:29:00.921450 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5764 12:29:00.921597 # ok 4033 Set Streaming SVE VL 7920
5765 12:29:00.921765 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5766 12:29:00.921892 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5767 12:29:00.922010 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5768 12:29:00.922126 # ok 4037 Set Streaming SVE VL 7936
5769 12:29:00.922242 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5770 12:29:00.925724 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5771 12:29:00.926024 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5772 12:29:00.926127 # ok 4041 Set Streaming SVE VL 7952
5773 12:29:00.926258 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5774 12:29:00.926357 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5775 12:29:00.926476 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5776 12:29:00.926586 # ok 4045 Set Streaming SVE VL 7968
5777 12:29:00.926695 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5778 12:29:00.926810 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5779 12:29:00.927111 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5780 12:29:00.927208 # ok 4049 Set Streaming SVE VL 7984
5781 12:29:00.927305 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5782 12:29:00.927395 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5783 12:29:00.927486 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5784 12:29:00.927746 # ok 4053 Set Streaming SVE VL 8000
5785 12:29:00.927821 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5786 12:29:00.927917 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5787 12:29:00.928035 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5788 12:29:00.928136 # ok 4057 Set Streaming SVE VL 8016
5789 12:29:00.928223 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5790 12:29:00.928335 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5791 12:29:00.928439 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5792 12:29:00.928549 # ok 4061 Set Streaming SVE VL 8032
5793 12:29:00.928847 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5794 12:29:00.928955 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5795 12:29:00.929067 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5796 12:29:00.929172 # ok 4065 Set Streaming SVE VL 8048
5797 12:29:00.929282 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5798 12:29:00.929376 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5799 12:29:00.931569 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5800 12:29:00.931864 # ok 4069 Set Streaming SVE VL 8064
5801 12:29:00.931972 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5802 12:29:00.932073 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5803 12:29:00.932186 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5804 12:29:00.932250 # ok 4073 Set Streaming SVE VL 8080
5805 12:29:00.932309 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5806 12:29:00.937535 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5807 12:29:00.939416 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5808 12:29:00.939585 # ok 4077 Set Streaming SVE VL 8096
5809 12:29:00.939954 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5810 12:29:00.940112 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5811 12:29:00.940244 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5812 12:29:00.940377 # ok 4081 Set Streaming SVE VL 8112
5813 12:29:00.940533 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5814 12:29:00.940666 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5815 12:29:00.940792 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5816 12:29:00.940919 # ok 4085 Set Streaming SVE VL 8128
5817 12:29:00.941046 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5818 12:29:00.941175 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5819 12:29:00.941298 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5820 12:29:00.941508 # ok 4089 Set Streaming SVE VL 8144
5821 12:29:00.941662 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5822 12:29:00.941786 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5823 12:29:00.941906 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5824 12:29:00.942025 # ok 4093 Set Streaming SVE VL 8160
5825 12:29:00.942142 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5826 12:29:00.942259 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5827 12:29:00.942379 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5828 12:29:00.945872 # ok 4097 Set Streaming SVE VL 8176
5829 12:29:00.946213 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5830 12:29:00.946397 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5831 12:29:00.946588 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5832 12:29:00.946801 # ok 4101 Set Streaming SVE VL 8192
5833 12:29:00.946942 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5834 12:29:00.947086 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5835 12:29:00.947228 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5836 12:29:00.947372 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5837 12:29:00.947514 ok 30 selftests: arm64: sve-ptrace
5838 12:29:00.947694 # selftests: arm64: sve-probe-vls
5839 12:29:00.947827 # TAP version 13
5840 12:29:00.947969 # 1..2
5841 12:29:00.948110 # ok 1 Enumerated 16 vector lengths
5842 12:29:00.948250 # ok 2 All vector lengths valid
5843 12:29:00.948392 # # 16
5844 12:29:00.948531 # # 32
5845 12:29:00.948672 # # 48
5846 12:29:00.948813 # # 64
5847 12:29:00.948954 # # 80
5848 12:29:00.949095 # # 96
5849 12:29:00.949236 # # 112
5850 12:29:00.949376 # # 128
5851 12:29:00.949516 # # 144
5852 12:29:00.949668 # # 160
5853 12:29:00.949811 # # 176
5854 12:29:00.949952 # # 192
5855 12:29:00.950093 # # 208
5856 12:29:00.950233 # # 224
5857 12:29:00.950375 # # 240
5858 12:29:00.950514 # # 256
5859 12:29:00.950654 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5860 12:29:00.950795 ok 31 selftests: arm64: sve-probe-vls
5861 12:29:00.975458 # selftests: arm64: vec-syscfg
5862 12:29:01.759143 # TAP version 13
5863 12:29:01.759432 # 1..20
5864 12:29:01.759810 # ok 1 SVE default vector length 64
5865 12:29:01.759957 # ok 2 SVE minimum vector length 16
5866 12:29:01.760150 # ok 3 SVE maximum vector length 256
5867 12:29:01.760330 # ok 4 SVE current VL is 64
5868 12:29:01.760498 # ok 5 SVE set VL 64 and have VL 64
5869 12:29:01.760674 # ok 6 SVE prctl() set min/max
5870 12:29:01.760858 # ok 7 SVE vector length used default
5871 12:29:01.761003 # ok 8 SVE vector length was inherited
5872 12:29:01.761123 # ok 9 SVE vector length set on exec
5873 12:29:01.761269 # ok 10 SVE prctl() set all VLs, 0 errors
5874 12:29:01.761390 # ok 11 SME default vector length 32
5875 12:29:01.761504 # ok 12 SME minimum vector length 16
5876 12:29:01.761617 # ok 13 SME maximum vector length 256
5877 12:29:01.761747 # ok 14 SME current VL is 32
5878 12:29:01.761860 # ok 15 SME set VL 32 and have VL 32
5879 12:29:01.761972 # ok 16 SME prctl() set min/max
5880 12:29:01.762084 # ok 17 SME vector length used default
5881 12:29:01.762196 # ok 18 SME vector length was inherited
5882 12:29:01.762307 # ok 19 SME vector length set on exec
5883 12:29:01.762419 # ok 20 SME prctl() set all VLs, 0 errors
5884 12:29:01.762530 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5885 12:29:01.780279 ok 32 selftests: arm64: vec-syscfg
5886 12:29:01.927590 # selftests: arm64: za-fork
5887 12:29:02.125942 # TAP version 13
5888 12:29:02.126222 # 1..1
5889 12:29:02.126353 # # PID: 1019
5890 12:29:02.126474 # ok 1 fork_test
5891 12:29:02.126815 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5892 12:29:02.143539 ok 33 selftests: arm64: za-fork
5893 12:29:02.262106 # selftests: arm64: za-ptrace
5894 12:29:02.386184 # TAP version 13
5895 12:29:02.386513 # 1..1536
5896 12:29:02.386686 # # Parent is 1037, child is 1038
5897 12:29:02.386856 # ok 1 Set VL 16
5898 12:29:02.387008 # ok 2 Disabled ZA for VL 16
5899 12:29:02.387156 # ok 3 Data match for VL 16
5900 12:29:02.387304 # ok 4 Set VL 32
5901 12:29:02.387469 # ok 5 Disabled ZA for VL 32
5902 12:29:02.387916 # ok 6 Data match for VL 32
5903 12:29:02.388121 # ok 7 Set VL 48
5904 12:29:02.388297 # ok 8 # SKIP Disabled ZA for VL 48
5905 12:29:02.388437 # ok 9 # SKIP Get and set data for VL 48
5906 12:29:02.388556 # ok 10 Set VL 64
5907 12:29:02.388672 # ok 11 Disabled ZA for VL 64
5908 12:29:02.388799 # ok 12 Data match for VL 64
5909 12:29:02.388918 # ok 13 Set VL 80
5910 12:29:02.389030 # ok 14 # SKIP Disabled ZA for VL 80
5911 12:29:02.389147 # ok 15 # SKIP Get and set data for VL 80
5912 12:29:02.389260 # ok 16 Set VL 96
5913 12:29:02.389372 # ok 17 # SKIP Disabled ZA for VL 96
5914 12:29:02.389485 # ok 18 # SKIP Get and set data for VL 96
5915 12:29:02.389597 # ok 19 Set VL 112
5916 12:29:02.389766 # ok 20 # SKIP Disabled ZA for VL 112
5917 12:29:02.389896 # ok 21 # SKIP Get and set data for VL 112
5918 12:29:02.390010 # ok 22 Set VL 128
5919 12:29:02.390125 # ok 23 Disabled ZA for VL 128
5920 12:29:02.390238 # ok 24 Data match for VL 128
5921 12:29:02.390351 # ok 25 Set VL 144
5922 12:29:02.390464 # ok 26 # SKIP Disabled ZA for VL 144
5923 12:29:02.390576 # ok 27 # SKIP Get and set data for VL 144
5924 12:29:02.390688 # ok 28 Set VL 160
5925 12:29:02.390829 # ok 29 # SKIP Disabled ZA for VL 160
5926 12:29:02.390951 # ok 30 # SKIP Get and set data for VL 160
5927 12:29:02.391069 # ok 31 Set VL 176
5928 12:29:02.391182 # ok 32 # SKIP Disabled ZA for VL 176
5929 12:29:02.394314 # ok 33 # SKIP Get and set data for VL 176
5930 12:29:02.394432 # ok 34 Set VL 192
5931 12:29:02.394723 # ok 35 # SKIP Disabled ZA for VL 192
5932 12:29:02.394827 # ok 36 # SKIP Get and set data for VL 192
5933 12:29:02.394916 # ok 37 Set VL 208
5934 12:29:02.395001 # ok 38 # SKIP Disabled ZA for VL 208
5935 12:29:02.395090 # ok 39 # SKIP Get and set data for VL 208
5936 12:29:02.395173 # ok 40 Set VL 224
5937 12:29:02.395275 # ok 41 # SKIP Disabled ZA for VL 224
5938 12:29:02.395362 # ok 42 # SKIP Get and set data for VL 224
5939 12:29:02.395448 # ok 43 Set VL 240
5940 12:29:02.395536 # ok 44 # SKIP Disabled ZA for VL 240
5941 12:29:02.395619 # ok 45 # SKIP Get and set data for VL 240
5942 12:29:02.395721 # ok 46 Set VL 256
5943 12:29:02.395808 # ok 47 Disabled ZA for VL 256
5944 12:29:02.395892 # ok 48 Data match for VL 256
5945 12:29:02.395977 # ok 49 Set VL 272
5946 12:29:02.396061 # ok 50 # SKIP Disabled ZA for VL 272
5947 12:29:02.396163 # ok 51 # SKIP Get and set data for VL 272
5948 12:29:02.396248 # ok 52 Set VL 288
5949 12:29:02.396328 # ok 53 # SKIP Disabled ZA for VL 288
5950 12:29:02.396405 # ok 54 # SKIP Get and set data for VL 288
5951 12:29:02.396497 # ok 55 Set VL 304
5952 12:29:02.396854 # ok 56 # SKIP Disabled ZA for VL 304
5953 12:29:02.397078 # ok 57 # SKIP Get and set data for VL 304
5954 12:29:02.397260 # ok 58 Set VL 320
5955 12:29:02.397425 # ok 59 # SKIP Disabled ZA for VL 320
5956 12:29:02.397584 # ok 60 # SKIP Get and set data for VL 320
5957 12:29:02.397752 # ok 61 Set VL 336
5958 12:29:02.397910 # ok 62 # SKIP Disabled ZA for VL 336
5959 12:29:02.398096 # ok 63 # SKIP Get and set data for VL 336
5960 12:29:02.398297 # ok 64 Set VL 352
5961 12:29:02.398448 # ok 65 # SKIP Disabled ZA for VL 352
5962 12:29:02.398620 # ok 66 # SKIP Get and set data for VL 352
5963 12:29:02.398824 # ok 67 Set VL 368
5964 12:29:02.398996 # ok 68 # SKIP Disabled ZA for VL 368
5965 12:29:02.399133 # ok 69 # SKIP Get and set data for VL 368
5966 12:29:02.399288 # ok 70 Set VL 384
5967 12:29:02.399432 # ok 71 # SKIP Disabled ZA for VL 384
5968 12:29:02.399613 # ok 72 # SKIP Get and set data for VL 384
5969 12:29:02.399808 # ok 73 Set VL 400
5970 12:29:02.399971 # ok 74 # SKIP Disabled ZA for VL 400
5971 12:29:02.400131 # ok 75 # SKIP Get and set data for VL 400
5972 12:29:02.400312 # ok 76 Set VL 416
5973 12:29:02.400478 # ok 77 # SKIP Disabled ZA for VL 416
5974 12:29:02.400604 # ok 78 # SKIP Get and set data for VL 416
5975 12:29:02.400720 # ok 79 Set VL 432
5976 12:29:02.400831 # ok 80 # SKIP Disabled ZA for VL 432
5977 12:29:02.400945 # ok 81 # SKIP Get and set data for VL 432
5978 12:29:02.401059 # ok 82 Set VL 448
5979 12:29:02.401173 # ok 83 # SKIP Disabled ZA for VL 448
5980 12:29:02.401284 # ok 84 # SKIP Get and set data for VL 448
5981 12:29:02.401396 # ok 85 Set VL 464
5982 12:29:02.401509 # ok 86 # SKIP Disabled ZA for VL 464
5983 12:29:02.401622 # ok 87 # SKIP Get and set data for VL 464
5984 12:29:02.401846 # ok 88 Set VL 480
5985 12:29:02.402037 # ok 89 # SKIP Disabled ZA for VL 480
5986 12:29:02.402218 # ok 90 # SKIP Get and set data for VL 480
5987 12:29:02.402399 # ok 91 Set VL 496
5988 12:29:02.402609 # ok 92 # SKIP Disabled ZA for VL 496
5989 12:29:02.402747 # ok 93 # SKIP Get and set data for VL 496
5990 12:29:02.402889 # ok 94 Set VL 512
5991 12:29:02.403031 # ok 95 # SKIP Disabled ZA for VL 512
5992 12:29:02.406601 # ok 96 # SKIP Get and set data for VL 512
5993 12:29:02.406727 # ok 97 Set VL 528
5994 12:29:02.407019 # ok 98 # SKIP Disabled ZA for VL 528
5995 12:29:02.407149 # ok 99 # SKIP Get and set data for VL 528
5996 12:29:02.407241 # ok 100 Set VL 544
5997 12:29:02.407328 # ok 101 # SKIP Disabled ZA for VL 544
5998 12:29:02.407411 # ok 102 # SKIP Get and set data for VL 544
5999 12:29:02.407495 # ok 103 Set VL 560
6000 12:29:02.407596 # ok 104 # SKIP Disabled ZA for VL 560
6001 12:29:02.407685 # ok 105 # SKIP Get and set data for VL 560
6002 12:29:02.407772 # ok 106 Set VL 576
6003 12:29:02.407874 # ok 107 # SKIP Disabled ZA for VL 576
6004 12:29:02.407962 # ok 108 # SKIP Get and set data for VL 576
6005 12:29:02.408046 # ok 109 Set VL 592
6006 12:29:02.408132 # ok 110 # SKIP Disabled ZA for VL 592
6007 12:29:02.408236 # ok 111 # SKIP Get and set data for VL 592
6008 12:29:02.408322 # ok 112 Set VL 608
6009 12:29:02.408401 # ok 113 # SKIP Disabled ZA for VL 608
6010 12:29:02.408493 # ok 114 # SKIP Get and set data for VL 608
6011 12:29:02.408871 # ok 115 Set VL 624
6012 12:29:02.409334 # ok 116 # SKIP Disabled ZA for VL 624
6013 12:29:02.409544 # ok 117 # SKIP Get and set data for VL 624
6014 12:29:02.409717 # ok 118 Set VL 640
6015 12:29:02.409888 # ok 119 # SKIP Disabled ZA for VL 640
6016 12:29:02.410036 # ok 120 # SKIP Get and set data for VL 640
6017 12:29:02.410179 # ok 121 Set VL 656
6018 12:29:02.410357 # ok 122 # SKIP Disabled ZA for VL 656
6019 12:29:02.410497 # ok 123 # SKIP Get and set data for VL 656
6020 12:29:02.410641 # ok 124 Set VL 672
6021 12:29:02.419317 # ok 125 # SKIP Disabled ZA for VL 672
6022 12:29:02.419685 # ok 126 # SKIP Get and set data for VL 672
6023 12:29:02.419782 # ok 127 Set VL 688
6024 12:29:02.419872 # ok 128 # SKIP Disabled ZA for VL 688
6025 12:29:02.419960 # ok 129 # SKIP Get and set data for VL 688
6026 12:29:02.420045 # ok 130 Set VL 704
6027 12:29:02.420151 # ok 131 # SKIP Disabled ZA for VL 704
6028 12:29:02.420240 # ok 132 # SKIP Get and set data for VL 704
6029 12:29:02.420330 # ok 133 Set VL 720
6030 12:29:02.420415 # ok 134 # SKIP Disabled ZA for VL 720
6031 12:29:02.420513 # ok 135 # SKIP Get and set data for VL 720
6032 12:29:02.420594 # ok 136 Set VL 736
6033 12:29:02.420672 # ok 137 # SKIP Disabled ZA for VL 736
6034 12:29:02.420943 # ok 138 # SKIP Get and set data for VL 736
6035 12:29:02.421054 # ok 139 Set VL 752
6036 12:29:02.421154 # ok 140 # SKIP Disabled ZA for VL 752
6037 12:29:02.421257 # ok 141 # SKIP Get and set data for VL 752
6038 12:29:02.421343 # ok 142 Set VL 768
6039 12:29:02.421443 # ok 143 # SKIP Disabled ZA for VL 768
6040 12:29:02.421742 # ok 144 # SKIP Get and set data for VL 768
6041 12:29:02.421847 # ok 145 Set VL 784
6042 12:29:02.421954 # ok 146 # SKIP Disabled ZA for VL 784
6043 12:29:02.422042 # ok 147 # SKIP Get and set data for VL 784
6044 12:29:02.422129 # ok 148 Set VL 800
6045 12:29:02.422214 # ok 149 # SKIP Disabled ZA for VL 800
6046 12:29:02.422315 # ok 150 # SKIP Get and set data for VL 800
6047 12:29:02.422404 # ok 151 Set VL 816
6048 12:29:02.422488 # ok 152 # SKIP Disabled ZA for VL 816
6049 12:29:02.422591 # ok 153 # SKIP Get and set data for VL 816
6050 12:29:02.422680 # ok 154 Set VL 832
6051 12:29:02.422766 # ok 155 # SKIP Disabled ZA for VL 832
6052 12:29:02.422868 # ok 156 # SKIP Get and set data for VL 832
6053 12:29:02.422955 # ok 157 Set VL 848
6054 12:29:02.423057 # ok 158 # SKIP Disabled ZA for VL 848
6055 12:29:02.423151 # ok 159 # SKIP Get and set data for VL 848
6056 12:29:02.423253 # ok 160 Set VL 864
6057 12:29:02.423358 # ok 161 # SKIP Disabled ZA for VL 864
6058 12:29:02.423445 # ok 162 # SKIP Get and set data for VL 864
6059 12:29:02.423543 # ok 163 Set VL 880
6060 12:29:02.423630 # ok 164 # SKIP Disabled ZA for VL 880
6061 12:29:02.423731 # ok 165 # SKIP Get and set data for VL 880
6062 12:29:02.423818 # ok 166 Set VL 896
6063 12:29:02.423916 # ok 167 # SKIP Disabled ZA for VL 896
6064 12:29:02.424017 # ok 168 # SKIP Get and set data for VL 896
6065 12:29:02.424117 # ok 169 Set VL 912
6066 12:29:02.424216 # ok 170 # SKIP Disabled ZA for VL 912
6067 12:29:02.424320 # ok 171 # SKIP Get and set data for VL 912
6068 12:29:02.433125 # ok 172 Set VL 928
6069 12:29:02.433263 # ok 173 # SKIP Disabled ZA for VL 928
6070 12:29:02.433371 # ok 174 # SKIP Get and set data for VL 928
6071 12:29:02.433460 # ok 175 Set VL 944
6072 12:29:02.433547 # ok 176 # SKIP Disabled ZA for VL 944
6073 12:29:02.433653 # ok 177 # SKIP Get and set data for VL 944
6074 12:29:02.433744 # ok 178 Set VL 960
6075 12:29:02.433827 # ok 179 # SKIP Disabled ZA for VL 960
6076 12:29:02.433930 # ok 180 # SKIP Get and set data for VL 960
6077 12:29:02.434017 # ok 181 Set VL 976
6078 12:29:02.434105 # ok 182 # SKIP Disabled ZA for VL 976
6079 12:29:02.434206 # ok 183 # SKIP Get and set data for VL 976
6080 12:29:02.434294 # ok 184 Set VL 992
6081 12:29:02.434395 # ok 185 # SKIP Disabled ZA for VL 992
6082 12:29:02.434495 # ok 186 # SKIP Get and set data for VL 992
6083 12:29:02.434582 # ok 187 Set VL 1008
6084 12:29:02.434679 # ok 188 # SKIP Disabled ZA for VL 1008
6085 12:29:02.434779 # ok 189 # SKIP Get and set data for VL 1008
6086 12:29:02.434879 # ok 190 Set VL 1024
6087 12:29:02.434976 # ok 191 # SKIP Disabled ZA for VL 1024
6088 12:29:02.435410 # ok 192 # SKIP Get and set data for VL 1024
6089 12:29:02.435517 # ok 193 Set VL 1040
6090 12:29:02.435602 # ok 194 # SKIP Disabled ZA for VL 1040
6091 12:29:02.435703 # ok 195 # SKIP Get and set data for VL 1040
6092 12:29:02.435795 # ok 196 Set VL 1056
6093 12:29:02.435897 # ok 197 # SKIP Disabled ZA for VL 1056
6094 12:29:02.435985 # ok 198 # SKIP Get and set data for VL 1056
6095 12:29:02.436072 # ok 199 Set VL 1072
6096 12:29:02.436178 # ok 200 # SKIP Disabled ZA for VL 1072
6097 12:29:02.436264 # ok 201 # SKIP Get and set data for VL 1072
6098 12:29:02.436358 # ok 202 Set VL 1088
6099 12:29:02.442329 # ok 203 # SKIP Disabled ZA for VL 1088
6100 12:29:02.442666 # ok 204 # SKIP Get and set data for VL 1088
6101 12:29:02.442771 # ok 205 Set VL 1104
6102 12:29:02.442860 # ok 206 # SKIP Disabled ZA for VL 1104
6103 12:29:02.442947 # ok 207 # SKIP Get and set data for VL 1104
6104 12:29:02.443053 # ok 208 Set VL 1120
6105 12:29:02.443142 # ok 209 # SKIP Disabled ZA for VL 1120
6106 12:29:02.443235 # ok 210 # SKIP Get and set data for VL 1120
6107 12:29:02.443320 # ok 211 Set VL 1136
6108 12:29:02.443423 # ok 212 # SKIP Disabled ZA for VL 1136
6109 12:29:02.443511 # ok 213 # SKIP Get and set data for VL 1136
6110 12:29:02.443597 # ok 214 Set VL 1152
6111 12:29:02.443682 # ok 215 # SKIP Disabled ZA for VL 1152
6112 12:29:02.443783 # ok 216 # SKIP Get and set data for VL 1152
6113 12:29:02.443870 # ok 217 Set VL 1168
6114 12:29:02.443955 # ok 218 # SKIP Disabled ZA for VL 1168
6115 12:29:02.444056 # ok 219 # SKIP Get and set data for VL 1168
6116 12:29:02.444142 # ok 220 Set VL 1184
6117 12:29:02.444240 # ok 221 # SKIP Disabled ZA for VL 1184
6118 12:29:02.444323 # ok 222 # SKIP Get and set data for VL 1184
6119 12:29:02.444874 # ok 223 Set VL 1200
6120 12:29:02.445074 # ok 224 # SKIP Disabled ZA for VL 1200
6121 12:29:02.445225 # ok 225 # SKIP Get and set data for VL 1200
6122 12:29:02.445571 # ok 226 Set VL 1216
6123 12:29:02.445767 # ok 227 # SKIP Disabled ZA for VL 1216
6124 12:29:02.445963 # ok 228 # SKIP Get and set data for VL 1216
6125 12:29:02.446139 # ok 229 Set VL 1232
6126 12:29:02.446295 # ok 230 # SKIP Disabled ZA for VL 1232
6127 12:29:02.446456 # ok 231 # SKIP Get and set data for VL 1232
6128 12:29:02.446617 # ok 232 Set VL 1248
6129 12:29:02.446775 # ok 233 # SKIP Disabled ZA for VL 1248
6130 12:29:02.446980 # ok 234 # SKIP Get and set data for VL 1248
6131 12:29:02.447154 # ok 235 Set VL 1264
6132 12:29:02.447323 # ok 236 # SKIP Disabled ZA for VL 1264
6133 12:29:02.447496 # ok 237 # SKIP Get and set data for VL 1264
6134 12:29:02.447710 # ok 238 Set VL 1280
6135 12:29:02.447920 # ok 239 # SKIP Disabled ZA for VL 1280
6136 12:29:02.448093 # ok 240 # SKIP Get and set data for VL 1280
6137 12:29:02.448254 # ok 241 Set VL 1296
6138 12:29:02.448374 # ok 242 # SKIP Disabled ZA for VL 1296
6139 12:29:02.448489 # ok 243 # SKIP Get and set data for VL 1296
6140 12:29:02.448602 # ok 244 Set VL 1312
6141 12:29:02.448713 # ok 245 # SKIP Disabled ZA for VL 1312
6142 12:29:02.448825 # ok 246 # SKIP Get and set data for VL 1312
6143 12:29:02.448937 # ok 247 Set VL 1328
6144 12:29:02.449048 # ok 248 # SKIP Disabled ZA for VL 1328
6145 12:29:02.449161 # ok 249 # SKIP Get and set data for VL 1328
6146 12:29:02.449276 # ok 250 Set VL 1344
6147 12:29:02.449420 # ok 251 # SKIP Disabled ZA for VL 1344
6148 12:29:02.449541 # ok 252 # SKIP Get and set data for VL 1344
6149 12:29:02.449697 # ok 253 Set VL 1360
6150 12:29:02.449909 # ok 254 # SKIP Disabled ZA for VL 1360
6151 12:29:02.450094 # ok 255 # SKIP Get and set data for VL 1360
6152 12:29:02.450299 # ok 256 Set VL 1376
6153 12:29:02.450458 # ok 257 # SKIP Disabled ZA for VL 1376
6154 12:29:02.450621 # ok 258 # SKIP Get and set data for VL 1376
6155 12:29:02.450780 # ok 259 Set VL 1392
6156 12:29:02.450936 # ok 260 # SKIP Disabled ZA for VL 1392
6157 12:29:02.451093 # ok 261 # SKIP Get and set data for VL 1392
6158 12:29:02.451251 # ok 262 Set VL 1408
6159 12:29:02.451408 # ok 263 # SKIP Disabled ZA for VL 1408
6160 12:29:02.451565 # ok 264 # SKIP Get and set data for VL 1408
6161 12:29:02.451724 # ok 265 Set VL 1424
6162 12:29:02.451883 # ok 266 # SKIP Disabled ZA for VL 1424
6163 12:29:02.456350 # ok 267 # SKIP Get and set data for VL 1424
6164 12:29:02.458210 # ok 268 Set VL 1440
6165 12:29:02.458647 # ok 269 # SKIP Disabled ZA for VL 1440
6166 12:29:02.458841 # ok 270 # SKIP Get and set data for VL 1440
6167 12:29:02.459006 # ok 271 Set VL 1456
6168 12:29:02.459159 # ok 272 # SKIP Disabled ZA for VL 1456
6169 12:29:02.459350 # ok 273 # SKIP Get and set data for VL 1456
6170 12:29:02.459501 # ok 274 Set VL 1472
6171 12:29:02.459665 # ok 275 # SKIP Disabled ZA for VL 1472
6172 12:29:02.459800 # ok 276 # SKIP Get and set data for VL 1472
6173 12:29:02.459945 # ok 277 Set VL 1488
6174 12:29:02.460063 # ok 278 # SKIP Disabled ZA for VL 1488
6175 12:29:02.460200 # ok 279 # SKIP Get and set data for VL 1488
6176 12:29:02.460339 # ok 280 Set VL 1504
6177 12:29:02.460455 # ok 281 # SKIP Disabled ZA for VL 1504
6178 12:29:02.460568 # ok 282 # SKIP Get and set data for VL 1504
6179 12:29:02.460681 # ok 283 Set VL 1520
6180 12:29:02.460793 # ok 284 # SKIP Disabled ZA for VL 1520
6181 12:29:02.460907 # ok 285 # SKIP Get and set data for VL 1520
6182 12:29:02.461021 # ok 286 Set VL 1536
6183 12:29:02.461163 # ok 287 # SKIP Disabled ZA for VL 1536
6184 12:29:02.461284 # ok 288 # SKIP Get and set data for VL 1536
6185 12:29:02.461400 # ok 289 Set VL 1552
6186 12:29:02.461514 # ok 290 # SKIP Disabled ZA for VL 1552
6187 12:29:02.461628 # ok 291 # SKIP Get and set data for VL 1552
6188 12:29:02.461840 # ok 292 Set VL 1568
6189 12:29:02.462035 # ok 293 # SKIP Disabled ZA for VL 1568
6190 12:29:02.462808 # ok 294 # SKIP Get and set data for VL 1568
6191 12:29:02.463003 # ok 295 Set VL 1584
6192 12:29:02.463435 # ok 296 # SKIP Disabled ZA for VL 1584
6193 12:29:02.463636 # ok 297 # SKIP Get and set data for VL 1584
6194 12:29:02.463809 # ok 298 Set VL 1600
6195 12:29:02.463975 # ok 299 # SKIP Disabled ZA for VL 1600
6196 12:29:02.464136 # ok 300 # SKIP Get and set data for VL 1600
6197 12:29:02.464302 # ok 301 Set VL 1616
6198 12:29:02.464434 # ok 302 # SKIP Disabled ZA for VL 1616
6199 12:29:02.464592 # ok 303 # SKIP Get and set data for VL 1616
6200 12:29:02.464725 # ok 304 Set VL 1632
6201 12:29:02.464845 # ok 305 # SKIP Disabled ZA for VL 1632
6202 12:29:02.464963 # ok 306 # SKIP Get and set data for VL 1632
6203 12:29:02.465079 # ok 307 Set VL 1648
6204 12:29:02.465197 # ok 308 # SKIP Disabled ZA for VL 1648
6205 12:29:02.465314 # ok 309 # SKIP Get and set data for VL 1648
6206 12:29:02.465430 # ok 310 Set VL 1664
6207 12:29:02.465544 # ok 311 # SKIP Disabled ZA for VL 1664
6208 12:29:02.465684 # ok 312 # SKIP Get and set data for VL 1664
6209 12:29:02.465859 # ok 313 Set VL 1680
6210 12:29:02.466005 # ok 314 # SKIP Disabled ZA for VL 1680
6211 12:29:02.506862 # ok 315 # SKIP Get and set data for VL 1680
6212 12:29:02.507176 # ok 316 Set VL 1696
6213 12:29:02.507353 # ok 317 # SKIP Disabled ZA for VL 1696
6214 12:29:02.507553 # ok 318 # SKIP Get and set data for VL 1696
6215 12:29:02.507992 # ok 319 Set VL 1712
6216 12:29:02.508196 # ok 320 # SKIP Disabled ZA for VL 1712
6217 12:29:02.508367 # ok 321 # SKIP Get and set data for VL 1712
6218 12:29:02.508490 # ok 322 Set VL 1728
6219 12:29:02.508607 # ok 323 # SKIP Disabled ZA for VL 1728
6220 12:29:02.508723 # ok 324 # SKIP Get and set data for VL 1728
6221 12:29:02.508838 # ok 325 Set VL 1744
6222 12:29:02.508953 # ok 326 # SKIP Disabled ZA for VL 1744
6223 12:29:02.509067 # ok 327 # SKIP Get and set data for VL 1744
6224 12:29:02.509183 # ok 328 Set VL 1760
6225 12:29:02.509298 # ok 329 # SKIP Disabled ZA for VL 1760
6226 12:29:02.509413 # ok 330 # SKIP Get and set data for VL 1760
6227 12:29:02.509530 # ok 331 Set VL 1776
6228 12:29:02.509695 # ok 332 # SKIP Disabled ZA for VL 1776
6229 12:29:02.509822 # ok 333 # SKIP Get and set data for VL 1776
6230 12:29:02.509938 # ok 334 Set VL 1792
6231 12:29:02.524299 # ok 335 # SKIP Disabled ZA for VL 1792
6232 12:29:02.524809 # ok 336 # SKIP Get and set data for VL 1792
6233 12:29:02.539432 # ok 337 Set VL 1808
6234 12:29:02.540024 # ok 338 # SKIP Disabled ZA for VL 1808
6235 12:29:02.540224 # ok 339 # SKIP Get and set data for VL 1808
6236 12:29:02.540401 # ok 340 Set VL 1824
6237 12:29:02.540546 # ok 341 # SKIP Disabled ZA for VL 1824
6238 12:29:02.540687 # ok 342 # SKIP Get and set data for VL 1824
6239 12:29:02.540829 # ok 343 Set VL 1840
6240 12:29:02.540973 # ok 344 # SKIP Disabled ZA for VL 1840
6241 12:29:02.541149 # ok 345 # SKIP Get and set data for VL 1840
6242 12:29:02.541287 # ok 346 Set VL 1856
6243 12:29:02.542164 # ok 347 # SKIP Disabled ZA for VL 1856
6244 12:29:02.542691 # ok 348 # SKIP Get and set data for VL 1856
6245 12:29:02.543039 # ok 349 Set VL 1872
6246 12:29:02.543214 # ok 350 # SKIP Disabled ZA for VL 1872
6247 12:29:02.543337 # ok 351 # SKIP Get and set data for VL 1872
6248 12:29:02.543454 # ok 352 Set VL 1888
6249 12:29:02.543567 # ok 353 # SKIP Disabled ZA for VL 1888
6250 12:29:02.543708 # ok 354 # SKIP Get and set data for VL 1888
6251 12:29:02.543830 # ok 355 Set VL 1904
6252 12:29:02.543990 # ok 356 # SKIP Disabled ZA for VL 1904
6253 12:29:02.544147 # ok 357 # SKIP Get and set data for VL 1904
6254 12:29:02.544295 # ok 358 Set VL 1920
6255 12:29:02.544441 # ok 359 # SKIP Disabled ZA for VL 1920
6256 12:29:02.544563 # ok 360 # SKIP Get and set data for VL 1920
6257 12:29:02.544680 # ok 361 Set VL 1936
6258 12:29:02.549403 # ok 362 # SKIP Disabled ZA for VL 1936
6259 12:29:02.549945 # ok 363 # SKIP Get and set data for VL 1936
6260 12:29:02.550145 # ok 364 Set VL 1952
6261 12:29:02.550286 # ok 365 # SKIP Disabled ZA for VL 1952
6262 12:29:02.550403 # ok 366 # SKIP Get and set data for VL 1952
6263 12:29:02.550518 # ok 367 Set VL 1968
6264 12:29:02.550630 # ok 368 # SKIP Disabled ZA for VL 1968
6265 12:29:02.550744 # ok 369 # SKIP Get and set data for VL 1968
6266 12:29:02.550884 # ok 370 Set VL 1984
6267 12:29:02.551262 # ok 371 # SKIP Disabled ZA for VL 1984
6268 12:29:02.551483 # ok 372 # SKIP Get and set data for VL 1984
6269 12:29:02.551689 # ok 373 Set VL 2000
6270 12:29:02.551895 # ok 374 # SKIP Disabled ZA for VL 2000
6271 12:29:02.552112 # ok 375 # SKIP Get and set data for VL 2000
6272 12:29:02.552335 # ok 376 Set VL 2016
6273 12:29:02.552552 # ok 377 # SKIP Disabled ZA for VL 2016
6274 12:29:02.552746 # ok 378 # SKIP Get and set data for VL 2016
6275 12:29:02.552919 # ok 379 Set VL 2032
6276 12:29:02.553085 # ok 380 # SKIP Disabled ZA for VL 2032
6277 12:29:02.553254 # ok 381 # SKIP Get and set data for VL 2032
6278 12:29:02.553422 # ok 382 Set VL 2048
6279 12:29:02.553588 # ok 383 # SKIP Disabled ZA for VL 2048
6280 12:29:02.553758 # ok 384 # SKIP Get and set data for VL 2048
6281 12:29:02.553925 # ok 385 Set VL 2064
6282 12:29:02.554092 # ok 386 # SKIP Disabled ZA for VL 2064
6283 12:29:02.554258 # ok 387 # SKIP Get and set data for VL 2064
6284 12:29:02.554426 # ok 388 Set VL 2080
6285 12:29:02.554586 # ok 389 # SKIP Disabled ZA for VL 2080
6286 12:29:02.554851 # ok 390 # SKIP Get and set data for VL 2080
6287 12:29:02.555049 # ok 391 Set VL 2096
6288 12:29:02.555254 # ok 392 # SKIP Disabled ZA for VL 2096
6289 12:29:02.555439 # ok 393 # SKIP Get and set data for VL 2096
6290 12:29:02.555590 # ok 394 Set VL 2112
6291 12:29:02.555738 # ok 395 # SKIP Disabled ZA for VL 2112
6292 12:29:02.555906 # ok 396 # SKIP Get and set data for VL 2112
6293 12:29:02.556065 # ok 397 Set VL 2128
6294 12:29:02.556226 # ok 398 # SKIP Disabled ZA for VL 2128
6295 12:29:02.556389 # ok 399 # SKIP Get and set data for VL 2128
6296 12:29:02.556547 # ok 400 Set VL 2144
6297 12:29:02.556710 # ok 401 # SKIP Disabled ZA for VL 2144
6298 12:29:02.556868 # ok 402 # SKIP Get and set data for VL 2144
6299 12:29:02.557048 # ok 403 Set VL 2160
6300 12:29:02.557251 # ok 404 # SKIP Disabled ZA for VL 2160
6301 12:29:02.557425 # ok 405 # SKIP Get and set data for VL 2160
6302 12:29:02.557628 # ok 406 Set VL 2176
6303 12:29:02.557835 # ok 407 # SKIP Disabled ZA for VL 2176
6304 12:29:02.557973 # ok 408 # SKIP Get and set data for VL 2176
6305 12:29:02.558091 # ok 409 Set VL 2192
6306 12:29:02.558206 # ok 410 # SKIP Disabled ZA for VL 2192
6307 12:29:02.558362 # ok 411 # SKIP Get and set data for VL 2192
6308 12:29:02.558496 # ok 412 Set VL 2208
6309 12:29:02.558614 # ok 413 # SKIP Disabled ZA for VL 2208
6310 12:29:02.558730 # ok 414 # SKIP Get and set data for VL 2208
6311 12:29:02.558846 # ok 415 Set VL 2224
6312 12:29:02.558962 # ok 416 # SKIP Disabled ZA for VL 2224
6313 12:29:02.559078 # ok 417 # SKIP Get and set data for VL 2224
6314 12:29:02.559194 # ok 418 Set VL 2240
6315 12:29:02.559309 # ok 419 # SKIP Disabled ZA for VL 2240
6316 12:29:02.559425 # ok 420 # SKIP Get and set data for VL 2240
6317 12:29:02.559542 # ok 421 Set VL 2256
6318 12:29:02.559657 # ok 422 # SKIP Disabled ZA for VL 2256
6319 12:29:02.559774 # ok 423 # SKIP Get and set data for VL 2256
6320 12:29:02.559888 # ok 424 Set VL 2272
6321 12:29:02.560243 # ok 425 # SKIP Disabled ZA for VL 2272
6322 12:29:02.560379 # ok 426 # SKIP Get and set data for VL 2272
6323 12:29:02.560514 # ok 427 Set VL 2288
6324 12:29:02.560634 # ok 428 # SKIP Disabled ZA for VL 2288
6325 12:29:02.560752 # ok 429 # SKIP Get and set data for VL 2288
6326 12:29:02.560871 # ok 430 Set VL 2304
6327 12:29:02.560987 # ok 431 # SKIP Disabled ZA for VL 2304
6328 12:29:02.561104 # ok 432 # SKIP Get and set data for VL 2304
6329 12:29:02.561221 # ok 433 Set VL 2320
6330 12:29:02.561339 # ok 434 # SKIP Disabled ZA for VL 2320
6331 12:29:02.561461 # ok 435 # SKIP Get and set data for VL 2320
6332 12:29:02.561578 # ok 436 Set VL 2336
6333 12:29:02.561709 # ok 437 # SKIP Disabled ZA for VL 2336
6334 12:29:02.561827 # ok 438 # SKIP Get and set data for VL 2336
6335 12:29:02.561944 # ok 439 Set VL 2352
6336 12:29:02.562060 # ok 440 # SKIP Disabled ZA for VL 2352
6337 12:29:02.562178 # ok 441 # SKIP Get and set data for VL 2352
6338 12:29:02.562295 # ok 442 Set VL 2368
6339 12:29:02.562415 # ok 443 # SKIP Disabled ZA for VL 2368
6340 12:29:02.562533 # ok 444 # SKIP Get and set data for VL 2368
6341 12:29:02.562649 # ok 445 Set VL 2384
6342 12:29:02.562767 # ok 446 # SKIP Disabled ZA for VL 2384
6343 12:29:02.562885 # ok 447 # SKIP Get and set data for VL 2384
6344 12:29:02.563002 # ok 448 Set VL 2400
6345 12:29:02.563117 # ok 449 # SKIP Disabled ZA for VL 2400
6346 12:29:02.563234 # ok 450 # SKIP Get and set data for VL 2400
6347 12:29:02.563351 # ok 451 Set VL 2416
6348 12:29:02.563470 # ok 452 # SKIP Disabled ZA for VL 2416
6349 12:29:02.563586 # ok 453 # SKIP Get and set data for VL 2416
6350 12:29:02.563702 # ok 454 Set VL 2432
6351 12:29:02.563818 # ok 455 # SKIP Disabled ZA for VL 2432
6352 12:29:02.563935 # ok 456 # SKIP Get and set data for VL 2432
6353 12:29:02.564051 # ok 457 Set VL 2448
6354 12:29:02.564185 # ok 458 # SKIP Disabled ZA for VL 2448
6355 12:29:02.564305 # ok 459 # SKIP Get and set data for VL 2448
6356 12:29:02.564425 # ok 460 Set VL 2464
6357 12:29:02.571022 # ok 461 # SKIP Disabled ZA for VL 2464
6358 12:29:02.571330 # ok 462 # SKIP Get and set data for VL 2464
6359 12:29:02.571501 # ok 463 Set VL 2480
6360 12:29:02.571974 # ok 464 # SKIP Disabled ZA for VL 2480
6361 12:29:02.572161 # ok 465 # SKIP Get and set data for VL 2480
6362 12:29:02.572335 # ok 466 Set VL 2496
6363 12:29:02.572477 # ok 467 # SKIP Disabled ZA for VL 2496
6364 12:29:02.572638 # ok 468 # SKIP Get and set data for VL 2496
6365 12:29:02.572770 # ok 469 Set VL 2512
6366 12:29:02.572889 # ok 470 # SKIP Disabled ZA for VL 2512
6367 12:29:02.573004 # ok 471 # SKIP Get and set data for VL 2512
6368 12:29:02.573121 # ok 472 Set VL 2528
6369 12:29:02.573236 # ok 473 # SKIP Disabled ZA for VL 2528
6370 12:29:02.573352 # ok 474 # SKIP Get and set data for VL 2528
6371 12:29:02.573466 # ok 475 Set VL 2544
6372 12:29:02.573609 # ok 476 # SKIP Disabled ZA for VL 2544
6373 12:29:02.573751 # ok 477 # SKIP Get and set data for VL 2544
6374 12:29:02.577975 # ok 478 Set VL 2560
6375 12:29:02.578422 # ok 479 # SKIP Disabled ZA for VL 2560
6376 12:29:02.578568 # ok 480 # SKIP Get and set data for VL 2560
6377 12:29:02.578699 # ok 481 Set VL 2576
6378 12:29:02.578828 # ok 482 # SKIP Disabled ZA for VL 2576
6379 12:29:02.578954 # ok 483 # SKIP Get and set data for VL 2576
6380 12:29:02.579080 # ok 484 Set VL 2592
6381 12:29:02.579203 # ok 485 # SKIP Disabled ZA for VL 2592
6382 12:29:02.579361 # ok 486 # SKIP Get and set data for VL 2592
6383 12:29:02.579492 # ok 487 Set VL 2608
6384 12:29:02.579610 # ok 488 # SKIP Disabled ZA for VL 2608
6385 12:29:02.579729 # ok 489 # SKIP Get and set data for VL 2608
6386 12:29:02.579846 # ok 490 Set VL 2624
6387 12:29:02.579964 # ok 491 # SKIP Disabled ZA for VL 2624
6388 12:29:02.580101 # ok 492 # SKIP Get and set data for VL 2624
6389 12:29:02.580253 # ok 493 Set VL 2640
6390 12:29:02.580373 # ok 494 # SKIP Disabled ZA for VL 2640
6391 12:29:02.580505 # ok 495 # SKIP Get and set data for VL 2640
6392 12:29:02.580625 # ok 496 Set VL 2656
6393 12:29:02.580741 # ok 497 # SKIP Disabled ZA for VL 2656
6394 12:29:02.580857 # ok 498 # SKIP Get and set data for VL 2656
6395 12:29:02.581222 # ok 499 Set VL 2672
6396 12:29:02.581382 # ok 500 # SKIP Disabled ZA for VL 2672
6397 12:29:02.581505 # ok 501 # SKIP Get and set data for VL 2672
6398 12:29:02.581624 # ok 502 Set VL 2688
6399 12:29:02.581768 # ok 503 # SKIP Disabled ZA for VL 2688
6400 12:29:02.581886 # ok 504 # SKIP Get and set data for VL 2688
6401 12:29:02.582003 # ok 505 Set VL 2704
6402 12:29:02.582122 # ok 506 # SKIP Disabled ZA for VL 2704
6403 12:29:02.582239 # ok 507 # SKIP Get and set data for VL 2704
6404 12:29:02.582354 # ok 508 Set VL 2720
6405 12:29:02.582469 # ok 509 # SKIP Disabled ZA for VL 2720
6406 12:29:02.582586 # ok 510 # SKIP Get and set data for VL 2720
6407 12:29:02.582702 # ok 511 Set VL 2736
6408 12:29:02.582816 # ok 512 # SKIP Disabled ZA for VL 2736
6409 12:29:02.582933 # ok 513 # SKIP Get and set data for VL 2736
6410 12:29:02.585667 # ok 514 Set VL 2752
6411 12:29:02.585897 # ok 515 # SKIP Disabled ZA for VL 2752
6412 12:29:02.586106 # ok 516 # SKIP Get and set data for VL 2752
6413 12:29:02.586307 # ok 517 Set VL 2768
6414 12:29:02.586461 # ok 518 # SKIP Disabled ZA for VL 2768
6415 12:29:02.586623 # ok 519 # SKIP Get and set data for VL 2768
6416 12:29:02.586783 # ok 520 Set VL 2784
6417 12:29:02.586987 # ok 521 # SKIP Disabled ZA for VL 2784
6418 12:29:02.587171 # ok 522 # SKIP Get and set data for VL 2784
6419 12:29:02.587390 # ok 523 Set VL 2800
6420 12:29:02.587595 # ok 524 # SKIP Disabled ZA for VL 2800
6421 12:29:02.587819 # ok 525 # SKIP Get and set data for VL 2800
6422 12:29:02.587978 # ok 526 Set VL 2816
6423 12:29:02.588145 # ok 527 # SKIP Disabled ZA for VL 2816
6424 12:29:02.588329 # ok 528 # SKIP Get and set data for VL 2816
6425 12:29:02.588467 # ok 529 Set VL 2832
6426 12:29:02.588629 # ok 530 # SKIP Disabled ZA for VL 2832
6427 12:29:02.588762 # ok 531 # SKIP Get and set data for VL 2832
6428 12:29:02.588880 # ok 532 Set VL 2848
6429 12:29:02.588997 # ok 533 # SKIP Disabled ZA for VL 2848
6430 12:29:02.589113 # ok 534 # SKIP Get and set data for VL 2848
6431 12:29:02.589229 # ok 535 Set VL 2864
6432 12:29:02.589345 # ok 536 # SKIP Disabled ZA for VL 2864
6433 12:29:02.589460 # ok 537 # SKIP Get and set data for VL 2864
6434 12:29:02.589577 # ok 538 Set VL 2880
6435 12:29:02.589706 # ok 539 # SKIP Disabled ZA for VL 2880
6436 12:29:02.589855 # ok 540 # SKIP Get and set data for VL 2880
6437 12:29:02.589978 # ok 541 Set VL 2896
6438 12:29:02.590094 # ok 542 # SKIP Disabled ZA for VL 2896
6439 12:29:02.590211 # ok 543 # SKIP Get and set data for VL 2896
6440 12:29:02.590327 # ok 544 Set VL 2912
6441 12:29:02.590445 # ok 545 # SKIP Disabled ZA for VL 2912
6442 12:29:02.593543 # ok 546 # SKIP Get and set data for VL 2912
6443 12:29:02.594051 # ok 547 Set VL 2928
6444 12:29:02.594241 # ok 548 # SKIP Disabled ZA for VL 2928
6445 12:29:02.594406 # ok 549 # SKIP Get and set data for VL 2928
6446 12:29:02.594566 # ok 550 Set VL 2944
6447 12:29:02.594727 # ok 551 # SKIP Disabled ZA for VL 2944
6448 12:29:02.594884 # ok 552 # SKIP Get and set data for VL 2944
6449 12:29:02.595069 # ok 553 Set VL 2960
6450 12:29:02.595257 # ok 554 # SKIP Disabled ZA for VL 2960
6451 12:29:02.595443 # ok 555 # SKIP Get and set data for VL 2960
6452 12:29:02.595639 # ok 556 Set VL 2976
6453 12:29:02.595842 # ok 557 # SKIP Disabled ZA for VL 2976
6454 12:29:02.596018 # ok 558 # SKIP Get and set data for VL 2976
6455 12:29:02.596212 # ok 559 Set VL 2992
6456 12:29:02.596377 # ok 560 # SKIP Disabled ZA for VL 2992
6457 12:29:02.596529 # ok 561 # SKIP Get and set data for VL 2992
6458 12:29:02.596680 # ok 562 Set VL 3008
6459 12:29:02.596831 # ok 563 # SKIP Disabled ZA for VL 3008
6460 12:29:02.597022 # ok 564 # SKIP Get and set data for VL 3008
6461 12:29:02.597186 # ok 565 Set VL 3024
6462 12:29:02.597340 # ok 566 # SKIP Disabled ZA for VL 3024
6463 12:29:02.597498 # ok 567 # SKIP Get and set data for VL 3024
6464 12:29:02.597666 # ok 568 Set VL 3040
6465 12:29:02.597828 # ok 569 # SKIP Disabled ZA for VL 3040
6466 12:29:02.597978 # ok 570 # SKIP Get and set data for VL 3040
6467 12:29:02.598129 # ok 571 Set VL 3056
6468 12:29:02.598280 # ok 572 # SKIP Disabled ZA for VL 3056
6469 12:29:02.598430 # ok 573 # SKIP Get and set data for VL 3056
6470 12:29:02.598549 # ok 574 Set VL 3072
6471 12:29:02.601506 # ok 575 # SKIP Disabled ZA for VL 3072
6472 12:29:02.601879 # ok 576 # SKIP Get and set data for VL 3072
6473 12:29:02.601983 # ok 577 Set VL 3088
6474 12:29:02.602062 # ok 578 # SKIP Disabled ZA for VL 3088
6475 12:29:02.602134 # ok 579 # SKIP Get and set data for VL 3088
6476 12:29:02.602260 # ok 580 Set VL 3104
6477 12:29:02.602361 # ok 581 # SKIP Disabled ZA for VL 3104
6478 12:29:02.602448 # ok 582 # SKIP Get and set data for VL 3104
6479 12:29:02.602543 # ok 583 Set VL 3120
6480 12:29:02.602639 # ok 584 # SKIP Disabled ZA for VL 3120
6481 12:29:02.602711 # ok 585 # SKIP Get and set data for VL 3120
6482 12:29:02.602786 # ok 586 Set VL 3136
6483 12:29:02.602878 # ok 587 # SKIP Disabled ZA for VL 3136
6484 12:29:02.602948 # ok 588 # SKIP Get and set data for VL 3136
6485 12:29:02.603023 # ok 589 Set VL 3152
6486 12:29:02.608046 # ok 590 # SKIP Disabled ZA for VL 3152
6487 12:29:02.608450 # ok 591 # SKIP Get and set data for VL 3152
6488 12:29:02.608542 # ok 592 Set VL 3168
6489 12:29:02.609127 # ok 593 # SKIP Disabled ZA for VL 3168
6490 12:29:02.609423 # ok 594 # SKIP Get and set data for VL 3168
6491 12:29:02.609535 # ok 595 Set VL 3184
6492 12:29:02.609621 # ok 596 # SKIP Disabled ZA for VL 3184
6493 12:29:02.609732 # ok 597 # SKIP Get and set data for VL 3184
6494 12:29:02.609810 # ok 598 Set VL 3200
6495 12:29:02.609891 # ok 599 # SKIP Disabled ZA for VL 3200
6496 12:29:02.610005 # ok 600 # SKIP Get and set data for VL 3200
6497 12:29:02.610096 # ok 601 Set VL 3216
6498 12:29:02.610189 # ok 602 # SKIP Disabled ZA for VL 3216
6499 12:29:02.610280 # ok 603 # SKIP Get and set data for VL 3216
6500 12:29:02.610398 # ok 604 Set VL 3232
6501 12:29:02.610482 # ok 605 # SKIP Disabled ZA for VL 3232
6502 12:29:02.610570 # ok 606 # SKIP Get and set data for VL 3232
6503 12:29:02.610657 # ok 607 Set VL 3248
6504 12:29:02.610743 # ok 608 # SKIP Disabled ZA for VL 3248
6505 12:29:02.610842 # ok 609 # SKIP Get and set data for VL 3248
6506 12:29:02.610937 # ok 610 Set VL 3264
6507 12:29:02.611014 # ok 611 # SKIP Disabled ZA for VL 3264
6508 12:29:02.611141 # ok 612 # SKIP Get and set data for VL 3264
6509 12:29:02.611241 # ok 613 Set VL 3280
6510 12:29:02.611334 # ok 614 # SKIP Disabled ZA for VL 3280
6511 12:29:02.611418 # ok 615 # SKIP Get and set data for VL 3280
6512 12:29:02.611493 # ok 616 Set VL 3296
6513 12:29:02.611589 # ok 617 # SKIP Disabled ZA for VL 3296
6514 12:29:02.611675 # ok 618 # SKIP Get and set data for VL 3296
6515 12:29:02.611768 # ok 619 Set VL 3312
6516 12:29:02.611845 # ok 620 # SKIP Disabled ZA for VL 3312
6517 12:29:02.611962 # ok 621 # SKIP Get and set data for VL 3312
6518 12:29:02.612062 # ok 622 Set VL 3328
6519 12:29:02.612162 # ok 623 # SKIP Disabled ZA for VL 3328
6520 12:29:02.612253 # ok 624 # SKIP Get and set data for VL 3328
6521 12:29:02.612336 # ok 625 Set VL 3344
6522 12:29:02.612415 # ok 626 # SKIP Disabled ZA for VL 3344
6523 12:29:02.612478 # ok 627 # SKIP Get and set data for VL 3344
6524 12:29:02.612538 # ok 628 Set VL 3360
6525 12:29:02.615546 # ok 629 # SKIP Disabled ZA for VL 3360
6526 12:29:02.616009 # ok 630 # SKIP Get and set data for VL 3360
6527 12:29:02.616185 # ok 631 Set VL 3376
6528 12:29:02.616285 # ok 632 # SKIP Disabled ZA for VL 3376
6529 12:29:02.616364 # ok 633 # SKIP Get and set data for VL 3376
6530 12:29:02.616439 # ok 634 Set VL 3392
6531 12:29:02.616517 # ok 635 # SKIP Disabled ZA for VL 3392
6532 12:29:02.616610 # ok 636 # SKIP Get and set data for VL 3392
6533 12:29:02.616688 # ok 637 Set VL 3408
6534 12:29:02.621594 # ok 638 # SKIP Disabled ZA for VL 3408
6535 12:29:02.621898 # ok 639 # SKIP Get and set data for VL 3408
6536 12:29:02.622095 # ok 640 Set VL 3424
6537 12:29:02.622512 # ok 641 # SKIP Disabled ZA for VL 3424
6538 12:29:02.622671 # ok 642 # SKIP Get and set data for VL 3424
6539 12:29:02.622795 # ok 643 Set VL 3440
6540 12:29:02.622913 # ok 644 # SKIP Disabled ZA for VL 3440
6541 12:29:02.623029 # ok 645 # SKIP Get and set data for VL 3440
6542 12:29:02.623146 # ok 646 Set VL 3456
6543 12:29:02.623261 # ok 647 # SKIP Disabled ZA for VL 3456
6544 12:29:02.623377 # ok 648 # SKIP Get and set data for VL 3456
6545 12:29:02.623492 # ok 649 Set VL 3472
6546 12:29:02.623607 # ok 650 # SKIP Disabled ZA for VL 3472
6547 12:29:02.623967 # ok 651 # SKIP Get and set data for VL 3472
6548 12:29:02.624160 # ok 652 Set VL 3488
6549 12:29:02.624309 # ok 653 # SKIP Disabled ZA for VL 3488
6550 12:29:02.624430 # ok 654 # SKIP Get and set data for VL 3488
6551 12:29:02.624547 # ok 655 Set VL 3504
6552 12:29:02.624665 # ok 656 # SKIP Disabled ZA for VL 3504
6553 12:29:02.624781 # ok 657 # SKIP Get and set data for VL 3504
6554 12:29:02.624897 # ok 658 Set VL 3520
6555 12:29:02.625011 # ok 659 # SKIP Disabled ZA for VL 3520
6556 12:29:02.625127 # ok 660 # SKIP Get and set data for VL 3520
6557 12:29:02.625241 # ok 661 Set VL 3536
6558 12:29:02.625357 # ok 662 # SKIP Disabled ZA for VL 3536
6559 12:29:02.625472 # ok 663 # SKIP Get and set data for VL 3536
6560 12:29:02.625589 # ok 664 Set VL 3552
6561 12:29:02.625720 # ok 665 # SKIP Disabled ZA for VL 3552
6562 12:29:02.625835 # ok 666 # SKIP Get and set data for VL 3552
6563 12:29:02.625948 # ok 667 Set VL 3568
6564 12:29:02.626060 # ok 668 # SKIP Disabled ZA for VL 3568
6565 12:29:02.626172 # ok 669 # SKIP Get and set data for VL 3568
6566 12:29:02.626283 # ok 670 Set VL 3584
6567 12:29:02.626395 # ok 671 # SKIP Disabled ZA for VL 3584
6568 12:29:02.626538 # ok 672 # SKIP Get and set data for VL 3584
6569 12:29:02.626661 # ok 673 Set VL 3600
6570 12:29:02.626776 # ok 674 # SKIP Disabled ZA for VL 3600
6571 12:29:02.629338 # ok 675 # SKIP Get and set data for VL 3600
6572 12:29:02.629801 # ok 676 Set VL 3616
6573 12:29:02.629984 # ok 677 # SKIP Disabled ZA for VL 3616
6574 12:29:02.630193 # ok 678 # SKIP Get and set data for VL 3616
6575 12:29:02.630377 # ok 679 Set VL 3632
6576 12:29:02.630615 # ok 680 # SKIP Disabled ZA for VL 3632
6577 12:29:02.630840 # ok 681 # SKIP Get and set data for VL 3632
6578 12:29:02.631059 # ok 682 Set VL 3648
6579 12:29:02.631277 # ok 683 # SKIP Disabled ZA for VL 3648
6580 12:29:02.631454 # ok 684 # SKIP Get and set data for VL 3648
6581 12:29:02.631619 # ok 685 Set VL 3664
6582 12:29:02.631768 # ok 686 # SKIP Disabled ZA for VL 3664
6583 12:29:02.631931 # ok 687 # SKIP Get and set data for VL 3664
6584 12:29:02.632092 # ok 688 Set VL 3680
6585 12:29:02.632217 # ok 689 # SKIP Disabled ZA for VL 3680
6586 12:29:02.632335 # ok 690 # SKIP Get and set data for VL 3680
6587 12:29:02.632452 # ok 691 Set VL 3696
6588 12:29:02.632566 # ok 692 # SKIP Disabled ZA for VL 3696
6589 12:29:02.632677 # ok 693 # SKIP Get and set data for VL 3696
6590 12:29:02.632789 # ok 694 Set VL 3712
6591 12:29:02.632899 # ok 695 # SKIP Disabled ZA for VL 3712
6592 12:29:02.633009 # ok 696 # SKIP Get and set data for VL 3712
6593 12:29:02.633120 # ok 697 Set VL 3728
6594 12:29:02.633230 # ok 698 # SKIP Disabled ZA for VL 3728
6595 12:29:02.633783 # ok 699 # SKIP Get and set data for VL 3728
6596 12:29:02.633889 # ok 700 Set VL 3744
6597 12:29:02.633975 # ok 701 # SKIP Disabled ZA for VL 3744
6598 12:29:02.634058 # ok 702 # SKIP Get and set data for VL 3744
6599 12:29:02.634138 # ok 703 Set VL 3760
6600 12:29:02.634222 # ok 704 # SKIP Disabled ZA for VL 3760
6601 12:29:02.634306 # ok 705 # SKIP Get and set data for VL 3760
6602 12:29:02.634386 # ok 706 Set VL 3776
6603 12:29:02.634465 # ok 707 # SKIP Disabled ZA for VL 3776
6604 12:29:02.634543 # ok 708 # SKIP Get and set data for VL 3776
6605 12:29:02.634627 # ok 709 Set VL 3792
6606 12:29:02.634703 # ok 710 # SKIP Disabled ZA for VL 3792
6607 12:29:02.639501 # ok 711 # SKIP Get and set data for VL 3792
6608 12:29:02.639714 # ok 712 Set VL 3808
6609 12:29:02.640071 # ok 713 # SKIP Disabled ZA for VL 3808
6610 12:29:02.640175 # ok 714 # SKIP Get and set data for VL 3808
6611 12:29:02.640255 # ok 715 Set VL 3824
6612 12:29:02.640329 # ok 716 # SKIP Disabled ZA for VL 3824
6613 12:29:02.640401 # ok 717 # SKIP Get and set data for VL 3824
6614 12:29:02.640488 # ok 718 Set VL 3840
6615 12:29:02.645217 # ok 719 # SKIP Disabled ZA for VL 3840
6616 12:29:02.645623 # ok 720 # SKIP Get and set data for VL 3840
6617 12:29:02.645736 # ok 721 Set VL 3856
6618 12:29:02.645825 # ok 722 # SKIP Disabled ZA for VL 3856
6619 12:29:02.645929 # ok 723 # SKIP Get and set data for VL 3856
6620 12:29:02.646018 # ok 724 Set VL 3872
6621 12:29:02.646102 # ok 725 # SKIP Disabled ZA for VL 3872
6622 12:29:02.646206 # ok 726 # SKIP Get and set data for VL 3872
6623 12:29:02.646295 # ok 727 Set VL 3888
6624 12:29:02.646381 # ok 728 # SKIP Disabled ZA for VL 3888
6625 12:29:02.646482 # ok 729 # SKIP Get and set data for VL 3888
6626 12:29:02.646574 # ok 730 Set VL 3904
6627 12:29:02.646672 # ok 731 # SKIP Disabled ZA for VL 3904
6628 12:29:02.646780 # ok 732 # SKIP Get and set data for VL 3904
6629 12:29:02.646869 # ok 733 Set VL 3920
6630 12:29:02.646971 # ok 734 # SKIP Disabled ZA for VL 3920
6631 12:29:02.647075 # ok 735 # SKIP Get and set data for VL 3920
6632 12:29:02.647163 # ok 736 Set VL 3936
6633 12:29:02.647419 # ok 737 # SKIP Disabled ZA for VL 3936
6634 12:29:02.647522 # ok 738 # SKIP Get and set data for VL 3936
6635 12:29:02.647619 # ok 739 Set VL 3952
6636 12:29:02.647719 # ok 740 # SKIP Disabled ZA for VL 3952
6637 12:29:02.647806 # ok 741 # SKIP Get and set data for VL 3952
6638 12:29:02.647891 # ok 742 Set VL 3968
6639 12:29:02.647992 # ok 743 # SKIP Disabled ZA for VL 3968
6640 12:29:02.648085 # ok 744 # SKIP Get and set data for VL 3968
6641 12:29:02.648183 # ok 745 Set VL 3984
6642 12:29:02.648266 # ok 746 # SKIP Disabled ZA for VL 3984
6643 12:29:02.648356 # ok 747 # SKIP Get and set data for VL 3984
6644 12:29:02.662324 # ok 748 Set VL 4000
6645 12:29:02.662576 # ok 749 # SKIP Disabled ZA for VL 4000
6646 12:29:02.662892 # ok 750 # SKIP Get and set data for VL 4000
6647 12:29:02.662989 # ok 751 Set VL 4016
6648 12:29:02.663066 # ok 752 # SKIP Disabled ZA for VL 4016
6649 12:29:02.663140 # ok 753 # SKIP Get and set data for VL 4016
6650 12:29:02.663214 # ok 754 Set VL 4032
6651 12:29:02.663289 # ok 755 # SKIP Disabled ZA for VL 4032
6652 12:29:02.663379 # ok 756 # SKIP Get and set data for VL 4032
6653 12:29:02.663453 # ok 757 Set VL 4048
6654 12:29:02.663527 # ok 758 # SKIP Disabled ZA for VL 4048
6655 12:29:02.663605 # ok 759 # SKIP Get and set data for VL 4048
6656 12:29:02.663682 # ok 760 Set VL 4064
6657 12:29:02.663758 # ok 761 # SKIP Disabled ZA for VL 4064
6658 12:29:02.663849 # ok 762 # SKIP Get and set data for VL 4064
6659 12:29:02.663931 # ok 763 Set VL 4080
6660 12:29:02.664008 # ok 764 # SKIP Disabled ZA for VL 4080
6661 12:29:02.664089 # ok 765 # SKIP Get and set data for VL 4080
6662 12:29:02.664164 # ok 766 Set VL 4096
6663 12:29:02.664237 # ok 767 # SKIP Disabled ZA for VL 4096
6664 12:29:02.664326 # ok 768 # SKIP Get and set data for VL 4096
6665 12:29:02.664401 # ok 769 Set VL 4112
6666 12:29:02.664476 # ok 770 # SKIP Disabled ZA for VL 4112
6667 12:29:02.677666 # ok 771 # SKIP Get and set data for VL 4112
6668 12:29:02.677886 # ok 772 Set VL 4128
6669 12:29:02.677964 # ok 773 # SKIP Disabled ZA for VL 4128
6670 12:29:02.678052 # ok 774 # SKIP Get and set data for VL 4128
6671 12:29:02.678128 # ok 775 Set VL 4144
6672 12:29:02.678201 # ok 776 # SKIP Disabled ZA for VL 4144
6673 12:29:02.678272 # ok 777 # SKIP Get and set data for VL 4144
6674 12:29:02.678344 # ok 778 Set VL 4160
6675 12:29:02.678431 # ok 779 # SKIP Disabled ZA for VL 4160
6676 12:29:02.678505 # ok 780 # SKIP Get and set data for VL 4160
6677 12:29:02.678578 # ok 781 Set VL 4176
6678 12:29:02.678651 # ok 782 # SKIP Disabled ZA for VL 4176
6679 12:29:02.678735 # ok 783 # SKIP Get and set data for VL 4176
6680 12:29:02.678808 # ok 784 Set VL 4192
6681 12:29:02.678879 # ok 785 # SKIP Disabled ZA for VL 4192
6682 12:29:02.678963 # ok 786 # SKIP Get and set data for VL 4192
6683 12:29:02.679036 # ok 787 Set VL 4208
6684 12:29:02.679106 # ok 788 # SKIP Disabled ZA for VL 4208
6685 12:29:02.679192 # ok 789 # SKIP Get and set data for VL 4208
6686 12:29:02.679269 # ok 790 Set VL 4224
6687 12:29:02.679355 # ok 791 # SKIP Disabled ZA for VL 4224
6688 12:29:02.679428 # ok 792 # SKIP Get and set data for VL 4224
6689 12:29:02.679513 # ok 793 Set VL 4240
6690 12:29:02.679584 # ok 794 # SKIP Disabled ZA for VL 4240
6691 12:29:02.679668 # ok 795 # SKIP Get and set data for VL 4240
6692 12:29:02.679740 # ok 796 Set VL 4256
6693 12:29:02.679828 # ok 797 # SKIP Disabled ZA for VL 4256
6694 12:29:02.679917 # ok 798 # SKIP Get and set data for VL 4256
6695 12:29:02.680000 # ok 799 Set VL 4272
6696 12:29:02.680104 # ok 800 # SKIP Disabled ZA for VL 4272
6697 12:29:02.694817 # ok 801 # SKIP Get and set data for VL 4272
6698 12:29:02.695037 # ok 802 Set VL 4288
6699 12:29:02.695338 # ok 803 # SKIP Disabled ZA for VL 4288
6700 12:29:02.695443 # ok 804 # SKIP Get and set data for VL 4288
6701 12:29:02.695526 # ok 805 Set VL 4304
6702 12:29:02.695599 # ok 806 # SKIP Disabled ZA for VL 4304
6703 12:29:02.695658 # ok 807 # SKIP Get and set data for VL 4304
6704 12:29:02.695720 # ok 808 Set VL 4320
6705 12:29:02.695933 # ok 809 # SKIP Disabled ZA for VL 4320
6706 12:29:02.696029 # ok 810 # SKIP Get and set data for VL 4320
6707 12:29:02.696100 # ok 811 Set VL 4336
6708 12:29:02.696168 # ok 812 # SKIP Disabled ZA for VL 4336
6709 12:29:02.696230 # ok 813 # SKIP Get and set data for VL 4336
6710 12:29:02.696290 # ok 814 Set VL 4352
6711 12:29:02.696364 # ok 815 # SKIP Disabled ZA for VL 4352
6712 12:29:02.701401 # ok 816 # SKIP Get and set data for VL 4352
6713 12:29:02.701696 # ok 817 Set VL 4368
6714 12:29:02.701802 # ok 818 # SKIP Disabled ZA for VL 4368
6715 12:29:02.701886 # ok 819 # SKIP Get and set data for VL 4368
6716 12:29:02.701964 # ok 820 Set VL 4384
6717 12:29:02.702028 # ok 821 # SKIP Disabled ZA for VL 4384
6718 12:29:02.703013 # ok 822 # SKIP Get and set data for VL 4384
6719 12:29:02.703115 # ok 823 Set VL 4400
6720 12:29:02.703212 # ok 824 # SKIP Disabled ZA for VL 4400
6721 12:29:02.703290 # ok 825 # SKIP Get and set data for VL 4400
6722 12:29:02.703376 # ok 826 Set VL 4416
6723 12:29:02.703450 # ok 827 # SKIP Disabled ZA for VL 4416
6724 12:29:02.703535 # ok 828 # SKIP Get and set data for VL 4416
6725 12:29:02.703797 # ok 829 Set VL 4432
6726 12:29:02.703877 # ok 830 # SKIP Disabled ZA for VL 4432
6727 12:29:02.703949 # ok 831 # SKIP Get and set data for VL 4432
6728 12:29:02.704022 # ok 832 Set VL 4448
6729 12:29:02.704117 # ok 833 # SKIP Disabled ZA for VL 4448
6730 12:29:02.704198 # ok 834 # SKIP Get and set data for VL 4448
6731 12:29:02.704274 # ok 835 Set VL 4464
6732 12:29:02.713579 # ok 836 # SKIP Disabled ZA for VL 4464
6733 12:29:02.713734 # ok 837 # SKIP Get and set data for VL 4464
6734 12:29:02.713842 # ok 838 Set VL 4480
6735 12:29:02.713924 # ok 839 # SKIP Disabled ZA for VL 4480
6736 12:29:02.713998 # ok 840 # SKIP Get and set data for VL 4480
6737 12:29:02.714102 # ok 841 Set VL 4496
6738 12:29:02.714217 # ok 842 # SKIP Disabled ZA for VL 4496
6739 12:29:02.714328 # ok 843 # SKIP Get and set data for VL 4496
6740 12:29:02.714433 # ok 844 Set VL 4512
6741 12:29:02.714555 # ok 845 # SKIP Disabled ZA for VL 4512
6742 12:29:02.714661 # ok 846 # SKIP Get and set data for VL 4512
6743 12:29:02.714756 # ok 847 Set VL 4528
6744 12:29:02.714847 # ok 848 # SKIP Disabled ZA for VL 4528
6745 12:29:02.714940 # ok 849 # SKIP Get and set data for VL 4528
6746 12:29:02.715020 # ok 850 Set VL 4544
6747 12:29:02.715110 # ok 851 # SKIP Disabled ZA for VL 4544
6748 12:29:02.715196 # ok 852 # SKIP Get and set data for VL 4544
6749 12:29:02.715293 # ok 853 Set VL 4560
6750 12:29:02.715370 # ok 854 # SKIP Disabled ZA for VL 4560
6751 12:29:02.715443 # ok 855 # SKIP Get and set data for VL 4560
6752 12:29:02.715519 # ok 856 Set VL 4576
6753 12:29:02.715611 # ok 857 # SKIP Disabled ZA for VL 4576
6754 12:29:02.715699 # ok 858 # SKIP Get and set data for VL 4576
6755 12:29:02.715782 # ok 859 Set VL 4592
6756 12:29:02.715856 # ok 860 # SKIP Disabled ZA for VL 4592
6757 12:29:02.715930 # ok 861 # SKIP Get and set data for VL 4592
6758 12:29:02.716004 # ok 862 Set VL 4608
6759 12:29:02.716081 # ok 863 # SKIP Disabled ZA for VL 4608
6760 12:29:02.716143 # ok 864 # SKIP Get and set data for VL 4608
6761 12:29:02.716216 # ok 865 Set VL 4624
6762 12:29:02.716289 # ok 866 # SKIP Disabled ZA for VL 4624
6763 12:29:02.716350 # ok 867 # SKIP Get and set data for VL 4624
6764 12:29:02.726496 # ok 868 Set VL 4640
6765 12:29:02.726748 # ok 869 # SKIP Disabled ZA for VL 4640
6766 12:29:02.726842 # ok 870 # SKIP Get and set data for VL 4640
6767 12:29:02.727147 # ok 871 Set VL 4656
6768 12:29:02.727252 # ok 872 # SKIP Disabled ZA for VL 4656
6769 12:29:02.727344 # ok 873 # SKIP Get and set data for VL 4656
6770 12:29:02.727429 # ok 874 Set VL 4672
6771 12:29:02.727518 # ok 875 # SKIP Disabled ZA for VL 4672
6772 12:29:02.727603 # ok 876 # SKIP Get and set data for VL 4672
6773 12:29:02.727687 # ok 877 Set VL 4688
6774 12:29:02.727770 # ok 878 # SKIP Disabled ZA for VL 4688
6775 12:29:02.727853 # ok 879 # SKIP Get and set data for VL 4688
6776 12:29:02.727957 # ok 880 Set VL 4704
6777 12:29:02.728044 # ok 881 # SKIP Disabled ZA for VL 4704
6778 12:29:02.728122 # ok 882 # SKIP Get and set data for VL 4704
6779 12:29:02.728197 # ok 883 Set VL 4720
6780 12:29:02.728274 # ok 884 # SKIP Disabled ZA for VL 4720
6781 12:29:02.728350 # ok 885 # SKIP Get and set data for VL 4720
6782 12:29:02.728428 # ok 886 Set VL 4736
6783 12:29:02.728504 # ok 887 # SKIP Disabled ZA for VL 4736
6784 12:29:02.728580 # ok 888 # SKIP Get and set data for VL 4736
6785 12:29:02.728656 # ok 889 Set VL 4752
6786 12:29:02.728736 # ok 890 # SKIP Disabled ZA for VL 4752
6787 12:29:02.728829 # ok 891 # SKIP Get and set data for VL 4752
6788 12:29:02.731358 # ok 892 Set VL 4768
6789 12:29:02.731664 # ok 893 # SKIP Disabled ZA for VL 4768
6790 12:29:02.731773 # ok 894 # SKIP Get and set data for VL 4768
6791 12:29:02.731863 # ok 895 Set VL 4784
6792 12:29:02.731950 # ok 896 # SKIP Disabled ZA for VL 4784
6793 12:29:02.732050 # ok 897 # SKIP Get and set data for VL 4784
6794 12:29:02.732134 # ok 898 Set VL 4800
6795 12:29:02.732213 # ok 899 # SKIP Disabled ZA for VL 4800
6796 12:29:02.732310 # ok 900 # SKIP Get and set data for VL 4800
6797 12:29:02.735601 # ok 901 Set VL 4816
6798 12:29:02.735708 # ok 902 # SKIP Disabled ZA for VL 4816
6799 12:29:02.735812 # ok 903 # SKIP Get and set data for VL 4816
6800 12:29:02.735903 # ok 904 Set VL 4832
6801 12:29:02.736001 # ok 905 # SKIP Disabled ZA for VL 4832
6802 12:29:02.736084 # ok 906 # SKIP Get and set data for VL 4832
6803 12:29:02.736165 # ok 907 Set VL 4848
6804 12:29:02.739305 # ok 908 # SKIP Disabled ZA for VL 4848
6805 12:29:02.739642 # ok 909 # SKIP Get and set data for VL 4848
6806 12:29:02.739744 # ok 910 Set VL 4864
6807 12:29:02.739842 # ok 911 # SKIP Disabled ZA for VL 4864
6808 12:29:02.739925 # ok 912 # SKIP Get and set data for VL 4864
6809 12:29:02.740019 # ok 913 Set VL 4880
6810 12:29:02.740099 # ok 914 # SKIP Disabled ZA for VL 4880
6811 12:29:02.740162 # ok 915 # SKIP Get and set data for VL 4880
6812 12:29:02.740221 # ok 916 Set VL 4896
6813 12:29:02.740293 # ok 917 # SKIP Disabled ZA for VL 4896
6814 12:29:02.740354 # ok 918 # SKIP Get and set data for VL 4896
6815 12:29:02.745900 # ok 919 Set VL 4912
6816 12:29:02.746101 # ok 920 # SKIP Disabled ZA for VL 4912
6817 12:29:02.746426 # ok 921 # SKIP Get and set data for VL 4912
6818 12:29:02.746535 # ok 922 Set VL 4928
6819 12:29:02.746622 # ok 923 # SKIP Disabled ZA for VL 4928
6820 12:29:02.746709 # ok 924 # SKIP Get and set data for VL 4928
6821 12:29:02.746795 # ok 925 Set VL 4944
6822 12:29:02.746878 # ok 926 # SKIP Disabled ZA for VL 4944
6823 12:29:02.746961 # ok 927 # SKIP Get and set data for VL 4944
6824 12:29:02.747044 # ok 928 Set VL 4960
6825 12:29:02.747146 # ok 929 # SKIP Disabled ZA for VL 4960
6826 12:29:02.747231 # ok 930 # SKIP Get and set data for VL 4960
6827 12:29:02.747316 # ok 931 Set VL 4976
6828 12:29:02.747398 # ok 932 # SKIP Disabled ZA for VL 4976
6829 12:29:02.747482 # ok 933 # SKIP Get and set data for VL 4976
6830 12:29:02.747566 # ok 934 Set VL 4992
6831 12:29:02.747649 # ok 935 # SKIP Disabled ZA for VL 4992
6832 12:29:02.747737 # ok 936 # SKIP Get and set data for VL 4992
6833 12:29:02.747820 # ok 937 Set VL 5008
6834 12:29:02.747922 # ok 938 # SKIP Disabled ZA for VL 5008
6835 12:29:02.748006 # ok 939 # SKIP Get and set data for VL 5008
6836 12:29:02.748082 # ok 940 Set VL 5024
6837 12:29:02.748153 # ok 941 # SKIP Disabled ZA for VL 5024
6838 12:29:02.748224 # ok 942 # SKIP Get and set data for VL 5024
6839 12:29:02.748295 # ok 943 Set VL 5040
6840 12:29:02.748364 # ok 944 # SKIP Disabled ZA for VL 5040
6841 12:29:02.748433 # ok 945 # SKIP Get and set data for VL 5040
6842 12:29:02.748503 # ok 946 Set VL 5056
6843 12:29:02.748572 # ok 947 # SKIP Disabled ZA for VL 5056
6844 12:29:02.748668 # ok 948 # SKIP Get and set data for VL 5056
6845 12:29:02.754816 # ok 949 Set VL 5072
6846 12:29:02.755298 # ok 950 # SKIP Disabled ZA for VL 5072
6847 12:29:02.755490 # ok 951 # SKIP Get and set data for VL 5072
6848 12:29:02.755664 # ok 952 Set VL 5088
6849 12:29:02.755824 # ok 953 # SKIP Disabled ZA for VL 5088
6850 12:29:02.755971 # ok 954 # SKIP Get and set data for VL 5088
6851 12:29:02.756173 # ok 955 Set VL 5104
6852 12:29:02.756299 # ok 956 # SKIP Disabled ZA for VL 5104
6853 12:29:02.756414 # ok 957 # SKIP Get and set data for VL 5104
6854 12:29:02.756527 # ok 958 Set VL 5120
6855 12:29:02.756640 # ok 959 # SKIP Disabled ZA for VL 5120
6856 12:29:02.756756 # ok 960 # SKIP Get and set data for VL 5120
6857 12:29:02.756870 # ok 961 Set VL 5136
6858 12:29:02.756982 # ok 962 # SKIP Disabled ZA for VL 5136
6859 12:29:02.757094 # ok 963 # SKIP Get and set data for VL 5136
6860 12:29:02.757207 # ok 964 Set VL 5152
6861 12:29:02.757907 # ok 965 # SKIP Disabled ZA for VL 5152
6862 12:29:02.758095 # ok 966 # SKIP Get and set data for VL 5152
6863 12:29:02.758254 # ok 967 Set VL 5168
6864 12:29:02.758403 # ok 968 # SKIP Disabled ZA for VL 5168
6865 12:29:02.758554 # ok 969 # SKIP Get and set data for VL 5168
6866 12:29:02.758709 # ok 970 Set VL 5184
6867 12:29:02.758865 # ok 971 # SKIP Disabled ZA for VL 5184
6868 12:29:02.759053 # ok 972 # SKIP Get and set data for VL 5184
6869 12:29:02.759221 # ok 973 Set VL 5200
6870 12:29:02.759387 # ok 974 # SKIP Disabled ZA for VL 5200
6871 12:29:02.759543 # ok 975 # SKIP Get and set data for VL 5200
6872 12:29:02.759702 # ok 976 Set VL 5216
6873 12:29:02.759865 # ok 977 # SKIP Disabled ZA for VL 5216
6874 12:29:02.760019 # ok 978 # SKIP Get and set data for VL 5216
6875 12:29:02.760141 # ok 979 Set VL 5232
6876 12:29:02.760253 # ok 980 # SKIP Disabled ZA for VL 5232
6877 12:29:02.760366 # ok 981 # SKIP Get and set data for VL 5232
6878 12:29:02.760478 # ok 982 Set VL 5248
6879 12:29:02.760587 # ok 983 # SKIP Disabled ZA for VL 5248
6880 12:29:02.760697 # ok 984 # SKIP Get and set data for VL 5248
6881 12:29:02.760809 # ok 985 Set VL 5264
6882 12:29:02.760917 # ok 986 # SKIP Disabled ZA for VL 5264
6883 12:29:02.761027 # ok 987 # SKIP Get and set data for VL 5264
6884 12:29:02.761136 # ok 988 Set VL 5280
6885 12:29:02.761276 # ok 989 # SKIP Disabled ZA for VL 5280
6886 12:29:02.761394 # ok 990 # SKIP Get and set data for VL 5280
6887 12:29:02.761506 # ok 991 Set VL 5296
6888 12:29:02.761616 # ok 992 # SKIP Disabled ZA for VL 5296
6889 12:29:02.761843 # ok 993 # SKIP Get and set data for VL 5296
6890 12:29:02.762037 # ok 994 Set VL 5312
6891 12:29:02.762218 # ok 995 # SKIP Disabled ZA for VL 5312
6892 12:29:02.762398 # ok 996 # SKIP Get and set data for VL 5312
6893 12:29:02.762578 # ok 997 Set VL 5328
6894 12:29:02.762758 # ok 998 # SKIP Disabled ZA for VL 5328
6895 12:29:02.762900 # ok 999 # SKIP Get and set data for VL 5328
6896 12:29:02.763039 # ok 1000 Set VL 5344
6897 12:29:02.763180 # ok 1001 # SKIP Disabled ZA for VL 5344
6898 12:29:02.769738 # ok 1002 # SKIP Get and set data for VL 5344
6899 12:29:02.770055 # ok 1003 Set VL 5360
6900 12:29:02.770490 # ok 1004 # SKIP Disabled ZA for VL 5360
6901 12:29:02.770739 # ok 1005 # SKIP Get and set data for VL 5360
6902 12:29:02.770997 # ok 1006 Set VL 5376
6903 12:29:02.771219 # ok 1007 # SKIP Disabled ZA for VL 5376
6904 12:29:02.771400 # ok 1008 # SKIP Get and set data for VL 5376
6905 12:29:02.771575 # ok 1009 Set VL 5392
6906 12:29:02.771765 # ok 1010 # SKIP Disabled ZA for VL 5392
6907 12:29:02.771934 # ok 1011 # SKIP Get and set data for VL 5392
6908 12:29:02.772095 # ok 1012 Set VL 5408
6909 12:29:02.772251 # ok 1013 # SKIP Disabled ZA for VL 5408
6910 12:29:02.772373 # ok 1014 # SKIP Get and set data for VL 5408
6911 12:29:02.772489 # ok 1015 Set VL 5424
6912 12:29:02.772603 # ok 1016 # SKIP Disabled ZA for VL 5424
6913 12:29:02.772716 # ok 1017 # SKIP Get and set data for VL 5424
6914 12:29:02.772828 # ok 1018 Set VL 5440
6915 12:29:02.772941 # ok 1019 # SKIP Disabled ZA for VL 5440
6916 12:29:02.773055 # ok 1020 # SKIP Get and set data for VL 5440
6917 12:29:02.773166 # ok 1021 Set VL 5456
6918 12:29:02.773278 # ok 1022 # SKIP Disabled ZA for VL 5456
6919 12:29:02.773389 # ok 1023 # SKIP Get and set data for VL 5456
6920 12:29:02.773502 # ok 1024 Set VL 5472
6921 12:29:02.773615 # ok 1025 # SKIP Disabled ZA for VL 5472
6922 12:29:02.773814 # ok 1026 # SKIP Get and set data for VL 5472
6923 12:29:02.774007 # ok 1027 Set VL 5488
6924 12:29:02.774188 # ok 1028 # SKIP Disabled ZA for VL 5488
6925 12:29:02.777777 # ok 1029 # SKIP Get and set data for VL 5488
6926 12:29:02.778215 # ok 1030 Set VL 5504
6927 12:29:02.778321 # ok 1031 # SKIP Disabled ZA for VL 5504
6928 12:29:02.778413 # ok 1032 # SKIP Get and set data for VL 5504
6929 12:29:02.778498 # ok 1033 Set VL 5520
6930 12:29:02.778602 # ok 1034 # SKIP Disabled ZA for VL 5520
6931 12:29:02.778689 # ok 1035 # SKIP Get and set data for VL 5520
6932 12:29:02.778778 # ok 1036 Set VL 5536
6933 12:29:02.778862 # ok 1037 # SKIP Disabled ZA for VL 5536
6934 12:29:02.778963 # ok 1038 # SKIP Get and set data for VL 5536
6935 12:29:02.779051 # ok 1039 Set VL 5552
6936 12:29:02.779135 # ok 1040 # SKIP Disabled ZA for VL 5552
6937 12:29:02.779218 # ok 1041 # SKIP Get and set data for VL 5552
6938 12:29:02.779317 # ok 1042 Set VL 5568
6939 12:29:02.779401 # ok 1043 # SKIP Disabled ZA for VL 5568
6940 12:29:02.779485 # ok 1044 # SKIP Get and set data for VL 5568
6941 12:29:02.779587 # ok 1045 Set VL 5584
6942 12:29:02.779672 # ok 1046 # SKIP Disabled ZA for VL 5584
6943 12:29:02.779777 # ok 1047 # SKIP Get and set data for VL 5584
6944 12:29:02.779864 # ok 1048 Set VL 5600
6945 12:29:02.779970 # ok 1049 # SKIP Disabled ZA for VL 5600
6946 12:29:02.780056 # ok 1050 # SKIP Get and set data for VL 5600
6947 12:29:02.780148 # ok 1051 Set VL 5616
6948 12:29:02.780983 # ok 1052 # SKIP Disabled ZA for VL 5616
6949 12:29:02.782623 # ok 1053 # SKIP Get and set data for VL 5616
6950 12:29:02.782757 # ok 1054 Set VL 5632
6951 12:29:02.782848 # ok 1055 # SKIP Disabled ZA for VL 5632
6952 12:29:02.782952 # ok 1056 # SKIP Get and set data for VL 5632
6953 12:29:02.783040 # ok 1057 Set VL 5648
6954 12:29:02.783123 # ok 1058 # SKIP Disabled ZA for VL 5648
6955 12:29:02.783209 # ok 1059 # SKIP Get and set data for VL 5648
6956 12:29:02.783311 # ok 1060 Set VL 5664
6957 12:29:02.783397 # ok 1061 # SKIP Disabled ZA for VL 5664
6958 12:29:02.783495 # ok 1062 # SKIP Get and set data for VL 5664
6959 12:29:02.783582 # ok 1063 Set VL 5680
6960 12:29:02.783681 # ok 1064 # SKIP Disabled ZA for VL 5680
6961 12:29:02.783767 # ok 1065 # SKIP Get and set data for VL 5680
6962 12:29:02.783875 # ok 1066 Set VL 5696
6963 12:29:02.783964 # ok 1067 # SKIP Disabled ZA for VL 5696
6964 12:29:02.784063 # ok 1068 # SKIP Get and set data for VL 5696
6965 12:29:02.784142 # ok 1069 Set VL 5712
6966 12:29:02.789692 # ok 1070 # SKIP Disabled ZA for VL 5712
6967 12:29:02.790250 # ok 1071 # SKIP Get and set data for VL 5712
6968 12:29:02.790417 # ok 1072 Set VL 5728
6969 12:29:02.790549 # ok 1073 # SKIP Disabled ZA for VL 5728
6970 12:29:02.790685 # ok 1074 # SKIP Get and set data for VL 5728
6971 12:29:02.790862 # ok 1075 Set VL 5744
6972 12:29:02.791007 # ok 1076 # SKIP Disabled ZA for VL 5744
6973 12:29:02.791174 # ok 1077 # SKIP Get and set data for VL 5744
6974 12:29:02.791319 # ok 1078 Set VL 5760
6975 12:29:02.791484 # ok 1079 # SKIP Disabled ZA for VL 5760
6976 12:29:02.791627 # ok 1080 # SKIP Get and set data for VL 5760
6977 12:29:02.791770 # ok 1081 Set VL 5776
6978 12:29:02.791888 # ok 1082 # SKIP Disabled ZA for VL 5776
6979 12:29:02.792020 # ok 1083 # SKIP Get and set data for VL 5776
6980 12:29:02.792149 # ok 1084 Set VL 5792
6981 12:29:02.792263 # ok 1085 # SKIP Disabled ZA for VL 5792
6982 12:29:02.792378 # ok 1086 # SKIP Get and set data for VL 5792
6983 12:29:02.792491 # ok 1087 Set VL 5808
6984 12:29:02.792605 # ok 1088 # SKIP Disabled ZA for VL 5808
6985 12:29:02.792720 # ok 1089 # SKIP Get and set data for VL 5808
6986 12:29:02.792837 # ok 1090 Set VL 5824
6987 12:29:02.792950 # ok 1091 # SKIP Disabled ZA for VL 5824
6988 12:29:02.793092 # ok 1092 # SKIP Get and set data for VL 5824
6989 12:29:02.793210 # ok 1093 Set VL 5840
6990 12:29:02.793324 # ok 1094 # SKIP Disabled ZA for VL 5840
6991 12:29:02.793438 # ok 1095 # SKIP Get and set data for VL 5840
6992 12:29:02.793551 # ok 1096 Set VL 5856
6993 12:29:02.801374 # ok 1097 # SKIP Disabled ZA for VL 5856
6994 12:29:02.801683 # ok 1098 # SKIP Get and set data for VL 5856
6995 12:29:02.802135 # ok 1099 Set VL 5872
6996 12:29:02.802312 # ok 1100 # SKIP Disabled ZA for VL 5872
6997 12:29:02.802514 # ok 1101 # SKIP Get and set data for VL 5872
6998 12:29:02.802689 # ok 1102 Set VL 5888
6999 12:29:02.802839 # ok 1103 # SKIP Disabled ZA for VL 5888
7000 12:29:02.802982 # ok 1104 # SKIP Get and set data for VL 5888
7001 12:29:02.803124 # ok 1105 Set VL 5904
7002 12:29:02.803264 # ok 1106 # SKIP Disabled ZA for VL 5904
7003 12:29:02.803404 # ok 1107 # SKIP Get and set data for VL 5904
7004 12:29:02.803546 # ok 1108 Set VL 5920
7005 12:29:02.803730 # ok 1109 # SKIP Disabled ZA for VL 5920
7006 12:29:02.803866 # ok 1110 # SKIP Get and set data for VL 5920
7007 12:29:02.804009 # ok 1111 Set VL 5936
7008 12:29:02.804149 # ok 1112 # SKIP Disabled ZA for VL 5936
7009 12:29:02.804289 # ok 1113 # SKIP Get and set data for VL 5936
7010 12:29:02.804428 # ok 1114 Set VL 5952
7011 12:29:02.804567 # ok 1115 # SKIP Disabled ZA for VL 5952
7012 12:29:02.804707 # ok 1116 # SKIP Get and set data for VL 5952
7013 12:29:02.804848 # ok 1117 Set VL 5968
7014 12:29:02.804987 # ok 1118 # SKIP Disabled ZA for VL 5968
7015 12:29:02.805127 # ok 1119 # SKIP Get and set data for VL 5968
7016 12:29:02.805268 # ok 1120 Set VL 5984
7017 12:29:02.805408 # ok 1121 # SKIP Disabled ZA for VL 5984
7018 12:29:02.805546 # ok 1122 # SKIP Get and set data for VL 5984
7019 12:29:02.805703 # ok 1123 Set VL 6000
7020 12:29:02.805849 # ok 1124 # SKIP Disabled ZA for VL 6000
7021 12:29:02.805992 # ok 1125 # SKIP Get and set data for VL 6000
7022 12:29:02.806132 # ok 1126 Set VL 6016
7023 12:29:02.806271 # ok 1127 # SKIP Disabled ZA for VL 6016
7024 12:29:02.806463 # ok 1128 # SKIP Get and set data for VL 6016
7025 12:29:02.806595 # ok 1129 Set VL 6032
7026 12:29:02.806737 # ok 1130 # SKIP Disabled ZA for VL 6032
7027 12:29:02.806879 # ok 1131 # SKIP Get and set data for VL 6032
7028 12:29:02.809424 # ok 1132 Set VL 6048
7029 12:29:02.809575 # ok 1133 # SKIP Disabled ZA for VL 6048
7030 12:29:02.809882 # ok 1134 # SKIP Get and set data for VL 6048
7031 12:29:02.809986 # ok 1135 Set VL 6064
7032 12:29:02.810072 # ok 1136 # SKIP Disabled ZA for VL 6064
7033 12:29:02.810158 # ok 1137 # SKIP Get and set data for VL 6064
7034 12:29:02.810243 # ok 1138 Set VL 6080
7035 12:29:02.810345 # ok 1139 # SKIP Disabled ZA for VL 6080
7036 12:29:02.810434 # ok 1140 # SKIP Get and set data for VL 6080
7037 12:29:02.810521 # ok 1141 Set VL 6096
7038 12:29:02.810620 # ok 1142 # SKIP Disabled ZA for VL 6096
7039 12:29:02.810707 # ok 1143 # SKIP Get and set data for VL 6096
7040 12:29:02.810793 # ok 1144 Set VL 6112
7041 12:29:02.810892 # ok 1145 # SKIP Disabled ZA for VL 6112
7042 12:29:02.810979 # ok 1146 # SKIP Get and set data for VL 6112
7043 12:29:02.811079 # ok 1147 Set VL 6128
7044 12:29:02.811165 # ok 1148 # SKIP Disabled ZA for VL 6128
7045 12:29:02.811266 # ok 1149 # SKIP Get and set data for VL 6128
7046 12:29:02.811357 # ok 1150 Set VL 6144
7047 12:29:02.811460 # ok 1151 # SKIP Disabled ZA for VL 6144
7048 12:29:02.811563 # ok 1152 # SKIP Get and set data for VL 6144
7049 12:29:02.811652 # ok 1153 Set VL 6160
7050 12:29:02.811753 # ok 1154 # SKIP Disabled ZA for VL 6160
7051 12:29:02.811869 # ok 1155 # SKIP Get and set data for VL 6160
7052 12:29:02.811973 # ok 1156 Set VL 6176
7053 12:29:02.820829 # ok 1157 # SKIP Disabled ZA for VL 6176
7054 12:29:02.821307 # ok 1158 # SKIP Get and set data for VL 6176
7055 12:29:02.821408 # ok 1159 Set VL 6192
7056 12:29:02.821490 # ok 1160 # SKIP Disabled ZA for VL 6192
7057 12:29:02.821565 # ok 1161 # SKIP Get and set data for VL 6192
7058 12:29:02.821641 # ok 1162 Set VL 6208
7059 12:29:02.821724 # ok 1163 # SKIP Disabled ZA for VL 6208
7060 12:29:02.821812 # ok 1164 # SKIP Get and set data for VL 6208
7061 12:29:02.821886 # ok 1165 Set VL 6224
7062 12:29:02.821964 # ok 1166 # SKIP Disabled ZA for VL 6224
7063 12:29:02.822035 # ok 1167 # SKIP Get and set data for VL 6224
7064 12:29:02.822107 # ok 1168 Set VL 6240
7065 12:29:02.822191 # ok 1169 # SKIP Disabled ZA for VL 6240
7066 12:29:02.822566 # ok 1170 # SKIP Get and set data for VL 6240
7067 12:29:02.822896 # ok 1171 Set VL 6256
7068 12:29:02.823296 # ok 1172 # SKIP Disabled ZA for VL 6256
7069 12:29:02.823519 # ok 1173 # SKIP Get and set data for VL 6256
7070 12:29:02.823720 # ok 1174 Set VL 6272
7071 12:29:02.823895 # ok 1175 # SKIP Disabled ZA for VL 6272
7072 12:29:02.824045 # ok 1176 # SKIP Get and set data for VL 6272
7073 12:29:02.824232 # ok 1177 Set VL 6288
7074 12:29:02.824367 # ok 1178 # SKIP Disabled ZA for VL 6288
7075 12:29:02.824510 # ok 1179 # SKIP Get and set data for VL 6288
7076 12:29:02.824652 # ok 1180 Set VL 6304
7077 12:29:02.824792 # ok 1181 # SKIP Disabled ZA for VL 6304
7078 12:29:02.824933 # ok 1182 # SKIP Get and set data for VL 6304
7079 12:29:02.825074 # ok 1183 Set VL 6320
7080 12:29:02.825213 # ok 1184 # SKIP Disabled ZA for VL 6320
7081 12:29:02.825353 # ok 1185 # SKIP Get and set data for VL 6320
7082 12:29:02.825493 # ok 1186 Set VL 6336
7083 12:29:02.825631 # ok 1187 # SKIP Disabled ZA for VL 6336
7084 12:29:02.825791 # ok 1188 # SKIP Get and set data for VL 6336
7085 12:29:02.825934 # ok 1189 Set VL 6352
7086 12:29:02.826072 # ok 1190 # SKIP Disabled ZA for VL 6352
7087 12:29:02.826212 # ok 1191 # SKIP Get and set data for VL 6352
7088 12:29:02.826352 # ok 1192 Set VL 6368
7089 12:29:02.828890 # ok 1193 # SKIP Disabled ZA for VL 6368
7090 12:29:02.829224 # ok 1194 # SKIP Get and set data for VL 6368
7091 12:29:02.829704 # ok 1195 Set VL 6384
7092 12:29:02.829810 # ok 1196 # SKIP Disabled ZA for VL 6384
7093 12:29:02.829905 # ok 1197 # SKIP Get and set data for VL 6384
7094 12:29:02.829990 # ok 1198 Set VL 6400
7095 12:29:02.830075 # ok 1199 # SKIP Disabled ZA for VL 6400
7096 12:29:02.830160 # ok 1200 # SKIP Get and set data for VL 6400
7097 12:29:02.830244 # ok 1201 Set VL 6416
7098 12:29:02.830325 # ok 1202 # SKIP Disabled ZA for VL 6416
7099 12:29:02.830408 # ok 1203 # SKIP Get and set data for VL 6416
7100 12:29:02.830508 # ok 1204 Set VL 6432
7101 12:29:02.830594 # ok 1205 # SKIP Disabled ZA for VL 6432
7102 12:29:02.830677 # ok 1206 # SKIP Get and set data for VL 6432
7103 12:29:02.830759 # ok 1207 Set VL 6448
7104 12:29:02.830840 # ok 1208 # SKIP Disabled ZA for VL 6448
7105 12:29:02.830924 # ok 1209 # SKIP Get and set data for VL 6448
7106 12:29:02.831007 # ok 1210 Set VL 6464
7107 12:29:02.831090 # ok 1211 # SKIP Disabled ZA for VL 6464
7108 12:29:02.831191 # ok 1212 # SKIP Get and set data for VL 6464
7109 12:29:02.831278 # ok 1213 Set VL 6480
7110 12:29:02.831362 # ok 1214 # SKIP Disabled ZA for VL 6480
7111 12:29:02.831444 # ok 1215 # SKIP Get and set data for VL 6480
7112 12:29:02.831524 # ok 1216 Set VL 6496
7113 12:29:02.831607 # ok 1217 # SKIP Disabled ZA for VL 6496
7114 12:29:02.831707 # ok 1218 # SKIP Get and set data for VL 6496
7115 12:29:02.831793 # ok 1219 Set VL 6512
7116 12:29:02.831873 # ok 1220 # SKIP Disabled ZA for VL 6512
7117 12:29:02.831954 # ok 1221 # SKIP Get and set data for VL 6512
7118 12:29:02.832031 # ok 1222 Set VL 6528
7119 12:29:02.832118 # ok 1223 # SKIP Disabled ZA for VL 6528
7120 12:29:02.832192 # ok 1224 # SKIP Get and set data for VL 6528
7121 12:29:02.845471 # ok 1225 Set VL 6544
7122 12:29:02.845720 # ok 1226 # SKIP Disabled ZA for VL 6544
7123 12:29:02.846020 # ok 1227 # SKIP Get and set data for VL 6544
7124 12:29:02.846118 # ok 1228 Set VL 6560
7125 12:29:02.846189 # ok 1229 # SKIP Disabled ZA for VL 6560
7126 12:29:02.846256 # ok 1230 # SKIP Get and set data for VL 6560
7127 12:29:02.846334 # ok 1231 Set VL 6576
7128 12:29:02.846423 # ok 1232 # SKIP Disabled ZA for VL 6576
7129 12:29:02.846699 # ok 1233 # SKIP Get and set data for VL 6576
7130 12:29:02.846794 # ok 1234 Set VL 6592
7131 12:29:02.846877 # ok 1235 # SKIP Disabled ZA for VL 6592
7132 12:29:02.846964 # ok 1236 # SKIP Get and set data for VL 6592
7133 12:29:02.847041 # ok 1237 Set VL 6608
7134 12:29:02.847108 # ok 1238 # SKIP Disabled ZA for VL 6608
7135 12:29:02.847169 # ok 1239 # SKIP Get and set data for VL 6608
7136 12:29:02.847231 # ok 1240 Set VL 6624
7137 12:29:02.847295 # ok 1241 # SKIP Disabled ZA for VL 6624
7138 12:29:02.847374 # ok 1242 # SKIP Get and set data for VL 6624
7139 12:29:02.847441 # ok 1243 Set VL 6640
7140 12:29:02.847506 # ok 1244 # SKIP Disabled ZA for VL 6640
7141 12:29:02.847569 # ok 1245 # SKIP Get and set data for VL 6640
7142 12:29:02.847633 # ok 1246 Set VL 6656
7143 12:29:02.847696 # ok 1247 # SKIP Disabled ZA for VL 6656
7144 12:29:02.847757 # ok 1248 # SKIP Get and set data for VL 6656
7145 12:29:02.847833 # ok 1249 Set VL 6672
7146 12:29:02.847941 # ok 1250 # SKIP Disabled ZA for VL 6672
7147 12:29:02.848037 # ok 1251 # SKIP Get and set data for VL 6672
7148 12:29:02.848102 # ok 1252 Set VL 6688
7149 12:29:02.848163 # ok 1253 # SKIP Disabled ZA for VL 6688
7150 12:29:02.848224 # ok 1254 # SKIP Get and set data for VL 6688
7151 12:29:02.848284 # ok 1255 Set VL 6704
7152 12:29:02.848344 # ok 1256 # SKIP Disabled ZA for VL 6704
7153 12:29:02.848417 # ok 1257 # SKIP Get and set data for VL 6704
7154 12:29:02.853382 # ok 1258 Set VL 6720
7155 12:29:02.853596 # ok 1259 # SKIP Disabled ZA for VL 6720
7156 12:29:02.853936 # ok 1260 # SKIP Get and set data for VL 6720
7157 12:29:02.854038 # ok 1261 Set VL 6736
7158 12:29:02.854118 # ok 1262 # SKIP Disabled ZA for VL 6736
7159 12:29:02.854209 # ok 1263 # SKIP Get and set data for VL 6736
7160 12:29:02.854295 # ok 1264 Set VL 6752
7161 12:29:02.854381 # ok 1265 # SKIP Disabled ZA for VL 6752
7162 12:29:02.854459 # ok 1266 # SKIP Get and set data for VL 6752
7163 12:29:02.854540 # ok 1267 Set VL 6768
7164 12:29:02.854623 # ok 1268 # SKIP Disabled ZA for VL 6768
7165 12:29:02.854747 # ok 1269 # SKIP Get and set data for VL 6768
7166 12:29:02.854826 # ok 1270 Set VL 6784
7167 12:29:02.854893 # ok 1271 # SKIP Disabled ZA for VL 6784
7168 12:29:02.854954 # ok 1272 # SKIP Get and set data for VL 6784
7169 12:29:02.855014 # ok 1273 Set VL 6800
7170 12:29:02.855074 # ok 1274 # SKIP Disabled ZA for VL 6800
7171 12:29:02.855133 # ok 1275 # SKIP Get and set data for VL 6800
7172 12:29:02.855193 # ok 1276 Set VL 6816
7173 12:29:02.855267 # ok 1277 # SKIP Disabled ZA for VL 6816
7174 12:29:02.856097 # ok 1278 # SKIP Get and set data for VL 6816
7175 12:29:02.863372 # ok 1279 Set VL 6832
7176 12:29:02.863813 # ok 1280 # SKIP Disabled ZA for VL 6832
7177 12:29:02.863913 # ok 1281 # SKIP Get and set data for VL 6832
7178 12:29:02.864075 # ok 1282 Set VL 6848
7179 12:29:02.864247 # ok 1283 # SKIP Disabled ZA for VL 6848
7180 12:29:02.864427 # ok 1284 # SKIP Get and set data for VL 6848
7181 12:29:02.864566 # ok 1285 Set VL 6864
7182 12:29:02.864755 # ok 1286 # SKIP Disabled ZA for VL 6864
7183 12:29:02.864956 # ok 1287 # SKIP Get and set data for VL 6864
7184 12:29:02.865117 # ok 1288 Set VL 6880
7185 12:29:02.865302 # ok 1289 # SKIP Disabled ZA for VL 6880
7186 12:29:02.865559 # ok 1290 # SKIP Get and set data for VL 6880
7187 12:29:02.865757 # ok 1291 Set VL 6896
7188 12:29:02.865959 # ok 1292 # SKIP Disabled ZA for VL 6896
7189 12:29:02.866112 # ok 1293 # SKIP Get and set data for VL 6896
7190 12:29:02.866293 # ok 1294 Set VL 6912
7191 12:29:02.866504 # ok 1295 # SKIP Disabled ZA for VL 6912
7192 12:29:02.866698 # ok 1296 # SKIP Get and set data for VL 6912
7193 12:29:02.866935 # ok 1297 Set VL 6928
7194 12:29:02.867160 # ok 1298 # SKIP Disabled ZA for VL 6928
7195 12:29:02.867368 # ok 1299 # SKIP Get and set data for VL 6928
7196 12:29:02.867518 # ok 1300 Set VL 6944
7197 12:29:02.867684 # ok 1301 # SKIP Disabled ZA for VL 6944
7198 12:29:02.867862 # ok 1302 # SKIP Get and set data for VL 6944
7199 12:29:02.868070 # ok 1303 Set VL 6960
7200 12:29:02.868203 # ok 1304 # SKIP Disabled ZA for VL 6960
7201 12:29:02.868321 # ok 1305 # SKIP Get and set data for VL 6960
7202 12:29:02.868436 # ok 1306 Set VL 6976
7203 12:29:02.868551 # ok 1307 # SKIP Disabled ZA for VL 6976
7204 12:29:02.868665 # ok 1308 # SKIP Get and set data for VL 6976
7205 12:29:02.868781 # ok 1309 Set VL 6992
7206 12:29:02.868897 # ok 1310 # SKIP Disabled ZA for VL 6992
7207 12:29:02.869015 # ok 1311 # SKIP Get and set data for VL 6992
7208 12:29:02.869130 # ok 1312 Set VL 7008
7209 12:29:02.869243 # ok 1313 # SKIP Disabled ZA for VL 7008
7210 12:29:02.869357 # ok 1314 # SKIP Get and set data for VL 7008
7211 12:29:02.869472 # ok 1315 Set VL 7024
7212 12:29:02.869586 # ok 1316 # SKIP Disabled ZA for VL 7024
7213 12:29:02.869720 # ok 1317 # SKIP Get and set data for VL 7024
7214 12:29:02.869836 # ok 1318 Set VL 7040
7215 12:29:02.869952 # ok 1319 # SKIP Disabled ZA for VL 7040
7216 12:29:02.870066 # ok 1320 # SKIP Get and set data for VL 7040
7217 12:29:02.870221 # ok 1321 Set VL 7056
7218 12:29:02.870343 # ok 1322 # SKIP Disabled ZA for VL 7056
7219 12:29:02.870458 # ok 1323 # SKIP Get and set data for VL 7056
7220 12:29:02.870571 # ok 1324 Set VL 7072
7221 12:29:02.870683 # ok 1325 # SKIP Disabled ZA for VL 7072
7222 12:29:02.870795 # ok 1326 # SKIP Get and set data for VL 7072
7223 12:29:02.870907 # ok 1327 Set VL 7088
7224 12:29:02.871020 # ok 1328 # SKIP Disabled ZA for VL 7088
7225 12:29:02.871132 # ok 1329 # SKIP Get and set data for VL 7088
7226 12:29:02.885637 # ok 1330 Set VL 7104
7227 12:29:02.885880 # ok 1331 # SKIP Disabled ZA for VL 7104
7228 12:29:02.886202 # ok 1332 # SKIP Get and set data for VL 7104
7229 12:29:02.886306 # ok 1333 Set VL 7120
7230 12:29:02.886394 # ok 1334 # SKIP Disabled ZA for VL 7120
7231 12:29:02.886479 # ok 1335 # SKIP Get and set data for VL 7120
7232 12:29:02.886563 # ok 1336 Set VL 7136
7233 12:29:02.886664 # ok 1337 # SKIP Disabled ZA for VL 7136
7234 12:29:02.886752 # ok 1338 # SKIP Get and set data for VL 7136
7235 12:29:02.886837 # ok 1339 Set VL 7152
7236 12:29:02.886923 # ok 1340 # SKIP Disabled ZA for VL 7152
7237 12:29:02.887023 # ok 1341 # SKIP Get and set data for VL 7152
7238 12:29:02.887107 # ok 1342 Set VL 7168
7239 12:29:02.887190 # ok 1343 # SKIP Disabled ZA for VL 7168
7240 12:29:02.887291 # ok 1344 # SKIP Get and set data for VL 7168
7241 12:29:02.887378 # ok 1345 Set VL 7184
7242 12:29:02.887477 # ok 1346 # SKIP Disabled ZA for VL 7184
7243 12:29:02.887579 # ok 1347 # SKIP Get and set data for VL 7184
7244 12:29:02.887666 # ok 1348 Set VL 7200
7245 12:29:02.887765 # ok 1349 # SKIP Disabled ZA for VL 7200
7246 12:29:02.887868 # ok 1350 # SKIP Get and set data for VL 7200
7247 12:29:02.887963 # ok 1351 Set VL 7216
7248 12:29:02.895535 # ok 1352 # SKIP Disabled ZA for VL 7216
7249 12:29:02.895775 # ok 1353 # SKIP Get and set data for VL 7216
7250 12:29:02.895867 # ok 1354 Set VL 7232
7251 12:29:02.895948 # ok 1355 # SKIP Disabled ZA for VL 7232
7252 12:29:02.896043 # ok 1356 # SKIP Get and set data for VL 7232
7253 12:29:02.896128 # ok 1357 Set VL 7248
7254 12:29:02.896206 # ok 1358 # SKIP Disabled ZA for VL 7248
7255 12:29:02.896289 # ok 1359 # SKIP Get and set data for VL 7248
7256 12:29:02.896371 # ok 1360 Set VL 7264
7257 12:29:02.900934 # ok 1361 # SKIP Disabled ZA for VL 7264
7258 12:29:02.901179 # ok 1362 # SKIP Get and set data for VL 7264
7259 12:29:02.901476 # ok 1363 Set VL 7280
7260 12:29:02.901572 # ok 1364 # SKIP Disabled ZA for VL 7280
7261 12:29:02.901675 # ok 1365 # SKIP Get and set data for VL 7280
7262 12:29:02.901767 # ok 1366 Set VL 7296
7263 12:29:02.901845 # ok 1367 # SKIP Disabled ZA for VL 7296
7264 12:29:02.901918 # ok 1368 # SKIP Get and set data for VL 7296
7265 12:29:02.901992 # ok 1369 Set VL 7312
7266 12:29:02.902090 # ok 1370 # SKIP Disabled ZA for VL 7312
7267 12:29:02.902169 # ok 1371 # SKIP Get and set data for VL 7312
7268 12:29:02.902264 # ok 1372 Set VL 7328
7269 12:29:02.902341 # ok 1373 # SKIP Disabled ZA for VL 7328
7270 12:29:02.902408 # ok 1374 # SKIP Get and set data for VL 7328
7271 12:29:02.902473 # ok 1375 Set VL 7344
7272 12:29:02.902543 # ok 1376 # SKIP Disabled ZA for VL 7344
7273 12:29:02.902611 # ok 1377 # SKIP Get and set data for VL 7344
7274 12:29:02.902689 # ok 1378 Set VL 7360
7275 12:29:02.902755 # ok 1379 # SKIP Disabled ZA for VL 7360
7276 12:29:02.902818 # ok 1380 # SKIP Get and set data for VL 7360
7277 12:29:02.902881 # ok 1381 Set VL 7376
7278 12:29:02.902944 # ok 1382 # SKIP Disabled ZA for VL 7376
7279 12:29:02.903007 # ok 1383 # SKIP Get and set data for VL 7376
7280 12:29:02.903073 # ok 1384 Set VL 7392
7281 12:29:02.903155 # ok 1385 # SKIP Disabled ZA for VL 7392
7282 12:29:02.903224 # ok 1386 # SKIP Get and set data for VL 7392
7283 12:29:02.903288 # ok 1387 Set VL 7408
7284 12:29:02.903349 # ok 1388 # SKIP Disabled ZA for VL 7408
7285 12:29:02.903411 # ok 1389 # SKIP Get and set data for VL 7408
7286 12:29:02.903487 # ok 1390 Set VL 7424
7287 12:29:02.903553 # ok 1391 # SKIP Disabled ZA for VL 7424
7288 12:29:02.903616 # ok 1392 # SKIP Get and set data for VL 7424
7289 12:29:02.903691 # ok 1393 Set VL 7440
7290 12:29:02.903756 # ok 1394 # SKIP Disabled ZA for VL 7440
7291 12:29:02.903820 # ok 1395 # SKIP Get and set data for VL 7440
7292 12:29:02.903896 # ok 1396 Set VL 7456
7293 12:29:02.903965 # ok 1397 # SKIP Disabled ZA for VL 7456
7294 12:29:02.913889 # ok 1398 # SKIP Get and set data for VL 7456
7295 12:29:02.914337 # ok 1399 Set VL 7472
7296 12:29:02.914425 # ok 1400 # SKIP Disabled ZA for VL 7472
7297 12:29:02.914495 # ok 1401 # SKIP Get and set data for VL 7472
7298 12:29:02.914597 # ok 1402 Set VL 7488
7299 12:29:02.914703 # ok 1403 # SKIP Disabled ZA for VL 7488
7300 12:29:02.914805 # ok 1404 # SKIP Get and set data for VL 7488
7301 12:29:02.914918 # ok 1405 Set VL 7504
7302 12:29:02.915097 # ok 1406 # SKIP Disabled ZA for VL 7504
7303 12:29:02.915301 # ok 1407 # SKIP Get and set data for VL 7504
7304 12:29:02.915473 # ok 1408 Set VL 7520
7305 12:29:02.915633 # ok 1409 # SKIP Disabled ZA for VL 7520
7306 12:29:02.915789 # ok 1410 # SKIP Get and set data for VL 7520
7307 12:29:02.915950 # ok 1411 Set VL 7536
7308 12:29:02.916106 # ok 1412 # SKIP Disabled ZA for VL 7536
7309 12:29:02.916226 # ok 1413 # SKIP Get and set data for VL 7536
7310 12:29:02.916340 # ok 1414 Set VL 7552
7311 12:29:02.916482 # ok 1415 # SKIP Disabled ZA for VL 7552
7312 12:29:02.916602 # ok 1416 # SKIP Get and set data for VL 7552
7313 12:29:02.916716 # ok 1417 Set VL 7568
7314 12:29:02.916828 # ok 1418 # SKIP Disabled ZA for VL 7568
7315 12:29:02.916942 # ok 1419 # SKIP Get and set data for VL 7568
7316 12:29:02.917055 # ok 1420 Set VL 7584
7317 12:29:02.917167 # ok 1421 # SKIP Disabled ZA for VL 7584
7318 12:29:02.917279 # ok 1422 # SKIP Get and set data for VL 7584
7319 12:29:02.917391 # ok 1423 Set VL 7600
7320 12:29:02.930020 # ok 1424 # SKIP Disabled ZA for VL 7600
7321 12:29:02.930605 # ok 1425 # SKIP Get and set data for VL 7600
7322 12:29:02.930810 # ok 1426 Set VL 7616
7323 12:29:02.931015 # ok 1427 # SKIP Disabled ZA for VL 7616
7324 12:29:02.931209 # ok 1428 # SKIP Get and set data for VL 7616
7325 12:29:02.931370 # ok 1429 Set VL 7632
7326 12:29:02.931545 # ok 1430 # SKIP Disabled ZA for VL 7632
7327 12:29:02.931750 # ok 1431 # SKIP Get and set data for VL 7632
7328 12:29:02.932012 # ok 1432 Set VL 7648
7329 12:29:02.932156 # ok 1433 # SKIP Disabled ZA for VL 7648
7330 12:29:02.932274 # ok 1434 # SKIP Get and set data for VL 7648
7331 12:29:02.932387 # ok 1435 Set VL 7664
7332 12:29:02.932502 # ok 1436 # SKIP Disabled ZA for VL 7664
7333 12:29:02.932616 # ok 1437 # SKIP Get and set data for VL 7664
7334 12:29:02.932728 # ok 1438 Set VL 7680
7335 12:29:02.932840 # ok 1439 # SKIP Disabled ZA for VL 7680
7336 12:29:02.932951 # ok 1440 # SKIP Get and set data for VL 7680
7337 12:29:02.933064 # ok 1441 Set VL 7696
7338 12:29:02.933175 # ok 1442 # SKIP Disabled ZA for VL 7696
7339 12:29:02.933287 # ok 1443 # SKIP Get and set data for VL 7696
7340 12:29:02.933399 # ok 1444 Set VL 7712
7341 12:29:02.933510 # ok 1445 # SKIP Disabled ZA for VL 7712
7342 12:29:02.933621 # ok 1446 # SKIP Get and set data for VL 7712
7343 12:29:02.941905 # ok 1447 Set VL 7728
7344 12:29:02.942500 # ok 1448 # SKIP Disabled ZA for VL 7728
7345 12:29:02.942674 # ok 1449 # SKIP Get and set data for VL 7728
7346 12:29:02.942830 # ok 1450 Set VL 7744
7347 12:29:02.942992 # ok 1451 # SKIP Disabled ZA for VL 7744
7348 12:29:02.943150 # ok 1452 # SKIP Get and set data for VL 7744
7349 12:29:02.943363 # ok 1453 Set VL 7760
7350 12:29:02.943562 # ok 1454 # SKIP Disabled ZA for VL 7760
7351 12:29:02.943750 # ok 1455 # SKIP Get and set data for VL 7760
7352 12:29:02.943922 # ok 1456 Set VL 7776
7353 12:29:02.944051 # ok 1457 # SKIP Disabled ZA for VL 7776
7354 12:29:02.944168 # ok 1458 # SKIP Get and set data for VL 7776
7355 12:29:02.944285 # ok 1459 Set VL 7792
7356 12:29:02.944399 # ok 1460 # SKIP Disabled ZA for VL 7792
7357 12:29:02.944514 # ok 1461 # SKIP Get and set data for VL 7792
7358 12:29:02.944629 # ok 1462 Set VL 7808
7359 12:29:02.944743 # ok 1463 # SKIP Disabled ZA for VL 7808
7360 12:29:02.944858 # ok 1464 # SKIP Get and set data for VL 7808
7361 12:29:02.944973 # ok 1465 Set VL 7824
7362 12:29:02.945088 # ok 1466 # SKIP Disabled ZA for VL 7824
7363 12:29:02.945204 # ok 1467 # SKIP Get and set data for VL 7824
7364 12:29:02.945319 # ok 1468 Set VL 7840
7365 12:29:02.945472 # ok 1469 # SKIP Disabled ZA for VL 7840
7366 12:29:02.945593 # ok 1470 # SKIP Get and set data for VL 7840
7367 12:29:02.953863 # ok 1471 Set VL 7856
7368 12:29:02.954324 # ok 1472 # SKIP Disabled ZA for VL 7856
7369 12:29:02.954526 # ok 1473 # SKIP Get and set data for VL 7856
7370 12:29:02.954665 # ok 1474 Set VL 7872
7371 12:29:02.954791 # ok 1475 # SKIP Disabled ZA for VL 7872
7372 12:29:02.954914 # ok 1476 # SKIP Get and set data for VL 7872
7373 12:29:02.955032 # ok 1477 Set VL 7888
7374 12:29:02.955176 # ok 1478 # SKIP Disabled ZA for VL 7888
7375 12:29:02.955296 # ok 1479 # SKIP Get and set data for VL 7888
7376 12:29:02.955412 # ok 1480 Set VL 7904
7377 12:29:02.955527 # ok 1481 # SKIP Disabled ZA for VL 7904
7378 12:29:02.955640 # ok 1482 # SKIP Get and set data for VL 7904
7379 12:29:02.957846 # ok 1483 Set VL 7920
7380 12:29:02.958003 # ok 1484 # SKIP Disabled ZA for VL 7920
7381 12:29:02.958128 # ok 1485 # SKIP Get and set data for VL 7920
7382 12:29:02.958244 # ok 1486 Set VL 7936
7383 12:29:02.958359 # ok 1487 # SKIP Disabled ZA for VL 7936
7384 12:29:02.958474 # ok 1488 # SKIP Get and set data for VL 7936
7385 12:29:02.958589 # ok 1489 Set VL 7952
7386 12:29:02.958704 # ok 1490 # SKIP Disabled ZA for VL 7952
7387 12:29:02.958819 # ok 1491 # SKIP Get and set data for VL 7952
7388 12:29:02.958934 # ok 1492 Set VL 7968
7389 12:29:02.959048 # ok 1493 # SKIP Disabled ZA for VL 7968
7390 12:29:02.959164 # ok 1494 # SKIP Get and set data for VL 7968
7391 12:29:02.959278 # ok 1495 Set VL 7984
7392 12:29:02.959392 # ok 1496 # SKIP Disabled ZA for VL 7984
7393 12:29:02.963738 # ok 1497 # SKIP Get and set data for VL 7984
7394 12:29:02.964153 # ok 1498 Set VL 8000
7395 12:29:02.964313 # ok 1499 # SKIP Disabled ZA for VL 8000
7396 12:29:02.965078 # ok 1500 # SKIP Get and set data for VL 8000
7397 12:29:02.965240 # ok 1501 Set VL 8016
7398 12:29:02.965606 # ok 1502 # SKIP Disabled ZA for VL 8016
7399 12:29:02.966229 # ok 1503 # SKIP Get and set data for VL 8016
7400 12:29:02.966613 # ok 1504 Set VL 8032
7401 12:29:02.966800 # ok 1505 # SKIP Disabled ZA for VL 8032
7402 12:29:02.966963 # ok 1506 # SKIP Get and set data for VL 8032
7403 12:29:02.967122 # ok 1507 Set VL 8048
7404 12:29:02.967502 # ok 1508 # SKIP Disabled ZA for VL 8048
7405 12:29:02.967663 # ok 1509 # SKIP Get and set data for VL 8048
7406 12:29:02.967797 # ok 1510 Set VL 8064
7407 12:29:02.967923 # ok 1511 # SKIP Disabled ZA for VL 8064
7408 12:29:02.968054 # ok 1512 # SKIP Get and set data for VL 8064
7409 12:29:02.968173 # ok 1513 Set VL 8080
7410 12:29:02.968287 # ok 1514 # SKIP Disabled ZA for VL 8080
7411 12:29:02.968400 # ok 1515 # SKIP Get and set data for VL 8080
7412 12:29:02.968514 # ok 1516 Set VL 8096
7413 12:29:02.968628 # ok 1517 # SKIP Disabled ZA for VL 8096
7414 12:29:02.968740 # ok 1518 # SKIP Get and set data for VL 8096
7415 12:29:02.968854 # ok 1519 Set VL 8112
7416 12:29:02.968994 # ok 1520 # SKIP Disabled ZA for VL 8112
7417 12:29:02.969114 # ok 1521 # SKIP Get and set data for VL 8112
7418 12:29:02.969234 # ok 1522 Set VL 8128
7419 12:29:02.969349 # ok 1523 # SKIP Disabled ZA for VL 8128
7420 12:29:02.973985 # ok 1524 # SKIP Get and set data for VL 8128
7421 12:29:02.974153 # ok 1525 Set VL 8144
7422 12:29:02.974296 # ok 1526 # SKIP Disabled ZA for VL 8144
7423 12:29:02.974416 # ok 1527 # SKIP Get and set data for VL 8144
7424 12:29:02.974553 # ok 1528 Set VL 8160
7425 12:29:02.974722 # ok 1529 # SKIP Disabled ZA for VL 8160
7426 12:29:02.974894 # ok 1530 # SKIP Get and set data for VL 8160
7427 12:29:02.975092 # ok 1531 Set VL 8176
7428 12:29:02.975295 # ok 1532 # SKIP Disabled ZA for VL 8176
7429 12:29:02.975429 # ok 1533 # SKIP Get and set data for VL 8176
7430 12:29:02.975544 # ok 1534 Set VL 8192
7431 12:29:02.975656 # ok 1535 # SKIP Disabled ZA for VL 8192
7432 12:29:02.975769 # ok 1536 # SKIP Get and set data for VL 8192
7433 12:29:02.975907 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7434 12:29:02.976028 ok 34 selftests: arm64: za-ptrace
7435 12:29:02.976146 # selftests: arm64: check_buffer_fill
7436 12:29:03.441986 # 1..20
7437 12:29:03.442225 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7438 12:29:03.442527 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7439 12:29:03.442637 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7440 12:29:03.442730 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7441 12:29:03.443095 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7442 12:29:03.443202 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7443 12:29:03.443291 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7444 12:29:03.443390 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7445 12:29:03.443490 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7446 12:29:03.449556 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7447 12:29:03.449814 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7448 12:29:03.450124 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7449 12:29:03.450232 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7450 12:29:03.450339 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7451 12:29:03.450442 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7452 12:29:03.450737 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7453 12:29:03.450855 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7454 12:29:03.451188 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7455 12:29:03.451395 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7456 12:29:03.451593 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7457 12:29:03.451727 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7458 12:29:03.474578 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7459 12:29:03.614265 # selftests: arm64: check_child_memory
7460 12:29:04.129316 # 1..12
7461 12:29:04.129568 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7462 12:29:04.129882 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7463 12:29:04.129988 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7464 12:29:04.130092 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7465 12:29:04.130379 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7466 12:29:04.130498 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7467 12:29:04.130796 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7468 12:29:04.130913 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7469 12:29:04.131253 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7470 12:29:04.139312 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7471 12:29:04.145569 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7472 12:29:04.146032 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7473 12:29:04.146194 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7474 12:29:04.177608 not ok 36 selftests: arm64: check_child_memory # exit=1
7475 12:29:04.336635 # selftests: arm64: check_gcr_el1_cswitch
7476 12:29:49.490365 <47>[ 102.578470] systemd-journald[109]: Sent WATCHDOG=1 notification.
7477 12:29:50.172941 <47>[ 103.261103] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
7478 12:29:50.173559 <47>[ 103.263221] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7479 12:29:50.173848 <47>[ 103.263767] systemd-journald[109]: Rotating...
7480 12:29:50.213740 <47>[ 103.303365] systemd-journald[109]: Reserving 333 entries in field hash table.
7481 12:29:50.266512 <47>[ 103.356360] systemd-journald[109]: Reserving 4408 entries in data hash table.
7482 12:29:50.297926 <47>[ 103.387787] systemd-journald[109]: Vacuuming...
7483 12:29:50.310874 <47>[ 103.400567] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7484 12:29:50.736414 # 1..1
7485 12:29:50.736704 # 1..1
7486 12:29:50.736797 # 1..1
7487 12:29:50.736886 # 1..1
7488 12:29:50.736973 # 1..1
7489 12:29:50.737063 # 1..1
7490 12:29:50.737365 # 1..1
7491 12:29:50.737469 # 1..1
7492 12:29:50.737559 # 1..1
7493 12:29:50.737643 # 1..1
7494 12:29:50.737738 # 1..1
7495 12:29:50.737819 # 1..1
7496 12:29:50.737902 # 1..1
7497 12:29:50.737984 # 1..1
7498 12:29:50.738061 # 1..1
7499 12:29:50.738138 # 1..1
7500 12:29:50.738215 # 1..1
7501 12:29:50.738290 # 1..1
7502 12:29:50.738365 # 1..1
7503 12:29:50.738440 # 1..1
7504 12:29:50.738521 # 1..1
7505 12:29:50.738601 # 1..1
7506 12:29:50.738685 # 1..1
7507 12:29:50.738774 # 1..1
7508 12:29:50.739117 # 1..1
7509 12:29:50.739217 # 1..1
7510 12:29:50.739307 # 1..1
7511 12:29:50.739393 # 1..1
7512 12:29:50.739479 # 1..1
7513 12:29:50.739561 # 1..1
7514 12:29:50.739648 # 1..1
7515 12:29:50.739734 # 1..1
7516 12:29:50.739818 # 1..1
7517 12:29:50.739905 # 1..1
7518 12:29:50.739992 # 1..1
7519 12:29:50.740078 # 1..1
7520 12:29:50.740188 # 1..1
7521 12:29:50.740277 # 1..1
7522 12:29:50.740366 # 1..1
7523 12:29:50.740455 # 1..1
7524 12:29:50.740541 # 1..1
7525 12:29:50.740628 # 1..1
7526 12:29:50.740717 # 1..1
7527 12:29:50.740804 # 1..1
7528 12:29:50.740894 # 1..1
7529 12:29:50.740982 # 1..1
7530 12:29:50.741069 # 1..1
7531 12:29:50.741155 # 1..1
7532 12:29:50.741237 # 1..1
7533 12:29:50.741322 # 1..1
7534 12:29:50.741405 # 1..1
7535 12:29:50.741487 # 1..1
7536 12:29:50.741570 # 1..1
7537 12:29:50.741653 # 1..1
7538 12:29:50.741733 # 1..1
7539 12:29:50.741811 # 1..1
7540 12:29:50.741888 # 1..1
7541 12:29:50.741968 # 1..1
7542 12:29:50.742054 # 1..1
7543 12:29:50.742136 # 1..1
7544 12:29:50.742219 # 1..1
7545 12:29:50.742306 # 1..1
7546 12:29:50.742392 # 1..1
7547 12:29:50.742476 # 1..1
7548 12:29:50.742558 # 1..1
7549 12:29:50.742640 # 1..1
7550 12:29:50.742725 # 1..1
7551 12:29:50.742815 # 1..1
7552 12:29:50.742900 # 1..1
7553 12:29:50.742983 # 1..1
7554 12:29:50.743068 # 1..1
7555 12:29:50.743153 # 1..1
7556 12:29:50.743241 # 1..1
7557 12:29:50.743329 # 1..1
7558 12:29:50.743413 # 1..1
7559 12:29:50.743498 # 1..1
7560 12:29:50.743585 # 1..1
7561 12:29:50.743667 # 1..1
7562 12:29:50.743753 # 1..1
7563 12:29:50.743839 # 1..1
7564 12:29:50.743915 # 1..1
7565 12:29:50.744001 # 1..1
7566 12:29:50.744088 # 1..1
7567 12:29:50.744176 # 1..1
7568 12:29:50.744265 # 1..1
7569 12:29:50.744355 # 1..1
7570 12:29:50.744445 # 1..1
7571 12:29:50.768716 # 1..1
7572 12:29:50.768969 # 1..1
7573 12:29:50.769059 # 1..1
7574 12:29:50.769142 # 1..1
7575 12:29:50.769451 # 1..1
7576 12:29:50.769560 # 1..1
7577 12:29:50.769657 # 1..1
7578 12:29:50.769741 # 1..1
7579 12:29:50.769820 # 1..1
7580 12:29:50.769900 # 1..1
7581 12:29:50.769980 # 1..1
7582 12:29:50.770059 # 1..1
7583 12:29:50.770139 # 1..1
7584 12:29:50.770218 # 1..1
7585 12:29:50.770297 # 1..1
7586 12:29:50.770376 # 1..1
7587 12:29:50.770456 # 1..1
7588 12:29:50.770535 # 1..1
7589 12:29:50.770614 # 1..1
7590 12:29:50.770693 # 1..1
7591 12:29:50.770772 # 1..1
7592 12:29:50.770854 # 1..1
7593 12:29:50.770932 # 1..1
7594 12:29:50.771010 # 1..1
7595 12:29:50.771089 # 1..1
7596 12:29:50.771167 # 1..1
7597 12:29:50.771267 # 1..1
7598 12:29:50.771349 # 1..1
7599 12:29:50.771428 # 1..1
7600 12:29:50.771506 # 1..1
7601 12:29:50.771584 # 1..1
7602 12:29:50.771662 # 1..1
7603 12:29:50.771740 # 1..1
7604 12:29:50.771819 # 1..1
7605 12:29:50.771905 # 1..1
7606 12:29:50.771984 # 1..1
7607 12:29:50.772063 # 1..1
7608 12:29:50.772142 # 1..1
7609 12:29:50.772221 # 1..1
7610 12:29:50.772300 # 1..1
7611 12:29:50.772379 # 1..1
7612 12:29:50.772457 # 1..1
7613 12:29:50.772536 # 1..1
7614 12:29:50.772615 # 1..1
7615 12:29:50.772694 # 1..1
7616 12:29:50.772772 # 1..1
7617 12:29:50.772851 # 1..1
7618 12:29:50.772929 # 1..1
7619 12:29:50.773009 # 1..1
7620 12:29:50.773088 # 1..1
7621 12:29:50.773167 # 1..1
7622 12:29:50.773246 # 1..1
7623 12:29:50.773325 # 1..1
7624 12:29:50.773403 # 1..1
7625 12:29:50.773482 # 1..1
7626 12:29:50.773561 # 1..1
7627 12:29:50.774345 # 1..1
7628 12:29:50.774457 # 1..1
7629 12:29:50.774543 # 1..1
7630 12:29:50.774624 # 1..1
7631 12:29:50.774705 # 1..1
7632 12:29:50.774785 # 1..1
7633 12:29:50.774866 # 1..1
7634 12:29:50.774947 # 1..1
7635 12:29:50.775027 # 1..1
7636 12:29:50.775108 # 1..1
7637 12:29:50.775189 # 1..1
7638 12:29:50.775269 # 1..1
7639 12:29:50.775349 # 1..1
7640 12:29:50.775430 # 1..1
7641 12:29:50.775510 # 1..1
7642 12:29:50.775591 # 1..1
7643 12:29:50.775672 # 1..1
7644 12:29:50.775752 # 1..1
7645 12:29:50.775833 # 1..1
7646 12:29:50.775913 # 1..1
7647 12:29:50.775994 # 1..1
7648 12:29:50.776074 # 1..1
7649 12:29:50.800642 # 1..1
7650 12:29:50.800887 # 1..1
7651 12:29:50.800984 # 1..1
7652 12:29:50.801071 # 1..1
7653 12:29:50.801376 # 1..1
7654 12:29:50.801485 # 1..1
7655 12:29:50.801572 # 1..1
7656 12:29:50.801666 # 1..1
7657 12:29:50.801752 # 1..1
7658 12:29:50.801836 # 1..1
7659 12:29:50.801920 # 1..1
7660 12:29:50.802004 # 1..1
7661 12:29:50.802090 # 1..1
7662 12:29:50.802175 # 1..1
7663 12:29:50.802261 # 1..1
7664 12:29:50.802346 # 1..1
7665 12:29:50.802431 # 1..1
7666 12:29:50.802517 # 1..1
7667 12:29:50.802603 # 1..1
7668 12:29:50.802691 # 1..1
7669 12:29:50.802777 # 1..1
7670 12:29:50.802858 # 1..1
7671 12:29:50.802951 # 1..1
7672 12:29:50.803039 # 1..1
7673 12:29:50.803125 # 1..1
7674 12:29:50.803210 # 1..1
7675 12:29:50.803293 # 1..1
7676 12:29:50.803379 # 1..1
7677 12:29:50.803462 # 1..1
7678 12:29:50.803546 # 1..1
7679 12:29:50.803630 # 1..1
7680 12:29:50.803716 # 1..1
7681 12:29:50.803825 # 1..1
7682 12:29:50.803921 # 1..1
7683 12:29:50.804008 # 1..1
7684 12:29:50.804095 # 1..1
7685 12:29:50.804180 # 1..1
7686 12:29:50.804265 # 1..1
7687 12:29:50.804352 # 1..1
7688 12:29:50.804437 # 1..1
7689 12:29:50.804523 # 1..1
7690 12:29:50.804608 # 1..1
7691 12:29:50.804693 # 1..1
7692 12:29:50.804777 # 1..1
7693 12:29:50.804863 # 1..1
7694 12:29:50.804949 # 1..1
7695 12:29:50.805034 # 1..1
7696 12:29:50.805122 # 1..1
7697 12:29:50.805209 # 1..1
7698 12:29:50.805296 # 1..1
7699 12:29:50.805383 # 1..1
7700 12:29:50.805470 # 1..1
7701 12:29:50.805558 # 1..1
7702 12:29:50.806429 # 1..1
7703 12:29:50.806538 # 1..1
7704 12:29:50.806630 # 1..1
7705 12:29:50.806721 # 1..1
7706 12:29:50.806812 # 1..1
7707 12:29:50.806902 # 1..1
7708 12:29:50.806990 # 1..1
7709 12:29:50.807078 # 1..1
7710 12:29:50.807168 # 1..1
7711 12:29:50.807259 # 1..1
7712 12:29:50.807350 # 1..1
7713 12:29:50.807440 # 1..1
7714 12:29:50.807530 # 1..1
7715 12:29:50.807621 # 1..1
7716 12:29:50.807707 # 1..1
7717 12:29:50.807794 # 1..1
7718 12:29:50.807883 # 1..1
7719 12:29:50.807973 # 1..1
7720 12:29:50.808062 # 1..1
7721 12:29:50.808152 # 1..1
7722 12:29:50.808240 # 1..1
7723 12:29:50.808328 # 1..1
7724 12:29:50.808415 # 1..1
7725 12:29:50.808501 # 1..1
7726 12:29:50.808585 # 1..1
7727 12:29:50.808672 # 1..1
7728 12:29:50.808760 # 1..1
7729 12:29:50.808849 # 1..1
7730 12:29:50.808945 # 1..1
7731 12:29:50.809038 # 1..1
7732 12:29:50.809127 # 1..1
7733 12:29:50.809217 # 1..1
7734 12:29:50.809301 # 1..1
7735 12:29:50.841826 # 1..1
7736 12:29:50.842074 # 1..1
7737 12:29:50.842169 # 1..1
7738 12:29:50.842254 # 1..1
7739 12:29:50.842340 # 1..1
7740 12:29:50.842424 # 1..1
7741 12:29:50.842722 # 1..1
7742 12:29:50.842862 # 1..1
7743 12:29:50.842961 # 1..1
7744 12:29:50.843038 # 1..1
7745 12:29:50.843120 # 1..1
7746 12:29:50.843202 # 1..1
7747 12:29:50.843284 # 1..1
7748 12:29:50.843365 # 1..1
7749 12:29:50.843447 # 1..1
7750 12:29:50.843527 # 1..1
7751 12:29:50.843607 # 1..1
7752 12:29:50.843688 # 1..1
7753 12:29:50.843771 # 1..1
7754 12:29:50.843853 # 1..1
7755 12:29:50.843938 # 1..1
7756 12:29:50.844032 # 1..1
7757 12:29:50.844118 # 1..1
7758 12:29:50.844204 # 1..1
7759 12:29:50.844290 # 1..1
7760 12:29:50.844377 # 1..1
7761 12:29:50.844462 # 1..1
7762 12:29:50.844549 # 1..1
7763 12:29:50.844632 # 1..1
7764 12:29:50.844715 # 1..1
7765 12:29:50.844797 # 1..1
7766 12:29:50.844881 # 1..1
7767 12:29:50.844968 # 1..1
7768 12:29:50.845052 # 1..1
7769 12:29:50.845136 # 1..1
7770 12:29:50.845223 # 1..1
7771 12:29:50.845308 # 1..1
7772 12:29:50.845393 # 1..1
7773 12:29:50.845496 # 1..1
7774 12:29:50.845584 # 1..1
7775 12:29:50.845676 # 1..1
7776 12:29:50.845758 # 1..1
7777 12:29:50.845838 # 1..1
7778 12:29:50.860636 # 1..1
7779 12:29:50.860856 # 1..1
7780 12:29:50.860948 # 1..1
7781 12:29:50.861037 # 1..1
7782 12:29:50.861123 # 1..1
7783 12:29:50.861210 # 1..1
7784 12:29:50.861297 # 1..1
7785 12:29:50.861383 # 1..1
7786 12:29:50.861692 # 1..1
7787 12:29:50.861799 # 1..1
7788 12:29:50.861884 # 1..1
7789 12:29:50.861968 # 1..1
7790 12:29:50.862060 # 1..1
7791 12:29:50.862144 # 1..1
7792 12:29:50.862227 # 1..1
7793 12:29:50.862308 # 1..1
7794 12:29:50.862389 # 1..1
7795 12:29:50.862474 # 1..1
7796 12:29:50.862556 # 1..1
7797 12:29:50.862640 # 1..1
7798 12:29:50.862723 # 1..1
7799 12:29:50.862806 # 1..1
7800 12:29:50.862890 # 1..1
7801 12:29:50.862976 # 1..1
7802 12:29:50.863058 # 1..1
7803 12:29:50.863140 # 1..1
7804 12:29:50.863222 # 1..1
7805 12:29:50.863302 # 1..1
7806 12:29:50.863385 # 1..1
7807 12:29:50.863470 # 1..1
7808 12:29:50.863554 # 1..1
7809 12:29:50.863640 # 1..1
7810 12:29:50.863723 # 1..1
7811 12:29:50.863808 # 1..1
7812 12:29:50.863893 # 1..1
7813 12:29:50.863980 # 1..1
7814 12:29:50.864067 # 1..1
7815 12:29:50.864155 # 1..1
7816 12:29:50.864241 # 1..1
7817 12:29:50.864326 # 1..1
7818 12:29:50.864413 # 1..1
7819 12:29:50.864499 # 1..1
7820 12:29:50.864606 # 1..1
7821 12:29:50.864691 # 1..1
7822 12:29:50.864776 # 1..1
7823 12:29:50.864863 # 1..1
7824 12:29:50.864950 # 1..1
7825 12:29:50.865040 # 1..1
7826 12:29:50.865125 # 1..1
7827 12:29:50.865209 # 1..1
7828 12:29:50.865293 # 1..1
7829 12:29:50.865376 # 1..1
7830 12:29:50.865460 # 1..1
7831 12:29:50.865544 # 1..1
7832 12:29:50.865629 # 1..1
7833 12:29:50.866359 # 1..1
7834 12:29:50.866454 # 1..1
7835 12:29:50.866537 # 1..1
7836 12:29:50.866619 # 1..1
7837 12:29:50.866705 # 1..1
7838 12:29:50.866790 # 1..1
7839 12:29:50.866877 # 1..1
7840 12:29:50.866964 # 1..1
7841 12:29:50.867052 # 1..1
7842 12:29:50.867139 # 1..1
7843 12:29:50.867227 # 1..1
7844 12:29:50.867314 # 1..1
7845 12:29:50.867401 # 1..1
7846 12:29:50.867488 # 1..1
7847 12:29:50.867575 # 1..1
7848 12:29:50.867661 # 1..1
7849 12:29:50.867748 # 1..1
7850 12:29:50.867835 # 1..1
7851 12:29:50.867922 # 1..1
7852 12:29:50.868012 # 1..1
7853 12:29:50.868108 # 1..1
7854 12:29:50.868193 # 1..1
7855 12:29:50.868284 # 1..1
7856 12:29:50.868375 # 1..1
7857 12:29:50.868461 # 1..1
7858 12:29:50.868548 # 1..1
7859 12:29:50.868633 # 1..1
7860 12:29:50.868720 # 1..1
7861 12:29:50.868804 # 1..1
7862 12:29:50.868889 # 1..1
7863 12:29:50.868974 # 1..1
7864 12:29:50.869065 # 1..1
7865 12:29:50.869153 # 1..1
7866 12:29:50.869242 # 1..1
7867 12:29:50.869328 # 1..1
7868 12:29:50.869414 # 1..1
7869 12:29:50.869502 # 1..1
7870 12:29:50.869587 # 1..1
7871 12:29:50.869679 # 1..1
7872 12:29:50.869767 # 1..1
7873 12:29:50.879883 # 1..1
7874 12:29:50.880083 # 1..1
7875 12:29:50.880179 # 1..1
7876 12:29:50.880267 # 1..1
7877 12:29:50.880354 # 1..1
7878 12:29:50.880739 # 1..1
7879 12:29:50.880960 # 1..1
7880 12:29:50.881127 # 1..1
7881 12:29:50.881269 # 1..1
7882 12:29:50.881386 # 1..1
7883 12:29:50.881520 # 1..1
7884 12:29:50.881705 # 1..1
7885 12:29:50.881882 # 1..1
7886 12:29:50.882060 # 1..1
7887 12:29:50.882230 # 1..1
7888 12:29:50.882401 # 1..1
7889 12:29:50.882558 # 1..1
7890 12:29:50.882676 # 1..1
7891 12:29:50.882790 # 1..1
7892 12:29:50.882951 # 1..1
7893 12:29:50.883120 # 1..1
7894 12:29:50.883263 # 1..1
7895 12:29:50.883378 # 1..1
7896 12:29:50.883493 # 1..1
7897 12:29:50.883606 # 1..1
7898 12:29:50.883718 # 1..1
7899 12:29:50.883830 # 1..1
7900 12:29:50.883995 # 1..1
7901 12:29:50.884126 # 1..1
7902 12:29:50.884241 # 1..1
7903 12:29:50.884356 # 1..1
7904 12:29:50.884468 # 1..1
7905 12:29:50.884581 # 1..1
7906 12:29:50.884692 # 1..1
7907 12:29:50.884806 # 1..1
7908 12:29:50.884919 # 1..1
7909 12:29:50.885033 # 1..1
7910 12:29:50.885148 # 1..1
7911 12:29:50.885261 # 1..1
7912 12:29:50.885373 # 1..1
7913 12:29:50.885524 # 1..1
7914 12:29:50.886379 # 1..1
7915 12:29:50.886545 # 1..1
7916 12:29:50.886667 # 1..1
7917 12:29:50.886782 # 1..1
7918 12:29:50.886940 # 1..1
7919 12:29:50.887075 # 1..1
7920 12:29:50.887193 # 1..1
7921 12:29:50.887309 # 1..1
7922 12:29:50.887440 # 1..1
7923 12:29:50.887557 # 1..1
7924 12:29:50.887673 # 1..1
7925 12:29:50.887789 # 1..1
7926 12:29:50.887945 # 1..1
7927 12:29:50.888090 # 1..1
7928 12:29:50.888206 # 1..1
7929 12:29:50.888321 # 1..1
7930 12:29:50.888436 # 1..1
7931 12:29:50.888552 # 1..1
7932 12:29:50.888666 # 1..1
7933 12:29:50.888781 # 1..1
7934 12:29:50.888895 # 1..1
7935 12:29:50.889010 # 1..1
7936 12:29:50.889126 # 1..1
7937 12:29:50.889240 # 1..1
7938 12:29:50.889354 # 1..1
7939 12:29:50.889469 # 1..1
7940 12:29:50.889584 # 1..1
7941 12:29:50.889751 # 1..1
7942 12:29:50.889897 # 1..1
7943 12:29:50.890017 # 1..1
7944 12:29:50.890133 # 1..1
7945 12:29:50.890249 # 1..1
7946 12:29:50.890365 # 1..1
7947 12:29:50.890480 # 1..1
7948 12:29:50.890595 # 1..1
7949 12:29:50.890710 # 1..1
7950 12:29:50.890822 # 1..1
7951 12:29:50.890985 # 1..1
7952 12:29:50.891117 # 1..1
7953 12:29:50.891235 # 1..1
7954 12:29:50.891363 # 1..1
7955 12:29:50.891483 # 1..1
7956 12:29:50.891599 # 1..1
7957 12:29:50.891714 # 1..1
7958 12:29:50.891830 # 1..1
7959 12:29:50.891998 # 1..1
7960 12:29:50.892132 # 1..1
7961 12:29:50.892247 # 1..1
7962 12:29:50.892363 # 1..1
7963 12:29:50.892478 # 1..1
7964 12:29:50.892592 # 1..1
7965 12:29:50.892706 # 1..1
7966 12:29:50.892822 # 1..1
7967 12:29:50.892938 # 1..1
7968 12:29:50.893053 # 1..1
7969 12:29:50.893167 # 1..1
7970 12:29:50.893282 # 1..1
7971 12:29:50.893397 # 1..1
7972 12:29:50.901131 #
7973 12:29:50.901324 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7974 12:29:51.290207 # selftests: arm64: check_ksm_options
7975 12:29:51.760444 # 1..4
7976 12:29:51.760848 # # Invalid MTE synchronous exception caught!
7977 12:29:51.825943 not ok 38 selftests: arm64: check_ksm_options # exit=1
7978 12:29:52.222429 # selftests: arm64: check_mmap_options
7979 12:29:53.437187 # 1..22
7980 12:29:53.437664 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
7981 12:29:53.437775 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
7982 12:29:53.437891 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
7983 12:29:53.438195 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
7984 12:29:53.438611 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
7985 12:29:53.438754 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7986 12:29:53.438874 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
7987 12:29:53.460363 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7988 12:29:53.460944 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
7989 12:29:53.461055 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7990 12:29:53.461151 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
7991 12:29:53.461556 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
7992 12:29:53.461777 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
7993 12:29:53.462177 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7994 12:29:53.462383 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
7995 12:29:53.462556 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7996 12:29:53.462758 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
7997 12:29:53.462921 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7998 12:29:53.463046 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
7999 12:29:53.480877 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8000 12:29:53.481515 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8001 12:29:53.481695 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8002 12:29:53.481896 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8003 12:29:53.540551 not ok 39 selftests: arm64: check_mmap_options # exit=1
8004 12:29:54.001703 # selftests: arm64: check_prctl
8005 12:29:54.433257 # TAP version 13
8006 12:29:54.433585 # 1..5
8007 12:29:54.434010 # ok 1 check_basic_read
8008 12:29:54.434157 # ok 2 NONE
8009 12:29:54.434306 # ok 3 SYNC
8010 12:29:54.434452 # ok 4 ASYNC
8011 12:29:54.434596 # ok 5 SYNC+ASYNC
8012 12:29:54.434740 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8013 12:29:54.481709 ok 40 selftests: arm64: check_prctl
8014 12:29:54.985927 # selftests: arm64: check_tags_inclusion
8015 12:29:55.387971 # 1..4
8016 12:29:55.388437 # # Unexpected fault recorded for 0xd00ffffb3b09000-0xd00ffffb3b09050 in mode 1
8017 12:29:55.388548 # not ok 1 Check an included tag value with sync mode
8018 12:29:55.388643 # # Unexpected fault recorded for 0x100ffffb3b09000-0x100ffffb3b09050 in mode 1
8019 12:29:55.388750 # not ok 2 Check different included tags value with sync mode
8020 12:29:55.388841 # ok 3 Check none included tags value with sync mode
8021 12:29:55.388946 # # Unexpected fault recorded for 0xc00ffffb3b09000-0xc00ffffb3b09050 in mode 1
8022 12:29:55.389249 # not ok 4 Check all included tags value with sync mode
8023 12:29:55.389350 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8024 12:29:55.450664 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8025 12:29:55.782165 # selftests: arm64: check_user_mem
8026 12:30:05.086945 # 1..64
8027 12:30:05.088343 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8028 12:30:05.088939 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8029 12:30:05.089592 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8030 12:30:05.089850 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8031 12:30:05.089961 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8032 12:30:05.090301 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8033 12:30:05.090530 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8034 12:30:05.090754 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8035 12:30:05.091036 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8036 12:30:05.091222 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8037 12:30:05.091318 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8038 12:30:05.091428 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8039 12:30:05.091520 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8040 12:30:05.091613 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8041 12:30:05.100454 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8042 12:30:05.100694 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8043 12:30:05.100783 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8044 12:30:05.101257 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8045 12:30:05.101385 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8046 12:30:05.101475 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8047 12:30:05.101556 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8048 12:30:05.101954 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8049 12:30:05.102373 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8050 12:30:05.102478 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8051 12:30:05.102591 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8052 12:30:05.102733 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8053 12:30:05.102836 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8054 12:30:05.102926 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8055 12:30:05.103027 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8056 12:30:05.103133 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8057 12:30:05.108560 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8058 12:30:05.109042 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8059 12:30:05.109449 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8060 12:30:05.109572 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8061 12:30:05.109737 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8062 12:30:05.110042 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8063 12:30:05.110180 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8064 12:30:05.110276 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8065 12:30:05.111184 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8066 12:30:05.111298 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8067 12:30:05.111410 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8068 12:30:05.111502 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8069 12:30:05.111816 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8070 12:30:05.111940 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8071 12:30:05.112709 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8072 12:30:05.112815 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8073 12:30:05.112905 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8074 12:30:05.112995 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8075 12:30:05.113081 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8076 12:30:05.113166 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8077 12:30:05.113254 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8078 12:30:06.921759 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8079 12:30:06.922402 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8080 12:30:06.922611 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8081 12:30:06.922789 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8082 12:30:06.923022 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8083 12:30:06.923196 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8084 12:30:06.923341 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8085 12:30:06.923541 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8086 12:30:06.929227 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8087 12:30:06.929763 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8088 12:30:06.929873 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8089 12:30:06.929965 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8090 12:30:06.930072 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8091 12:30:06.930162 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8092 12:30:06.977698 ok 42 selftests: arm64: check_user_mem
8093 12:30:07.161307 # selftests: arm64: btitest
8094 12:30:07.350313 # TAP version 13
8095 12:30:07.350767 # 1..18
8096 12:30:07.350878 # # HWCAP_PACA present
8097 12:30:07.350969 # # HWCAP2_BTI present
8098 12:30:07.351049 # # Test binary built for BTI
8099 12:30:07.351140 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8100 12:30:07.352702 # ok 1 nohint_func/call_using_br_x0
8101 12:30:07.353063 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8102 12:30:07.353173 # ok 2 nohint_func/call_using_br_x16
8103 12:30:07.353448 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8104 12:30:07.353554 # ok 3 nohint_func/call_using_blr
8105 12:30:07.353642 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8106 12:30:07.353763 # ok 4 bti_none_func/call_using_br_x0
8107 12:30:07.353873 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8108 12:30:07.353980 # ok 5 bti_none_func/call_using_br_x16
8109 12:30:07.354299 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8110 12:30:07.354407 # ok 6 bti_none_func/call_using_blr
8111 12:30:07.354701 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8112 12:30:07.354807 # ok 7 bti_c_func/call_using_br_x0
8113 12:30:07.354894 # ok 8 bti_c_func/call_using_br_x16
8114 12:30:07.354986 # ok 9 bti_c_func/call_using_blr
8115 12:30:07.355063 # ok 10 bti_j_func/call_using_br_x0
8116 12:30:07.360552 # ok 11 bti_j_func/call_using_br_x16
8117 12:30:07.361102 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8118 12:30:07.361262 # ok 12 bti_j_func/call_using_blr
8119 12:30:07.361418 # ok 13 bti_jc_func/call_using_br_x0
8120 12:30:07.361567 # ok 14 bti_jc_func/call_using_br_x16
8121 12:30:07.361716 # ok 15 bti_jc_func/call_using_blr
8122 12:30:07.361846 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8123 12:30:07.361946 # ok 16 paciasp_func/call_using_br_x0
8124 12:30:07.362038 # ok 17 paciasp_func/call_using_br_x16
8125 12:30:07.362130 # ok 18 paciasp_func/call_using_blr
8126 12:30:07.362221 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8127 12:30:07.382780 ok 43 selftests: arm64: btitest
8128 12:30:07.558508 # selftests: arm64: nobtitest
8129 12:30:07.705812 # TAP version 13
8130 12:30:07.706073 # 1..18
8131 12:30:07.706175 # # HWCAP_PACA present
8132 12:30:07.706476 # # HWCAP2_BTI present
8133 12:30:07.706576 # # Test binary not built for BTI
8134 12:30:07.706666 # ok 1 nohint_func/call_using_br_x0
8135 12:30:07.706757 # ok 2 nohint_func/call_using_br_x16
8136 12:30:07.706848 # ok 3 nohint_func/call_using_blr
8137 12:30:07.706934 # ok 4 bti_none_func/call_using_br_x0
8138 12:30:07.707023 # ok 5 bti_none_func/call_using_br_x16
8139 12:30:07.707106 # ok 6 bti_none_func/call_using_blr
8140 12:30:07.707188 # ok 7 bti_c_func/call_using_br_x0
8141 12:30:07.707268 # ok 8 bti_c_func/call_using_br_x16
8142 12:30:07.707366 # ok 9 bti_c_func/call_using_blr
8143 12:30:07.707452 # ok 10 bti_j_func/call_using_br_x0
8144 12:30:07.707535 # ok 11 bti_j_func/call_using_br_x16
8145 12:30:07.707620 # ok 12 bti_j_func/call_using_blr
8146 12:30:07.707708 # ok 13 bti_jc_func/call_using_br_x0
8147 12:30:07.708991 # ok 14 bti_jc_func/call_using_br_x16
8148 12:30:07.709099 # ok 15 bti_jc_func/call_using_blr
8149 12:30:07.709204 # ok 16 paciasp_func/call_using_br_x0
8150 12:30:07.709294 # ok 17 paciasp_func/call_using_br_x16
8151 12:30:07.709379 # ok 18 paciasp_func/call_using_blr
8152 12:30:07.709481 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8153 12:30:07.729633 ok 44 selftests: arm64: nobtitest
8154 12:30:07.882657 # selftests: arm64: hwcap
8155 12:30:08.048616 # TAP version 13
8156 12:30:08.048875 # 1..28
8157 12:30:08.048976 # # RNG present
8158 12:30:08.049070 # ok 1 cpuinfo_match_RNG
8159 12:30:08.049164 # ok 2 sigill_RNG
8160 12:30:08.049257 # # SME present
8161 12:30:08.049350 # ok 3 cpuinfo_match_SME
8162 12:30:08.049444 # ok 4 sigill_SME
8163 12:30:08.049719 # # SVE present
8164 12:30:08.049832 # ok 5 cpuinfo_match_SVE
8165 12:30:08.049927 # ok 6 sigill_SVE
8166 12:30:08.050016 # # SVE 2 present
8167 12:30:08.050104 # ok 7 cpuinfo_match_SVE 2
8168 12:30:08.050191 # ok 8 sigill_SVE 2
8169 12:30:08.050278 # # SVE AES present
8170 12:30:08.050365 # ok 9 cpuinfo_match_SVE AES
8171 12:30:08.050451 # ok 10 sigill_SVE AES
8172 12:30:08.050538 # # SVE2 PMULL present
8173 12:30:08.050624 # ok 11 cpuinfo_match_SVE2 PMULL
8174 12:30:08.050716 # ok 12 sigill_SVE2 PMULL
8175 12:30:08.050805 # # SVE2 BITPERM present
8176 12:30:08.050896 # ok 13 cpuinfo_match_SVE2 BITPERM
8177 12:30:08.050976 # ok 14 sigill_SVE2 BITPERM
8178 12:30:08.051051 # # SVE2 SHA3 present
8179 12:30:08.051125 # ok 15 cpuinfo_match_SVE2 SHA3
8180 12:30:08.051200 # ok 16 sigill_SVE2 SHA3
8181 12:30:08.051274 # # SVE2 SM4 present
8182 12:30:08.051371 # ok 17 cpuinfo_match_SVE2 SM4
8183 12:30:08.051448 # ok 18 sigill_SVE2 SM4
8184 12:30:08.051523 # # SVE2 I8MM present
8185 12:30:08.051598 # ok 19 cpuinfo_match_SVE2 I8MM
8186 12:30:08.051673 # ok 20 sigill_SVE2 I8MM
8187 12:30:08.051747 # # SVE2 F32MM present
8188 12:30:08.051823 # ok 21 cpuinfo_match_SVE2 F32MM
8189 12:30:08.051896 # ok 22 sigill_SVE2 F32MM
8190 12:30:08.051969 # # SVE2 F64MM present
8191 12:30:08.052049 # ok 23 cpuinfo_match_SVE2 F64MM
8192 12:30:08.052131 # ok 24 sigill_SVE2 F64MM
8193 12:30:08.052202 # # SVE2 BF16 present
8194 12:30:08.052279 # ok 25 cpuinfo_match_SVE2 BF16
8195 12:30:08.052357 # ok 26 sigill_SVE2 BF16
8196 12:30:08.052433 # ok 27 cpuinfo_match_SVE2 EBF16
8197 12:30:08.061362 # ok 28 # SKIP sigill_SVE2 EBF16
8198 12:30:08.061597 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8199 12:30:08.074266 ok 45 selftests: arm64: hwcap
8200 12:30:08.233219 # selftests: arm64: ptrace
8201 12:30:08.393292 # TAP version 13
8202 12:30:08.393539 # 1..7
8203 12:30:08.393627 # # Parent is 4201, child is 4202
8204 12:30:08.393725 # ok 1 read_tpidr_one
8205 12:30:08.393804 # ok 2 write_tpidr_one
8206 12:30:08.393881 # ok 3 verify_tpidr_one
8207 12:30:08.393958 # ok 4 count_tpidrs
8208 12:30:08.394042 # ok 5 tpidr2_write
8209 12:30:08.394122 # ok 6 tpidr2_read
8210 12:30:08.394414 # ok 7 write_tpidr_only
8211 12:30:08.394515 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8212 12:30:08.412677 ok 46 selftests: arm64: ptrace
8213 12:30:08.553090 # selftests: arm64: syscall-abi
8214 12:30:11.361312 # TAP version 13
8215 12:30:11.361693 # 1..514
8216 12:30:11.361877 # # SME with FA64
8217 12:30:11.362044 # ok 1 getpid() FPSIMD
8218 12:30:11.362414 # ok 2 getpid() SVE VL 256
8219 12:30:11.362531 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8220 12:30:11.362628 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8221 12:30:11.362718 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8222 12:30:11.362806 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8223 12:30:11.362916 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8224 12:30:11.363007 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8225 12:30:11.363095 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8226 12:30:11.363183 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8227 12:30:11.363270 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8228 12:30:11.363356 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8229 12:30:11.363443 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8230 12:30:11.363529 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8231 12:30:11.363616 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8232 12:30:11.363703 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8233 12:30:11.363789 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8234 12:30:11.363877 # ok 18 getpid() SVE VL 240
8235 12:30:11.363963 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8236 12:30:11.364049 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8237 12:30:11.364135 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8238 12:30:11.364242 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8239 12:30:11.368712 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8240 12:30:11.369068 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8241 12:30:11.369502 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8242 12:30:11.369692 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8243 12:30:11.369895 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8244 12:30:11.370106 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8245 12:30:11.370283 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8246 12:30:11.370435 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8247 12:30:11.370621 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8248 12:30:11.370759 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8249 12:30:11.370951 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8250 12:30:11.371125 # ok 34 getpid() SVE VL 224
8251 12:30:11.371271 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8252 12:30:11.371453 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8253 12:30:11.371628 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8254 12:30:11.371784 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8255 12:30:11.371976 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8256 12:30:11.372143 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8257 12:30:11.372267 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8258 12:30:11.372385 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8259 12:30:11.372501 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8260 12:30:11.372619 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8261 12:30:11.372792 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8262 12:30:11.375780 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8263 12:30:11.376200 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8264 12:30:11.376300 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8265 12:30:11.376409 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8266 12:30:11.376519 # ok 50 getpid() SVE VL 208
8267 12:30:11.376637 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8268 12:30:11.376744 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8269 12:30:11.376849 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8270 12:30:11.377170 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8271 12:30:11.377284 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8272 12:30:11.377402 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8273 12:30:11.377494 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8274 12:30:11.377582 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8275 12:30:11.377707 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8276 12:30:11.377803 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8277 12:30:11.377911 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8278 12:30:11.378003 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8279 12:30:11.378104 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8280 12:30:11.378405 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8281 12:30:11.378513 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8282 12:30:11.378604 # ok 66 getpid() SVE VL 192
8283 12:30:11.378689 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8284 12:30:11.378777 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8285 12:30:11.378864 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8286 12:30:11.378966 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8287 12:30:11.379060 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8288 12:30:11.379145 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8289 12:30:11.379228 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8290 12:30:11.379311 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8291 12:30:11.379408 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8292 12:30:11.383527 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8293 12:30:11.383769 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8294 12:30:11.384081 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8295 12:30:11.384265 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8296 12:30:11.384361 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8297 12:30:11.384447 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8298 12:30:11.384534 # ok 82 getpid() SVE VL 176
8299 12:30:11.384638 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8300 12:30:11.384724 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8301 12:30:11.384810 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8302 12:30:11.384894 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8303 12:30:11.384988 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8304 12:30:11.385075 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8305 12:30:11.385161 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8306 12:30:11.385248 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8307 12:30:11.385354 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8308 12:30:11.385444 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8309 12:30:11.385531 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8310 12:30:11.385615 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8311 12:30:11.385710 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8312 12:30:11.385795 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8313 12:30:11.385882 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8314 12:30:11.385971 # ok 98 getpid() SVE VL 160
8315 12:30:14.016099 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8316 12:30:14.016394 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8317 12:30:14.016606 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8318 12:30:14.016760 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8319 12:30:14.016923 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8320 12:30:14.017117 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8321 12:30:14.017285 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8322 12:30:14.017456 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8323 12:30:14.017623 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8324 12:30:14.017791 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8325 12:30:14.017996 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8326 12:30:14.018157 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8327 12:30:14.018319 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8328 12:30:14.018481 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8329 12:30:14.018646 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8330 12:30:14.018807 # ok 114 getpid() SVE VL 144
8331 12:30:14.018958 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8332 12:30:14.019078 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8333 12:30:14.019200 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8334 12:30:14.019317 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8335 12:30:14.019465 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8336 12:30:14.019591 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8337 12:30:14.019708 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8338 12:30:14.019822 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8339 12:30:14.019941 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8340 12:30:14.020055 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8341 12:30:14.020170 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8342 12:30:14.020295 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8343 12:30:14.020412 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8344 12:30:14.020528 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8345 12:30:14.020644 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8346 12:30:14.023972 # ok 130 getpid() SVE VL 128
8347 12:30:14.024288 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8348 12:30:14.024381 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8349 12:30:14.024482 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8350 12:30:14.024760 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8351 12:30:14.024844 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8352 12:30:14.024915 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8353 12:30:14.025006 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8354 12:30:14.025126 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8355 12:30:14.025225 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8356 12:30:14.025325 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8357 12:30:14.025597 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8358 12:30:14.025700 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8359 12:30:14.025782 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8360 12:30:14.025876 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8361 12:30:14.025972 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8362 12:30:14.026084 # ok 146 getpid() SVE VL 112
8363 12:30:14.026185 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8364 12:30:14.026299 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8365 12:30:14.026418 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8366 12:30:14.026523 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8367 12:30:14.026873 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8368 12:30:14.027057 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8369 12:30:14.027217 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8370 12:30:14.035609 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8371 12:30:14.036043 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8372 12:30:14.036128 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8373 12:30:14.036193 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8374 12:30:14.036255 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8375 12:30:14.036329 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8376 12:30:14.036392 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8377 12:30:14.036466 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8378 12:30:14.036529 # ok 162 getpid() SVE VL 96
8379 12:30:14.036602 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8380 12:30:14.036857 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8381 12:30:14.036925 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8382 12:30:14.037001 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8383 12:30:14.037078 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8384 12:30:14.037317 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8385 12:30:14.037443 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8386 12:30:14.037540 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8387 12:30:14.037645 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8388 12:30:14.037745 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8389 12:30:14.038041 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8390 12:30:14.038158 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8391 12:30:14.038248 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8392 12:30:14.038353 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8393 12:30:14.038462 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8394 12:30:14.038552 # ok 178 getpid() SVE VL 80
8395 12:30:14.038654 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8396 12:30:14.038745 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8397 12:30:14.038859 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8398 12:30:14.038964 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8399 12:30:14.039961 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8400 12:30:14.040257 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8401 12:30:14.040366 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8402 12:30:14.040457 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8403 12:30:14.040562 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8404 12:30:14.040654 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8405 12:30:14.040757 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8406 12:30:14.040859 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8407 12:30:14.040969 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8408 12:30:14.041261 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8409 12:30:14.041356 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8410 12:30:14.041463 # ok 194 getpid() SVE VL 64
8411 12:30:14.041549 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8412 12:30:16.562544 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8413 12:30:16.563122 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8414 12:30:16.563294 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8415 12:30:16.563474 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8416 12:30:16.571429 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8417 12:30:16.571846 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8418 12:30:16.571961 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8419 12:30:16.572056 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8420 12:30:16.572146 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8421 12:30:16.572254 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8422 12:30:16.572345 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8423 12:30:16.572769 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8424 12:30:16.572878 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8425 12:30:16.572972 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8426 12:30:16.573063 # ok 210 getpid() SVE VL 48
8427 12:30:16.573156 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8428 12:30:16.573247 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8429 12:30:16.573336 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8430 12:30:16.573424 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8431 12:30:16.573515 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8432 12:30:16.573807 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8433 12:30:16.573915 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8434 12:30:16.574002 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8435 12:30:16.574091 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8436 12:30:16.574181 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8437 12:30:16.574269 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8438 12:30:16.574358 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8439 12:30:16.574444 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8440 12:30:16.574533 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8441 12:30:16.574620 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8442 12:30:16.574728 # ok 226 getpid() SVE VL 32
8443 12:30:16.574818 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8444 12:30:16.574912 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8445 12:30:16.574999 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8446 12:30:16.575086 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8447 12:30:16.575174 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8448 12:30:16.575260 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8449 12:30:16.575347 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8450 12:30:16.575427 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8451 12:30:16.575511 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8452 12:30:16.575597 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8453 12:30:16.575703 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8454 12:30:16.575793 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8455 12:30:16.575877 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8456 12:30:16.575964 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8457 12:30:16.576050 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8458 12:30:16.576136 # ok 242 getpid() SVE VL 16
8459 12:30:16.576222 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8460 12:30:16.576310 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8461 12:30:16.576396 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8462 12:30:16.576503 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8463 12:30:16.576590 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8464 12:30:16.576674 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8465 12:30:16.576760 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8466 12:30:16.576847 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8467 12:30:16.576934 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8468 12:30:16.577040 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8469 12:30:16.577128 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8470 12:30:16.577217 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8471 12:30:16.577305 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8472 12:30:16.577391 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8473 12:30:16.577479 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8474 12:30:16.577568 # ok 258 sched_yield() FPSIMD
8475 12:30:16.578357 # ok 259 sched_yield() SVE VL 256
8476 12:30:16.578459 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8477 12:30:16.578545 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8478 12:30:16.578847 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8479 12:30:16.578960 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8480 12:30:16.579047 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8481 12:30:16.583565 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8482 12:30:16.584018 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8483 12:30:16.584230 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8484 12:30:16.584391 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8485 12:30:16.584565 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8486 12:30:16.584748 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8487 12:30:16.584926 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8488 12:30:16.585077 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8489 12:30:16.585237 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8490 12:30:16.585398 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8491 12:30:16.585545 # ok 275 sched_yield() SVE VL 240
8492 12:30:16.585772 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8493 12:30:16.585959 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8494 12:30:16.586122 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8495 12:30:16.586268 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8496 12:30:16.586441 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8497 12:30:16.586592 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8498 12:30:16.586786 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8499 12:30:16.586962 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8500 12:30:16.587113 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8501 12:30:16.587282 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8502 12:30:16.587429 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8503 12:30:16.587596 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8504 12:30:16.587756 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8505 12:30:16.587904 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8506 12:30:18.674163 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8507 12:30:18.674612 # ok 291 sched_yield() SVE VL 224
8508 12:30:18.674832 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8509 12:30:18.675005 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8510 12:30:18.675197 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8511 12:30:18.675363 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8512 12:30:18.683472 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8513 12:30:18.684068 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8514 12:30:18.684291 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8515 12:30:18.684485 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8516 12:30:18.684673 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8517 12:30:18.684857 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8518 12:30:18.685070 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8519 12:30:18.685244 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8520 12:30:18.685429 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8521 12:30:18.685598 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8522 12:30:18.685800 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8523 12:30:18.685931 # ok 307 sched_yield() SVE VL 208
8524 12:30:18.686048 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8525 12:30:18.686189 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8526 12:30:18.686387 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8527 12:30:18.686552 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8528 12:30:18.686720 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8529 12:30:18.686896 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8530 12:30:18.687069 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8531 12:30:18.687198 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8532 12:30:18.687317 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8533 12:30:18.687434 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8534 12:30:18.687553 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8535 12:30:18.687702 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8536 12:30:18.687830 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8537 12:30:18.688034 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8538 12:30:18.688232 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8539 12:30:18.688421 # ok 323 sched_yield() SVE VL 192
8540 12:30:18.688575 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8541 12:30:18.688773 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8542 12:30:18.688979 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8543 12:30:18.689426 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8544 12:30:18.689628 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8545 12:30:18.689774 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8546 12:30:18.689906 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8547 12:30:18.690067 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8548 12:30:18.690191 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8549 12:30:18.690340 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8550 12:30:18.690465 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8551 12:30:18.690586 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8552 12:30:18.690740 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8553 12:30:18.690912 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8554 12:30:18.691063 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8555 12:30:18.691289 # ok 339 sched_yield() SVE VL 176
8556 12:30:18.691458 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8557 12:30:18.691599 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8558 12:30:18.691792 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8559 12:30:18.696228 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8560 12:30:18.696549 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8561 12:30:18.696761 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8562 12:30:18.696935 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8563 12:30:18.697103 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8564 12:30:18.697302 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8565 12:30:18.697476 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8566 12:30:18.697644 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8567 12:30:18.697828 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8568 12:30:18.698029 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8569 12:30:18.698201 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8570 12:30:18.698367 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8571 12:30:18.698534 # ok 355 sched_yield() SVE VL 160
8572 12:30:18.698698 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8573 12:30:18.698899 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8574 12:30:18.699071 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8575 12:30:18.699237 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8576 12:30:18.699402 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8577 12:30:18.699567 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8578 12:30:18.699732 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8579 12:30:18.704345 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8580 12:30:18.704915 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8581 12:30:18.705119 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8582 12:30:18.705307 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8583 12:30:18.705492 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8584 12:30:18.705721 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8585 12:30:18.705909 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8586 12:30:18.706094 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8587 12:30:18.706277 # ok 371 sched_yield() SVE VL 144
8588 12:30:18.706459 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8589 12:30:18.706638 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8590 12:30:18.706847 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8591 12:30:18.707033 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8592 12:30:18.707217 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8593 12:30:20.883877 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8594 12:30:20.889492 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8595 12:30:20.889758 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8596 12:30:20.889950 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8597 12:30:20.890135 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8598 12:30:20.890320 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8599 12:30:20.890503 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8600 12:30:20.890689 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8601 12:30:20.890832 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8602 12:30:20.890978 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8603 12:30:20.891104 # ok 387 sched_yield() SVE VL 128
8604 12:30:20.891218 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8605 12:30:20.891334 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8606 12:30:20.891450 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8607 12:30:20.891565 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8608 12:30:20.891680 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8609 12:30:20.891795 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8610 12:30:20.891911 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8611 12:30:20.892025 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8612 12:30:20.892139 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8613 12:30:20.892252 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8614 12:30:20.892366 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8615 12:30:20.892480 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8616 12:30:20.892593 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8617 12:30:20.892707 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8618 12:30:20.892821 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8619 12:30:20.892934 # ok 403 sched_yield() SVE VL 112
8620 12:30:20.893049 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8621 12:30:20.893164 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8622 12:30:20.893278 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8623 12:30:20.893392 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8624 12:30:20.893571 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8625 12:30:20.893773 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8626 12:30:20.895564 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8627 12:30:20.896017 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8628 12:30:20.896137 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8629 12:30:20.896225 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8630 12:30:20.896309 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8631 12:30:20.896404 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8632 12:30:20.896488 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8633 12:30:20.896588 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8634 12:30:20.896679 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8635 12:30:20.896763 # ok 419 sched_yield() SVE VL 96
8636 12:30:20.897280 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8637 12:30:20.897392 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8638 12:30:20.897496 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8639 12:30:20.897599 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8640 12:30:20.897904 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8641 12:30:20.898009 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8642 12:30:20.898099 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8643 12:30:20.898202 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8644 12:30:20.898488 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8645 12:30:20.898602 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8646 12:30:20.898695 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8647 12:30:20.898786 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8648 12:30:20.898876 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8649 12:30:20.898981 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8650 12:30:20.899071 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8651 12:30:20.899158 # ok 435 sched_yield() SVE VL 80
8652 12:30:20.907810 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8653 12:30:20.908048 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8654 12:30:20.908154 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8655 12:30:20.908258 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8656 12:30:20.908347 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8657 12:30:20.908444 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8658 12:30:20.908726 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8659 12:30:20.908820 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8660 12:30:20.908908 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8661 12:30:20.909010 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8662 12:30:20.909099 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8663 12:30:20.909188 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8664 12:30:20.909292 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8665 12:30:20.909576 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8666 12:30:20.909675 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8667 12:30:20.909758 # ok 451 sched_yield() SVE VL 64
8668 12:30:20.909850 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8669 12:30:20.909932 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8670 12:30:20.910023 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8671 12:30:20.910105 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8672 12:30:20.910427 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8673 12:30:20.910623 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8674 12:30:20.910790 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8675 12:30:20.910986 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8676 12:30:20.911153 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8677 12:30:20.911278 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8678 12:30:20.911395 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8679 12:30:20.911512 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8680 12:30:21.643582 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8681 12:30:21.643838 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8682 12:30:21.643941 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8683 12:30:21.644412 # ok 467 sched_yield() SVE VL 48
8684 12:30:21.644523 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8685 12:30:21.644625 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8686 12:30:21.644704 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8687 12:30:21.644790 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8688 12:30:21.644879 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8689 12:30:21.644956 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8690 12:30:21.645036 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8691 12:30:21.645381 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8692 12:30:21.645601 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8693 12:30:21.645802 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8694 12:30:21.645977 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8695 12:30:21.646185 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8696 12:30:21.646399 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8697 12:30:21.646625 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8698 12:30:21.646847 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8699 12:30:21.647009 # ok 483 sched_yield() SVE VL 32
8700 12:30:21.647144 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8701 12:30:21.647263 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8702 12:30:21.647376 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8703 12:30:21.647488 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8704 12:30:21.647600 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8705 12:30:21.647713 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8706 12:30:21.647825 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8707 12:30:21.647937 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8708 12:30:21.648049 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8709 12:30:21.648162 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8710 12:30:21.662240 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8711 12:30:21.662692 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8712 12:30:21.662909 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8713 12:30:21.663059 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8714 12:30:21.663181 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8715 12:30:21.663325 # ok 499 sched_yield() SVE VL 16
8716 12:30:21.663450 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8717 12:30:21.664115 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8718 12:30:21.664435 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8719 12:30:21.664547 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8720 12:30:21.664837 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8721 12:30:21.664949 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8722 12:30:21.665041 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8723 12:30:21.665147 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8724 12:30:21.665432 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8725 12:30:21.665548 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8726 12:30:21.665632 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8727 12:30:21.665742 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8728 12:30:21.665834 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8729 12:30:21.665919 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8730 12:30:21.666012 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8731 12:30:21.666093 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8732 12:30:21.666741 ok 47 selftests: arm64: syscall-abi
8733 12:30:21.735860 # selftests: arm64: tpidr2
8734 12:30:21.895048 # TAP version 13
8735 12:30:21.895324 # 1..5
8736 12:30:21.898873 # # PID: 4236
8737 12:30:21.899298 # ok 1 default_value
8738 12:30:21.899446 # ok 2 write_read
8739 12:30:21.900233 # ok 3 write_sleep_read
8740 12:30:21.900670 # ok 4 write_fork_read
8741 12:30:21.900829 # ok 5 write_clone_read
8742 12:30:21.900975 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8743 12:30:21.914691 ok 48 selftests: arm64: tpidr2
8744 12:30:22.464841 arm64_tags_test pass
8745 12:30:22.465169 arm64_run_tags_test_sh pass
8746 12:30:22.465657 arm64_fake_sigreturn_bad_magic pass
8747 12:30:22.465857 arm64_fake_sigreturn_bad_size pass
8748 12:30:22.466037 arm64_fake_sigreturn_bad_size_for_magic0 pass
8749 12:30:22.466187 arm64_fake_sigreturn_duplicated_fpsimd pass
8750 12:30:22.466346 arm64_fake_sigreturn_misaligned_sp pass
8751 12:30:22.466507 arm64_fake_sigreturn_missing_fpsimd pass
8752 12:30:22.466654 arm64_fake_sigreturn_sme_change_vl pass
8753 12:30:22.466851 arm64_fake_sigreturn_sve_change_vl pass
8754 12:30:22.467018 arm64_mangle_pstate_invalid_compat_toggle pass
8755 12:30:22.467191 arm64_mangle_pstate_invalid_daif_bits pass
8756 12:30:22.467352 arm64_mangle_pstate_invalid_mode_el1h pass
8757 12:30:22.467518 arm64_mangle_pstate_invalid_mode_el1t pass
8758 12:30:22.467718 arm64_mangle_pstate_invalid_mode_el2h pass
8759 12:30:22.467913 arm64_mangle_pstate_invalid_mode_el2t pass
8760 12:30:22.468110 arm64_mangle_pstate_invalid_mode_el3h pass
8761 12:30:22.468281 arm64_mangle_pstate_invalid_mode_el3t pass
8762 12:30:22.468440 arm64_sme_trap_no_sm pass
8763 12:30:22.468601 arm64_sme_trap_non_streaming skip
8764 12:30:22.468767 arm64_sme_trap_za pass
8765 12:30:22.468932 arm64_sme_vl pass
8766 12:30:22.469091 arm64_ssve_regs pass
8767 12:30:22.469255 arm64_sve_regs pass
8768 12:30:22.469413 arm64_sve_vl pass
8769 12:30:22.469570 arm64_za_no_regs pass
8770 12:30:22.469760 arm64_za_regs pass
8771 12:30:22.469958 arm64_pac_global_corrupt_pac pass
8772 12:30:22.470119 arm64_pac_global_pac_instructions_not_nop pass
8773 12:30:22.470322 arm64_pac_global_pac_instructions_not_nop_generic pass
8774 12:30:22.470529 arm64_pac_global_single_thread_different_keys pass
8775 12:30:22.470775 arm64_pac_global_exec_changed_keys pass
8776 12:30:22.470964 arm64_pac_global_context_switch_keep_keys pass
8777 12:30:22.471183 arm64_pac_global_context_switch_keep_keys_generic pass
8778 12:30:22.471371 arm64_pac pass
8779 12:30:22.471560 arm64_fp-stress_FPSIMD-0-0 pass
8780 12:30:22.471693 arm64_fp-stress_SVE-VL-256-0 pass
8781 12:30:22.471808 arm64_fp-stress_SVE-VL-240-0 pass
8782 12:30:22.471968 arm64_fp-stress_SVE-VL-224-0 pass
8783 12:30:22.472149 arm64_fp-stress_SVE-VL-208-0 pass
8784 12:30:22.472277 arm64_fp-stress_SVE-VL-192-0 pass
8785 12:30:22.472392 arm64_fp-stress_SVE-VL-176-0 pass
8786 12:30:22.472514 arm64_fp-stress_SVE-VL-160-0 pass
8787 12:30:22.472633 arm64_fp-stress_SVE-VL-144-0 pass
8788 12:30:22.472749 arm64_fp-stress_SVE-VL-128-0 pass
8789 12:30:22.472863 arm64_fp-stress_SVE-VL-112-0 pass
8790 12:30:22.472979 arm64_fp-stress_SVE-VL-96-0 pass
8791 12:30:22.473095 arm64_fp-stress_SVE-VL-80-0 pass
8792 12:30:22.473209 arm64_fp-stress_SVE-VL-64-0 pass
8793 12:30:22.473324 arm64_fp-stress_SVE-VL-48-0 pass
8794 12:30:22.473438 arm64_fp-stress_SVE-VL-32-0 pass
8795 12:30:22.473552 arm64_fp-stress_SVE-VL-16-0 pass
8796 12:30:22.474103 arm64_fp-stress_SSVE-VL-256-0 pass
8797 12:30:22.474281 arm64_fp-stress_ZA-VL-256-0 pass
8798 12:30:22.474426 arm64_fp-stress_SSVE-VL-128-0 pass
8799 12:30:22.474800 arm64_fp-stress_ZA-VL-128-0 pass
8800 12:30:22.474941 arm64_fp-stress_SSVE-VL-64-0 pass
8801 12:30:22.475086 arm64_fp-stress_ZA-VL-64-0 pass
8802 12:30:22.475228 arm64_fp-stress_SSVE-VL-32-0 pass
8803 12:30:22.475371 arm64_fp-stress_ZA-VL-32-0 pass
8804 12:30:22.475512 arm64_fp-stress_SSVE-VL-16-0 pass
8805 12:30:22.475707 arm64_fp-stress_ZA-VL-16-0 pass
8806 12:30:22.475893 arm64_fp-stress pass
8807 12:30:22.476057 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8808 12:30:22.476205 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8809 12:30:22.476362 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8810 12:30:22.476508 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8811 12:30:22.476681 arm64_sve-ptrace_Set_SVE_VL_16 pass
8812 12:30:22.476831 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8813 12:30:22.476997 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8814 12:30:22.477133 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8815 12:30:22.477289 arm64_sve-ptrace_Set_SVE_VL_32 pass
8816 12:30:22.477433 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8817 12:30:22.477597 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8818 12:30:22.477770 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8819 12:30:22.477917 arm64_sve-ptrace_Set_SVE_VL_48 pass
8820 12:30:22.478085 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8821 12:30:22.478228 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8822 12:30:22.478385 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8823 12:30:22.478543 arm64_sve-ptrace_Set_SVE_VL_64 pass
8824 12:30:22.479320 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8825 12:30:22.479764 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8826 12:30:22.479938 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8827 12:30:22.481845 arm64_sve-ptrace_Set_SVE_VL_80 pass
8828 12:30:22.482071 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8829 12:30:22.482254 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8830 12:30:22.482404 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8831 12:30:22.482575 arm64_sve-ptrace_Set_SVE_VL_96 pass
8832 12:30:22.482719 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8833 12:30:22.482881 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8834 12:30:22.483039 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8835 12:30:22.483185 arm64_sve-ptrace_Set_SVE_VL_112 pass
8836 12:30:22.483353 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8837 12:30:22.483496 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8838 12:30:22.483657 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8839 12:30:22.483813 arm64_sve-ptrace_Set_SVE_VL_128 pass
8840 12:30:22.483959 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8841 12:30:22.484130 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8842 12:30:22.484273 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8843 12:30:22.484436 arm64_sve-ptrace_Set_SVE_VL_144 pass
8844 12:30:22.484588 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8845 12:30:22.484734 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8846 12:30:22.484902 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8847 12:30:22.485047 arm64_sve-ptrace_Set_SVE_VL_160 pass
8848 12:30:22.485210 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8849 12:30:22.485360 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8850 12:30:22.485715 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8851 12:30:22.485819 arm64_sve-ptrace_Set_SVE_VL_176 pass
8852 12:30:22.485904 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8853 12:30:22.485984 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8854 12:30:22.486069 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8855 12:30:22.486157 arm64_sve-ptrace_Set_SVE_VL_192 pass
8856 12:30:22.486247 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8857 12:30:22.486339 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8858 12:30:22.486430 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8859 12:30:22.487559 arm64_sve-ptrace_Set_SVE_VL_208 pass
8860 12:30:22.487669 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8861 12:30:22.487991 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8862 12:30:22.488113 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8863 12:30:22.488203 arm64_sve-ptrace_Set_SVE_VL_224 pass
8864 12:30:22.488512 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8865 12:30:22.488622 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8866 12:30:22.488716 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8867 12:30:22.488806 arm64_sve-ptrace_Set_SVE_VL_240 pass
8868 12:30:22.488896 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8869 12:30:22.489003 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8870 12:30:22.489088 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8871 12:30:22.489328 arm64_sve-ptrace_Set_SVE_VL_256 pass
8872 12:30:22.489434 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8873 12:30:22.489547 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8874 12:30:22.489640 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8875 12:30:22.489740 arm64_sve-ptrace_Set_SVE_VL_272 pass
8876 12:30:22.489825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8877 12:30:22.489903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8878 12:30:22.489997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8879 12:30:22.490084 arm64_sve-ptrace_Set_SVE_VL_288 pass
8880 12:30:22.490171 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8881 12:30:22.490260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8882 12:30:22.490368 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8883 12:30:22.490460 arm64_sve-ptrace_Set_SVE_VL_304 pass
8884 12:30:22.490549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8885 12:30:22.490886 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8886 12:30:22.490994 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8887 12:30:22.491086 arm64_sve-ptrace_Set_SVE_VL_320 pass
8888 12:30:22.491176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8889 12:30:22.491282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8890 12:30:22.495331 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8891 12:30:22.495438 arm64_sve-ptrace_Set_SVE_VL_336 pass
8892 12:30:22.495764 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8893 12:30:22.495999 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8894 12:30:22.496233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8895 12:30:22.496449 arm64_sve-ptrace_Set_SVE_VL_352 pass
8896 12:30:22.496598 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8897 12:30:22.496758 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8898 12:30:22.496919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8899 12:30:22.497044 arm64_sve-ptrace_Set_SVE_VL_368 pass
8900 12:30:22.497194 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8901 12:30:22.497314 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8902 12:30:22.497439 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8903 12:30:22.497549 arm64_sve-ptrace_Set_SVE_VL_384 pass
8904 12:30:22.497664 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8905 12:30:22.497807 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8906 12:30:22.497927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8907 12:30:22.498045 arm64_sve-ptrace_Set_SVE_VL_400 pass
8908 12:30:22.498121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8909 12:30:22.498194 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8910 12:30:22.498267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8911 12:30:22.498341 arm64_sve-ptrace_Set_SVE_VL_416 pass
8912 12:30:22.501796 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8913 12:30:22.501884 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8914 12:30:22.501950 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8915 12:30:22.502012 arm64_sve-ptrace_Set_SVE_VL_432 pass
8916 12:30:22.502076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8917 12:30:22.502137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8918 12:30:22.502198 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8919 12:30:22.502257 arm64_sve-ptrace_Set_SVE_VL_448 pass
8920 12:30:22.502318 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8921 12:30:22.503290 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8922 12:30:22.517513 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8923 12:30:22.517762 arm64_sve-ptrace_Set_SVE_VL_464 pass
8924 12:30:22.517946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8925 12:30:22.518353 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8926 12:30:22.518526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8927 12:30:22.518727 arm64_sve-ptrace_Set_SVE_VL_480 pass
8928 12:30:22.518917 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8929 12:30:22.519061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8930 12:30:22.519197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8931 12:30:22.519367 arm64_sve-ptrace_Set_SVE_VL_496 pass
8932 12:30:22.519528 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8933 12:30:22.519708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8934 12:30:22.519896 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8935 12:30:22.520057 arm64_sve-ptrace_Set_SVE_VL_512 pass
8936 12:30:22.520260 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8937 12:30:22.520461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8938 12:30:22.520644 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8939 12:30:22.520801 arm64_sve-ptrace_Set_SVE_VL_528 pass
8940 12:30:22.520961 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8941 12:30:22.521166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8942 12:30:22.521324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8943 12:30:22.521465 arm64_sve-ptrace_Set_SVE_VL_544 pass
8944 12:30:22.521627 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8945 12:30:22.521868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8946 12:30:22.522051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8947 12:30:22.522212 arm64_sve-ptrace_Set_SVE_VL_560 pass
8948 12:30:22.522347 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8949 12:30:22.522496 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8950 12:30:22.522650 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8951 12:30:22.522798 arm64_sve-ptrace_Set_SVE_VL_576 pass
8952 12:30:22.522966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8953 12:30:22.523138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8954 12:30:22.523271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8955 12:30:22.523391 arm64_sve-ptrace_Set_SVE_VL_592 pass
8956 12:30:22.523508 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8957 12:30:22.523673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8958 12:30:22.523820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8959 12:30:22.523941 arm64_sve-ptrace_Set_SVE_VL_608 pass
8960 12:30:22.524061 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8961 12:30:22.524179 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8962 12:30:22.524507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8963 12:30:22.524638 arm64_sve-ptrace_Set_SVE_VL_624 pass
8964 12:30:22.527486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8965 12:30:22.527899 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8966 12:30:22.528097 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8967 12:30:22.528278 arm64_sve-ptrace_Set_SVE_VL_640 pass
8968 12:30:22.528449 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8969 12:30:22.528601 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8970 12:30:22.528746 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8971 12:30:22.528886 arm64_sve-ptrace_Set_SVE_VL_656 pass
8972 12:30:22.529010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8973 12:30:22.529158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8974 12:30:22.529306 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8975 12:30:22.529425 arm64_sve-ptrace_Set_SVE_VL_672 pass
8976 12:30:22.529541 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8977 12:30:22.529678 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8978 12:30:22.529930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8979 12:30:22.530123 arm64_sve-ptrace_Set_SVE_VL_688 pass
8980 12:30:22.530286 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
8981 12:30:22.530448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
8982 12:30:22.530583 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
8983 12:30:22.530743 arm64_sve-ptrace_Set_SVE_VL_704 pass
8984 12:30:22.530880 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
8985 12:30:22.531010 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
8986 12:30:22.531158 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
8987 12:30:22.531280 arm64_sve-ptrace_Set_SVE_VL_720 pass
8988 12:30:22.531399 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
8989 12:30:22.531515 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
8990 12:30:22.531683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
8991 12:30:22.531832 arm64_sve-ptrace_Set_SVE_VL_736 pass
8992 12:30:22.535761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
8993 12:30:22.535950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
8994 12:30:22.536125 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
8995 12:30:22.536296 arm64_sve-ptrace_Set_SVE_VL_752 pass
8996 12:30:22.536444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
8997 12:30:22.536680 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
8998 12:30:22.536868 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
8999 12:30:22.537009 arm64_sve-ptrace_Set_SVE_VL_768 pass
9000 12:30:22.537167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9001 12:30:22.537300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9002 12:30:22.537420 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9003 12:30:22.537565 arm64_sve-ptrace_Set_SVE_VL_784 pass
9004 12:30:22.537734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9005 12:30:22.537888 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9006 12:30:22.538079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9007 12:30:22.538245 arm64_sve-ptrace_Set_SVE_VL_800 pass
9008 12:30:22.538399 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9009 12:30:22.538624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9010 12:30:22.538821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9011 12:30:22.538962 arm64_sve-ptrace_Set_SVE_VL_816 pass
9012 12:30:22.539082 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9013 12:30:22.539199 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9014 12:30:22.539345 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9015 12:30:22.539471 arm64_sve-ptrace_Set_SVE_VL_832 pass
9016 12:30:22.539590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9017 12:30:22.543404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9018 12:30:22.543859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9019 12:30:22.544053 arm64_sve-ptrace_Set_SVE_VL_848 pass
9020 12:30:22.544243 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9021 12:30:22.544406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9022 12:30:22.544602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9023 12:30:22.544773 arm64_sve-ptrace_Set_SVE_VL_864 pass
9024 12:30:22.544938 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9025 12:30:22.545103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9026 12:30:22.545269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9027 12:30:22.545461 arm64_sve-ptrace_Set_SVE_VL_880 pass
9028 12:30:22.545628 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9029 12:30:22.545845 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9030 12:30:22.546044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9031 12:30:22.546245 arm64_sve-ptrace_Set_SVE_VL_896 pass
9032 12:30:22.546408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9033 12:30:22.546590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9034 12:30:22.546777 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9035 12:30:22.546948 arm64_sve-ptrace_Set_SVE_VL_912 pass
9036 12:30:22.547079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9037 12:30:22.547195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9038 12:30:22.547308 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9039 12:30:22.547422 arm64_sve-ptrace_Set_SVE_VL_928 pass
9040 12:30:22.547536 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9041 12:30:22.547678 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9042 12:30:22.547802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9043 12:30:22.551405 arm64_sve-ptrace_Set_SVE_VL_944 pass
9044 12:30:22.551842 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9045 12:30:22.552020 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9046 12:30:22.552244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9047 12:30:22.552433 arm64_sve-ptrace_Set_SVE_VL_960 pass
9048 12:30:22.552604 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9049 12:30:22.552825 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9050 12:30:22.553013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9051 12:30:22.553202 arm64_sve-ptrace_Set_SVE_VL_976 pass
9052 12:30:22.553366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9053 12:30:22.553527 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9054 12:30:22.553765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9055 12:30:22.553918 arm64_sve-ptrace_Set_SVE_VL_992 pass
9056 12:30:22.554067 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9057 12:30:22.554221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9058 12:30:22.554362 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9059 12:30:22.554509 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9060 12:30:22.554684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9061 12:30:22.554849 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9062 12:30:22.555010 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9063 12:30:22.555134 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9064 12:30:22.555252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9065 12:30:22.555370 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9066 12:30:22.555488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9067 12:30:22.555670 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9068 12:30:22.555867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9069 12:30:22.559496 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9070 12:30:22.559713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9071 12:30:22.560104 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9072 12:30:22.560261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9073 12:30:22.560418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9074 12:30:22.560575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9075 12:30:22.560835 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9076 12:30:22.561020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9077 12:30:22.561176 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9078 12:30:22.561296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9079 12:30:22.561388 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9080 12:30:22.561495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9081 12:30:22.561587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9082 12:30:22.561717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9083 12:30:22.561872 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9084 12:30:22.587863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9085 12:30:22.588382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9086 12:30:22.588494 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9087 12:30:22.588580 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9088 12:30:22.588663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9089 12:30:22.588745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9090 12:30:22.588851 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9091 12:30:22.588946 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9092 12:30:22.589630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9093 12:30:22.589744 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9094 12:30:22.589840 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9095 12:30:22.589930 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9096 12:30:22.590014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9097 12:30:22.590094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9098 12:30:22.590172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9099 12:30:22.590523 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9100 12:30:22.590724 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9101 12:30:22.590871 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9102 12:30:22.590992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9103 12:30:22.591109 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9104 12:30:22.591228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9105 12:30:22.591370 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9106 12:30:22.591492 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9107 12:30:22.591609 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9108 12:30:22.595421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9109 12:30:22.595895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9110 12:30:22.596071 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9111 12:30:22.596266 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9112 12:30:22.596412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9113 12:30:22.596574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9114 12:30:22.596738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9115 12:30:22.596931 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9116 12:30:22.597096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9117 12:30:22.597269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9118 12:30:22.597421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9119 12:30:22.597582 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9120 12:30:22.597814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9121 12:30:22.598024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9122 12:30:22.598202 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9123 12:30:22.598368 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9124 12:30:22.598518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9125 12:30:22.598721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9126 12:30:22.598948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9127 12:30:22.599126 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9128 12:30:22.599277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9129 12:30:22.599397 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9130 12:30:22.599512 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9131 12:30:22.599626 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9132 12:30:22.599741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9133 12:30:22.599856 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9134 12:30:22.599997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9135 12:30:22.603325 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9136 12:30:22.603768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9137 12:30:22.603969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9138 12:30:22.604147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9139 12:30:22.604432 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9140 12:30:22.604660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9141 12:30:22.604876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9142 12:30:22.605151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9143 12:30:22.605356 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9144 12:30:22.605540 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9145 12:30:22.605727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9146 12:30:22.605897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9147 12:30:22.606064 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9148 12:30:22.606277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9149 12:30:22.606517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9150 12:30:22.606715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9151 12:30:22.606920 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9152 12:30:22.607083 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9153 12:30:22.607206 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9154 12:30:22.607324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9155 12:30:22.607439 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9156 12:30:22.607552 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9157 12:30:22.607667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9158 12:30:22.607782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9159 12:30:22.607896 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9160 12:30:22.608040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9161 12:30:22.608164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9162 12:30:22.611368 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9163 12:30:22.611838 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9164 12:30:22.612038 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9165 12:30:22.612261 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9166 12:30:22.612511 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9167 12:30:22.612709 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9168 12:30:22.612885 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9169 12:30:22.613056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9170 12:30:22.613275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9171 12:30:22.613455 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9172 12:30:22.613625 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9173 12:30:22.613806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9174 12:30:22.613996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9175 12:30:22.614221 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9176 12:30:22.614406 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9177 12:30:22.614614 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9178 12:30:22.614799 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9179 12:30:22.614968 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9180 12:30:22.615095 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9181 12:30:22.615211 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9182 12:30:22.615327 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9183 12:30:22.615440 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9184 12:30:22.615553 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9185 12:30:22.615668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9186 12:30:22.615808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9187 12:30:22.615946 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9188 12:30:22.616132 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9189 12:30:22.619414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9190 12:30:22.619762 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9191 12:30:22.619865 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9192 12:30:22.620423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9193 12:30:22.620525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9194 12:30:22.620626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9195 12:30:22.620711 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9196 12:30:22.620806 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9197 12:30:22.620901 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9198 12:30:22.621218 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9199 12:30:22.621419 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9200 12:30:22.621589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9201 12:30:22.621774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9202 12:30:22.621949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9203 12:30:22.622154 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9204 12:30:22.622319 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9205 12:30:22.622489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9206 12:30:22.622661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9207 12:30:22.622833 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9208 12:30:22.623056 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9209 12:30:22.623220 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9210 12:30:22.623395 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9211 12:30:22.623520 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9212 12:30:22.623637 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9213 12:30:22.623752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9214 12:30:22.623867 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9215 12:30:22.623981 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9216 12:30:22.627365 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9217 12:30:22.627673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9218 12:30:22.627788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9219 12:30:22.627904 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9220 12:30:22.627988 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9221 12:30:22.628088 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9222 12:30:22.628195 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9223 12:30:22.628307 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9224 12:30:22.628414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9225 12:30:22.628744 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9226 12:30:22.628853 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9227 12:30:22.628950 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9228 12:30:22.629045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9229 12:30:22.629343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9230 12:30:22.629453 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9231 12:30:22.629565 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9232 12:30:22.629682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9233 12:30:22.629790 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9234 12:30:22.629895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9235 12:30:22.629998 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9236 12:30:22.630096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9237 12:30:22.630426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9238 12:30:22.630533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9239 12:30:22.630643 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9240 12:30:22.630749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9241 12:30:22.630856 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9242 12:30:22.630963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9243 12:30:22.631069 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9244 12:30:22.662307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9245 12:30:22.662714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9246 12:30:22.662844 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9247 12:30:22.662941 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9248 12:30:22.663047 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9249 12:30:22.663173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9250 12:30:22.663263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9251 12:30:22.663586 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9252 12:30:22.663707 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9253 12:30:22.663797 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9254 12:30:22.663911 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9255 12:30:22.664218 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9256 12:30:22.664326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9257 12:30:22.664440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9258 12:30:22.664564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9259 12:30:22.664654 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9260 12:30:22.664754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9261 12:30:22.665151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9262 12:30:22.665377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9263 12:30:22.665683 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9264 12:30:22.665923 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9265 12:30:22.666113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9266 12:30:22.666283 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9267 12:30:22.666444 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9268 12:30:22.666609 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9269 12:30:22.666774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9270 12:30:22.666958 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9271 12:30:22.667087 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9272 12:30:22.667204 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9273 12:30:22.667320 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9274 12:30:22.667438 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9275 12:30:22.667552 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9276 12:30:22.667666 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9277 12:30:22.671354 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9278 12:30:22.671670 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9279 12:30:22.671771 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9280 12:30:22.671897 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9281 12:30:22.671988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9282 12:30:22.672083 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9283 12:30:22.672173 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9284 12:30:22.672476 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9285 12:30:22.672593 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9286 12:30:22.672904 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9287 12:30:22.673006 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9288 12:30:22.673115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9289 12:30:22.673202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9290 12:30:22.673523 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9291 12:30:22.673640 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9292 12:30:22.673765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9293 12:30:22.673890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9294 12:30:22.673989 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9295 12:30:22.674098 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9296 12:30:22.674403 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9297 12:30:22.674504 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9298 12:30:22.674613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9299 12:30:22.674704 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9300 12:30:22.674805 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9301 12:30:22.674911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9302 12:30:22.674999 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9303 12:30:22.679362 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9304 12:30:22.679865 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9305 12:30:22.680130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9306 12:30:22.680316 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9307 12:30:22.680521 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9308 12:30:22.680687 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9309 12:30:22.680841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9310 12:30:22.681004 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9311 12:30:22.681166 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9312 12:30:22.681322 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9313 12:30:22.681517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9314 12:30:22.681691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9315 12:30:22.681898 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9316 12:30:22.682096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9317 12:30:22.682270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9318 12:30:22.682480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9319 12:30:22.682692 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9320 12:30:22.683038 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9321 12:30:22.683188 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9322 12:30:22.683309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9323 12:30:22.683429 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9324 12:30:22.683544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9325 12:30:22.683660 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9326 12:30:22.683775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9327 12:30:22.683889 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9328 12:30:22.684003 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9329 12:30:22.684117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9330 12:30:22.687381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9331 12:30:22.687839 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9332 12:30:22.687981 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9333 12:30:22.688114 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9334 12:30:22.688236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9335 12:30:22.688376 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9336 12:30:22.688462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9337 12:30:22.688543 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9338 12:30:22.688619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9339 12:30:22.688714 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9340 12:30:22.688787 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9341 12:30:22.688879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9342 12:30:22.689141 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9343 12:30:22.689214 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9344 12:30:22.689291 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9345 12:30:22.689383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9346 12:30:22.689470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9347 12:30:22.689557 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9348 12:30:22.689841 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9349 12:30:22.689916 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9350 12:30:22.690009 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9351 12:30:22.690273 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9352 12:30:22.690345 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9353 12:30:22.690438 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9354 12:30:22.690524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9355 12:30:22.690611 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9356 12:30:22.690868 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9357 12:30:22.690941 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9358 12:30:22.695347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9359 12:30:22.695751 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9360 12:30:22.695842 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9361 12:30:22.695936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9362 12:30:22.696034 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9363 12:30:22.696107 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9364 12:30:22.696200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9365 12:30:22.696297 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9366 12:30:22.696383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9367 12:30:22.696652 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9368 12:30:22.696725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9369 12:30:22.697002 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9370 12:30:22.697076 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9371 12:30:22.697346 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9372 12:30:22.697430 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9373 12:30:22.697540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9374 12:30:22.697613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9375 12:30:22.697716 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9376 12:30:22.697972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9377 12:30:22.698059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9378 12:30:22.698147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9379 12:30:22.698234 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9380 12:30:22.698488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9381 12:30:22.698574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9382 12:30:22.698661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9383 12:30:22.698748 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9384 12:30:22.699003 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9385 12:30:22.703458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9386 12:30:22.703668 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9387 12:30:22.703969 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9388 12:30:22.704054 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9389 12:30:22.704146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9390 12:30:22.704243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9391 12:30:22.704323 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9392 12:30:22.704392 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9393 12:30:22.704477 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9394 12:30:22.704556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9395 12:30:22.704814 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9396 12:30:22.704911 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9397 12:30:22.704978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9398 12:30:22.705063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9399 12:30:22.705362 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9400 12:30:22.705452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9401 12:30:22.705568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9402 12:30:22.705694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9403 12:30:22.705806 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9404 12:30:22.735094 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9405 12:30:22.735566 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9406 12:30:22.735673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9407 12:30:22.735766 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9408 12:30:22.735868 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9409 12:30:22.735956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9410 12:30:22.736244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9411 12:30:22.736350 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9412 12:30:22.736453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9413 12:30:22.736550 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9414 12:30:22.736653 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9415 12:30:22.736758 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9416 12:30:22.736862 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9417 12:30:22.736973 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9418 12:30:22.737273 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9419 12:30:22.737378 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9420 12:30:22.737484 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9421 12:30:22.737586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9422 12:30:22.737880 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9423 12:30:22.738002 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9424 12:30:22.738095 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9425 12:30:22.738203 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9426 12:30:22.738297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9427 12:30:22.738404 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9428 12:30:22.738497 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9429 12:30:22.738613 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9430 12:30:22.738706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9431 12:30:22.738816 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9432 12:30:22.738906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9433 12:30:22.738997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9434 12:30:22.739105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9435 12:30:22.743322 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9436 12:30:22.743560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9437 12:30:22.743873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9438 12:30:22.743978 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9439 12:30:22.744067 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9440 12:30:22.744155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9441 12:30:22.744260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9442 12:30:22.744348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9443 12:30:22.744434 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9444 12:30:22.744544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9445 12:30:22.744633 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9446 12:30:22.744736 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9447 12:30:22.744821 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9448 12:30:22.744921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9449 12:30:22.745021 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9450 12:30:22.745123 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9451 12:30:22.745226 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9452 12:30:22.745331 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9453 12:30:22.745440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9454 12:30:22.745709 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9455 12:30:22.745821 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9456 12:30:22.745934 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9457 12:30:22.746025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9458 12:30:22.746127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9459 12:30:22.746230 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9460 12:30:22.746535 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9461 12:30:22.746641 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9462 12:30:22.746747 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9463 12:30:22.746835 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9464 12:30:22.746936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9465 12:30:22.751301 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9466 12:30:22.751763 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9467 12:30:22.751873 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9468 12:30:22.751966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9469 12:30:22.752056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9470 12:30:22.752163 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9471 12:30:22.752252 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9472 12:30:22.752353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9473 12:30:22.752458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9474 12:30:22.752549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9475 12:30:22.752653 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9476 12:30:22.752755 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9477 12:30:22.753066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9478 12:30:22.753173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9479 12:30:22.753281 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9480 12:30:22.753371 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9481 12:30:22.753473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9482 12:30:22.753776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9483 12:30:22.753880 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9484 12:30:22.754168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9485 12:30:22.754267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9486 12:30:22.754374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9487 12:30:22.754467 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9488 12:30:22.754561 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9489 12:30:22.754668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9490 12:30:22.754759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9491 12:30:22.754849 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9492 12:30:22.754955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9493 12:30:22.755046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9494 12:30:22.759332 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9495 12:30:22.759567 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9496 12:30:22.759873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9497 12:30:22.759977 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9498 12:30:22.760071 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9499 12:30:22.760164 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9500 12:30:22.760257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9501 12:30:22.760350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9502 12:30:22.760461 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9503 12:30:22.760558 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9504 12:30:22.760654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9505 12:30:22.760748 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9506 12:30:22.760858 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9507 12:30:22.760954 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9508 12:30:22.761046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9509 12:30:22.761154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9510 12:30:22.761249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9511 12:30:22.761361 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9512 12:30:22.761455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9513 12:30:22.761563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9514 12:30:22.761665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9515 12:30:22.761769 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9516 12:30:22.761854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9517 12:30:22.761936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9518 12:30:22.762037 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9519 12:30:22.762126 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9520 12:30:22.762213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9521 12:30:22.762320 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9522 12:30:22.762422 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9523 12:30:22.762512 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9524 12:30:22.762618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9525 12:30:22.762709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9526 12:30:22.762813 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9527 12:30:22.762900 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9528 12:30:22.763002 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9529 12:30:22.763094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9530 12:30:22.767277 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9531 12:30:22.767504 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9532 12:30:22.767814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9533 12:30:22.767919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9534 12:30:22.768009 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9535 12:30:22.768096 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9536 12:30:22.768181 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9537 12:30:22.768282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9538 12:30:22.768369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9539 12:30:22.768450 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9540 12:30:22.768535 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9541 12:30:22.768631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9542 12:30:22.768714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9543 12:30:22.768797 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9544 12:30:22.768896 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9545 12:30:22.768981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9546 12:30:22.769066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9547 12:30:22.769171 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9548 12:30:22.769259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9549 12:30:22.769358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9550 12:30:22.769444 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9551 12:30:22.769548 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9552 12:30:22.769661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9553 12:30:22.769753 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9554 12:30:22.769853 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9555 12:30:22.769939 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9556 12:30:22.770042 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9557 12:30:22.770145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9558 12:30:22.770249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9559 12:30:22.770355 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9560 12:30:22.770445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9561 12:30:22.770546 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9562 12:30:22.770648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9563 12:30:22.770749 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9564 12:30:22.789984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9565 12:30:22.790465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9566 12:30:22.790580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9567 12:30:22.790675 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9568 12:30:22.790764 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9569 12:30:22.790853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9570 12:30:22.790945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9571 12:30:22.791058 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9572 12:30:22.791153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9573 12:30:22.791246 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9574 12:30:22.791337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9575 12:30:22.791430 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9576 12:30:22.791541 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9577 12:30:22.791641 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9578 12:30:22.791734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9579 12:30:22.792024 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9580 12:30:22.792120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9581 12:30:22.792225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9582 12:30:22.792314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9583 12:30:22.792400 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9584 12:30:22.792489 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9585 12:30:22.792595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9586 12:30:22.792685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9587 12:30:22.792773 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9588 12:30:22.792873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9589 12:30:22.792962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9590 12:30:22.793048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9591 12:30:22.793151 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9592 12:30:22.793240 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9593 12:30:22.793328 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9594 12:30:22.793431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9595 12:30:22.793519 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9596 12:30:22.793620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9597 12:30:22.793721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9598 12:30:22.793826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9599 12:30:22.793917 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9600 12:30:22.794021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9601 12:30:22.794129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9602 12:30:22.794221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9603 12:30:22.794311 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9604 12:30:22.794410 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9605 12:30:22.794501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9606 12:30:22.794591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9607 12:30:22.794679 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9608 12:30:22.794780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9609 12:30:22.794867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9610 12:30:22.794953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9611 12:30:22.795057 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9612 12:30:22.795149 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9613 12:30:22.799315 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9614 12:30:22.799748 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9615 12:30:22.799851 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9616 12:30:22.799940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9617 12:30:22.800027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9618 12:30:22.800129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9619 12:30:22.800218 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9620 12:30:22.800304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9621 12:30:22.800406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9622 12:30:22.800491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9623 12:30:22.800596 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9624 12:30:22.800697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9625 12:30:22.801001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9626 12:30:22.801118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9627 12:30:22.801205 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9628 12:30:22.801305 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9629 12:30:22.801405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9630 12:30:22.801507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9631 12:30:22.801608 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9632 12:30:22.801925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9633 12:30:22.802027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9634 12:30:22.802129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9635 12:30:22.802231 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9636 12:30:22.802330 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9637 12:30:22.802431 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9638 12:30:22.802699 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9639 12:30:22.802808 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9640 12:30:22.802918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9641 12:30:22.803026 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9642 12:30:22.808060 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9643 12:30:22.808291 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9644 12:30:22.808375 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9645 12:30:22.808458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9646 12:30:22.808538 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9647 12:30:22.808619 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9648 12:30:22.808704 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9649 12:30:22.808976 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9650 12:30:22.809068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9651 12:30:22.809134 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9652 12:30:22.809195 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9653 12:30:22.809256 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9654 12:30:22.809320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9655 12:30:22.809401 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9656 12:30:22.809505 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9657 12:30:22.809592 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9658 12:30:22.809692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9659 12:30:22.809771 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9660 12:30:22.809845 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9661 12:30:22.809919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9662 12:30:22.810000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9663 12:30:22.810076 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9664 12:30:22.810153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9665 12:30:22.810250 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9666 12:30:22.810332 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9667 12:30:22.810409 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9668 12:30:22.810485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9669 12:30:22.810562 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9670 12:30:22.810639 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9671 12:30:22.810716 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9672 12:30:22.810809 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9673 12:30:22.810890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9674 12:30:22.810967 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9675 12:30:22.811048 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9676 12:30:22.811118 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9677 12:30:22.811193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9678 12:30:22.811255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9679 12:30:22.820113 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9680 12:30:22.820322 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9681 12:30:22.820388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9682 12:30:22.820450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9683 12:30:22.820511 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9684 12:30:22.820570 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9685 12:30:22.820635 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9686 12:30:22.820694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9687 12:30:22.820754 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9688 12:30:22.820813 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9689 12:30:22.820872 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9690 12:30:22.820931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9691 12:30:22.820994 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9692 12:30:22.821053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9693 12:30:22.821113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9694 12:30:22.821171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9695 12:30:22.821230 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9696 12:30:22.821288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9697 12:30:22.821347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9698 12:30:22.821405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9699 12:30:22.821464 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9700 12:30:22.821523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9701 12:30:22.821582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9702 12:30:22.821656 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9703 12:30:22.821718 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9704 12:30:22.821777 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9705 12:30:22.821835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9706 12:30:22.821894 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9707 12:30:22.821953 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9708 12:30:22.822012 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9709 12:30:22.822071 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9710 12:30:22.822130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9711 12:30:22.822188 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9712 12:30:22.822247 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9713 12:30:22.822305 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9714 12:30:22.822364 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9715 12:30:22.822423 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9716 12:30:22.822685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9717 12:30:22.822751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9718 12:30:22.822811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9719 12:30:22.823284 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9720 12:30:22.823538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9721 12:30:22.823646 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9722 12:30:22.823753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9723 12:30:22.823853 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9724 12:30:22.842950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9725 12:30:22.843384 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9726 12:30:22.843475 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9727 12:30:22.843544 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9728 12:30:22.843657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9729 12:30:22.843756 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9730 12:30:22.843878 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9731 12:30:22.843973 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9732 12:30:22.844085 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9733 12:30:22.844366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9734 12:30:22.844457 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9735 12:30:22.844531 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9736 12:30:22.844609 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9737 12:30:22.844694 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9738 12:30:22.844972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9739 12:30:22.845065 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9740 12:30:22.845173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9741 12:30:22.845259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9742 12:30:22.845360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9743 12:30:22.845433 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9744 12:30:22.845501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9745 12:30:22.845578 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9746 12:30:22.845670 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9747 12:30:22.845737 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9748 12:30:22.845994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9749 12:30:22.846075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9750 12:30:22.846144 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9751 12:30:22.846225 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9752 12:30:22.846293 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9753 12:30:22.846357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9754 12:30:22.846721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9755 12:30:22.846793 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9756 12:30:22.846859 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9757 12:30:22.846926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9758 12:30:22.847014 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9759 12:30:22.847093 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9760 12:30:22.847336 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9761 12:30:22.847403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9762 12:30:22.851281 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9763 12:30:22.851429 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9764 12:30:22.851700 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9765 12:30:22.851818 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9766 12:30:22.851915 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9767 12:30:22.852002 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9768 12:30:22.852099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9769 12:30:22.852196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9770 12:30:22.852265 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9771 12:30:22.852329 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9772 12:30:22.852403 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9773 12:30:22.852468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9774 12:30:22.852717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9775 12:30:22.852786 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9776 12:30:22.853030 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9777 12:30:22.853098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9778 12:30:22.853164 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9779 12:30:22.853226 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9780 12:30:22.853301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9781 12:30:22.853365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9782 12:30:22.853426 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9783 12:30:22.853488 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9784 12:30:22.853743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9785 12:30:22.853833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9786 12:30:22.853905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9787 12:30:22.853969 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9788 12:30:22.854044 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9789 12:30:22.854110 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9790 12:30:22.854172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9791 12:30:22.854246 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9792 12:30:22.854310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9793 12:30:22.854556 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9794 12:30:22.854627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9795 12:30:22.854692 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9796 12:30:22.854757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9797 12:30:22.854832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9798 12:30:22.854897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9799 12:30:22.854958 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9800 12:30:22.855031 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9801 12:30:22.855106 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9802 12:30:22.859323 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9803 12:30:22.859795 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9804 12:30:22.859921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9805 12:30:22.860013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9806 12:30:22.860096 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9807 12:30:22.860182 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9808 12:30:22.860268 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9809 12:30:22.860372 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9810 12:30:22.860460 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9811 12:30:22.860546 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9812 12:30:22.860645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9813 12:30:22.860746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9814 12:30:22.860842 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9815 12:30:22.860940 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9816 12:30:22.861251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9817 12:30:22.861370 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9818 12:30:22.861457 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9819 12:30:22.861553 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9820 12:30:22.861664 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9821 12:30:22.861977 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9822 12:30:22.862096 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9823 12:30:22.862197 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9824 12:30:22.862302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9825 12:30:22.862607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9826 12:30:22.862729 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9827 12:30:22.862831 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9828 12:30:22.862934 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9829 12:30:22.867414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9830 12:30:22.868364 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9831 12:30:22.868481 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9832 12:30:22.868574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9833 12:30:22.868665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9834 12:30:22.868756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9835 12:30:22.868840 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9836 12:30:22.868944 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9837 12:30:22.869033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9838 12:30:22.869121 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9839 12:30:22.869208 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9840 12:30:22.869294 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9841 12:30:22.869400 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9842 12:30:22.869485 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9843 12:30:22.869567 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9844 12:30:22.869677 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9845 12:30:22.869765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9846 12:30:22.870058 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9847 12:30:22.870151 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9848 12:30:22.870238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9849 12:30:22.870342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9850 12:30:22.870446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9851 12:30:22.870547 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9852 12:30:22.870648 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9853 12:30:22.870948 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9854 12:30:22.875408 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9855 12:30:22.875839 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9856 12:30:22.876155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9857 12:30:22.876250 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9858 12:30:22.876336 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9859 12:30:22.876423 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9860 12:30:22.876509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9861 12:30:22.876595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9862 12:30:22.876679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9863 12:30:22.876783 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9864 12:30:22.876872 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9865 12:30:22.876956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9866 12:30:22.877041 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9867 12:30:22.877125 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9868 12:30:22.877231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9869 12:30:22.877354 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9870 12:30:22.877451 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9871 12:30:22.877541 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9872 12:30:22.877654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9873 12:30:22.877772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9874 12:30:22.877881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9875 12:30:22.877984 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9876 12:30:22.878089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9877 12:30:22.878195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9878 12:30:22.878500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9879 12:30:22.878597 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9880 12:30:22.878698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9881 12:30:22.878801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9882 12:30:22.879090 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9883 12:30:22.883343 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9884 12:30:22.901881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9885 12:30:22.902142 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9886 12:30:22.902438 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9887 12:30:22.902549 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9888 12:30:22.902643 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9889 12:30:22.902731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9890 12:30:22.902841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9891 12:30:22.902934 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9892 12:30:22.903039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9893 12:30:22.903345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9894 12:30:22.903779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9895 12:30:22.903890 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9896 12:30:22.903981 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9897 12:30:22.904274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9898 12:30:22.904384 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9899 12:30:22.904477 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9900 12:30:22.904565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9901 12:30:22.904672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9902 12:30:22.904762 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9903 12:30:22.904850 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9904 12:30:22.904955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9905 12:30:22.905062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9906 12:30:22.905167 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9907 12:30:22.905275 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9908 12:30:22.905387 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9909 12:30:22.905724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9910 12:30:22.905930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9911 12:30:22.906045 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9912 12:30:22.906136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9913 12:30:22.906243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9914 12:30:22.906331 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9915 12:30:22.906433 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9916 12:30:22.906537 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9917 12:30:22.906642 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9918 12:30:22.906750 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9919 12:30:22.906858 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9920 12:30:22.906959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9921 12:30:22.911278 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9922 12:30:22.911738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9923 12:30:22.911850 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9924 12:30:22.911941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9925 12:30:22.912045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9926 12:30:22.912135 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9927 12:30:22.912222 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9928 12:30:22.912327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9929 12:30:22.912416 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9930 12:30:22.912503 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9931 12:30:22.912603 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9932 12:30:22.912691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9933 12:30:22.912777 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9934 12:30:22.912890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9935 12:30:22.912979 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9936 12:30:22.913068 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9937 12:30:22.913173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9938 12:30:22.913260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9939 12:30:22.913364 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9940 12:30:22.913454 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9941 12:30:22.913558 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9942 12:30:22.913671 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9943 12:30:22.913762 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9944 12:30:22.913865 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9945 12:30:22.913968 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9946 12:30:22.914072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9947 12:30:22.914180 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9948 12:30:22.914286 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9949 12:30:22.914391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9950 12:30:22.914497 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9951 12:30:22.914603 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9952 12:30:22.914710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9953 12:30:22.914823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9954 12:30:22.914931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9955 12:30:22.919270 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9956 12:30:22.919728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9957 12:30:22.919838 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9958 12:30:22.919933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9959 12:30:22.920021 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9960 12:30:22.920107 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9961 12:30:22.920212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9962 12:30:22.920298 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9963 12:30:22.920382 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9964 12:30:22.920488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9965 12:30:22.920577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9966 12:30:22.920679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9967 12:30:22.920765 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9968 12:30:22.920867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9969 12:30:22.920952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9970 12:30:22.921053 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9971 12:30:22.921139 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9972 12:30:22.921241 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9973 12:30:22.921565 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9974 12:30:22.921682 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9975 12:30:22.921787 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9976 12:30:22.922103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9977 12:30:22.922212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9978 12:30:22.922319 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9979 12:30:22.922407 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9980 12:30:22.922509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
9981 12:30:22.922597 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
9982 12:30:22.922701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
9983 12:30:22.922786 arm64_sve-ptrace_Set_SVE_VL_4704 pass
9984 12:30:22.922897 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
9985 12:30:22.922988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
9986 12:30:22.927311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
9987 12:30:22.927546 arm64_sve-ptrace_Set_SVE_VL_4720 pass
9988 12:30:22.927854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
9989 12:30:22.927962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
9990 12:30:22.928049 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
9991 12:30:22.928133 arm64_sve-ptrace_Set_SVE_VL_4736 pass
9992 12:30:22.928235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
9993 12:30:22.928322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
9994 12:30:22.928421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
9995 12:30:22.928510 arm64_sve-ptrace_Set_SVE_VL_4752 pass
9996 12:30:22.928613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
9997 12:30:22.928717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
9998 12:30:22.929041 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
9999 12:30:22.929146 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10000 12:30:22.929249 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10001 12:30:22.929554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10002 12:30:22.929675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10003 12:30:22.929781 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10004 12:30:22.929886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10005 12:30:22.930175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10006 12:30:22.930521 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10007 12:30:22.930625 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10008 12:30:22.930710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10009 12:30:22.930809 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10010 12:30:22.930918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10011 12:30:22.935337 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10012 12:30:22.935767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10013 12:30:22.935871 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10014 12:30:22.935970 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10015 12:30:22.936074 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10016 12:30:22.936164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10017 12:30:22.936252 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10018 12:30:22.936355 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10019 12:30:22.936446 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10020 12:30:22.936549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10021 12:30:22.936653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10022 12:30:22.936954 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10023 12:30:22.937060 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10024 12:30:22.937161 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10025 12:30:22.937461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10026 12:30:22.937567 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10027 12:30:22.937679 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10028 12:30:22.937781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10029 12:30:22.938102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10030 12:30:22.938209 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10031 12:30:22.938328 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10032 12:30:22.938460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10033 12:30:22.938578 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10034 12:30:22.938689 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10035 12:30:22.938794 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10036 12:30:22.943182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10037 12:30:22.943590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10038 12:30:22.943698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10039 12:30:22.943791 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10040 12:30:22.944078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10041 12:30:22.944173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10042 12:30:22.944296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10043 12:30:22.944381 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10044 12:30:22.964518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10045 12:30:22.964998 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10046 12:30:22.965109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10047 12:30:22.965206 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10048 12:30:22.965303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10049 12:30:22.965413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10050 12:30:22.965507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10051 12:30:22.965597 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10052 12:30:22.965725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10053 12:30:22.965816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10054 12:30:22.965921 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10055 12:30:22.966012 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10056 12:30:22.966120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10057 12:30:22.966227 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10058 12:30:22.966334 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10059 12:30:22.966443 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10060 12:30:22.966746 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10061 12:30:22.966847 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10062 12:30:22.966957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10063 12:30:22.967050 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10064 12:30:22.967154 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10065 12:30:22.967260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10066 12:30:22.967578 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10067 12:30:22.967675 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10068 12:30:22.967778 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10069 12:30:22.967895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10070 12:30:22.975231 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10071 12:30:22.975435 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10072 12:30:22.975744 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10073 12:30:22.975850 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10074 12:30:22.975941 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10075 12:30:22.976050 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10076 12:30:22.976142 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10077 12:30:22.976233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10078 12:30:22.976337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10079 12:30:22.976424 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10080 12:30:22.976529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10081 12:30:22.976618 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10082 12:30:22.976720 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10083 12:30:22.976811 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10084 12:30:22.976916 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10085 12:30:22.977011 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10086 12:30:22.977118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10087 12:30:22.977211 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10088 12:30:22.977318 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10089 12:30:22.977425 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10090 12:30:22.977531 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10091 12:30:22.977624 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10092 12:30:22.977723 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10093 12:30:22.977831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10094 12:30:22.977922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10095 12:30:22.978209 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10096 12:30:22.978506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10097 12:30:22.978607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10098 12:30:22.978701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10099 12:30:22.978794 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10100 12:30:22.978886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10101 12:30:22.978994 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10102 12:30:22.979085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10103 12:30:22.979176 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10104 12:30:22.979266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10105 12:30:22.979357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10106 12:30:22.979464 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10107 12:30:22.979556 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10108 12:30:22.979652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10109 12:30:22.979740 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10110 12:30:22.979846 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10111 12:30:22.979934 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10112 12:30:22.980019 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10113 12:30:22.980119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10114 12:30:22.980206 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10115 12:30:22.980289 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10116 12:30:22.980391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10117 12:30:22.980478 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10118 12:30:22.980579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10119 12:30:22.980680 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10120 12:30:22.980763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10121 12:30:22.980842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10122 12:30:22.980941 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10123 12:30:22.981029 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10124 12:30:22.981115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10125 12:30:22.981215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10126 12:30:22.981302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10127 12:30:22.981402 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10128 12:30:22.981489 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10129 12:30:22.981575 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10130 12:30:22.982048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10131 12:30:22.982152 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10132 12:30:22.982245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10133 12:30:22.982336 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10134 12:30:22.982625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10135 12:30:22.982725 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10136 12:30:22.982818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10137 12:30:22.982909 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10138 12:30:22.982996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10139 12:30:22.983084 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10140 12:30:22.983172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10141 12:30:22.983259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10142 12:30:22.983360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10143 12:30:22.983443 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10144 12:30:22.983529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10145 12:30:22.983618 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10146 12:30:22.987313 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10147 12:30:22.987438 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10148 12:30:22.987755 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10149 12:30:22.987874 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10150 12:30:22.987957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10151 12:30:22.988026 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10152 12:30:22.988089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10153 12:30:22.988165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10154 12:30:22.988230 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10155 12:30:22.988293 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10156 12:30:22.988367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10157 12:30:22.988431 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10158 12:30:22.988506 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10159 12:30:22.988582 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10160 12:30:22.988851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10161 12:30:22.988935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10162 12:30:22.989045 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10163 12:30:22.989123 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10164 12:30:22.989221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10165 12:30:22.989330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10166 12:30:22.989441 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10167 12:30:22.989555 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10168 12:30:22.989661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10169 12:30:22.989771 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10170 12:30:22.989862 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10171 12:30:22.989970 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10172 12:30:22.990084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10173 12:30:22.990175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10174 12:30:22.990284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10175 12:30:22.990381 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10176 12:30:22.990493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10177 12:30:22.990586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10178 12:30:22.990701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10179 12:30:22.990806 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10180 12:30:22.990913 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10181 12:30:22.995177 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10182 12:30:22.995553 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10183 12:30:22.995646 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10184 12:30:22.995732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10185 12:30:22.995831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10186 12:30:22.995917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10187 12:30:22.996019 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10188 12:30:22.996110 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10189 12:30:22.996372 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10190 12:30:22.996443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10191 12:30:22.996524 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10192 12:30:22.996602 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10193 12:30:22.996681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10194 12:30:22.996936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10195 12:30:22.997008 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10196 12:30:22.997086 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10197 12:30:22.997156 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10198 12:30:22.997234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10199 12:30:22.997313 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10200 12:30:22.997393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10201 12:30:22.998366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10202 12:30:22.998444 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10203 12:30:22.998506 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10204 12:30:23.018564 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10205 12:30:23.018816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10206 12:30:23.019172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10207 12:30:23.019351 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10208 12:30:23.019558 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10209 12:30:23.019769 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10210 12:30:23.020023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10211 12:30:23.020250 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10212 12:30:23.020477 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10213 12:30:23.020709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10214 12:30:23.020943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10215 12:30:23.021169 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10216 12:30:23.021451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10217 12:30:23.021689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10218 12:30:23.021918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10219 12:30:23.022132 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10220 12:30:23.022349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10221 12:30:23.022573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10222 12:30:23.022776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10223 12:30:23.022978 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10224 12:30:23.023168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10225 12:30:23.023314 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10226 12:30:23.023437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10227 12:30:23.023551 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10228 12:30:23.023697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10229 12:30:23.023846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10230 12:30:23.024030 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10231 12:30:23.024196 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10232 12:30:23.024339 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10233 12:30:23.024455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10234 12:30:23.024568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10235 12:30:23.024680 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10236 12:30:23.024793 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10237 12:30:23.024911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10238 12:30:23.025068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10239 12:30:23.027324 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10240 12:30:23.027452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10241 12:30:23.027770 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10242 12:30:23.027876 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10243 12:30:23.027964 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10244 12:30:23.028264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10245 12:30:23.028368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10246 12:30:23.028471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10247 12:30:23.028556 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10248 12:30:23.028657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10249 12:30:23.028925 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10250 12:30:23.029027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10251 12:30:23.029119 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10252 12:30:23.029490 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10253 12:30:23.029600 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10254 12:30:23.029698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10255 12:30:23.029998 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10256 12:30:23.030104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10257 12:30:23.030190 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10258 12:30:23.030290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10259 12:30:23.030377 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10260 12:30:23.030460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10261 12:30:23.030758 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10262 12:30:23.030859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10263 12:30:23.030948 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10264 12:30:23.031431 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10265 12:30:23.035233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10266 12:30:23.035601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10267 12:30:23.035708 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10268 12:30:23.035796 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10269 12:30:23.035895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10270 12:30:23.035986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10271 12:30:23.036093 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10272 12:30:23.036195 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10273 12:30:23.036501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10274 12:30:23.036605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10275 12:30:23.036707 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10276 12:30:23.036807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10277 12:30:23.036892 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10278 12:30:23.036992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10279 12:30:23.037300 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10280 12:30:23.037422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10281 12:30:23.037524 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10282 12:30:23.037626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10283 12:30:23.037924 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10284 12:30:23.038028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10285 12:30:23.038131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10286 12:30:23.038252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10287 12:30:23.038356 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10288 12:30:23.038646 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10289 12:30:23.038753 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10290 12:30:23.038839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10291 12:30:23.038938 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10292 12:30:23.043259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10293 12:30:23.043667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10294 12:30:23.043776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10295 12:30:23.043883 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10296 12:30:23.043973 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10297 12:30:23.044082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10298 12:30:23.044179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10299 12:30:23.044280 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10300 12:30:23.044385 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10301 12:30:23.044494 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10302 12:30:23.044605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10303 12:30:23.044882 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10304 12:30:23.045004 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10305 12:30:23.045112 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10306 12:30:23.045411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10307 12:30:23.045529 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10308 12:30:23.045616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10309 12:30:23.045729 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10310 12:30:23.045835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10311 12:30:23.045941 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10312 12:30:23.046053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10313 12:30:23.046164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10314 12:30:23.046468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10315 12:30:23.046573 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10316 12:30:23.046672 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10317 12:30:23.046773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10318 12:30:23.046873 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10319 12:30:23.046973 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10320 12:30:23.051452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10321 12:30:23.051665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10322 12:30:23.051765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10323 12:30:23.051856 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10324 12:30:23.051961 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10325 12:30:23.052059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10326 12:30:23.052170 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10327 12:30:23.052260 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10328 12:30:23.052365 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10329 12:30:23.052455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10330 12:30:23.052559 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10331 12:30:23.052650 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10332 12:30:23.052754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10333 12:30:23.052842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10334 12:30:23.052921 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10335 12:30:23.053023 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10336 12:30:23.053111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10337 12:30:23.053202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10338 12:30:23.053304 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10339 12:30:23.053391 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10340 12:30:23.053475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10341 12:30:23.053578 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10342 12:30:23.053675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10343 12:30:23.053763 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10344 12:30:23.053864 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10345 12:30:23.053953 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10346 12:30:23.054038 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10347 12:30:23.054142 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10348 12:30:23.054230 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10349 12:30:23.054334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10350 12:30:23.054420 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10351 12:30:23.054517 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10352 12:30:23.054606 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10353 12:30:23.054716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10354 12:30:23.054805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10355 12:30:23.054910 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10356 12:30:23.054998 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10357 12:30:23.055086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10358 12:30:23.055376 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10359 12:30:23.059350 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10360 12:30:23.059532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10361 12:30:23.059848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10362 12:30:23.059958 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10363 12:30:23.060054 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10364 12:30:23.078055 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10365 12:30:23.078299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10366 12:30:23.078392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10367 12:30:23.078683 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10368 12:30:23.078793 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10369 12:30:23.078882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10370 12:30:23.078965 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10371 12:30:23.079062 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10372 12:30:23.079145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10373 12:30:23.079226 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10374 12:30:23.079509 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10375 12:30:23.079622 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10376 12:30:23.079710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10377 12:30:23.079793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10378 12:30:23.079894 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10379 12:30:23.079980 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10380 12:30:23.080069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10381 12:30:23.080172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10382 12:30:23.080258 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10383 12:30:23.080344 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10384 12:30:23.080442 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10385 12:30:23.080543 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10386 12:30:23.080645 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10387 12:30:23.080940 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10388 12:30:23.081048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10389 12:30:23.081154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10390 12:30:23.081243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10391 12:30:23.081327 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10392 12:30:23.081426 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10393 12:30:23.081515 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10394 12:30:23.081613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10395 12:30:23.081726 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10396 12:30:23.081827 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10397 12:30:23.082134 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10398 12:30:23.082239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10399 12:30:23.082328 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10400 12:30:23.082423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10401 12:30:23.082504 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10402 12:30:23.082602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10403 12:30:23.082895 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10404 12:30:23.083014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10405 12:30:23.087259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10406 12:30:23.087620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10407 12:30:23.087740 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10408 12:30:23.087827 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10409 12:30:23.087932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10410 12:30:23.088024 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10411 12:30:23.088111 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10412 12:30:23.088214 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10413 12:30:23.088304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10414 12:30:23.088405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10415 12:30:23.088494 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10416 12:30:23.088579 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10417 12:30:23.088681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10418 12:30:23.088771 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10419 12:30:23.088971 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10420 12:30:23.089116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10421 12:30:23.089218 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10422 12:30:23.089346 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10423 12:30:23.089445 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10424 12:30:23.089550 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10425 12:30:23.089636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10426 12:30:23.089745 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10427 12:30:23.090053 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10428 12:30:23.090175 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10429 12:30:23.090267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10430 12:30:23.090365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10431 12:30:23.090465 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10432 12:30:23.090757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10433 12:30:23.090862 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10434 12:30:23.090966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10435 12:30:23.091065 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10436 12:30:23.095257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10437 12:30:23.095664 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10438 12:30:23.095767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10439 12:30:23.095852 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10440 12:30:23.095953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10441 12:30:23.096042 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10442 12:30:23.096132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10443 12:30:23.096218 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10444 12:30:23.096317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10445 12:30:23.096402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10446 12:30:23.096496 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10447 12:30:23.096580 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10448 12:30:23.096680 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10449 12:30:23.096965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10450 12:30:23.097070 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10451 12:30:23.097168 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10452 12:30:23.097254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10453 12:30:23.097573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10454 12:30:23.097686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10455 12:30:23.097825 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10456 12:30:23.097933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10457 12:30:23.098069 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10458 12:30:23.098177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10459 12:30:23.098261 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10460 12:30:23.098361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10461 12:30:23.098460 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10462 12:30:23.098548 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10463 12:30:23.098649 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10464 12:30:23.098736 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10465 12:30:23.098836 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10466 12:30:23.098938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10467 12:30:23.099040 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10468 12:30:23.103323 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10469 12:30:23.103710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10470 12:30:23.103813 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10471 12:30:23.103901 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10472 12:30:23.103985 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10473 12:30:23.104081 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10474 12:30:23.104167 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10475 12:30:23.104265 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10476 12:30:23.104350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10477 12:30:23.104448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10478 12:30:23.104533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10479 12:30:23.104630 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10480 12:30:23.104715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10481 12:30:23.104822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10482 12:30:23.105116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10483 12:30:23.105244 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10484 12:30:23.105339 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10485 12:30:23.106400 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10486 12:30:23.106514 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10487 12:30:23.106606 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10488 12:30:23.106697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10489 12:30:23.106789 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10490 12:30:23.106877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10491 12:30:23.106966 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10492 12:30:23.107056 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10493 12:30:23.107145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10494 12:30:23.107229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10495 12:30:23.107312 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10496 12:30:23.107600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10497 12:30:23.107711 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10498 12:30:23.107808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10499 12:30:23.107902 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10500 12:30:23.107996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10501 12:30:23.108090 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10502 12:30:23.108182 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10503 12:30:23.111496 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10504 12:30:23.111668 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10505 12:30:23.111758 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10506 12:30:23.111863 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10507 12:30:23.111953 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10508 12:30:23.112053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10509 12:30:23.112153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10510 12:30:23.112261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10511 12:30:23.112559 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10512 12:30:23.112665 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10513 12:30:23.112769 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10514 12:30:23.112872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10515 12:30:23.113159 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10516 12:30:23.113266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10517 12:30:23.113368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10518 12:30:23.113453 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10519 12:30:23.113551 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10520 12:30:23.113664 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10521 12:30:23.113753 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10522 12:30:23.114053 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10523 12:30:23.114163 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10524 12:30:23.137581 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10525 12:30:23.137836 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10526 12:30:23.138136 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10527 12:30:23.138244 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10528 12:30:23.138334 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10529 12:30:23.138419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10530 12:30:23.138502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10531 12:30:23.138586 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10532 12:30:23.138688 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10533 12:30:23.138773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10534 12:30:23.138856 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10535 12:30:23.138942 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10536 12:30:23.139025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10537 12:30:23.139129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10538 12:30:23.139219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10539 12:30:23.139305 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10540 12:30:23.139399 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10541 12:30:23.139480 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10542 12:30:23.139577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10543 12:30:23.139659 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10544 12:30:23.139752 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10545 12:30:23.139832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10546 12:30:23.139923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10547 12:30:23.140002 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10548 12:30:23.140093 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10549 12:30:23.140173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10550 12:30:23.140269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10551 12:30:23.140348 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10552 12:30:23.140439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10553 12:30:23.140531 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10554 12:30:23.140623 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10555 12:30:23.140715 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10556 12:30:23.140807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10557 12:30:23.140898 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10558 12:30:23.141430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10559 12:30:23.141536 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10560 12:30:23.141618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10561 12:30:23.141708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10562 12:30:23.141803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10563 12:30:23.142095 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10564 12:30:23.142200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10565 12:30:23.142309 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10566 12:30:23.142445 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10567 12:30:23.142538 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10568 12:30:23.142667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10569 12:30:23.142781 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10570 12:30:23.142920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10571 12:30:23.143366 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10572 12:30:23.143466 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10573 12:30:23.143552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10574 12:30:23.143639 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10575 12:30:23.143725 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10576 12:30:23.147405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10577 12:30:23.147782 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10578 12:30:23.147888 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10579 12:30:23.147983 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10580 12:30:23.148090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10581 12:30:23.148180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10582 12:30:23.148284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10583 12:30:23.148373 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10584 12:30:23.148459 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10585 12:30:23.148567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10586 12:30:23.148656 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10587 12:30:23.148759 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10588 12:30:23.148849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10589 12:30:23.148952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10590 12:30:23.149043 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10591 12:30:23.149147 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10592 12:30:23.149235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10593 12:30:23.149341 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10594 12:30:23.149432 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10595 12:30:23.149518 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10596 12:30:23.149618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10597 12:30:23.149714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10598 12:30:23.149800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10599 12:30:23.150098 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10600 12:30:23.150202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10601 12:30:23.150289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10602 12:30:23.150375 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10603 12:30:23.150474 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10604 12:30:23.150560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10605 12:30:23.150660 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10606 12:30:23.150745 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10607 12:30:23.150845 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10608 12:30:23.150954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10609 12:30:23.155530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10610 12:30:23.155799 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10611 12:30:23.155926 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10612 12:30:23.156274 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10613 12:30:23.156433 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10614 12:30:23.156584 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10615 12:30:23.156739 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10616 12:30:23.156906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10617 12:30:23.157058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10618 12:30:23.157247 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10619 12:30:23.157404 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10620 12:30:23.157556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10621 12:30:23.157728 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10622 12:30:23.157882 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10623 12:30:23.158054 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10624 12:30:23.158204 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10625 12:30:23.158479 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10626 12:30:23.158730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10627 12:30:23.158973 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10628 12:30:23.159079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10629 12:30:23.159224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10630 12:30:23.159409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10631 12:30:23.159584 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10632 12:30:23.159685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10633 12:30:23.159825 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10634 12:30:23.159927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10635 12:30:23.160014 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10636 12:30:23.160097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10637 12:30:23.160182 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10638 12:30:23.160266 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10639 12:30:23.160352 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10640 12:30:23.160437 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10641 12:30:23.160520 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10642 12:30:23.160604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10643 12:30:23.160689 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10644 12:30:23.160772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10645 12:30:23.163349 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10646 12:30:23.163480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10647 12:30:23.163784 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10648 12:30:23.163892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10649 12:30:23.163981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10650 12:30:23.164070 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10651 12:30:23.164159 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10652 12:30:23.164272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10653 12:30:23.164371 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10654 12:30:23.164478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10655 12:30:23.164584 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10656 12:30:23.164689 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10657 12:30:23.164999 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10658 12:30:23.165111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10659 12:30:23.165478 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10660 12:30:23.165582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10661 12:30:23.165681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10662 12:30:23.165784 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10663 12:30:23.165872 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10664 12:30:23.165972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10665 12:30:23.166073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10666 12:30:23.166365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10667 12:30:23.166456 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10668 12:30:23.169820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10669 12:30:23.169972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10670 12:30:23.170069 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10671 12:30:23.170161 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10672 12:30:23.170253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10673 12:30:23.171501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10674 12:30:23.171614 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10675 12:30:23.171704 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10676 12:30:23.171991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10677 12:30:23.172093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10678 12:30:23.172194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10679 12:30:23.172281 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10680 12:30:23.172367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10681 12:30:23.172451 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10682 12:30:23.172549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10683 12:30:23.172633 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10684 12:30:23.193990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10685 12:30:23.194462 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10686 12:30:23.194558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10687 12:30:23.194651 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10688 12:30:23.194741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10689 12:30:23.194827 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10690 12:30:23.194926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10691 12:30:23.195011 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10692 12:30:23.195091 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10693 12:30:23.195173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10694 12:30:23.195256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10695 12:30:23.195355 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10696 12:30:23.195443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10697 12:30:23.195722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10698 12:30:23.195818 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10699 12:30:23.195917 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10700 12:30:23.196001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10701 12:30:23.196089 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10702 12:30:23.196177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10703 12:30:23.196282 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10704 12:30:23.196370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10705 12:30:23.196469 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10706 12:30:23.196554 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10707 12:30:23.196812 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10708 12:30:23.196895 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10709 12:30:23.197113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10710 12:30:23.197192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10711 12:30:23.197254 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10712 12:30:23.197314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10713 12:30:23.197571 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10714 12:30:23.197658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10715 12:30:23.197958 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10716 12:30:23.198044 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10717 12:30:23.198111 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10718 12:30:23.198173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10719 12:30:23.198234 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10720 12:30:23.198479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10721 12:30:23.198552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10722 12:30:23.198614 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10723 12:30:23.198688 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10724 12:30:23.198945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10725 12:30:23.199028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10726 12:30:23.199105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10727 12:30:23.203355 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10728 12:30:23.203749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10729 12:30:23.203860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10730 12:30:23.203969 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10731 12:30:23.204060 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10732 12:30:23.204150 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10733 12:30:23.204256 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10734 12:30:23.204345 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10735 12:30:23.204451 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10736 12:30:23.204555 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10737 12:30:23.204669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10738 12:30:23.204769 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10739 12:30:23.205076 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10740 12:30:23.205180 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10741 12:30:23.205298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10742 12:30:23.205432 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10743 12:30:23.205560 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10744 12:30:23.205698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10745 12:30:23.205827 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10746 12:30:23.205957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10747 12:30:23.206082 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10748 12:30:23.206398 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10749 12:30:23.206506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10750 12:30:23.206612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10751 12:30:23.206718 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10752 12:30:23.206823 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10753 12:30:23.207121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10754 12:30:23.211622 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10755 12:30:23.211797 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10756 12:30:23.211907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10757 12:30:23.211999 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10758 12:30:23.212105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10759 12:30:23.212194 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10760 12:30:23.212295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10761 12:30:23.212395 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10762 12:30:23.212695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10763 12:30:23.212797 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10764 12:30:23.212899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10765 12:30:23.213002 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10766 12:30:23.213335 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10767 12:30:23.213438 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10768 12:30:23.213536 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10769 12:30:23.213636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10770 12:30:23.213753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10771 12:30:23.213874 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10772 12:30:23.214185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10773 12:30:23.214304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10774 12:30:23.214417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10775 12:30:23.214523 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10776 12:30:23.214631 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10777 12:30:23.214927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10778 12:30:23.219380 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10779 12:30:23.219599 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10780 12:30:23.219941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10781 12:30:23.220065 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10782 12:30:23.220168 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10783 12:30:23.220288 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10784 12:30:23.220388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10785 12:30:23.220483 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10786 12:30:23.220598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10787 12:30:23.220706 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10788 12:30:23.220837 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10789 12:30:23.220954 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10790 12:30:23.221074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10791 12:30:23.221181 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10792 12:30:23.221310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10793 12:30:23.221430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10794 12:30:23.221558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10795 12:30:23.221710 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10796 12:30:23.222030 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10797 12:30:23.222150 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10798 12:30:23.222240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10799 12:30:23.222342 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10800 12:30:23.222434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10801 12:30:23.222536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10802 12:30:23.222638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10803 12:30:23.222741 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10804 12:30:23.223010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10805 12:30:23.227352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10806 12:30:23.227705 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10807 12:30:23.227810 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10808 12:30:23.227900 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10809 12:30:23.228000 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10810 12:30:23.228104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10811 12:30:23.228193 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10812 12:30:23.228295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10813 12:30:23.228382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10814 12:30:23.228488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10815 12:30:23.228772 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10816 12:30:23.228870 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10817 12:30:23.228978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10818 12:30:23.229067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10819 12:30:23.229167 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10820 12:30:23.229255 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10821 12:30:23.229535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10822 12:30:23.229639 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10823 12:30:23.229753 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10824 12:30:23.229854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10825 12:30:23.229955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10826 12:30:23.230056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10827 12:30:23.230160 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10828 12:30:23.230491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10829 12:30:23.230598 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10830 12:30:23.230703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10831 12:30:23.230805 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10832 12:30:23.230908 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10833 12:30:23.235224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10834 12:30:23.235662 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10835 12:30:23.235777 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10836 12:30:23.235893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10837 12:30:23.236022 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10838 12:30:23.236132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10839 12:30:23.236218 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10840 12:30:23.236296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10841 12:30:23.236360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10842 12:30:23.236432 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10843 12:30:23.236531 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10844 12:30:23.262722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10845 12:30:23.262974 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10846 12:30:23.263056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10847 12:30:23.263135 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10848 12:30:23.263212 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10849 12:30:23.263300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10850 12:30:23.263380 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10851 12:30:23.263464 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10852 12:30:23.263547 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10853 12:30:23.263633 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10854 12:30:23.263716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10855 12:30:23.263800 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10856 12:30:23.263879 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10857 12:30:23.263960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10858 12:30:23.264039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10859 12:30:23.264126 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10860 12:30:23.264206 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10861 12:30:23.264287 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10862 12:30:23.264615 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10863 12:30:23.264728 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10864 12:30:23.264822 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10865 12:30:23.264912 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10866 12:30:23.265001 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10867 12:30:23.265090 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10868 12:30:23.265177 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10869 12:30:23.265266 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10870 12:30:23.265355 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10871 12:30:23.265442 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10872 12:30:23.265548 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10873 12:30:23.265641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10874 12:30:23.265738 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10875 12:30:23.265849 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10876 12:30:23.265940 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10877 12:30:23.266028 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10878 12:30:23.266117 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10879 12:30:23.266203 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10880 12:30:23.266499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10881 12:30:23.266605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10882 12:30:23.266700 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10883 12:30:23.266788 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10884 12:30:23.266900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10885 12:30:23.266990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10886 12:30:23.267076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10887 12:30:23.267181 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10888 12:30:23.271718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10889 12:30:23.271876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10890 12:30:23.271971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10891 12:30:23.272264 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10892 12:30:23.272373 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10893 12:30:23.272465 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10894 12:30:23.272576 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10895 12:30:23.272665 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10896 12:30:23.272754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10897 12:30:23.272860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10898 12:30:23.272967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10899 12:30:23.273074 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10900 12:30:23.273360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10901 12:30:23.273541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10902 12:30:23.273692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10903 12:30:23.273810 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10904 12:30:23.274127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10905 12:30:23.274229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10906 12:30:23.274348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10907 12:30:23.274615 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10908 12:30:23.274884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10909 12:30:23.274995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10910 12:30:23.279256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10911 12:30:23.279517 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10912 12:30:23.279628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10913 12:30:23.279741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10914 12:30:23.279852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10915 12:30:23.280164 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10916 12:30:23.280269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10917 12:30:23.280381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10918 12:30:23.280708 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10919 12:30:23.280912 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10920 12:30:23.281126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10921 12:30:23.281297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10922 12:30:23.281489 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10923 12:30:23.281637 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10924 12:30:23.281804 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10925 12:30:23.281977 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10926 12:30:23.282141 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10927 12:30:23.282285 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10928 12:30:23.282474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10929 12:30:23.282609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10930 12:30:23.282735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10931 12:30:23.282936 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10932 12:30:23.283107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10933 12:30:23.287263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10934 12:30:23.287590 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10935 12:30:23.287685 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10936 12:30:23.287815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10937 12:30:23.287945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10938 12:30:23.288241 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10939 12:30:23.288353 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10940 12:30:23.288476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10941 12:30:23.288599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10942 12:30:23.288710 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10943 12:30:23.288986 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10944 12:30:23.289288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10945 12:30:23.289380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10946 12:30:23.289525 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10947 12:30:23.289631 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10948 12:30:23.289798 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10949 12:30:23.290117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10950 12:30:23.290346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10951 12:30:23.290556 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10952 12:30:23.290786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10953 12:30:23.290972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10954 12:30:23.291178 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10955 12:30:23.291330 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10956 12:30:23.299219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10957 12:30:23.299702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10958 12:30:23.299866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10959 12:30:23.300005 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10960 12:30:23.300160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10961 12:30:23.300294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10962 12:30:23.300425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10963 12:30:23.300577 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10964 12:30:23.300913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10965 12:30:23.301007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10966 12:30:23.301103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10967 12:30:23.301180 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10968 12:30:23.301452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10969 12:30:23.301550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10970 12:30:23.301631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10971 12:30:23.301977 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10972 12:30:23.302171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10973 12:30:23.302371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10974 12:30:23.302560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10975 12:30:23.302740 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10976 12:30:23.302923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10977 12:30:23.303069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10978 12:30:23.307253 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10979 12:30:23.307592 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10980 12:30:23.307701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
10981 12:30:23.328591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
10982 12:30:23.329111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
10983 12:30:23.329225 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
10984 12:30:23.329319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
10985 12:30:23.329408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
10986 12:30:23.329511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
10987 12:30:23.329595 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
10988 12:30:23.329707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
10989 12:30:23.330012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
10990 12:30:23.330118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
10991 12:30:23.330224 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
10992 12:30:23.330328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
10993 12:30:23.330698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
10994 12:30:23.330935 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
10995 12:30:23.331149 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
10996 12:30:23.331289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
10997 12:30:23.335320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
10998 12:30:23.335805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
10999 12:30:23.336069 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11000 12:30:23.336311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11001 12:30:23.336499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11002 12:30:23.336704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11003 12:30:23.336894 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11004 12:30:23.337094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11005 12:30:23.337260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11006 12:30:23.337458 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11007 12:30:23.337613 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11008 12:30:23.337827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11009 12:30:23.338057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11010 12:30:23.338226 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11011 12:30:23.338391 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11012 12:30:23.338565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11013 12:30:23.339351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11014 12:30:23.339597 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11015 12:30:23.339763 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11016 12:30:23.339952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11017 12:30:23.340127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11018 12:30:23.340274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11019 12:30:23.340417 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11020 12:30:23.343303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11021 12:30:23.343805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11022 12:30:23.343986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11023 12:30:23.344212 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11024 12:30:23.344511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11025 12:30:23.344700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11026 12:30:23.344895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11027 12:30:23.345059 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11028 12:30:23.345285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11029 12:30:23.345553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11030 12:30:23.345811 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11031 12:30:23.346534 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11032 12:30:23.346927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11033 12:30:23.347184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11034 12:30:23.347384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11035 12:30:23.347590 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11036 12:30:23.347747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11037 12:30:23.347953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11038 12:30:23.348261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11039 12:30:23.348454 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11040 12:30:23.348600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11041 12:30:23.348876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11042 12:30:23.349100 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11043 12:30:23.351372 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11044 12:30:23.351581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11045 12:30:23.352022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11046 12:30:23.352224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11047 12:30:23.352407 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11048 12:30:23.352570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11049 12:30:23.352773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11050 12:30:23.352943 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11051 12:30:23.353102 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11052 12:30:23.353277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11053 12:30:23.353529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11054 12:30:23.353747 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11055 12:30:23.353955 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11056 12:30:23.354116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11057 12:30:23.354276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11058 12:30:23.354480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11059 12:30:23.354657 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11060 12:30:23.354813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11061 12:30:23.355004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11062 12:30:23.355172 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11063 12:30:23.355308 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11064 12:30:23.355453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11065 12:30:23.355576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11066 12:30:23.355693 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11067 12:30:23.359313 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11068 12:30:23.359759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11069 12:30:23.359973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11070 12:30:23.360194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11071 12:30:23.360381 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11072 12:30:23.360571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11073 12:30:23.360735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11074 12:30:23.360921 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11075 12:30:23.361104 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11076 12:30:23.361296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11077 12:30:23.361448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11078 12:30:23.361592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11079 12:30:23.361815 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11080 12:30:23.361977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11081 12:30:23.362136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11082 12:30:23.362290 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11083 12:30:23.362447 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11084 12:30:23.362641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11085 12:30:23.362811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11086 12:30:23.362990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11087 12:30:23.363158 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11088 12:30:23.363309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11089 12:30:23.363506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11090 12:30:23.363664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11091 12:30:23.363828 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11092 12:30:23.363985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11093 12:30:23.364136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11094 12:30:23.364284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11095 12:30:23.364451 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11096 12:30:23.364604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11097 12:30:23.364760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11098 12:30:23.364904 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11099 12:30:23.365079 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11100 12:30:23.365518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11101 12:30:23.365703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11102 12:30:23.365864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11103 12:30:23.365988 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11104 12:30:23.366105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11105 12:30:23.366223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11106 12:30:23.366341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11107 12:30:23.371470 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11108 12:30:23.371734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11109 12:30:23.372239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11110 12:30:23.372458 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11111 12:30:23.372685 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11112 12:30:23.372806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11113 12:30:23.372899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11114 12:30:23.373002 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11115 12:30:23.373097 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11116 12:30:23.373233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11117 12:30:23.396178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11118 12:30:23.396705 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11119 12:30:23.396822 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11120 12:30:23.396914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11121 12:30:23.397021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11122 12:30:23.397110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11123 12:30:23.397197 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11124 12:30:23.397302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11125 12:30:23.397408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11126 12:30:23.397696 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11127 12:30:23.397807 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11128 12:30:23.397915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11129 12:30:23.398023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11130 12:30:23.398311 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11131 12:30:23.398427 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11132 12:30:23.398730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11133 12:30:23.398838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11134 12:30:23.398936 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11135 12:30:23.399037 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11136 12:30:23.403504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11137 12:30:23.403660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11138 12:30:23.403828 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11139 12:30:23.403960 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11140 12:30:23.404076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11141 12:30:23.404577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11142 12:30:23.404686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11143 12:30:23.404784 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11144 12:30:23.404888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11145 12:30:23.405071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11146 12:30:23.405196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11147 12:30:23.405303 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11148 12:30:23.405564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11149 12:30:23.405880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11150 12:30:23.405967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11151 12:30:23.406062 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11152 12:30:23.406154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11153 12:30:23.406450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11154 12:30:23.406564 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11155 12:30:23.406894 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11156 12:30:23.407058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11157 12:30:23.411327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11158 12:30:23.411623 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11159 12:30:23.411724 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11160 12:30:23.411818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11161 12:30:23.411911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11162 12:30:23.412201 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11163 12:30:23.412320 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11164 12:30:23.412441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11165 12:30:23.412556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11166 12:30:23.412837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11167 12:30:23.412954 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11168 12:30:23.413229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11169 12:30:23.413340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11170 12:30:23.413429 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11171 12:30:23.413703 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11172 12:30:23.413833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11173 12:30:23.414142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11174 12:30:23.414250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11175 12:30:23.414577 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11176 12:30:23.414691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11177 12:30:23.414789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11178 12:30:23.414883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11179 12:30:23.419215 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11180 12:30:23.419569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11181 12:30:23.419775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11182 12:30:23.419974 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11183 12:30:23.420168 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11184 12:30:23.420334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11185 12:30:23.420532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11186 12:30:23.420702 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11187 12:30:23.420900 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11188 12:30:23.421052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11189 12:30:23.421248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11190 12:30:23.421411 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11191 12:30:23.421608 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11192 12:30:23.421795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11193 12:30:23.421993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11194 12:30:23.422158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11195 12:30:23.422352 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11196 12:30:23.422519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11197 12:30:23.422700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11198 12:30:23.422890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11199 12:30:23.423094 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11200 12:30:23.423258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11201 12:30:23.427237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11202 12:30:23.427566 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11203 12:30:23.427712 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11204 12:30:23.427918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11205 12:30:23.428071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11206 12:30:23.428165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11207 12:30:23.428267 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11208 12:30:23.428367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11209 12:30:23.428776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11210 12:30:23.428982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11211 12:30:23.429183 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11212 12:30:23.429358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11213 12:30:23.429578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11214 12:30:23.429782 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11215 12:30:23.429957 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11216 12:30:23.430161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11217 12:30:23.430323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11218 12:30:23.430490 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11219 12:30:23.430683 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11220 12:30:23.430852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11221 12:30:23.431011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11222 12:30:23.431158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11223 12:30:23.431280 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11224 12:30:23.435424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11225 12:30:23.435770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11226 12:30:23.435949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11227 12:30:23.436056 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11228 12:30:23.436163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11229 12:30:23.436268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11230 12:30:23.436371 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11231 12:30:23.436726 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11232 12:30:23.436826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11233 12:30:23.437127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11234 12:30:23.437223 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11235 12:30:23.437344 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11236 12:30:23.437455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11237 12:30:23.437738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11238 12:30:23.437837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11239 12:30:23.437956 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11240 12:30:23.438252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11241 12:30:23.438361 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11242 12:30:23.438466 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11243 12:30:23.438570 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11244 12:30:23.438872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11245 12:30:23.438992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11246 12:30:23.443247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11247 12:30:23.443618 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11248 12:30:23.443803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11249 12:30:23.444007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11250 12:30:23.444148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11251 12:30:23.466084 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11252 12:30:23.466383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11253 12:30:23.466789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11254 12:30:23.466908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11255 12:30:23.467000 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11256 12:30:23.467074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11257 12:30:23.467202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11258 12:30:23.467325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11259 12:30:23.467627 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11260 12:30:23.467742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11261 12:30:23.468083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11262 12:30:23.468184 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11263 12:30:23.468265 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11264 12:30:23.468358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11265 12:30:23.468635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11266 12:30:23.468733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11267 12:30:23.468833 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11268 12:30:23.469104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11269 12:30:23.469226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11270 12:30:23.469333 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11271 12:30:23.469418 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11272 12:30:23.469510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11273 12:30:23.469605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11274 12:30:23.469959 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11275 12:30:23.470460 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11276 12:30:23.470667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11277 12:30:23.470939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11278 12:30:23.471137 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11279 12:30:23.471268 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11280 12:30:23.471389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11281 12:30:23.475304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11282 12:30:23.475667 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11283 12:30:23.475793 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11284 12:30:23.475947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11285 12:30:23.476158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11286 12:30:23.476327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11287 12:30:23.476484 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11288 12:30:23.476670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11289 12:30:23.476818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11290 12:30:23.476992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11291 12:30:23.477140 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11292 12:30:23.477329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11293 12:30:23.477491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11294 12:30:23.477749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11295 12:30:23.477959 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11296 12:30:23.478151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11297 12:30:23.478339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11298 12:30:23.478514 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11299 12:30:23.478703 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11300 12:30:23.478917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11301 12:30:23.479064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11302 12:30:23.479184 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11303 12:30:23.479300 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11304 12:30:23.483307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11305 12:30:23.483799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11306 12:30:23.483908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11307 12:30:23.484005 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11308 12:30:23.484112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11309 12:30:23.484204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11310 12:30:23.484310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11311 12:30:23.484589 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11312 12:30:23.484696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11313 12:30:23.484803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11314 12:30:23.484894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11315 12:30:23.485001 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11316 12:30:23.485306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11317 12:30:23.485415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11318 12:30:23.485761 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11319 12:30:23.485903 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11320 12:30:23.486019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11321 12:30:23.486115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11322 12:30:23.486222 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11323 12:30:23.486314 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11324 12:30:23.486634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11325 12:30:23.486742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11326 12:30:23.486855 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11327 12:30:23.486969 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11328 12:30:23.491237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11329 12:30:23.491553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11330 12:30:23.491675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11331 12:30:23.491787 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11332 12:30:23.492087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11333 12:30:23.492195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11334 12:30:23.492568 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11335 12:30:23.492673 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11336 12:30:23.492758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11337 12:30:23.493067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11338 12:30:23.493174 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11339 12:30:23.493264 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11340 12:30:23.493365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11341 12:30:23.493454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11342 12:30:23.493554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11343 12:30:23.493801 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11344 12:30:23.493920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11345 12:30:23.494221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11346 12:30:23.494327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11347 12:30:23.494429 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11348 12:30:23.494513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11349 12:30:23.494838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11350 12:30:23.494942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11351 12:30:23.499291 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11352 12:30:23.499907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11353 12:30:23.500113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11354 12:30:23.500286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11355 12:30:23.500556 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11356 12:30:23.500666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11357 12:30:23.500760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11358 12:30:23.500849 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11359 12:30:23.501085 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11360 12:30:23.501199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11361 12:30:23.501292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11362 12:30:23.501380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11363 12:30:23.501486 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11364 12:30:23.501576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11365 12:30:23.501692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11366 12:30:23.501782 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11367 12:30:23.501883 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11368 12:30:23.502189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11369 12:30:23.502297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11370 12:30:23.502400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11371 12:30:23.502491 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11372 12:30:23.502875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11373 12:30:23.502981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11374 12:30:23.503069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11375 12:30:23.503170 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11376 12:30:23.507233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11377 12:30:23.507596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11378 12:30:23.507717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11379 12:30:23.507830 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11380 12:30:23.507928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11381 12:30:23.508039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11382 12:30:23.508339 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11383 12:30:23.508446 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11384 12:30:23.508551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11385 12:30:23.533745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11386 12:30:23.534051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11387 12:30:23.534515 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11388 12:30:23.534714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11389 12:30:23.534875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11390 12:30:23.535049 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11391 12:30:23.535194 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11392 12:30:23.535391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11393 12:30:23.535548 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11394 12:30:23.535706 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11395 12:30:23.536220 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11396 12:30:23.536455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11397 12:30:23.536607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11398 12:30:23.536784 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11399 12:30:23.536948 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11400 12:30:23.537118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11401 12:30:23.537283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11402 12:30:23.537448 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11403 12:30:23.537939 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11404 12:30:23.538152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11405 12:30:23.538325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11406 12:30:23.538493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11407 12:30:23.538660 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11408 12:30:23.538807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11409 12:30:23.538963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11410 12:30:23.539141 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11411 12:30:23.539267 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11412 12:30:23.539383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11413 12:30:23.539498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11414 12:30:23.539614 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11415 12:30:23.539729 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11416 12:30:23.539851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11417 12:30:23.539967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11418 12:30:23.543336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11419 12:30:23.543822 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11420 12:30:23.544025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11421 12:30:23.544176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11422 12:30:23.544372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11423 12:30:23.544539 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11424 12:30:23.544704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11425 12:30:23.544882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11426 12:30:23.545050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11427 12:30:23.545200 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11428 12:30:23.545384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11429 12:30:23.545551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11430 12:30:23.545723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11431 12:30:23.545950 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11432 12:30:23.546117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11433 12:30:23.546264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11434 12:30:23.546453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11435 12:30:23.546623 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11436 12:30:23.546786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11437 12:30:23.546937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11438 12:30:23.547096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11439 12:30:23.547222 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11440 12:30:23.547338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11441 12:30:23.551381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11442 12:30:23.551576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11443 12:30:23.552007 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11444 12:30:23.552267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11445 12:30:23.552825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11446 12:30:23.553016 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11447 12:30:23.553191 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11448 12:30:23.553339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11449 12:30:23.553502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11450 12:30:23.553673 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11451 12:30:23.553824 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11452 12:30:23.554029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11453 12:30:23.554181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11454 12:30:23.554351 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11455 12:30:23.554499 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11456 12:30:23.554656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11457 12:30:23.554819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11458 12:30:23.555027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11459 12:30:23.555228 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11460 12:30:23.555387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11461 12:30:23.555577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11462 12:30:23.555742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11463 12:30:23.555901 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11464 12:30:23.556067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11465 12:30:23.556209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11466 12:30:23.556364 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11467 12:30:23.556486 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11468 12:30:23.556600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11469 12:30:23.556715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11470 12:30:23.559247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11471 12:30:23.559714 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11472 12:30:23.559856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11473 12:30:23.559963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11474 12:30:23.560059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11475 12:30:23.560168 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11476 12:30:23.560259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11477 12:30:23.560347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11478 12:30:23.560453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11479 12:30:23.560543 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11480 12:30:23.560629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11481 12:30:23.560715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11482 12:30:23.560819 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11483 12:30:23.560907 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11484 12:30:23.560993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11485 12:30:23.561093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11486 12:30:23.561182 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11487 12:30:23.561284 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11488 12:30:23.561711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11489 12:30:23.561820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11490 12:30:23.561912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11491 12:30:23.562001 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11492 12:30:23.562108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11493 12:30:23.562418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11494 12:30:23.562524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11495 12:30:23.562612 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11496 12:30:23.562698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11497 12:30:23.562803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11498 12:30:23.563098 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11499 12:30:23.563230 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11500 12:30:23.563323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11501 12:30:23.563411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11502 12:30:23.563499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11503 12:30:23.563588 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11504 12:30:23.567248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11505 12:30:23.567581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11506 12:30:23.567702 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11507 12:30:23.567801 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11508 12:30:23.568097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11509 12:30:23.568219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11510 12:30:23.568311 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11511 12:30:23.568415 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11512 12:30:23.568518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11513 12:30:23.568754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11514 12:30:23.568848 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11515 12:30:23.568947 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11516 12:30:23.569379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11517 12:30:23.569485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11518 12:30:23.569579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11519 12:30:23.595684 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11520 12:30:23.595942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11521 12:30:23.596167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11522 12:30:23.596495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11523 12:30:23.596605 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11524 12:30:23.596704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11525 12:30:23.596789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11526 12:30:23.596870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11527 12:30:23.596950 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11528 12:30:23.597038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11529 12:30:23.597128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11530 12:30:23.597215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11531 12:30:23.597310 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11532 12:30:23.597398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11533 12:30:23.597487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11534 12:30:23.597787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11535 12:30:23.597902 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11536 12:30:23.598028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11537 12:30:23.598130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11538 12:30:23.598238 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11539 12:30:23.598540 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11540 12:30:23.598647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11541 12:30:23.598756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11542 12:30:23.598864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11543 12:30:23.603214 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11544 12:30:23.603587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11545 12:30:23.603823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11546 12:30:23.604138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11547 12:30:23.604334 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11548 12:30:23.604472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11549 12:30:23.605850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11550 12:30:23.606068 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11551 12:30:23.606288 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11552 12:30:23.606467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11553 12:30:23.606643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11554 12:30:23.606819 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11555 12:30:23.606969 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11556 12:30:23.607098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11557 12:30:23.607214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11558 12:30:23.607326 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11559 12:30:23.607438 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11560 12:30:23.607747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11561 12:30:23.607830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11562 12:30:23.607895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11563 12:30:23.607958 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11564 12:30:23.608020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11565 12:30:23.608080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11566 12:30:23.608141 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11567 12:30:23.611245 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11568 12:30:23.611791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11569 12:30:23.612087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11570 12:30:23.612318 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11571 12:30:23.612508 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11572 12:30:23.612674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11573 12:30:23.612837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11574 12:30:23.613047 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11575 12:30:23.613223 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11576 12:30:23.613383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11577 12:30:23.613539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11578 12:30:23.613734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11579 12:30:23.613984 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11580 12:30:23.614164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11581 12:30:23.614323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11582 12:30:23.614480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11583 12:30:23.614640 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11584 12:30:23.614796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11585 12:30:23.614978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11586 12:30:23.615111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11587 12:30:23.615239 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11588 12:30:23.615362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11589 12:30:23.615485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11590 12:30:23.615607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11591 12:30:23.615730 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11592 12:30:23.619466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11593 12:30:23.619716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11594 12:30:23.619950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11595 12:30:23.620133 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11596 12:30:23.620301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11597 12:30:23.620499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11598 12:30:23.620668 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11599 12:30:23.620836 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11600 12:30:23.621010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11601 12:30:23.621188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11602 12:30:23.621378 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11603 12:30:23.621642 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11604 12:30:23.621848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11605 12:30:23.622025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11606 12:30:23.622193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11607 12:30:23.622366 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11608 12:30:23.622558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11609 12:30:23.622733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11610 12:30:23.625798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11611 12:30:23.625983 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11612 12:30:23.626189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11613 12:30:23.626355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11614 12:30:23.626513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11615 12:30:23.626669 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11616 12:30:23.626825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11617 12:30:23.626980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11618 12:30:23.627134 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11619 12:30:23.627290 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11620 12:30:23.627476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11621 12:30:23.627632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11622 12:30:23.627788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11623 12:30:23.628206 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11624 12:30:23.628405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11625 12:30:23.628572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11626 12:30:23.628730 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11627 12:30:23.628886 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11628 12:30:23.629041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11629 12:30:23.629197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11630 12:30:23.629353 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11631 12:30:23.629508 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11632 12:30:23.629675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11633 12:30:23.629870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11634 12:30:23.630032 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11635 12:30:23.630188 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11636 12:30:23.630342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11637 12:30:23.630497 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11638 12:30:23.630652 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11639 12:30:23.630805 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11640 12:30:23.630959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11641 12:30:23.631113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11642 12:30:23.631270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11643 12:30:23.631458 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11644 12:30:23.631619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11645 12:30:23.631775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11646 12:30:23.631931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11647 12:30:23.632086 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11648 12:30:23.632243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11649 12:30:23.632398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11650 12:30:23.632553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11651 12:30:23.635283 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11652 12:30:23.635676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11653 12:30:23.651274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11654 12:30:23.651903 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11655 12:30:23.652004 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11656 12:30:23.652090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11657 12:30:23.652164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11658 12:30:23.652239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11659 12:30:23.652302 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11660 12:30:23.652553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11661 12:30:23.652832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11662 12:30:23.652967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11663 12:30:23.653086 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11664 12:30:23.653216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11665 12:30:23.653288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11666 12:30:23.653594 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11667 12:30:23.653712 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11668 12:30:23.653797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11669 12:30:23.653900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11670 12:30:23.654210 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11671 12:30:23.654307 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11672 12:30:23.654408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11673 12:30:23.654685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11674 12:30:23.654808 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11675 12:30:23.654910 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11676 12:30:23.655203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11677 12:30:23.655288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11678 12:30:23.659450 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11679 12:30:23.659786 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11680 12:30:23.659885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11681 12:30:23.659988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11682 12:30:23.660274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11683 12:30:23.660374 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11684 12:30:23.660471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11685 12:30:23.660571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11686 12:30:23.660669 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11687 12:30:23.660957 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11688 12:30:23.661242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11689 12:30:23.661347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11690 12:30:23.661438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11691 12:30:23.661705 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11692 12:30:23.661811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11693 12:30:23.662149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11694 12:30:23.662361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11695 12:30:23.662561 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11696 12:30:23.662730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11697 12:30:23.662905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11698 12:30:23.663097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11699 12:30:23.663267 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11700 12:30:23.667301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11701 12:30:23.667654 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11702 12:30:23.667723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11703 12:30:23.667796 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11704 12:30:23.668047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11705 12:30:23.668127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11706 12:30:23.668375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11707 12:30:23.668442 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11708 12:30:23.668687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11709 12:30:23.668937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11710 12:30:23.669012 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11711 12:30:23.669084 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11712 12:30:23.669324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11713 12:30:23.669571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11714 12:30:23.669655 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11715 12:30:23.669908 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11716 12:30:23.669984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11717 12:30:23.670230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11718 12:30:23.670322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11719 12:30:23.670569 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11720 12:30:23.670816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11721 12:30:23.671066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11722 12:30:23.675218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11723 12:30:23.675522 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11724 12:30:23.675612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11725 12:30:23.675687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11726 12:30:23.676108 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11727 12:30:23.676179 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11728 12:30:23.676251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11729 12:30:23.676504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11730 12:30:23.676754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11731 12:30:23.676820 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11732 12:30:23.677066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11733 12:30:23.677141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11734 12:30:23.677386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11735 12:30:23.677629 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11736 12:30:23.677735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11737 12:30:23.677808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11738 12:30:23.678048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11739 12:30:23.678122 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11740 12:30:23.678403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11741 12:30:23.678509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11742 12:30:23.678883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11743 12:30:23.678996 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11744 12:30:23.679286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11745 12:30:23.679376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11746 12:30:23.683350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11747 12:30:23.683473 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11748 12:30:23.683582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11749 12:30:23.683893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11750 12:30:23.683989 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11751 12:30:23.684104 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11752 12:30:23.684416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11753 12:30:23.684520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11754 12:30:23.684636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11755 12:30:23.684742 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11756 12:30:23.684840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11757 12:30:23.685119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11758 12:30:23.685218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11759 12:30:23.685337 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11760 12:30:23.685623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11761 12:30:23.685752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11762 12:30:23.685861 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11763 12:30:23.685986 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11764 12:30:23.686091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11765 12:30:23.686437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11766 12:30:23.686687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11767 12:30:23.686871 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11768 12:30:23.687081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11769 12:30:23.687263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11770 12:30:23.691230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11771 12:30:23.691598 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11772 12:30:23.691693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11773 12:30:23.691793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11774 12:30:23.692242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11775 12:30:23.692342 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11776 12:30:23.693145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11777 12:30:23.693266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11778 12:30:23.693382 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11779 12:30:23.693473 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11780 12:30:23.693591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11781 12:30:23.693692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11782 12:30:23.693988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11783 12:30:23.695680 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11784 12:30:23.695786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11785 12:30:23.695883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11786 12:30:23.695970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11787 12:30:23.712189 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11788 12:30:23.712667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11789 12:30:23.712788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11790 12:30:23.712878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11791 12:30:23.712987 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11792 12:30:23.713077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11793 12:30:23.713182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11794 12:30:23.713290 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11795 12:30:23.713401 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11796 12:30:23.713698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11797 12:30:23.713822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11798 12:30:23.714121 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11799 12:30:23.714240 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11800 12:30:23.714495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11801 12:30:23.714630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11802 12:30:23.715189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11803 12:30:23.719341 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11804 12:30:23.719756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11805 12:30:23.719878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11806 12:30:23.719987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11807 12:30:23.720080 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11808 12:30:23.720184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11809 12:30:23.720495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11810 12:30:23.720614 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11811 12:30:23.720914 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11812 12:30:23.721024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11813 12:30:23.721318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11814 12:30:23.721411 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11815 12:30:23.721513 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11816 12:30:23.721617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11817 12:30:23.721755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11818 12:30:23.722053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11819 12:30:23.722152 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11820 12:30:23.722252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11821 12:30:23.722566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11822 12:30:23.722680 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11823 12:30:23.722786 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11824 12:30:23.722899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11825 12:30:23.727343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11826 12:30:23.727745 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11827 12:30:23.727841 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11828 12:30:23.727930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11829 12:30:23.728047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11830 12:30:23.728151 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11831 12:30:23.728253 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11832 12:30:23.728322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11833 12:30:23.728608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11834 12:30:23.728899 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11835 12:30:23.729016 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11836 12:30:23.729104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11837 12:30:23.729187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11838 12:30:23.729261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11839 12:30:23.729558 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11840 12:30:23.729689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11841 12:30:23.729769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11842 12:30:23.729845 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11843 12:30:23.730136 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11844 12:30:23.730231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11845 12:30:23.730346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11846 12:30:23.730640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11847 12:30:23.730736 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11848 12:30:23.730841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11849 12:30:23.730945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11850 12:30:23.735412 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11851 12:30:23.735844 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11852 12:30:23.735963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11853 12:30:23.736439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11854 12:30:23.736554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11855 12:30:23.736650 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11856 12:30:23.736738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11857 12:30:23.737076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11858 12:30:23.737183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11859 12:30:23.737299 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11860 12:30:23.737389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11861 12:30:23.737498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11862 12:30:23.737584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11863 12:30:23.737697 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11864 12:30:23.737784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11865 12:30:23.741793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11866 12:30:23.741942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11867 12:30:23.742012 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11868 12:30:23.742075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11869 12:30:23.742181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11870 12:30:23.742263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11871 12:30:23.742326 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11872 12:30:23.742409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11873 12:30:23.742479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11874 12:30:23.743224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11875 12:30:23.743529 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11876 12:30:23.743623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11877 12:30:23.743742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11878 12:30:23.744037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11879 12:30:23.744142 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11880 12:30:23.744472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11881 12:30:23.744782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11882 12:30:23.744883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11883 12:30:23.744984 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11884 12:30:23.745092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11885 12:30:23.745215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11886 12:30:23.745332 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11887 12:30:23.745635 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11888 12:30:23.745781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11889 12:30:23.745951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11890 12:30:23.746083 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11891 12:30:23.746398 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11892 12:30:23.746509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11893 12:30:23.746632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11894 12:30:23.746753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11895 12:30:23.746856 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11896 12:30:23.746975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11897 12:30:23.751289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11898 12:30:23.751662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11899 12:30:23.751767 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11900 12:30:23.751886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11901 12:30:23.751966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11902 12:30:23.752084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11903 12:30:23.752205 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11904 12:30:23.752306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11905 12:30:23.752623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11906 12:30:23.752741 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11907 12:30:23.752849 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11908 12:30:23.752960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11909 12:30:23.753067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11910 12:30:23.753376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11911 12:30:23.753488 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11912 12:30:23.753589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11913 12:30:23.753735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11914 12:30:23.753862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11915 12:30:23.753984 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11916 12:30:23.754352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11917 12:30:23.754455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11918 12:30:23.754562 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11919 12:30:23.754663 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11920 12:30:23.754732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11921 12:30:23.771387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11922 12:30:23.771635 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11923 12:30:23.771905 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11924 12:30:23.772034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11925 12:30:23.772198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11926 12:30:23.772284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11927 12:30:23.772363 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11928 12:30:23.772457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11929 12:30:23.772743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11930 12:30:23.772846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11931 12:30:23.772945 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11932 12:30:23.773035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11933 12:30:23.773319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11934 12:30:23.773423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11935 12:30:23.773695 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11936 12:30:23.773807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11937 12:30:23.773897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11938 12:30:23.774171 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11939 12:30:23.774286 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11940 12:30:23.774409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11941 12:30:23.774559 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11942 12:30:23.774892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11943 12:30:23.775012 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11944 12:30:23.779317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11945 12:30:23.779689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11946 12:30:23.779784 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11947 12:30:23.779910 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11948 12:30:23.779986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11949 12:30:23.780261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11950 12:30:23.780385 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11951 12:30:23.780694 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11952 12:30:23.780811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11953 12:30:23.780916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11954 12:30:23.781036 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11955 12:30:23.781138 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11956 12:30:23.781406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11957 12:30:23.781503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11958 12:30:23.781633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11959 12:30:23.781747 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11960 12:30:23.781867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11961 12:30:23.781990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11962 12:30:23.782110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11963 12:30:23.782231 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11964 12:30:23.782442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11965 12:30:23.782781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11966 12:30:23.782909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11967 12:30:23.783008 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11968 12:30:23.787372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11969 12:30:23.787748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11970 12:30:23.787873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11971 12:30:23.788194 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11972 12:30:23.788290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11973 12:30:23.788410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11974 12:30:23.788533 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11975 12:30:23.788654 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11976 12:30:23.788775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11977 12:30:23.789102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11978 12:30:23.789230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11979 12:30:23.789548 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11980 12:30:23.789678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
11981 12:30:23.789808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
11982 12:30:23.789930 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
11983 12:30:23.790036 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
11984 12:30:23.790155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
11985 12:30:23.790276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
11986 12:30:23.790605 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
11987 12:30:23.790720 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
11988 12:30:23.790893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
11989 12:30:23.791015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
11990 12:30:23.795247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
11991 12:30:23.795653 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
11992 12:30:23.795762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
11993 12:30:23.795890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
11994 12:30:23.796013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
11995 12:30:23.796328 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
11996 12:30:23.796420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
11997 12:30:23.796544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
11998 12:30:23.796665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
11999 12:30:23.796971 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12000 12:30:23.797092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12001 12:30:23.797197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12002 12:30:23.797511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12003 12:30:23.797639 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12004 12:30:23.797774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12005 12:30:23.797871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12006 12:30:23.798185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12007 12:30:23.798315 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12008 12:30:23.798435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12009 12:30:23.798745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12010 12:30:23.798862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12011 12:30:23.798982 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12012 12:30:23.803326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12013 12:30:23.803737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12014 12:30:23.803859 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12015 12:30:23.803966 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12016 12:30:23.804089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12017 12:30:23.804200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12018 12:30:23.804330 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12019 12:30:23.804466 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12020 12:30:23.804595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12021 12:30:23.804924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12022 12:30:23.805053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12023 12:30:23.805169 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12024 12:30:23.805305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12025 12:30:23.805511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12026 12:30:23.805721 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12027 12:30:23.805857 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12028 12:30:23.805968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12029 12:30:23.806078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12030 12:30:23.809849 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12031 12:30:23.810046 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12032 12:30:23.810155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12033 12:30:23.810257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12034 12:30:23.810358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12035 12:30:23.810459 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12036 12:30:23.811152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12037 12:30:23.811493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12038 12:30:23.811610 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12039 12:30:23.811730 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12040 12:30:23.811832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12041 12:30:23.811948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12042 12:30:23.812065 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12043 12:30:23.812352 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12044 12:30:23.812466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12045 12:30:23.812584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12046 12:30:23.812686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12047 12:30:23.812801 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12048 12:30:23.812914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12049 12:30:23.812992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12050 12:30:23.813103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12051 12:30:23.813239 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12052 12:30:23.813359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12053 12:30:23.813482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12054 12:30:23.813585 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12055 12:30:23.829391 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12056 12:30:23.829615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12057 12:30:23.829930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12058 12:30:23.830037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12059 12:30:23.830128 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12060 12:30:23.830240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12061 12:30:23.830317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12062 12:30:23.830599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12063 12:30:23.830685 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12064 12:30:23.830795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12065 12:30:23.831097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12066 12:30:23.831373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12067 12:30:23.831467 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12068 12:30:23.832005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12069 12:30:23.832080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12070 12:30:23.832147 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12071 12:30:23.832389 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12072 12:30:23.832471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12073 12:30:23.832720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12074 12:30:23.832792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12075 12:30:23.832870 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12076 12:30:23.833126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12077 12:30:23.833198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12078 12:30:23.833516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12079 12:30:23.833605 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12080 12:30:23.833890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12081 12:30:23.834177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12082 12:30:23.834272 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12083 12:30:23.834377 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12084 12:30:23.834472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12085 12:30:23.834757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12086 12:30:23.834865 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12087 12:30:23.834943 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12088 12:30:23.839222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12089 12:30:23.839589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12090 12:30:23.839862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12091 12:30:23.839946 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12092 12:30:23.840037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12093 12:30:23.840292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12094 12:30:23.840548 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12095 12:30:23.840631 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12096 12:30:23.840878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12097 12:30:23.841166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12098 12:30:23.841284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12099 12:30:23.841356 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12100 12:30:23.841614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12101 12:30:23.841923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12102 12:30:23.842018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12103 12:30:23.842085 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12104 12:30:23.842171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12105 12:30:23.842262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12106 12:30:23.842514 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12107 12:30:23.842759 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12108 12:30:23.842827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12109 12:30:23.847184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12110 12:30:23.847481 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12111 12:30:23.847584 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12112 12:30:23.847710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12113 12:30:23.847821 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12114 12:30:23.847945 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12115 12:30:23.848267 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12116 12:30:23.848375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12117 12:30:23.848474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12118 12:30:23.848581 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12119 12:30:23.848668 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12120 12:30:23.848787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12121 12:30:23.848897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12122 12:30:23.849162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12123 12:30:23.849277 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12124 12:30:23.849388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12125 12:30:23.849709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12126 12:30:23.849871 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12127 12:30:23.849979 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12128 12:30:23.850114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12129 12:30:23.850236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12130 12:30:23.850333 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12131 12:30:23.850437 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12132 12:30:23.850569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12133 12:30:23.850681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12134 12:30:23.850802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12135 12:30:23.850921 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12136 12:30:23.855387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12137 12:30:23.855559 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12138 12:30:23.855688 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12139 12:30:23.855821 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12140 12:30:23.856186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12141 12:30:23.856280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12142 12:30:23.856404 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12143 12:30:23.856512 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12144 12:30:23.856678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12145 12:30:23.856773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12146 12:30:23.856889 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12147 12:30:23.856998 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12148 12:30:23.857099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12149 12:30:23.857201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12150 12:30:23.857306 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12151 12:30:23.857414 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12152 12:30:23.857512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12153 12:30:23.857800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12154 12:30:23.858126 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12155 12:30:23.858223 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12156 12:30:23.858511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12157 12:30:23.858617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12158 12:30:23.858748 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12159 12:30:23.858867 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12160 12:30:23.858989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12161 12:30:23.863197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12162 12:30:23.863525 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12163 12:30:23.863628 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12164 12:30:23.863752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12165 12:30:23.863876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12166 12:30:23.863997 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12167 12:30:23.864121 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12168 12:30:23.864248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12169 12:30:23.864363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12170 12:30:23.864682 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12171 12:30:23.864784 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12172 12:30:23.864898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12173 12:30:23.865011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12174 12:30:23.865310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12175 12:30:23.865425 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12176 12:30:23.865543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12177 12:30:23.865663 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12178 12:30:23.865978 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12179 12:30:23.866083 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12180 12:30:23.866191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12181 12:30:23.866502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12182 12:30:23.866608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12183 12:30:23.866905 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12184 12:30:23.867010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12185 12:30:23.871189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12186 12:30:23.871544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12187 12:30:23.871629 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12188 12:30:23.871706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12189 12:30:23.886745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12190 12:30:23.887236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12191 12:30:23.887345 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12192 12:30:23.887436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12193 12:30:23.887540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12194 12:30:23.887627 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12195 12:30:23.887716 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12196 12:30:23.887817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12197 12:30:23.888412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12198 12:30:23.888522 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12199 12:30:23.888611 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12200 12:30:23.888700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12201 12:30:23.888786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12202 12:30:23.888894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12203 12:30:23.888985 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12204 12:30:23.889073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12205 12:30:23.889378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12206 12:30:23.889535 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12207 12:30:23.889693 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12208 12:30:23.889841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12209 12:30:23.889995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12210 12:30:23.890148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12211 12:30:23.890257 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12212 12:30:23.890364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12213 12:30:23.890453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12214 12:30:23.890540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12215 12:30:23.890625 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12216 12:30:23.890716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12217 12:30:23.890818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12218 12:30:23.890908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12219 12:30:23.890992 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12220 12:30:23.891073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12221 12:30:23.891154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12222 12:30:23.891252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12223 12:30:23.891336 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12224 12:30:23.895206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12225 12:30:23.895683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12226 12:30:23.895790 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12227 12:30:23.895904 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12228 12:30:23.895998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12229 12:30:23.896106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12230 12:30:23.896215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12231 12:30:23.896325 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12232 12:30:23.896433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12233 12:30:23.896540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12234 12:30:23.896849 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12235 12:30:23.896951 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12236 12:30:23.897036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12237 12:30:23.897135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12238 12:30:23.897219 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12239 12:30:23.897310 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12240 12:30:23.897389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12241 12:30:23.897480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12242 12:30:23.897570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12243 12:30:23.897940 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12244 12:30:23.898032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12245 12:30:23.898327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12246 12:30:23.898438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12247 12:30:23.898534 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12248 12:30:23.898643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12249 12:30:23.898742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12250 12:30:23.898850 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12251 12:30:23.898941 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12252 12:30:23.903235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12253 12:30:23.903696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12254 12:30:23.903835 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12255 12:30:23.903925 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12256 12:30:23.904039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12257 12:30:23.904145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12258 12:30:23.904262 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12259 12:30:23.904348 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12260 12:30:23.904483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12261 12:30:23.905387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12262 12:30:23.905498 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12263 12:30:23.905589 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12264 12:30:23.905682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12265 12:30:23.905767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12266 12:30:23.905858 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12267 12:30:23.906142 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12268 12:30:23.906248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12269 12:30:23.906336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12270 12:30:23.906422 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12271 12:30:23.906510 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12272 12:30:23.906616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12273 12:30:23.906710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12274 12:30:23.906817 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12275 12:30:23.906908 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12276 12:30:23.911160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12277 12:30:23.911570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12278 12:30:23.911666 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12279 12:30:23.911770 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12280 12:30:23.911889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12281 12:30:23.912170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12282 12:30:23.912276 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12283 12:30:23.912563 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12284 12:30:23.912669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12285 12:30:23.912948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12286 12:30:23.913037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12287 12:30:23.913305 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12288 12:30:23.913573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12289 12:30:23.913669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12290 12:30:23.913981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12291 12:30:23.914068 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12292 12:30:23.914189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12293 12:30:23.915674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12294 12:30:23.915775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12295 12:30:23.915887 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12296 12:30:23.915963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12297 12:30:23.916025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12298 12:30:23.916094 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12299 12:30:23.919186 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12300 12:30:23.919532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12301 12:30:23.919646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12302 12:30:23.919782 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12303 12:30:23.919990 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12304 12:30:23.920179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12305 12:30:23.920486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12306 12:30:23.920606 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12307 12:30:23.920694 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12308 12:30:23.920990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12309 12:30:23.921109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12310 12:30:23.921210 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12311 12:30:23.921407 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12312 12:30:23.921726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12313 12:30:23.921886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12314 12:30:23.921998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12315 12:30:23.922288 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12316 12:30:23.922393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12317 12:30:23.922495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12318 12:30:23.922593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12319 12:30:23.922693 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12320 12:30:23.923003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12321 12:30:23.927204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12322 12:30:23.927579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12323 12:30:23.939990 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12324 12:30:23.940438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12325 12:30:23.940546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12326 12:30:23.940656 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12327 12:30:23.940747 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12328 12:30:23.940854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12329 12:30:23.940958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12330 12:30:23.941070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12331 12:30:23.941374 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12332 12:30:23.941495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12333 12:30:23.941794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12334 12:30:23.941935 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12335 12:30:23.942048 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12336 12:30:23.942154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12337 12:30:23.942456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12338 12:30:23.942576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12339 12:30:23.942682 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12340 12:30:23.942993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12341 12:30:23.947432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12342 12:30:23.947636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12343 12:30:23.947942 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12344 12:30:23.948052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12345 12:30:23.948141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12346 12:30:23.948246 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12347 12:30:23.948337 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12348 12:30:23.948442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12349 12:30:23.948743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12350 12:30:23.948869 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12351 12:30:23.949058 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12352 12:30:23.949182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12353 12:30:23.949486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12354 12:30:23.949607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12355 12:30:23.949729 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12356 12:30:23.949834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12357 12:30:23.950137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12358 12:30:23.950261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12359 12:30:23.950366 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12360 12:30:23.950668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12361 12:30:23.950793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12362 12:30:23.951109 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12363 12:30:23.951216 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12364 12:30:23.955250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12365 12:30:23.955612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12366 12:30:23.955720 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12367 12:30:23.955823 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12368 12:30:23.955929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12369 12:30:23.956225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12370 12:30:23.956348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12371 12:30:23.956658 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12372 12:30:23.956764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12373 12:30:23.956869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12374 12:30:23.957172 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12375 12:30:23.957281 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12376 12:30:23.957388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12377 12:30:23.957722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12378 12:30:23.957846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12379 12:30:23.957952 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12380 12:30:23.958063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12381 12:30:23.958366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12382 12:30:23.958489 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12383 12:30:23.958789 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12384 12:30:23.958913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12385 12:30:23.959016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12386 12:30:23.959317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12387 12:30:23.963290 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12388 12:30:23.963753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12389 12:30:23.963870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12390 12:30:23.963981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12391 12:30:23.964070 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12392 12:30:23.964170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12393 12:30:23.964475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12394 12:30:23.964601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12395 12:30:23.964707 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12396 12:30:23.964812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12397 12:30:23.965121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12398 12:30:23.965245 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12399 12:30:23.965516 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12400 12:30:23.965626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12401 12:30:23.965743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12402 12:30:23.966053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12403 12:30:23.966162 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12404 12:30:23.966262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12405 12:30:23.966556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12406 12:30:23.966680 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12407 12:30:23.966785 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12408 12:30:23.967090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12409 12:30:23.971226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12410 12:30:23.971613 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12411 12:30:23.971721 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12412 12:30:23.971826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12413 12:30:23.971936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12414 12:30:23.972040 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12415 12:30:23.972344 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12416 12:30:23.972450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12417 12:30:23.972555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12418 12:30:23.972840 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12419 12:30:23.972961 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12420 12:30:23.973075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12421 12:30:23.973370 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12422 12:30:23.973479 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12423 12:30:23.973581 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12424 12:30:23.973794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12425 12:30:23.973919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12426 12:30:23.974228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12427 12:30:23.974349 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12428 12:30:23.974463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12429 12:30:23.974761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12430 12:30:23.975085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12431 12:30:23.975192 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12432 12:30:23.979264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12433 12:30:23.979609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12434 12:30:23.979716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12435 12:30:23.979819 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12436 12:30:23.979926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12437 12:30:23.980028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12438 12:30:23.980323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12439 12:30:23.980444 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12440 12:30:23.980547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12441 12:30:23.980844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12442 12:30:23.980965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12443 12:30:23.981076 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12444 12:30:23.981379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12445 12:30:23.981499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12446 12:30:23.981801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12447 12:30:23.981923 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12448 12:30:23.982098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12449 12:30:23.982220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12450 12:30:23.982518 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12451 12:30:23.982652 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12452 12:30:23.982764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12453 12:30:23.982989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12454 12:30:23.987313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12455 12:30:23.987607 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12456 12:30:23.987712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12457 12:30:24.005355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12458 12:30:24.005600 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12459 12:30:24.005921 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12460 12:30:24.006037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12461 12:30:24.006127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12462 12:30:24.006230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12463 12:30:24.006321 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12464 12:30:24.006427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12465 12:30:24.006516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12466 12:30:24.006820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12467 12:30:24.006945 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12468 12:30:24.007048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12469 12:30:24.007345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12470 12:30:24.007692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12471 12:30:24.007820 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12472 12:30:24.008085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12473 12:30:24.008193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12474 12:30:24.008296 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12475 12:30:24.008483 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12476 12:30:24.008605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12477 12:30:24.008912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12478 12:30:24.009017 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12479 12:30:24.009319 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12480 12:30:24.009426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12481 12:30:24.009532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12482 12:30:24.009619 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12483 12:30:24.009929 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12484 12:30:24.010039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12485 12:30:24.010343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12486 12:30:24.010465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12487 12:30:24.010758 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12488 12:30:24.010948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12489 12:30:24.011144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12490 12:30:24.015317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12491 12:30:24.015682 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12492 12:30:24.015791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12493 12:30:24.016053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12494 12:30:24.016161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12495 12:30:24.016267 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12496 12:30:24.016373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12497 12:30:24.016477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12498 12:30:24.016781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12499 12:30:24.016902 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12500 12:30:24.017012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12501 12:30:24.017376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12502 12:30:24.017520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12503 12:30:24.017781 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12504 12:30:24.017925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12505 12:30:24.018182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12506 12:30:24.018323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12507 12:30:24.018553 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12508 12:30:24.018719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12509 12:30:24.019006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12510 12:30:24.019189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12511 12:30:24.019440 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12512 12:30:24.019607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12513 12:30:24.027307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12514 12:30:24.027750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12515 12:30:24.027898 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12516 12:30:24.028084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12517 12:30:24.028213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12518 12:30:24.028306 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12519 12:30:24.028396 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12520 12:30:24.028498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12521 12:30:24.028597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12522 12:30:24.028899 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12523 12:30:24.029024 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12524 12:30:24.029327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12525 12:30:24.029433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12526 12:30:24.029535 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12527 12:30:24.029833 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12528 12:30:24.029939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12529 12:30:24.030039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12530 12:30:24.030341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12531 12:30:24.030447 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12532 12:30:24.030553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12533 12:30:24.030955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12534 12:30:24.031063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12535 12:30:24.035339 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12536 12:30:24.035776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12537 12:30:24.035887 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12538 12:30:24.036013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12539 12:30:24.036120 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12540 12:30:24.036229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12541 12:30:24.036520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12542 12:30:24.036626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12543 12:30:24.036732 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12544 12:30:24.036836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12545 12:30:24.037140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12546 12:30:24.037246 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12547 12:30:24.037351 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12548 12:30:24.037456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12549 12:30:24.037769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12550 12:30:24.037890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12551 12:30:24.037998 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12552 12:30:24.038297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12553 12:30:24.038418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12554 12:30:24.038523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12555 12:30:24.038633 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12556 12:30:24.038934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12557 12:30:24.043300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12558 12:30:24.043684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12559 12:30:24.043792 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12560 12:30:24.043903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12561 12:30:24.044002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12562 12:30:24.044296 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12563 12:30:24.044403 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12564 12:30:24.044508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12565 12:30:24.044810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12566 12:30:24.044932 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12567 12:30:24.045043 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12568 12:30:24.045336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12569 12:30:24.045423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12570 12:30:24.045549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12571 12:30:24.045858 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12572 12:30:24.045965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12573 12:30:24.046076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12574 12:30:24.046375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12575 12:30:24.046484 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12576 12:30:24.046586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12577 12:30:24.046689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12578 12:30:24.046989 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12579 12:30:24.051347 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12580 12:30:24.051780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12581 12:30:24.051895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12582 12:30:24.051999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12583 12:30:24.052084 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12584 12:30:24.052183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12585 12:30:24.052284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12586 12:30:24.052576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12587 12:30:24.052683 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12588 12:30:24.052786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12589 12:30:24.053087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12590 12:30:24.053208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12591 12:30:24.070893 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12592 12:30:24.071330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12593 12:30:24.071434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12594 12:30:24.071544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12595 12:30:24.071658 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12596 12:30:24.071956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12597 12:30:24.072070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12598 12:30:24.072206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12599 12:30:24.072497 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12600 12:30:24.072598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12601 12:30:24.072877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12602 12:30:24.072977 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12603 12:30:24.073077 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12604 12:30:24.073369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12605 12:30:24.073751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12606 12:30:24.073860 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12607 12:30:24.073952 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12608 12:30:24.074232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12609 12:30:24.074327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12610 12:30:24.074433 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12611 12:30:24.074534 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12612 12:30:24.074638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12613 12:30:24.074932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12614 12:30:24.079236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12615 12:30:24.079648 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12616 12:30:24.079766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12617 12:30:24.080066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12618 12:30:24.080371 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12619 12:30:24.080477 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12620 12:30:24.080581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12621 12:30:24.080864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12622 12:30:24.080973 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12623 12:30:24.081264 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12624 12:30:24.081764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12625 12:30:24.082086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12626 12:30:24.082206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12627 12:30:24.082500 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12628 12:30:24.082755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12629 12:30:24.083026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12630 12:30:24.087406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12631 12:30:24.087827 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12632 12:30:24.088560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12633 12:30:24.088663 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12634 12:30:24.088746 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12635 12:30:24.088835 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12636 12:30:24.088911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12637 12:30:24.088997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12638 12:30:24.089279 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12639 12:30:24.089381 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12640 12:30:24.089467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12641 12:30:24.089543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12642 12:30:24.089659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12643 12:30:24.089743 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12644 12:30:24.089847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12645 12:30:24.089937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12646 12:30:24.090230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12647 12:30:24.090333 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12648 12:30:24.090434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12649 12:30:24.090723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12650 12:30:24.090808 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12651 12:30:24.095245 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12652 12:30:24.095594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12653 12:30:24.095713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12654 12:30:24.095856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12655 12:30:24.095990 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12656 12:30:24.096093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12657 12:30:24.096178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12658 12:30:24.096456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12659 12:30:24.096709 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12660 12:30:24.096775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12661 12:30:24.096836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12662 12:30:24.096907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12663 12:30:24.096969 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12664 12:30:24.097216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12665 12:30:24.097293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12666 12:30:24.097542 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12667 12:30:24.097638 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12668 12:30:24.097929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12669 12:30:24.098183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12670 12:30:24.098261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12671 12:30:24.098507 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12672 12:30:24.099093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12673 12:30:24.099172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12674 12:30:24.103257 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12675 12:30:24.103631 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12676 12:30:24.103856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12677 12:30:24.103984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12678 12:30:24.104088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12679 12:30:24.104220 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12680 12:30:24.104322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12681 12:30:24.104412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12682 12:30:24.104513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12683 12:30:24.104600 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12684 12:30:24.104694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12685 12:30:24.104775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12686 12:30:24.104870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12687 12:30:24.104951 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12688 12:30:24.105055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12689 12:30:24.105387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12690 12:30:24.105488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12691 12:30:24.105588 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12692 12:30:24.105705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12693 12:30:24.105794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12694 12:30:24.105892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12695 12:30:24.105977 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12696 12:30:24.106054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12697 12:30:24.106318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12698 12:30:24.106424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12699 12:30:24.106708 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12700 12:30:24.106809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12701 12:30:24.107103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12702 12:30:24.111199 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12703 12:30:24.111676 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12704 12:30:24.111787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12705 12:30:24.111882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12706 12:30:24.112003 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12707 12:30:24.112113 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12708 12:30:24.112221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12709 12:30:24.112307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12710 12:30:24.112396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12711 12:30:24.112492 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12712 12:30:24.112593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12713 12:30:24.112921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12714 12:30:24.113235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12715 12:30:24.113337 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12716 12:30:24.113433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12717 12:30:24.113707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12718 12:30:24.113843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12719 12:30:24.113967 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12720 12:30:24.114069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12721 12:30:24.114188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12722 12:30:24.114303 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12723 12:30:24.114421 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12724 12:30:24.114746 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12725 12:30:24.129480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12726 12:30:24.129944 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12727 12:30:24.130049 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12728 12:30:24.130141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12729 12:30:24.130249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12730 12:30:24.130336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12731 12:30:24.130634 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12732 12:30:24.130725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12733 12:30:24.130818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12734 12:30:24.130900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12735 12:30:24.131151 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12736 12:30:24.131422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12737 12:30:24.131531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12738 12:30:24.131834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12739 12:30:24.133773 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12740 12:30:24.133859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12741 12:30:24.133926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12742 12:30:24.133990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12743 12:30:24.134052 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12744 12:30:24.134114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12745 12:30:24.134175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12746 12:30:24.134237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12747 12:30:24.134298 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12748 12:30:24.134359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12749 12:30:24.134421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12750 12:30:24.134481 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12751 12:30:24.134543 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12752 12:30:24.134607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12753 12:30:24.134668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12754 12:30:24.134731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12755 12:30:24.134792 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12756 12:30:24.134858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12757 12:30:24.135102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12758 12:30:24.135170 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12759 12:30:24.135233 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12760 12:30:24.135295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12761 12:30:24.135356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12762 12:30:24.139169 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12763 12:30:24.139477 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12764 12:30:24.139548 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12765 12:30:24.139706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12766 12:30:24.139810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12767 12:30:24.140090 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12768 12:30:24.140178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12769 12:30:24.140429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12770 12:30:24.140508 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12771 12:30:24.140758 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12772 12:30:24.141009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12773 12:30:24.141104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12774 12:30:24.141384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12775 12:30:24.141453 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12776 12:30:24.141671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12777 12:30:24.141757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12778 12:30:24.142008 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12779 12:30:24.142085 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12780 12:30:24.142389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12781 12:30:24.142471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12782 12:30:24.142725 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12783 12:30:24.142793 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12784 12:30:24.142871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12785 12:30:24.147180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12786 12:30:24.147526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12787 12:30:24.147604 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12788 12:30:24.147704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12789 12:30:24.147972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12790 12:30:24.148069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12791 12:30:24.148152 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12792 12:30:24.148403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12793 12:30:24.148662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12794 12:30:24.148739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12795 12:30:24.148987 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12796 12:30:24.149064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12797 12:30:24.149311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12798 12:30:24.149388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12799 12:30:24.149635 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12800 12:30:24.149746 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12801 12:30:24.149857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12802 12:30:24.150120 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12803 12:30:24.150207 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12804 12:30:24.150469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12805 12:30:24.150549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12806 12:30:24.150798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12807 12:30:24.150876 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12808 12:30:24.155225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12809 12:30:24.155603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12810 12:30:24.155688 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12811 12:30:24.155798 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12812 12:30:24.155907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12813 12:30:24.156015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12814 12:30:24.156281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12815 12:30:24.156360 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12816 12:30:24.156610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12817 12:30:24.156688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12818 12:30:24.156972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12819 12:30:24.157071 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12820 12:30:24.157160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12821 12:30:24.157476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12822 12:30:24.157585 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12823 12:30:24.157704 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12824 12:30:24.158045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12825 12:30:24.158149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12826 12:30:24.158266 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12827 12:30:24.158379 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12828 12:30:24.158485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12829 12:30:24.158796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12830 12:30:24.158909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12831 12:30:24.163159 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12832 12:30:24.163507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12833 12:30:24.163595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12834 12:30:24.163906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12835 12:30:24.164012 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12836 12:30:24.164310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12837 12:30:24.164433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12838 12:30:24.164542 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12839 12:30:24.164817 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12840 12:30:24.165101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12841 12:30:24.165187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12842 12:30:24.165280 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12843 12:30:24.165368 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12844 12:30:24.165690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12845 12:30:24.165766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12846 12:30:24.166041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12847 12:30:24.166336 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12848 12:30:24.166421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12849 12:30:24.166531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12850 12:30:24.166644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12851 12:30:24.166751 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12852 12:30:24.167052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12853 12:30:24.175228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12854 12:30:24.175646 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12855 12:30:24.175750 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12856 12:30:24.175866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12857 12:30:24.175944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12858 12:30:24.176022 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12859 12:30:24.202371 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12860 12:30:24.202621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12861 12:30:24.202931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12862 12:30:24.203041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12863 12:30:24.203135 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12864 12:30:24.203229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12865 12:30:24.203545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12866 12:30:24.203658 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12867 12:30:24.203752 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12868 12:30:24.203858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12869 12:30:24.203947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12870 12:30:24.204047 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12871 12:30:24.204155 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12872 12:30:24.204259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12873 12:30:24.204562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12874 12:30:24.204683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12875 12:30:24.204777 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12876 12:30:24.205075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12877 12:30:24.205181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12878 12:30:24.205477 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12879 12:30:24.205573 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12880 12:30:24.205884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12881 12:30:24.205990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12882 12:30:24.206095 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12883 12:30:24.206185 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12884 12:30:24.206291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12885 12:30:24.206587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12886 12:30:24.206696 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12887 12:30:24.206998 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12888 12:30:24.211351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12889 12:30:24.211715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12890 12:30:24.211821 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12891 12:30:24.211932 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12892 12:30:24.212021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12893 12:30:24.212126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12894 12:30:24.212231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12895 12:30:24.212533 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12896 12:30:24.212645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12897 12:30:24.212767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12898 12:30:24.213072 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12899 12:30:24.213177 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12900 12:30:24.213288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12901 12:30:24.213586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12902 12:30:24.213891 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12903 12:30:24.213980 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12904 12:30:24.214055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12905 12:30:24.214143 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12906 12:30:24.214230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12907 12:30:24.214510 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12908 12:30:24.214630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12909 12:30:24.214922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12910 12:30:24.219155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12911 12:30:24.219527 arm64_sve-ptrace pass
12912 12:30:24.219630 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12913 12:30:24.219714 arm64_sve-probe-vls_All_vector_lengths_valid pass
12914 12:30:24.219796 arm64_sve-probe-vls pass
12915 12:30:24.219902 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12916 12:30:24.219994 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12917 12:30:24.220079 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12918 12:30:24.220204 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12919 12:30:24.220312 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12920 12:30:24.220410 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12921 12:30:24.220517 arm64_vec-syscfg_SVE_vector_length_used_default pass
12922 12:30:24.220621 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12923 12:30:24.220734 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12924 12:30:24.220831 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12925 12:30:24.220922 arm64_vec-syscfg_SME_default_vector_length_32 pass
12926 12:30:24.221019 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12927 12:30:24.221302 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12928 12:30:24.221401 arm64_vec-syscfg_SME_current_VL_is_32 pass
12929 12:30:24.221495 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12930 12:30:24.221799 arm64_vec-syscfg_SME_prctl_set_min_max pass
12931 12:30:24.221915 arm64_vec-syscfg_SME_vector_length_used_default pass
12932 12:30:24.222013 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12933 12:30:24.222310 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12934 12:30:24.222421 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12935 12:30:24.222512 arm64_vec-syscfg pass
12936 12:30:24.222617 arm64_za-fork_fork_test pass
12937 12:30:24.222705 arm64_za-fork pass
12938 12:30:24.222790 arm64_za-ptrace_Set_VL_16 pass
12939 12:30:24.222890 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12940 12:30:24.222978 arm64_za-ptrace_Data_match_for_VL_16 pass
12941 12:30:24.223078 arm64_za-ptrace_Set_VL_32 pass
12942 12:30:24.227224 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12943 12:30:24.227605 arm64_za-ptrace_Data_match_for_VL_32 pass
12944 12:30:24.227709 arm64_za-ptrace_Set_VL_48 pass
12945 12:30:24.227793 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12946 12:30:24.227884 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12947 12:30:24.227988 arm64_za-ptrace_Set_VL_64 pass
12948 12:30:24.228076 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12949 12:30:24.228162 arm64_za-ptrace_Data_match_for_VL_64 pass
12950 12:30:24.228263 arm64_za-ptrace_Set_VL_80 pass
12951 12:30:24.228351 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12952 12:30:24.228452 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12953 12:30:24.228778 arm64_za-ptrace_Set_VL_96 pass
12954 12:30:24.228942 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12955 12:30:24.229088 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12956 12:30:24.229212 arm64_za-ptrace_Set_VL_112 pass
12957 12:30:24.229352 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12958 12:30:24.229476 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12959 12:30:24.229595 arm64_za-ptrace_Set_VL_128 pass
12960 12:30:24.229801 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12961 12:30:24.229946 arm64_za-ptrace_Data_match_for_VL_128 pass
12962 12:30:24.230069 arm64_za-ptrace_Set_VL_144 pass
12963 12:30:24.233789 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12964 12:30:24.234013 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12965 12:30:24.234136 arm64_za-ptrace_Set_VL_160 pass
12966 12:30:24.234253 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12967 12:30:24.234371 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12968 12:30:24.234485 arm64_za-ptrace_Set_VL_176 pass
12969 12:30:24.234598 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12970 12:30:24.234711 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12971 12:30:24.234825 arm64_za-ptrace_Set_VL_192 pass
12972 12:30:24.234939 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12973 12:30:24.235052 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12974 12:30:24.235167 arm64_za-ptrace_Set_VL_208 pass
12975 12:30:24.235499 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12976 12:30:24.235696 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12977 12:30:24.235877 arm64_za-ptrace_Set_VL_224 pass
12978 12:30:24.236096 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12979 12:30:24.236245 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12980 12:30:24.236366 arm64_za-ptrace_Set_VL_240 pass
12981 12:30:24.236482 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
12982 12:30:24.236596 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
12983 12:30:24.236711 arm64_za-ptrace_Set_VL_256 pass
12984 12:30:24.236852 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
12985 12:30:24.236971 arm64_za-ptrace_Data_match_for_VL_256 pass
12986 12:30:24.237086 arm64_za-ptrace_Set_VL_272 pass
12987 12:30:24.237201 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
12988 12:30:24.237316 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
12989 12:30:24.237430 arm64_za-ptrace_Set_VL_288 pass
12990 12:30:24.237545 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
12991 12:30:24.237727 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
12992 12:30:24.237883 arm64_za-ptrace_Set_VL_304 pass
12993 12:30:24.238004 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
12994 12:30:24.238121 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
12995 12:30:24.238236 arm64_za-ptrace_Set_VL_320 pass
12996 12:30:24.238355 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
12997 12:30:24.238472 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
12998 12:30:24.238587 arm64_za-ptrace_Set_VL_336 pass
12999 12:30:24.238703 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13000 12:30:24.238851 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13001 12:30:24.238974 arm64_za-ptrace_Set_VL_352 pass
13002 12:30:24.239090 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13003 12:30:24.239205 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13004 12:30:24.239321 arm64_za-ptrace_Set_VL_368 pass
13005 12:30:24.239479 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13006 12:30:24.239647 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13007 12:30:24.239795 arm64_za-ptrace_Set_VL_384 pass
13008 12:30:24.239944 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13009 12:30:24.240113 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13010 12:30:24.243158 arm64_za-ptrace_Set_VL_400 pass
13011 12:30:24.243470 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13012 12:30:24.243576 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13013 12:30:24.243681 arm64_za-ptrace_Set_VL_416 pass
13014 12:30:24.243768 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13015 12:30:24.243871 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13016 12:30:24.243970 arm64_za-ptrace_Set_VL_432 pass
13017 12:30:24.244066 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13018 12:30:24.244363 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13019 12:30:24.244466 arm64_za-ptrace_Set_VL_448 pass
13020 12:30:24.244566 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13021 12:30:24.244652 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13022 12:30:24.244749 arm64_za-ptrace_Set_VL_464 pass
13023 12:30:24.244832 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13024 12:30:24.244927 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13025 12:30:24.245206 arm64_za-ptrace_Set_VL_480 pass
13026 12:30:24.245323 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13027 12:30:24.245418 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13028 12:30:24.245505 arm64_za-ptrace_Set_VL_496 pass
13029 12:30:24.245603 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13030 12:30:24.265349 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13031 12:30:24.265557 arm64_za-ptrace_Set_VL_512 pass
13032 12:30:24.265663 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13033 12:30:24.265794 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13034 12:30:24.265917 arm64_za-ptrace_Set_VL_528 pass
13035 12:30:24.266038 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13036 12:30:24.266143 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13037 12:30:24.266277 arm64_za-ptrace_Set_VL_544 pass
13038 12:30:24.266379 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13039 12:30:24.266502 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13040 12:30:24.266604 arm64_za-ptrace_Set_VL_560 pass
13041 12:30:24.266709 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13042 12:30:24.266800 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13043 12:30:24.267100 arm64_za-ptrace_Set_VL_576 pass
13044 12:30:24.267206 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13045 12:30:24.267294 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13046 12:30:24.267377 arm64_za-ptrace_Set_VL_592 pass
13047 12:30:24.267459 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13048 12:30:24.267539 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13049 12:30:24.267619 arm64_za-ptrace_Set_VL_608 pass
13050 12:30:24.267700 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13051 12:30:24.267783 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13052 12:30:24.267871 arm64_za-ptrace_Set_VL_624 pass
13053 12:30:24.267972 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13054 12:30:24.268056 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13055 12:30:24.268136 arm64_za-ptrace_Set_VL_640 pass
13056 12:30:24.268215 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13057 12:30:24.268297 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13058 12:30:24.271352 arm64_za-ptrace_Set_VL_656 pass
13059 12:30:24.271693 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13060 12:30:24.271802 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13061 12:30:24.271888 arm64_za-ptrace_Set_VL_672 pass
13062 12:30:24.271974 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13063 12:30:24.272075 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13064 12:30:24.272164 arm64_za-ptrace_Set_VL_688 pass
13065 12:30:24.272251 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13066 12:30:24.272339 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13067 12:30:24.272449 arm64_za-ptrace_Set_VL_704 pass
13068 12:30:24.272541 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13069 12:30:24.272645 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13070 12:30:24.272732 arm64_za-ptrace_Set_VL_720 pass
13071 12:30:24.272832 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13072 12:30:24.272921 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13073 12:30:24.273025 arm64_za-ptrace_Set_VL_736 pass
13074 12:30:24.273128 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13075 12:30:24.273226 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13076 12:30:24.273326 arm64_za-ptrace_Set_VL_752 pass
13077 12:30:24.273434 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13078 12:30:24.273696 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13079 12:30:24.273814 arm64_za-ptrace_Set_VL_768 pass
13080 12:30:24.274099 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13081 12:30:24.274192 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13082 12:30:24.274294 arm64_za-ptrace_Set_VL_784 pass
13083 12:30:24.274381 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13084 12:30:24.274475 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13085 12:30:24.274580 arm64_za-ptrace_Set_VL_800 pass
13086 12:30:24.274704 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13087 12:30:24.274809 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13088 12:30:24.274998 arm64_za-ptrace_Set_VL_816 pass
13089 12:30:24.275133 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13090 12:30:24.275245 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13091 12:30:24.279188 arm64_za-ptrace_Set_VL_832 pass
13092 12:30:24.279581 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13093 12:30:24.279751 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13094 12:30:24.279943 arm64_za-ptrace_Set_VL_848 pass
13095 12:30:24.280169 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13096 12:30:24.280348 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13097 12:30:24.280520 arm64_za-ptrace_Set_VL_864 pass
13098 12:30:24.280692 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13099 12:30:24.280862 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13100 12:30:24.281035 arm64_za-ptrace_Set_VL_880 pass
13101 12:30:24.281209 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13102 12:30:24.281415 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13103 12:30:24.281584 arm64_za-ptrace_Set_VL_896 pass
13104 12:30:24.281767 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13105 12:30:24.281938 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13106 12:30:24.282104 arm64_za-ptrace_Set_VL_912 pass
13107 12:30:24.282269 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13108 12:30:24.282421 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13109 12:30:24.282545 arm64_za-ptrace_Set_VL_928 pass
13110 12:30:24.282669 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13111 12:30:24.282821 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13112 12:30:24.283341 arm64_za-ptrace_Set_VL_944 pass
13113 12:30:24.283458 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13114 12:30:24.283546 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13115 12:30:24.283629 arm64_za-ptrace_Set_VL_960 pass
13116 12:30:24.283712 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13117 12:30:24.283794 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13118 12:30:24.283879 arm64_za-ptrace_Set_VL_976 pass
13119 12:30:24.283963 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13120 12:30:24.284047 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13121 12:30:24.284131 arm64_za-ptrace_Set_VL_992 pass
13122 12:30:24.284214 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13123 12:30:24.284319 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13124 12:30:24.284408 arm64_za-ptrace_Set_VL_1008 pass
13125 12:30:24.284494 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13126 12:30:24.284579 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13127 12:30:24.284666 arm64_za-ptrace_Set_VL_1024 pass
13128 12:30:24.287514 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13129 12:30:24.287668 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13130 12:30:24.287760 arm64_za-ptrace_Set_VL_1040 pass
13131 12:30:24.287849 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13132 12:30:24.287952 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13133 12:30:24.288040 arm64_za-ptrace_Set_VL_1056 pass
13134 12:30:24.288160 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13135 12:30:24.288255 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13136 12:30:24.288344 arm64_za-ptrace_Set_VL_1072 pass
13137 12:30:24.288453 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13138 12:30:24.288539 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13139 12:30:24.288642 arm64_za-ptrace_Set_VL_1088 pass
13140 12:30:24.288731 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13141 12:30:24.288829 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13142 12:30:24.288928 arm64_za-ptrace_Set_VL_1104 pass
13143 12:30:24.289032 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13144 12:30:24.289335 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13145 12:30:24.289457 arm64_za-ptrace_Set_VL_1120 pass
13146 12:30:24.289576 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13147 12:30:24.289680 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13148 12:30:24.289769 arm64_za-ptrace_Set_VL_1136 pass
13149 12:30:24.289867 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13150 12:30:24.290149 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13151 12:30:24.290254 arm64_za-ptrace_Set_VL_1152 pass
13152 12:30:24.290344 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13153 12:30:24.290447 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13154 12:30:24.290547 arm64_za-ptrace_Set_VL_1168 pass
13155 12:30:24.290649 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13156 12:30:24.290761 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13157 12:30:24.290867 arm64_za-ptrace_Set_VL_1184 pass
13158 12:30:24.290984 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13159 12:30:24.291076 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13160 12:30:24.291171 arm64_za-ptrace_Set_VL_1200 pass
13161 12:30:24.291255 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13162 12:30:24.291320 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13163 12:30:24.291380 arm64_za-ptrace_Set_VL_1216 pass
13164 12:30:24.295339 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13165 12:30:24.295508 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13166 12:30:24.295733 arm64_za-ptrace_Set_VL_1232 pass
13167 12:30:24.296120 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13168 12:30:24.296233 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13169 12:30:24.296322 arm64_za-ptrace_Set_VL_1248 pass
13170 12:30:24.296410 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13171 12:30:24.296496 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13172 12:30:24.296583 arm64_za-ptrace_Set_VL_1264 pass
13173 12:30:24.296668 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13174 12:30:24.296771 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13175 12:30:24.296857 arm64_za-ptrace_Set_VL_1280 pass
13176 12:30:24.296941 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13177 12:30:24.297026 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13178 12:30:24.297112 arm64_za-ptrace_Set_VL_1296 pass
13179 12:30:24.297199 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13180 12:30:24.297303 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13181 12:30:24.297394 arm64_za-ptrace_Set_VL_1312 pass
13182 12:30:24.297480 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13183 12:30:24.297582 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13184 12:30:24.297681 arm64_za-ptrace_Set_VL_1328 pass
13185 12:30:24.297771 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13186 12:30:24.297873 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13187 12:30:24.297958 arm64_za-ptrace_Set_VL_1344 pass
13188 12:30:24.298393 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13189 12:30:24.298620 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13190 12:30:24.298722 arm64_za-ptrace_Set_VL_1360 pass
13191 12:30:24.298799 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13192 12:30:24.298880 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13193 12:30:24.298962 arm64_za-ptrace_Set_VL_1376 pass
13194 12:30:24.299064 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13195 12:30:24.299151 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13196 12:30:24.299235 arm64_za-ptrace_Set_VL_1392 pass
13197 12:30:24.299319 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13198 12:30:24.303165 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13199 12:30:24.303666 arm64_za-ptrace_Set_VL_1408 pass
13200 12:30:24.303778 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13201 12:30:24.303907 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13202 12:30:24.304038 arm64_za-ptrace_Set_VL_1424 pass
13203 12:30:24.304160 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13204 12:30:24.304255 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13205 12:30:24.304344 arm64_za-ptrace_Set_VL_1440 pass
13206 12:30:24.304435 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13207 12:30:24.304541 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13208 12:30:24.304626 arm64_za-ptrace_Set_VL_1456 pass
13209 12:30:24.304708 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13210 12:30:24.304806 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13211 12:30:24.304896 arm64_za-ptrace_Set_VL_1472 pass
13212 12:30:24.304998 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13213 12:30:24.305087 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13214 12:30:24.305176 arm64_za-ptrace_Set_VL_1488 pass
13215 12:30:24.305279 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13216 12:30:24.305381 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13217 12:30:24.305483 arm64_za-ptrace_Set_VL_1504 pass
13218 12:30:24.305572 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13219 12:30:24.306352 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13220 12:30:24.306460 arm64_za-ptrace_Set_VL_1520 pass
13221 12:30:24.306544 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13222 12:30:24.306630 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13223 12:30:24.306715 arm64_za-ptrace_Set_VL_1536 pass
13224 12:30:24.306800 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13225 12:30:24.329376 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13226 12:30:24.329793 arm64_za-ptrace_Set_VL_1552 pass
13227 12:30:24.329900 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13228 12:30:24.329990 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13229 12:30:24.330079 arm64_za-ptrace_Set_VL_1568 pass
13230 12:30:24.330178 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13231 12:30:24.330274 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13232 12:30:24.330397 arm64_za-ptrace_Set_VL_1584 pass
13233 12:30:24.330506 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13234 12:30:24.330610 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13235 12:30:24.330693 arm64_za-ptrace_Set_VL_1600 pass
13236 12:30:24.330807 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13237 12:30:24.331028 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13238 12:30:24.331128 arm64_za-ptrace_Set_VL_1616 pass
13239 12:30:24.331236 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13240 12:30:24.331514 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13241 12:30:24.331672 arm64_za-ptrace_Set_VL_1632 pass
13242 12:30:24.331750 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13243 12:30:24.331824 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13244 12:30:24.331914 arm64_za-ptrace_Set_VL_1648 pass
13245 12:30:24.332000 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13246 12:30:24.332106 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13247 12:30:24.332192 arm64_za-ptrace_Set_VL_1664 pass
13248 12:30:24.332269 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13249 12:30:24.332336 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13250 12:30:24.332409 arm64_za-ptrace_Set_VL_1680 pass
13251 12:30:24.332485 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13252 12:30:24.332584 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13253 12:30:24.332666 arm64_za-ptrace_Set_VL_1696 pass
13254 12:30:24.332752 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13255 12:30:24.332835 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13256 12:30:24.332922 arm64_za-ptrace_Set_VL_1712 pass
13257 12:30:24.332987 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13258 12:30:24.333070 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13259 12:30:24.333164 arm64_za-ptrace_Set_VL_1728 pass
13260 12:30:24.333244 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13261 12:30:24.333335 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13262 12:30:24.333414 arm64_za-ptrace_Set_VL_1744 pass
13263 12:30:24.333505 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13264 12:30:24.333604 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13265 12:30:24.333701 arm64_za-ptrace_Set_VL_1760 pass
13266 12:30:24.334287 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13267 12:30:24.334402 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13268 12:30:24.334500 arm64_za-ptrace_Set_VL_1776 pass
13269 12:30:24.334596 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13270 12:30:24.334707 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13271 12:30:24.334805 arm64_za-ptrace_Set_VL_1792 pass
13272 12:30:24.334894 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13273 12:30:24.334988 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13274 12:30:24.335082 arm64_za-ptrace_Set_VL_1808 pass
13275 12:30:24.335188 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13276 12:30:24.335283 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13277 12:30:24.335380 arm64_za-ptrace_Set_VL_1824 pass
13278 12:30:24.335476 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13279 12:30:24.339451 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13280 12:30:24.339906 arm64_za-ptrace_Set_VL_1840 pass
13281 12:30:24.340016 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13282 12:30:24.340140 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13283 12:30:24.340235 arm64_za-ptrace_Set_VL_1856 pass
13284 12:30:24.340325 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13285 12:30:24.340414 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13286 12:30:24.340502 arm64_za-ptrace_Set_VL_1872 pass
13287 12:30:24.340589 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13288 12:30:24.340696 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13289 12:30:24.340788 arm64_za-ptrace_Set_VL_1888 pass
13290 12:30:24.340875 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13291 12:30:24.340964 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13292 12:30:24.341054 arm64_za-ptrace_Set_VL_1904 pass
13293 12:30:24.341157 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13294 12:30:24.341246 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13295 12:30:24.341334 arm64_za-ptrace_Set_VL_1920 pass
13296 12:30:24.341423 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13297 12:30:24.341528 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13298 12:30:24.341615 arm64_za-ptrace_Set_VL_1936 pass
13299 12:30:24.341715 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13300 12:30:24.341818 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13301 12:30:24.341909 arm64_za-ptrace_Set_VL_1952 pass
13302 12:30:24.341998 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13303 12:30:24.342105 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13304 12:30:24.342194 arm64_za-ptrace_Set_VL_1968 pass
13305 12:30:24.342291 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13306 12:30:24.342376 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13307 12:30:24.342478 arm64_za-ptrace_Set_VL_1984 pass
13308 12:30:24.342591 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13309 12:30:24.342696 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13310 12:30:24.342800 arm64_za-ptrace_Set_VL_2000 pass
13311 12:30:24.342903 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13312 12:30:24.343200 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13313 12:30:24.347162 arm64_za-ptrace_Set_VL_2016 pass
13314 12:30:24.347532 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13315 12:30:24.347684 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13316 12:30:24.347861 arm64_za-ptrace_Set_VL_2032 pass
13317 12:30:24.347984 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13318 12:30:24.348117 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13319 12:30:24.348255 arm64_za-ptrace_Set_VL_2048 pass
13320 12:30:24.348361 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13321 12:30:24.348509 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13322 12:30:24.348670 arm64_za-ptrace_Set_VL_2064 pass
13323 12:30:24.348778 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13324 12:30:24.348888 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13325 12:30:24.349020 arm64_za-ptrace_Set_VL_2080 pass
13326 12:30:24.349125 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13327 12:30:24.349259 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13328 12:30:24.349363 arm64_za-ptrace_Set_VL_2096 pass
13329 12:30:24.349489 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13330 12:30:24.349657 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13331 12:30:24.349792 arm64_za-ptrace_Set_VL_2112 pass
13332 12:30:24.349943 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13333 12:30:24.350110 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13334 12:30:24.350252 arm64_za-ptrace_Set_VL_2128 pass
13335 12:30:24.350403 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13336 12:30:24.350546 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13337 12:30:24.350716 arm64_za-ptrace_Set_VL_2144 pass
13338 12:30:24.350871 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13339 12:30:24.351022 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13340 12:30:24.351172 arm64_za-ptrace_Set_VL_2160 pass
13341 12:30:24.351306 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13342 12:30:24.351454 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13343 12:30:24.351617 arm64_za-ptrace_Set_VL_2176 pass
13344 12:30:24.351783 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13345 12:30:24.355158 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13346 12:30:24.355516 arm64_za-ptrace_Set_VL_2192 pass
13347 12:30:24.355623 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13348 12:30:24.355713 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13349 12:30:24.355811 arm64_za-ptrace_Set_VL_2208 pass
13350 12:30:24.355917 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13351 12:30:24.356008 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13352 12:30:24.356099 arm64_za-ptrace_Set_VL_2224 pass
13353 12:30:24.356204 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13354 12:30:24.356293 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13355 12:30:24.356382 arm64_za-ptrace_Set_VL_2240 pass
13356 12:30:24.356489 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13357 12:30:24.356583 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13358 12:30:24.356672 arm64_za-ptrace_Set_VL_2256 pass
13359 12:30:24.356779 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13360 12:30:24.356869 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13361 12:30:24.356957 arm64_za-ptrace_Set_VL_2272 pass
13362 12:30:24.357062 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13363 12:30:24.357152 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13364 12:30:24.357242 arm64_za-ptrace_Set_VL_2288 pass
13365 12:30:24.357345 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13366 12:30:24.357432 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13367 12:30:24.357533 arm64_za-ptrace_Set_VL_2304 pass
13368 12:30:24.357637 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13369 12:30:24.357746 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13370 12:30:24.357829 arm64_za-ptrace_Set_VL_2320 pass
13371 12:30:24.357923 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13372 12:30:24.358021 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13373 12:30:24.358122 arm64_za-ptrace_Set_VL_2336 pass
13374 12:30:24.358432 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13375 12:30:24.358627 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13376 12:30:24.358750 arm64_za-ptrace_Set_VL_2352 pass
13377 12:30:24.358932 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13378 12:30:24.359053 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13379 12:30:24.359146 arm64_za-ptrace_Set_VL_2368 pass
13380 12:30:24.359236 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13381 12:30:24.363185 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13382 12:30:24.363536 arm64_za-ptrace_Set_VL_2384 pass
13383 12:30:24.363635 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13384 12:30:24.363722 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13385 12:30:24.363824 arm64_za-ptrace_Set_VL_2400 pass
13386 12:30:24.363913 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13387 12:30:24.364018 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13388 12:30:24.364108 arm64_za-ptrace_Set_VL_2416 pass
13389 12:30:24.364208 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13390 12:30:24.364312 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13391 12:30:24.364633 arm64_za-ptrace_Set_VL_2432 pass
13392 12:30:24.364843 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13393 12:30:24.365050 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13394 12:30:24.365310 arm64_za-ptrace_Set_VL_2448 pass
13395 12:30:24.365530 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13396 12:30:24.365767 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13397 12:30:24.365998 arm64_za-ptrace_Set_VL_2464 pass
13398 12:30:24.366185 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13399 12:30:24.366365 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13400 12:30:24.366540 arm64_za-ptrace_Set_VL_2480 pass
13401 12:30:24.366702 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13402 12:30:24.366831 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13403 12:30:24.367001 arm64_za-ptrace_Set_VL_2496 pass
13404 12:30:24.367127 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13405 12:30:24.367258 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13406 12:30:24.367379 arm64_za-ptrace_Set_VL_2512 pass
13407 12:30:24.367495 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13408 12:30:24.367622 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13409 12:30:24.367758 arm64_za-ptrace_Set_VL_2528 pass
13410 12:30:24.367956 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13411 12:30:24.368083 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13412 12:30:24.368202 arm64_za-ptrace_Set_VL_2544 pass
13413 12:30:24.368318 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13414 12:30:24.371123 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13415 12:30:24.371441 arm64_za-ptrace_Set_VL_2560 pass
13416 12:30:24.371536 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13417 12:30:24.371898 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13418 12:30:24.390201 arm64_za-ptrace_Set_VL_2576 pass
13419 12:30:24.390794 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13420 12:30:24.390992 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13421 12:30:24.391128 arm64_za-ptrace_Set_VL_2592 pass
13422 12:30:24.391249 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13423 12:30:24.391398 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13424 12:30:24.391594 arm64_za-ptrace_Set_VL_2608 pass
13425 12:30:24.391733 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13426 12:30:24.391858 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13427 12:30:24.391984 arm64_za-ptrace_Set_VL_2624 pass
13428 12:30:24.392105 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13429 12:30:24.392252 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13430 12:30:24.392375 arm64_za-ptrace_Set_VL_2640 pass
13431 12:30:24.392497 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13432 12:30:24.392616 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13433 12:30:24.392740 arm64_za-ptrace_Set_VL_2656 pass
13434 12:30:24.392866 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13435 12:30:24.393024 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13436 12:30:24.393151 arm64_za-ptrace_Set_VL_2672 pass
13437 12:30:24.393275 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13438 12:30:24.393395 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13439 12:30:24.393504 arm64_za-ptrace_Set_VL_2688 pass
13440 12:30:24.393624 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13441 12:30:24.393742 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13442 12:30:24.393844 arm64_za-ptrace_Set_VL_2704 pass
13443 12:30:24.393987 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13444 12:30:24.394110 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13445 12:30:24.394232 arm64_za-ptrace_Set_VL_2720 pass
13446 12:30:24.394340 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13447 12:30:24.394452 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13448 12:30:24.394565 arm64_za-ptrace_Set_VL_2736 pass
13449 12:30:24.394653 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13450 12:30:24.394723 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13451 12:30:24.394796 arm64_za-ptrace_Set_VL_2752 pass
13452 12:30:24.394878 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13453 12:30:24.394949 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13454 12:30:24.395014 arm64_za-ptrace_Set_VL_2768 pass
13455 12:30:24.395074 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13456 12:30:24.395133 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13457 12:30:24.395192 arm64_za-ptrace_Set_VL_2784 pass
13458 12:30:24.395253 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13459 12:30:24.395313 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13460 12:30:24.395372 arm64_za-ptrace_Set_VL_2800 pass
13461 12:30:24.399163 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13462 12:30:24.399522 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13463 12:30:24.399668 arm64_za-ptrace_Set_VL_2816 pass
13464 12:30:24.399815 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13465 12:30:24.400010 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13466 12:30:24.400109 arm64_za-ptrace_Set_VL_2832 pass
13467 12:30:24.400196 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13468 12:30:24.400281 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13469 12:30:24.400382 arm64_za-ptrace_Set_VL_2848 pass
13470 12:30:24.400469 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13471 12:30:24.400570 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13472 12:30:24.400658 arm64_za-ptrace_Set_VL_2864 pass
13473 12:30:24.400757 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13474 12:30:24.400845 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13475 12:30:24.400945 arm64_za-ptrace_Set_VL_2880 pass
13476 12:30:24.401045 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13477 12:30:24.401388 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13478 12:30:24.401495 arm64_za-ptrace_Set_VL_2896 pass
13479 12:30:24.401600 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13480 12:30:24.401743 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13481 12:30:24.401855 arm64_za-ptrace_Set_VL_2912 pass
13482 12:30:24.401945 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13483 12:30:24.402048 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13484 12:30:24.402151 arm64_za-ptrace_Set_VL_2928 pass
13485 12:30:24.402260 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13486 12:30:24.402554 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13487 12:30:24.402667 arm64_za-ptrace_Set_VL_2944 pass
13488 12:30:24.402770 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13489 12:30:24.402867 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13490 12:30:24.402967 arm64_za-ptrace_Set_VL_2960 pass
13491 12:30:24.407146 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13492 12:30:24.407487 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13493 12:30:24.407594 arm64_za-ptrace_Set_VL_2976 pass
13494 12:30:24.407687 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13495 12:30:24.407790 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13496 12:30:24.407884 arm64_za-ptrace_Set_VL_2992 pass
13497 12:30:24.407991 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13498 12:30:24.408082 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13499 12:30:24.408190 arm64_za-ptrace_Set_VL_3008 pass
13500 12:30:24.408283 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13501 12:30:24.408388 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13502 12:30:24.408496 arm64_za-ptrace_Set_VL_3024 pass
13503 12:30:24.408597 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13504 12:30:24.408688 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13505 12:30:24.408791 arm64_za-ptrace_Set_VL_3040 pass
13506 12:30:24.408893 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13507 12:30:24.408994 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13508 12:30:24.409094 arm64_za-ptrace_Set_VL_3056 pass
13509 12:30:24.409392 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13510 12:30:24.409493 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13511 12:30:24.409600 arm64_za-ptrace_Set_VL_3072 pass
13512 12:30:24.409701 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13513 12:30:24.409807 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13514 12:30:24.409911 arm64_za-ptrace_Set_VL_3088 pass
13515 12:30:24.409996 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13516 12:30:24.410097 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13517 12:30:24.410185 arm64_za-ptrace_Set_VL_3104 pass
13518 12:30:24.410285 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13519 12:30:24.410386 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13520 12:30:24.410814 arm64_za-ptrace_Set_VL_3120 pass
13521 12:30:24.411019 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13522 12:30:24.411175 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13523 12:30:24.411299 arm64_za-ptrace_Set_VL_3136 pass
13524 12:30:24.411420 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13525 12:30:24.415263 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13526 12:30:24.415501 arm64_za-ptrace_Set_VL_3152 pass
13527 12:30:24.416727 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13528 12:30:24.416881 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13529 12:30:24.417042 arm64_za-ptrace_Set_VL_3168 pass
13530 12:30:24.417190 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13531 12:30:24.417427 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13532 12:30:24.417606 arm64_za-ptrace_Set_VL_3184 pass
13533 12:30:24.417797 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13534 12:30:24.417965 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13535 12:30:24.418114 arm64_za-ptrace_Set_VL_3200 pass
13536 12:30:24.418284 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13537 12:30:24.418428 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13538 12:30:24.418588 arm64_za-ptrace_Set_VL_3216 pass
13539 12:30:24.418788 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13540 12:30:24.418954 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13541 12:30:24.419116 arm64_za-ptrace_Set_VL_3232 pass
13542 12:30:24.419262 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13543 12:30:24.419432 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13544 12:30:24.419578 arm64_za-ptrace_Set_VL_3248 pass
13545 12:30:24.419736 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13546 12:30:24.419896 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13547 12:30:24.420040 arm64_za-ptrace_Set_VL_3264 pass
13548 12:30:24.420209 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13549 12:30:24.420355 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13550 12:30:24.420513 arm64_za-ptrace_Set_VL_3280 pass
13551 12:30:24.420719 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13552 12:30:24.420880 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13553 12:30:24.421044 arm64_za-ptrace_Set_VL_3296 pass
13554 12:30:24.421188 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13555 12:30:24.421356 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13556 12:30:24.421504 arm64_za-ptrace_Set_VL_3312 pass
13557 12:30:24.422335 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13558 12:30:24.422542 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13559 12:30:24.422696 arm64_za-ptrace_Set_VL_3328 pass
13560 12:30:24.422853 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13561 12:30:24.423009 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13562 12:30:24.423155 arm64_za-ptrace_Set_VL_3344 pass
13563 12:30:24.423318 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13564 12:30:24.423460 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13565 12:30:24.423617 arm64_za-ptrace_Set_VL_3360 pass
13566 12:30:24.423740 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13567 12:30:24.423922 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13568 12:30:24.424072 arm64_za-ptrace_Set_VL_3376 pass
13569 12:30:24.424189 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13570 12:30:24.424305 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13571 12:30:24.424703 arm64_za-ptrace_Set_VL_3392 pass
13572 12:30:24.424920 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13573 12:30:24.425079 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13574 12:30:24.425225 arm64_za-ptrace_Set_VL_3408 pass
13575 12:30:24.425371 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13576 12:30:24.425514 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13577 12:30:24.425673 arm64_za-ptrace_Set_VL_3424 pass
13578 12:30:24.425820 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13579 12:30:24.425965 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13580 12:30:24.426108 arm64_za-ptrace_Set_VL_3440 pass
13581 12:30:24.426252 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13582 12:30:24.426395 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13583 12:30:24.426540 arm64_za-ptrace_Set_VL_3456 pass
13584 12:30:24.426674 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13585 12:30:24.426782 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13586 12:30:24.426890 arm64_za-ptrace_Set_VL_3472 pass
13587 12:30:24.426997 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13588 12:30:24.427105 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13589 12:30:24.427213 arm64_za-ptrace_Set_VL_3488 pass
13590 12:30:24.427321 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13591 12:30:24.431198 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13592 12:30:24.431381 arm64_za-ptrace_Set_VL_3504 pass
13593 12:30:24.431667 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13594 12:30:24.431778 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13595 12:30:24.431870 arm64_za-ptrace_Set_VL_3520 pass
13596 12:30:24.431958 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13597 12:30:24.432045 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13598 12:30:24.432152 arm64_za-ptrace_Set_VL_3536 pass
13599 12:30:24.432241 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13600 12:30:24.432324 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13601 12:30:24.432428 arm64_za-ptrace_Set_VL_3552 pass
13602 12:30:24.432516 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13603 12:30:24.432618 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13604 12:30:24.432712 arm64_za-ptrace_Set_VL_3568 pass
13605 12:30:24.432814 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13606 12:30:24.432918 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13607 12:30:24.433006 arm64_za-ptrace_Set_VL_3584 pass
13608 12:30:24.433107 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13609 12:30:24.433205 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13610 12:30:24.449131 arm64_za-ptrace_Set_VL_3600 pass
13611 12:30:24.449532 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13612 12:30:24.449602 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13613 12:30:24.449860 arm64_za-ptrace_Set_VL_3616 pass
13614 12:30:24.449928 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13615 12:30:24.449988 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13616 12:30:24.450047 arm64_za-ptrace_Set_VL_3632 pass
13617 12:30:24.450106 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13618 12:30:24.450166 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13619 12:30:24.450239 arm64_za-ptrace_Set_VL_3648 pass
13620 12:30:24.450301 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13621 12:30:24.450360 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13622 12:30:24.450434 arm64_za-ptrace_Set_VL_3664 pass
13623 12:30:24.450496 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13624 12:30:24.450744 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13625 12:30:24.450813 arm64_za-ptrace_Set_VL_3680 pass
13626 12:30:24.450884 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13627 12:30:24.451128 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13628 12:30:24.451379 arm64_za-ptrace_Set_VL_3696 pass
13629 12:30:24.451443 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13630 12:30:24.451514 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13631 12:30:24.451607 arm64_za-ptrace_Set_VL_3712 pass
13632 12:30:24.451858 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13633 12:30:24.452103 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13634 12:30:24.452167 arm64_za-ptrace_Set_VL_3728 pass
13635 12:30:24.452228 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13636 12:30:24.452298 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13637 12:30:24.452370 arm64_za-ptrace_Set_VL_3744 pass
13638 12:30:24.452617 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13639 12:30:24.452692 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13640 12:30:24.452943 arm64_za-ptrace_Set_VL_3760 pass
13641 12:30:24.453008 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13642 12:30:24.453108 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13643 12:30:24.453209 arm64_za-ptrace_Set_VL_3776 pass
13644 12:30:24.453505 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13645 12:30:24.453613 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13646 12:30:24.453739 arm64_za-ptrace_Set_VL_3792 pass
13647 12:30:24.453833 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13648 12:30:24.454143 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13649 12:30:24.454247 arm64_za-ptrace_Set_VL_3808 pass
13650 12:30:24.454333 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13651 12:30:24.454434 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13652 12:30:24.454522 arm64_za-ptrace_Set_VL_3824 pass
13653 12:30:24.454623 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13654 12:30:24.454711 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13655 12:30:24.454815 arm64_za-ptrace_Set_VL_3840 pass
13656 12:30:24.454902 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13657 12:30:24.455002 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13658 12:30:24.455089 arm64_za-ptrace_Set_VL_3856 pass
13659 12:30:24.459345 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13660 12:30:24.459567 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13661 12:30:24.459913 arm64_za-ptrace_Set_VL_3872 pass
13662 12:30:24.460017 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13663 12:30:24.460105 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13664 12:30:24.460191 arm64_za-ptrace_Set_VL_3888 pass
13665 12:30:24.460275 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13666 12:30:24.460360 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13667 12:30:24.460462 arm64_za-ptrace_Set_VL_3904 pass
13668 12:30:24.460553 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13669 12:30:24.460638 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13670 12:30:24.460723 arm64_za-ptrace_Set_VL_3920 pass
13671 12:30:24.460812 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13672 12:30:24.460895 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13673 12:30:24.460997 arm64_za-ptrace_Set_VL_3936 pass
13674 12:30:24.461084 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13675 12:30:24.461168 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13676 12:30:24.461253 arm64_za-ptrace_Set_VL_3952 pass
13677 12:30:24.461337 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13678 12:30:24.461438 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13679 12:30:24.461526 arm64_za-ptrace_Set_VL_3968 pass
13680 12:30:24.461610 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13681 12:30:24.461715 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13682 12:30:24.461805 arm64_za-ptrace_Set_VL_3984 pass
13683 12:30:24.461906 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13684 12:30:24.461993 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13685 12:30:24.462079 arm64_za-ptrace_Set_VL_4000 pass
13686 12:30:24.462164 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13687 12:30:24.462248 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13688 12:30:24.462351 arm64_za-ptrace_Set_VL_4016 pass
13689 12:30:24.462438 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13690 12:30:24.462524 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13691 12:30:24.462608 arm64_za-ptrace_Set_VL_4032 pass
13692 12:30:24.462708 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13693 12:30:24.462799 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13694 12:30:24.462885 arm64_za-ptrace_Set_VL_4048 pass
13695 12:30:24.462983 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13696 12:30:24.463067 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13697 12:30:24.467578 arm64_za-ptrace_Set_VL_4064 pass
13698 12:30:24.467809 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13699 12:30:24.467899 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13700 12:30:24.468006 arm64_za-ptrace_Set_VL_4080 pass
13701 12:30:24.468094 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13702 12:30:24.468182 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13703 12:30:24.468266 arm64_za-ptrace_Set_VL_4096 pass
13704 12:30:24.468365 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13705 12:30:24.468454 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13706 12:30:24.468555 arm64_za-ptrace_Set_VL_4112 pass
13707 12:30:24.468655 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13708 12:30:24.468760 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13709 12:30:24.468848 arm64_za-ptrace_Set_VL_4128 pass
13710 12:30:24.468947 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13711 12:30:24.469033 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13712 12:30:24.469130 arm64_za-ptrace_Set_VL_4144 pass
13713 12:30:24.469460 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13714 12:30:24.469565 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13715 12:30:24.469667 arm64_za-ptrace_Set_VL_4160 pass
13716 12:30:24.469770 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13717 12:30:24.469877 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13718 12:30:24.469963 arm64_za-ptrace_Set_VL_4176 pass
13719 12:30:24.470047 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13720 12:30:24.470130 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13721 12:30:24.470214 arm64_za-ptrace_Set_VL_4192 pass
13722 12:30:24.470312 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13723 12:30:24.470413 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13724 12:30:24.470499 arm64_za-ptrace_Set_VL_4208 pass
13725 12:30:24.470583 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13726 12:30:24.470681 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13727 12:30:24.470785 arm64_za-ptrace_Set_VL_4224 pass
13728 12:30:24.470873 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13729 12:30:24.470956 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13730 12:30:24.471055 arm64_za-ptrace_Set_VL_4240 pass
13731 12:30:24.475358 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13732 12:30:24.475585 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13733 12:30:24.475887 arm64_za-ptrace_Set_VL_4256 pass
13734 12:30:24.476023 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13735 12:30:24.476113 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13736 12:30:24.476197 arm64_za-ptrace_Set_VL_4272 pass
13737 12:30:24.476300 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13738 12:30:24.476386 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13739 12:30:24.476471 arm64_za-ptrace_Set_VL_4288 pass
13740 12:30:24.476553 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13741 12:30:24.476637 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13742 12:30:24.476725 arm64_za-ptrace_Set_VL_4304 pass
13743 12:30:24.476832 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13744 12:30:24.476919 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13745 12:30:24.477005 arm64_za-ptrace_Set_VL_4320 pass
13746 12:30:24.477089 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13747 12:30:24.477172 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13748 12:30:24.477273 arm64_za-ptrace_Set_VL_4336 pass
13749 12:30:24.477359 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13750 12:30:24.477444 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13751 12:30:24.477529 arm64_za-ptrace_Set_VL_4352 pass
13752 12:30:24.477629 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13753 12:30:24.477746 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13754 12:30:24.477838 arm64_za-ptrace_Set_VL_4368 pass
13755 12:30:24.477939 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13756 12:30:24.478026 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13757 12:30:24.478111 arm64_za-ptrace_Set_VL_4384 pass
13758 12:30:24.478213 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13759 12:30:24.478300 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13760 12:30:24.478385 arm64_za-ptrace_Set_VL_4400 pass
13761 12:30:24.478481 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13762 12:30:24.478981 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13763 12:30:24.479086 arm64_za-ptrace_Set_VL_4416 pass
13764 12:30:24.479176 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13765 12:30:24.479261 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13766 12:30:24.479346 arm64_za-ptrace_Set_VL_4432 pass
13767 12:30:24.479428 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13768 12:30:24.483315 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13769 12:30:24.483497 arm64_za-ptrace_Set_VL_4448 pass
13770 12:30:24.483853 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13771 12:30:24.483957 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13772 12:30:24.484045 arm64_za-ptrace_Set_VL_4464 pass
13773 12:30:24.484131 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13774 12:30:24.484217 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13775 12:30:24.484321 arm64_za-ptrace_Set_VL_4480 pass
13776 12:30:24.484408 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13777 12:30:24.484492 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13778 12:30:24.484575 arm64_za-ptrace_Set_VL_4496 pass
13779 12:30:24.484662 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13780 12:30:24.484748 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13781 12:30:24.484855 arm64_za-ptrace_Set_VL_4512 pass
13782 12:30:24.484942 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13783 12:30:24.485028 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13784 12:30:24.485113 arm64_za-ptrace_Set_VL_4528 pass
13785 12:30:24.485196 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13786 12:30:24.485281 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13787 12:30:24.485388 arm64_za-ptrace_Set_VL_4544 pass
13788 12:30:24.485476 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13789 12:30:24.485561 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13790 12:30:24.485659 arm64_za-ptrace_Set_VL_4560 pass
13791 12:30:24.485748 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13792 12:30:24.485851 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13793 12:30:24.485939 arm64_za-ptrace_Set_VL_4576 pass
13794 12:30:24.486024 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13795 12:30:24.486108 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13796 12:30:24.486192 arm64_za-ptrace_Set_VL_4592 pass
13797 12:30:24.486496 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13798 12:30:24.486598 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13799 12:30:24.486686 arm64_za-ptrace_Set_VL_4608 pass
13800 12:30:24.486772 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13801 12:30:24.486854 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13802 12:30:24.486952 arm64_za-ptrace_Set_VL_4624 pass
13803 12:30:24.509192 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13804 12:30:24.509427 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13805 12:30:24.509518 arm64_za-ptrace_Set_VL_4640 pass
13806 12:30:24.509622 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13807 12:30:24.509732 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13808 12:30:24.509819 arm64_za-ptrace_Set_VL_4656 pass
13809 12:30:24.509913 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13810 12:30:24.510000 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13811 12:30:24.510102 arm64_za-ptrace_Set_VL_4672 pass
13812 12:30:24.510189 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13813 12:30:24.510273 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13814 12:30:24.510357 arm64_za-ptrace_Set_VL_4688 pass
13815 12:30:24.510454 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13816 12:30:24.510541 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13817 12:30:24.510638 arm64_za-ptrace_Set_VL_4704 pass
13818 12:30:24.510720 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13819 12:30:24.510953 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13820 12:30:24.511083 arm64_za-ptrace_Set_VL_4720 pass
13821 12:30:24.511186 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13822 12:30:24.511270 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13823 12:30:24.511668 arm64_za-ptrace_Set_VL_4736 pass
13824 12:30:24.511818 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13825 12:30:24.511958 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13826 12:30:24.512044 arm64_za-ptrace_Set_VL_4752 pass
13827 12:30:24.512126 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13828 12:30:24.512255 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13829 12:30:24.512347 arm64_za-ptrace_Set_VL_4768 pass
13830 12:30:24.512503 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13831 12:30:24.512635 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13832 12:30:24.512734 arm64_za-ptrace_Set_VL_4784 pass
13833 12:30:24.512819 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13834 12:30:24.512906 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13835 12:30:24.512989 arm64_za-ptrace_Set_VL_4800 pass
13836 12:30:24.513094 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13837 12:30:24.513180 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13838 12:30:24.513264 arm64_za-ptrace_Set_VL_4816 pass
13839 12:30:24.513344 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13840 12:30:24.513427 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13841 12:30:24.513507 arm64_za-ptrace_Set_VL_4832 pass
13842 12:30:24.513587 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13843 12:30:24.513701 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13844 12:30:24.513789 arm64_za-ptrace_Set_VL_4848 pass
13845 12:30:24.513876 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13846 12:30:24.513960 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13847 12:30:24.514043 arm64_za-ptrace_Set_VL_4864 pass
13848 12:30:24.514143 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13849 12:30:24.514228 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13850 12:30:24.514312 arm64_za-ptrace_Set_VL_4880 pass
13851 12:30:24.514395 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13852 12:30:24.514495 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13853 12:30:24.514581 arm64_za-ptrace_Set_VL_4896 pass
13854 12:30:24.514665 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13855 12:30:24.514954 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13856 12:30:24.515047 arm64_za-ptrace_Set_VL_4912 pass
13857 12:30:24.515133 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13858 12:30:24.515219 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13859 12:30:24.515302 arm64_za-ptrace_Set_VL_4928 pass
13860 12:30:24.515384 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13861 12:30:24.519467 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13862 12:30:24.519665 arm64_za-ptrace_Set_VL_4944 pass
13863 12:30:24.519752 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13864 12:30:24.520035 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13865 12:30:24.520136 arm64_za-ptrace_Set_VL_4960 pass
13866 12:30:24.520221 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13867 12:30:24.520304 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13868 12:30:24.520390 arm64_za-ptrace_Set_VL_4976 pass
13869 12:30:24.520471 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13870 12:30:24.520570 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13871 12:30:24.520673 arm64_za-ptrace_Set_VL_4992 pass
13872 12:30:24.520759 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13873 12:30:24.520861 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13874 12:30:24.520945 arm64_za-ptrace_Set_VL_5008 pass
13875 12:30:24.521029 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13876 12:30:24.521117 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13877 12:30:24.521204 arm64_za-ptrace_Set_VL_5024 pass
13878 12:30:24.521305 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13879 12:30:24.521390 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13880 12:30:24.521473 arm64_za-ptrace_Set_VL_5040 pass
13881 12:30:24.521558 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13882 12:30:24.521672 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13883 12:30:24.521763 arm64_za-ptrace_Set_VL_5056 pass
13884 12:30:24.521848 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13885 12:30:24.521932 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13886 12:30:24.522031 arm64_za-ptrace_Set_VL_5072 pass
13887 12:30:24.522119 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13888 12:30:24.522223 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13889 12:30:24.522308 arm64_za-ptrace_Set_VL_5088 pass
13890 12:30:24.522413 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13891 12:30:24.522501 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13892 12:30:24.522600 arm64_za-ptrace_Set_VL_5104 pass
13893 12:30:24.522690 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13894 12:30:24.522788 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13895 12:30:24.522887 arm64_za-ptrace_Set_VL_5120 pass
13896 12:30:24.522986 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13897 12:30:24.527197 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13898 12:30:24.527423 arm64_za-ptrace_Set_VL_5136 pass
13899 12:30:24.527885 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13900 12:30:24.528081 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13901 12:30:24.528168 arm64_za-ptrace_Set_VL_5152 pass
13902 12:30:24.528270 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13903 12:30:24.528567 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13904 12:30:24.528672 arm64_za-ptrace_Set_VL_5168 pass
13905 12:30:24.528762 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13906 12:30:24.528855 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13907 12:30:24.528944 arm64_za-ptrace_Set_VL_5184 pass
13908 12:30:24.529030 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13909 12:30:24.529113 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13910 12:30:24.529216 arm64_za-ptrace_Set_VL_5200 pass
13911 12:30:24.529304 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13912 12:30:24.529392 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13913 12:30:24.529481 arm64_za-ptrace_Set_VL_5216 pass
13914 12:30:24.529571 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13915 12:30:24.529665 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13916 12:30:24.529768 arm64_za-ptrace_Set_VL_5232 pass
13917 12:30:24.529855 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13918 12:30:24.529948 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13919 12:30:24.530035 arm64_za-ptrace_Set_VL_5248 pass
13920 12:30:24.530120 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13921 12:30:24.530225 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13922 12:30:24.530312 arm64_za-ptrace_Set_VL_5264 pass
13923 12:30:24.530399 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13924 12:30:24.530484 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13925 12:30:24.530570 arm64_za-ptrace_Set_VL_5280 pass
13926 12:30:24.530674 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13927 12:30:24.530776 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13928 12:30:24.530865 arm64_za-ptrace_Set_VL_5296 pass
13929 12:30:24.530950 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13930 12:30:24.531055 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13931 12:30:24.531141 arm64_za-ptrace_Set_VL_5312 pass
13932 12:30:24.535234 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13933 12:30:24.535673 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13934 12:30:24.535777 arm64_za-ptrace_Set_VL_5328 pass
13935 12:30:24.535862 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13936 12:30:24.535947 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13937 12:30:24.536029 arm64_za-ptrace_Set_VL_5344 pass
13938 12:30:24.536125 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13939 12:30:24.536212 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13940 12:30:24.536298 arm64_za-ptrace_Set_VL_5360 pass
13941 12:30:24.536401 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13942 12:30:24.536491 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13943 12:30:24.536575 arm64_za-ptrace_Set_VL_5376 pass
13944 12:30:24.536675 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13945 12:30:24.536762 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13946 12:30:24.536848 arm64_za-ptrace_Set_VL_5392 pass
13947 12:30:24.536951 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13948 12:30:24.537040 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13949 12:30:24.537141 arm64_za-ptrace_Set_VL_5408 pass
13950 12:30:24.537239 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13951 12:30:24.537617 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13952 12:30:24.537719 arm64_za-ptrace_Set_VL_5424 pass
13953 12:30:24.537803 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13954 12:30:24.537902 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13955 12:30:24.537984 arm64_za-ptrace_Set_VL_5440 pass
13956 12:30:24.541902 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13957 12:30:24.542113 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13958 12:30:24.542204 arm64_za-ptrace_Set_VL_5456 pass
13959 12:30:24.542293 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13960 12:30:24.542381 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13961 12:30:24.542468 arm64_za-ptrace_Set_VL_5472 pass
13962 12:30:24.542555 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13963 12:30:24.542643 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13964 12:30:24.542731 arm64_za-ptrace_Set_VL_5488 pass
13965 12:30:24.542816 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13966 12:30:24.543141 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13967 12:30:24.543234 arm64_za-ptrace_Set_VL_5504 pass
13968 12:30:24.543538 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13969 12:30:24.543695 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13970 12:30:24.543788 arm64_za-ptrace_Set_VL_5520 pass
13971 12:30:24.544067 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13972 12:30:24.544172 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13973 12:30:24.544260 arm64_za-ptrace_Set_VL_5536 pass
13974 12:30:24.544345 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13975 12:30:24.544453 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13976 12:30:24.544544 arm64_za-ptrace_Set_VL_5552 pass
13977 12:30:24.544629 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13978 12:30:24.544718 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13979 12:30:24.544803 arm64_za-ptrace_Set_VL_5568 pass
13980 12:30:24.544890 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
13981 12:30:24.544979 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
13982 12:30:24.545086 arm64_za-ptrace_Set_VL_5584 pass
13983 12:30:24.545176 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
13984 12:30:24.545262 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
13985 12:30:24.545351 arm64_za-ptrace_Set_VL_5600 pass
13986 12:30:24.545437 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
13987 12:30:24.545521 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
13988 12:30:24.545626 arm64_za-ptrace_Set_VL_5616 pass
13989 12:30:24.545724 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
13990 12:30:24.545809 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
13991 12:30:24.545893 arm64_za-ptrace_Set_VL_5632 pass
13992 12:30:24.545975 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
13993 12:30:24.546070 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
13994 12:30:24.546155 arm64_za-ptrace_Set_VL_5648 pass
13995 12:30:24.565506 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
13996 12:30:24.565734 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
13997 12:30:24.566058 arm64_za-ptrace_Set_VL_5664 pass
13998 12:30:24.566161 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
13999 12:30:24.566249 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14000 12:30:24.566338 arm64_za-ptrace_Set_VL_5680 pass
14001 12:30:24.566426 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14002 12:30:24.566509 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14003 12:30:24.566608 arm64_za-ptrace_Set_VL_5696 pass
14004 12:30:24.566893 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14005 12:30:24.566993 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14006 12:30:24.567079 arm64_za-ptrace_Set_VL_5712 pass
14007 12:30:24.567165 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14008 12:30:24.567251 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14009 12:30:24.567337 arm64_za-ptrace_Set_VL_5728 pass
14010 12:30:24.567418 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14011 12:30:24.567500 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14012 12:30:24.567583 arm64_za-ptrace_Set_VL_5744 pass
14013 12:30:24.567666 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14014 12:30:24.567766 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14015 12:30:24.567852 arm64_za-ptrace_Set_VL_5760 pass
14016 12:30:24.568143 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14017 12:30:24.568250 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14018 12:30:24.568336 arm64_za-ptrace_Set_VL_5776 pass
14019 12:30:24.568437 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14020 12:30:24.568523 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14021 12:30:24.569272 arm64_za-ptrace_Set_VL_5792 pass
14022 12:30:24.569382 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14023 12:30:24.569474 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14024 12:30:24.569560 arm64_za-ptrace_Set_VL_5808 pass
14025 12:30:24.569731 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14026 12:30:24.569844 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14027 12:30:24.569953 arm64_za-ptrace_Set_VL_5824 pass
14028 12:30:24.570046 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14029 12:30:24.570131 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14030 12:30:24.570215 arm64_za-ptrace_Set_VL_5840 pass
14031 12:30:24.570313 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14032 12:30:24.570400 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14033 12:30:24.570484 arm64_za-ptrace_Set_VL_5856 pass
14034 12:30:24.570568 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14035 12:30:24.570669 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14036 12:30:24.570757 arm64_za-ptrace_Set_VL_5872 pass
14037 12:30:24.570841 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14038 12:30:24.570942 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14039 12:30:24.571029 arm64_za-ptrace_Set_VL_5888 pass
14040 12:30:24.575183 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14041 12:30:24.575640 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14042 12:30:24.575747 arm64_za-ptrace_Set_VL_5904 pass
14043 12:30:24.575833 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14044 12:30:24.575918 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14045 12:30:24.576008 arm64_za-ptrace_Set_VL_5920 pass
14046 12:30:24.576113 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14047 12:30:24.576205 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14048 12:30:24.576289 arm64_za-ptrace_Set_VL_5936 pass
14049 12:30:24.576372 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14050 12:30:24.576456 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14051 12:30:24.576539 arm64_za-ptrace_Set_VL_5952 pass
14052 12:30:24.576622 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14053 12:30:24.576723 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14054 12:30:24.576808 arm64_za-ptrace_Set_VL_5968 pass
14055 12:30:24.576893 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14056 12:30:24.576976 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14057 12:30:24.577057 arm64_za-ptrace_Set_VL_5984 pass
14058 12:30:24.577138 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14059 12:30:24.577236 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14060 12:30:24.577321 arm64_za-ptrace_Set_VL_6000 pass
14061 12:30:24.577404 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14062 12:30:24.577489 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14063 12:30:24.577573 arm64_za-ptrace_Set_VL_6016 pass
14064 12:30:24.577683 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14065 12:30:24.577771 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14066 12:30:24.577855 arm64_za-ptrace_Set_VL_6032 pass
14067 12:30:24.577938 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14068 12:30:24.578037 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14069 12:30:24.578122 arm64_za-ptrace_Set_VL_6048 pass
14070 12:30:24.578204 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14071 12:30:24.578299 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14072 12:30:24.578382 arm64_za-ptrace_Set_VL_6064 pass
14073 12:30:24.578463 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14074 12:30:24.578562 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14075 12:30:24.578649 arm64_za-ptrace_Set_VL_6080 pass
14076 12:30:24.578733 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14077 12:30:24.578832 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14078 12:30:24.578920 arm64_za-ptrace_Set_VL_6096 pass
14079 12:30:24.579007 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14080 12:30:24.579116 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14081 12:30:24.579749 arm64_za-ptrace_Set_VL_6112 pass
14082 12:30:24.583107 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14083 12:30:24.583513 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14084 12:30:24.583621 arm64_za-ptrace_Set_VL_6128 pass
14085 12:30:24.583705 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14086 12:30:24.583786 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14087 12:30:24.583888 arm64_za-ptrace_Set_VL_6144 pass
14088 12:30:24.583973 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14089 12:30:24.584061 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14090 12:30:24.584145 arm64_za-ptrace_Set_VL_6160 pass
14091 12:30:24.584243 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14092 12:30:24.584329 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14093 12:30:24.584412 arm64_za-ptrace_Set_VL_6176 pass
14094 12:30:24.584511 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14095 12:30:24.584597 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14096 12:30:24.584696 arm64_za-ptrace_Set_VL_6192 pass
14097 12:30:24.584795 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14098 12:30:24.584895 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14099 12:30:24.584982 arm64_za-ptrace_Set_VL_6208 pass
14100 12:30:24.585082 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14101 12:30:24.585169 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14102 12:30:24.585633 arm64_za-ptrace_Set_VL_6224 pass
14103 12:30:24.585753 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14104 12:30:24.585842 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14105 12:30:24.585926 arm64_za-ptrace_Set_VL_6240 pass
14106 12:30:24.586015 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14107 12:30:24.586115 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14108 12:30:24.586202 arm64_za-ptrace_Set_VL_6256 pass
14109 12:30:24.586286 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14110 12:30:24.586369 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14111 12:30:24.586453 arm64_za-ptrace_Set_VL_6272 pass
14112 12:30:24.586794 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14113 12:30:24.586899 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14114 12:30:24.586986 arm64_za-ptrace_Set_VL_6288 pass
14115 12:30:24.587074 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14116 12:30:24.587157 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14117 12:30:24.587439 arm64_za-ptrace_Set_VL_6304 pass
14118 12:30:24.587544 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14119 12:30:24.587631 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14120 12:30:24.587713 arm64_za-ptrace_Set_VL_6320 pass
14121 12:30:24.591335 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14122 12:30:24.591538 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14123 12:30:24.591631 arm64_za-ptrace_Set_VL_6336 pass
14124 12:30:24.591732 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14125 12:30:24.591816 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14126 12:30:24.591900 arm64_za-ptrace_Set_VL_6352 pass
14127 12:30:24.591999 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14128 12:30:24.592086 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14129 12:30:24.592191 arm64_za-ptrace_Set_VL_6368 pass
14130 12:30:24.592279 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14131 12:30:24.592380 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14132 12:30:24.592471 arm64_za-ptrace_Set_VL_6384 pass
14133 12:30:24.592573 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14134 12:30:24.592677 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14135 12:30:24.592778 arm64_za-ptrace_Set_VL_6400 pass
14136 12:30:24.592880 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14137 12:30:24.592983 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14138 12:30:24.593090 arm64_za-ptrace_Set_VL_6416 pass
14139 12:30:24.593385 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14140 12:30:24.593477 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14141 12:30:24.593579 arm64_za-ptrace_Set_VL_6432 pass
14142 12:30:24.593892 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14143 12:30:24.593981 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14144 12:30:24.594086 arm64_za-ptrace_Set_VL_6448 pass
14145 12:30:24.594173 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14146 12:30:24.594256 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14147 12:30:24.594339 arm64_za-ptrace_Set_VL_6464 pass
14148 12:30:24.594422 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14149 12:30:24.594522 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14150 12:30:24.594607 arm64_za-ptrace_Set_VL_6480 pass
14151 12:30:24.594690 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14152 12:30:24.594774 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14153 12:30:24.594874 arm64_za-ptrace_Set_VL_6496 pass
14154 12:30:24.594959 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14155 12:30:24.595047 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14156 12:30:24.595130 arm64_za-ptrace_Set_VL_6512 pass
14157 12:30:24.599129 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14158 12:30:24.599571 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14159 12:30:24.599674 arm64_za-ptrace_Set_VL_6528 pass
14160 12:30:24.599758 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14161 12:30:24.599840 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14162 12:30:24.599920 arm64_za-ptrace_Set_VL_6544 pass
14163 12:30:24.600023 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14164 12:30:24.600111 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14165 12:30:24.600198 arm64_za-ptrace_Set_VL_6560 pass
14166 12:30:24.600280 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14167 12:30:24.600384 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14168 12:30:24.600471 arm64_za-ptrace_Set_VL_6576 pass
14169 12:30:24.600554 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14170 12:30:24.600637 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14171 12:30:24.600737 arm64_za-ptrace_Set_VL_6592 pass
14172 12:30:24.600824 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14173 12:30:24.600910 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14174 12:30:24.601013 arm64_za-ptrace_Set_VL_6608 pass
14175 12:30:24.601100 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14176 12:30:24.601186 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14177 12:30:24.601284 arm64_za-ptrace_Set_VL_6624 pass
14178 12:30:24.601366 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14179 12:30:24.601465 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14180 12:30:24.601548 arm64_za-ptrace_Set_VL_6640 pass
14181 12:30:24.601644 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14182 12:30:24.601757 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14183 12:30:24.601843 arm64_za-ptrace_Set_VL_6656 pass
14184 12:30:24.601942 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14185 12:30:24.602044 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14186 12:30:24.602156 arm64_za-ptrace_Set_VL_6672 pass
14187 12:30:24.602482 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14188 12:30:24.622001 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14189 12:30:24.622233 arm64_za-ptrace_Set_VL_6688 pass
14190 12:30:24.622345 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14191 12:30:24.622431 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14192 12:30:24.622517 arm64_za-ptrace_Set_VL_6704 pass
14193 12:30:24.622601 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14194 12:30:24.622702 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14195 12:30:24.622787 arm64_za-ptrace_Set_VL_6720 pass
14196 12:30:24.622870 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14197 12:30:24.622969 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14198 12:30:24.623061 arm64_za-ptrace_Set_VL_6736 pass
14199 12:30:24.623159 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14200 12:30:24.623242 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14201 12:30:24.623340 arm64_za-ptrace_Set_VL_6752 pass
14202 12:30:24.623440 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14203 12:30:24.623538 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14204 12:30:24.623990 arm64_za-ptrace_Set_VL_6768 pass
14205 12:30:24.624084 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14206 12:30:24.624169 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14207 12:30:24.624253 arm64_za-ptrace_Set_VL_6784 pass
14208 12:30:24.624351 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14209 12:30:24.624440 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14210 12:30:24.624539 arm64_za-ptrace_Set_VL_6800 pass
14211 12:30:24.624625 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14212 12:30:24.624725 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14213 12:30:24.624813 arm64_za-ptrace_Set_VL_6816 pass
14214 12:30:24.624900 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14215 12:30:24.624980 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14216 12:30:24.625079 arm64_za-ptrace_Set_VL_6832 pass
14217 12:30:24.625166 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14218 12:30:24.625252 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14219 12:30:24.625353 arm64_za-ptrace_Set_VL_6848 pass
14220 12:30:24.625439 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14221 12:30:24.625538 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14222 12:30:24.625624 arm64_za-ptrace_Set_VL_6864 pass
14223 12:30:24.625730 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14224 12:30:24.625827 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14225 12:30:24.625914 arm64_za-ptrace_Set_VL_6880 pass
14226 12:30:24.626012 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14227 12:30:24.626116 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14228 12:30:24.626220 arm64_za-ptrace_Set_VL_6896 pass
14229 12:30:24.626323 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14230 12:30:24.626425 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14231 12:30:24.626719 arm64_za-ptrace_Set_VL_6912 pass
14232 12:30:24.626812 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14233 12:30:24.626897 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14234 12:30:24.626998 arm64_za-ptrace_Set_VL_6928 pass
14235 12:30:24.627089 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14236 12:30:24.631191 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14237 12:30:24.631621 arm64_za-ptrace_Set_VL_6944 pass
14238 12:30:24.631735 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14239 12:30:24.631826 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14240 12:30:24.631921 arm64_za-ptrace_Set_VL_6960 pass
14241 12:30:24.632006 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14242 12:30:24.632112 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14243 12:30:24.632201 arm64_za-ptrace_Set_VL_6976 pass
14244 12:30:24.632286 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14245 12:30:24.632375 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14246 12:30:24.632480 arm64_za-ptrace_Set_VL_6992 pass
14247 12:30:24.632572 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14248 12:30:24.632664 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14249 12:30:24.632771 arm64_za-ptrace_Set_VL_7008 pass
14250 12:30:24.632861 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14251 12:30:24.632952 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14252 12:30:24.633057 arm64_za-ptrace_Set_VL_7024 pass
14253 12:30:24.633144 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14254 12:30:24.633255 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14255 12:30:24.633345 arm64_za-ptrace_Set_VL_7040 pass
14256 12:30:24.633447 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14257 12:30:24.633534 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14258 12:30:24.633634 arm64_za-ptrace_Set_VL_7056 pass
14259 12:30:24.633746 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14260 12:30:24.633848 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14261 12:30:24.634148 arm64_za-ptrace_Set_VL_7072 pass
14262 12:30:24.634243 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14263 12:30:24.634330 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14264 12:30:24.634436 arm64_za-ptrace_Set_VL_7088 pass
14265 12:30:24.634522 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14266 12:30:24.634609 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14267 12:30:24.634712 arm64_za-ptrace_Set_VL_7104 pass
14268 12:30:24.634803 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14269 12:30:24.634909 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14270 12:30:24.635000 arm64_za-ptrace_Set_VL_7120 pass
14271 12:30:24.639170 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14272 12:30:24.639611 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14273 12:30:24.639714 arm64_za-ptrace_Set_VL_7136 pass
14274 12:30:24.639799 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14275 12:30:24.639881 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14276 12:30:24.639964 arm64_za-ptrace_Set_VL_7152 pass
14277 12:30:24.640063 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14278 12:30:24.640147 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14279 12:30:24.640242 arm64_za-ptrace_Set_VL_7168 pass
14280 12:30:24.640342 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14281 12:30:24.640430 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14282 12:30:24.640516 arm64_za-ptrace_Set_VL_7184 pass
14283 12:30:24.640604 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14284 12:30:24.640706 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14285 12:30:24.640796 arm64_za-ptrace_Set_VL_7200 pass
14286 12:30:24.640883 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14287 12:30:24.640982 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14288 12:30:24.641071 arm64_za-ptrace_Set_VL_7216 pass
14289 12:30:24.641176 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14290 12:30:24.641260 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14291 12:30:24.641352 arm64_za-ptrace_Set_VL_7232 pass
14292 12:30:24.641444 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14293 12:30:24.641752 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14294 12:30:24.641859 arm64_za-ptrace_Set_VL_7248 pass
14295 12:30:24.641963 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14296 12:30:24.642052 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14297 12:30:24.642161 arm64_za-ptrace_Set_VL_7264 pass
14298 12:30:24.642249 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14299 12:30:24.642350 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14300 12:30:24.642451 arm64_za-ptrace_Set_VL_7280 pass
14301 12:30:24.642637 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14302 12:30:24.642728 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14303 12:30:24.642831 arm64_za-ptrace_Set_VL_7296 pass
14304 12:30:24.642920 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14305 12:30:24.647298 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14306 12:30:24.647584 arm64_za-ptrace_Set_VL_7312 pass
14307 12:30:24.647677 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14308 12:30:24.647975 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14309 12:30:24.648084 arm64_za-ptrace_Set_VL_7328 pass
14310 12:30:24.648173 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14311 12:30:24.648268 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14312 12:30:24.648354 arm64_za-ptrace_Set_VL_7344 pass
14313 12:30:24.648459 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14314 12:30:24.648548 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14315 12:30:24.648634 arm64_za-ptrace_Set_VL_7360 pass
14316 12:30:24.648719 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14317 12:30:24.648823 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14318 12:30:24.648912 arm64_za-ptrace_Set_VL_7376 pass
14319 12:30:24.648999 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14320 12:30:24.649101 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14321 12:30:24.649191 arm64_za-ptrace_Set_VL_7392 pass
14322 12:30:24.649276 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14323 12:30:24.649378 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14324 12:30:24.649467 arm64_za-ptrace_Set_VL_7408 pass
14325 12:30:24.649551 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14326 12:30:24.649662 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14327 12:30:24.649753 arm64_za-ptrace_Set_VL_7424 pass
14328 12:30:24.649839 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14329 12:30:24.649940 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14330 12:30:24.650028 arm64_za-ptrace_Set_VL_7440 pass
14331 12:30:24.650114 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14332 12:30:24.650219 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14333 12:30:24.650308 arm64_za-ptrace_Set_VL_7456 pass
14334 12:30:24.650393 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14335 12:30:24.650493 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14336 12:30:24.650581 arm64_za-ptrace_Set_VL_7472 pass
14337 12:30:24.650678 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14338 12:30:24.650974 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14339 12:30:24.651069 arm64_za-ptrace_Set_VL_7488 pass
14340 12:30:24.655223 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14341 12:30:24.655622 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14342 12:30:24.655735 arm64_za-ptrace_Set_VL_7504 pass
14343 12:30:24.655832 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14344 12:30:24.655923 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14345 12:30:24.656030 arm64_za-ptrace_Set_VL_7520 pass
14346 12:30:24.656123 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14347 12:30:24.656218 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14348 12:30:24.656306 arm64_za-ptrace_Set_VL_7536 pass
14349 12:30:24.656412 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14350 12:30:24.656506 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14351 12:30:24.656614 arm64_za-ptrace_Set_VL_7552 pass
14352 12:30:24.656706 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14353 12:30:24.656796 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14354 12:30:24.656900 arm64_za-ptrace_Set_VL_7568 pass
14355 12:30:24.656993 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14356 12:30:24.657083 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14357 12:30:24.657190 arm64_za-ptrace_Set_VL_7584 pass
14358 12:30:24.657281 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14359 12:30:24.657390 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14360 12:30:24.657479 arm64_za-ptrace_Set_VL_7600 pass
14361 12:30:24.657565 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14362 12:30:24.657681 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14363 12:30:24.657771 arm64_za-ptrace_Set_VL_7616 pass
14364 12:30:24.657870 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14365 12:30:24.657956 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14366 12:30:24.658057 arm64_za-ptrace_Set_VL_7632 pass
14367 12:30:24.658144 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14368 12:30:24.658248 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14369 12:30:24.658335 arm64_za-ptrace_Set_VL_7648 pass
14370 12:30:24.658438 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14371 12:30:24.658528 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14372 12:30:24.658631 arm64_za-ptrace_Set_VL_7664 pass
14373 12:30:24.658734 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14374 12:30:24.658823 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14375 12:30:24.658911 arm64_za-ptrace_Set_VL_7680 pass
14376 12:30:24.659014 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14377 12:30:24.663300 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14378 12:30:24.663548 arm64_za-ptrace_Set_VL_7696 pass
14379 12:30:24.663644 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14380 12:30:24.689830 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14381 12:30:24.690289 arm64_za-ptrace_Set_VL_7712 pass
14382 12:30:24.690391 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14383 12:30:24.690481 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14384 12:30:24.690569 arm64_za-ptrace_Set_VL_7728 pass
14385 12:30:24.690657 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14386 12:30:24.690762 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14387 12:30:24.690849 arm64_za-ptrace_Set_VL_7744 pass
14388 12:30:24.690936 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14389 12:30:24.691022 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14390 12:30:24.691121 arm64_za-ptrace_Set_VL_7760 pass
14391 12:30:24.691220 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14392 12:30:24.691324 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14393 12:30:24.691427 arm64_za-ptrace_Set_VL_7776 pass
14394 12:30:24.691512 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14395 12:30:24.691612 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14396 12:30:24.691713 arm64_za-ptrace_Set_VL_7792 pass
14397 12:30:24.691851 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14398 12:30:24.691975 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14399 12:30:24.692086 arm64_za-ptrace_Set_VL_7808 pass
14400 12:30:24.692398 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14401 12:30:24.692505 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14402 12:30:24.692616 arm64_za-ptrace_Set_VL_7824 pass
14403 12:30:24.692702 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14404 12:30:24.692804 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14405 12:30:24.692909 arm64_za-ptrace_Set_VL_7840 pass
14406 12:30:24.692997 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14407 12:30:24.693096 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14408 12:30:24.693188 arm64_za-ptrace_Set_VL_7856 pass
14409 12:30:24.693286 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14410 12:30:24.693370 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14411 12:30:24.693465 arm64_za-ptrace_Set_VL_7872 pass
14412 12:30:24.693560 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14413 12:30:24.693867 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14414 12:30:24.693970 arm64_za-ptrace_Set_VL_7888 pass
14415 12:30:24.694075 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14416 12:30:24.694168 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14417 12:30:24.694274 arm64_za-ptrace_Set_VL_7904 pass
14418 12:30:24.694365 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14419 12:30:24.694464 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14420 12:30:24.694567 arm64_za-ptrace_Set_VL_7920 pass
14421 12:30:24.694657 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14422 12:30:24.694755 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14423 12:30:24.694854 arm64_za-ptrace_Set_VL_7936 pass
14424 12:30:24.694956 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14425 12:30:24.699129 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14426 12:30:24.699529 arm64_za-ptrace_Set_VL_7952 pass
14427 12:30:24.699633 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14428 12:30:24.699722 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14429 12:30:24.699821 arm64_za-ptrace_Set_VL_7968 pass
14430 12:30:24.699907 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14431 12:30:24.699992 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14432 12:30:24.700095 arm64_za-ptrace_Set_VL_7984 pass
14433 12:30:24.700182 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14434 12:30:24.700283 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14435 12:30:24.700369 arm64_za-ptrace_Set_VL_8000 pass
14436 12:30:24.700467 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14437 12:30:24.700553 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14438 12:30:24.700654 arm64_za-ptrace_Set_VL_8016 pass
14439 12:30:24.700756 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14440 12:30:24.700843 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14441 12:30:24.700945 arm64_za-ptrace_Set_VL_8032 pass
14442 12:30:24.701033 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14443 12:30:24.701134 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14444 12:30:24.701223 arm64_za-ptrace_Set_VL_8048 pass
14445 12:30:24.701328 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14446 12:30:24.701433 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14447 12:30:24.701518 arm64_za-ptrace_Set_VL_8064 pass
14448 12:30:24.701619 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14449 12:30:24.701717 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14450 12:30:24.701817 arm64_za-ptrace_Set_VL_8080 pass
14451 12:30:24.701912 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14452 12:30:24.702011 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14453 12:30:24.702112 arm64_za-ptrace_Set_VL_8096 pass
14454 12:30:24.702411 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14455 12:30:24.702518 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14456 12:30:24.702624 arm64_za-ptrace_Set_VL_8112 pass
14457 12:30:24.702718 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14458 12:30:24.702825 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14459 12:30:24.702915 arm64_za-ptrace_Set_VL_8128 pass
14460 12:30:24.703004 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14461 12:30:24.707143 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14462 12:30:24.707571 arm64_za-ptrace_Set_VL_8144 pass
14463 12:30:24.707956 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14464 12:30:24.708064 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14465 12:30:24.708155 arm64_za-ptrace_Set_VL_8160 pass
14466 12:30:24.708244 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14467 12:30:24.708330 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14468 12:30:24.708416 arm64_za-ptrace_Set_VL_8176 pass
14469 12:30:24.708501 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14470 12:30:24.708782 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14471 12:30:24.708877 arm64_za-ptrace_Set_VL_8192 pass
14472 12:30:24.708962 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14473 12:30:24.709047 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14474 12:30:24.709133 arm64_za-ptrace pass
14475 12:30:24.709218 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14476 12:30:24.709326 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14477 12:30:24.709414 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14478 12:30:24.709505 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14479 12:30:24.709609 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14480 12:30:24.709761 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14481 12:30:24.710067 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14482 12:30:24.710186 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14483 12:30:24.710495 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14484 12:30:24.710812 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14485 12:30:24.711129 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14486 12:30:24.715116 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14487 12:30:24.715531 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14488 12:30:24.715639 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14489 12:30:24.715931 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14490 12:30:24.716226 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14491 12:30:24.716335 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14492 12:30:24.716615 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14493 12:30:24.716942 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14494 12:30:24.717039 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14495 12:30:24.717316 arm64_check_buffer_fill fail
14496 12:30:24.717604 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14497 12:30:24.717711 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14498 12:30:24.718178 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14499 12:30:24.718839 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14500 12:30:24.718942 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14501 12:30:24.719030 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14502 12:30:24.719307 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14503 12:30:24.719402 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14504 12:30:24.723155 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14505 12:30:24.723612 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14506 12:30:24.723722 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14507 12:30:24.723834 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14508 12:30:24.723940 arm64_check_child_memory fail
14509 12:30:24.724240 arm64_check_gcr_el1_cswitch fail
14510 12:30:24.724341 arm64_check_ksm_options fail
14511 12:30:24.724457 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14512 12:30:24.724938 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14513 12:30:24.725053 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14514 12:30:24.725348 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14515 12:30:24.725681 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14516 12:30:24.733504 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14517 12:30:24.733978 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14518 12:30:24.734286 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14519 12:30:24.734578 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14520 12:30:24.734875 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14521 12:30:24.735167 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14522 12:30:24.735464 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14523 12:30:24.735775 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14524 12:30:24.736278 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14525 12:30:24.736588 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14526 12:30:24.736897 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14527 12:30:24.737223 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14528 12:30:24.737350 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14529 12:30:24.737857 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14530 12:30:24.737977 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14531 12:30:24.738464 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14532 12:30:24.738583 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14533 12:30:24.738687 arm64_check_mmap_options fail
14534 12:30:24.738791 arm64_check_prctl_check_basic_read pass
14535 12:30:24.738875 arm64_check_prctl_NONE pass
14536 12:30:24.738971 arm64_check_prctl_SYNC pass
14537 12:30:24.743123 arm64_check_prctl_ASYNC pass
14538 12:30:24.743569 arm64_check_prctl_SYNC_ASYNC pass
14539 12:30:24.743670 arm64_check_prctl pass
14540 12:30:24.743761 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14541 12:30:24.743867 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14542 12:30:24.743956 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14543 12:30:24.744052 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14544 12:30:24.744154 arm64_check_tags_inclusion fail
14545 12:30:24.744461 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14546 12:30:24.744579 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14547 12:30:24.745055 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14548 12:30:24.745170 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14549 12:30:24.745467 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14550 12:30:24.745580 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14551 12:30:24.745882 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14552 12:30:24.746213 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14553 12:30:24.746347 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14554 12:30:24.746457 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14555 12:30:24.746745 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14556 12:30:24.747048 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14557 12:30:24.751096 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14558 12:30:24.751512 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14559 12:30:24.751647 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14560 12:30:24.751973 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14561 12:30:24.752079 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14562 12:30:24.752495 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14563 12:30:24.752605 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14564 12:30:24.752716 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14565 12:30:24.752808 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14566 12:30:24.752914 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14567 12:30:24.753335 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14568 12:30:24.753640 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14569 12:30:24.753752 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14570 12:30:24.753854 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14571 12:30:24.753956 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14572 12:30:24.754310 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14573 12:30:24.754438 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14574 12:30:24.754564 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14575 12:30:24.754886 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14576 12:30:24.755003 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14577 12:30:24.755108 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14578 12:30:24.759302 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14579 12:30:24.759750 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14580 12:30:24.759859 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14581 12:30:24.759948 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14582 12:30:24.760051 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14583 12:30:24.760140 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14584 12:30:24.760442 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14585 12:30:24.760564 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14586 12:30:24.760864 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14587 12:30:24.760979 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14588 12:30:24.761276 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14589 12:30:24.761620 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14590 12:30:24.761748 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14591 12:30:24.762051 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14592 12:30:24.762170 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14593 12:30:24.762468 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14594 12:30:24.765736 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14595 12:30:24.765983 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14596 12:30:24.771166 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14597 12:30:24.771625 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14598 12:30:24.771878 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14599 12:30:24.772073 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14600 12:30:24.772284 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14601 12:30:24.772636 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14602 12:30:24.774296 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14603 12:30:24.774501 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14604 12:30:24.774886 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14605 12:30:24.775085 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14606 12:30:24.779239 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14607 12:30:24.791519 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14608 12:30:24.791928 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14609 12:30:24.792031 arm64_check_user_mem pass
14610 12:30:24.792121 arm64_btitest_nohint_func_call_using_br_x0 pass
14611 12:30:24.792226 arm64_btitest_nohint_func_call_using_br_x16 pass
14612 12:30:24.793835 arm64_btitest_nohint_func_call_using_blr pass
14613 12:30:24.794050 arm64_btitest_bti_none_func_call_using_br_x0 pass
14614 12:30:24.794241 arm64_btitest_bti_none_func_call_using_br_x16 pass
14615 12:30:24.794402 arm64_btitest_bti_none_func_call_using_blr pass
14616 12:30:24.794581 arm64_btitest_bti_c_func_call_using_br_x0 pass
14617 12:30:24.794759 arm64_btitest_bti_c_func_call_using_br_x16 pass
14618 12:30:24.794947 arm64_btitest_bti_c_func_call_using_blr pass
14619 12:30:24.795123 arm64_btitest_bti_j_func_call_using_br_x0 pass
14620 12:30:24.795286 arm64_btitest_bti_j_func_call_using_br_x16 pass
14621 12:30:24.795464 arm64_btitest_bti_j_func_call_using_blr pass
14622 12:30:24.795649 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14623 12:30:24.795826 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14624 12:30:24.796011 arm64_btitest_bti_jc_func_call_using_blr pass
14625 12:30:24.796186 arm64_btitest_paciasp_func_call_using_br_x0 pass
14626 12:30:24.796363 arm64_btitest_paciasp_func_call_using_br_x16 pass
14627 12:30:24.796539 arm64_btitest_paciasp_func_call_using_blr pass
14628 12:30:24.796713 arm64_btitest pass
14629 12:30:24.797138 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14630 12:30:24.797329 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14631 12:30:24.797510 arm64_nobtitest_nohint_func_call_using_blr pass
14632 12:30:24.797701 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14633 12:30:24.797875 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14634 12:30:24.798050 arm64_nobtitest_bti_none_func_call_using_blr pass
14635 12:30:24.798224 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14636 12:30:24.798403 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14637 12:30:24.798578 arm64_nobtitest_bti_c_func_call_using_blr pass
14638 12:30:24.798747 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14639 12:30:24.799175 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14640 12:30:24.799420 arm64_nobtitest_bti_j_func_call_using_blr pass
14641 12:30:24.799601 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14642 12:30:24.799789 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14643 12:30:24.799968 arm64_nobtitest_bti_jc_func_call_using_blr pass
14644 12:30:24.800144 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14645 12:30:24.800353 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14646 12:30:24.800527 arm64_nobtitest_paciasp_func_call_using_blr pass
14647 12:30:24.800703 arm64_nobtitest pass
14648 12:30:24.800878 arm64_hwcap_cpuinfo_match_RNG pass
14649 12:30:24.801052 arm64_hwcap_sigill_RNG pass
14650 12:30:24.801260 arm64_hwcap_cpuinfo_match_SME pass
14651 12:30:24.801438 arm64_hwcap_sigill_SME pass
14652 12:30:24.801612 arm64_hwcap_cpuinfo_match_SVE pass
14653 12:30:24.801803 arm64_hwcap_sigill_SVE pass
14654 12:30:24.801978 arm64_hwcap_cpuinfo_match_SVE_2 pass
14655 12:30:24.802149 arm64_hwcap_sigill_SVE_2 pass
14656 12:30:24.802323 arm64_hwcap_cpuinfo_match_SVE_AES pass
14657 12:30:24.802497 arm64_hwcap_sigill_SVE_AES pass
14658 12:30:24.802716 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14659 12:30:24.802895 arm64_hwcap_sigill_SVE2_PMULL pass
14660 12:30:24.803064 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14661 12:30:24.803238 arm64_hwcap_sigill_SVE2_BITPERM pass
14662 12:30:24.803415 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14663 12:30:24.803590 arm64_hwcap_sigill_SVE2_SHA3 pass
14664 12:30:24.803763 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14665 12:30:24.803931 arm64_hwcap_sigill_SVE2_SM4 pass
14666 12:30:24.804104 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14667 12:30:24.804277 arm64_hwcap_sigill_SVE2_I8MM pass
14668 12:30:24.804451 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14669 12:30:24.804625 arm64_hwcap_sigill_SVE2_F32MM pass
14670 12:30:24.804794 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14671 12:30:24.804968 arm64_hwcap_sigill_SVE2_F64MM pass
14672 12:30:24.805124 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14673 12:30:24.805294 arm64_hwcap_sigill_SVE2_BF16 pass
14674 12:30:24.805471 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14675 12:30:24.805642 arm64_hwcap_sigill_SVE2_EBF16 skip
14676 12:30:24.805812 arm64_hwcap pass
14677 12:30:24.805967 arm64_ptrace_read_tpidr_one pass
14678 12:30:24.806154 arm64_ptrace_write_tpidr_one pass
14679 12:30:24.806318 arm64_ptrace_verify_tpidr_one pass
14680 12:30:24.807182 arm64_ptrace_count_tpidrs pass
14681 12:30:24.807398 arm64_ptrace_tpidr2_write pass
14682 12:30:24.807843 arm64_ptrace_tpidr2_read pass
14683 12:30:24.808057 arm64_ptrace_write_tpidr_only pass
14684 12:30:24.808238 arm64_ptrace pass
14685 12:30:24.808414 arm64_syscall-abi_getpid_FPSIMD pass
14686 12:30:24.808589 arm64_syscall-abi_getpid_SVE_VL_256 pass
14687 12:30:24.808761 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14688 12:30:24.808972 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14689 12:30:24.809152 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14690 12:30:24.809327 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14691 12:30:24.809499 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14692 12:30:24.809687 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14693 12:30:24.809865 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14694 12:30:24.810040 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14695 12:30:24.810215 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14696 12:30:24.810384 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14697 12:30:24.810601 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14698 12:30:24.810782 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14699 12:30:24.810948 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14700 12:30:24.811116 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14701 12:30:24.811290 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14702 12:30:24.811464 arm64_syscall-abi_getpid_SVE_VL_240 pass
14703 12:30:24.811639 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14704 12:30:24.811814 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14705 12:30:24.811990 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14706 12:30:24.812162 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14707 12:30:24.812336 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14708 12:30:24.812514 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14709 12:30:24.812689 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14710 12:30:24.812900 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14711 12:30:24.813078 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14712 12:30:24.813254 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14713 12:30:24.815237 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14714 12:30:24.815649 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14715 12:30:24.815755 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14716 12:30:24.815850 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14717 12:30:24.815938 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14718 12:30:24.816041 arm64_syscall-abi_getpid_SVE_VL_224 pass
14719 12:30:24.816129 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14720 12:30:24.816229 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14721 12:30:24.816331 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14722 12:30:24.816431 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14723 12:30:24.816735 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14724 12:30:24.816836 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14725 12:30:24.816939 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14726 12:30:24.817041 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14727 12:30:24.817151 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14728 12:30:24.817255 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14729 12:30:24.817600 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14730 12:30:24.817913 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14731 12:30:24.818109 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14732 12:30:24.818289 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14733 12:30:24.818500 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14734 12:30:24.818682 arm64_syscall-abi_getpid_SVE_VL_208 pass
14735 12:30:24.818859 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14736 12:30:24.819029 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14737 12:30:24.819238 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14738 12:30:24.819420 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14739 12:30:24.819595 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14740 12:30:24.819765 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14741 12:30:24.819940 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14742 12:30:24.823184 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14743 12:30:24.823657 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14744 12:30:24.823855 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14745 12:30:24.824037 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14746 12:30:24.824247 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14747 12:30:24.824430 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14748 12:30:24.824595 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14749 12:30:24.824754 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14750 12:30:24.824927 arm64_syscall-abi_getpid_SVE_VL_192 pass
14751 12:30:24.825139 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14752 12:30:24.825319 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14753 12:30:24.825489 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14754 12:30:24.825678 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14755 12:30:24.825855 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14756 12:30:24.826029 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14757 12:30:24.826201 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14758 12:30:24.826376 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14759 12:30:24.826591 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14760 12:30:24.826772 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14761 12:30:24.826946 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14762 12:30:24.827119 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14763 12:30:24.827295 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14764 12:30:24.827471 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14765 12:30:24.827650 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14766 12:30:24.827821 arm64_syscall-abi_getpid_SVE_VL_176 pass
14767 12:30:24.827997 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14768 12:30:24.828171 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14769 12:30:24.828346 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14770 12:30:24.828560 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14771 12:30:24.828735 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14772 12:30:24.828907 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14773 12:30:24.831322 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14774 12:30:24.831546 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14775 12:30:24.831734 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14776 12:30:24.832148 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14777 12:30:24.842221 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14778 12:30:24.842457 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14779 12:30:24.842679 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14780 12:30:24.842866 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14781 12:30:24.843049 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14782 12:30:24.843231 arm64_syscall-abi_getpid_SVE_VL_160 pass
14783 12:30:24.843451 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14784 12:30:24.843639 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14785 12:30:24.843822 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14786 12:30:24.844002 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14787 12:30:24.844184 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14788 12:30:24.844402 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14789 12:30:24.844590 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14790 12:30:24.844772 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14791 12:30:24.844953 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14792 12:30:24.845133 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14793 12:30:24.845315 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14794 12:30:24.845499 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14795 12:30:24.845815 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14796 12:30:24.846028 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14797 12:30:24.846212 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14798 12:30:24.846397 arm64_syscall-abi_getpid_SVE_VL_144 pass
14799 12:30:24.846547 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14800 12:30:24.846685 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14801 12:30:24.846821 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14802 12:30:24.846957 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14803 12:30:24.847095 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14804 12:30:24.847233 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14805 12:30:24.847369 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14806 12:30:24.847498 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14807 12:30:24.847662 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14808 12:30:24.847804 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14809 12:30:24.847942 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14810 12:30:24.848079 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14811 12:30:24.848215 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14812 12:30:24.848351 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14813 12:30:24.848705 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14814 12:30:24.848849 arm64_syscall-abi_getpid_SVE_VL_128 pass
14815 12:30:24.848987 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14816 12:30:24.851252 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14817 12:30:24.851367 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14818 12:30:24.851651 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14819 12:30:24.851741 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14820 12:30:24.851822 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14821 12:30:24.851914 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14822 12:30:24.851994 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14823 12:30:24.852087 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14824 12:30:24.852181 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14825 12:30:24.852262 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14826 12:30:24.852541 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14827 12:30:24.852627 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14828 12:30:24.852706 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14829 12:30:24.852795 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14830 12:30:24.852871 arm64_syscall-abi_getpid_SVE_VL_112 pass
14831 12:30:24.852960 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14832 12:30:24.853049 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14833 12:30:24.853138 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14834 12:30:24.853247 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14835 12:30:24.853341 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14836 12:30:24.853449 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14837 12:30:24.853559 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14838 12:30:24.853963 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14839 12:30:24.854184 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14840 12:30:24.854360 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14841 12:30:24.854552 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14842 12:30:24.854695 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14843 12:30:24.854836 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14844 12:30:24.855019 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14845 12:30:24.855226 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14846 12:30:24.855366 arm64_syscall-abi_getpid_SVE_VL_96 pass
14847 12:30:24.855487 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14848 12:30:24.859168 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14849 12:30:24.859627 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14850 12:30:24.859824 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14851 12:30:24.860116 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14852 12:30:24.860301 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14853 12:30:24.860446 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14854 12:30:24.860604 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14855 12:30:24.860800 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14856 12:30:24.860984 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14857 12:30:24.861198 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14858 12:30:24.861390 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14859 12:30:24.861574 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14860 12:30:24.861808 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14861 12:30:24.862013 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14862 12:30:24.862177 arm64_syscall-abi_getpid_SVE_VL_80 pass
14863 12:30:24.862338 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14864 12:30:24.862521 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14865 12:30:24.862665 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14866 12:30:24.862804 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14867 12:30:24.862966 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14868 12:30:24.863131 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14869 12:30:24.863310 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14870 12:30:24.863514 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14871 12:30:24.863665 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14872 12:30:24.863788 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14873 12:30:24.863942 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14874 12:30:24.864087 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14875 12:30:24.864206 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14876 12:30:24.864321 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14877 12:30:24.864434 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14878 12:30:24.864551 arm64_syscall-abi_getpid_SVE_VL_64 pass
14879 12:30:24.864665 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14880 12:30:24.864779 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14881 12:30:24.864893 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14882 12:30:24.865007 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14883 12:30:24.865121 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14884 12:30:24.865235 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14885 12:30:24.865588 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14886 12:30:24.865777 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14887 12:30:24.865902 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14888 12:30:24.866019 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14889 12:30:24.866136 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14890 12:30:24.866251 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14891 12:30:24.866368 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14892 12:30:24.866480 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14893 12:30:24.866573 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14894 12:30:24.866661 arm64_syscall-abi_getpid_SVE_VL_48 pass
14895 12:30:24.866750 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14896 12:30:24.866842 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14897 12:30:24.866943 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14898 12:30:24.867035 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14899 12:30:24.867123 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14900 12:30:24.867212 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14901 12:30:24.867299 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14902 12:30:24.867387 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14903 12:30:24.867476 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14904 12:30:24.875155 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14905 12:30:24.875267 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14906 12:30:24.875510 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14907 12:30:24.875620 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14908 12:30:24.875723 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14909 12:30:24.875846 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14910 12:30:24.875930 arm64_syscall-abi_getpid_SVE_VL_32 pass
14911 12:30:24.876031 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14912 12:30:24.876139 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14913 12:30:24.876212 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14914 12:30:24.876289 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14915 12:30:24.876367 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14916 12:30:24.876461 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14917 12:30:24.876558 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14918 12:30:24.876679 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14919 12:30:24.876797 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14920 12:30:24.876900 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14921 12:30:24.876989 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14922 12:30:24.877305 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14923 12:30:24.877407 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14924 12:30:24.877513 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14925 12:30:24.877641 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14926 12:30:24.877740 arm64_syscall-abi_getpid_SVE_VL_16 pass
14927 12:30:24.877830 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14928 12:30:24.877924 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14929 12:30:24.890032 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14930 12:30:24.890188 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14931 12:30:24.890527 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14932 12:30:24.890629 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14933 12:30:24.890730 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14934 12:30:24.890820 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14935 12:30:24.891082 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14936 12:30:24.891188 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14937 12:30:24.891281 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14938 12:30:24.891388 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14939 12:30:24.891479 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14940 12:30:24.891586 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14941 12:30:24.891675 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14942 12:30:24.891777 arm64_syscall-abi_sched_yield_FPSIMD pass
14943 12:30:24.891879 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14944 12:30:24.891982 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14945 12:30:24.892294 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14946 12:30:24.892414 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14947 12:30:24.892521 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14948 12:30:24.892635 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14949 12:30:24.892938 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14950 12:30:24.893044 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14951 12:30:24.893149 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14952 12:30:24.893262 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14953 12:30:24.893775 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14954 12:30:24.893881 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14955 12:30:24.893970 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14956 12:30:24.894070 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14957 12:30:24.894157 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14958 12:30:24.894257 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14959 12:30:24.894357 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14960 12:30:24.894661 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14961 12:30:24.894779 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14962 12:30:24.894887 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14963 12:30:24.895188 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14964 12:30:24.899140 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14965 12:30:24.899430 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14966 12:30:24.899521 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14967 12:30:24.899621 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14968 12:30:24.899717 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14969 12:30:24.899986 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14970 12:30:24.900098 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14971 12:30:24.900196 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14972 12:30:24.900278 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14973 12:30:24.900347 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14974 12:30:24.900426 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14975 12:30:24.900490 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14976 12:30:24.900567 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14977 12:30:24.900632 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14978 12:30:24.900708 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14979 12:30:24.900790 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14980 12:30:24.901066 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
14981 12:30:24.901346 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
14982 12:30:24.901434 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
14983 12:30:24.901514 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
14984 12:30:24.901595 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
14985 12:30:24.901724 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
14986 12:30:24.901809 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
14987 12:30:24.901904 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
14988 12:30:24.901988 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
14989 12:30:24.902074 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
14990 12:30:24.902152 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
14991 12:30:24.902425 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
14992 12:30:24.902522 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
14993 12:30:24.902621 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
14994 12:30:24.902920 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
14995 12:30:24.903015 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
14996 12:30:24.903132 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
14997 12:30:24.907215 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
14998 12:30:24.907314 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
14999 12:30:24.907703 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15000 12:30:24.907916 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15001 12:30:24.908106 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15002 12:30:24.908283 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15003 12:30:24.908490 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15004 12:30:24.908624 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15005 12:30:24.908765 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15006 12:30:24.908985 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15007 12:30:24.909183 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15008 12:30:24.909331 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15009 12:30:24.909529 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15010 12:30:24.909722 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15011 12:30:24.909924 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15012 12:30:24.910112 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15013 12:30:24.910278 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15014 12:30:24.910441 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15015 12:30:24.910604 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15016 12:30:24.910765 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15017 12:30:24.910952 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15018 12:30:24.911079 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15019 12:30:24.911196 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15020 12:30:24.911311 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15021 12:30:24.911427 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15022 12:30:24.911541 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15023 12:30:24.911658 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15024 12:30:24.911774 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15025 12:30:24.911888 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15026 12:30:24.912003 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15027 12:30:24.912116 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15028 12:30:24.915205 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15029 12:30:24.915313 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15030 12:30:24.915627 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15031 12:30:24.915714 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15032 12:30:24.915778 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15033 12:30:24.915872 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15034 12:30:24.915949 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15035 12:30:24.916037 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15036 12:30:24.916131 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15037 12:30:24.916221 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15038 12:30:24.916311 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15039 12:30:24.916407 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15040 12:30:24.916744 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15041 12:30:24.917055 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15042 12:30:24.917159 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15043 12:30:24.917247 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15044 12:30:24.917334 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15045 12:30:24.917437 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15046 12:30:24.917524 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15047 12:30:24.917626 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15048 12:30:24.917739 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15049 12:30:24.917842 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15050 12:30:24.918143 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15051 12:30:24.918267 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15052 12:30:24.918379 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15053 12:30:24.918489 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15054 12:30:24.918789 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15055 12:30:24.918936 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15056 12:30:24.919251 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15057 12:30:24.923328 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15058 12:30:24.923540 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15059 12:30:24.923749 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15060 12:30:24.923941 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15061 12:30:24.924166 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15062 12:30:24.924369 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15063 12:30:24.924585 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15064 12:30:24.924779 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15065 12:30:24.924944 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15066 12:30:24.925100 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15067 12:30:24.925255 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15068 12:30:24.925375 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15069 12:30:24.937246 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15070 12:30:24.937480 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15071 12:30:24.937994 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15072 12:30:24.938217 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15073 12:30:24.938414 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15074 12:30:24.938620 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15075 12:30:24.938830 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15076 12:30:24.939061 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15077 12:30:24.939259 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15078 12:30:24.939457 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15079 12:30:24.939654 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15080 12:30:24.939896 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15081 12:30:24.940102 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15082 12:30:24.940281 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15083 12:30:24.940446 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15084 12:30:24.940613 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15085 12:30:24.940768 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15086 12:30:24.940915 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15087 12:30:24.941056 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15088 12:30:24.941244 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15089 12:30:24.941390 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15090 12:30:24.941511 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15091 12:30:24.941644 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15092 12:30:24.942283 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15093 12:30:24.942434 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15094 12:30:24.942609 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15095 12:30:24.942780 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15096 12:30:24.942927 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15097 12:30:24.943061 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15098 12:30:24.943179 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15099 12:30:24.943293 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15100 12:30:24.943409 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15101 12:30:24.943523 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15102 12:30:24.943636 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15103 12:30:24.943752 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15104 12:30:24.944099 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15105 12:30:24.944278 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15106 12:30:24.944414 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15107 12:30:24.944533 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15108 12:30:24.944653 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15109 12:30:24.944770 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15110 12:30:24.944887 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15111 12:30:24.947230 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15112 12:30:24.947343 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15113 12:30:24.947661 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15114 12:30:24.947767 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15115 12:30:24.947860 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15116 12:30:24.948154 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15117 12:30:24.948259 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15118 12:30:24.948347 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15119 12:30:24.948447 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15120 12:30:24.948535 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15121 12:30:24.948637 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15122 12:30:24.948935 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15123 12:30:24.949055 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15124 12:30:24.949144 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15125 12:30:24.949242 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15126 12:30:24.949445 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15127 12:30:24.949811 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15128 12:30:24.950018 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15129 12:30:24.950228 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15130 12:30:24.950399 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15131 12:30:24.950566 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15132 12:30:24.950763 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15133 12:30:24.950925 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15134 12:30:24.951081 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15135 12:30:24.951227 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15136 12:30:24.951347 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15137 12:30:24.955159 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15138 12:30:24.955588 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15139 12:30:24.955701 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15140 12:30:24.955791 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15141 12:30:24.955893 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15142 12:30:24.955985 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15143 12:30:24.956087 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15144 12:30:24.956188 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15145 12:30:24.956492 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15146 12:30:24.956598 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15147 12:30:24.956700 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15148 12:30:24.956995 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15149 12:30:24.957099 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15150 12:30:24.957202 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15151 12:30:24.957304 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15152 12:30:24.957406 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15153 12:30:24.957693 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15154 12:30:24.957812 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15155 12:30:24.958114 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15156 12:30:24.958258 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15157 12:30:24.958380 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15158 12:30:24.958484 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15159 12:30:24.958588 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15160 12:30:24.958924 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15161 12:30:24.959109 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15162 12:30:24.963185 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15163 12:30:24.963643 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15164 12:30:24.963849 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15165 12:30:24.964012 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15166 12:30:24.964210 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15167 12:30:24.964389 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15168 12:30:24.964562 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15169 12:30:24.964737 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15170 12:30:24.964901 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15171 12:30:24.965155 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15172 12:30:24.965336 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15173 12:30:24.965518 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15174 12:30:24.965692 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15175 12:30:24.965850 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15176 12:30:24.966035 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15177 12:30:24.966323 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15178 12:30:24.966549 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15179 12:30:24.966769 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15180 12:30:24.966962 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15181 12:30:24.967111 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15182 12:30:24.967230 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15183 12:30:24.967345 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15184 12:30:24.967460 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15185 12:30:24.967588 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15186 12:30:24.967785 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15187 12:30:24.967915 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15188 12:30:24.968034 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15189 12:30:24.968151 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15190 12:30:24.971228 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15191 12:30:24.971439 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15192 12:30:24.971845 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15193 12:30:24.972023 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15194 12:30:24.972155 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15195 12:30:24.972274 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15196 12:30:24.972696 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15197 12:30:24.972860 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15198 12:30:24.972988 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15199 12:30:24.973108 arm64_syscall-abi pass
15200 12:30:24.973228 arm64_tpidr2_default_value pass
15201 12:30:24.973346 arm64_tpidr2_write_read pass
15202 12:30:24.973465 arm64_tpidr2_write_sleep_read pass
15203 12:30:24.973584 arm64_tpidr2_write_fork_read pass
15204 12:30:24.973757 arm64_tpidr2_write_clone_read pass
15205 12:30:24.973905 arm64_tpidr2 pass
15206 12:30:24.987473 + ../../utils/send-to-lava.sh ./output/result.txt
15207 12:30:25.032871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15208 12:30:25.033799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15210 12:30:25.067349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15212 12:30:25.067806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15213 12:30:25.101539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15214 12:30:25.101975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15216 12:30:25.134836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15217 12:30:25.135261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15219 12:30:25.168864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15220 12:30:25.169297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15222 12:30:25.202402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15223 12:30:25.202940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15225 12:30:25.236506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15227 12:30:25.237118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15228 12:30:25.270592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15230 12:30:25.271154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15231 12:30:25.304842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15233 12:30:25.305408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15234 12:30:25.338768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15236 12:30:25.339390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15237 12:30:25.373228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15238 12:30:25.373695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15240 12:30:25.407515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15242 12:30:25.408002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15243 12:30:25.442003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15245 12:30:25.442411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15246 12:30:25.476749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15248 12:30:25.477374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15249 12:30:25.512102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15250 12:30:25.512632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15252 12:30:25.547648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15253 12:30:25.548046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15255 12:30:25.580857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15257 12:30:25.581332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15258 12:30:25.614538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15259 12:30:25.614972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15261 12:30:25.651905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15263 12:30:25.652333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15264 12:30:25.700894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15266 12:30:25.701539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15267 12:30:25.741502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15269 12:30:25.741979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15270 12:30:25.778540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15272 12:30:25.779030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15273 12:30:25.818884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15274 12:30:25.819339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15276 12:30:25.867054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15277 12:30:25.867514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15279 12:30:25.915976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15280 12:30:25.916436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15282 12:30:25.961103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15284 12:30:25.961581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15285 12:30:26.016567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15287 12:30:26.017039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15288 12:30:26.054005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15289 12:30:26.054446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15291 12:30:26.090235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15292 12:30:26.090678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15294 12:30:26.140395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15295 12:30:26.140851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15297 12:30:26.190953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15299 12:30:26.191437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15300 12:30:26.237350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15301 12:30:26.237794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15303 12:30:26.275469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15305 12:30:26.275901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15306 12:30:26.310617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15307 12:30:26.311020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15309 12:30:26.352120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15311 12:30:26.352510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15312 12:30:26.396832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15313 12:30:26.397286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15315 12:30:26.441033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15316 12:30:26.441492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15318 12:30:26.478720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15319 12:30:26.479178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15321 12:30:26.514921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15323 12:30:26.515411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15324 12:30:26.559765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15325 12:30:26.560233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15327 12:30:26.599804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15329 12:30:26.600224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15330 12:30:26.634294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15332 12:30:26.634672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15333 12:30:26.669927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15335 12:30:26.670413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15336 12:30:26.705335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15337 12:30:26.705778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15339 12:30:26.750779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15340 12:30:26.751249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15342 12:30:26.798930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15344 12:30:26.799413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15345 12:30:26.851967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15346 12:30:26.852393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15348 12:30:26.896017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15349 12:30:26.896962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15351 12:30:26.942016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15353 12:30:26.942494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15354 12:30:26.985720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15356 12:30:26.986203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15357 12:30:27.026302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15358 12:30:27.026865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15360 12:30:27.063772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15361 12:30:27.064342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15363 12:30:27.109942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15364 12:30:27.110396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15366 12:30:27.157394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15367 12:30:27.157858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15369 12:30:27.193433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15370 12:30:27.193901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15372 12:30:27.243090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15374 12:30:27.243564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15375 12:30:27.299178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15377 12:30:27.299657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15378 12:30:27.338123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15379 12:30:27.338575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15381 12:30:27.376827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15383 12:30:27.377296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15384 12:30:27.413065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15385 12:30:27.413521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15387 12:30:27.449380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15388 12:30:27.449848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15390 12:30:27.492039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15392 12:30:27.492523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15393 12:30:27.545873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15394 12:30:27.546308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15396 12:30:27.584648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15397 12:30:27.585106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15399 12:30:27.622134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15400 12:30:27.622560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15402 12:30:27.666220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15403 12:30:27.666618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15405 12:30:27.716624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15406 12:30:27.717042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15408 12:30:27.773817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15409 12:30:27.774268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15411 12:30:27.831061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15413 12:30:27.831563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15414 12:30:27.876601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15415 12:30:27.877059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15417 12:30:27.922451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15418 12:30:27.922943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15420 12:30:27.965144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15421 12:30:27.965598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15423 12:30:28.017449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15425 12:30:28.017956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15426 12:30:28.072696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15427 12:30:28.073113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15429 12:30:28.129576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15430 12:30:28.130063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15432 12:30:28.185341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15433 12:30:28.185755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15435 12:30:28.241955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15437 12:30:28.242550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15438 12:30:28.299453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15440 12:30:28.300177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15441 12:30:28.353908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15443 12:30:28.354329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15444 12:30:28.411182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15446 12:30:28.411670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15447 12:30:28.466250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15449 12:30:28.466902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15450 12:30:28.521147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15452 12:30:28.521629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15453 12:30:28.576581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15455 12:30:28.577061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15456 12:30:28.613688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15457 12:30:28.614149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15459 12:30:28.664964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15461 12:30:28.665399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15462 12:30:28.715531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15464 12:30:28.716020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15465 12:30:28.769531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15467 12:30:28.770048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15468 12:30:28.811814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15470 12:30:28.812346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15471 12:30:28.849195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15472 12:30:28.849637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15474 12:30:28.890043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15475 12:30:28.890453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15477 12:30:28.937917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15478 12:30:28.938332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15480 12:30:28.972040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15481 12:30:28.972416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15483 12:30:29.005614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15484 12:30:29.006124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15486 12:30:29.039615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15487 12:30:29.040170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15489 12:30:29.074529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15491 12:30:29.075111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15492 12:30:29.108708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15493 12:30:29.109140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15495 12:30:29.143450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15497 12:30:29.143923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15498 12:30:29.177826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15499 12:30:29.178310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15501 12:30:29.213009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15502 12:30:29.213482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15504 12:30:29.246639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15505 12:30:29.247061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15507 12:30:29.280821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15508 12:30:29.281258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15510 12:30:29.315278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15512 12:30:29.315750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15513 12:30:29.349678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15515 12:30:29.350146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15516 12:30:29.383732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15518 12:30:29.384200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15519 12:30:29.417483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15521 12:30:29.417951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15522 12:30:29.453333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15523 12:30:29.453747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15525 12:30:29.488109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15527 12:30:29.488565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15528 12:30:29.521989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15529 12:30:29.522458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15531 12:30:29.556481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15532 12:30:29.556953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15534 12:30:29.590764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15535 12:30:29.591167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15537 12:30:29.628059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15538 12:30:29.628469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15540 12:30:29.661878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15542 12:30:29.662513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15543 12:30:29.696330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15544 12:30:29.696823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15546 12:30:29.730677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15548 12:30:29.731323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15549 12:30:29.765992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15551 12:30:29.766583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15552 12:30:29.800647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15554 12:30:29.801383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15555 12:30:29.834918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15557 12:30:29.835505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15558 12:30:29.869039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15559 12:30:29.869520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15561 12:30:29.904019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15562 12:30:29.904564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15564 12:30:29.938898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15565 12:30:29.939367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15567 12:30:29.975359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15569 12:30:29.975809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15570 12:30:30.013440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15571 12:30:30.013860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15573 12:30:30.066529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15574 12:30:30.066937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15576 12:30:30.114611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15577 12:30:30.115049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15579 12:30:30.160844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15580 12:30:30.161289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15582 12:30:30.219140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15584 12:30:30.219642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15585 12:30:30.270367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15587 12:30:30.270766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15588 12:30:30.306685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15589 12:30:30.307081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15591 12:30:30.349038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15592 12:30:30.349444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15594 12:30:30.401467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15595 12:30:30.401911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15597 12:30:30.442727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15599 12:30:30.443212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15600 12:30:30.492115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15602 12:30:30.492538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15603 12:30:30.538001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15604 12:30:30.538392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15606 12:30:30.584382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15607 12:30:30.584747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15609 12:30:30.623330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15611 12:30:30.623794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15612 12:30:30.660105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15613 12:30:30.660560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15615 12:30:30.697591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15616 12:30:30.698070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15618 12:30:30.733597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15619 12:30:30.734051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15621 12:30:30.786177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15622 12:30:30.786630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15624 12:30:30.832399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15626 12:30:30.832872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15627 12:30:30.870767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15628 12:30:30.871220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15630 12:30:30.911223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15632 12:30:30.911640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15633 12:30:30.950626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15634 12:30:30.951032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15636 12:30:30.989184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15637 12:30:30.989700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15639 12:30:31.029182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15640 12:30:31.029688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15642 12:30:31.072831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15644 12:30:31.073499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15645 12:30:31.118906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15646 12:30:31.119364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15648 12:30:31.158879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15649 12:30:31.159304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15651 12:30:31.198974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15652 12:30:31.199397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15654 12:30:31.253211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15655 12:30:31.253677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15657 12:30:31.296827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15658 12:30:31.297262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15660 12:30:31.337764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15662 12:30:31.338214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15663 12:30:31.389593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15664 12:30:31.390062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15666 12:30:31.429487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15668 12:30:31.429971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15669 12:30:31.473733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15670 12:30:31.474195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15672 12:30:31.521607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15673 12:30:31.522075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15675 12:30:31.566270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15676 12:30:31.566707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15678 12:30:31.612388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15679 12:30:31.612827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15681 12:30:31.658933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15682 12:30:31.659484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15684 12:30:31.701989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15685 12:30:31.702394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15687 12:30:31.741024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15689 12:30:31.741489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15690 12:30:31.782465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15692 12:30:31.782925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15693 12:30:31.823326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15695 12:30:31.823924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15696 12:30:31.862101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15698 12:30:31.862567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15699 12:30:31.905939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15700 12:30:31.906344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15702 12:30:31.945860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15703 12:30:31.946287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15705 12:30:31.999013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15706 12:30:31.999449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15708 12:30:32.042987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15709 12:30:32.043442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15711 12:30:32.086904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15712 12:30:32.087334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15714 12:30:32.128943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15715 12:30:32.129300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15717 12:30:32.172607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15718 12:30:32.173004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15720 12:30:32.217699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15721 12:30:32.218088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15723 12:30:32.264421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15725 12:30:32.264902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15726 12:30:32.309099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15728 12:30:32.309539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15729 12:30:32.352487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15730 12:30:32.352920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15732 12:30:32.390901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15734 12:30:32.391413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15735 12:30:32.432441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15736 12:30:32.432898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15738 12:30:32.469335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15739 12:30:32.469838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15741 12:30:32.507342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15743 12:30:32.507796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15744 12:30:32.548342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15745 12:30:32.548837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15747 12:30:32.588594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15748 12:30:32.589067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15750 12:30:32.627502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15752 12:30:32.627977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15753 12:30:32.670538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15754 12:30:32.671041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15756 12:30:32.710785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15757 12:30:32.711349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15759 12:30:32.751011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15760 12:30:32.751448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15762 12:30:32.794348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15764 12:30:32.794844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15765 12:30:32.845530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15766 12:30:32.845977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15768 12:30:32.892239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15770 12:30:32.892626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15771 12:30:32.941204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15772 12:30:32.941691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15774 12:30:32.978835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15775 12:30:32.979322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15777 12:30:33.018519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15778 12:30:33.018957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15780 12:30:33.065411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15781 12:30:33.065862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15783 12:30:33.107980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15784 12:30:33.108497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15786 12:30:33.148685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15787 12:30:33.149145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15789 12:30:33.186362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15791 12:30:33.186831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15792 12:30:33.229268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15793 12:30:33.229719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15795 12:30:33.272076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15796 12:30:33.272507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15798 12:30:33.316819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15800 12:30:33.317532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15801 12:30:33.358017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15803 12:30:33.358514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15804 12:30:33.398568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15805 12:30:33.399019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15807 12:30:33.438957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15808 12:30:33.439398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15810 12:30:33.490498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15811 12:30:33.490932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15813 12:30:33.541862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15815 12:30:33.542459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15816 12:30:33.592770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15818 12:30:33.593488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15819 12:30:33.646206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15821 12:30:33.646969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15822 12:30:33.696380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15824 12:30:33.696888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15825 12:30:33.741305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15826 12:30:33.741775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15828 12:30:33.790508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15829 12:30:33.790909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15831 12:30:33.835062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15832 12:30:33.835526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15834 12:30:33.877972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15835 12:30:33.878421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15837 12:30:33.918051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15838 12:30:33.918473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15840 12:30:33.958724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15842 12:30:33.959193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15843 12:30:34.006151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15845 12:30:34.006781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15846 12:30:34.066975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15847 12:30:34.067381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15849 12:30:34.121243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15850 12:30:34.121720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15852 12:30:34.165890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15853 12:30:34.166367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15855 12:30:34.218564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15857 12:30:34.218995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15858 12:30:34.271970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15859 12:30:34.272406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15861 12:30:34.325731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15863 12:30:34.326237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15864 12:30:34.375998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15865 12:30:34.376377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15867 12:30:34.430745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15869 12:30:34.431197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15870 12:30:34.478993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15871 12:30:34.479402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15873 12:30:34.531480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15875 12:30:34.531979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15876 12:30:34.589393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15878 12:30:34.589825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15879 12:30:34.644825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15880 12:30:34.645476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15882 12:30:34.705421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15884 12:30:34.705842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15885 12:30:34.766546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15886 12:30:34.766954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15888 12:30:34.826545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15889 12:30:34.826996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15891 12:30:34.880472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15893 12:30:34.880969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15894 12:30:34.942415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15895 12:30:34.942804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15897 12:30:35.001176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15898 12:30:35.001624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15900 12:30:35.055416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15902 12:30:35.055861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15903 12:30:35.093961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15904 12:30:35.094372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15906 12:30:35.135382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15908 12:30:35.135841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15909 12:30:35.188567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15911 12:30:35.189377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15912 12:30:35.230228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15913 12:30:35.230688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15915 12:30:35.272369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15917 12:30:35.273143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15918 12:30:35.320712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15919 12:30:35.321162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15921 12:30:35.364258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15922 12:30:35.364716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15924 12:30:35.406964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15925 12:30:35.407417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15927 12:30:35.450865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15929 12:30:35.451353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15930 12:30:35.490973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15932 12:30:35.491459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15933 12:30:35.540693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15935 12:30:35.541120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15936 12:30:35.582635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15938 12:30:35.583120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15939 12:30:35.627593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15941 12:30:35.628364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15942 12:30:35.673183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15944 12:30:35.673656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15945 12:30:35.714278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15946 12:30:35.714702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15948 12:30:35.762951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15950 12:30:35.763441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15951 12:30:35.803954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15952 12:30:35.804383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15954 12:30:35.846450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15956 12:30:35.847113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15957 12:30:35.889524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15958 12:30:35.889989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15960 12:30:35.933793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15961 12:30:35.934200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15963 12:30:35.981990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15964 12:30:35.982419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15966 12:30:36.042565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15967 12:30:36.042993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15969 12:30:36.089328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15971 12:30:36.089834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15972 12:30:36.134697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15974 12:30:36.135187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15975 12:30:36.180661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15976 12:30:36.181093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15978 12:30:36.222561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15979 12:30:36.223000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
15981 12:30:36.266267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
15982 12:30:36.266709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
15984 12:30:36.304967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
15986 12:30:36.305449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
15987 12:30:36.344988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
15988 12:30:36.345414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
15990 12:30:36.387129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
15992 12:30:36.387620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
15993 12:30:36.428298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
15994 12:30:36.428870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
15996 12:30:36.470626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
15997 12:30:36.471085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
15999 12:30:36.514362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16000 12:30:36.514796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16002 12:30:36.557566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16003 12:30:36.558017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16005 12:30:36.598781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16007 12:30:36.599284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16008 12:30:36.640624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16010 12:30:36.641095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16011 12:30:36.681599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16012 12:30:36.682050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16014 12:30:36.732291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16015 12:30:36.732735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16017 12:30:36.793149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16018 12:30:36.793610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16020 12:30:36.848516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16021 12:30:36.848949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16023 12:30:36.889917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16025 12:30:36.890395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16026 12:30:36.940422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16027 12:30:36.940861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16029 12:30:36.985344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16030 12:30:36.985773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16032 12:30:37.027562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16034 12:30:37.028053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16035 12:30:37.066331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16037 12:30:37.066801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16038 12:30:37.112686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16039 12:30:37.113089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16041 12:30:37.161615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16043 12:30:37.162094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16044 12:30:37.212739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16045 12:30:37.213178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16047 12:30:37.254825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16049 12:30:37.255327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16050 12:30:37.306454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16051 12:30:37.306904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16053 12:30:37.360212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16054 12:30:37.360662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16056 12:30:37.419354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16058 12:30:37.419991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16059 12:30:37.467553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16061 12:30:37.468044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16062 12:30:37.515526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16064 12:30:37.516033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16065 12:30:37.572414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16066 12:30:37.572877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16068 12:30:37.630433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16069 12:30:37.630848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16071 12:30:37.673262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16072 12:30:37.673697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16074 12:30:37.716780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16075 12:30:37.717239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16077 12:30:37.760018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16079 12:30:37.760509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16080 12:30:37.802989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16081 12:30:37.803403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16083 12:30:37.846955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16084 12:30:37.847396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16086 12:30:37.894302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16087 12:30:37.894743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16089 12:30:37.949695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16090 12:30:37.950130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16092 12:30:37.994109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16094 12:30:37.994577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16095 12:30:38.054304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16096 12:30:38.054719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16098 12:30:38.108943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16099 12:30:38.109413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16101 12:30:38.153238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16102 12:30:38.153709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16104 12:30:38.197504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16106 12:30:38.197998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16107 12:30:38.237536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16109 12:30:38.238071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16110 12:30:38.282075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16111 12:30:38.282503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16113 12:30:38.324756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16114 12:30:38.325190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16116 12:30:38.366764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16117 12:30:38.367223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16119 12:30:38.411055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16121 12:30:38.411540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16122 12:30:38.451128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16124 12:30:38.451621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16125 12:30:38.499256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16127 12:30:38.499747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16128 12:30:38.549031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16129 12:30:38.549464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16131 12:30:38.605037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16132 12:30:38.605502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16134 12:30:38.650122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16136 12:30:38.650603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16137 12:30:38.692657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16138 12:30:38.693096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16140 12:30:38.752010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16141 12:30:38.752598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16143 12:30:38.800806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16144 12:30:38.801153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16146 12:30:38.841055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16147 12:30:38.841531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16149 12:30:38.881143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16151 12:30:38.881629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16152 12:30:38.924805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16153 12:30:38.925203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16155 12:30:38.969659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16156 12:30:38.970094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16158 12:30:39.016755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16160 12:30:39.017236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16161 12:30:39.062780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16163 12:30:39.063254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16164 12:30:39.109402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16166 12:30:39.110188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16167 12:30:39.150660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16168 12:30:39.151095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16170 12:30:39.195083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16172 12:30:39.195562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16173 12:30:39.239361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16175 12:30:39.239834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16176 12:30:39.281818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16177 12:30:39.282324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16179 12:30:39.321733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16180 12:30:39.322167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16182 12:30:39.360302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16183 12:30:39.360703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16185 12:30:39.398027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16187 12:30:39.398520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16188 12:30:39.436405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16189 12:30:39.436912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16191 12:30:39.476092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16193 12:30:39.476866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16194 12:30:39.516511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16195 12:30:39.516947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16197 12:30:39.557980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16198 12:30:39.558434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16200 12:30:39.597965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16202 12:30:39.598451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16203 12:30:39.637824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16204 12:30:39.638266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16206 12:30:39.679461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16208 12:30:39.679951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16209 12:30:39.725720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16210 12:30:39.726238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16212 12:30:39.774811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16213 12:30:39.775252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16215 12:30:39.834197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16216 12:30:39.834640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16218 12:30:39.881902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16219 12:30:39.882333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16221 12:30:39.922034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16222 12:30:39.922420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16224 12:30:39.968434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16226 12:30:39.968908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16227 12:30:40.010568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16228 12:30:40.010961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16230 12:30:40.070564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16232 12:30:40.070957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16233 12:30:40.124683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16234 12:30:40.125066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16236 12:30:40.166012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16237 12:30:40.166395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16239 12:30:40.205190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16240 12:30:40.205682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16242 12:30:40.244649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16243 12:30:40.245130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16245 12:30:40.285484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16247 12:30:40.286159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16248 12:30:40.330556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16250 12:30:40.331153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16251 12:30:40.373432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16252 12:30:40.373877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16254 12:30:40.417337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16255 12:30:40.417901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16257 12:30:40.457671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16258 12:30:40.458108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16260 12:30:40.504534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16261 12:30:40.504982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16263 12:30:40.549347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16265 12:30:40.549850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16266 12:30:40.592989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16267 12:30:40.593429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16269 12:30:40.638021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16270 12:30:40.638433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16272 12:30:40.680115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16274 12:30:40.680609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16275 12:30:40.722181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16276 12:30:40.722654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16278 12:30:40.769692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16279 12:30:40.770217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16281 12:30:40.815137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16282 12:30:40.815694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16284 12:30:40.857984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16285 12:30:40.858397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16287 12:30:40.900099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16288 12:30:40.900489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16290 12:30:40.939503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16292 12:30:40.939934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16293 12:30:40.980669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16294 12:30:40.981052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16296 12:30:41.020791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16297 12:30:41.021259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16299 12:30:41.060455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16301 12:30:41.060934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16302 12:30:41.099487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16304 12:30:41.099965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16305 12:30:41.140538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16306 12:30:41.140979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16308 12:30:41.185660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16309 12:30:41.186120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16311 12:30:41.234734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16312 12:30:41.235284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16314 12:30:41.284264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16316 12:30:41.284894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16317 12:30:41.333435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16318 12:30:41.333905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16320 12:30:41.371375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16322 12:30:41.371870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16323 12:30:41.409287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16324 12:30:41.409857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16326 12:30:41.448855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16327 12:30:41.449313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16329 12:30:41.495096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16330 12:30:41.495539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16332 12:30:41.541206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16334 12:30:41.541875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16335 12:30:41.582844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16337 12:30:41.583327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16338 12:30:41.625748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16339 12:30:41.626259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16341 12:30:41.665595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16343 12:30:41.666084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16344 12:30:41.714124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16345 12:30:41.714586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16347 12:30:41.760533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16349 12:30:41.761199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16350 12:30:41.809219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16352 12:30:41.809819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16353 12:30:41.856244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16354 12:30:41.856734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16356 12:30:41.902303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16357 12:30:41.902737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16359 12:30:41.950322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16361 12:30:41.950808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16362 12:30:42.000874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16363 12:30:42.001348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16365 12:30:42.049416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16366 12:30:42.049900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16368 12:30:42.097450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16369 12:30:42.097910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16371 12:30:42.151300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16373 12:30:42.151862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16374 12:30:42.202989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16375 12:30:42.203421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16377 12:30:42.246130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16378 12:30:42.246560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16380 12:30:42.290353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16381 12:30:42.290861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16383 12:30:42.341255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16384 12:30:42.341757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16386 12:30:42.382751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16387 12:30:42.383198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16389 12:30:42.422210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16390 12:30:42.422650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16392 12:30:42.462371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16394 12:30:42.462976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16395 12:30:42.501533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16396 12:30:42.502058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16398 12:30:42.543322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16400 12:30:42.543754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16401 12:30:42.589753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16402 12:30:42.590221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16404 12:30:42.634236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16406 12:30:42.634735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16407 12:30:42.681438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16408 12:30:42.681888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16410 12:30:42.741698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16412 12:30:42.742153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16413 12:30:42.788537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16414 12:30:42.788967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16416 12:30:42.840730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16418 12:30:42.841210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16419 12:30:42.884240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16420 12:30:42.884673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16422 12:30:42.926488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16423 12:30:42.926879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16425 12:30:42.969023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16426 12:30:42.969417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16428 12:30:43.012665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16429 12:30:43.013115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16431 12:30:43.052799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16432 12:30:43.053343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16434 12:30:43.093704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16435 12:30:43.094118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16437 12:30:43.134472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16439 12:30:43.134963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16440 12:30:43.178193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16441 12:30:43.178724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16443 12:30:43.220424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16445 12:30:43.221013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16446 12:30:43.262511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16447 12:30:43.262868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16449 12:30:43.302390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16451 12:30:43.302772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16452 12:30:43.340949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16454 12:30:43.341745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16455 12:30:43.382584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16456 12:30:43.383027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16458 12:30:43.438854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16460 12:30:43.439334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16461 12:30:43.481085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16462 12:30:43.481582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16464 12:30:43.520483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16466 12:30:43.520973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16467 12:30:43.559869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16468 12:30:43.560345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16470 12:30:43.601814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16471 12:30:43.602261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16473 12:30:43.641144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16475 12:30:43.641660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16476 12:30:43.679792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16477 12:30:43.680262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16479 12:30:43.719443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16481 12:30:43.719940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16482 12:30:43.760711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16483 12:30:43.761188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16485 12:30:43.805108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16487 12:30:43.805516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16488 12:30:43.849990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16489 12:30:43.850381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16491 12:30:43.909289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16492 12:30:43.909694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16494 12:30:43.957134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16495 12:30:43.957574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16497 12:30:43.999369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16499 12:30:43.999789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16500 12:30:44.042793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16501 12:30:44.043224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16503 12:30:44.092673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16505 12:30:44.093283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16506 12:30:44.138624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16508 12:30:44.139104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16509 12:30:44.184328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16510 12:30:44.184784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16512 12:30:44.228879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16513 12:30:44.229337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16515 12:30:44.273966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16516 12:30:44.274377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16518 12:30:44.318570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16519 12:30:44.318962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16521 12:30:44.376004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16522 12:30:44.376451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16524 12:30:44.418922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16526 12:30:44.419406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16527 12:30:44.461610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16529 12:30:44.462100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16530 12:30:44.504115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16531 12:30:44.504548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16533 12:30:44.545558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16535 12:30:44.546044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16536 12:30:44.597839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16537 12:30:44.598298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16539 12:30:44.640407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16540 12:30:44.640849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16542 12:30:44.702136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16544 12:30:44.702615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16545 12:30:44.758708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16546 12:30:44.759138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16548 12:30:44.817370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16549 12:30:44.817810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16551 12:30:44.879356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16553 12:30:44.879829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16554 12:30:44.934746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16556 12:30:44.935212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16557 12:30:44.986554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16558 12:30:44.986993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16560 12:30:45.036669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16561 12:30:45.037066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16563 12:30:45.092747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16565 12:30:45.093220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16566 12:30:45.152413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16567 12:30:45.152903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16569 12:30:45.210398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16570 12:30:45.210890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16572 12:30:45.266682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16573 12:30:45.267172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16575 12:30:45.324802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16577 12:30:45.325457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16578 12:30:45.381689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16580 12:30:45.382346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16581 12:30:45.429296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16582 12:30:45.429753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16584 12:30:45.469874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16586 12:30:45.470358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16587 12:30:45.510025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16588 12:30:45.510451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16590 12:30:45.550689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16591 12:30:45.551116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16593 12:30:45.591429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16595 12:30:45.591925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16596 12:30:45.631055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16598 12:30:45.631545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16599 12:30:45.673939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16601 12:30:45.674407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16602 12:30:45.717060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16603 12:30:45.717518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16605 12:30:45.758864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16607 12:30:45.759343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16608 12:30:45.799318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16610 12:30:45.799821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16611 12:30:45.841625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16613 12:30:45.842136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16614 12:30:45.883343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16616 12:30:45.883831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16617 12:30:45.932406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16619 12:30:45.932848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16620 12:30:45.973633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16622 12:30:45.974159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16623 12:30:46.013109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16624 12:30:46.013540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16626 12:30:46.070433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16627 12:30:46.070870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16629 12:30:46.130994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16630 12:30:46.131437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16632 12:30:46.180025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16633 12:30:46.180484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16635 12:30:46.213185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16637 12:30:46.213674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16638 12:30:46.247123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16640 12:30:46.247607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16641 12:30:46.284223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16642 12:30:46.284675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16644 12:30:46.320424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16645 12:30:46.320914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16647 12:30:46.354876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16648 12:30:46.355312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16650 12:30:46.396740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16651 12:30:46.397172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16653 12:30:46.447080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16655 12:30:46.447572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16656 12:30:46.506467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16658 12:30:46.506944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16659 12:30:46.566044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16661 12:30:46.566519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16662 12:30:46.626402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16664 12:30:46.627025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16665 12:30:46.674969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16666 12:30:46.675429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16668 12:30:46.735530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16670 12:30:46.736026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16671 12:30:46.792319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16672 12:30:46.792744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16674 12:30:46.837032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16675 12:30:46.837496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16677 12:30:46.889874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16679 12:30:46.890363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16680 12:30:46.941917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16682 12:30:46.942350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16683 12:30:46.985005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16685 12:30:46.985493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16686 12:30:47.028077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16688 12:30:47.028539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16689 12:30:47.089366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16690 12:30:47.089811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16692 12:30:47.149658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16694 12:30:47.150156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16695 12:30:47.200170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16696 12:30:47.200607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16698 12:30:47.245510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16700 12:30:47.246012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16701 12:30:47.307575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16703 12:30:47.308108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16704 12:30:47.359306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16706 12:30:47.359871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16707 12:30:47.418326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16708 12:30:47.418763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16710 12:30:47.465644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16712 12:30:47.466203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16713 12:30:47.523141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16714 12:30:47.523578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16716 12:30:47.577188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16718 12:30:47.577644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16719 12:30:47.626888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16721 12:30:47.627673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16722 12:30:47.682447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16723 12:30:47.682908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16725 12:30:47.733571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16726 12:30:47.734045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16728 12:30:47.779873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16729 12:30:47.780220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16731 12:30:47.838064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16732 12:30:47.838501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16734 12:30:47.882852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16735 12:30:47.883289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16737 12:30:47.927846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16738 12:30:47.928309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16740 12:30:47.969930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16742 12:30:47.970408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16743 12:30:48.014731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16744 12:30:48.015186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16746 12:30:48.057946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16748 12:30:48.058430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16749 12:30:48.101586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16750 12:30:48.102019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16752 12:30:48.144345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16754 12:30:48.145022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16755 12:30:48.182757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16756 12:30:48.183221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16758 12:30:48.224584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16759 12:30:48.225013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16761 12:30:48.265792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16762 12:30:48.266218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16764 12:30:48.306412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16765 12:30:48.306821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16767 12:30:48.346919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16768 12:30:48.347278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16770 12:30:48.393749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16772 12:30:48.394295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16773 12:30:48.445708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16774 12:30:48.446147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16776 12:30:48.508466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16777 12:30:48.508898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16779 12:30:48.549321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16780 12:30:48.549760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16782 12:30:48.597324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16783 12:30:48.597693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16785 12:30:48.656418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16787 12:30:48.656918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16788 12:30:48.695908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16789 12:30:48.696353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16791 12:30:48.744822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16792 12:30:48.745283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16794 12:30:48.796263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16795 12:30:48.796651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16797 12:30:48.837547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16798 12:30:48.838001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16800 12:30:48.896101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16801 12:30:48.896541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16803 12:30:48.945703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16804 12:30:48.946177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16806 12:30:48.991394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16808 12:30:48.991886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16809 12:30:49.053213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16810 12:30:49.053620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16812 12:30:49.117572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16814 12:30:49.118078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16815 12:30:49.178757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16816 12:30:49.179147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16818 12:30:49.241070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16819 12:30:49.241534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16821 12:30:49.299060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16822 12:30:49.299502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16824 12:30:49.340541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16825 12:30:49.340966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16827 12:30:49.380320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16828 12:30:49.380801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16830 12:30:49.420172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16831 12:30:49.420611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16833 12:30:49.462198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16834 12:30:49.462655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16836 12:30:49.501600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16837 12:30:49.502049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16839 12:30:49.540334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16840 12:30:49.540771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16842 12:30:49.586288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16843 12:30:49.586733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16845 12:30:49.642430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16846 12:30:49.642868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16848 12:30:49.702309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16850 12:30:49.702797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16851 12:30:49.758830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16852 12:30:49.759230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16854 12:30:49.818220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16855 12:30:49.818677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16857 12:30:49.867558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16859 12:30:49.868042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16860 12:30:49.909617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16861 12:30:49.910078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16863 12:30:49.961031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16864 12:30:49.961465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16866 12:30:50.002865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16867 12:30:50.003327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16869 12:30:50.045095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16871 12:30:50.045577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16872 12:30:50.098137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16874 12:30:50.098574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16875 12:30:50.140778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16876 12:30:50.141301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16878 12:30:50.186692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16879 12:30:50.187090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16881 12:30:50.228672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16882 12:30:50.229054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16884 12:30:50.273930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16885 12:30:50.274322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16887 12:30:50.313440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16888 12:30:50.313838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16890 12:30:50.352057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16891 12:30:50.352504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16893 12:30:50.392013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16895 12:30:50.392676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16896 12:30:50.447968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16897 12:30:50.448523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16899 12:30:50.500753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16900 12:30:50.501198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16902 12:30:50.538966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16904 12:30:50.539449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16905 12:30:50.578875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16906 12:30:50.579320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16908 12:30:50.624779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16910 12:30:50.625252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16911 12:30:50.661435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16912 12:30:50.661897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16914 12:30:50.699140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16916 12:30:50.699617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16917 12:30:50.737062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16918 12:30:50.737511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16920 12:30:50.775852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16921 12:30:50.776312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16923 12:30:50.814118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16924 12:30:50.814542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16926 12:30:50.852877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16928 12:30:50.853559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16929 12:30:50.890382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16930 12:30:50.890789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16932 12:30:50.928499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16933 12:30:50.928934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16935 12:30:50.965941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16937 12:30:50.966425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16938 12:30:51.004022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16939 12:30:51.004528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16941 12:30:51.040546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16942 12:30:51.041114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16944 12:30:51.081271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16945 12:30:51.081867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16947 12:30:51.133329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16948 12:30:51.133844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16950 12:30:51.195451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16952 12:30:51.195956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16953 12:30:51.258725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16955 12:30:51.259200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16956 12:30:51.321704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16957 12:30:51.322112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16959 12:30:51.378792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16961 12:30:51.379289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16962 12:30:51.429223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16963 12:30:51.429683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16965 12:30:51.489425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16966 12:30:51.489871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16968 12:30:51.536793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16969 12:30:51.537233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16971 12:30:51.585720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16973 12:30:51.586155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16974 12:30:51.634383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16975 12:30:51.634796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16977 12:30:51.679044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16978 12:30:51.679470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16980 12:30:51.726610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
16981 12:30:51.727192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
16983 12:30:51.772700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
16985 12:30:51.773361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
16986 12:30:51.812707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
16988 12:30:51.813138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
16989 12:30:51.865017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
16990 12:30:51.865619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
16992 12:30:51.908109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
16993 12:30:51.908611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
16995 12:30:51.961131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
16996 12:30:51.961587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
16998 12:30:52.008776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
16999 12:30:52.009239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17001 12:30:52.050601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17002 12:30:52.051050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17004 12:30:52.109054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17005 12:30:52.109514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17007 12:30:52.150405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17008 12:30:52.150791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17010 12:30:52.192051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17011 12:30:52.192490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17013 12:30:52.236242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17014 12:30:52.236600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17016 12:30:52.278090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17018 12:30:52.278556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17019 12:30:52.319792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17020 12:30:52.320319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17022 12:30:52.363120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17024 12:30:52.363862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17025 12:30:52.409265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17026 12:30:52.409695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17028 12:30:52.456720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17029 12:30:52.457114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17031 12:30:52.510281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17033 12:30:52.510706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17034 12:30:52.553093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17036 12:30:52.553581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17037 12:30:52.617905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17038 12:30:52.618492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17040 12:30:52.657145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17041 12:30:52.657608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17043 12:30:52.715535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17044 12:30:52.716003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17046 12:30:52.764637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17048 12:30:52.765128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17049 12:30:52.810645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17050 12:30:52.811027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17052 12:30:52.867321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17054 12:30:52.867783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17055 12:30:52.908952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17056 12:30:52.909365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17058 12:30:52.957616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17059 12:30:52.958031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17061 12:30:53.017082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17062 12:30:53.017519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17064 12:30:53.076471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17066 12:30:53.076845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17067 12:30:53.134372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17069 12:30:53.134975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17070 12:30:53.193633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17071 12:30:53.194079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17073 12:30:53.240130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17074 12:30:53.240569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17076 12:30:53.287427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17078 12:30:53.287922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17079 12:30:53.331305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17081 12:30:53.331750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17082 12:30:53.372641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17083 12:30:53.373075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17085 12:30:53.412636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17087 12:30:53.413117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17088 12:30:53.453181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17090 12:30:53.453678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17091 12:30:53.497446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17093 12:30:53.497959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17094 12:30:53.543979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17095 12:30:53.544431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17097 12:30:53.589442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17099 12:30:53.589944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17100 12:30:53.631039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17102 12:30:53.631498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17103 12:30:53.674762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17104 12:30:53.675189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17106 12:30:53.716592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17107 12:30:53.717105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17109 12:30:53.755064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17110 12:30:53.755646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17112 12:30:53.793905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17113 12:30:53.794489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17115 12:30:53.834015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17116 12:30:53.834422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17118 12:30:53.874764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17119 12:30:53.875170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17121 12:30:53.913082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17123 12:30:53.913591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17124 12:30:53.950783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17126 12:30:53.951240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17127 12:30:53.997566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17129 12:30:53.998064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17130 12:30:54.046679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17131 12:30:54.047063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17133 12:30:54.090036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17134 12:30:54.090564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17136 12:30:54.132792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17137 12:30:54.133366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17139 12:30:54.178100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17140 12:30:54.178486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17142 12:30:54.237411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17143 12:30:54.237977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17145 12:30:54.295457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17147 12:30:54.296374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17148 12:30:54.341091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17150 12:30:54.341564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17151 12:30:54.378897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17152 12:30:54.379352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17154 12:30:54.417586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17155 12:30:54.418051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17157 12:30:54.456110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17158 12:30:54.456559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17160 12:30:54.496596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17162 12:30:54.497075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17163 12:30:54.539465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17165 12:30:54.540147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17166 12:30:54.579106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17168 12:30:54.579591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17169 12:30:54.617403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17170 12:30:54.617825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17172 12:30:54.655330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17174 12:30:54.655803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17175 12:30:54.694052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17177 12:30:54.694648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17178 12:30:54.732085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17179 12:30:54.732493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17181 12:30:54.773435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17182 12:30:54.773887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17184 12:30:54.812339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17185 12:30:54.812790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17187 12:30:54.852399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17189 12:30:54.852877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17190 12:30:54.893715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17191 12:30:54.894125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17193 12:30:54.934578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17194 12:30:54.935007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17196 12:30:54.983977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17198 12:30:54.984425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17199 12:30:55.027815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17200 12:30:55.028265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17202 12:30:55.069543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17203 12:30:55.069944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17205 12:30:55.112732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17206 12:30:55.113142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17208 12:30:55.156656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17210 12:30:55.157072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17211 12:30:55.202856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17212 12:30:55.203246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17214 12:30:55.245170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17215 12:30:55.245708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17217 12:30:55.289714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17218 12:30:55.290102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17220 12:30:55.330031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17221 12:30:55.330527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17223 12:30:55.368633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17224 12:30:55.369122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17226 12:30:55.407296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17228 12:30:55.407957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17229 12:30:55.445400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17230 12:30:55.445885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17232 12:30:55.482172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17233 12:30:55.482711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17235 12:30:55.525709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17237 12:30:55.526091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17238 12:30:55.577824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17240 12:30:55.578207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17241 12:30:55.634908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17242 12:30:55.635402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17244 12:30:55.687836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17245 12:30:55.688346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17247 12:30:55.725698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17249 12:30:55.726182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17250 12:30:55.764343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17252 12:30:55.764828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17253 12:30:55.805110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17255 12:30:55.805946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17256 12:30:55.849184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17258 12:30:55.849754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17259 12:30:55.888600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17260 12:30:55.889001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17262 12:30:55.929456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17264 12:30:55.929957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17265 12:30:55.973420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17267 12:30:55.973885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17268 12:30:56.014296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17269 12:30:56.014700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17271 12:30:56.054224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17273 12:30:56.054601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17274 12:30:56.093221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17275 12:30:56.093666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17277 12:30:56.131924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17278 12:30:56.132351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17280 12:30:56.170972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17281 12:30:56.171399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17283 12:30:56.215762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17284 12:30:56.216147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17286 12:30:56.256084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17288 12:30:56.256841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17289 12:30:56.296118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17290 12:30:56.296498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17292 12:30:56.336635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17293 12:30:56.337059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17295 12:30:56.378105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17297 12:30:56.378569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17298 12:30:56.417443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17299 12:30:56.417999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17301 12:30:56.458703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17302 12:30:56.459134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17304 12:30:56.502174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17305 12:30:56.502591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17307 12:30:56.544377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17308 12:30:56.544807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17310 12:30:56.584460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17311 12:30:56.584914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17313 12:30:56.624681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17314 12:30:56.625112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17316 12:30:56.666012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17318 12:30:56.666479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17319 12:30:56.721668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17320 12:30:56.722094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17322 12:30:56.775138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17324 12:30:56.775616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17325 12:30:56.815915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17327 12:30:56.816380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17328 12:30:56.854184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17329 12:30:56.854627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17331 12:30:56.893582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17332 12:30:56.894021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17334 12:30:56.934253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17335 12:30:56.934679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17337 12:30:56.990653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17338 12:30:56.991095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17340 12:30:57.049471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17342 12:30:57.049964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17343 12:30:57.108332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17344 12:30:57.108791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17346 12:30:57.160627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17347 12:30:57.161080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17349 12:30:57.199500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17351 12:30:57.199976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17352 12:30:57.253431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17353 12:30:57.253902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17355 12:30:57.304815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17356 12:30:57.305231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17358 12:30:57.360713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17359 12:30:57.361174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17361 12:30:57.400714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17362 12:30:57.401138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17364 12:30:57.449861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17365 12:30:57.450279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17367 12:30:57.509803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17369 12:30:57.510191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17370 12:30:57.569052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17371 12:30:57.569514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17373 12:30:57.628876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17374 12:30:57.629271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17376 12:30:57.688806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17377 12:30:57.689227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17379 12:30:57.750123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17381 12:30:57.750566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17382 12:30:57.794708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17383 12:30:57.795117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17385 12:30:57.837097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17386 12:30:57.837545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17388 12:30:57.878504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17390 12:30:57.878995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17391 12:30:57.929890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17393 12:30:57.930346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17394 12:30:57.981460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17396 12:30:57.982101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17397 12:30:58.027015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17398 12:30:58.027487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17400 12:30:58.070456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17401 12:30:58.070918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17403 12:30:58.112844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17404 12:30:58.113250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17406 12:30:58.151133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17408 12:30:58.151615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17409 12:30:58.194996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17410 12:30:58.195369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17412 12:30:58.253658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17414 12:30:58.254154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17415 12:30:58.293325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17416 12:30:58.293769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17418 12:30:58.338984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17419 12:30:58.339430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17421 12:30:58.381275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17423 12:30:58.381775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17424 12:30:58.424449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17425 12:30:58.424907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17427 12:30:58.467288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17429 12:30:58.467961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17430 12:30:58.505912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17431 12:30:58.506304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17433 12:30:58.547589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17435 12:30:58.548364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17436 12:30:58.598888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17438 12:30:58.599331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17439 12:30:58.641605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17440 12:30:58.642107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17442 12:30:58.684725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17443 12:30:58.685230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17445 12:30:58.725040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17447 12:30:58.725741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17448 12:30:58.767711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17450 12:30:58.768277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17451 12:30:58.814417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17452 12:30:58.814902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17454 12:30:58.872442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17455 12:30:58.872930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17457 12:30:58.913803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17458 12:30:58.914256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17460 12:30:58.957387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17461 12:30:58.957827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17463 12:30:59.004039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17464 12:30:59.004425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17466 12:30:59.049723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17467 12:30:59.050293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17469 12:30:59.096823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17470 12:30:59.097296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17472 12:30:59.138784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17474 12:30:59.139271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17475 12:30:59.181451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17476 12:30:59.181904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17478 12:30:59.232851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17479 12:30:59.233343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17481 12:30:59.280424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17482 12:30:59.280897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17484 12:30:59.324339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17485 12:30:59.324760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17487 12:30:59.364242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17489 12:30:59.364721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17490 12:30:59.408418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17491 12:30:59.408847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17493 12:30:59.453186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17495 12:30:59.453595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17496 12:30:59.494241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17497 12:30:59.494758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17499 12:30:59.544658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17500 12:30:59.545039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17502 12:30:59.593452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17504 12:30:59.593838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17505 12:30:59.650322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17507 12:30:59.650695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17508 12:30:59.708120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17510 12:30:59.708729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17511 12:30:59.764736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17512 12:30:59.765169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17514 12:30:59.806770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17515 12:30:59.807352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17517 12:30:59.857016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17519 12:30:59.857687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17520 12:30:59.911055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17522 12:30:59.911764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17523 12:30:59.975397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17525 12:30:59.975874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17526 12:31:00.020878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17528 12:31:00.021375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17529 12:31:00.062708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17530 12:31:00.063189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17532 12:31:00.103593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17534 12:31:00.104260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17535 12:31:00.151497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17537 12:31:00.151920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17538 12:31:00.194002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17539 12:31:00.194505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17541 12:31:00.233285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17542 12:31:00.233885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17544 12:31:00.272605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17545 12:31:00.273060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17547 12:31:00.325204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17548 12:31:00.325718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17550 12:31:00.366934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17552 12:31:00.367693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17553 12:31:00.405977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17555 12:31:00.406456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17556 12:31:00.448037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17557 12:31:00.448426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17559 12:31:00.488354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17560 12:31:00.488787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17562 12:31:00.525594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17563 12:31:00.526165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17565 12:31:00.562378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17566 12:31:00.562820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17568 12:31:00.612359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17569 12:31:00.612809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17571 12:31:00.656866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17572 12:31:00.657345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17574 12:31:00.709193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17575 12:31:00.709608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17577 12:31:00.757375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17579 12:31:00.757805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17580 12:31:00.798991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17581 12:31:00.799439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17583 12:31:00.839383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17585 12:31:00.839818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17586 12:31:00.880753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17587 12:31:00.881177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17589 12:31:00.928827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17591 12:31:00.929264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17592 12:31:00.987185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17594 12:31:00.987724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17595 12:31:01.035688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17597 12:31:01.036557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17598 12:31:01.074043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17600 12:31:01.074802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17601 12:31:01.112709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17602 12:31:01.113109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17604 12:31:01.153789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17605 12:31:01.154204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17607 12:31:01.200168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17608 12:31:01.200635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17610 12:31:01.243073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17611 12:31:01.243495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17613 12:31:01.286835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17615 12:31:01.287323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17616 12:31:01.326719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17617 12:31:01.327144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17619 12:31:01.371434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17621 12:31:01.372057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17622 12:31:01.413124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17624 12:31:01.413865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17625 12:31:01.453344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17627 12:31:01.453964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17628 12:31:01.497125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17630 12:31:01.497823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17631 12:31:01.537547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17632 12:31:01.537944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17634 12:31:01.583952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17635 12:31:01.584384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17637 12:31:01.621966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17638 12:31:01.622446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17640 12:31:01.668159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17642 12:31:01.668695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17643 12:31:01.710567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17644 12:31:01.711040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17646 12:31:01.750520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17647 12:31:01.750924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17649 12:31:01.798613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17650 12:31:01.799066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17652 12:31:01.843719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17653 12:31:01.844225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17655 12:31:01.892844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17656 12:31:01.893355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17658 12:31:01.949249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17659 12:31:01.949692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17661 12:31:02.003354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17663 12:31:02.003971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17664 12:31:02.049508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17665 12:31:02.049946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17667 12:31:02.089117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17668 12:31:02.089523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17670 12:31:02.126414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17672 12:31:02.126840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17673 12:31:02.161710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17674 12:31:02.162106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17676 12:31:02.197707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17677 12:31:02.198107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17679 12:31:02.244837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17681 12:31:02.245329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17682 12:31:02.284618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17683 12:31:02.285076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17685 12:31:02.322236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17686 12:31:02.322671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17688 12:31:02.360914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17689 12:31:02.361446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17691 12:31:02.397732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17693 12:31:02.398348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17694 12:31:02.437498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17696 12:31:02.438199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17697 12:31:02.498778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17698 12:31:02.499263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17700 12:31:02.538214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17701 12:31:02.538711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17703 12:31:02.576176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17705 12:31:02.576638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17706 12:31:02.619065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17707 12:31:02.619540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17709 12:31:02.654717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17710 12:31:02.655230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17712 12:31:02.701062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17714 12:31:02.701509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17715 12:31:02.746976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17716 12:31:02.747412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17718 12:31:02.798938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17719 12:31:02.799391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17721 12:31:02.848743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17722 12:31:02.849135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17724 12:31:02.903024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17725 12:31:02.903422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17727 12:31:02.957832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17728 12:31:02.958245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17730 12:31:03.000346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17731 12:31:03.000778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17733 12:31:03.042884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17735 12:31:03.043319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17736 12:31:03.081245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17737 12:31:03.081699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17739 12:31:03.120620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17740 12:31:03.121009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17742 12:31:03.165213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17744 12:31:03.165615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17745 12:31:03.210142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17746 12:31:03.210573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17748 12:31:03.251312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17750 12:31:03.251749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17751 12:31:03.291851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17752 12:31:03.292362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17754 12:31:03.336986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17755 12:31:03.338896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17757 12:31:03.379539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17759 12:31:03.380204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17760 12:31:03.424671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17761 12:31:03.425236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17763 12:31:03.469355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17764 12:31:03.469812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17766 12:31:03.508598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17767 12:31:03.509170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17769 12:31:03.556290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17771 12:31:03.556765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17772 12:31:03.606932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17773 12:31:03.607338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17775 12:31:03.664072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17777 12:31:03.664535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17778 12:31:03.706446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17780 12:31:03.706916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17781 12:31:03.759382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17783 12:31:03.760024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17784 12:31:03.820573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17785 12:31:03.821031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17787 12:31:03.881297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17788 12:31:03.881753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17790 12:31:03.941750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17792 12:31:03.942219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17793 12:31:04.002821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17795 12:31:04.003308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17796 12:31:04.062082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17797 12:31:04.062506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17799 12:31:04.121722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17800 12:31:04.122134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17802 12:31:04.181272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17803 12:31:04.181694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17805 12:31:04.233630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17806 12:31:04.234079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17808 12:31:04.288658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17809 12:31:04.289116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17811 12:31:04.343506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17813 12:31:04.343997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17814 12:31:04.394716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17816 12:31:04.395198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17817 12:31:04.444706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17818 12:31:04.445170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17820 12:31:04.492885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17822 12:31:04.493378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17823 12:31:04.541329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17825 12:31:04.541829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17826 12:31:04.599551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17828 12:31:04.600024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17829 12:31:04.655297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17831 12:31:04.655770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17832 12:31:04.715416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17834 12:31:04.715946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17835 12:31:04.769497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17836 12:31:04.769928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17838 12:31:04.818433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17839 12:31:04.818902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17841 12:31:04.873778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17842 12:31:04.874221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17844 12:31:04.929207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17845 12:31:04.929660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17847 12:31:04.990829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17848 12:31:04.991265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17850 12:31:05.050738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17851 12:31:05.051183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17853 12:31:05.102811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17854 12:31:05.103253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17856 12:31:05.152681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17858 12:31:05.153169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17859 12:31:05.206404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17860 12:31:05.206837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17862 12:31:05.261886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17864 12:31:05.262368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17865 12:31:05.309996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17866 12:31:05.310434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17868 12:31:05.364211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17869 12:31:05.364638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17871 12:31:05.419564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17873 12:31:05.420060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17874 12:31:05.472133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17875 12:31:05.472570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17877 12:31:05.522916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17878 12:31:05.523363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17880 12:31:05.579589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17882 12:31:05.580047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17883 12:31:05.638860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17884 12:31:05.639281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17886 12:31:05.697625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17887 12:31:05.698083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17889 12:31:05.756109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17890 12:31:05.756559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17892 12:31:05.817262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17893 12:31:05.817757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17895 12:31:05.873161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17896 12:31:05.873591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17898 12:31:05.925450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17899 12:31:05.925874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17901 12:31:05.980933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17902 12:31:05.981376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17904 12:31:06.032235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17905 12:31:06.032679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17907 12:31:06.090841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17909 12:31:06.091338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17910 12:31:06.141207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17912 12:31:06.141753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17913 12:31:06.197586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17915 12:31:06.198060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17916 12:31:06.256476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17917 12:31:06.256931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17919 12:31:06.308831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17920 12:31:06.309281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17922 12:31:06.356440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17923 12:31:06.356847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17925 12:31:06.405798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17926 12:31:06.406221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17928 12:31:06.468741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17929 12:31:06.469182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17931 12:31:06.528313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17933 12:31:06.528975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17934 12:31:06.585222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17935 12:31:06.585668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17937 12:31:06.644356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17938 12:31:06.644821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17940 12:31:06.700797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17941 12:31:06.701217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17943 12:31:06.757666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17945 12:31:06.758128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17946 12:31:06.808764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17947 12:31:06.809434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17949 12:31:06.869419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17950 12:31:06.869816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17952 12:31:06.932902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17953 12:31:06.933343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17955 12:31:06.990140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17956 12:31:06.990546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17958 12:31:07.037023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17959 12:31:07.037495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17961 12:31:07.085335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17962 12:31:07.085758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17964 12:31:07.128862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17966 12:31:07.129322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17967 12:31:07.177446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17968 12:31:07.177902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17970 12:31:07.230783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17971 12:31:07.231210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17973 12:31:07.281405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17974 12:31:07.281856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17976 12:31:07.329359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17977 12:31:07.329800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17979 12:31:07.372760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
17981 12:31:07.373237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17982 12:31:07.426806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
17983 12:31:07.427267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
17985 12:31:07.474608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
17987 12:31:07.475085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
17988 12:31:07.526849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
17990 12:31:07.527324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
17991 12:31:07.606735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
17992 12:31:07.607099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
17994 12:31:07.669487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
17995 12:31:07.669938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
17997 12:31:07.728678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
17999 12:31:07.729064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18000 12:31:07.781718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18001 12:31:07.782116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18003 12:31:07.825982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18004 12:31:07.826410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18006 12:31:07.878310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18007 12:31:07.878748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18009 12:31:07.926771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18010 12:31:07.927206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18012 12:31:07.978482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18013 12:31:07.978917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18015 12:31:08.024684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18016 12:31:08.025116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18018 12:31:08.072720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18019 12:31:08.073298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18021 12:31:08.113417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18023 12:31:08.113935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18024 12:31:08.162664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18026 12:31:08.163089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18027 12:31:08.218488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18028 12:31:08.218992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18030 12:31:08.275123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18031 12:31:08.275683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18033 12:31:08.320518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18034 12:31:08.320974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18036 12:31:08.364716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18038 12:31:08.365210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18039 12:31:08.421148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18040 12:31:08.421722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18042 12:31:08.478347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18043 12:31:08.478783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18045 12:31:08.529229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18046 12:31:08.529691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18048 12:31:08.578140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18050 12:31:08.578570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18051 12:31:08.624995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18052 12:31:08.625449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18054 12:31:08.673941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18056 12:31:08.674425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18057 12:31:08.721560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18058 12:31:08.721992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18060 12:31:08.781471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18062 12:31:08.781971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18063 12:31:08.841294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18064 12:31:08.841694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18066 12:31:08.901369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18067 12:31:08.901762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18069 12:31:08.962184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18070 12:31:08.962654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18072 12:31:09.024516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18074 12:31:09.025250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18075 12:31:09.085227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18076 12:31:09.085694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18078 12:31:09.146289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18079 12:31:09.146747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18081 12:31:09.206344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18082 12:31:09.206749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18084 12:31:09.267335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18086 12:31:09.267786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18087 12:31:09.328699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18088 12:31:09.329059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18090 12:31:09.390023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18091 12:31:09.390415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18093 12:31:09.450740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18094 12:31:09.451177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18096 12:31:09.510887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18098 12:31:09.511302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18099 12:31:09.572165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18100 12:31:09.572559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18102 12:31:09.633482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18103 12:31:09.633951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18105 12:31:09.689089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18106 12:31:09.689543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18108 12:31:09.744769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18109 12:31:09.745175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18111 12:31:09.793300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18112 12:31:09.793758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18114 12:31:09.840788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18115 12:31:09.841226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18117 12:31:09.889418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18119 12:31:09.889912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18120 12:31:09.948905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18122 12:31:09.949347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18123 12:31:10.008612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18124 12:31:10.009055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18126 12:31:10.070370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18127 12:31:10.070784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18129 12:31:10.126808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18131 12:31:10.127250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18132 12:31:10.180691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18133 12:31:10.181100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18135 12:31:10.223085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18136 12:31:10.223529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18138 12:31:10.263972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18139 12:31:10.264369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18141 12:31:10.304271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18142 12:31:10.304685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18144 12:31:10.346952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18145 12:31:10.347326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18147 12:31:10.393633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18148 12:31:10.394098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18150 12:31:10.438671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18151 12:31:10.439129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18153 12:31:10.491076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18154 12:31:10.491518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18156 12:31:10.539023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18158 12:31:10.539523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18159 12:31:10.582972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18161 12:31:10.583477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18162 12:31:10.625056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18164 12:31:10.625514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18165 12:31:10.681658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18166 12:31:10.682065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18168 12:31:10.740463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18169 12:31:10.740854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18171 12:31:10.798613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18173 12:31:10.799111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18174 12:31:10.857852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18175 12:31:10.858312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18177 12:31:10.917223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18178 12:31:10.917670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18180 12:31:10.975207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18182 12:31:10.975776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18183 12:31:11.033534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18184 12:31:11.033995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18186 12:31:11.093405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18187 12:31:11.093828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18189 12:31:11.152197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18191 12:31:11.152680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18192 12:31:11.209063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18194 12:31:11.209846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18195 12:31:11.257234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18196 12:31:11.257674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18198 12:31:11.314432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18200 12:31:11.314903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18201 12:31:11.364110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18202 12:31:11.364549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18204 12:31:11.417891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18205 12:31:11.418382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18207 12:31:11.474191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18208 12:31:11.474610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18210 12:31:11.527175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18211 12:31:11.527616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18213 12:31:11.573265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18214 12:31:11.573695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18216 12:31:11.617984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18217 12:31:11.618434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18219 12:31:11.658510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18220 12:31:11.658947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18222 12:31:11.707423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18224 12:31:11.707873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18225 12:31:11.755119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18227 12:31:11.755603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18228 12:31:11.798430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18229 12:31:11.798816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18231 12:31:11.844527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18232 12:31:11.844958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18234 12:31:11.891358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18236 12:31:11.892075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18237 12:31:11.933962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18239 12:31:11.934706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18240 12:31:11.974001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18242 12:31:11.974476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18243 12:31:12.012228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18244 12:31:12.012632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18246 12:31:12.057476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18247 12:31:12.057992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18249 12:31:12.101693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18251 12:31:12.102169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18252 12:31:12.150622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18254 12:31:12.151099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18255 12:31:12.192833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18256 12:31:12.193241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18258 12:31:12.236236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18259 12:31:12.236639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18261 12:31:12.281678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18263 12:31:12.282161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18264 12:31:12.343165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18266 12:31:12.343660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18267 12:31:12.402961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18268 12:31:12.403421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18270 12:31:12.458657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18271 12:31:12.459098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18273 12:31:12.512633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18274 12:31:12.513048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18276 12:31:12.560014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18278 12:31:12.560473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18279 12:31:12.610580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18281 12:31:12.611003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18282 12:31:12.652682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18283 12:31:12.653186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18285 12:31:12.715734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18286 12:31:12.716242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18288 12:31:12.754971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18289 12:31:12.755437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18291 12:31:12.803947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18292 12:31:12.804387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18294 12:31:12.849242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18296 12:31:12.849626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18297 12:31:12.889468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18298 12:31:12.889893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18300 12:31:12.936438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18301 12:31:12.936898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18303 12:31:12.981733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18304 12:31:12.982169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18306 12:31:13.037181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18308 12:31:13.037643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18309 12:31:13.081009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18311 12:31:13.081611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18312 12:31:13.124358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18313 12:31:13.124740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18315 12:31:13.169510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18316 12:31:13.169955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18318 12:31:13.210972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18320 12:31:13.211427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18321 12:31:13.258211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18322 12:31:13.258636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18324 12:31:13.310775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18326 12:31:13.311260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18327 12:31:13.357778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18328 12:31:13.358186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18330 12:31:13.405499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18332 12:31:13.405988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18333 12:31:13.445877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18335 12:31:13.446282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18336 12:31:13.499336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18338 12:31:13.499852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18339 12:31:13.550720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18341 12:31:13.551190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18342 12:31:13.601502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18343 12:31:13.601922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18345 12:31:13.649957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18346 12:31:13.650392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18348 12:31:13.696951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18349 12:31:13.697414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18351 12:31:13.733895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18352 12:31:13.734324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18354 12:31:13.783360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18355 12:31:13.783826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18357 12:31:13.835417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18359 12:31:13.835893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18360 12:31:13.885957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18362 12:31:13.886431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18363 12:31:13.926154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18364 12:31:13.926609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18366 12:31:13.969346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18367 12:31:13.969798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18369 12:31:14.026342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18370 12:31:14.026806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18372 12:31:14.081749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18373 12:31:14.082201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18375 12:31:14.130296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18376 12:31:14.130732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18378 12:31:14.184028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18379 12:31:14.184429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18381 12:31:14.235515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18383 12:31:14.235996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18384 12:31:14.276771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18385 12:31:14.277197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18387 12:31:14.322003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18388 12:31:14.322440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18390 12:31:14.373085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18392 12:31:14.373571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18393 12:31:14.422033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18394 12:31:14.422432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18396 12:31:14.478437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18397 12:31:14.478883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18399 12:31:14.531887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18400 12:31:14.532257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18402 12:31:14.584137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18403 12:31:14.584537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18405 12:31:14.629668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18406 12:31:14.630104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18408 12:31:14.678046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18409 12:31:14.678443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18411 12:31:14.726392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18412 12:31:14.726792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18414 12:31:14.780781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18415 12:31:14.781209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18417 12:31:14.835440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18419 12:31:14.835917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18420 12:31:14.873954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18421 12:31:14.874390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18423 12:31:14.913206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18425 12:31:14.913709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18426 12:31:14.957847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18428 12:31:14.958333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18429 12:31:15.000488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18431 12:31:15.000947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18432 12:31:15.061120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18433 12:31:15.061553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18435 12:31:15.117113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18437 12:31:15.117580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18438 12:31:15.157105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18440 12:31:15.157566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18441 12:31:15.206822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18442 12:31:15.207259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18444 12:31:15.245495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18446 12:31:15.245979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18447 12:31:15.283789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18448 12:31:15.284233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18450 12:31:15.327581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18452 12:31:15.328076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18453 12:31:15.372486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18454 12:31:15.372931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18456 12:31:15.417400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18457 12:31:15.417854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18459 12:31:15.459497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18461 12:31:15.459989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18462 12:31:15.504776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18464 12:31:15.505214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18465 12:31:15.545695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18466 12:31:15.546129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18468 12:31:15.592293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18470 12:31:15.593002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18471 12:31:15.640774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18472 12:31:15.641220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18474 12:31:15.689544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18475 12:31:15.690005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18477 12:31:15.728692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18478 12:31:15.729104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18480 12:31:15.767364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18482 12:31:15.767837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18483 12:31:15.806347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18484 12:31:15.806766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18486 12:31:15.849089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18487 12:31:15.849632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18489 12:31:15.890248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18491 12:31:15.890722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18492 12:31:15.934996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18493 12:31:15.935483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18495 12:31:15.998616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18496 12:31:15.998998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18498 12:31:16.061254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18499 12:31:16.061666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18501 12:31:16.122660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18503 12:31:16.123060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18504 12:31:16.183419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18506 12:31:16.183894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18507 12:31:16.242314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18509 12:31:16.242735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18510 12:31:16.300792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18511 12:31:16.301259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18513 12:31:16.351985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18514 12:31:16.352430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18516 12:31:16.391489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18518 12:31:16.391969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18519 12:31:16.431960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18521 12:31:16.432423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18522 12:31:16.473755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18523 12:31:16.474209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18525 12:31:16.516093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18526 12:31:16.516522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18528 12:31:16.568976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18529 12:31:16.569422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18531 12:31:16.618757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18532 12:31:16.619202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18534 12:31:16.671429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18536 12:31:16.671896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18537 12:31:16.733116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18538 12:31:16.733531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18540 12:31:16.793715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18542 12:31:16.794156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18543 12:31:16.854716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18544 12:31:16.855160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18546 12:31:16.916806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18547 12:31:16.917254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18549 12:31:16.959506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18551 12:31:16.960221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18552 12:31:17.002074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18553 12:31:17.002585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18555 12:31:17.041482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18556 12:31:17.041902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18558 12:31:17.091399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18560 12:31:17.092168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18561 12:31:17.148839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18562 12:31:17.149271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18564 12:31:17.204646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18565 12:31:17.205105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18567 12:31:17.261459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18569 12:31:17.261937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18570 12:31:17.306464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18571 12:31:17.306908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18573 12:31:17.354530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18575 12:31:17.354946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18576 12:31:17.410660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18578 12:31:17.411150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18579 12:31:17.465927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18581 12:31:17.466403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18582 12:31:17.514641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18583 12:31:17.515085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18585 12:31:17.557602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18586 12:31:17.558053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18588 12:31:17.594960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18589 12:31:17.595406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18591 12:31:17.635304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18593 12:31:17.635786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18594 12:31:17.678262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18596 12:31:17.678742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18597 12:31:17.727329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18599 12:31:17.727831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18600 12:31:17.772297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18602 12:31:17.772788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18603 12:31:17.837371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18604 12:31:17.837773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18606 12:31:17.888735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18607 12:31:17.889174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18609 12:31:17.928695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18610 12:31:17.929114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18612 12:31:17.968982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18614 12:31:17.969468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18615 12:31:18.009200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18617 12:31:18.009712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18618 12:31:18.050897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18619 12:31:18.051346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18621 12:31:18.091522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18623 12:31:18.092012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18624 12:31:18.134592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18626 12:31:18.135080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18627 12:31:18.174465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18628 12:31:18.174859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18630 12:31:18.221177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18631 12:31:18.221590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18633 12:31:18.265285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18634 12:31:18.265705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18636 12:31:18.303572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18638 12:31:18.304083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18639 12:31:18.341805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18641 12:31:18.342573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18642 12:31:18.380928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18643 12:31:18.381480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18645 12:31:18.418922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18646 12:31:18.419402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18648 12:31:18.473913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18650 12:31:18.474545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18651 12:31:18.512005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18652 12:31:18.512401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18654 12:31:18.550504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18655 12:31:18.550891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18657 12:31:18.589289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18658 12:31:18.589696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18660 12:31:18.625933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18662 12:31:18.626690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18663 12:31:18.662394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18664 12:31:18.662872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18666 12:31:18.699448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18668 12:31:18.700172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18669 12:31:18.737782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18671 12:31:18.738403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18672 12:31:18.774431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18673 12:31:18.774853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18675 12:31:18.814398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18677 12:31:18.814877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18678 12:31:18.855322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18680 12:31:18.855997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18681 12:31:18.897991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18682 12:31:18.898449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18684 12:31:18.944815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18685 12:31:18.945206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18687 12:31:18.996870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18688 12:31:18.997263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18690 12:31:19.044259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18691 12:31:19.044699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18693 12:31:19.089362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18695 12:31:19.089857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18696 12:31:19.136959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18698 12:31:19.137438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18699 12:31:19.187057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18700 12:31:19.187440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18702 12:31:19.238222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18703 12:31:19.238650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18705 12:31:19.284722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18706 12:31:19.285161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18708 12:31:19.324117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18710 12:31:19.324593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18711 12:31:19.365804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18712 12:31:19.366233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18714 12:31:19.412928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18715 12:31:19.413358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18717 12:31:19.454268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18718 12:31:19.454671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18720 12:31:19.498216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18722 12:31:19.498694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18723 12:31:19.540808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18724 12:31:19.541209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18726 12:31:19.583998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18727 12:31:19.584456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18729 12:31:19.631973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18730 12:31:19.632411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18732 12:31:19.685301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18733 12:31:19.685762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18735 12:31:19.733636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18736 12:31:19.734067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18738 12:31:19.779425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18740 12:31:19.779912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18741 12:31:19.829055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18742 12:31:19.829594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18744 12:31:19.878756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18746 12:31:19.879239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18747 12:31:19.925706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18749 12:31:19.926188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18750 12:31:19.970375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18751 12:31:19.970800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18753 12:31:20.017105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18754 12:31:20.017539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18756 12:31:20.064039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18757 12:31:20.064468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18759 12:31:20.102178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18760 12:31:20.102631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18762 12:31:20.143027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18763 12:31:20.143415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18765 12:31:20.182996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18767 12:31:20.183480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18768 12:31:20.224015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18769 12:31:20.224441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18771 12:31:20.263236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18773 12:31:20.264063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18774 12:31:20.306484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18775 12:31:20.306914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18777 12:31:20.350146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18778 12:31:20.350599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18780 12:31:20.392225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18782 12:31:20.392646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18783 12:31:20.431312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18785 12:31:20.431804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18786 12:31:20.470011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18787 12:31:20.470434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18789 12:31:20.510363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18790 12:31:20.510811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18792 12:31:20.556367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18794 12:31:20.556955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18795 12:31:20.596587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18797 12:31:20.597173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18798 12:31:20.636365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18800 12:31:20.636842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18801 12:31:20.678021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18802 12:31:20.678451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18804 12:31:20.718066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18806 12:31:20.718534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18807 12:31:20.757430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18808 12:31:20.757868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18810 12:31:20.796675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18812 12:31:20.797137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18813 12:31:20.841953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18814 12:31:20.842373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18816 12:31:20.884545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18817 12:31:20.884905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18819 12:31:20.927048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18821 12:31:20.927534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18822 12:31:20.970861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18823 12:31:20.971306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18825 12:31:21.022209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18826 12:31:21.022608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18828 12:31:21.062304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18830 12:31:21.062796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18831 12:31:21.113431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18832 12:31:21.113887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18834 12:31:21.158853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18835 12:31:21.159291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18837 12:31:21.211260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18839 12:31:21.212129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18840 12:31:21.262817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18842 12:31:21.263256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18843 12:31:21.318709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18844 12:31:21.319151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18846 12:31:21.358183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18847 12:31:21.358603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18849 12:31:21.400824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18850 12:31:21.401276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18852 12:31:21.441397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18853 12:31:21.441834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18855 12:31:21.488576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18856 12:31:21.488996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18858 12:31:21.538242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18859 12:31:21.538651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18861 12:31:21.585927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18862 12:31:21.586369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18864 12:31:21.630762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18865 12:31:21.631204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18867 12:31:21.672914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18869 12:31:21.673417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18870 12:31:21.718916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18871 12:31:21.719392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18873 12:31:21.758577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18874 12:31:21.759071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18876 12:31:21.796845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18877 12:31:21.797261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18879 12:31:21.841638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18880 12:31:21.842076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18882 12:31:21.882964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18883 12:31:21.883426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18885 12:31:21.921279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18886 12:31:21.921770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18888 12:31:21.968764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18889 12:31:21.969206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18891 12:31:22.016729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18893 12:31:22.017212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18894 12:31:22.065668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18895 12:31:22.066103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18897 12:31:22.110792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18898 12:31:22.111269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18900 12:31:22.164554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18901 12:31:22.164943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18903 12:31:22.218465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18904 12:31:22.218886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18906 12:31:22.270876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18907 12:31:22.271337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18909 12:31:22.320888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18911 12:31:22.321363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18912 12:31:22.368794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18914 12:31:22.369283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18915 12:31:22.421040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18916 12:31:22.421449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18918 12:31:22.468233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18920 12:31:22.468665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18921 12:31:22.513837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18922 12:31:22.514259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18924 12:31:22.561455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18925 12:31:22.561862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18927 12:31:22.604600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18929 12:31:22.605079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18930 12:31:22.652464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18931 12:31:22.652898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18933 12:31:22.696995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18934 12:31:22.697433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18936 12:31:22.746570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18937 12:31:22.746950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18939 12:31:22.802638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18941 12:31:22.803128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18942 12:31:22.848286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18943 12:31:22.848683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18945 12:31:22.907591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18947 12:31:22.908184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18948 12:31:22.990352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18949 12:31:22.990788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18951 12:31:23.038145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18952 12:31:23.038702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18954 12:31:23.090802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18955 12:31:23.091218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18957 12:31:23.143066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18958 12:31:23.143471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18960 12:31:23.197388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18961 12:31:23.197830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18963 12:31:23.246349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18964 12:31:23.246748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18966 12:31:23.298195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18967 12:31:23.298599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18969 12:31:23.350632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18970 12:31:23.351016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18972 12:31:23.398863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18973 12:31:23.399350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18975 12:31:23.448859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18976 12:31:23.449251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18978 12:31:23.496868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
18979 12:31:23.497347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18981 12:31:23.548679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
18982 12:31:23.549113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
18984 12:31:23.609091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
18985 12:31:23.609486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
18987 12:31:23.669034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
18989 12:31:23.669758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
18990 12:31:23.728168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
18991 12:31:23.728581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
18993 12:31:23.770967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
18994 12:31:23.771380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
18996 12:31:23.814554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
18997 12:31:23.814984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
18999 12:31:23.857362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19000 12:31:23.857800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19002 12:31:23.901793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19003 12:31:23.902234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19005 12:31:23.956773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19006 12:31:23.957202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19008 12:31:24.012148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19009 12:31:24.012624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19011 12:31:24.073124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19012 12:31:24.073498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19014 12:31:24.133114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19015 12:31:24.133504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19017 12:31:24.188183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19019 12:31:24.188670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19020 12:31:24.243068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19021 12:31:24.243470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19023 12:31:24.301349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19025 12:31:24.301804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19026 12:31:24.358730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19028 12:31:24.359171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19029 12:31:24.406899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19031 12:31:24.407345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19032 12:31:24.456819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19033 12:31:24.457220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19035 12:31:24.504259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19037 12:31:24.504891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19038 12:31:24.557256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19039 12:31:24.557668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19041 12:31:24.601303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19042 12:31:24.601765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19044 12:31:24.644181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19045 12:31:24.644620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19047 12:31:24.688828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19048 12:31:24.689234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19050 12:31:24.741694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19051 12:31:24.742262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19053 12:31:24.785268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19055 12:31:24.785757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19056 12:31:24.833211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19057 12:31:24.833610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19059 12:31:24.876886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19060 12:31:24.877315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19062 12:31:24.922556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19063 12:31:24.922951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19065 12:31:24.970029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19066 12:31:24.970431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19068 12:31:25.017154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19069 12:31:25.017568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19071 12:31:25.070122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19073 12:31:25.070500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19074 12:31:25.122949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19076 12:31:25.123337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19077 12:31:25.177270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19078 12:31:25.177698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19080 12:31:25.227742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19081 12:31:25.228184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19083 12:31:25.276425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19085 12:31:25.276813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19086 12:31:25.324369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19088 12:31:25.325092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19089 12:31:25.369362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19090 12:31:25.369809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19092 12:31:25.413413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19094 12:31:25.413914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19095 12:31:25.461074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19096 12:31:25.461513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19098 12:31:25.500583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19099 12:31:25.501041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19101 12:31:25.549542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19102 12:31:25.549990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19104 12:31:25.592613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19105 12:31:25.593002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19107 12:31:25.633049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19108 12:31:25.633490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19110 12:31:25.674238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19111 12:31:25.674672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19113 12:31:25.721075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19115 12:31:25.721511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19116 12:31:25.762507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19118 12:31:25.762980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19119 12:31:25.805808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19120 12:31:25.806237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19122 12:31:25.846284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19123 12:31:25.846850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19125 12:31:25.892353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19127 12:31:25.892737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19128 12:31:25.934493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19129 12:31:25.934892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19131 12:31:25.976277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19132 12:31:25.976802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19134 12:31:26.018046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19135 12:31:26.018474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19137 12:31:26.060174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19138 12:31:26.060641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19140 12:31:26.106989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19141 12:31:26.107463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19143 12:31:26.151501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19145 12:31:26.152189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19146 12:31:26.193147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19147 12:31:26.193529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19149 12:31:26.238047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19150 12:31:26.238472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19152 12:31:26.281294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19153 12:31:26.281690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19155 12:31:26.322392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19157 12:31:26.322798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19158 12:31:26.364957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19160 12:31:26.365412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19161 12:31:26.410656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19163 12:31:26.411152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19164 12:31:26.457131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19166 12:31:26.457601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19167 12:31:26.509519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19168 12:31:26.509964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19170 12:31:26.551778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19172 12:31:26.552263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19173 12:31:26.598384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19174 12:31:26.598821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19176 12:31:26.643635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19178 12:31:26.644088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19179 12:31:26.693932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19181 12:31:26.694409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19182 12:31:26.737713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19184 12:31:26.738171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19185 12:31:26.785314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19186 12:31:26.785746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19188 12:31:26.837966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19189 12:31:26.838395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19191 12:31:26.886567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19192 12:31:26.887007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19194 12:31:26.937965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19195 12:31:26.938398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19197 12:31:26.988484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19199 12:31:26.988928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19200 12:31:27.038043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19202 12:31:27.038501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19203 12:31:27.082658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19204 12:31:27.083096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19206 12:31:27.134666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19207 12:31:27.135068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19209 12:31:27.184034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19210 12:31:27.184448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19212 12:31:27.228443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19213 12:31:27.228809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19215 12:31:27.276768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19216 12:31:27.277232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19218 12:31:27.328554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19219 12:31:27.328990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19221 12:31:27.377560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19222 12:31:27.378015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19224 12:31:27.425791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19225 12:31:27.426243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19227 12:31:27.478263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19228 12:31:27.478731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19230 12:31:27.528729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19231 12:31:27.529165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19233 12:31:27.581371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19234 12:31:27.581832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19236 12:31:27.636537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19238 12:31:27.637033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19239 12:31:27.685719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19240 12:31:27.686158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19242 12:31:27.740352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19243 12:31:27.740815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19245 12:31:27.790794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19246 12:31:27.791242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19248 12:31:27.853295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19250 12:31:27.853784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19251 12:31:27.903819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19253 12:31:27.904368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19254 12:31:27.949363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19255 12:31:27.949810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19257 12:31:27.994465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19258 12:31:27.994904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19260 12:31:28.050374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19261 12:31:28.050816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19263 12:31:28.121036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19264 12:31:28.121500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19266 12:31:28.169428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19267 12:31:28.169844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19269 12:31:28.220245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19270 12:31:28.220675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19272 12:31:28.272148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19273 12:31:28.272531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19275 12:31:28.321938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19277 12:31:28.322706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19278 12:31:28.372188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19279 12:31:28.372573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19281 12:31:28.412014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19282 12:31:28.412441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19284 12:31:28.457855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19285 12:31:28.458310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19287 12:31:28.509585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19288 12:31:28.510062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19290 12:31:28.561401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19291 12:31:28.561908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19293 12:31:28.605004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19294 12:31:28.605435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19296 12:31:28.643212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19298 12:31:28.643694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19299 12:31:28.685036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19301 12:31:28.685473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19302 12:31:28.725282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19303 12:31:28.725689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19305 12:31:28.773039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19306 12:31:28.773442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19308 12:31:28.814573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19310 12:31:28.814982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19311 12:31:28.860778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19312 12:31:28.861146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19314 12:31:28.909583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19315 12:31:28.910029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19317 12:31:28.956476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19318 12:31:28.956910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19320 12:31:29.001378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19321 12:31:29.001789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19323 12:31:29.049036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19325 12:31:29.049533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19326 12:31:29.101813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19328 12:31:29.102292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19329 12:31:29.146281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19330 12:31:29.146724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19332 12:31:29.190917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19334 12:31:29.191380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19335 12:31:29.250958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19337 12:31:29.251464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19338 12:31:29.294771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19339 12:31:29.295229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19341 12:31:29.345514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19343 12:31:29.345976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19344 12:31:29.390302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19345 12:31:29.390753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19347 12:31:29.431109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19349 12:31:29.431593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19350 12:31:29.476658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19351 12:31:29.477084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19353 12:31:29.518793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19354 12:31:29.519254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19356 12:31:29.566291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19357 12:31:29.566713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19359 12:31:29.617907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19361 12:31:29.618364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19362 12:31:29.663130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19364 12:31:29.663636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19365 12:31:29.714830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19366 12:31:29.715276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19368 12:31:29.764114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19370 12:31:29.764514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19371 12:31:29.812541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19373 12:31:29.813164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19374 12:31:29.857867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19376 12:31:29.858554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19377 12:31:29.902838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19378 12:31:29.903351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19380 12:31:29.950706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19381 12:31:29.951168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19383 12:31:30.000203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19385 12:31:30.000686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19386 12:31:30.052629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19387 12:31:30.053089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19389 12:31:30.104235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19390 12:31:30.104626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19392 12:31:30.154284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19394 12:31:30.154755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19395 12:31:30.205493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19397 12:31:30.205989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19398 12:31:30.254897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19399 12:31:30.255341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19401 12:31:30.301726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19402 12:31:30.302196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19404 12:31:30.349958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19405 12:31:30.350396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19407 12:31:30.400185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19408 12:31:30.400572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19410 12:31:30.449482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19411 12:31:30.450056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19413 12:31:30.506585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19415 12:31:30.507063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19416 12:31:30.552688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19418 12:31:30.553517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19419 12:31:30.599249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19421 12:31:30.599728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19422 12:31:30.653727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19423 12:31:30.654174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19425 12:31:30.693630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19426 12:31:30.694103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19428 12:31:30.741441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19430 12:31:30.741936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19431 12:31:30.787822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19432 12:31:30.788275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19434 12:31:30.830025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19435 12:31:30.830460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19437 12:31:30.885065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19438 12:31:30.885591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19440 12:31:30.941439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19441 12:31:30.941886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19443 12:31:30.989236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19445 12:31:30.989753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19446 12:31:31.031981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19448 12:31:31.032461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19449 12:31:31.082048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19450 12:31:31.082474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19452 12:31:31.132553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19453 12:31:31.132977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19455 12:31:31.181613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19456 12:31:31.182058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19458 12:31:31.229556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19459 12:31:31.230003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19461 12:31:31.281147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19462 12:31:31.281583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19464 12:31:31.332181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19466 12:31:31.332676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19467 12:31:31.376080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19468 12:31:31.376505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19470 12:31:31.425261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19472 12:31:31.425779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19473 12:31:31.466486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19474 12:31:31.466939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19476 12:31:31.510144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19477 12:31:31.510602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19479 12:31:31.556702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19481 12:31:31.557200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19482 12:31:31.594614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19484 12:31:31.595061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19485 12:31:31.640919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19486 12:31:31.641344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19488 12:31:31.686625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19489 12:31:31.687081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19491 12:31:31.733237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19492 12:31:31.733691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19494 12:31:31.776594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19495 12:31:31.777178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19497 12:31:31.822112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19498 12:31:31.822544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19500 12:31:31.873483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19501 12:31:31.873885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19503 12:31:31.925165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19504 12:31:31.925588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19506 12:31:31.973493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19507 12:31:31.973942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19509 12:31:32.019641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19511 12:31:32.020078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19512 12:31:32.065456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19513 12:31:32.065865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19515 12:31:32.103432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19517 12:31:32.103913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19518 12:31:32.149489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19520 12:31:32.149964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19521 12:31:32.198800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19523 12:31:32.199278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19524 12:31:32.250109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19526 12:31:32.250492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19527 12:31:32.302133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19528 12:31:32.302698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19530 12:31:32.356240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19531 12:31:32.356719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19533 12:31:32.408300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19534 12:31:32.408764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19536 12:31:32.448409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19537 12:31:32.448850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19539 12:31:32.488941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19540 12:31:32.489388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19542 12:31:32.532927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19543 12:31:32.533311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19545 12:31:32.580872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19546 12:31:32.581277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19548 12:31:32.626562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19549 12:31:32.627003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19551 12:31:32.667219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19553 12:31:32.667698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19554 12:31:32.708478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19555 12:31:32.708905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19557 12:31:32.750605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19558 12:31:32.751045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19560 12:31:32.800577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19561 12:31:32.800994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19563 12:31:32.857876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19564 12:31:32.858259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19566 12:31:32.897569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19568 12:31:32.898037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19569 12:31:32.936798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19570 12:31:32.937246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19572 12:31:32.976692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19574 12:31:32.977160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19575 12:31:33.024678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19577 12:31:33.025148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19578 12:31:33.082277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19579 12:31:33.082708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19581 12:31:33.142815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19582 12:31:33.143280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19584 12:31:33.201528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19585 12:31:33.201984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19587 12:31:33.245137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19588 12:31:33.245525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19590 12:31:33.296323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19591 12:31:33.296784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19593 12:31:33.342129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19595 12:31:33.342616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19596 12:31:33.388740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19597 12:31:33.389130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19599 12:31:33.433716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19601 12:31:33.434188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19602 12:31:33.476726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19603 12:31:33.477228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19605 12:31:33.526574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19607 12:31:33.527224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19608 12:31:33.587512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19610 12:31:33.587969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19611 12:31:33.648005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19612 12:31:33.648515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19614 12:31:33.694254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19615 12:31:33.694709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19617 12:31:33.739021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19618 12:31:33.739454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19620 12:31:33.780518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19622 12:31:33.781269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19623 12:31:33.829410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19624 12:31:33.829799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19626 12:31:33.889699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19627 12:31:33.890087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19629 12:31:33.941229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19630 12:31:33.941669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19632 12:31:33.986556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19633 12:31:33.987020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19635 12:31:34.039565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19637 12:31:34.040219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19638 12:31:34.091309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19640 12:31:34.091776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19641 12:31:34.139421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19643 12:31:34.139901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19644 12:31:34.191331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19646 12:31:34.191840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19647 12:31:34.245724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19648 12:31:34.246146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19650 12:31:34.297265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19651 12:31:34.297694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19653 12:31:34.343008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19654 12:31:34.343502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19656 12:31:34.394215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19658 12:31:34.394650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19659 12:31:34.438564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19660 12:31:34.438952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19662 12:31:34.482634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19663 12:31:34.483114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19665 12:31:34.530617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19666 12:31:34.531058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19668 12:31:34.580597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19669 12:31:34.581063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19671 12:31:34.632371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19672 12:31:34.632837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19674 12:31:34.686486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19676 12:31:34.686919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19677 12:31:34.746797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19679 12:31:34.747251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19680 12:31:34.808593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19681 12:31:34.808977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19683 12:31:34.868529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19684 12:31:34.868959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19686 12:31:34.927500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19688 12:31:34.928271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19689 12:31:34.988145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19690 12:31:34.988515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19692 12:31:35.048762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19693 12:31:35.049143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19695 12:31:35.109541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19696 12:31:35.109965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19698 12:31:35.170561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19699 12:31:35.170985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19701 12:31:35.230629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19703 12:31:35.231109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19704 12:31:35.291014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19705 12:31:35.291411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19707 12:31:35.344821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19709 12:31:35.345332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19710 12:31:35.399331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19712 12:31:35.399799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19713 12:31:35.453428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19714 12:31:35.453878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19716 12:31:35.507956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19717 12:31:35.508366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19719 12:31:35.565211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19720 12:31:35.565695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19722 12:31:35.624508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19724 12:31:35.624969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19725 12:31:35.682539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19726 12:31:35.682974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19728 12:31:35.742252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19730 12:31:35.742713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19731 12:31:35.800697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19732 12:31:35.801119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19734 12:31:35.858255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19735 12:31:35.858730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19737 12:31:35.917064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19738 12:31:35.917500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19740 12:31:35.977234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19742 12:31:35.977724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19743 12:31:36.036075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19744 12:31:36.036518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19746 12:31:36.094430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19748 12:31:36.094907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19749 12:31:36.153366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19750 12:31:36.154110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19752 12:31:36.213171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19753 12:31:36.213609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19755 12:31:36.273298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19756 12:31:36.273792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19758 12:31:36.331135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19760 12:31:36.331615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19761 12:31:36.390470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19763 12:31:36.391752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19764 12:31:36.448889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19765 12:31:36.449282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19767 12:31:36.508541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19768 12:31:36.508982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19770 12:31:36.566610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19772 12:31:36.567076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19773 12:31:36.624677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19774 12:31:36.625120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19776 12:31:36.683530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19778 12:31:36.683982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19779 12:31:36.741721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19781 12:31:36.742203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19782 12:31:36.800228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19784 12:31:36.800611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19785 12:31:36.858070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19787 12:31:36.858537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19788 12:31:36.916579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19789 12:31:36.917036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19791 12:31:36.976171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19792 12:31:36.976569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19794 12:31:37.034673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19796 12:31:37.035101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19797 12:31:37.093865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19798 12:31:37.094296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19800 12:31:37.153172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19801 12:31:37.153607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19803 12:31:37.210837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19804 12:31:37.211271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19806 12:31:37.269378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19807 12:31:37.269820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19809 12:31:37.327419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19811 12:31:37.327864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19812 12:31:37.386784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19813 12:31:37.387200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19815 12:31:37.446063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19816 12:31:37.446498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19818 12:31:37.506906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19819 12:31:37.507347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19821 12:31:37.565606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19823 12:31:37.566391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19824 12:31:37.608604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19825 12:31:37.609059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19827 12:31:37.656620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19828 12:31:37.657044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19830 12:31:37.699794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19831 12:31:37.700251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19833 12:31:37.735426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19835 12:31:37.735916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19836 12:31:37.783958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19837 12:31:37.784407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19839 12:31:37.832678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19841 12:31:37.833109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19842 12:31:37.882338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19843 12:31:37.882733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19845 12:31:37.928404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19846 12:31:37.928778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19848 12:31:37.972368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19850 12:31:37.972829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19851 12:31:38.017254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19852 12:31:38.017694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19854 12:31:38.057790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19856 12:31:38.058266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19857 12:31:38.095562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19859 12:31:38.096269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19860 12:31:38.133706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19861 12:31:38.134232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19863 12:31:38.173476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19864 12:31:38.173879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19866 12:31:38.221115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19868 12:31:38.221547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19869 12:31:38.268327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19871 12:31:38.268815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19872 12:31:38.333261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19873 12:31:38.333691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19875 12:31:38.377058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19876 12:31:38.377508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19878 12:31:38.425440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19879 12:31:38.425878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19881 12:31:38.469837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19882 12:31:38.470269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19884 12:31:38.518868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19885 12:31:38.519291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19887 12:31:38.565802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19888 12:31:38.566244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19890 12:31:38.617777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19891 12:31:38.618337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19893 12:31:38.668210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19894 12:31:38.668785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19896 12:31:38.718748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19897 12:31:38.719217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19899 12:31:38.764068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19900 12:31:38.764478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19902 12:31:38.811980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19904 12:31:38.812782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19905 12:31:38.868033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19906 12:31:38.868496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19908 12:31:38.925044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19909 12:31:38.925481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19911 12:31:38.981443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19912 12:31:38.981880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19914 12:31:39.032668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19915 12:31:39.033107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19917 12:31:39.079889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19918 12:31:39.080352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19920 12:31:39.133264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19921 12:31:39.133700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19923 12:31:39.187945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19925 12:31:39.188389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19926 12:31:39.233142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19928 12:31:39.233615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19929 12:31:39.283074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19930 12:31:39.283492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19932 12:31:39.341223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19933 12:31:39.341660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19935 12:31:39.394978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19937 12:31:39.395583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19938 12:31:39.433347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19939 12:31:39.433833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19941 12:31:39.476159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19942 12:31:39.476591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19944 12:31:39.518011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19945 12:31:39.518381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19947 12:31:39.555362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19949 12:31:39.555833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19950 12:31:39.609894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19951 12:31:39.610352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19953 12:31:39.659948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19954 12:31:39.660409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19956 12:31:39.706479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19957 12:31:39.706924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19959 12:31:39.746304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19960 12:31:39.746748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19962 12:31:39.792365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19963 12:31:39.792804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19965 12:31:39.838607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19967 12:31:39.839106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19968 12:31:39.882173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19969 12:31:39.882588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19971 12:31:39.925335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19972 12:31:39.925739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19974 12:31:39.980022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19975 12:31:39.980417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19977 12:31:40.028583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19979 12:31:40.029352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19980 12:31:40.072542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
19982 12:31:40.072948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
19983 12:31:40.120862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
19984 12:31:40.121295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
19986 12:31:40.176991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
19987 12:31:40.177435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
19989 12:31:40.224414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
19990 12:31:40.224846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
19992 12:31:40.272211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
19994 12:31:40.272689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
19995 12:31:40.328488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
19996 12:31:40.328863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
19998 12:31:40.382770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
19999 12:31:40.383241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20001 12:31:40.436717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20002 12:31:40.437143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20004 12:31:40.484847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20005 12:31:40.485266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20007 12:31:40.540260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20008 12:31:40.540648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20010 12:31:40.589309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20012 12:31:40.589791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20013 12:31:40.637341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20014 12:31:40.637745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20016 12:31:40.693091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20018 12:31:40.693551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20019 12:31:40.734687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20020 12:31:40.735135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20022 12:31:40.774558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20023 12:31:40.774999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20025 12:31:40.822657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20026 12:31:40.823100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20028 12:31:40.881560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20029 12:31:40.882004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20031 12:31:40.939989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20033 12:31:40.940420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20034 12:31:40.985918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20035 12:31:40.986318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20037 12:31:41.034848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20039 12:31:41.035335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20040 12:31:41.094781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20041 12:31:41.095176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20043 12:31:41.149479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20045 12:31:41.149952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20046 12:31:41.194407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20048 12:31:41.194832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20049 12:31:41.243466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20051 12:31:41.244258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20052 12:31:41.293410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20054 12:31:41.293904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20055 12:31:41.354704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20056 12:31:41.355132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20058 12:31:41.412688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20060 12:31:41.413170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20061 12:31:41.460400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20062 12:31:41.460840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20064 12:31:41.504880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20065 12:31:41.505332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20067 12:31:41.548578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20068 12:31:41.549033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20070 12:31:41.594243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20071 12:31:41.594685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20073 12:31:41.642137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20074 12:31:41.642558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20076 12:31:41.694235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20077 12:31:41.694732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20079 12:31:41.747070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20081 12:31:41.747506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20082 12:31:41.806286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20083 12:31:41.806795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20085 12:31:41.865607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20086 12:31:41.866115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20088 12:31:41.924965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20089 12:31:41.925339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20091 12:31:41.984187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20092 12:31:41.984759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20094 12:31:42.024208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20095 12:31:42.024734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20097 12:31:42.070561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20098 12:31:42.070994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20100 12:31:42.110017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20102 12:31:42.110489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20103 12:31:42.149964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20105 12:31:42.150431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20106 12:31:42.191688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20107 12:31:42.192115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20109 12:31:42.229717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20110 12:31:42.230275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20112 12:31:42.268667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20114 12:31:42.269126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20115 12:31:42.315401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20117 12:31:42.315859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20118 12:31:42.371543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20120 12:31:42.372023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20121 12:31:42.420983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20123 12:31:42.421459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20124 12:31:42.462145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20126 12:31:42.462572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20127 12:31:42.516209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20128 12:31:42.516625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20130 12:31:42.562742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20131 12:31:42.563189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20133 12:31:42.622558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20134 12:31:42.623044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20136 12:31:42.673022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20137 12:31:42.673474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20139 12:31:42.721142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20140 12:31:42.721586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20142 12:31:42.759005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20143 12:31:42.759464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20145 12:31:42.809242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20146 12:31:42.809688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20148 12:31:42.851540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20150 12:31:42.852150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20151 12:31:42.900996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20152 12:31:42.901405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20154 12:31:42.942200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20155 12:31:42.942640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20157 12:31:42.985710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20158 12:31:42.986140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20160 12:31:43.029253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20161 12:31:43.029691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20163 12:31:43.085353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20164 12:31:43.085777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20166 12:31:43.130363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20167 12:31:43.130750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20169 12:31:43.171397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20171 12:31:43.171829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20172 12:31:43.226866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20173 12:31:43.227334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20175 12:31:43.273075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20176 12:31:43.273521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20178 12:31:43.318727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20179 12:31:43.319141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20181 12:31:43.368178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20182 12:31:43.368630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20184 12:31:43.441426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20185 12:31:43.441812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20187 12:31:43.495030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20188 12:31:43.495401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20190 12:31:43.541522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20191 12:31:43.541988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20193 12:31:43.579085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20194 12:31:43.579532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20196 12:31:43.622144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20198 12:31:43.622802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20199 12:31:43.665815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20200 12:31:43.666385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20202 12:31:43.704791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20204 12:31:43.705268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20205 12:31:43.753126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20206 12:31:43.753658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20208 12:31:43.805469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20209 12:31:43.805954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20211 12:31:43.856987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20212 12:31:43.857413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20214 12:31:43.909214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20215 12:31:43.909613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20217 12:31:43.948389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20218 12:31:43.948839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20220 12:31:43.989560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20221 12:31:43.990026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20223 12:31:44.032390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20225 12:31:44.032861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20226 12:31:44.085574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20227 12:31:44.085982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20229 12:31:44.134888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20230 12:31:44.135463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20232 12:31:44.178371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20233 12:31:44.178838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20235 12:31:44.223863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20236 12:31:44.224273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20238 12:31:44.269025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20239 12:31:44.269428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20241 12:31:44.311015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20243 12:31:44.311472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20244 12:31:44.358710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20245 12:31:44.359210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20247 12:31:44.401362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20248 12:31:44.401790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20250 12:31:44.445470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20252 12:31:44.445962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20253 12:31:44.485543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20254 12:31:44.485989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20256 12:31:44.533991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20257 12:31:44.534422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20259 12:31:44.584651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20260 12:31:44.585085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20262 12:31:44.626263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20264 12:31:44.626733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20265 12:31:44.672253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20266 12:31:44.672701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20268 12:31:44.710280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20269 12:31:44.710655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20271 12:31:44.748592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20272 12:31:44.749119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20274 12:31:44.787430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20276 12:31:44.787881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20277 12:31:44.833721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20278 12:31:44.834139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20280 12:31:44.872828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20282 12:31:44.873268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20283 12:31:44.910860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20285 12:31:44.911341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20286 12:31:44.949094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20288 12:31:44.949702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20289 12:31:44.987727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20291 12:31:44.988132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20292 12:31:45.027068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20294 12:31:45.027737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20295 12:31:45.070455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20296 12:31:45.070949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20298 12:31:45.113762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20299 12:31:45.114189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20301 12:31:45.155340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20303 12:31:45.155767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20304 12:31:45.201681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20305 12:31:45.202114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20307 12:31:45.252980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20308 12:31:45.253393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20310 12:31:45.296867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20311 12:31:45.297280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20313 12:31:45.339415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20315 12:31:45.340198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20316 12:31:45.378915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20317 12:31:45.379309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20319 12:31:45.419959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20320 12:31:45.420310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20322 12:31:45.473333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20323 12:31:45.473770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20325 12:31:45.520547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20326 12:31:45.520988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20328 12:31:45.570489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20329 12:31:45.570919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20331 12:31:45.616978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20332 12:31:45.617408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20334 12:31:45.661681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20336 12:31:45.662158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20337 12:31:45.707057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20338 12:31:45.707499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20340 12:31:45.756090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20342 12:31:45.756527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20343 12:31:45.814943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20344 12:31:45.815456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20346 12:31:45.874204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20347 12:31:45.874616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20349 12:31:45.934531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20351 12:31:45.935023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20352 12:31:45.993599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20353 12:31:45.994110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20355 12:31:46.054118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20356 12:31:46.054616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20358 12:31:46.113083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20360 12:31:46.113865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20361 12:31:46.171347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20363 12:31:46.171754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20364 12:31:46.229524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20365 12:31:46.229914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20367 12:31:46.288433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20368 12:31:46.288926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20370 12:31:46.332791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20371 12:31:46.333290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20373 12:31:46.372060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20374 12:31:46.372615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20376 12:31:46.412146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20378 12:31:46.412783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20379 12:31:46.454335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20380 12:31:46.454805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20382 12:31:46.494174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20384 12:31:46.494751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20385 12:31:46.533134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20387 12:31:46.533916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20388 12:31:46.572039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20389 12:31:46.572483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20391 12:31:46.621019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20392 12:31:46.621577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20394 12:31:46.673309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20395 12:31:46.673761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20397 12:31:46.730153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20398 12:31:46.730590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20400 12:31:46.787598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20402 12:31:46.788341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20403 12:31:46.845411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20404 12:31:46.845871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20406 12:31:46.901967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20408 12:31:46.902446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20409 12:31:46.960971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20410 12:31:46.961355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20412 12:31:47.018681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20414 12:31:47.019079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20415 12:31:47.078501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20416 12:31:47.078899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20418 12:31:47.137488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20419 12:31:47.137867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20421 12:31:47.193988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20423 12:31:47.194570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20424 12:31:47.252456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20425 12:31:47.252904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20427 12:31:47.303486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20429 12:31:47.303991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20430 12:31:47.360066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20432 12:31:47.360424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20433 12:31:47.417471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20435 12:31:47.417962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20436 12:31:47.474318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20437 12:31:47.474713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20439 12:31:47.524778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20440 12:31:47.525323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20442 12:31:47.574040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20444 12:31:47.574464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20445 12:31:47.629106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20446 12:31:47.629503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20448 12:31:47.675406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20450 12:31:47.676428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20451 12:31:47.725860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20453 12:31:47.726326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20454 12:31:47.770409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20455 12:31:47.770811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20457 12:31:47.829816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20458 12:31:47.830267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20460 12:31:47.873541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20461 12:31:47.873986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20463 12:31:47.934251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20464 12:31:47.934690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20466 12:31:47.989132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20467 12:31:47.989475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20469 12:31:48.033315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20470 12:31:48.033805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20472 12:31:48.076858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20473 12:31:48.077312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20475 12:31:48.121620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20476 12:31:48.122071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20478 12:31:48.162174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20479 12:31:48.162760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20481 12:31:48.205714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20482 12:31:48.206047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20484 12:31:48.251879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20485 12:31:48.252286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20487 12:31:48.312350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20489 12:31:48.312953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20490 12:31:48.369701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20491 12:31:48.370162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20493 12:31:48.424932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20495 12:31:48.425371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20496 12:31:48.486355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20497 12:31:48.486813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20499 12:31:48.570258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20500 12:31:48.570692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20502 12:31:48.612456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20503 12:31:48.612901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20505 12:31:48.654161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20507 12:31:48.654612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20508 12:31:48.701089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20509 12:31:48.701579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20511 12:31:48.754244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20512 12:31:48.754680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20514 12:31:48.805418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20515 12:31:48.805992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20517 12:31:48.849209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20519 12:31:48.849851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20520 12:31:48.897383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20521 12:31:48.897826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20523 12:31:48.946514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20524 12:31:48.947058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20526 12:31:48.996550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20528 12:31:48.997012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20529 12:31:49.052551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20531 12:31:49.052973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20532 12:31:49.098957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20533 12:31:49.099408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20535 12:31:49.149340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20536 12:31:49.149787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20538 12:31:49.200016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20539 12:31:49.200465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20541 12:31:49.246562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20542 12:31:49.247008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20544 12:31:49.293659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20545 12:31:49.294113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20547 12:31:49.344336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20549 12:31:49.344769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20550 12:31:49.392848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20551 12:31:49.393310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20553 12:31:49.438999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20554 12:31:49.439442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20556 12:31:49.483125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20557 12:31:49.483571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20559 12:31:49.529209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20560 12:31:49.529635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20562 12:31:49.582982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20563 12:31:49.583413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20565 12:31:49.641616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20566 12:31:49.642028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20568 12:31:49.694640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20569 12:31:49.695067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20571 12:31:49.744819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20572 12:31:49.745274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20574 12:31:49.788296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20575 12:31:49.788734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20577 12:31:49.831970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20578 12:31:49.832465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20580 12:31:49.882390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20581 12:31:49.882916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20583 12:31:49.933722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20585 12:31:49.934197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20586 12:31:49.981331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20588 12:31:49.981819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20589 12:31:50.029056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20591 12:31:50.029505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20592 12:31:50.084402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20594 12:31:50.085024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20595 12:31:50.145253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20596 12:31:50.145774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20598 12:31:50.206391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20599 12:31:50.206792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20601 12:31:50.250526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20602 12:31:50.250925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20604 12:31:50.290513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20605 12:31:50.290957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20607 12:31:50.333877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20609 12:31:50.334259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20610 12:31:50.375999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20611 12:31:50.376432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20613 12:31:50.418640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20615 12:31:50.419091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20616 12:31:50.465848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20617 12:31:50.466297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20619 12:31:50.512345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20620 12:31:50.512754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20622 12:31:50.549905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20623 12:31:50.550278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20625 12:31:50.588519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20626 12:31:50.588945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20628 12:31:50.632370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20630 12:31:50.633136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20631 12:31:50.677761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20633 12:31:50.678153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20634 12:31:50.715984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20635 12:31:50.716415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20637 12:31:50.756757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20638 12:31:50.757189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20640 12:31:50.797714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20642 12:31:50.798200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20643 12:31:50.845564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20644 12:31:50.846029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20646 12:31:50.888812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20647 12:31:50.889246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20649 12:31:50.927541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20651 12:31:50.928041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20652 12:31:50.974857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20653 12:31:50.975291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20655 12:31:51.017887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20656 12:31:51.018379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20658 12:31:51.060776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20659 12:31:51.061143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20661 12:31:51.107071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20663 12:31:51.107496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20664 12:31:51.148820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20665 12:31:51.149331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20667 12:31:51.188695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20668 12:31:51.189217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20670 12:31:51.229967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20672 12:31:51.230462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20673 12:31:51.234839 <47>[ 224.324672] systemd-journald[109]: Sent WATCHDOG=1 notification.
20674 12:31:51.290194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20676 12:31:51.290692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20677 12:31:51.333191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20678 12:31:51.333715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20680 12:31:51.380535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20682 12:31:51.380956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20683 12:31:51.422214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20685 12:31:51.422606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20686 12:31:51.464448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20687 12:31:51.464871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20689 12:31:51.516833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20691 12:31:51.517314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20692 12:31:51.560134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20694 12:31:51.560564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20695 12:31:51.608516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20696 12:31:51.608945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20698 12:31:51.649443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20699 12:31:51.649905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20701 12:31:51.689152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20703 12:31:51.689614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20704 12:31:51.738463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20705 12:31:51.738923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20707 12:31:51.781595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20708 12:31:51.782051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20710 12:31:51.820378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20711 12:31:51.820822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20713 12:31:51.858734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20715 12:31:51.859170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20716 12:31:51.893920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20717 12:31:51.894552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20719 12:31:51.936804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20720 12:31:51.937388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20722 12:31:51.980852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20724 12:31:51.981330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20725 12:31:52.025116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20726 12:31:52.025573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20728 12:31:52.071514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20730 12:31:52.072075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20731 12:31:52.120753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20732 12:31:52.121152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20734 12:31:52.172498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20735 12:31:52.172918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20737 12:31:52.226769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20739 12:31:52.227397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20740 12:31:52.270234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20741 12:31:52.270666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20743 12:31:52.320552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20744 12:31:52.321093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20746 12:31:52.360790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20747 12:31:52.361241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20749 12:31:52.404655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20750 12:31:52.405064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20752 12:31:52.444693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20753 12:31:52.445187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20755 12:31:52.488420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20756 12:31:52.488841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20758 12:31:52.529610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20759 12:31:52.530055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20761 12:31:52.569116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20762 12:31:52.569545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20764 12:31:52.614891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20765 12:31:52.615309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20767 12:31:52.656582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20769 12:31:52.657015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20770 12:31:52.704339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20771 12:31:52.704916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20773 12:31:52.753375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20774 12:31:52.753794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20776 12:31:52.803408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20778 12:31:52.803846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20779 12:31:52.855005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20780 12:31:52.855457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20782 12:31:52.902891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20784 12:31:52.903385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20785 12:31:52.951101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20787 12:31:52.951586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20788 12:31:52.997983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20789 12:31:52.998426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20791 12:31:53.044716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20793 12:31:53.045146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20794 12:31:53.094010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20795 12:31:53.094439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20797 12:31:53.138819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20798 12:31:53.139229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20800 12:31:53.185255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20802 12:31:53.185703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20803 12:31:53.233468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20805 12:31:53.233959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20806 12:31:53.285381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20808 12:31:53.285874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20809 12:31:53.335497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20811 12:31:53.335962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20812 12:31:53.387015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20813 12:31:53.387414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20815 12:31:53.448759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20816 12:31:53.449153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20818 12:31:53.493416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20819 12:31:53.493861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20821 12:31:53.531012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20822 12:31:53.531448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20824 12:31:53.570052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20825 12:31:53.570433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20827 12:31:53.615954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20828 12:31:53.616333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20830 12:31:53.683499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20832 12:31:53.684908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20833 12:31:53.730709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20835 12:31:53.731184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20836 12:31:53.777096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20837 12:31:53.777558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20839 12:31:53.817741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20840 12:31:53.818198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20842 12:31:53.862702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20843 12:31:53.863283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20845 12:31:53.904273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20846 12:31:53.904664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20848 12:31:53.944770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20849 12:31:53.945192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20851 12:31:53.986817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20852 12:31:53.987215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20854 12:31:54.026312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20855 12:31:54.026770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20857 12:31:54.068637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20858 12:31:54.069074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20860 12:31:54.107563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20862 12:31:54.108130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20863 12:31:54.158867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20864 12:31:54.159315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20866 12:31:54.209721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20867 12:31:54.210143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20869 12:31:54.254151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20870 12:31:54.254542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20872 12:31:54.295480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20874 12:31:54.295905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20875 12:31:54.343273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20877 12:31:54.343760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20878 12:31:54.384862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20879 12:31:54.385240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20881 12:31:54.425541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20883 12:31:54.426035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20884 12:31:54.471275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20886 12:31:54.471842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20887 12:31:54.516814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20888 12:31:54.517304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20890 12:31:54.567439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20892 12:31:54.567969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20893 12:31:54.616957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20894 12:31:54.617442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20896 12:31:54.659031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20897 12:31:54.659467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20899 12:31:54.704165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20900 12:31:54.704619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20902 12:31:54.750531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20903 12:31:54.750957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20905 12:31:54.791798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20907 12:31:54.792285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20908 12:31:54.830117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20910 12:31:54.830554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20911 12:31:54.870433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20912 12:31:54.870876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20914 12:31:54.918307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20915 12:31:54.918713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20917 12:31:54.959539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20919 12:31:54.960021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20920 12:31:55.007579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20922 12:31:55.008097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20923 12:31:55.052997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20924 12:31:55.053416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20926 12:31:55.100816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20928 12:31:55.101252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20929 12:31:55.144028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20930 12:31:55.144457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20932 12:31:55.189905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20933 12:31:55.190350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20935 12:31:55.237323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20936 12:31:55.237736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20938 12:31:55.285994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20939 12:31:55.286406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20941 12:31:55.341263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20942 12:31:55.341672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20944 12:31:55.389005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20945 12:31:55.389398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20947 12:31:55.434730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20948 12:31:55.435163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20950 12:31:55.477881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20951 12:31:55.478236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20953 12:31:55.522241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20954 12:31:55.522637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20956 12:31:55.562898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20957 12:31:55.563334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20959 12:31:55.609199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20960 12:31:55.609662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20962 12:31:55.652851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20963 12:31:55.653260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20965 12:31:55.698123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20967 12:31:55.698544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20968 12:31:55.743289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20970 12:31:55.743753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20971 12:31:55.796015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20972 12:31:55.796457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20974 12:31:55.850811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20975 12:31:55.851303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20977 12:31:55.896203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20978 12:31:55.896646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20980 12:31:55.942769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
20981 12:31:55.943203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
20983 12:31:55.999682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
20984 12:31:56.000068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
20986 12:31:56.054892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
20988 12:31:56.055372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
20989 12:31:56.101975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
20991 12:31:56.102451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
20992 12:31:56.149692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
20993 12:31:56.150123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
20995 12:31:56.191001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
20996 12:31:56.191417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
20998 12:31:56.234496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
20999 12:31:56.234922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21001 12:31:56.278722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21003 12:31:56.279216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21004 12:31:56.327356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21006 12:31:56.327830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21007 12:31:56.370794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21008 12:31:56.371153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21010 12:31:56.417542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21011 12:31:56.417981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21013 12:31:56.474489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21014 12:31:56.474922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21016 12:31:56.528670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21017 12:31:56.529066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21019 12:31:56.574424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21020 12:31:56.574844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21022 12:31:56.620189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21024 12:31:56.620658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21025 12:31:56.665453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21027 12:31:56.665941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21028 12:31:56.707486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21030 12:31:56.708103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21031 12:31:56.748592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21032 12:31:56.749092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21034 12:31:56.793903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21035 12:31:56.794279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21037 12:31:56.841165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21038 12:31:56.841597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21040 12:31:56.885635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21042 12:31:56.886063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21043 12:31:56.925814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21044 12:31:56.926310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21046 12:31:56.973818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21047 12:31:56.974315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21049 12:31:57.035512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21051 12:31:57.036536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21052 12:31:57.089760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21053 12:31:57.090158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21055 12:31:57.149425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21057 12:31:57.149924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21058 12:31:57.203305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21060 12:31:57.203799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21061 12:31:57.245100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21062 12:31:57.245539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21064 12:31:57.297555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21065 12:31:57.297982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21067 12:31:57.347825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21068 12:31:57.348258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21070 12:31:57.390527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21072 12:31:57.391298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21073 12:31:57.450449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21074 12:31:57.450903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21076 12:31:57.496407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21077 12:31:57.496838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21079 12:31:57.538930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21080 12:31:57.539371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21082 12:31:57.588697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21083 12:31:57.589124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21085 12:31:57.639408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21087 12:31:57.639883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21088 12:31:57.685539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21089 12:31:57.686115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21091 12:31:57.733076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21092 12:31:57.733574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21094 12:31:57.778172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21095 12:31:57.778626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21097 12:31:57.821192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21098 12:31:57.821628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21100 12:31:57.863761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21101 12:31:57.864290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21103 12:31:57.904857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21104 12:31:57.905291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21106 12:31:57.961727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21107 12:31:57.962165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21109 12:31:58.024005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21110 12:31:58.024467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21112 12:31:58.074345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21114 12:31:58.074831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21115 12:31:58.124277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21116 12:31:58.124716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21118 12:31:58.174294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21120 12:31:58.174776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21121 12:31:58.234715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21123 12:31:58.235201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21124 12:31:58.294258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21125 12:31:58.294802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21127 12:31:58.352084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21128 12:31:58.352511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21130 12:31:58.401896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21132 12:31:58.402562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21133 12:31:58.446582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21134 12:31:58.447008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21136 12:31:58.493088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21137 12:31:58.493541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21139 12:31:58.543381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21141 12:31:58.543866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21142 12:31:58.592963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21144 12:31:58.593443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21145 12:31:58.645611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21146 12:31:58.646056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21148 12:31:58.688033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21149 12:31:58.688483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21151 12:31:58.730732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21152 12:31:58.731178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21154 12:31:58.797231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21155 12:31:58.797698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21157 12:31:58.850633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21158 12:31:58.851125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21160 12:31:58.903458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21162 12:31:58.903923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21163 12:31:58.946379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21165 12:31:58.947089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21166 12:31:59.001868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21167 12:31:59.002318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21169 12:31:59.052095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21170 12:31:59.052523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21172 12:31:59.102384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21173 12:31:59.102860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21175 12:31:59.153360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21177 12:31:59.153873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21178 12:31:59.212736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21179 12:31:59.213143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21181 12:31:59.264482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21182 12:31:59.264917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21184 12:31:59.317480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21185 12:31:59.317977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21187 12:31:59.365943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21189 12:31:59.366398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21190 12:31:59.426567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21191 12:31:59.426999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21193 12:31:59.479361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21195 12:31:59.479980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21196 12:31:59.524489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21197 12:31:59.524902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21199 12:31:59.568417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21200 12:31:59.568808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21202 12:31:59.621857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21204 12:31:59.622604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21205 12:31:59.665463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21206 12:31:59.665901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21208 12:31:59.706873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21210 12:31:59.707317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21211 12:31:59.750941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21213 12:31:59.751374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21214 12:31:59.802973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21215 12:31:59.803413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21217 12:31:59.858815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21218 12:31:59.859237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21220 12:31:59.914517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21221 12:31:59.914915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21223 12:31:59.961476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21224 12:31:59.961985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21226 12:32:00.013839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21227 12:32:00.014268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21229 12:32:00.057962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21230 12:32:00.058412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21232 12:32:00.100867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21234 12:32:00.101313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21235 12:32:00.145991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21236 12:32:00.146381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21238 12:32:00.198005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21240 12:32:00.198729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21241 12:32:00.246363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21243 12:32:00.246750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21244 12:32:00.294361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21245 12:32:00.294789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21247 12:32:00.340734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21248 12:32:00.341205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21250 12:32:00.395254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21252 12:32:00.395685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21253 12:32:00.445936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21255 12:32:00.446415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21256 12:32:00.489221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21258 12:32:00.489619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21259 12:32:00.533983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21260 12:32:00.534421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21262 12:32:00.584782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21263 12:32:00.585223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21265 12:32:00.633197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21266 12:32:00.633630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21268 12:32:00.678754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21269 12:32:00.679215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21271 12:32:00.730110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21272 12:32:00.730549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21274 12:32:00.775990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21276 12:32:00.776759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21277 12:32:00.817636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21278 12:32:00.818090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21280 12:32:00.866092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21281 12:32:00.866492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21283 12:32:00.910416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21284 12:32:00.910854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21286 12:32:00.952969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21288 12:32:00.953523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21289 12:32:00.996991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21291 12:32:00.997407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21292 12:32:01.044306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21293 12:32:01.044825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21295 12:32:01.092979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21297 12:32:01.093423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21298 12:32:01.141981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21299 12:32:01.142393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21301 12:32:01.193945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21302 12:32:01.194350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21304 12:32:01.242896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21305 12:32:01.243290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21307 12:32:01.286501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21308 12:32:01.286935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21310 12:32:01.342405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21311 12:32:01.342852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21313 12:32:01.400814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21314 12:32:01.401283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21316 12:32:01.451489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21318 12:32:01.452012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21319 12:32:01.493431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21321 12:32:01.493942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21322 12:32:01.536768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21323 12:32:01.537204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21325 12:32:01.578257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21327 12:32:01.578730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21328 12:32:01.619045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21329 12:32:01.619482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21331 12:32:01.673029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21332 12:32:01.673467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21334 12:32:01.725600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21335 12:32:01.726028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21337 12:32:01.769913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21338 12:32:01.770333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21340 12:32:01.814614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21341 12:32:01.815061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21343 12:32:01.865826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21344 12:32:01.866272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21346 12:32:01.927053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21348 12:32:01.927541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21349 12:32:01.986741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21350 12:32:01.987193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21352 12:32:02.054337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21353 12:32:02.054832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21355 12:32:02.116212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21357 12:32:02.116663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21358 12:32:02.175035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21360 12:32:02.175670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21361 12:32:02.236224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21362 12:32:02.236611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21364 12:32:02.297189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21365 12:32:02.297685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21367 12:32:02.350106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21368 12:32:02.350682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21370 12:32:02.396801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21371 12:32:02.397163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21373 12:32:02.438858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21375 12:32:02.439279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21376 12:32:02.492919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21377 12:32:02.493319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21379 12:32:02.546376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21381 12:32:02.547037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21382 12:32:02.598000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21383 12:32:02.598585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21385 12:32:02.646207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21386 12:32:02.646617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21388 12:32:02.695471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21390 12:32:02.695963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21391 12:32:02.748701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21392 12:32:02.749134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21394 12:32:02.794065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21395 12:32:02.794473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21397 12:32:02.837579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21399 12:32:02.838049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21400 12:32:02.885610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21401 12:32:02.886077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21403 12:32:02.944025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21405 12:32:02.944425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21406 12:32:02.998646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21407 12:32:02.999066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21409 12:32:03.053617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21410 12:32:03.054073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21412 12:32:03.098110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21413 12:32:03.098519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21415 12:32:03.150941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21416 12:32:03.151354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21418 12:32:03.204974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21420 12:32:03.205469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21421 12:32:03.248652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21423 12:32:03.249135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21424 12:32:03.292463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21425 12:32:03.292892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21427 12:32:03.335173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21429 12:32:03.335674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21430 12:32:03.381006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21431 12:32:03.381434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21433 12:32:03.425504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21434 12:32:03.426065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21436 12:32:03.473010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21437 12:32:03.473450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21439 12:32:03.516507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21440 12:32:03.516955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21442 12:32:03.562912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21443 12:32:03.563365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21445 12:32:03.608643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21446 12:32:03.609076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21448 12:32:03.648651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21449 12:32:03.649084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21451 12:32:03.697131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21452 12:32:03.697571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21454 12:32:03.738974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21455 12:32:03.739439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21457 12:32:03.797850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21459 12:32:03.798338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21460 12:32:03.841430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21462 12:32:03.841906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21463 12:32:03.909979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21464 12:32:03.910418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21466 12:32:03.966933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21467 12:32:03.967395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21469 12:32:04.018988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21470 12:32:04.019423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21472 12:32:04.069531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21473 12:32:04.070132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21475 12:32:04.123952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21477 12:32:04.124429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21478 12:32:04.168439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21479 12:32:04.168864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21481 12:32:04.217707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21483 12:32:04.218170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21484 12:32:04.270643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21485 12:32:04.271059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21487 12:32:04.323365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21489 12:32:04.323847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21490 12:32:04.367285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21491 12:32:04.367753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21493 12:32:04.422094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21494 12:32:04.422485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21496 12:32:04.474407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21497 12:32:04.474935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21499 12:32:04.534299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21500 12:32:04.534854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21502 12:32:04.593935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21504 12:32:04.594416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21505 12:32:04.654286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21506 12:32:04.654687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21508 12:32:04.714159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21509 12:32:04.714624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21511 12:32:04.772215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21512 12:32:04.772647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21514 12:32:04.817133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21515 12:32:04.817764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21517 12:32:04.860066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21518 12:32:04.860480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21520 12:32:04.905066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21521 12:32:04.905493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21523 12:32:04.948363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21524 12:32:04.948831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21526 12:32:05.006102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21527 12:32:05.006560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21529 12:32:05.051393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21531 12:32:05.051868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21532 12:32:05.104710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21533 12:32:05.105131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21535 12:32:05.153494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21536 12:32:05.153897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21538 12:32:05.208667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21539 12:32:05.209124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21541 12:32:05.260589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21542 12:32:05.261007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21544 12:32:05.305137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21545 12:32:05.305566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21547 12:32:05.351044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21548 12:32:05.351433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21550 12:32:05.390591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21551 12:32:05.391012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21553 12:32:05.434646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21554 12:32:05.435073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21556 12:32:05.482115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21557 12:32:05.482579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21559 12:32:05.536830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21560 12:32:05.537563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21562 12:32:05.585871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21563 12:32:05.586324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21565 12:32:05.634298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21566 12:32:05.634755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21568 12:32:05.682425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21569 12:32:05.682891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21571 12:32:05.728556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21572 12:32:05.728989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21574 12:32:05.782432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21575 12:32:05.782819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21577 12:32:05.837066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21579 12:32:05.837555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21580 12:32:05.880126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21581 12:32:05.880598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21583 12:32:05.937562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21584 12:32:05.937991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21586 12:32:05.990290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21587 12:32:05.990711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21589 12:32:06.041382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21590 12:32:06.041820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21592 12:32:06.089027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21593 12:32:06.089424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21595 12:32:06.137373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21596 12:32:06.137800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21598 12:32:06.178743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21600 12:32:06.179171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21601 12:32:06.222077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21602 12:32:06.222530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21604 12:32:06.266945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21605 12:32:06.267404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21607 12:32:06.322666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21608 12:32:06.323095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21610 12:32:06.364628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21611 12:32:06.365065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21613 12:32:06.407353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21615 12:32:06.407850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21616 12:32:06.456339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21617 12:32:06.456833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21619 12:32:06.497596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21621 12:32:06.498090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21622 12:32:06.540159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21623 12:32:06.540722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21625 12:32:06.579154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21627 12:32:06.579747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21628 12:32:06.620944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21629 12:32:06.621395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21631 12:32:06.668833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21632 12:32:06.669267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21634 12:32:06.711063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21635 12:32:06.711607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21637 12:32:06.749567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21638 12:32:06.750090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21640 12:32:06.794105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21641 12:32:06.794521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21643 12:32:06.845084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21645 12:32:06.845719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21646 12:32:06.890132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21647 12:32:06.890547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21649 12:32:06.941706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21650 12:32:06.942149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21652 12:32:06.990382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21653 12:32:06.990821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21655 12:32:07.034758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21656 12:32:07.035141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21658 12:32:07.088226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21659 12:32:07.088630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21661 12:32:07.145070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21662 12:32:07.145529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21664 12:32:07.202208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21665 12:32:07.202623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21667 12:32:07.261275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21669 12:32:07.261923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21670 12:32:07.305087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21671 12:32:07.305537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21673 12:32:07.351888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21674 12:32:07.352302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21676 12:32:07.392685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21677 12:32:07.393100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21679 12:32:07.439415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21681 12:32:07.439877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21682 12:32:07.497729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21683 12:32:07.498167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21685 12:32:07.556773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21687 12:32:07.557226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21688 12:32:07.607022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21689 12:32:07.607419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21691 12:32:07.646757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21692 12:32:07.647263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21694 12:32:07.694376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21695 12:32:07.694834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21697 12:32:07.740213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21698 12:32:07.740660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21700 12:32:07.786581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21702 12:32:07.787284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21703 12:32:07.828852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21704 12:32:07.829287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21706 12:32:07.872696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21707 12:32:07.873133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21709 12:32:07.909781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21710 12:32:07.910210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21712 12:32:07.950149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21713 12:32:07.950582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21715 12:32:07.993671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21716 12:32:07.994118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21718 12:32:08.037049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21719 12:32:08.037510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21721 12:32:08.088737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21722 12:32:08.089127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21724 12:32:08.138321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21725 12:32:08.138712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21727 12:32:08.181518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21728 12:32:08.181971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21730 12:32:08.225983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21731 12:32:08.226415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21733 12:32:08.274339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21734 12:32:08.274702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21736 12:32:08.314581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21737 12:32:08.314995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21739 12:32:08.358733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21740 12:32:08.359148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21742 12:32:08.408597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21743 12:32:08.409016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21745 12:32:08.452760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21746 12:32:08.453229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21748 12:32:08.502583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21749 12:32:08.503008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21751 12:32:08.545016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21752 12:32:08.545476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21754 12:32:08.596336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21755 12:32:08.596779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21757 12:32:08.645212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21759 12:32:08.645718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21760 12:32:08.690634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21762 12:32:08.691259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21763 12:32:08.738716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21764 12:32:08.739154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21766 12:32:08.788445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21767 12:32:08.788899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21769 12:32:08.836372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21771 12:32:08.836808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21772 12:32:08.881081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21773 12:32:08.881478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21775 12:32:08.920899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21777 12:32:08.921373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21778 12:32:08.959939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21779 12:32:08.960366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21781 12:32:08.998462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21782 12:32:08.998992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21784 12:32:09.053867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21785 12:32:09.054296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21787 12:32:09.095319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21789 12:32:09.095796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21790 12:32:09.139051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21791 12:32:09.139481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21793 12:32:09.178883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21794 12:32:09.179293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21796 12:32:09.230272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21797 12:32:09.230715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21799 12:32:09.282673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21800 12:32:09.283129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21802 12:32:09.330303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21803 12:32:09.330748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21805 12:32:09.370264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21806 12:32:09.370698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21808 12:32:09.410411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21809 12:32:09.410836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21811 12:32:09.449927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21813 12:32:09.450431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21814 12:32:09.496060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21815 12:32:09.496479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21817 12:32:09.538229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21819 12:32:09.538940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21820 12:32:09.580090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21821 12:32:09.580527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21823 12:32:09.621530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21824 12:32:09.622006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21826 12:32:09.682286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21827 12:32:09.682705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21829 12:32:09.744268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21830 12:32:09.744702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21832 12:32:09.794293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21833 12:32:09.794668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21835 12:32:09.841080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21836 12:32:09.841473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21838 12:32:09.897848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21839 12:32:09.898294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21841 12:32:09.944896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21842 12:32:09.945296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21844 12:32:09.993684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21846 12:32:09.994082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21847 12:32:10.036363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21848 12:32:10.036782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21850 12:32:10.085765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21851 12:32:10.086234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21853 12:32:10.127945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21854 12:32:10.128319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21856 12:32:10.177685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21857 12:32:10.178075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21859 12:32:10.232601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21860 12:32:10.232976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21862 12:32:10.286829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21863 12:32:10.287249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21865 12:32:10.329886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21866 12:32:10.330331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21868 12:32:10.376205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21869 12:32:10.376588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21871 12:32:10.421340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21872 12:32:10.421780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21874 12:32:10.469395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21876 12:32:10.469830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21877 12:32:10.521051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21878 12:32:10.521490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21880 12:32:10.562051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21881 12:32:10.562508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21883 12:32:10.620578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21884 12:32:10.621086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21886 12:32:10.682068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21887 12:32:10.682468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21889 12:32:10.733106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21891 12:32:10.733868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21892 12:32:10.782689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21893 12:32:10.783087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21895 12:32:10.838224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21896 12:32:10.838631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21898 12:32:10.885405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21899 12:32:10.885819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21901 12:32:10.940786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21902 12:32:10.941358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21904 12:32:10.984507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21906 12:32:10.985266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21907 12:32:11.036495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21908 12:32:11.036895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21910 12:32:11.084407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21911 12:32:11.084872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21913 12:32:11.136183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21915 12:32:11.136680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21916 12:32:11.178227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21917 12:32:11.178687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21919 12:32:11.223859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21920 12:32:11.224288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21922 12:32:11.273713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21923 12:32:11.274108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21925 12:32:11.321835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21926 12:32:11.322315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21928 12:32:11.374786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21929 12:32:11.375225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21931 12:32:11.429363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21932 12:32:11.429808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21934 12:32:11.479140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21935 12:32:11.479581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21937 12:32:11.523245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21939 12:32:11.523748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21940 12:32:11.564128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21941 12:32:11.564562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21943 12:32:11.605272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21944 12:32:11.605692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21946 12:32:11.653570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21947 12:32:11.654019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21949 12:32:11.698205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21950 12:32:11.698605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21952 12:32:11.750252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21953 12:32:11.750650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21955 12:32:11.802415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21957 12:32:11.803103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21958 12:32:11.854524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21959 12:32:11.854906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21961 12:32:11.909807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21962 12:32:11.910268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21964 12:32:11.957692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21965 12:32:11.958124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21967 12:32:11.997239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21969 12:32:11.997735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21970 12:32:12.040372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21971 12:32:12.040798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21973 12:32:12.080991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21974 12:32:12.081415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21976 12:32:12.121351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21977 12:32:12.121743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21979 12:32:12.162833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21980 12:32:12.163291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
21982 12:32:12.208873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
21984 12:32:12.209364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
21985 12:32:12.250769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
21986 12:32:12.251214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
21988 12:32:12.297191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
21990 12:32:12.297696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
21991 12:32:12.349140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
21993 12:32:12.349624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
21994 12:32:12.390148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
21995 12:32:12.390576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
21997 12:32:12.430938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
21999 12:32:12.431420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22000 12:32:12.470713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22002 12:32:12.471188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22003 12:32:12.510818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22004 12:32:12.511253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22006 12:32:12.552105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22007 12:32:12.552581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22009 12:32:12.593127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22010 12:32:12.593641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22012 12:32:12.633597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22014 12:32:12.634315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22015 12:32:12.674847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22016 12:32:12.675293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22018 12:32:12.718729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22019 12:32:12.719164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22021 12:32:12.772832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22023 12:32:12.773284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22024 12:32:12.824387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22025 12:32:12.824795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22027 12:32:12.877513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22028 12:32:12.877912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22030 12:32:12.931032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22031 12:32:12.931430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22033 12:32:12.983551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22035 12:32:12.984207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22036 12:32:13.025613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22037 12:32:13.026045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22039 12:32:13.069235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22040 12:32:13.069661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22042 12:32:13.117189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22044 12:32:13.117983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22045 12:32:13.159955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22046 12:32:13.160460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22048 12:32:13.205765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22049 12:32:13.206182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22051 12:32:13.245236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22053 12:32:13.245729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22054 12:32:13.290933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22055 12:32:13.291374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22057 12:32:13.337610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22059 12:32:13.338056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22060 12:32:13.386114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22061 12:32:13.386513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22063 12:32:13.433164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22064 12:32:13.433565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22066 12:32:13.476199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22067 12:32:13.476604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22069 12:32:13.516974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22071 12:32:13.517451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22072 12:32:13.560855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22073 12:32:13.561212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22075 12:32:13.606695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22076 12:32:13.607129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22078 12:32:13.650282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22079 12:32:13.650711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22081 12:32:13.690844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22082 12:32:13.691289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22084 12:32:13.736754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22085 12:32:13.737193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22087 12:32:13.780449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22089 12:32:13.780882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22090 12:32:13.821013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22092 12:32:13.821410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22093 12:32:13.874822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22094 12:32:13.875336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22096 12:32:13.927600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22098 12:32:13.928213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22099 12:32:13.980784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22100 12:32:13.981234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22102 12:32:14.028254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22104 12:32:14.028741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22105 12:32:14.077349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22107 12:32:14.077808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22108 12:32:14.117882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22109 12:32:14.118330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22111 12:32:14.194852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22112 12:32:14.195267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22114 12:32:14.254870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22115 12:32:14.255344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22117 12:32:14.313607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22118 12:32:14.314056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22120 12:32:14.372698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22121 12:32:14.373082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22123 12:32:14.418235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22125 12:32:14.418721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22126 12:32:14.466472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22128 12:32:14.466887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22129 12:32:14.510270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22131 12:32:14.510730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22132 12:32:14.553830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22134 12:32:14.554265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22135 12:32:14.608128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22136 12:32:14.608558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22138 12:32:14.650310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22139 12:32:14.650728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22141 12:32:14.697979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22142 12:32:14.698391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22144 12:32:14.750848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22145 12:32:14.751244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22147 12:32:14.806101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22148 12:32:14.806550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22150 12:32:14.856712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22151 12:32:14.857150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22153 12:32:14.914017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22154 12:32:14.914487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22156 12:32:14.972492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22158 12:32:14.972959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22159 12:32:15.014929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22160 12:32:15.015372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22162 12:32:15.057304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22164 12:32:15.057805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22165 12:32:15.097928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22167 12:32:15.098402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22168 12:32:15.139334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22170 12:32:15.139816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22171 12:32:15.182709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22173 12:32:15.183186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22174 12:32:15.224028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22176 12:32:15.224506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22177 12:32:15.264492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22179 12:32:15.264958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22180 12:32:15.322652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22181 12:32:15.323101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22183 12:32:15.377903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22184 12:32:15.378338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22186 12:32:15.433207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22187 12:32:15.433634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22189 12:32:15.481372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22190 12:32:15.481763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22192 12:32:15.522335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22193 12:32:15.522867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22195 12:32:15.562339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22196 12:32:15.562706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22198 12:32:15.622225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22200 12:32:15.622890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22201 12:32:15.682720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22202 12:32:15.683130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22204 12:32:15.733474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22205 12:32:15.733916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22207 12:32:15.776421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22209 12:32:15.777076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22210 12:32:15.821297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22211 12:32:15.821690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22213 12:32:15.867687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22214 12:32:15.868121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22216 12:32:15.908694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22218 12:32:15.909186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22219 12:32:15.949581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22220 12:32:15.949990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22222 12:32:15.990202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22223 12:32:15.990595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22225 12:32:16.030098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22226 12:32:16.030530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22228 12:32:16.070901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22229 12:32:16.071342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22231 12:32:16.112930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22233 12:32:16.113401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22234 12:32:16.154484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22236 12:32:16.154924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22237 12:32:16.205451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22238 12:32:16.205888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22240 12:32:16.261985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22242 12:32:16.262463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22243 12:32:16.320231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22245 12:32:16.320707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22246 12:32:16.379070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22247 12:32:16.379521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22249 12:32:16.437814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22250 12:32:16.438211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22252 12:32:16.497696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22253 12:32:16.498189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22255 12:32:16.558466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22256 12:32:16.558855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22258 12:32:16.599058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22260 12:32:16.599543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22261 12:32:16.656406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22263 12:32:16.656923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22264 12:32:16.694679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22265 12:32:16.695114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22267 12:32:16.734310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22268 12:32:16.734708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22270 12:32:16.777064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22272 12:32:16.777533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22273 12:32:16.821944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22275 12:32:16.822422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22276 12:32:16.866209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22278 12:32:16.866674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22279 12:32:16.927666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22281 12:32:16.928117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22282 12:32:16.967341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22284 12:32:16.967925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22285 12:32:17.008455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22287 12:32:17.008914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22288 12:32:17.050439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22289 12:32:17.051530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22291 12:32:17.092740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22293 12:32:17.093196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22294 12:32:17.142574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22295 12:32:17.143011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22297 12:32:17.195808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22298 12:32:17.196672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22300 12:32:17.238369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22301 12:32:17.238797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22303 12:32:17.285185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22304 12:32:17.285625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22306 12:32:17.341379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22307 12:32:17.341908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22309 12:32:17.388285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22311 12:32:17.388727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22312 12:32:17.438244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22313 12:32:17.438655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22315 12:32:17.487694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22317 12:32:17.488193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22318 12:32:17.538573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22319 12:32:17.539043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22321 12:32:17.586823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22322 12:32:17.587284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22324 12:32:17.630019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22325 12:32:17.630477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22327 12:32:17.680891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22328 12:32:17.681327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22330 12:32:17.729468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22332 12:32:17.729952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22333 12:32:17.772929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22334 12:32:17.773328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22336 12:32:17.830811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22337 12:32:17.831251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22339 12:32:17.873773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22340 12:32:17.874209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22342 12:32:17.915262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22343 12:32:17.915721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22345 12:32:17.957536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22346 12:32:17.957952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22348 12:32:18.005259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22349 12:32:18.005698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22351 12:32:18.058996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22352 12:32:18.059383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22354 12:32:18.110968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22355 12:32:18.111395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22357 12:32:18.161196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22358 12:32:18.161637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22360 12:32:18.210688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22361 12:32:18.211109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22363 12:32:18.259349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22365 12:32:18.259798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22366 12:32:18.300789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22367 12:32:18.301225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22369 12:32:18.348096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22370 12:32:18.348535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22372 12:32:18.390022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22374 12:32:18.390514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22375 12:32:18.432896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22376 12:32:18.433320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22378 12:32:18.479530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22380 12:32:18.480189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22381 12:32:18.529299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22382 12:32:18.529690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22384 12:32:18.580958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22385 12:32:18.581378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22387 12:32:18.623930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22388 12:32:18.624334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22390 12:32:18.668321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22391 12:32:18.668730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22393 12:32:18.717940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22395 12:32:18.718433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22396 12:32:18.765976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22397 12:32:18.766416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22399 12:32:18.809656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22400 12:32:18.810088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22402 12:32:18.855148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22404 12:32:18.855599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22405 12:32:18.905662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22406 12:32:18.906066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22408 12:32:18.953748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22409 12:32:18.954200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22411 12:32:18.995058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22412 12:32:18.995488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22414 12:32:19.038723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22416 12:32:19.039211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22417 12:32:19.084794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22418 12:32:19.085215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22420 12:32:19.133600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22421 12:32:19.134052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22423 12:32:19.176256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22424 12:32:19.176690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22426 12:32:19.225097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22427 12:32:19.225541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22429 12:32:19.301277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22430 12:32:19.301692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22432 12:32:19.363494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22434 12:32:19.363962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22435 12:32:19.426104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22436 12:32:19.426543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22438 12:32:19.481522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22439 12:32:19.481933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22441 12:32:19.536058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22442 12:32:19.536510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22444 12:32:19.585661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22445 12:32:19.586093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22447 12:32:19.638919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22448 12:32:19.639341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22450 12:32:19.695739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22451 12:32:19.696143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22453 12:32:19.755158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22454 12:32:19.755619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22456 12:32:19.810282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22457 12:32:19.810722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22459 12:32:19.857447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22460 12:32:19.857893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22462 12:32:19.904652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22463 12:32:19.905111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22465 12:32:19.965270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22466 12:32:19.965690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22468 12:32:20.026819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22469 12:32:20.027230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22471 12:32:20.081848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22472 12:32:20.082283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22474 12:32:20.133798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22475 12:32:20.134273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22477 12:32:20.187111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22478 12:32:20.187557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22480 12:32:20.236680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22481 12:32:20.237121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22483 12:32:20.290486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22484 12:32:20.290928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22486 12:32:20.348778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22487 12:32:20.349171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22489 12:32:20.404719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22490 12:32:20.405178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22492 12:32:20.466284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22493 12:32:20.466731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22495 12:32:20.521126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22497 12:32:20.521612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22498 12:32:20.572627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22500 12:32:20.573374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22501 12:32:20.633805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22502 12:32:20.634207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22504 12:32:20.697879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22505 12:32:20.698350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22507 12:32:20.750508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22508 12:32:20.750950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22510 12:32:20.805069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22511 12:32:20.805476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22513 12:32:20.857871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22514 12:32:20.858340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22516 12:32:20.912850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22517 12:32:20.913273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22519 12:32:20.958511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22521 12:32:20.959037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22522 12:32:21.027480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22524 12:32:21.028071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22525 12:32:21.080210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22526 12:32:21.080639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22528 12:32:21.126250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22529 12:32:21.126686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22531 12:32:21.173990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22533 12:32:21.174455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22534 12:32:21.221401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22535 12:32:21.221886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22537 12:32:21.265161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22538 12:32:21.265601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22540 12:32:21.321626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22541 12:32:21.322072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22543 12:32:21.369465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22544 12:32:21.369965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22546 12:32:21.433108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22548 12:32:21.433552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22549 12:32:21.481690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22550 12:32:21.482121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22552 12:32:21.536090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22553 12:32:21.536504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22555 12:32:21.576966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22556 12:32:21.577373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22558 12:32:21.630682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22560 12:32:21.631141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22561 12:32:21.682799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22562 12:32:21.683287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22564 12:32:21.733725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22565 12:32:21.734160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22567 12:32:21.783251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22569 12:32:21.784041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22570 12:32:21.831183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22572 12:32:21.831672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22573 12:32:21.878782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22574 12:32:21.879208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22576 12:32:21.938201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22577 12:32:21.938640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22579 12:32:21.995274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22581 12:32:21.995753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22582 12:32:22.040814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22583 12:32:22.041324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22585 12:32:22.084694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22586 12:32:22.085097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22588 12:32:22.125957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22589 12:32:22.126387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22591 12:32:22.177608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22592 12:32:22.177988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22594 12:32:22.223128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22596 12:32:22.223568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22597 12:32:22.262630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22598 12:32:22.263075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22600 12:32:22.305512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22601 12:32:22.306011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22603 12:32:22.362541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22604 12:32:22.363004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22606 12:32:22.402303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22607 12:32:22.402757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22609 12:32:22.450120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22610 12:32:22.450554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22612 12:32:22.503963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22613 12:32:22.504392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22615 12:32:22.547481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22617 12:32:22.548001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22618 12:32:22.590248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22620 12:32:22.590676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22621 12:32:22.634435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22622 12:32:22.634877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22624 12:32:22.680737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22625 12:32:22.681173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22627 12:32:22.720624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22628 12:32:22.721089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22630 12:32:22.766308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22631 12:32:22.766744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22633 12:32:22.812940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22634 12:32:22.813329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22636 12:32:22.857344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22637 12:32:22.857740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22639 12:32:22.910790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22640 12:32:22.911167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22642 12:32:22.961614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22643 12:32:22.962137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22645 12:32:23.008810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22646 12:32:23.009223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22648 12:32:23.058406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22649 12:32:23.058836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22651 12:32:23.110870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22652 12:32:23.111318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22654 12:32:23.165943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22655 12:32:23.166403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22657 12:32:23.217802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22658 12:32:23.218213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22660 12:32:23.261110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22661 12:32:23.261577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22663 12:32:23.309564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22664 12:32:23.310015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22666 12:32:23.358245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22667 12:32:23.358686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22669 12:32:23.406093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22670 12:32:23.406563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22672 12:32:23.459338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22674 12:32:23.459930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22675 12:32:23.510813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22676 12:32:23.511243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22678 12:32:23.554924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22679 12:32:23.555336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22681 12:32:23.602209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22683 12:32:23.602841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22684 12:32:23.648449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22685 12:32:23.648883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22687 12:32:23.697514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22688 12:32:23.698045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22690 12:32:23.750492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22691 12:32:23.750899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22693 12:32:23.804694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22694 12:32:23.805096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22696 12:32:23.854521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22697 12:32:23.854967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22699 12:32:23.908970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22700 12:32:23.909388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22702 12:32:23.962110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22703 12:32:23.962517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22705 12:32:24.013973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22706 12:32:24.014410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22708 12:32:24.064945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22709 12:32:24.065356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22711 12:32:24.105024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22712 12:32:24.105473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22714 12:32:24.150684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22716 12:32:24.151141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22717 12:32:24.195497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22719 12:32:24.196082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22720 12:32:24.255525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22722 12:32:24.255972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22723 12:32:24.302757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22725 12:32:24.303232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22726 12:32:24.352664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22727 12:32:24.353221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22729 12:32:24.428537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22730 12:32:24.428988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22732 12:32:24.480875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22733 12:32:24.481269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22735 12:32:24.532949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22736 12:32:24.533365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22738 12:32:24.587886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22739 12:32:24.588290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22741 12:32:24.633881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22743 12:32:24.634328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22744 12:32:24.679488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22746 12:32:24.679977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22747 12:32:24.726188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22748 12:32:24.726738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22750 12:32:24.780870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22751 12:32:24.781346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22753 12:32:24.834806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22755 12:32:24.835303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22756 12:32:24.882528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22758 12:32:24.883131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22759 12:32:24.921384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22760 12:32:24.921785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22762 12:32:24.961364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22764 12:32:24.961863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22765 12:32:25.016279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22767 12:32:25.016982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22768 12:32:25.065814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22769 12:32:25.066368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22771 12:32:25.111776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22773 12:32:25.112247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22774 12:32:25.158859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22775 12:32:25.159259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22777 12:32:25.208575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22778 12:32:25.209108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22780 12:32:25.258036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22781 12:32:25.258620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22783 12:32:25.308862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22785 12:32:25.309301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22786 12:32:25.365358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22787 12:32:25.365775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22789 12:32:25.412498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22790 12:32:25.412898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22792 12:32:25.462860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22794 12:32:25.463336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22795 12:32:25.510544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22796 12:32:25.510959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22798 12:32:25.558893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22799 12:32:25.559309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22801 12:32:25.621273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22803 12:32:25.621771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22804 12:32:25.680592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22805 12:32:25.681000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22807 12:32:25.740435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22808 12:32:25.740875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22810 12:32:25.801678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22811 12:32:25.802123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22813 12:32:25.862080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22814 12:32:25.862480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22816 12:32:25.913787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22818 12:32:25.914274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22819 12:32:25.960814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22820 12:32:25.961256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22822 12:32:26.005434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22824 12:32:26.005965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22825 12:32:26.046894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22826 12:32:26.047401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22828 12:32:26.092823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22830 12:32:26.093431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22831 12:32:26.139169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22833 12:32:26.139663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22834 12:32:26.189284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22835 12:32:26.189704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22837 12:32:26.234563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22838 12:32:26.235006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22840 12:32:26.274750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22841 12:32:26.275160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22843 12:32:26.314176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22845 12:32:26.314650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22846 12:32:26.360499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22847 12:32:26.360924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22849 12:32:26.412017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22850 12:32:26.412445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22852 12:32:26.466925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22853 12:32:26.467362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22855 12:32:26.516186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22856 12:32:26.516625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22858 12:32:26.563435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22860 12:32:26.564350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22861 12:32:26.613356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22862 12:32:26.613795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22864 12:32:26.664444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22865 12:32:26.664884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22867 12:32:26.714682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22868 12:32:26.715099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22870 12:32:26.774564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22872 12:32:26.775047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22873 12:32:26.836282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22874 12:32:26.836728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22876 12:32:26.893772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22877 12:32:26.894162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22879 12:32:26.940042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22880 12:32:26.940482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22882 12:32:26.987099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22883 12:32:26.987544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22885 12:32:27.034656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22886 12:32:27.035242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22888 12:32:27.078754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22889 12:32:27.079264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22891 12:32:27.121737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22892 12:32:27.122298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22894 12:32:27.165295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22895 12:32:27.165694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22897 12:32:27.214199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22898 12:32:27.214585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22900 12:32:27.273865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22901 12:32:27.274359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22903 12:32:27.328174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22905 12:32:27.328612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22906 12:32:27.377064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22907 12:32:27.377493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22909 12:32:27.418984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22910 12:32:27.419449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22912 12:32:27.470203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22913 12:32:27.470628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22915 12:32:27.519031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22916 12:32:27.519428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22918 12:32:27.566679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22919 12:32:27.567109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22921 12:32:27.617866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22923 12:32:27.618328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22924 12:32:27.665572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22925 12:32:27.665998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22927 12:32:27.705626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22928 12:32:27.706040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22930 12:32:27.745869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22931 12:32:27.746322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22933 12:32:27.791144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22935 12:32:27.791538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22936 12:32:27.840371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22937 12:32:27.840803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22939 12:32:27.892743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22941 12:32:27.893231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22942 12:32:27.934743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22944 12:32:27.935222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22945 12:32:27.987093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22946 12:32:27.987488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22948 12:32:28.037917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22949 12:32:28.038363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22951 12:32:28.094481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22952 12:32:28.094858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22954 12:32:28.155993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22955 12:32:28.156396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22957 12:32:28.195093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22958 12:32:28.195513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22960 12:32:28.236758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22962 12:32:28.237208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22963 12:32:28.296315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22964 12:32:28.296703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22966 12:32:28.355595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22968 12:32:28.356048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22969 12:32:28.397640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22970 12:32:28.398102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22972 12:32:28.441797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22973 12:32:28.442231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22975 12:32:28.480567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22976 12:32:28.480999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22978 12:32:28.524860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
22979 12:32:28.525416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22981 12:32:28.569610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
22982 12:32:28.570133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
22984 12:32:28.615430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
22986 12:32:28.616073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
22987 12:32:28.661896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
22988 12:32:28.662331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
22990 12:32:28.708783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
22991 12:32:28.709220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
22993 12:32:28.754939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
22994 12:32:28.755370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
22996 12:32:28.805877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
22997 12:32:28.806333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
22999 12:32:28.853620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23000 12:32:28.854200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23002 12:32:28.893361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23004 12:32:28.894130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23005 12:32:28.940863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23006 12:32:28.941308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23008 12:32:28.989862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23009 12:32:28.990434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23011 12:32:29.045803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23012 12:32:29.046295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23014 12:32:29.101080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23015 12:32:29.101674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23017 12:32:29.152829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23018 12:32:29.153286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23020 12:32:29.202729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23021 12:32:29.203310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23023 12:32:29.241481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23024 12:32:29.242003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23026 12:32:29.281700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23027 12:32:29.282280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23029 12:32:29.326816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23030 12:32:29.327393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23032 12:32:29.377883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23034 12:32:29.378382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23035 12:32:29.422381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23036 12:32:29.422835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23038 12:32:29.472780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23039 12:32:29.473147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23041 12:32:29.546097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23042 12:32:29.546496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23044 12:32:29.597035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23046 12:32:29.597697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23047 12:32:29.648482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23048 12:32:29.648887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23050 12:32:29.695342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23052 12:32:29.695835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23053 12:32:29.752927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23054 12:32:29.753321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23056 12:32:29.806404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23057 12:32:29.806847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23059 12:32:29.844311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23060 12:32:29.844710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23062 12:32:29.891063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23063 12:32:29.891472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23065 12:32:29.936855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23066 12:32:29.937318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23068 12:32:29.985421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23070 12:32:29.985904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23071 12:32:30.033396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23072 12:32:30.033785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23074 12:32:30.077148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23075 12:32:30.077569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23077 12:32:30.130773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23079 12:32:30.131281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23080 12:32:30.179489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23082 12:32:30.179940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23083 12:32:30.232910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23084 12:32:30.233411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23086 12:32:30.280144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23087 12:32:30.280552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23089 12:32:30.330913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23091 12:32:30.331362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23092 12:32:30.384357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23093 12:32:30.384748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23095 12:32:30.435237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23097 12:32:30.435747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23098 12:32:30.496600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23099 12:32:30.497010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23101 12:32:30.551126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23103 12:32:30.551615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23104 12:32:30.609025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23105 12:32:30.609475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23107 12:32:30.670628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23108 12:32:30.671080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23110 12:32:30.732646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23111 12:32:30.733049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23113 12:32:30.792798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23114 12:32:30.793186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23116 12:32:30.854051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23117 12:32:30.854461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23119 12:32:30.915085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23120 12:32:30.915519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23122 12:32:30.977416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23124 12:32:30.978122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23125 12:32:31.037784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23127 12:32:31.038283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23128 12:32:31.085293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23129 12:32:31.085692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23131 12:32:31.132833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23133 12:32:31.133446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23134 12:32:31.177746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23136 12:32:31.178436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23137 12:32:31.228544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23139 12:32:31.228931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23140 12:32:31.280069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23142 12:32:31.280552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23143 12:32:31.327008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23144 12:32:31.327433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23146 12:32:31.377082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23147 12:32:31.377474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23149 12:32:31.425402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23150 12:32:31.425830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23152 12:32:31.486006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23153 12:32:31.486401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23155 12:32:31.546162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23157 12:32:31.546545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23158 12:32:31.598557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23159 12:32:31.598960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23161 12:32:31.644870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23162 12:32:31.645305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23164 12:32:31.682459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23165 12:32:31.682887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23167 12:32:31.724527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23168 12:32:31.724965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23170 12:32:31.772775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23171 12:32:31.773171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23173 12:32:31.820988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23174 12:32:31.821400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23176 12:32:31.869977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23177 12:32:31.870381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23179 12:32:31.917246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23180 12:32:31.917676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23182 12:32:31.959023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23183 12:32:31.959469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23185 12:32:32.006833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23187 12:32:32.007598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23188 12:32:32.051889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23189 12:32:32.052293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23191 12:32:32.098867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23192 12:32:32.099314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23194 12:32:32.141411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23196 12:32:32.141905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23197 12:32:32.181361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23199 12:32:32.182022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23200 12:32:32.224774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23201 12:32:32.225279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23203 12:32:32.277669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23204 12:32:32.278099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23206 12:32:32.330509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23207 12:32:32.330936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23209 12:32:32.371776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23210 12:32:32.372164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23212 12:32:32.420993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23213 12:32:32.421439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23215 12:32:32.468987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23216 12:32:32.469517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23218 12:32:32.515896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23219 12:32:32.516354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23221 12:32:32.558418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23222 12:32:32.558939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23224 12:32:32.601516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23225 12:32:32.601959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23227 12:32:32.650294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23228 12:32:32.650734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23230 12:32:32.696680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23231 12:32:32.697139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23233 12:32:32.747155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23235 12:32:32.747561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23236 12:32:32.792651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23237 12:32:32.793089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23239 12:32:32.849328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23240 12:32:32.849784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23242 12:32:32.897406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23243 12:32:32.897860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23245 12:32:32.955514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23247 12:32:32.956232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23248 12:32:33.013722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23249 12:32:33.014156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23251 12:32:33.073095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23252 12:32:33.073562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23254 12:32:33.132489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23255 12:32:33.132881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23257 12:32:33.192782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23259 12:32:33.193297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23260 12:32:33.252264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23261 12:32:33.252655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23263 12:32:33.312225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23264 12:32:33.312626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23266 12:32:33.370785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23267 12:32:33.371227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23269 12:32:33.429777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23270 12:32:33.430217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23272 12:32:33.490063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23273 12:32:33.490485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23275 12:32:33.550128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23276 12:32:33.550632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23278 12:32:33.608888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23279 12:32:33.609324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23281 12:32:33.658869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23282 12:32:33.659258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23284 12:32:33.700111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23285 12:32:33.700547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23287 12:32:33.752580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23288 12:32:33.753009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23290 12:32:33.794847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23291 12:32:33.795291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23293 12:32:33.848194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23294 12:32:33.848685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23296 12:32:33.891106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23297 12:32:33.891495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23299 12:32:33.942193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23300 12:32:33.942656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23302 12:32:33.985219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23303 12:32:33.985602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23305 12:32:34.029685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23306 12:32:34.030247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23308 12:32:34.076091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23309 12:32:34.076533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23311 12:32:34.123371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23313 12:32:34.123853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23314 12:32:34.162161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23315 12:32:34.162588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23317 12:32:34.200778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23318 12:32:34.201310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23320 12:32:34.241497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23321 12:32:34.241952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23323 12:32:34.283530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23325 12:32:34.284016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23326 12:32:34.327426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23328 12:32:34.327907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23329 12:32:34.375035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23330 12:32:34.375469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23332 12:32:34.418860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23333 12:32:34.419306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23335 12:32:34.464889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23336 12:32:34.465347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23338 12:32:34.512466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23340 12:32:34.512954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23341 12:32:34.563753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23343 12:32:34.564227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23344 12:32:34.627415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23346 12:32:34.627807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23347 12:32:34.673776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23349 12:32:34.674160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23350 12:32:34.716932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23351 12:32:34.717362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23353 12:32:34.768698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23354 12:32:34.769119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23356 12:32:34.822333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23358 12:32:34.822804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23359 12:32:34.878227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23360 12:32:34.878641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23362 12:32:34.934709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23364 12:32:34.935211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23365 12:32:34.985203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23367 12:32:34.985581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23368 12:32:35.025528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23369 12:32:35.025970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23371 12:32:35.069235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23372 12:32:35.069683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23374 12:32:35.120370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23375 12:32:35.120741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23377 12:32:35.180779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23379 12:32:35.181363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23380 12:32:35.238721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23381 12:32:35.239162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23383 12:32:35.288562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23384 12:32:35.288999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23386 12:32:35.336675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23387 12:32:35.337094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23389 12:32:35.394868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23390 12:32:35.395323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23392 12:32:35.446612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23393 12:32:35.447026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23395 12:32:35.504236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23396 12:32:35.504657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23398 12:32:35.560045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23399 12:32:35.560567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23401 12:32:35.606399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23402 12:32:35.606822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23404 12:32:35.654501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23406 12:32:35.654951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23407 12:32:35.694679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23408 12:32:35.695253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23410 12:32:35.743329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23412 12:32:35.743798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23413 12:32:35.799798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23414 12:32:35.800216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23416 12:32:35.845262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23417 12:32:35.845668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23419 12:32:35.886081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23420 12:32:35.886486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23422 12:32:35.931513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23424 12:32:35.932452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23425 12:32:35.983084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23427 12:32:35.983793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23428 12:32:36.030305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23430 12:32:36.030781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23431 12:32:36.077272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23432 12:32:36.077630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23434 12:32:36.119566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23436 12:32:36.120044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23437 12:32:36.169263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23439 12:32:36.169728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23440 12:32:36.219434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23442 12:32:36.220067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23443 12:32:36.269106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23444 12:32:36.269614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23446 12:32:36.306500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23447 12:32:36.307050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23449 12:32:36.354952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23450 12:32:36.355389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23452 12:32:36.397952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23454 12:32:36.398632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23455 12:32:36.438341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23457 12:32:36.438807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23458 12:32:36.478405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23459 12:32:36.478850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23461 12:32:36.524366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23463 12:32:36.525224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23464 12:32:36.568391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23465 12:32:36.568833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23467 12:32:36.627870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23468 12:32:36.628327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23470 12:32:36.685939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23472 12:32:36.686385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23473 12:32:36.741333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23474 12:32:36.741767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23476 12:32:36.784191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23477 12:32:36.784649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23479 12:32:36.824465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23480 12:32:36.824879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23482 12:32:36.869713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23483 12:32:36.870146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23485 12:32:36.915160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23486 12:32:36.915586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23488 12:32:36.957565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23489 12:32:36.958006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23491 12:32:37.003414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23493 12:32:37.003832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23494 12:32:37.050474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23495 12:32:37.050887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23497 12:32:37.094047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23498 12:32:37.094485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23500 12:32:37.141481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23501 12:32:37.142062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23503 12:32:37.185186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23504 12:32:37.185596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23506 12:32:37.220668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23507 12:32:37.221109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23509 12:32:37.265397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23510 12:32:37.265914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23512 12:32:37.308802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23513 12:32:37.309239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23515 12:32:37.346269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23517 12:32:37.346933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23518 12:32:37.384122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23520 12:32:37.384600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23521 12:32:37.438502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23523 12:32:37.438966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23524 12:32:37.490181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23525 12:32:37.490614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23527 12:32:37.541894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23528 12:32:37.542309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23530 12:32:37.592275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23531 12:32:37.592653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23533 12:32:37.636509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23534 12:32:37.636957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23536 12:32:37.675440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23538 12:32:37.675923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23539 12:32:37.720132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23540 12:32:37.720555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23542 12:32:37.765089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23543 12:32:37.765465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23545 12:32:37.810577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23547 12:32:37.811049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23548 12:32:37.851507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23550 12:32:37.851962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23551 12:32:37.895508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23553 12:32:37.897867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23554 12:32:37.938512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23555 12:32:37.938941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23557 12:32:37.981448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23558 12:32:37.981912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23560 12:32:38.024449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23562 12:32:38.024918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23563 12:32:38.069269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23565 12:32:38.070059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23566 12:32:38.117333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23567 12:32:38.117782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23569 12:32:38.160937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23570 12:32:38.161367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23572 12:32:38.205701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23574 12:32:38.206197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23575 12:32:38.258959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23576 12:32:38.259408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23578 12:32:38.302219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23580 12:32:38.302690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23581 12:32:38.340787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23583 12:32:38.341259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23584 12:32:38.382655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23586 12:32:38.383105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23587 12:32:38.429181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23588 12:32:38.429598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23590 12:32:38.466887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23592 12:32:38.467376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23593 12:32:38.506486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23594 12:32:38.506959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23596 12:32:38.545419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23597 12:32:38.545930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23599 12:32:38.596734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23600 12:32:38.597279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23602 12:32:38.644469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23603 12:32:38.644918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23605 12:32:38.686452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23607 12:32:38.686951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23608 12:32:38.733206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23609 12:32:38.733721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23611 12:32:38.778601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23613 12:32:38.779268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23614 12:32:38.824445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23615 12:32:38.824858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23617 12:32:38.865474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23618 12:32:38.865938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23620 12:32:38.909010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23621 12:32:38.909450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23623 12:32:38.956948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23624 12:32:38.957386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23626 12:32:39.001991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23628 12:32:39.002529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23629 12:32:39.042712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23631 12:32:39.043204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23632 12:32:39.091197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23634 12:32:39.091680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23635 12:32:39.133677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23636 12:32:39.134127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23638 12:32:39.174819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23640 12:32:39.175391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23641 12:32:39.213967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23643 12:32:39.214397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23644 12:32:39.251809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23645 12:32:39.252241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23647 12:32:39.291962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23648 12:32:39.292404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23650 12:32:39.332448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23652 12:32:39.333261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23653 12:32:39.374572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23654 12:32:39.374965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23656 12:32:39.427016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23657 12:32:39.427460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23659 12:32:39.482466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23660 12:32:39.482917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23662 12:32:39.532333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23663 12:32:39.532756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23665 12:32:39.575370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23667 12:32:39.575870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23668 12:32:39.619172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23669 12:32:39.619617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23671 12:32:39.675408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23673 12:32:39.676146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23674 12:32:39.720668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23675 12:32:39.721060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23677 12:32:39.788947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23678 12:32:39.789385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23680 12:32:39.832622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23681 12:32:39.833194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23683 12:32:39.875376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23685 12:32:39.875859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23686 12:32:39.914735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23687 12:32:39.915164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23689 12:32:39.963085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23690 12:32:39.963477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23692 12:32:40.006508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23693 12:32:40.006944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23695 12:32:40.054824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23696 12:32:40.055211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23698 12:32:40.106237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23699 12:32:40.106712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23701 12:32:40.148280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23703 12:32:40.148776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23704 12:32:40.186896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23706 12:32:40.187386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23707 12:32:40.231047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23708 12:32:40.231515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23710 12:32:40.272607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23712 12:32:40.273088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23713 12:32:40.313656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23714 12:32:40.314118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23716 12:32:40.352749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23717 12:32:40.353214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23719 12:32:40.400859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23720 12:32:40.401298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23722 12:32:40.445157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23723 12:32:40.445570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23725 12:32:40.494757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23726 12:32:40.495176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23728 12:32:40.537019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23729 12:32:40.537503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23731 12:32:40.575933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23732 12:32:40.576351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23734 12:32:40.630153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23735 12:32:40.630550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23737 12:32:40.677335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23739 12:32:40.677766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23740 12:32:40.714193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23741 12:32:40.714639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23743 12:32:40.756717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23744 12:32:40.757151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23746 12:32:40.797973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23747 12:32:40.798397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23749 12:32:40.839390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23751 12:32:40.839857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23752 12:32:40.881443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23753 12:32:40.881904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23755 12:32:40.932488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23756 12:32:40.932898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23758 12:32:40.976734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23759 12:32:40.977172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23761 12:32:41.015016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23762 12:32:41.015448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23764 12:32:41.068792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23765 12:32:41.069230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23767 12:32:41.124991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23768 12:32:41.125452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23770 12:32:41.183346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23772 12:32:41.183964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23773 12:32:41.228422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23774 12:32:41.228884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23776 12:32:41.283955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23777 12:32:41.284366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23779 12:32:41.328122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23780 12:32:41.328562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23782 12:32:41.376713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23784 12:32:41.377377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23785 12:32:41.426991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23787 12:32:41.427437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23788 12:32:41.472859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23789 12:32:41.473290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23791 12:32:41.514559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23792 12:32:41.514953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23794 12:32:41.557130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23795 12:32:41.557534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23797 12:32:41.596735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23799 12:32:41.597204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23800 12:32:41.641718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23802 12:32:41.642200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23803 12:32:41.687064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23805 12:32:41.687551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23806 12:32:41.724881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23807 12:32:41.725306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23809 12:32:41.770026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23810 12:32:41.770414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23812 12:32:41.809538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23814 12:32:41.810052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23815 12:32:41.848479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23816 12:32:41.848878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23818 12:32:41.886568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23820 12:32:41.887012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23821 12:32:41.932447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23823 12:32:41.932909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23824 12:32:41.980485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23826 12:32:41.981160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23827 12:32:42.020016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23828 12:32:42.020448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23830 12:32:42.056992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23831 12:32:42.057420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23833 12:32:42.100978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23834 12:32:42.101528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23836 12:32:42.156950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23837 12:32:42.157346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23839 12:32:42.213792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23840 12:32:42.214237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23842 12:32:42.265024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23843 12:32:42.265461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23845 12:32:42.308317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23846 12:32:42.308832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23848 12:32:42.349526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23849 12:32:42.349955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23851 12:32:42.389844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23852 12:32:42.390241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23854 12:32:42.441155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23855 12:32:42.441633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23857 12:32:42.489358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23858 12:32:42.489903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23860 12:32:42.537117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23861 12:32:42.537546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23863 12:32:42.585705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23864 12:32:42.586138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23866 12:32:42.636555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23867 12:32:42.637005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23869 12:32:42.680453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23870 12:32:42.680972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23872 12:32:42.725475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23874 12:32:42.725969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23875 12:32:42.769994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23876 12:32:42.770428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23878 12:32:42.816313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23879 12:32:42.816715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23881 12:32:42.852767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23882 12:32:42.853173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23884 12:32:42.889690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23886 12:32:42.890174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23887 12:32:42.931059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23888 12:32:42.931483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23890 12:32:42.972580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23891 12:32:42.973033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23893 12:32:43.018713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23894 12:32:43.019123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23896 12:32:43.055631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23898 12:32:43.056232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23899 12:32:43.097626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23900 12:32:43.098067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23902 12:32:43.142431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23903 12:32:43.142851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23905 12:32:43.192413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23906 12:32:43.192837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23908 12:32:43.238758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23909 12:32:43.239209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23911 12:32:43.286786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23912 12:32:43.287181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23914 12:32:43.324166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23915 12:32:43.324561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23917 12:32:43.364780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23918 12:32:43.365158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23920 12:32:43.401981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23921 12:32:43.402424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23923 12:32:43.440771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23924 12:32:43.441256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23926 12:32:43.477557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23927 12:32:43.478001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23929 12:32:43.516056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23930 12:32:43.516446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23932 12:32:43.552241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23934 12:32:43.553009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23935 12:32:43.600997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23937 12:32:43.601475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23938 12:32:43.646062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23940 12:32:43.646538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23941 12:32:43.686410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23943 12:32:43.686795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23944 12:32:43.730718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23945 12:32:43.731123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23947 12:32:43.782794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23948 12:32:43.783229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23950 12:32:43.837684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23951 12:32:43.838118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23953 12:32:43.895160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23954 12:32:43.895602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23956 12:32:43.953339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23957 12:32:43.953792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23959 12:32:43.992608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23960 12:32:43.993097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23962 12:32:44.040199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23963 12:32:44.040659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23965 12:32:44.086109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23966 12:32:44.086533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23968 12:32:44.125189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23970 12:32:44.125621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23971 12:32:44.166836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23972 12:32:44.167254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23974 12:32:44.205096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23976 12:32:44.205572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23977 12:32:44.241810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23978 12:32:44.242244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23980 12:32:44.277718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
23982 12:32:44.278195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
23983 12:32:44.314880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
23984 12:32:44.315318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
23986 12:32:44.352465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
23987 12:32:44.352890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
23989 12:32:44.393776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
23990 12:32:44.394278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
23992 12:32:44.433142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
23993 12:32:44.433658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
23995 12:32:44.475379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
23997 12:32:44.476166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
23998 12:32:44.517221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24000 12:32:44.517736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24001 12:32:44.569415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24002 12:32:44.569889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24004 12:32:44.614136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24005 12:32:44.614565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24007 12:32:44.658856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24009 12:32:44.659357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24010 12:32:44.710272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24011 12:32:44.710779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24013 12:32:44.760006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24014 12:32:44.760460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24016 12:32:44.809926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24017 12:32:44.810391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24019 12:32:44.877316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24020 12:32:44.877752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24022 12:32:44.918803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24023 12:32:44.919240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24025 12:32:44.968248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24026 12:32:44.968661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24028 12:32:45.017883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24029 12:32:45.018318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24031 12:32:45.069296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24032 12:32:45.069719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24034 12:32:45.115263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24036 12:32:45.115738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24037 12:32:45.158086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24039 12:32:45.158556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24040 12:32:45.199271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24042 12:32:45.199778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24043 12:32:45.240593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24044 12:32:45.241026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24046 12:32:45.281343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24047 12:32:45.281742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24049 12:32:45.325122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24050 12:32:45.325553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24052 12:32:45.367153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24053 12:32:45.367622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24055 12:32:45.408684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24056 12:32:45.409095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24058 12:32:45.451021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24059 12:32:45.451492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24061 12:32:45.498757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24062 12:32:45.499147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24064 12:32:45.543975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24065 12:32:45.544417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24067 12:32:45.592785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24068 12:32:45.593197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24070 12:32:45.637344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24071 12:32:45.637823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24073 12:32:45.683559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24075 12:32:45.684054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24076 12:32:45.723900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24077 12:32:45.724292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24079 12:32:45.762189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24080 12:32:45.762611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24082 12:32:45.802689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24083 12:32:45.803091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24085 12:32:45.838473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24087 12:32:45.838977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24088 12:32:45.874227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24089 12:32:45.874659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24091 12:32:45.912564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24092 12:32:45.913002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24094 12:32:45.949687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24095 12:32:45.950122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24097 12:32:45.993469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24098 12:32:45.993916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24100 12:32:46.034651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24102 12:32:46.035032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24103 12:32:46.076959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24104 12:32:46.077367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24106 12:32:46.119102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24108 12:32:46.119578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24109 12:32:46.162954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24111 12:32:46.163435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24112 12:32:46.208403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24113 12:32:46.208836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24115 12:32:46.245965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24117 12:32:46.246637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24118 12:32:46.293828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24119 12:32:46.294240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24121 12:32:46.347254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24123 12:32:46.347750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24124 12:32:46.390883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24125 12:32:46.391352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24127 12:32:46.435554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24129 12:32:46.436047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24130 12:32:46.481634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24131 12:32:46.482098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24133 12:32:46.526964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24135 12:32:46.527432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24136 12:32:46.576773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24137 12:32:46.577206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24139 12:32:46.626530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24141 12:32:46.627200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24142 12:32:46.669011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24144 12:32:46.669497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24145 12:32:46.713753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24146 12:32:46.714163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24148 12:32:46.766519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24149 12:32:46.766916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24151 12:32:46.822500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24152 12:32:46.822936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24154 12:32:46.869839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24156 12:32:46.870316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24157 12:32:46.914358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24158 12:32:46.914779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24160 12:32:46.953225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24161 12:32:46.953690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24163 12:32:46.998768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24164 12:32:46.999201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24166 12:32:47.053682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24168 12:32:47.054170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24169 12:32:47.104677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24170 12:32:47.105133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24172 12:32:47.150064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24173 12:32:47.150553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24175 12:32:47.194026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24176 12:32:47.194421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24178 12:32:47.252217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24179 12:32:47.252607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24181 12:32:47.310963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24182 12:32:47.311409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24184 12:32:47.365817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24185 12:32:47.366263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24187 12:32:47.408833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24188 12:32:47.409256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24190 12:32:47.454275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24192 12:32:47.454664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24193 12:32:47.501712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24194 12:32:47.502131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24196 12:32:47.546807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24197 12:32:47.547213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24199 12:32:47.593589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24200 12:32:47.593997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24202 12:32:47.642986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24203 12:32:47.643550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24205 12:32:47.684353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24206 12:32:47.684739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24208 12:32:47.734723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24209 12:32:47.735133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24211 12:32:47.775231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24213 12:32:47.775792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24214 12:32:47.821388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24215 12:32:47.821838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24217 12:32:47.865561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24218 12:32:47.866002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24220 12:32:47.911546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24222 12:32:47.912017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24223 12:32:47.958258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24224 12:32:47.958657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24226 12:32:48.005021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24227 12:32:48.005414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24229 12:32:48.046814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24230 12:32:48.047280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24232 12:32:48.088829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24233 12:32:48.089306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24235 12:32:48.137737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24236 12:32:48.138192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24238 12:32:48.185860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24239 12:32:48.186287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24241 12:32:48.238022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24242 12:32:48.238482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24244 12:32:48.282654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24245 12:32:48.283099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24247 12:32:48.329240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24248 12:32:48.329786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24250 12:32:48.384949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24251 12:32:48.385386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24253 12:32:48.436363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24254 12:32:48.436757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24256 12:32:48.486437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24258 12:32:48.487196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24259 12:32:48.536826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24261 12:32:48.537446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24262 12:32:48.585323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24263 12:32:48.585767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24265 12:32:48.623969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24266 12:32:48.624448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24268 12:32:48.660664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24269 12:32:48.661072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24271 12:32:48.710254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24273 12:32:48.710744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24274 12:32:48.758000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24275 12:32:48.758489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24277 12:32:48.804931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24278 12:32:48.805337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24280 12:32:48.854530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24281 12:32:48.854921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24283 12:32:48.895223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24285 12:32:48.895778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24286 12:32:48.941667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24288 12:32:48.942256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24289 12:32:48.980273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24290 12:32:48.980654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24292 12:32:49.018932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24293 12:32:49.019352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24295 12:32:49.068132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24297 12:32:49.068605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24298 12:32:49.109244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24299 12:32:49.109677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24301 12:32:49.149822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24302 12:32:49.150373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24304 12:32:49.187486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24306 12:32:49.188070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24307 12:32:49.227178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24309 12:32:49.227804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24310 12:32:49.266938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24311 12:32:49.267374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24313 12:32:49.315978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24315 12:32:49.316330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24316 12:32:49.354328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24317 12:32:49.354757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24319 12:32:49.405270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24320 12:32:49.405659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24322 12:32:49.454292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24323 12:32:49.454721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24325 12:32:49.502105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24327 12:32:49.502586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24328 12:32:49.561896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24329 12:32:49.562324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24331 12:32:49.610680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24332 12:32:49.611124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24334 12:32:49.649294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24335 12:32:49.649687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24337 12:32:49.688911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24338 12:32:49.689291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24340 12:32:49.730218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24341 12:32:49.730665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24343 12:32:49.776772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24344 12:32:49.777165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24346 12:32:49.829493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24347 12:32:49.829898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24349 12:32:49.885610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24350 12:32:49.886057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24352 12:32:49.931340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24354 12:32:49.932125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24355 12:32:49.990271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24356 12:32:49.990827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24358 12:32:50.040795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24359 12:32:50.041186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24361 12:32:50.083773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24362 12:32:50.084237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24364 12:32:50.122189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24365 12:32:50.122747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24367 12:32:50.166562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24368 12:32:50.167761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24370 12:32:50.209330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24371 12:32:50.209733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24373 12:32:50.258810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24374 12:32:50.259249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24376 12:32:50.310087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24377 12:32:50.310579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24379 12:32:50.360730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24380 12:32:50.361248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24382 12:32:50.409247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24383 12:32:50.409800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24385 12:32:50.460123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24387 12:32:50.460516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24388 12:32:50.518157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24389 12:32:50.518566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24391 12:32:50.568279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24392 12:32:50.568734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24394 12:32:50.606339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24396 12:32:50.606814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24397 12:32:50.646035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24399 12:32:50.646591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24400 12:32:50.693393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24401 12:32:50.693830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24403 12:32:50.742199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24404 12:32:50.742647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24406 12:32:50.788414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24408 12:32:50.788905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24409 12:32:50.836599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24410 12:32:50.836985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24412 12:32:50.880874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24414 12:32:50.881322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24415 12:32:50.922857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24416 12:32:50.923259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24418 12:32:50.973282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24419 12:32:50.973719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24421 12:32:51.023428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24423 12:32:51.023929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24424 12:32:51.073544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24425 12:32:51.073994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24427 12:32:51.119634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24429 12:32:51.120158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24430 12:32:51.164340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24431 12:32:51.164769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24433 12:32:51.204737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24434 12:32:51.205162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24436 12:32:51.232860 <47>[ 284.322562] systemd-journald[109]: Sent WATCHDOG=1 notification.
24437 12:32:51.257783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24439 12:32:51.258264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24440 12:32:51.301077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24441 12:32:51.301519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24443 12:32:51.355268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24445 12:32:51.356034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24446 12:32:51.408297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24447 12:32:51.408760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24449 12:32:51.458380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24450 12:32:51.458821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24452 12:32:51.514583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24454 12:32:51.515079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24455 12:32:51.561332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24456 12:32:51.561791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24458 12:32:51.608523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24460 12:32:51.608993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24461 12:32:51.665256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24462 12:32:51.665687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24464 12:32:51.717356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24465 12:32:51.717792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24467 12:32:51.767461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24469 12:32:51.768007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24470 12:32:51.810776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24471 12:32:51.811226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24473 12:32:51.855916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24474 12:32:51.856355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24476 12:32:51.904437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24477 12:32:51.904816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24479 12:32:51.949504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24481 12:32:51.950116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24482 12:32:52.001527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24483 12:32:52.001978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24485 12:32:52.053724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24487 12:32:52.054176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24488 12:32:52.112482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24489 12:32:52.112895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24491 12:32:52.172985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24492 12:32:52.173417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24494 12:32:52.232844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24496 12:32:52.233334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24497 12:32:52.291530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24499 12:32:52.292399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24500 12:32:52.349792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24501 12:32:52.350187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24503 12:32:52.408837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24504 12:32:52.409257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24506 12:32:52.469426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24507 12:32:52.469838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24509 12:32:52.528678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24510 12:32:52.529029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24512 12:32:52.586729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24513 12:32:52.587181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24515 12:32:52.645929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24516 12:32:52.646375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24518 12:32:52.704524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24519 12:32:52.704951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24521 12:32:52.762183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24523 12:32:52.762854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24524 12:32:52.821285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24526 12:32:52.822077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24527 12:32:52.880340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24528 12:32:52.880788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24530 12:32:52.938417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24531 12:32:52.938837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24533 12:32:52.998369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24534 12:32:52.998807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24536 12:32:53.058082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24537 12:32:53.058509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24539 12:32:53.119238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24540 12:32:53.119654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24542 12:32:53.178892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24543 12:32:53.179352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24545 12:32:53.241355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24547 12:32:53.241861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24548 12:32:53.302476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24549 12:32:53.302906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24551 12:32:53.361771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24552 12:32:53.362170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24554 12:32:53.420565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24556 12:32:53.421050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24557 12:32:53.478570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24558 12:32:53.479031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24560 12:32:53.537567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24561 12:32:53.537962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24563 12:32:53.596856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24564 12:32:53.597362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24566 12:32:53.655074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24567 12:32:53.655490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24569 12:32:53.714138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24570 12:32:53.714547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24572 12:32:53.773110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24574 12:32:53.773907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24575 12:32:53.817641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24576 12:32:53.818079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24578 12:32:53.858570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24580 12:32:53.859213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24581 12:32:53.906550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24582 12:32:53.906940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24584 12:32:53.953053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24585 12:32:53.953504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24587 12:32:54.002221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24588 12:32:54.002656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24590 12:32:54.043073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24591 12:32:54.043531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24593 12:32:54.086223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24594 12:32:54.086676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24596 12:32:54.133893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24597 12:32:54.134325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24599 12:32:54.182182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24601 12:32:54.182668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24602 12:32:54.232708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24603 12:32:54.233143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24605 12:32:54.272770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24606 12:32:54.273166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24608 12:32:54.323911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24609 12:32:54.324363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24611 12:32:54.377287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24613 12:32:54.377775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24614 12:32:54.415156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24615 12:32:54.415578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24617 12:32:54.462158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24618 12:32:54.462580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24620 12:32:54.512637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24621 12:32:54.513079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24623 12:32:54.560285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24625 12:32:54.560779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24626 12:32:54.607345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24627 12:32:54.607794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24629 12:32:54.654765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24630 12:32:54.655158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24632 12:32:54.702736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24633 12:32:54.703195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24635 12:32:54.755436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24637 12:32:54.756135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24638 12:32:54.814159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24640 12:32:54.814658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24641 12:32:54.865142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24643 12:32:54.865626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24644 12:32:54.908509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24645 12:32:54.908915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24647 12:32:54.960249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24648 12:32:54.960674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24650 12:32:55.010425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24651 12:32:55.010872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24653 12:32:55.058034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24655 12:32:55.058561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24656 12:32:55.125541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24657 12:32:55.125964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24659 12:32:55.169996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24661 12:32:55.170479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24662 12:32:55.214766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24664 12:32:55.215370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24665 12:32:55.266248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24666 12:32:55.266765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24668 12:32:55.312780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24669 12:32:55.313223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24671 12:32:55.365268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24672 12:32:55.365700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24674 12:32:55.416841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24675 12:32:55.417281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24677 12:32:55.476232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24678 12:32:55.476646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24680 12:32:55.527032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24681 12:32:55.527443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24683 12:32:55.565137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24684 12:32:55.565576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24686 12:32:55.609773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24687 12:32:55.610192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24689 12:32:55.654164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24690 12:32:55.654740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24692 12:32:55.696304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24693 12:32:55.696792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24695 12:32:55.741085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24696 12:32:55.741575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24698 12:32:55.787922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24699 12:32:55.788345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24701 12:32:55.844665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24702 12:32:55.845085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24704 12:32:55.894800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24706 12:32:55.895290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24707 12:32:55.944538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24708 12:32:55.944974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24710 12:32:55.993718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24711 12:32:55.994121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24713 12:32:56.041180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24714 12:32:56.041763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24716 12:32:56.090822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24717 12:32:56.091197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24719 12:32:56.135067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24720 12:32:56.135555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24722 12:32:56.172866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24723 12:32:56.173356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24725 12:32:56.214751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24726 12:32:56.215179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24728 12:32:56.257660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24729 12:32:56.258101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24731 12:32:56.302162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24732 12:32:56.302584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24734 12:32:56.349007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24735 12:32:56.349505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24737 12:32:56.389344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24738 12:32:56.389684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24740 12:32:56.428899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24742 12:32:56.429329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24743 12:32:56.472005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24744 12:32:56.472446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24746 12:32:56.513595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24747 12:32:56.514131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24749 12:32:56.560431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24750 12:32:56.560799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24752 12:32:56.609284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24753 12:32:56.609695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24755 12:32:56.665538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24756 12:32:56.665985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24758 12:32:56.706300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24759 12:32:56.706731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24761 12:32:56.751928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24762 12:32:56.752342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24764 12:32:56.796904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24766 12:32:56.797348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24767 12:32:56.838881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24768 12:32:56.839297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24770 12:32:56.885674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24771 12:32:56.886246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24773 12:32:56.930060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24774 12:32:56.930649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24776 12:32:56.973631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24777 12:32:56.974105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24779 12:32:57.012349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24780 12:32:57.012788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24782 12:32:57.056876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24784 12:32:57.057329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24785 12:32:57.104247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24786 12:32:57.104683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24788 12:32:57.148920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24789 12:32:57.149422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24791 12:32:57.206431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24792 12:32:57.206861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24794 12:32:57.268060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24795 12:32:57.268476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24797 12:32:57.325772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24798 12:32:57.326246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24800 12:32:57.386224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24801 12:32:57.386648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24803 12:32:57.448335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24805 12:32:57.448776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24806 12:32:57.503471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24808 12:32:57.503951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24809 12:32:57.553666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24811 12:32:57.554139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24812 12:32:57.604196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24813 12:32:57.604633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24815 12:32:57.657509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24817 12:32:57.658295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24818 12:32:57.710126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24819 12:32:57.710563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24821 12:32:57.761248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24822 12:32:57.761712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24824 12:32:57.810933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24825 12:32:57.811373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24827 12:32:57.858171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24828 12:32:57.858677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24830 12:32:57.904558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24831 12:32:57.904969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24833 12:32:57.950439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24834 12:32:57.950884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24836 12:32:58.002852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24838 12:32:58.003300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24839 12:32:58.052497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24840 12:32:58.052919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24842 12:32:58.094934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24843 12:32:58.095381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24845 12:32:58.150229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24846 12:32:58.150653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24848 12:32:58.204983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24849 12:32:58.205426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24851 12:32:58.269854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24852 12:32:58.270208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24854 12:32:58.320783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24856 12:32:58.321244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24857 12:32:58.368542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24858 12:32:58.368978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24860 12:32:58.411996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24861 12:32:58.412411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24863 12:32:58.470623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24865 12:32:58.471060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24866 12:32:58.521269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24867 12:32:58.521671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24869 12:32:58.566085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24871 12:32:58.566576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24872 12:32:58.606742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24873 12:32:58.607128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24875 12:32:58.662471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24877 12:32:58.663069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24878 12:32:58.722452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24880 12:32:58.722938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24881 12:32:58.782765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24882 12:32:58.783330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24884 12:32:58.839324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24886 12:32:58.839900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24887 12:32:58.889583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24889 12:32:58.890078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24890 12:32:58.930575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24891 12:32:58.931003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24893 12:32:58.976451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24894 12:32:58.976899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24896 12:32:59.016895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24897 12:32:59.017312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24899 12:32:59.059213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24901 12:32:59.059698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24902 12:32:59.100547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24903 12:32:59.100960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24905 12:32:59.145286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24907 12:32:59.145698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24908 12:32:59.199441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24910 12:32:59.199885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24911 12:32:59.243957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24912 12:32:59.244394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24914 12:32:59.286895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24915 12:32:59.287347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24917 12:32:59.337065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24918 12:32:59.337470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24920 12:32:59.378021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24921 12:32:59.378463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24923 12:32:59.430662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24924 12:32:59.431076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24926 12:32:59.474565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24928 12:32:59.475039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24929 12:32:59.526777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24930 12:32:59.527220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24932 12:32:59.580359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24933 12:32:59.580794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24935 12:32:59.644980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24936 12:32:59.645379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24938 12:32:59.705186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24940 12:32:59.705634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24941 12:32:59.746580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24942 12:32:59.747037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24944 12:32:59.790478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24945 12:32:59.790967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24947 12:32:59.830439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24948 12:32:59.830865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24950 12:32:59.872779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24952 12:32:59.873224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24953 12:32:59.921992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24954 12:32:59.922445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24956 12:32:59.965983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24958 12:32:59.966443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24959 12:33:00.014119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24960 12:33:00.014682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24962 12:33:00.066870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24963 12:33:00.067306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24965 12:33:00.112072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24967 12:33:00.112568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24968 12:33:00.152382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24969 12:33:00.152820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24971 12:33:00.197194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24973 12:33:00.197629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24974 12:33:00.284520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24975 12:33:00.284981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24977 12:33:00.342735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24979 12:33:00.343401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24980 12:33:00.401265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24981 12:33:00.401690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
24983 12:33:00.460639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
24984 12:33:00.461074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
24986 12:33:00.521015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
24987 12:33:00.521451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
24989 12:33:00.581426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
24990 12:33:00.581862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
24992 12:33:00.641124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
24993 12:33:00.641519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
24995 12:33:00.700590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
24997 12:33:00.701014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
24998 12:33:00.757699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
24999 12:33:00.758131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25001 12:33:00.816458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25002 12:33:00.816907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25004 12:33:00.876745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25005 12:33:00.877132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25007 12:33:00.936450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25008 12:33:00.936849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25010 12:33:00.992698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25011 12:33:00.993320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25013 12:33:01.050376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25014 12:33:01.050795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25016 12:33:01.110169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25018 12:33:01.110610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25019 12:33:01.169491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25020 12:33:01.170024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25022 12:33:01.228001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25024 12:33:01.228389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25025 12:33:01.285922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25026 12:33:01.286366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25028 12:33:01.335513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25030 12:33:01.336004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25031 12:33:01.392641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25032 12:33:01.393143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25034 12:33:01.442900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25035 12:33:01.443330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25037 12:33:01.492651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25038 12:33:01.493085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25040 12:33:01.536560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25041 12:33:01.536952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25043 12:33:01.582427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25044 12:33:01.582872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25046 12:33:01.631071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25047 12:33:01.631623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25049 12:33:01.676124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25051 12:33:01.676751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25052 12:33:01.725018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25053 12:33:01.725452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25055 12:33:01.768087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25056 12:33:01.768467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25058 12:33:01.821483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25060 12:33:01.822135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25061 12:33:01.870963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25063 12:33:01.871453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25064 12:33:01.911258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25066 12:33:01.911748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25067 12:33:01.962570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25068 12:33:01.962985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25070 12:33:02.014379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25071 12:33:02.014829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25073 12:33:02.061749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25074 12:33:02.062254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25076 12:33:02.114323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25078 12:33:02.114946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25079 12:33:02.170754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25080 12:33:02.171198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25082 12:33:02.220580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25083 12:33:02.220972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25085 12:33:02.269425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25086 12:33:02.269853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25088 12:33:02.328490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25090 12:33:02.328970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25091 12:33:02.372716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25092 12:33:02.373152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25094 12:33:02.418964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25095 12:33:02.419436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25097 12:33:02.480298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25099 12:33:02.480770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25100 12:33:02.533363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25101 12:33:02.533767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25103 12:33:02.586280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25104 12:33:02.586666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25106 12:33:02.638096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25108 12:33:02.638520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25109 12:33:02.684313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25110 12:33:02.684763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25112 12:33:02.735181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25114 12:33:02.735683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25115 12:33:02.798763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25116 12:33:02.799165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25118 12:33:02.846970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25119 12:33:02.847405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25121 12:33:02.901155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25122 12:33:02.901541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25124 12:33:02.947465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25126 12:33:02.947953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25127 12:33:03.000545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25128 12:33:03.001083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25130 12:33:03.059502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25132 12:33:03.060127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25133 12:33:03.119160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25135 12:33:03.119715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25136 12:33:03.169635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25137 12:33:03.170051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25139 12:33:03.213583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25140 12:33:03.214039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25142 12:33:03.269314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25143 12:33:03.269755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25145 12:33:03.331401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25147 12:33:03.331892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25148 12:33:03.386627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25149 12:33:03.387024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25151 12:33:03.438583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25153 12:33:03.439473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25154 12:33:03.492051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25156 12:33:03.492502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25157 12:33:03.543516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25159 12:33:03.543950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25160 12:33:03.583926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25161 12:33:03.584358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25163 12:33:03.634644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25164 12:33:03.635141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25166 12:33:03.687164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25168 12:33:03.687663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25169 12:33:03.730291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25170 12:33:03.730742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25172 12:33:03.775115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25173 12:33:03.775684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25175 12:33:03.822839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25176 12:33:03.823295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25178 12:33:03.865868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25179 12:33:03.866255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25181 12:33:03.905310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25183 12:33:03.905745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25184 12:33:03.947509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25186 12:33:03.948288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25187 12:33:03.994304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25189 12:33:03.994773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25190 12:33:04.041050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25192 12:33:04.041424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25193 12:33:04.094089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25194 12:33:04.094513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25196 12:33:04.144360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25198 12:33:04.144727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25199 12:33:04.187971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25200 12:33:04.188352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25202 12:33:04.235013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25203 12:33:04.235430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25205 12:33:04.281800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25206 12:33:04.282206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25208 12:33:04.324013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25209 12:33:04.324399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25211 12:33:04.384374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25212 12:33:04.384902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25214 12:33:04.442851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25215 12:33:04.443230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25217 12:33:04.486568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25218 12:33:04.487001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25220 12:33:04.535004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25221 12:33:04.535437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25223 12:33:04.581857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25225 12:33:04.582333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25226 12:33:04.630569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25228 12:33:04.631048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25229 12:33:04.675536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25231 12:33:04.676049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25232 12:33:04.717037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25233 12:33:04.717479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25235 12:33:04.776140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25236 12:33:04.776576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25238 12:33:04.835055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25239 12:33:04.835534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25241 12:33:04.889295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25242 12:33:04.889697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25244 12:33:04.942683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25245 12:33:04.943211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25247 12:33:04.997233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25248 12:33:04.997696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25250 12:33:05.044414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25251 12:33:05.044797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25253 12:33:05.084984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25254 12:33:05.085415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25256 12:33:05.128336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25257 12:33:05.128786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25259 12:33:05.168728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25260 12:33:05.169168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25262 12:33:05.212260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25264 12:33:05.212731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25265 12:33:05.257209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25266 12:33:05.257643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25268 12:33:05.306448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25269 12:33:05.306849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25271 12:33:05.364918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25272 12:33:05.365314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25274 12:33:05.415471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25276 12:33:05.415960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25277 12:33:05.461217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25279 12:33:05.461681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25280 12:33:05.517695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25281 12:33:05.518118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25283 12:33:05.573927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25284 12:33:05.574346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25286 12:33:05.619364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25288 12:33:05.619844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25289 12:33:05.665477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25290 12:33:05.665939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25292 12:33:05.706226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25293 12:33:05.706687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25295 12:33:05.753399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25296 12:33:05.753851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25298 12:33:05.794181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25299 12:33:05.794650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25301 12:33:05.833663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25302 12:33:05.834225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25304 12:33:05.882771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25306 12:33:05.883277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25307 12:33:05.925718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25309 12:33:05.926494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25310 12:33:05.965722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25312 12:33:05.966204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25313 12:33:06.013924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25314 12:33:06.014354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25316 12:33:06.063017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25318 12:33:06.063626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25319 12:33:06.112473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25321 12:33:06.112970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25322 12:33:06.158736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25323 12:33:06.159158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25325 12:33:06.198536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25327 12:33:06.199008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25328 12:33:06.249265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25329 12:33:06.249720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25331 12:33:06.302608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25332 12:33:06.303047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25334 12:33:06.352682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25336 12:33:06.353093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25337 12:33:06.397465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25338 12:33:06.397847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25340 12:33:06.444834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25341 12:33:06.445267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25343 12:33:06.485430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25344 12:33:06.485882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25346 12:33:06.533230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25347 12:33:06.533686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25349 12:33:06.580643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25351 12:33:06.581315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25352 12:33:06.621990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25353 12:33:06.622419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25355 12:33:06.662054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25356 12:33:06.662471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25358 12:33:06.704076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25360 12:33:06.704563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25361 12:33:06.746475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25362 12:33:06.746856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25364 12:33:06.789703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25365 12:33:06.790117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25367 12:33:06.844767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25368 12:33:06.845197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25370 12:33:06.901096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25371 12:33:06.901576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25373 12:33:06.958411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25374 12:33:06.958966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25376 12:33:07.009477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25378 12:33:07.009907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25379 12:33:07.060366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25380 12:33:07.060734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25382 12:33:07.098057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25383 12:33:07.098478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25385 12:33:07.138075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25387 12:33:07.138832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25388 12:33:07.177941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25389 12:33:07.178388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25391 12:33:07.218385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25392 12:33:07.218829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25394 12:33:07.259745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25395 12:33:07.260216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25397 12:33:07.310943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25399 12:33:07.311420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25400 12:33:07.348887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25401 12:33:07.349326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25403 12:33:07.389507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25404 12:33:07.389950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25406 12:33:07.436103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25407 12:33:07.436546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25409 12:33:07.479391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25411 12:33:07.479891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25412 12:33:07.521961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25413 12:33:07.522364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25415 12:33:07.564119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25416 12:33:07.564577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25418 12:33:07.603946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25419 12:33:07.604359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25421 12:33:07.641172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25422 12:33:07.641596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25424 12:33:07.684906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25425 12:33:07.685362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25427 12:33:07.726571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25428 12:33:07.727011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25430 12:33:07.768788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25431 12:33:07.769228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25433 12:33:07.814251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25434 12:33:07.814683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25436 12:33:07.852332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25438 12:33:07.852802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25439 12:33:07.897045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25440 12:33:07.897431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25442 12:33:07.939775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25443 12:33:07.940325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25445 12:33:07.978772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25446 12:33:07.979282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25448 12:33:08.019114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25449 12:33:08.019684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25451 12:33:08.068721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25453 12:33:08.069323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25454 12:33:08.117916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25456 12:33:08.118536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25457 12:33:08.160091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25458 12:33:08.160644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25460 12:33:08.201559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25462 12:33:08.202295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25463 12:33:08.243933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25464 12:33:08.244326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25466 12:33:08.284680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25467 12:33:08.285102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25469 12:33:08.327992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25470 12:33:08.328407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25472 12:33:08.376726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25473 12:33:08.377106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25475 12:33:08.416561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25476 12:33:08.416986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25478 12:33:08.457231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25479 12:33:08.457666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25481 12:33:08.495256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25483 12:33:08.495689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25484 12:33:08.534622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25485 12:33:08.535177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25487 12:33:08.581336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25488 12:33:08.581792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25490 12:33:08.619282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25492 12:33:08.619738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25493 12:33:08.666894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25494 12:33:08.667339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25496 12:33:08.705728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25497 12:33:08.706154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25499 12:33:08.746088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25500 12:33:08.746519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25502 12:33:08.789395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25504 12:33:08.789894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25505 12:33:08.828469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25506 12:33:08.828901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25508 12:33:08.872132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25509 12:33:08.872624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25511 12:33:08.913378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25512 12:33:08.913829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25514 12:33:08.953598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25516 12:33:08.954079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25517 12:33:08.993219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25518 12:33:08.993598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25520 12:33:09.033185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25521 12:33:09.033572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25523 12:33:09.071531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25525 12:33:09.072013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25526 12:33:09.111175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25528 12:33:09.111666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25529 12:33:09.165233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25530 12:33:09.165695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25532 12:33:09.221503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25534 12:33:09.222053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25535 12:33:09.277447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25536 12:33:09.277939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25538 12:33:09.335366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25540 12:33:09.335824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25541 12:33:09.377285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25542 12:33:09.377739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25544 12:33:09.425207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25545 12:33:09.425697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25547 12:33:09.472962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25548 12:33:09.473512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25550 12:33:09.513063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25551 12:33:09.513515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25553 12:33:09.556323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25554 12:33:09.556720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25556 12:33:09.603643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25558 12:33:09.604139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25559 12:33:09.647230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25561 12:33:09.647726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25562 12:33:09.690172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25563 12:33:09.690611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25565 12:33:09.735783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25566 12:33:09.736245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25568 12:33:09.785808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25569 12:33:09.786171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25571 12:33:09.826806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25572 12:33:09.827364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25574 12:33:09.866576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25575 12:33:09.867002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25577 12:33:09.910643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25578 12:33:09.911081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25580 12:33:09.973277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25581 12:33:09.973691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25583 12:33:10.034185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25585 12:33:10.034568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25586 12:33:10.094311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25587 12:33:10.094694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25589 12:33:10.154243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25590 12:33:10.154715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25592 12:33:10.213161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25594 12:33:10.213638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25595 12:33:10.261459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25596 12:33:10.261927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25598 12:33:10.309112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25599 12:33:10.309579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25601 12:33:10.369477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25602 12:33:10.369928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25604 12:33:10.416210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25605 12:33:10.416644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25607 12:33:10.478074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25608 12:33:10.478491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25610 12:33:10.528138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25611 12:33:10.528589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25613 12:33:10.578875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25614 12:33:10.579275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25616 12:33:10.631049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25617 12:33:10.631486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25619 12:33:10.678215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25620 12:33:10.678658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25622 12:33:10.720437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25623 12:33:10.720857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25625 12:33:10.760908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25626 12:33:10.761361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25628 12:33:10.810590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25629 12:33:10.811014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25631 12:33:10.855821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25632 12:33:10.856299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25634 12:33:10.901327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25635 12:33:10.901875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25637 12:33:10.945525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25638 12:33:10.945941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25640 12:33:10.986606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25642 12:33:10.987075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25643 12:33:11.031946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25644 12:33:11.032441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25646 12:33:11.074779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25647 12:33:11.075336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25649 12:33:11.117817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25650 12:33:11.118298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25652 12:33:11.165898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25653 12:33:11.166353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25655 12:33:11.210798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25656 12:33:11.211237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25658 12:33:11.270631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25659 12:33:11.271040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25661 12:33:11.330182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25662 12:33:11.330627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25664 12:33:11.379023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25665 12:33:11.379453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25667 12:33:11.426375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25668 12:33:11.426735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25670 12:33:11.478065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25672 12:33:11.478448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25673 12:33:11.522874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25674 12:33:11.523311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25676 12:33:11.569399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25677 12:33:11.569835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25679 12:33:11.615208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25681 12:33:11.615674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25682 12:33:11.656027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25683 12:33:11.656425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25685 12:33:11.697254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25686 12:33:11.697707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25688 12:33:11.738198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25689 12:33:11.738631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25691 12:33:11.780783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25693 12:33:11.781269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25694 12:33:11.829343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25696 12:33:11.829829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25697 12:33:11.882515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25698 12:33:11.882899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25700 12:33:11.941497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25701 12:33:11.942077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25703 12:33:11.986083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25704 12:33:11.986551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25706 12:33:12.030734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25707 12:33:12.031171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25709 12:33:12.083495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25711 12:33:12.083975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25712 12:33:12.133882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25713 12:33:12.134312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25715 12:33:12.176905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25716 12:33:12.177354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25718 12:33:12.225590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25719 12:33:12.226028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25721 12:33:12.265428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25723 12:33:12.265914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25724 12:33:12.304399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25725 12:33:12.304860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25727 12:33:12.346298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25729 12:33:12.346768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25730 12:33:12.388571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25731 12:33:12.389017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25733 12:33:12.431604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25735 12:33:12.432207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25736 12:33:12.481240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25737 12:33:12.481698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25739 12:33:12.534480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25740 12:33:12.534920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25742 12:33:12.594486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25744 12:33:12.594927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25745 12:33:12.654007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25746 12:33:12.654360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25748 12:33:12.713930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25749 12:33:12.714329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25751 12:33:12.773177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25752 12:33:12.773602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25754 12:33:12.833225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25756 12:33:12.833862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25757 12:33:12.893168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25758 12:33:12.893555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25760 12:33:12.951461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25762 12:33:12.952208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25763 12:33:13.005098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25765 12:33:13.005473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25766 12:33:13.044331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25768 12:33:13.044818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25769 12:33:13.085956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25770 12:33:13.086380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25772 12:33:13.128677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25773 12:33:13.129116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25775 12:33:13.172380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25776 12:33:13.172806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25778 12:33:13.218893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25779 12:33:13.219350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25781 12:33:13.262903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25782 12:33:13.263348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25784 12:33:13.312966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25786 12:33:13.313435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25787 12:33:13.366538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25789 12:33:13.367038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25790 12:33:13.413290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25791 12:33:13.413759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25793 12:33:13.454101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25795 12:33:13.454602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25796 12:33:13.494085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25797 12:33:13.494528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25799 12:33:13.535921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25800 12:33:13.536359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25802 12:33:13.576441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25804 12:33:13.576906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25805 12:33:13.626633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25806 12:33:13.627123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25808 12:33:13.672425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25809 12:33:13.672863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25811 12:33:13.715284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25813 12:33:13.715763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25814 12:33:13.760467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25815 12:33:13.760896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25817 12:33:13.805331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25818 12:33:13.805688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25820 12:33:13.851515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25822 12:33:13.851955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25823 12:33:13.898986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25824 12:33:13.899392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25826 12:33:13.944973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25827 12:33:13.945405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25829 12:33:14.001266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25830 12:33:14.001784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25832 12:33:14.059348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25834 12:33:14.059834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25835 12:33:14.114756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25836 12:33:14.115188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25838 12:33:14.165149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25839 12:33:14.165575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25841 12:33:14.209093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25842 12:33:14.209524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25844 12:33:14.256328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25846 12:33:14.256790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25847 12:33:14.297644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25848 12:33:14.298089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25850 12:33:14.342768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25851 12:33:14.343219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25853 12:33:14.388774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25854 12:33:14.389290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25856 12:33:14.429433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25858 12:33:14.429928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25859 12:33:14.469504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25860 12:33:14.470002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25862 12:33:14.516766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25863 12:33:14.517226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25865 12:33:14.562741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25866 12:33:14.563199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25868 12:33:14.605243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25869 12:33:14.605707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25871 12:33:14.646428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25872 12:33:14.646897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25874 12:33:14.692441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25876 12:33:14.692844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25877 12:33:14.734966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25878 12:33:14.735501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25880 12:33:14.785003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25881 12:33:14.785426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25883 12:33:14.835465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25885 12:33:14.835891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25886 12:33:14.893818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25887 12:33:14.894327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25889 12:33:14.954554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25890 12:33:14.954991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25892 12:33:15.013361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25893 12:33:15.013745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25895 12:33:15.070282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25896 12:33:15.070669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25898 12:33:15.127242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25900 12:33:15.127709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25901 12:33:15.184176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25902 12:33:15.184658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25904 12:33:15.240760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25905 12:33:15.241233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25907 12:33:15.298696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25908 12:33:15.299185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25910 12:33:15.340649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25911 12:33:15.341098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25913 12:33:15.380774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25914 12:33:15.381205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25916 12:33:15.421109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25917 12:33:15.421569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25919 12:33:15.462601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25920 12:33:15.463009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25922 12:33:15.520869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25923 12:33:15.521296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25925 12:33:15.581320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25926 12:33:15.581767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25928 12:33:15.642995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25929 12:33:15.643431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25931 12:33:15.684998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25932 12:33:15.685435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25934 12:33:15.729519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25935 12:33:15.729925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25937 12:33:15.769892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25939 12:33:15.770371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25940 12:33:15.810417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25941 12:33:15.810843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25943 12:33:15.850257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25944 12:33:15.850665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25946 12:33:15.891467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25948 12:33:15.891928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25949 12:33:15.930999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25950 12:33:15.931437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25952 12:33:15.978208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25954 12:33:15.978698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25955 12:33:16.022328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25956 12:33:16.022728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25958 12:33:16.068439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25960 12:33:16.068903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25961 12:33:16.120472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25962 12:33:16.120859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25964 12:33:16.165814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25965 12:33:16.166221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25967 12:33:16.206731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25968 12:33:16.207188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25970 12:33:16.248846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25972 12:33:16.249335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25973 12:33:16.288910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25974 12:33:16.289362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25976 12:33:16.329567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25978 12:33:16.330050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25979 12:33:16.369349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25980 12:33:16.369853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
25982 12:33:16.409932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
25984 12:33:16.410703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
25985 12:33:16.452217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
25987 12:33:16.452830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
25988 12:33:16.494021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
25989 12:33:16.494441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
25991 12:33:16.548166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
25993 12:33:16.548641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
25994 12:33:16.589039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
25995 12:33:16.589494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
25997 12:33:16.637984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
25999 12:33:16.638470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26000 12:33:16.689966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26001 12:33:16.690407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26003 12:33:16.741128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26004 12:33:16.741568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26006 12:33:16.791106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26007 12:33:16.791545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26009 12:33:16.838095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26010 12:33:16.838516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26012 12:33:16.882634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26014 12:33:16.883128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26015 12:33:16.922264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26016 12:33:16.922675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26018 12:33:16.962818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26019 12:33:16.963262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26021 12:33:17.002805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26022 12:33:17.003255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26024 12:33:17.044968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26025 12:33:17.045471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26027 12:33:17.094193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26028 12:33:17.094739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26030 12:33:17.140520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26031 12:33:17.141000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26033 12:33:17.190909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26034 12:33:17.191352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26036 12:33:17.242999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26038 12:33:17.243595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26039 12:33:17.293822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26040 12:33:17.294241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26042 12:33:17.347000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26044 12:33:17.347424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26045 12:33:17.398092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26046 12:33:17.398511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26048 12:33:17.448675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26050 12:33:17.449133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26051 12:33:17.502022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26053 12:33:17.502467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26054 12:33:17.555383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26056 12:33:17.556081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26057 12:33:17.608186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26059 12:33:17.608831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26060 12:33:17.658043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26061 12:33:17.658450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26063 12:33:17.706413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26065 12:33:17.706855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26066 12:33:17.753492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26067 12:33:17.754017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26069 12:33:17.794610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26071 12:33:17.795013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26072 12:33:17.836051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26073 12:33:17.836613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26075 12:33:17.877549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26076 12:33:17.877987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26078 12:33:17.924338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26079 12:33:17.924806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26081 12:33:17.965511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26083 12:33:17.965972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26084 12:33:18.015617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26086 12:33:18.016095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26087 12:33:18.054626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26089 12:33:18.055108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26090 12:33:18.096517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26092 12:33:18.096983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26093 12:33:18.140788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26094 12:33:18.141221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26096 12:33:18.186619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26098 12:33:18.187091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26099 12:33:18.241843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26101 12:33:18.242316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26102 12:33:18.293668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26103 12:33:18.294114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26105 12:33:18.342380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26106 12:33:18.342812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26108 12:33:18.394127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26110 12:33:18.394551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26111 12:33:18.439438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26113 12:33:18.439925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26114 12:33:18.491354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26116 12:33:18.491815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26117 12:33:18.540302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26118 12:33:18.540740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26120 12:33:18.591084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26121 12:33:18.591556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26123 12:33:18.645298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26125 12:33:18.645829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26126 12:33:18.701370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26127 12:33:18.701790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26129 12:33:18.759932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26130 12:33:18.760295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26132 12:33:18.820074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26134 12:33:18.820549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26135 12:33:18.877892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26136 12:33:18.878324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26138 12:33:18.937291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26139 12:33:18.937756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26141 12:33:18.994585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26142 12:33:18.994986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26144 12:33:19.053351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26145 12:33:19.053968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26147 12:33:19.112145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26149 12:33:19.112919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26150 12:33:19.169722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26151 12:33:19.170202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26153 12:33:19.228746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26154 12:33:19.229195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26156 12:33:19.288893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26158 12:33:19.289371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26159 12:33:19.349011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26160 12:33:19.349443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26162 12:33:19.407479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26164 12:33:19.407972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26165 12:33:19.466969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26167 12:33:19.467438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26168 12:33:19.526087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26169 12:33:19.526542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26171 12:33:19.586647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26172 12:33:19.587087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26174 12:33:19.647144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26176 12:33:19.647642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26177 12:33:19.692188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26178 12:33:19.692653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26180 12:33:19.738040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26181 12:33:19.738461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26183 12:33:19.780116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26184 12:33:19.780566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26186 12:33:19.822064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26187 12:33:19.822497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26189 12:33:19.865380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26190 12:33:19.865772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26192 12:33:19.912514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26193 12:33:19.913084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26195 12:33:19.958591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26196 12:33:19.959054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26198 12:33:20.011047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26199 12:33:20.011574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26201 12:33:20.062571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26202 12:33:20.062956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26204 12:33:20.109287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26205 12:33:20.109674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26207 12:33:20.161282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26209 12:33:20.161781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26210 12:33:20.214305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26211 12:33:20.214694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26213 12:33:20.254734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26214 12:33:20.255133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26216 12:33:20.305597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26217 12:33:20.306066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26219 12:33:20.358289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26220 12:33:20.358728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26222 12:33:20.399008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26223 12:33:20.399457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26225 12:33:20.438045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26227 12:33:20.438518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26228 12:33:20.484954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26229 12:33:20.485349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26231 12:33:20.532835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26233 12:33:20.533306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26234 12:33:20.585264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26235 12:33:20.585690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26237 12:33:20.634556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26239 12:33:20.634959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26240 12:33:20.679222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26241 12:33:20.679665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26243 12:33:20.748317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26244 12:33:20.748752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26246 12:33:20.793629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26247 12:33:20.794097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26249 12:33:20.843944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26250 12:33:20.844335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26252 12:33:20.883516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26254 12:33:20.883957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26255 12:33:20.934522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26256 12:33:20.934962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26258 12:33:20.987200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26260 12:33:20.987687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26261 12:33:21.036898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26262 12:33:21.037333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26264 12:33:21.089279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26265 12:33:21.089849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26267 12:33:21.141911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26269 12:33:21.142520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26270 12:33:21.196049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26271 12:33:21.196567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26273 12:33:21.254715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26274 12:33:21.255210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26276 12:33:21.317553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26277 12:33:21.318018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26279 12:33:21.370883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26280 12:33:21.371436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26282 12:33:21.428162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26284 12:33:21.428687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26285 12:33:21.478944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26286 12:33:21.479386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26288 12:33:21.522284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26289 12:33:21.522743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26291 12:33:21.573309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26292 12:33:21.573751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26294 12:33:21.617162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26296 12:33:21.617609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26297 12:33:21.665079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26298 12:33:21.665532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26300 12:33:21.718333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26302 12:33:21.718814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26303 12:33:21.765999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26304 12:33:21.766410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26306 12:33:21.807197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26307 12:33:21.807700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26309 12:33:21.849640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26310 12:33:21.850060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26312 12:33:21.901203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26313 12:33:21.901629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26315 12:33:21.949331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26316 12:33:21.949755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26318 12:33:21.993331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26319 12:33:21.993759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26321 12:33:22.034796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26323 12:33:22.035232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26324 12:33:22.081864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26325 12:33:22.082298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26327 12:33:22.136721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26328 12:33:22.137080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26330 12:33:22.184875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26331 12:33:22.185242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26333 12:33:22.233241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26335 12:33:22.234004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26336 12:33:22.281386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26337 12:33:22.281955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26339 12:33:22.327466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26340 12:33:22.327987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26342 12:33:22.371654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26344 12:33:22.372313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26345 12:33:22.417818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26347 12:33:22.418300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26348 12:33:22.475844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26349 12:33:22.476284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26351 12:33:22.533428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26352 12:33:22.533883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26354 12:33:22.590567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26355 12:33:22.590919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26357 12:33:22.645464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26359 12:33:22.645925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26360 12:33:22.697162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26361 12:33:22.697599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26363 12:33:22.746352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26364 12:33:22.746781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26366 12:33:22.797345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26368 12:33:22.797826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26369 12:33:22.846964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26370 12:33:22.847409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26372 12:33:22.892763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26373 12:33:22.893156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26375 12:33:22.933346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26377 12:33:22.933781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26378 12:33:22.993988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26379 12:33:22.994393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26381 12:33:23.041205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26383 12:33:23.041820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26384 12:33:23.095224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26386 12:33:23.095680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26387 12:33:23.157114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26389 12:33:23.157594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26390 12:33:23.208059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26392 12:33:23.208517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26393 12:33:23.250610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26394 12:33:23.251024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26396 12:33:23.299434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26398 12:33:23.299879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26399 12:33:23.356961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26400 12:33:23.357399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26402 12:33:23.421910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26404 12:33:23.422340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26405 12:33:23.476674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26406 12:33:23.477241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26408 12:33:23.521133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26409 12:33:23.521571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26411 12:33:23.568888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26412 12:33:23.569320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26414 12:33:23.618086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26416 12:33:23.618583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26417 12:33:23.667005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26418 12:33:23.667432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26420 12:33:23.710518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26421 12:33:23.710871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26423 12:33:23.759385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26425 12:33:23.759855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26426 12:33:23.802879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26428 12:33:23.803364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26429 12:33:23.844151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26430 12:33:23.844548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26432 12:33:23.890119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26433 12:33:23.890548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26435 12:33:23.936850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26436 12:33:23.937311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26438 12:33:23.982877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26439 12:33:23.983345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26441 12:33:24.030774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26442 12:33:24.031169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26444 12:33:24.076540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26445 12:33:24.076999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26447 12:33:24.124578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26448 12:33:24.124984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26450 12:33:24.169719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26452 12:33:24.170184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26453 12:33:24.216686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26455 12:33:24.217159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26456 12:33:24.265063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26457 12:33:24.265506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26459 12:33:24.316624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26460 12:33:24.317060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26462 12:33:24.370137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26464 12:33:24.370532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26465 12:33:24.425698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26467 12:33:24.426133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26468 12:33:24.482153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26469 12:33:24.482748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26471 12:33:24.537221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26472 12:33:24.537604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26474 12:33:24.586301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26475 12:33:24.586756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26477 12:33:24.633249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26478 12:33:24.633697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26480 12:33:24.681260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26481 12:33:24.681700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26483 12:33:24.738173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26485 12:33:24.738685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26486 12:33:24.790325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26487 12:33:24.790760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26489 12:33:24.836385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26490 12:33:24.836806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26492 12:33:24.877600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26494 12:33:24.878383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26495 12:33:24.920605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26496 12:33:24.921108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26498 12:33:24.962252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26499 12:33:24.962738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26501 12:33:25.014404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26503 12:33:25.014900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26504 12:33:25.066378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26505 12:33:25.066841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26507 12:33:25.109040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26509 12:33:25.109741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26510 12:33:25.161631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26511 12:33:25.162081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26513 12:33:25.207027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26514 12:33:25.207432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26516 12:33:25.255404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26518 12:33:25.256099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26519 12:33:25.299314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26521 12:33:25.300059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26522 12:33:25.347198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26523 12:33:25.347725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26525 12:33:25.397667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26526 12:33:25.398159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26528 12:33:25.442487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26529 12:33:25.442981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26531 12:33:25.497153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26532 12:33:25.497704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26534 12:33:25.551376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26536 12:33:25.552019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26537 12:33:25.602910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26538 12:33:25.603361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26540 12:33:25.664503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26541 12:33:25.664955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26543 12:33:25.709925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26544 12:33:25.710339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26546 12:33:25.750025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26547 12:33:25.750566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26549 12:33:25.799473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26551 12:33:25.799972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26552 12:33:25.885378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26554 12:33:25.885882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26555 12:33:25.942937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26557 12:33:25.943327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26558 12:33:26.002353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26559 12:33:26.002802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26561 12:33:26.053626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26562 12:33:26.054039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26564 12:33:26.102910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26566 12:33:26.103346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26567 12:33:26.148932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26568 12:33:26.149375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26570 12:33:26.202292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26571 12:33:26.202689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26573 12:33:26.249134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26574 12:33:26.249567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26576 12:33:26.300930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26577 12:33:26.301338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26579 12:33:26.362756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26580 12:33:26.363205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26582 12:33:26.422845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26584 12:33:26.423306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26585 12:33:26.484539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26586 12:33:26.484997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26588 12:33:26.542370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26589 12:33:26.542807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26591 12:33:26.601898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26592 12:33:26.602382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26594 12:33:26.661903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26596 12:33:26.662345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26597 12:33:26.721355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26598 12:33:26.721872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26600 12:33:26.780651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26601 12:33:26.781106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26603 12:33:26.838954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26604 12:33:26.839355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26606 12:33:26.889961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26608 12:33:26.890408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26609 12:33:26.938692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26611 12:33:26.939162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26612 12:33:26.993287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26613 12:33:26.993685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26615 12:33:27.046009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26617 12:33:27.046488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26618 12:33:27.102153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26619 12:33:27.102550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26621 12:33:27.145412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26622 12:33:27.145827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26624 12:33:27.191571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26626 12:33:27.192113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26627 12:33:27.241246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26629 12:33:27.242037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26630 12:33:27.296352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26631 12:33:27.296783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26633 12:33:27.354661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26634 12:33:27.355103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26636 12:33:27.414993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26637 12:33:27.415436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26639 12:33:27.464173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26640 12:33:27.464606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26642 12:33:27.507187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26643 12:33:27.507620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26645 12:33:27.561627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26646 12:33:27.562102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26648 12:33:27.624223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26649 12:33:27.624631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26651 12:33:27.681214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26652 12:33:27.681606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26654 12:33:27.739030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26655 12:33:27.739438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26657 12:33:27.785697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26658 12:33:27.786123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26660 12:33:27.834782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26662 12:33:27.835261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26663 12:33:27.885935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26664 12:33:27.886327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26666 12:33:27.935052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26668 12:33:27.935503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26669 12:33:27.978362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26671 12:33:27.978800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26672 12:33:28.018482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26673 12:33:28.018941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26675 12:33:28.065391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26676 12:33:28.065849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26678 12:33:28.114895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26679 12:33:28.115316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26681 12:33:28.172492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26682 12:33:28.172934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26684 12:33:28.214589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26686 12:33:28.215080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26687 12:33:28.256518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26689 12:33:28.256994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26690 12:33:28.300050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26691 12:33:28.300494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26693 12:33:28.348397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26694 12:33:28.348833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26696 12:33:28.401386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26698 12:33:28.401888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26699 12:33:28.463985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26700 12:33:28.464422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26702 12:33:28.512333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26703 12:33:28.512782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26705 12:33:28.557416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26706 12:33:28.557828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26708 12:33:28.606237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26709 12:33:28.606702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26711 12:33:28.656332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26712 12:33:28.656765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26714 12:33:28.709931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26716 12:33:28.710370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26717 12:33:28.750150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26718 12:33:28.750636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26720 12:33:28.790035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26721 12:33:28.790467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26723 12:33:28.831099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26725 12:33:28.831577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26726 12:33:28.870016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26727 12:33:28.870532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26729 12:33:28.912651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26730 12:33:28.913081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26732 12:33:28.957003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26733 12:33:28.957499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26735 12:33:29.002520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26736 12:33:29.002957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26738 12:33:29.054290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26740 12:33:29.054772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26741 12:33:29.104462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26743 12:33:29.104947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26744 12:33:29.149120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26745 12:33:29.149577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26747 12:33:29.205856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26748 12:33:29.206279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26750 12:33:29.263387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26752 12:33:29.264011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26753 12:33:29.315486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26755 12:33:29.315942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26756 12:33:29.365909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26758 12:33:29.366382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26759 12:33:29.421600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26760 12:33:29.422044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26762 12:33:29.473379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26763 12:33:29.473799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26765 12:33:29.517931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26766 12:33:29.518367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26768 12:33:29.571382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26770 12:33:29.572016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26771 12:33:29.619047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26773 12:33:29.619533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26774 12:33:29.665713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26775 12:33:29.666201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26777 12:33:29.714258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26778 12:33:29.714704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26780 12:33:29.764904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26781 12:33:29.765341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26783 12:33:29.816950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26785 12:33:29.817429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26786 12:33:29.864556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26788 12:33:29.865022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26789 12:33:29.912868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26790 12:33:29.913276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26792 12:33:29.953238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26793 12:33:29.953682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26795 12:33:30.005437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26796 12:33:30.005841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26798 12:33:30.052183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26800 12:33:30.052606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26801 12:33:30.090853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26802 12:33:30.091293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26804 12:33:30.134126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26806 12:33:30.134597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26807 12:33:30.174626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26808 12:33:30.175080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26810 12:33:30.216330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26812 12:33:30.216803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26813 12:33:30.264021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26814 12:33:30.264484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26816 12:33:30.317027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26817 12:33:30.317443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26819 12:33:30.368450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26820 12:33:30.368870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26822 12:33:30.414584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26823 12:33:30.415027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26825 12:33:30.465402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26826 12:33:30.465851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26828 12:33:30.506927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26829 12:33:30.507380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26831 12:33:30.555437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26833 12:33:30.555926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26834 12:33:30.598990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26836 12:33:30.599475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26837 12:33:30.661211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26838 12:33:30.661686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26840 12:33:30.709176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26841 12:33:30.709601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26843 12:33:30.758756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26845 12:33:30.759237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26846 12:33:30.801491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26847 12:33:30.801922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26849 12:33:30.840507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26850 12:33:30.840939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26852 12:33:30.886612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26853 12:33:30.886995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26855 12:33:30.952070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26856 12:33:30.952454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26858 12:33:31.001664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26859 12:33:31.002087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26861 12:33:31.053666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26863 12:33:31.054130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26864 12:33:31.103405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26866 12:33:31.103885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26867 12:33:31.146688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26869 12:33:31.147166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26870 12:33:31.186722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26871 12:33:31.187157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26873 12:33:31.228695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26875 12:33:31.229505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26876 12:33:31.282672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26878 12:33:31.283478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26879 12:33:31.327548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26881 12:33:31.328074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26882 12:33:31.369447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26884 12:33:31.369894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26885 12:33:31.410078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26886 12:33:31.410573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26888 12:33:31.460999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26889 12:33:31.461460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26891 12:33:31.508373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26892 12:33:31.508830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26894 12:33:31.553839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26895 12:33:31.554270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26897 12:33:31.604573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26898 12:33:31.604985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26900 12:33:31.662016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26901 12:33:31.662459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26903 12:33:31.717721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26905 12:33:31.718183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26906 12:33:31.775932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26908 12:33:31.776431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26909 12:33:31.830057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26910 12:33:31.830513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26912 12:33:31.881782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26913 12:33:31.882233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26915 12:33:31.932737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26916 12:33:31.933172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26918 12:33:31.983002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26919 12:33:31.983440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26921 12:33:32.035942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26922 12:33:32.036443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26924 12:33:32.090782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26926 12:33:32.091318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26927 12:33:32.142991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26928 12:33:32.143436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26930 12:33:32.188896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26931 12:33:32.189337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26933 12:33:32.241702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26934 12:33:32.242153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26936 12:33:32.298993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26938 12:33:32.299483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26939 12:33:32.354482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26940 12:33:32.354920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26942 12:33:32.408186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26943 12:33:32.408620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26945 12:33:32.460582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26947 12:33:32.461052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26948 12:33:32.513047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26950 12:33:32.513572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26951 12:33:32.562671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26953 12:33:32.563448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26954 12:33:32.608493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26955 12:33:32.608963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26957 12:33:32.654840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26958 12:33:32.655248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26960 12:33:32.705141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26962 12:33:32.705627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26963 12:33:32.749392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26964 12:33:32.749856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26966 12:33:32.805863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26967 12:33:32.806343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26969 12:33:32.866952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26970 12:33:32.867503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26972 12:33:32.921974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26973 12:33:32.922369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26975 12:33:32.969617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26976 12:33:32.970137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26978 12:33:33.010177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26979 12:33:33.010639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26981 12:33:33.059191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
26983 12:33:33.059969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
26984 12:33:33.105456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
26985 12:33:33.105907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
26987 12:33:33.153961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
26988 12:33:33.154353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
26990 12:33:33.198668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
26991 12:33:33.199131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
26993 12:33:33.247417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
26995 12:33:33.247920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
26996 12:33:33.286307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
26997 12:33:33.286884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
26999 12:33:33.335625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27001 12:33:33.336239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27002 12:33:33.384159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27003 12:33:33.384637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27005 12:33:33.423452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27007 12:33:33.424068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27008 12:33:33.472246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27009 12:33:33.472685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27011 12:33:33.520903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27012 12:33:33.521312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27014 12:33:33.565567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27015 12:33:33.566033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27017 12:33:33.609324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27019 12:33:33.609831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27020 12:33:33.662271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27021 12:33:33.662763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27023 12:33:33.714604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27024 12:33:33.714997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27026 12:33:33.758388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27027 12:33:33.758840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27029 12:33:33.796886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27030 12:33:33.797381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27032 12:33:33.840401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27033 12:33:33.840935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27035 12:33:33.880462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27036 12:33:33.880891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27038 12:33:33.921383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27039 12:33:33.921828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27041 12:33:33.961103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27042 12:33:33.961483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27044 12:33:34.001815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27046 12:33:34.002401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27047 12:33:34.038147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27048 12:33:34.038580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27050 12:33:34.074041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27051 12:33:34.074477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27053 12:33:34.112005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27054 12:33:34.112397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27056 12:33:34.150154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27057 12:33:34.150667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27059 12:33:34.190550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27061 12:33:34.191316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27062 12:33:34.229438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27063 12:33:34.229944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27065 12:33:34.265779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27066 12:33:34.266222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27068 12:33:34.303294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27070 12:33:34.303981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27071 12:33:34.343533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27073 12:33:34.344028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27074 12:33:34.385444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27075 12:33:34.385873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27077 12:33:34.433773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27078 12:33:34.434193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27080 12:33:34.489731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27081 12:33:34.490149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27083 12:33:34.538068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27084 12:33:34.538609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27086 12:33:34.581053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27088 12:33:34.581491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27089 12:33:34.625312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27091 12:33:34.625823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27092 12:33:34.670979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27093 12:33:34.671420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27095 12:33:34.716627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27097 12:33:34.717119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27098 12:33:34.760139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27100 12:33:34.760609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27101 12:33:34.813596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27102 12:33:34.814053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27104 12:33:34.865749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27105 12:33:34.866198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27107 12:33:34.910115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27108 12:33:34.910588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27110 12:33:34.962690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27111 12:33:34.963119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27113 12:33:35.010101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27114 12:33:35.010537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27116 12:33:35.061441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27117 12:33:35.061907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27119 12:33:35.110947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27120 12:33:35.111345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27122 12:33:35.159205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27124 12:33:35.159703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27125 12:33:35.198019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27126 12:33:35.198733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27128 12:33:35.236906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27130 12:33:35.237676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27131 12:33:35.282927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27132 12:33:35.283493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27134 12:33:35.324037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27136 12:33:35.324745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27137 12:33:35.366394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27138 12:33:35.366820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27140 12:33:35.404642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27142 12:33:35.405234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27143 12:33:35.442695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27144 12:33:35.443167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27146 12:33:35.480524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27147 12:33:35.480893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27149 12:33:35.526686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27150 12:33:35.527107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27152 12:33:35.564671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27153 12:33:35.565242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27155 12:33:35.603290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27157 12:33:35.603811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27158 12:33:35.650772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27159 12:33:35.651213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27161 12:33:35.704622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27162 12:33:35.705009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27164 12:33:35.742908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27165 12:33:35.743357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27167 12:33:35.790425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27168 12:33:35.790860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27170 12:33:35.835866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27171 12:33:35.836327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27173 12:33:35.887088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27174 12:33:35.887728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27176 12:33:35.929943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27177 12:33:35.930399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27179 12:33:35.969932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27180 12:33:35.970519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27182 12:33:36.008174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27183 12:33:36.008720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27185 12:33:36.057958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27186 12:33:36.058326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27188 12:33:36.105689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27189 12:33:36.106196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27191 12:33:36.150681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27192 12:33:36.151161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27194 12:33:36.194310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27196 12:33:36.195078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27197 12:33:36.237221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27198 12:33:36.237707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27200 12:33:36.281212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27201 12:33:36.281616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27203 12:33:36.326464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27204 12:33:36.326902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27206 12:33:36.374888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27207 12:33:36.375341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27209 12:33:36.417060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27210 12:33:36.417522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27212 12:33:36.461090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27214 12:33:36.461563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27215 12:33:36.505680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27216 12:33:36.506116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27218 12:33:36.546279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27219 12:33:36.546740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27221 12:33:36.594291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27222 12:33:36.594705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27224 12:33:36.652797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27225 12:33:36.653188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27227 12:33:36.693059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27228 12:33:36.693558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27230 12:33:36.733117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27232 12:33:36.733530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27233 12:33:36.773668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27234 12:33:36.774073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27236 12:33:36.831628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27238 12:33:36.832414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27239 12:33:36.889112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27240 12:33:36.889499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27242 12:33:36.945374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27244 12:33:36.946051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27245 12:33:37.001115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27246 12:33:37.001592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27248 12:33:37.052064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27250 12:33:37.052547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27251 12:33:37.094869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27253 12:33:37.095267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27254 12:33:37.134078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27255 12:33:37.134479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27257 12:33:37.173892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27258 12:33:37.174309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27260 12:33:37.215527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27262 12:33:37.216105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27263 12:33:37.258146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27264 12:33:37.258598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27266 12:33:37.301152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27268 12:33:37.301624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27269 12:33:37.352602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27270 12:33:37.353083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27272 12:33:37.394305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27273 12:33:37.394742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27275 12:33:37.441963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27277 12:33:37.442437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27278 12:33:37.490634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27280 12:33:37.491175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27281 12:33:37.537716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27283 12:33:37.538218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27284 12:33:37.582092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27285 12:33:37.582527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27287 12:33:37.626118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27288 12:33:37.626559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27290 12:33:37.670816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27292 12:33:37.671304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27293 12:33:37.710210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27294 12:33:37.710648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27296 12:33:37.749604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27297 12:33:37.750057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27299 12:33:37.789009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27300 12:33:37.789475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27302 12:33:37.826733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27303 12:33:37.827180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27305 12:33:37.868506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27306 12:33:37.868903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27308 12:33:37.912180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27310 12:33:37.912596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27311 12:33:37.960636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27312 12:33:37.961067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27314 12:33:38.000761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27316 12:33:38.001187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27317 12:33:38.040686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27318 12:33:38.041109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27320 12:33:38.078008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27321 12:33:38.078399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27323 12:33:38.119431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27325 12:33:38.120037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27326 12:33:38.159467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27328 12:33:38.159949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27329 12:33:38.199998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27330 12:33:38.200455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27332 12:33:38.244433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27333 12:33:38.244837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27335 12:33:38.301339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27336 12:33:38.301787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27338 12:33:38.360600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27339 12:33:38.361031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27341 12:33:38.422429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27342 12:33:38.422900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27344 12:33:38.484703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27345 12:33:38.485092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27347 12:33:38.543164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27349 12:33:38.543607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27350 12:33:38.602603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27352 12:33:38.603413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27353 12:33:38.661545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27354 12:33:38.661939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27356 12:33:38.721560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27357 12:33:38.721980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27359 12:33:38.771415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27361 12:33:38.771880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27362 12:33:38.822084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27363 12:33:38.822517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27365 12:33:38.861393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27366 12:33:38.861781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27368 12:33:38.920685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27369 12:33:38.921118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27371 12:33:38.978845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27372 12:33:38.979281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27374 12:33:39.038690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27375 12:33:39.039180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27377 12:33:39.093272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27378 12:33:39.093692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27380 12:33:39.144250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27381 12:33:39.144757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27383 12:33:39.196977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27384 12:33:39.197415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27386 12:33:39.252182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27387 12:33:39.252590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27389 12:33:39.296766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27390 12:33:39.297196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27392 12:33:39.342275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27393 12:33:39.342710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27395 12:33:39.394304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27396 12:33:39.394751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27398 12:33:39.432419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27399 12:33:39.432856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27401 12:33:39.482786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27402 12:33:39.483239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27404 12:33:39.528515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27405 12:33:39.528962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27407 12:33:39.583384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27409 12:33:39.583868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27410 12:33:39.625224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27412 12:33:39.626087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27413 12:33:39.668979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27414 12:33:39.669415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27416 12:33:39.710463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27417 12:33:39.711109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27419 12:33:39.759955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27420 12:33:39.760437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27422 12:33:39.800735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27424 12:33:39.801199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27425 12:33:39.842729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27426 12:33:39.843178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27428 12:33:39.886545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27430 12:33:39.886952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27431 12:33:39.926591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27432 12:33:39.927005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27434 12:33:39.966493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27436 12:33:39.967154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27437 12:33:40.002182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27438 12:33:40.002642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27440 12:33:40.041448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27441 12:33:40.041877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27443 12:33:40.078575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27445 12:33:40.079011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27446 12:33:40.116399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27447 12:33:40.116797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27449 12:33:40.169115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27450 12:33:40.169528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27452 12:33:40.225108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27453 12:33:40.225668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27455 12:33:40.281548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27456 12:33:40.281941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27458 12:33:40.336995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27459 12:33:40.337457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27461 12:33:40.379456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27463 12:33:40.379941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27464 12:33:40.426706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27465 12:33:40.427143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27467 12:33:40.464822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27468 12:33:40.465253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27470 12:33:40.501722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27471 12:33:40.502140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27473 12:33:40.548569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27474 12:33:40.548997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27476 12:33:40.594380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27477 12:33:40.594739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27479 12:33:40.653238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27480 12:33:40.653739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27482 12:33:40.699888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27483 12:33:40.700285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27485 12:33:40.754539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27486 12:33:40.754936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27488 12:33:40.791499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27490 12:33:40.791985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27491 12:33:40.829922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27492 12:33:40.830354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27494 12:33:40.867943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27495 12:33:40.868374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27497 12:33:40.922512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27498 12:33:40.922985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27500 12:33:40.973135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27501 12:33:40.973535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27503 12:33:41.022270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27505 12:33:41.022681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27506 12:33:41.066312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27508 12:33:41.066734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27509 12:33:41.110946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27510 12:33:41.111374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27512 12:33:41.158375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27513 12:33:41.158786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27515 12:33:41.217899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27517 12:33:41.218665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27518 12:33:41.267914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27519 12:33:41.268354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27521 12:33:41.309330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27523 12:33:41.310183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27524 12:33:41.349218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27525 12:33:41.349708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27527 12:33:41.389461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27528 12:33:41.389941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27530 12:33:41.440387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27532 12:33:41.441066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27533 12:33:41.488431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27534 12:33:41.488883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27536 12:33:41.528782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27537 12:33:41.529223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27539 12:33:41.569368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27540 12:33:41.569814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27542 12:33:41.621556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27543 12:33:41.622005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27545 12:33:41.664452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27546 12:33:41.664895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27548 12:33:41.702188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27549 12:33:41.702577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27551 12:33:41.748946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27552 12:33:41.749331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27554 12:33:41.797744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27556 12:33:41.798508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27557 12:33:41.837237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27558 12:33:41.837679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27560 12:33:41.880253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27561 12:33:41.880695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27563 12:33:41.924961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27564 12:33:41.925397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27566 12:33:41.967025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27567 12:33:41.967465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27569 12:33:42.005333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27570 12:33:42.005764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27572 12:33:42.044746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27573 12:33:42.045217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27575 12:33:42.086273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27576 12:33:42.086701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27578 12:33:42.142058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27579 12:33:42.142480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27581 12:33:42.185906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27582 12:33:42.186301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27584 12:33:42.221634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27585 12:33:42.222164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27587 12:33:42.257510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27588 12:33:42.257958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27590 12:33:42.303265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27592 12:33:42.304049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27593 12:33:42.341925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27594 12:33:42.342484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27596 12:33:42.392642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27597 12:33:42.393064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27599 12:33:42.439821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27600 12:33:42.440261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27602 12:33:42.498930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27603 12:33:42.499371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27605 12:33:42.558569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27606 12:33:42.559005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27608 12:33:42.608493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27609 12:33:42.608936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27611 12:33:42.652174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27612 12:33:42.652622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27614 12:33:42.697944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27615 12:33:42.698329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27617 12:33:42.744319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27618 12:33:42.744753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27620 12:33:42.797278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27621 12:33:42.797689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27623 12:33:42.838249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27625 12:33:42.838813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27626 12:33:42.881189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27627 12:33:42.881586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27629 12:33:42.920389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27630 12:33:42.920853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27632 12:33:42.958102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27633 12:33:42.958570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27635 12:33:43.005595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27637 12:33:43.005983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27638 12:33:43.043054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27640 12:33:43.043529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27641 12:33:43.094150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27642 12:33:43.094551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27644 12:33:43.145813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27645 12:33:43.146206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27647 12:33:43.197324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27648 12:33:43.197691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27650 12:33:43.257473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27652 12:33:43.257908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27653 12:33:43.315480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27655 12:33:43.316141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27656 12:33:43.376691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27657 12:33:43.377079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27659 12:33:43.429726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27660 12:33:43.430162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27662 12:33:43.477173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27664 12:33:43.477613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27665 12:33:43.525850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27666 12:33:43.526288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27668 12:33:43.565409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27669 12:33:43.566016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27671 12:33:43.605582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27672 12:33:43.606090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27674 12:33:43.647070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27675 12:33:43.647538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27677 12:33:43.685901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27678 12:33:43.686336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27680 12:33:43.742253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27681 12:33:43.742743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27683 12:33:43.801726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27684 12:33:43.802159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27686 12:33:43.861083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27688 12:33:43.861531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27689 12:33:43.921378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27691 12:33:43.921878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27692 12:33:43.981556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27693 12:33:43.982035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27695 12:33:44.041066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27696 12:33:44.041472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27698 12:33:44.089449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27699 12:33:44.089899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27701 12:33:44.137400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27703 12:33:44.137900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27704 12:33:44.174982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27705 12:33:44.175429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27707 12:33:44.216443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27708 12:33:44.217004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27710 12:33:44.254478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27711 12:33:44.255005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27713 12:33:44.293822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27714 12:33:44.294246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27716 12:33:44.336775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27717 12:33:44.337210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27719 12:33:44.381079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27720 12:33:44.381488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27722 12:33:44.424695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27723 12:33:44.425124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27725 12:33:44.474191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27726 12:33:44.474669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27728 12:33:44.521901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27729 12:33:44.522332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27731 12:33:44.568153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27732 12:33:44.568584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27734 12:33:44.608806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27736 12:33:44.609281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27737 12:33:44.654430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27738 12:33:44.654822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27740 12:33:44.692328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27742 12:33:44.692771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27743 12:33:44.731998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27744 12:33:44.732436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27746 12:33:44.782309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27748 12:33:44.782785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27749 12:33:44.832147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27751 12:33:44.832602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27752 12:33:44.887955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27753 12:33:44.888398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27755 12:33:44.933528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27756 12:33:44.933967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27758 12:33:44.986981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27759 12:33:44.987418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27761 12:33:45.035778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27762 12:33:45.036202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27764 12:33:45.076703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27765 12:33:45.077099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27767 12:33:45.125634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27768 12:33:45.126142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27770 12:33:45.171080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27771 12:33:45.171544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27773 12:33:45.214099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27774 12:33:45.214498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27776 12:33:45.258486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27777 12:33:45.258959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27779 12:33:45.304904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27781 12:33:45.305402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27782 12:33:45.344380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27783 12:33:45.344833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27785 12:33:45.388706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27786 12:33:45.389161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27788 12:33:45.436238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27789 12:33:45.436656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27791 12:33:45.483927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27793 12:33:45.484406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27794 12:33:45.531422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27796 12:33:45.531948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27797 12:33:45.582693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27799 12:33:45.583083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27800 12:33:45.633546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27802 12:33:45.634267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27803 12:33:45.692065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27804 12:33:45.692637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27806 12:33:45.749254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27807 12:33:45.749680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27809 12:33:45.796103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27810 12:33:45.796534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27812 12:33:45.843073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27813 12:33:45.843418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27815 12:33:45.901857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27817 12:33:45.902601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27818 12:33:45.956564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27819 12:33:45.956979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27821 12:33:46.002003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27822 12:33:46.002455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27824 12:33:46.058996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27826 12:33:46.059436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27827 12:33:46.115173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27829 12:33:46.115889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27830 12:33:46.172215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27832 12:33:46.172695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27833 12:33:46.228241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27835 12:33:46.228733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27836 12:33:46.274392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27837 12:33:46.274812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27839 12:33:46.338320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27841 12:33:46.338789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27842 12:33:46.383576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27844 12:33:46.384078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27845 12:33:46.425795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27846 12:33:46.426228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27848 12:33:46.469447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27849 12:33:46.469880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27851 12:33:46.508835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27853 12:33:46.509303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27854 12:33:46.551090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27856 12:33:46.551572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27857 12:33:46.592836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27859 12:33:46.593261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27860 12:33:46.634885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27862 12:33:46.635693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27863 12:33:46.693101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27865 12:33:46.693582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27866 12:33:46.743508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27868 12:33:46.744111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27869 12:33:46.787300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27871 12:33:46.788044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27872 12:33:46.832813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27874 12:33:46.833394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27875 12:33:46.878670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27876 12:33:46.879119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27878 12:33:46.917980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27879 12:33:46.918407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27881 12:33:46.954513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27882 12:33:46.954958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27884 12:33:46.991821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27885 12:33:46.992257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27887 12:33:47.036072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27889 12:33:47.036521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27890 12:33:47.078780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27891 12:33:47.079177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27893 12:33:47.118027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27894 12:33:47.118449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27896 12:33:47.156673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27897 12:33:47.157175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27899 12:33:47.194483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27901 12:33:47.195094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27902 12:33:47.231431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27904 12:33:47.232059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27905 12:33:47.282250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27906 12:33:47.282731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27908 12:33:47.328451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27909 12:33:47.328887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27911 12:33:47.364919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27912 12:33:47.365426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27914 12:33:47.401108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27916 12:33:47.401572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27917 12:33:47.438231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27918 12:33:47.438654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27920 12:33:47.482282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27922 12:33:47.482924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27923 12:33:47.526231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27924 12:33:47.526611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27926 12:33:47.564882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27927 12:33:47.565293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27929 12:33:47.602659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27930 12:33:47.603061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27932 12:33:47.642708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27933 12:33:47.643143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27935 12:33:47.681579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27937 12:33:47.682083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27938 12:33:47.724753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27940 12:33:47.725234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27941 12:33:47.763925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27943 12:33:47.764310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27944 12:33:47.804379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27945 12:33:47.804784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27947 12:33:47.850266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27949 12:33:47.850648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27950 12:33:47.899911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27951 12:33:47.900297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27953 12:33:47.950853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27955 12:33:47.951456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27956 12:33:48.008135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27958 12:33:48.008623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27959 12:33:48.044791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27960 12:33:48.045227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27962 12:33:48.090616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27964 12:33:48.091037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27965 12:33:48.133304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27966 12:33:48.133753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27968 12:33:48.185307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27969 12:33:48.185872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27971 12:33:48.223410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27973 12:33:48.224089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27974 12:33:48.260726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27976 12:33:48.261171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27977 12:33:48.314694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27978 12:33:48.315124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27980 12:33:48.358664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27981 12:33:48.359046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
27983 12:33:48.410428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
27984 12:33:48.410898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
27986 12:33:48.462884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
27988 12:33:48.463361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
27989 12:33:48.520640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
27990 12:33:48.521070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
27992 12:33:48.562123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
27994 12:33:48.562501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
27995 12:33:48.619045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
27997 12:33:48.619805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
27998 12:33:48.658895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
27999 12:33:48.659434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28001 12:33:48.701757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28002 12:33:48.702241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28004 12:33:48.747002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28005 12:33:48.747445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28007 12:33:48.789041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28008 12:33:48.789488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28010 12:33:48.845225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28011 12:33:48.845788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28013 12:33:48.895982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28014 12:33:48.896540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28016 12:33:48.943348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28018 12:33:48.943770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28019 12:33:48.992854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28020 12:33:48.993316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28022 12:33:49.034484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28023 12:33:49.034917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28025 12:33:49.072700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28027 12:33:49.073127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28028 12:33:49.126366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28029 12:33:49.126780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28031 12:33:49.181147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28033 12:33:49.182020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28034 12:33:49.228395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28035 12:33:49.228879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28037 12:33:49.269865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28038 12:33:49.270375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28040 12:33:49.308340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28041 12:33:49.308813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28043 12:33:49.350159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28044 12:33:49.350724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28046 12:33:49.389465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28048 12:33:49.390259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28049 12:33:49.444715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28050 12:33:49.445172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28052 12:33:49.494508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28053 12:33:49.494965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28055 12:33:49.546198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28057 12:33:49.546678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28058 12:33:49.584350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28060 12:33:49.585036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28061 12:33:49.621188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28063 12:33:49.621671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28064 12:33:49.658201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28065 12:33:49.658676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28067 12:33:49.696981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28069 12:33:49.697463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28070 12:33:49.735323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28072 12:33:49.735798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28073 12:33:49.778648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28074 12:33:49.779078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28076 12:33:49.836599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28077 12:33:49.837062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28079 12:33:49.893352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28080 12:33:49.893787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28082 12:33:49.950260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28083 12:33:49.950682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28085 12:33:49.994544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28086 12:33:49.994930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28088 12:33:50.034519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28090 12:33:50.035003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28091 12:33:50.080894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28092 12:33:50.081331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28094 12:33:50.122816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28096 12:33:50.123316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28097 12:33:50.163363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28099 12:33:50.163876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28100 12:33:50.202764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28101 12:33:50.203223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28103 12:33:50.242161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28104 12:33:50.242610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28106 12:33:50.281391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28108 12:33:50.281848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28109 12:33:50.320502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28110 12:33:50.321056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28112 12:33:50.361659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28113 12:33:50.362093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28115 12:33:50.417393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28116 12:33:50.417832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28118 12:33:50.472799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28120 12:33:50.473228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28121 12:33:50.518461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28122 12:33:50.518834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28124 12:33:50.554130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28125 12:33:50.554562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28127 12:33:50.591908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28128 12:33:50.592328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28130 12:33:50.629280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28132 12:33:50.629918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28133 12:33:50.665088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28134 12:33:50.665580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28136 12:33:50.704859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28137 12:33:50.705238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28139 12:33:50.748480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28140 12:33:50.748984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28142 12:33:50.791089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28143 12:33:50.791527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28145 12:33:50.833794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28146 12:33:50.834235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28148 12:33:50.876271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28149 12:33:50.876677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28151 12:33:50.929329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28153 12:33:50.930108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28154 12:33:50.975032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28155 12:33:50.975425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28157 12:33:51.013304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28158 12:33:51.013688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28160 12:33:51.052093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28162 12:33:51.052513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28163 12:33:51.099422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28165 12:33:51.099889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28166 12:33:51.138021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28167 12:33:51.138436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28169 12:33:51.184951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28171 12:33:51.185429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28172 12:33:51.240487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28174 12:33:51.240970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28175 12:33:51.278790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28176 12:33:51.279184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28178 12:33:51.332353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28179 12:33:51.332790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28181 12:33:51.372137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28182 12:33:51.372535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28184 12:33:51.441240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28186 12:33:51.441620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28187 12:33:51.490444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28189 12:33:51.490861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28190 12:33:51.531074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28192 12:33:51.531502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28193 12:33:51.584853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28194 12:33:51.585239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28196 12:33:51.624672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28198 12:33:51.625155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28199 12:33:51.674396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28201 12:33:51.674883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28202 12:33:51.727375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28204 12:33:51.727851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28205 12:33:51.771889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28207 12:33:51.772579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28208 12:33:51.809247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28209 12:33:51.809707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28211 12:33:51.846637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28212 12:33:51.847067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28214 12:33:51.885201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28215 12:33:51.885619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28217 12:33:51.926062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28218 12:33:51.926481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28220 12:33:51.966907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28221 12:33:51.967331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28223 12:33:52.014689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28224 12:33:52.015109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28226 12:33:52.064649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28228 12:33:52.065134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28229 12:33:52.102336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28230 12:33:52.102760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28232 12:33:52.144609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28233 12:33:52.144995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28235 12:33:52.182557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28237 12:33:52.183041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28238 12:33:52.221867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28240 12:33:52.222540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28241 12:33:52.260745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28242 12:33:52.261300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28244 12:33:52.300561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28246 12:33:52.301182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28247 12:33:52.344774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28248 12:33:52.345236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28250 12:33:52.385824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28251 12:33:52.386220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28253 12:33:52.430946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28254 12:33:52.431395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28256 12:33:52.469959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28258 12:33:52.470422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28259 12:33:52.508391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28261 12:33:52.508883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28262 12:33:52.546593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28263 12:33:52.547023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28265 12:33:52.586498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28266 12:33:52.586921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28268 12:33:52.626928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28269 12:33:52.627385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28271 12:33:52.680480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28273 12:33:52.680948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28274 12:33:52.719242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28276 12:33:52.719906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28277 12:33:52.765866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28278 12:33:52.766393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28280 12:33:52.805613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28282 12:33:52.806333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28283 12:33:52.846067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28285 12:33:52.846690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28286 12:33:52.890930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28287 12:33:52.891413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28289 12:33:52.929691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28291 12:33:52.930164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28292 12:33:52.973613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28293 12:33:52.974053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28295 12:33:53.012478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28296 12:33:53.012923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28298 12:33:53.050298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28299 12:33:53.050726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28301 12:33:53.089033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28303 12:33:53.089496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28304 12:33:53.128053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28306 12:33:53.128513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28307 12:33:53.165722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28308 12:33:53.166111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28310 12:33:53.204528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28312 12:33:53.205010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28313 12:33:53.241989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28314 12:33:53.242443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28316 12:33:53.280688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28317 12:33:53.281093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28319 12:33:53.332160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28320 12:33:53.332547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28322 12:33:53.386694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28323 12:33:53.387120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28325 12:33:53.430567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28326 12:33:53.430933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28328 12:33:53.488470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28329 12:33:53.488888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28331 12:33:53.534986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28332 12:33:53.535377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28334 12:33:53.580716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28335 12:33:53.581147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28337 12:33:53.632111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28339 12:33:53.632540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28340 12:33:53.676280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28342 12:33:53.676678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28343 12:33:53.725561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28345 12:33:53.725991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28346 12:33:53.778050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28347 12:33:53.778423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28349 12:33:53.821944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28351 12:33:53.822428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28352 12:33:53.864655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28353 12:33:53.865084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28355 12:33:53.914953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28356 12:33:53.915371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28358 12:33:53.965733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28360 12:33:53.966306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28361 12:33:54.011441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28363 12:33:54.012096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28364 12:33:54.053140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28365 12:33:54.053540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28367 12:33:54.094987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28369 12:33:54.095537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28370 12:33:54.145448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28371 12:33:54.145854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28373 12:33:54.191454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28375 12:33:54.191943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28376 12:33:54.236098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28378 12:33:54.236569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28379 12:33:54.285702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28380 12:33:54.286075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28382 12:33:54.336559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28383 12:33:54.336990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28385 12:33:54.382066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28386 12:33:54.382560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28388 12:33:54.429850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28389 12:33:54.430254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28391 12:33:54.473362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28393 12:33:54.474027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28394 12:33:54.517467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28395 12:33:54.517840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28397 12:33:54.562322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28399 12:33:54.562909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28400 12:33:54.613008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28402 12:33:54.613490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28403 12:33:54.659379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28405 12:33:54.659831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28406 12:33:54.704627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28407 12:33:54.705081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28409 12:33:54.742273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28410 12:33:54.742663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28412 12:33:54.784678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28413 12:33:54.785117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28415 12:33:54.833424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28416 12:33:54.833765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28418 12:33:54.883282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28420 12:33:54.883793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28421 12:33:54.932033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28422 12:33:54.932434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28424 12:33:54.984910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28425 12:33:54.985301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28427 12:33:55.040231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28428 12:33:55.040663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28430 12:33:55.094570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28431 12:33:55.095011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28433 12:33:55.142190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28435 12:33:55.142675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28436 12:33:55.187339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28438 12:33:55.187826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28439 12:33:55.236017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28440 12:33:55.236520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28442 12:33:55.275075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28443 12:33:55.275530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28445 12:33:55.325229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28446 12:33:55.325668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28448 12:33:55.363093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28449 12:33:55.363530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28451 12:33:55.413634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28452 12:33:55.414091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28454 12:33:55.457443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28455 12:33:55.457879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28457 12:33:55.508396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28459 12:33:55.508819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28460 12:33:55.547858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28462 12:33:55.548287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28463 12:33:55.590267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28464 12:33:55.590663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28466 12:33:55.637182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28468 12:33:55.637822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28469 12:33:55.677538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28471 12:33:55.678016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28472 12:33:55.718237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28474 12:33:55.718704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28475 12:33:55.766350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28477 12:33:55.766810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28478 12:33:55.813729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28479 12:33:55.814149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28481 12:33:55.870849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28482 12:33:55.871299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28484 12:33:55.925075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28485 12:33:55.925493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28487 12:33:55.977776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28488 12:33:55.978196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28490 12:33:56.025246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28491 12:33:56.025695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28493 12:33:56.068138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28494 12:33:56.068574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28496 12:33:56.107039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28497 12:33:56.107484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28499 12:33:56.154022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28500 12:33:56.154447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28502 12:33:56.199410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28504 12:33:56.200094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28505 12:33:56.249680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28506 12:33:56.250117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28508 12:33:56.289756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28509 12:33:56.290207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28511 12:33:56.328302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28512 12:33:56.328752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28514 12:33:56.372879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28515 12:33:56.373327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28517 12:33:56.412773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28518 12:33:56.413164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28520 12:33:56.464620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28521 12:33:56.465050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28523 12:33:56.504436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28524 12:33:56.504888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28526 12:33:56.569272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28528 12:33:56.569715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28529 12:33:56.609530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28531 12:33:56.609989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28532 12:33:56.653038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28533 12:33:56.653541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28535 12:33:56.692948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28537 12:33:56.693443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28538 12:33:56.734890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28539 12:33:56.735325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28541 12:33:56.787934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28542 12:33:56.788326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28544 12:33:56.836647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28546 12:33:56.837133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28547 12:33:56.885882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28548 12:33:56.886338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28550 12:33:56.928023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28552 12:33:56.928450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28553 12:33:56.972635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28554 12:33:56.973043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28556 12:33:57.027292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28558 12:33:57.027741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28559 12:33:57.079339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28561 12:33:57.079823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28562 12:33:57.122809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28563 12:33:57.123235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28565 12:33:57.161931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28567 12:33:57.162551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28568 12:33:57.204361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28569 12:33:57.204875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28571 12:33:57.248368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28572 12:33:57.248776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28574 12:33:57.299007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28575 12:33:57.299437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28577 12:33:57.349111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28579 12:33:57.349600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28580 12:33:57.389006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28582 12:33:57.389486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28583 12:33:57.434014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28584 12:33:57.434504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28586 12:33:57.493810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28588 12:33:57.494291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28589 12:33:57.536337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28591 12:33:57.536717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28592 12:33:57.576217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28594 12:33:57.576687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28595 12:33:57.621055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28596 12:33:57.621511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28598 12:33:57.664861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28599 12:33:57.665276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28601 12:33:57.709167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28602 12:33:57.709698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28604 12:33:57.752230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28606 12:33:57.752694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28607 12:33:57.789392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28608 12:33:57.789823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28610 12:33:57.829713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28612 12:33:57.830195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28613 12:33:57.870929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28614 12:33:57.871342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28616 12:33:57.928264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28617 12:33:57.928688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28619 12:33:57.970453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28620 12:33:57.970877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28622 12:33:58.016499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28623 12:33:58.016993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28625 12:33:58.066681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28627 12:33:58.067312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28628 12:33:58.109278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28629 12:33:58.109694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28631 12:33:58.146990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28632 12:33:58.147411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28634 12:33:58.188774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28636 12:33:58.189237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28637 12:33:58.230974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28638 12:33:58.231433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28640 12:33:58.270917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28641 12:33:58.271387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28643 12:33:58.308563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28644 12:33:58.309028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28646 12:33:58.348144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28648 12:33:58.348635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28649 12:33:58.386149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28650 12:33:58.386582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28652 12:33:58.424917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28654 12:33:58.425373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28655 12:33:58.466466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28656 12:33:58.466896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28658 12:33:58.508523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28659 12:33:58.508953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28661 12:33:58.548469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28663 12:33:58.548933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28664 12:33:58.597186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28665 12:33:58.597613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28667 12:33:58.639383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28669 12:33:58.639852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28670 12:33:58.678761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28671 12:33:58.679161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28673 12:33:58.717213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28675 12:33:58.717641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28676 12:33:58.756282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28677 12:33:58.756669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28679 12:33:58.797952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28680 12:33:58.798377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28682 12:33:58.838413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28684 12:33:58.838886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28685 12:33:58.886239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28686 12:33:58.886739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28688 12:33:58.938244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28689 12:33:58.938736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28691 12:33:58.982058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28692 12:33:58.982581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28694 12:33:59.020803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28696 12:33:59.021425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28697 12:33:59.061936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28698 12:33:59.062353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28700 12:33:59.102983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28701 12:33:59.103436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28703 12:33:59.142522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28705 12:33:59.142992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28706 12:33:59.182454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28707 12:33:59.182868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28709 12:33:59.221406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28710 12:33:59.221877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28712 12:33:59.260582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28713 12:33:59.261032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28715 12:33:59.300979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28716 12:33:59.301414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28718 12:33:59.349468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28720 12:33:59.349942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28721 12:33:59.396111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28723 12:33:59.396608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28724 12:33:59.453909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28726 12:33:59.454387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28727 12:33:59.513550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28728 12:33:59.513933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28730 12:33:59.568059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28731 12:33:59.568509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28733 12:33:59.605390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28734 12:33:59.605970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28736 12:33:59.653409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28737 12:33:59.653797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28739 12:33:59.698054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28740 12:33:59.698469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28742 12:33:59.736609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28744 12:33:59.737008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28745 12:33:59.791266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28747 12:33:59.791703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28748 12:33:59.852588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28749 12:33:59.853066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28751 12:33:59.894208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28753 12:33:59.894639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28754 12:33:59.933762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28756 12:33:59.934154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28757 12:33:59.984343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28759 12:33:59.984845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28760 12:34:00.030817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28761 12:34:00.031229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28763 12:34:00.077538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28764 12:34:00.077994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28766 12:34:00.116152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28767 12:34:00.116585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28769 12:34:00.154967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28771 12:34:00.155444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28772 12:34:00.198869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28774 12:34:00.199319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28775 12:34:00.246433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28776 12:34:00.246819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28778 12:34:00.288924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28780 12:34:00.289400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28781 12:34:00.328604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28782 12:34:00.329157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28784 12:34:00.368871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28785 12:34:00.369301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28787 12:34:00.414415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28788 12:34:00.414863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28790 12:34:00.457269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28792 12:34:00.457788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28793 12:34:00.500670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28794 12:34:00.501076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28796 12:34:00.554859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28797 12:34:00.555250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28799 12:34:00.601931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28800 12:34:00.602321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28802 12:34:00.653834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28804 12:34:00.654338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28805 12:34:00.704826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28806 12:34:00.705269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28808 12:34:00.761623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28809 12:34:00.762072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28811 12:34:00.812922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28812 12:34:00.813337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28814 12:34:00.857962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28816 12:34:00.858338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28817 12:34:00.900415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28818 12:34:00.900862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28820 12:34:00.954388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28821 12:34:00.954729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28823 12:34:01.001549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28824 12:34:01.001927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28826 12:34:01.050816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28828 12:34:01.051387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28829 12:34:01.091616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28830 12:34:01.092077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28832 12:34:01.130310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28833 12:34:01.130718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28835 12:34:01.175263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28837 12:34:01.176053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28838 12:34:01.214837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28840 12:34:01.215320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28841 12:34:01.261263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28842 12:34:01.261694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28844 12:34:01.309197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28845 12:34:01.309659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28847 12:34:01.350447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28848 12:34:01.350905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28850 12:34:01.396833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28851 12:34:01.397300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28853 12:34:01.445619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28854 12:34:01.446101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28856 12:34:01.503445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28858 12:34:01.503929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28859 12:34:01.558940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28861 12:34:01.559414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28862 12:34:01.609881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28864 12:34:01.610347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28865 12:34:01.670378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28866 12:34:01.670810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28868 12:34:01.710643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28869 12:34:01.711063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28871 12:34:01.747060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28872 12:34:01.747514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28874 12:34:01.785958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28875 12:34:01.786407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28877 12:34:01.829588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28878 12:34:01.830018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28880 12:34:01.867011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28881 12:34:01.867460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28883 12:34:01.914399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28885 12:34:01.914975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28886 12:34:01.964163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28887 12:34:01.964567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28889 12:34:02.014305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28891 12:34:02.014890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28892 12:34:02.057301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28894 12:34:02.057780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28895 12:34:02.097713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28896 12:34:02.098146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28898 12:34:02.137422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28900 12:34:02.137912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28901 12:34:02.184796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28902 12:34:02.185245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28904 12:34:02.219941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28905 12:34:02.220340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28907 12:34:02.254220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28909 12:34:02.254986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28910 12:34:02.288287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28911 12:34:02.288725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28913 12:34:02.325884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28915 12:34:02.326596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28916 12:34:02.363185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28918 12:34:02.363592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28919 12:34:02.409808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28921 12:34:02.410296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28922 12:34:02.446637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28923 12:34:02.447018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28925 12:34:02.486481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28927 12:34:02.486925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28928 12:34:02.523314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28930 12:34:02.523759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28931 12:34:02.562209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28932 12:34:02.562628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28934 12:34:02.597518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28936 12:34:02.597958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28937 12:34:02.636707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28938 12:34:02.637215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28940 12:34:02.686338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28942 12:34:02.686790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28943 12:34:02.720752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28944 12:34:02.721161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28946 12:34:02.772559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28947 12:34:02.772996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28949 12:34:02.814253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28950 12:34:02.814714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28952 12:34:02.853412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28954 12:34:02.853902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28955 12:34:02.895539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28957 12:34:02.895994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28958 12:34:02.936010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28959 12:34:02.936445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28961 12:34:02.972502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28963 12:34:02.972894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28964 12:34:03.027657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28966 12:34:03.028057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28967 12:34:03.076266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28969 12:34:03.076744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28970 12:34:03.112726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28971 12:34:03.113172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28973 12:34:03.147861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28975 12:34:03.148542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28976 12:34:03.189860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28978 12:34:03.190514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28979 12:34:03.226566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28981 12:34:03.227220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
28982 12:34:03.264643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
28983 12:34:03.265153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
28985 12:34:03.300571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
28987 12:34:03.301265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
28988 12:34:03.346808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
28989 12:34:03.347279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
28991 12:34:03.390010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
28992 12:34:03.390570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
28994 12:34:03.433440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
28995 12:34:03.433842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
28997 12:34:03.474099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
28998 12:34:03.474550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29000 12:34:03.522051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29001 12:34:03.522498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29003 12:34:03.574822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29004 12:34:03.575384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29006 12:34:03.631954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29007 12:34:03.632379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29009 12:34:03.682055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29010 12:34:03.682486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29012 12:34:03.725234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29014 12:34:03.725691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29015 12:34:03.769360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29017 12:34:03.769851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29018 12:34:03.818520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29019 12:34:03.818962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29021 12:34:03.860817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29023 12:34:03.861270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29024 12:34:03.906726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29026 12:34:03.907200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29027 12:34:03.955119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29029 12:34:03.955598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29030 12:34:04.006599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29031 12:34:04.007044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29033 12:34:04.043389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29035 12:34:04.043830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29036 12:34:04.101357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29038 12:34:04.101798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29039 12:34:04.144123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29040 12:34:04.144557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29042 12:34:04.194316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29043 12:34:04.194760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29045 12:34:04.232869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29046 12:34:04.233269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29048 12:34:04.282490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29049 12:34:04.282916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29051 12:34:04.331294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29053 12:34:04.331766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29054 12:34:04.374623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29055 12:34:04.375068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29057 12:34:04.416737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29058 12:34:04.417136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29060 12:34:04.456373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29061 12:34:04.456817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29063 12:34:04.494571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29064 12:34:04.494975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29066 12:34:04.533344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29067 12:34:04.533766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29069 12:34:04.569962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29071 12:34:04.570748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29072 12:34:04.613720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29074 12:34:04.614186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29075 12:34:04.653233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29076 12:34:04.653631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29078 12:34:04.688533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29079 12:34:04.688987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29081 12:34:04.728045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29083 12:34:04.728528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29084 12:34:04.771026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29085 12:34:04.771460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29087 12:34:04.810268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29088 12:34:04.810746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29090 12:34:04.848983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29091 12:34:04.849563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29093 12:34:04.898994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29094 12:34:04.899442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29096 12:34:04.941224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29098 12:34:04.941604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29099 12:34:04.989113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29100 12:34:04.989569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29102 12:34:05.024694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29104 12:34:05.025165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29105 12:34:05.062078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29106 12:34:05.062535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29108 12:34:05.100340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29109 12:34:05.100766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29111 12:34:05.137849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29112 12:34:05.138262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29114 12:34:05.192571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29116 12:34:05.193162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29117 12:34:05.242079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29118 12:34:05.242865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29120 12:34:05.286035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29121 12:34:05.286574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29123 12:34:05.336708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29124 12:34:05.337137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29126 12:34:05.372793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29127 12:34:05.373708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29129 12:34:05.408424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29130 12:34:05.408881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29132 12:34:05.447910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29133 12:34:05.448373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29135 12:34:05.488721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29137 12:34:05.489204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29138 12:34:05.528952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29140 12:34:05.529434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29141 12:34:05.573881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29142 12:34:05.574332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29144 12:34:05.620351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29145 12:34:05.620761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29147 12:34:05.657502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29148 12:34:05.658002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29150 12:34:05.700104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29151 12:34:05.700499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29153 12:34:05.742898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29155 12:34:05.743378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29156 12:34:05.792529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29157 12:34:05.792923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29159 12:34:05.845010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29160 12:34:05.845574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29162 12:34:05.897747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29163 12:34:05.898172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29165 12:34:05.939491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29167 12:34:05.939951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29168 12:34:05.994131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29169 12:34:05.994569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29171 12:34:06.032968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29173 12:34:06.033430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29174 12:34:06.068420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29175 12:34:06.068854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29177 12:34:06.106380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29178 12:34:06.106800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29180 12:34:06.148351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29182 12:34:06.148796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29183 12:34:06.184155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29184 12:34:06.184594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29186 12:34:06.220781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29187 12:34:06.221188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29189 12:34:06.265534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29190 12:34:06.266118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29192 12:34:06.305968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29194 12:34:06.306461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29195 12:34:06.341941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29197 12:34:06.342370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29198 12:34:06.378230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29200 12:34:06.378716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29201 12:34:06.413722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29202 12:34:06.414168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29204 12:34:06.449185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29205 12:34:06.449661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29207 12:34:06.485548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29208 12:34:06.485984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29210 12:34:06.530339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29211 12:34:06.530742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29213 12:34:06.578332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29214 12:34:06.578785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29216 12:34:06.624057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29218 12:34:06.624483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29219 12:34:06.669545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29220 12:34:06.669943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29222 12:34:06.716790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29224 12:34:06.717260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29225 12:34:06.774358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29226 12:34:06.774938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29228 12:34:06.834849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29229 12:34:06.835291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29231 12:34:06.869360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29233 12:34:06.869975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29234 12:34:06.904598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29236 12:34:06.905350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29237 12:34:06.944382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29238 12:34:06.944898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29240 12:34:06.989443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29242 12:34:06.989882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29243 12:34:07.040374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29244 12:34:07.040806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29246 12:34:07.084690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29247 12:34:07.085249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29249 12:34:07.139890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29250 12:34:07.140282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29252 12:34:07.195950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29254 12:34:07.196388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29255 12:34:07.245264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29256 12:34:07.245683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29258 12:34:07.288503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29259 12:34:07.288942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29261 12:34:07.328834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29262 12:34:07.329347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29264 12:34:07.381476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29266 12:34:07.381931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29267 12:34:07.419380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29269 12:34:07.419828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29270 12:34:07.461496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29272 12:34:07.461978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29273 12:34:07.501279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29274 12:34:07.501696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29276 12:34:07.543848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29277 12:34:07.544336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29279 12:34:07.580307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29281 12:34:07.580779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29282 12:34:07.617169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29283 12:34:07.617597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29285 12:34:07.652503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29287 12:34:07.652975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29288 12:34:07.688801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29289 12:34:07.689226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29291 12:34:07.726045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29292 12:34:07.726466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29294 12:34:07.770383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29295 12:34:07.770774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29297 12:34:07.808577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29298 12:34:07.809006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29300 12:34:07.848371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29301 12:34:07.848805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29303 12:34:07.891810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29305 12:34:07.892186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29306 12:34:07.934041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29307 12:34:07.934423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29309 12:34:07.970912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29311 12:34:07.971341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29312 12:34:08.011850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29313 12:34:08.012260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29315 12:34:08.053321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29316 12:34:08.053829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29318 12:34:08.102445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29319 12:34:08.102941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29321 12:34:08.140445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29323 12:34:08.141097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29324 12:34:08.177336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29325 12:34:08.177920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29327 12:34:08.230263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29328 12:34:08.230675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29330 12:34:08.276108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29331 12:34:08.276560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29333 12:34:08.316698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29335 12:34:08.317489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29336 12:34:08.368579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29338 12:34:08.369376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29339 12:34:08.404031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29340 12:34:08.404456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29342 12:34:08.441149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29343 12:34:08.441717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29345 12:34:08.480952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29347 12:34:08.481390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29348 12:34:08.522300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29349 12:34:08.522762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29351 12:34:08.562828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29352 12:34:08.563267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29354 12:34:08.608667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29355 12:34:08.609103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29357 12:34:08.645020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29358 12:34:08.645456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29360 12:34:08.695973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29361 12:34:08.696387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29363 12:34:08.736447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29365 12:34:08.737182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29366 12:34:08.771977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29367 12:34:08.772444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29369 12:34:08.810022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29370 12:34:08.810451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29372 12:34:08.861156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29374 12:34:08.861659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29375 12:34:08.912653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29376 12:34:08.913105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29378 12:34:08.966865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29379 12:34:08.967304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29381 12:34:09.004819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29383 12:34:09.005296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29384 12:34:09.050146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29385 12:34:09.050522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29387 12:34:09.098570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29388 12:34:09.098994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29390 12:34:09.134557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29391 12:34:09.134949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29393 12:34:09.172590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29395 12:34:09.173064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29396 12:34:09.206538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29397 12:34:09.206987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29399 12:34:09.244275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29400 12:34:09.244700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29402 12:34:09.290795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29404 12:34:09.291443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29405 12:34:09.328075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29406 12:34:09.328492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29408 12:34:09.382255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29409 12:34:09.382686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29411 12:34:09.421053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29412 12:34:09.421451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29414 12:34:09.456342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29416 12:34:09.456933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29417 12:34:09.491613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29419 12:34:09.492208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29420 12:34:09.533887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29421 12:34:09.534279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29423 12:34:09.575364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29425 12:34:09.575862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29426 12:34:09.618644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29427 12:34:09.619104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29429 12:34:09.656488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29431 12:34:09.656864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29432 12:34:09.696092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29433 12:34:09.696638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29435 12:34:09.742341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29436 12:34:09.742801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29438 12:34:09.780934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29440 12:34:09.781579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29441 12:34:09.829822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29442 12:34:09.830356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29444 12:34:09.864466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29445 12:34:09.865036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29447 12:34:09.911324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29449 12:34:09.911799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29450 12:34:09.965168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29451 12:34:09.965572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29453 12:34:10.012716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29454 12:34:10.013079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29456 12:34:10.060815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29457 12:34:10.061222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29459 12:34:10.096946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29460 12:34:10.097329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29462 12:34:10.137218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29463 12:34:10.137697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29465 12:34:10.174856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29466 12:34:10.175312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29468 12:34:10.214151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29470 12:34:10.214588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29471 12:34:10.250219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29472 12:34:10.250652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29474 12:34:10.286855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29475 12:34:10.287275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29477 12:34:10.331928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29479 12:34:10.332402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29480 12:34:10.369424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29481 12:34:10.369856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29483 12:34:10.418936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29484 12:34:10.419332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29486 12:34:10.456642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29487 12:34:10.457205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29489 12:34:10.494452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29490 12:34:10.494897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29492 12:34:10.534591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29493 12:34:10.535053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29495 12:34:10.571399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29496 12:34:10.571974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29498 12:34:10.612057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29499 12:34:10.612498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29501 12:34:10.646980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29502 12:34:10.647326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29504 12:34:10.682563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29506 12:34:10.683053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29507 12:34:10.718152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29508 12:34:10.718576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29510 12:34:10.754769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29511 12:34:10.755220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29513 12:34:10.795371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29515 12:34:10.795828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29516 12:34:10.854122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29517 12:34:10.854543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29519 12:34:10.890883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29520 12:34:10.891303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29522 12:34:10.927104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29523 12:34:10.927461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29525 12:34:10.977455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29526 12:34:10.977898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29528 12:34:11.023695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29529 12:34:11.024103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29531 12:34:11.070679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29532 12:34:11.071118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29534 12:34:11.118870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29535 12:34:11.119313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29537 12:34:11.173325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29539 12:34:11.173774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29540 12:34:11.221584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29542 12:34:11.222401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29543 12:34:11.271479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29545 12:34:11.271928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29546 12:34:11.324768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29548 12:34:11.325196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29549 12:34:11.365969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29551 12:34:11.366664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29552 12:34:11.405952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29553 12:34:11.406449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29555 12:34:11.444572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29556 12:34:11.445021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29558 12:34:11.483737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29559 12:34:11.484199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29561 12:34:11.531973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29562 12:34:11.532358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29564 12:34:11.574132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29565 12:34:11.574586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29567 12:34:11.612511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29568 12:34:11.612899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29570 12:34:11.650497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29571 12:34:11.650954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29573 12:34:11.694029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29574 12:34:11.694461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29576 12:34:11.744550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29577 12:34:11.745009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29579 12:34:11.786860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29580 12:34:11.787307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29582 12:34:11.834127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29583 12:34:11.834559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29585 12:34:11.873573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29586 12:34:11.874007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29588 12:34:11.937888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29590 12:34:11.938381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29591 12:34:11.984812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29592 12:34:11.985259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29594 12:34:12.040420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29596 12:34:12.040865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29597 12:34:12.077977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29598 12:34:12.078430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29600 12:34:12.117242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29601 12:34:12.117716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29603 12:34:12.154249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29605 12:34:12.155020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29606 12:34:12.192805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29608 12:34:12.193379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29609 12:34:12.242392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29610 12:34:12.242889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29612 12:34:12.282472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29613 12:34:12.282863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29615 12:34:12.316635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29616 12:34:12.317106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29618 12:34:12.356823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29620 12:34:12.357230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29621 12:34:12.401668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29623 12:34:12.402141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29624 12:34:12.449358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29626 12:34:12.449956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29627 12:34:12.492804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29628 12:34:12.493236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29630 12:34:12.533026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29631 12:34:12.533516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29633 12:34:12.582347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29634 12:34:12.582837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29636 12:34:12.622971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29637 12:34:12.623440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29639 12:34:12.660318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29640 12:34:12.660769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29642 12:34:12.696106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29643 12:34:12.696552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29645 12:34:12.745040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29647 12:34:12.745793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29648 12:34:12.782930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29649 12:34:12.783339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29651 12:34:12.822621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29653 12:34:12.823137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29654 12:34:12.858068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29655 12:34:12.858478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29657 12:34:12.894116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29658 12:34:12.894509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29660 12:34:12.932378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29661 12:34:12.932825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29663 12:34:12.970255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29664 12:34:12.970698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29666 12:34:13.008382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29667 12:34:13.008832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29669 12:34:13.052151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29670 12:34:13.052569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29672 12:34:13.090392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29673 12:34:13.090846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29675 12:34:13.126348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29677 12:34:13.126883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29678 12:34:13.174102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29679 12:34:13.174570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29681 12:34:13.229866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29682 12:34:13.230458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29684 12:34:13.285797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29686 12:34:13.286451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29687 12:34:13.342717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29688 12:34:13.343121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29690 12:34:13.382705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29692 12:34:13.383107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29693 12:34:13.428769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29694 12:34:13.429177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29696 12:34:13.474011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29697 12:34:13.474455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29699 12:34:13.516369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29700 12:34:13.516991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29702 12:34:13.569532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29703 12:34:13.569986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29705 12:34:13.620066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29706 12:34:13.620450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29708 12:34:13.660454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29709 12:34:13.660912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29711 12:34:13.705819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29712 12:34:13.706249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29714 12:34:13.752417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29715 12:34:13.752862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29717 12:34:13.791232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29718 12:34:13.791648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29720 12:34:13.829865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29721 12:34:13.830251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29723 12:34:13.867731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29725 12:34:13.868429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29726 12:34:13.905693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29728 12:34:13.906365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29729 12:34:13.948358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29730 12:34:13.948866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29732 12:34:13.988539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29733 12:34:13.988944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29735 12:34:14.028684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29736 12:34:14.029047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29738 12:34:14.069218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29739 12:34:14.069622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29741 12:34:14.110050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29743 12:34:14.110399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29744 12:34:14.158196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29746 12:34:14.158734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29747 12:34:14.210505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29749 12:34:14.211256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29750 12:34:14.253973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29751 12:34:14.254411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29753 12:34:14.299903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29754 12:34:14.300353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29756 12:34:14.341927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29757 12:34:14.342333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29759 12:34:14.392746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29760 12:34:14.393167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29762 12:34:14.437658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29764 12:34:14.438141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29765 12:34:14.496606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29766 12:34:14.497034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29768 12:34:14.548071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29769 12:34:14.548532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29771 12:34:14.605212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29773 12:34:14.605712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29774 12:34:14.666055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29775 12:34:14.666495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29777 12:34:14.712487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29778 12:34:14.712918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29780 12:34:14.758256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29781 12:34:14.758710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29783 12:34:14.821596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29785 12:34:14.822100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29786 12:34:14.867148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29788 12:34:14.867614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29789 12:34:14.906432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29791 12:34:14.906818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29792 12:34:14.949121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29794 12:34:14.949546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29795 12:34:14.993124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29796 12:34:14.993531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29798 12:34:15.036442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29799 12:34:15.036868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29801 12:34:15.078285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29802 12:34:15.078691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29804 12:34:15.121860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29806 12:34:15.122521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29807 12:34:15.161012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29809 12:34:15.161467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29810 12:34:15.200548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29812 12:34:15.201041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29813 12:34:15.241945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29814 12:34:15.242377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29816 12:34:15.282138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29817 12:34:15.282590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29819 12:34:15.322073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29821 12:34:15.322547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29822 12:34:15.361352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29823 12:34:15.361779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29825 12:34:15.400653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29827 12:34:15.401110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29828 12:34:15.439830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29829 12:34:15.440280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29831 12:34:15.479898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29832 12:34:15.480327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29834 12:34:15.518312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29836 12:34:15.518786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29837 12:34:15.557291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29838 12:34:15.557694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29840 12:34:15.596286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29841 12:34:15.596745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29843 12:34:15.634930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29844 12:34:15.635359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29846 12:34:15.674196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29848 12:34:15.674675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29849 12:34:15.713698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29851 12:34:15.714163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29852 12:34:15.752515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29853 12:34:15.752964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29855 12:34:15.792218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29856 12:34:15.792664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29858 12:34:15.833864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29859 12:34:15.834311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29861 12:34:15.882191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29863 12:34:15.882673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29864 12:34:15.929414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29865 12:34:15.929862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29867 12:34:15.974899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29868 12:34:15.975388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29870 12:34:16.014496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29871 12:34:16.014950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29873 12:34:16.070576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29874 12:34:16.071015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29876 12:34:16.119035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29878 12:34:16.119502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29879 12:34:16.160609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29881 12:34:16.161079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29882 12:34:16.201711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29884 12:34:16.202188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29885 12:34:16.251073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29887 12:34:16.251547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29888 12:34:16.290822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29889 12:34:16.291251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29891 12:34:16.330593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29892 12:34:16.331036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29894 12:34:16.370005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29895 12:34:16.370417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29897 12:34:16.408801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29898 12:34:16.409226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29900 12:34:16.448812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29901 12:34:16.449260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29903 12:34:16.488470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29904 12:34:16.488872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29906 12:34:16.527183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29908 12:34:16.527740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29909 12:34:16.565775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29910 12:34:16.566196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29912 12:34:16.610634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29914 12:34:16.611353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29915 12:34:16.670034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29916 12:34:16.670504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29918 12:34:16.730206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29919 12:34:16.730678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29921 12:34:16.790687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29922 12:34:16.791108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29924 12:34:16.849622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29925 12:34:16.850039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29927 12:34:16.908366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29929 12:34:16.908998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29930 12:34:16.966393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29931 12:34:16.966806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29933 12:34:17.050087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29934 12:34:17.050540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29936 12:34:17.110297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29938 12:34:17.110662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29939 12:34:17.170550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29940 12:34:17.171021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29942 12:34:17.230489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29943 12:34:17.230908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29945 12:34:17.290900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29946 12:34:17.291365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29948 12:34:17.350383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29949 12:34:17.350870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29951 12:34:17.410060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29952 12:34:17.410406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29954 12:34:17.449743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29955 12:34:17.450293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29957 12:34:17.488540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29958 12:34:17.488911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29960 12:34:17.527721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29961 12:34:17.528129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29963 12:34:17.566539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29965 12:34:17.567057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29966 12:34:17.605799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29968 12:34:17.606555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29969 12:34:17.644991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29971 12:34:17.645431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29972 12:34:17.683817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29973 12:34:17.684241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29975 12:34:17.723053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29976 12:34:17.723485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29978 12:34:17.764790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29979 12:34:17.765241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29981 12:34:17.805307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
29983 12:34:17.805788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
29984 12:34:17.845118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
29986 12:34:17.845593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
29987 12:34:17.885861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
29988 12:34:17.886269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
29990 12:34:17.926322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
29992 12:34:17.926791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
29993 12:34:17.968576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
29995 12:34:17.969051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
29996 12:34:18.009113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
29997 12:34:18.009551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
29999 12:34:18.048855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30000 12:34:18.049252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30002 12:34:18.088780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30003 12:34:18.089172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30005 12:34:18.128342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30006 12:34:18.128773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30008 12:34:18.169409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30009 12:34:18.169931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30011 12:34:18.210033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30012 12:34:18.210457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30014 12:34:18.250497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30015 12:34:18.250938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30017 12:34:18.291071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30018 12:34:18.291439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30020 12:34:18.332542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30021 12:34:18.332900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30023 12:34:18.392283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30024 12:34:18.392620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30026 12:34:18.433411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30027 12:34:18.433830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30029 12:34:18.491916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30030 12:34:18.492313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30032 12:34:18.549865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30034 12:34:18.550515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30035 12:34:18.609225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30036 12:34:18.609761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30038 12:34:18.668537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30039 12:34:18.668937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30041 12:34:18.728239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30042 12:34:18.728694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30044 12:34:18.787350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30046 12:34:18.787878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30047 12:34:18.840975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30048 12:34:18.841361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30050 12:34:18.885140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30051 12:34:18.885530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30053 12:34:18.926577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30054 12:34:18.927012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30056 12:34:18.969447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30058 12:34:18.969942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30059 12:34:19.008490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30060 12:34:19.008885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30062 12:34:19.041921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30063 12:34:19.042346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30065 12:34:19.077997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30066 12:34:19.078395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30068 12:34:19.120362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30070 12:34:19.120786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30071 12:34:19.158920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30072 12:34:19.159355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30074 12:34:19.201714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30076 12:34:19.202177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30077 12:34:19.246897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30078 12:34:19.247321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30080 12:34:19.283972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30081 12:34:19.284371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30083 12:34:19.322094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30085 12:34:19.322472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30086 12:34:19.361535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30088 12:34:19.362107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30089 12:34:19.397854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30090 12:34:19.398396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30092 12:34:19.436711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30093 12:34:19.437135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30095 12:34:19.478205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30097 12:34:19.478661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30098 12:34:19.515753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30100 12:34:19.516187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30101 12:34:19.557858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30102 12:34:19.558266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30104 12:34:19.600983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30105 12:34:19.601393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30107 12:34:19.641211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30108 12:34:19.641657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30110 12:34:19.678006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30112 12:34:19.678509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30113 12:34:19.729081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30115 12:34:19.729560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30116 12:34:19.776899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30117 12:34:19.777374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30119 12:34:19.820445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30120 12:34:19.820942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30122 12:34:19.857273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30123 12:34:19.857699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30125 12:34:19.898816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30126 12:34:19.899207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30128 12:34:19.945410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30130 12:34:19.945860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30131 12:34:19.993724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30132 12:34:19.994179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30134 12:34:20.037190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30136 12:34:20.037680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30137 12:34:20.074950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30139 12:34:20.075433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30140 12:34:20.114541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30141 12:34:20.114933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30143 12:34:20.152557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30144 12:34:20.152992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30146 12:34:20.200419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30147 12:34:20.200915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30149 12:34:20.236707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30150 12:34:20.237167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30152 12:34:20.273704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30153 12:34:20.274138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30155 12:34:20.311258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30157 12:34:20.311737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30158 12:34:20.350836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30159 12:34:20.351252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30161 12:34:20.391022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30163 12:34:20.391512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30164 12:34:20.433204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30165 12:34:20.433619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30167 12:34:20.473053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30168 12:34:20.473514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30170 12:34:20.513628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30172 12:34:20.514105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30173 12:34:20.553569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30174 12:34:20.554027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30176 12:34:20.606738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30178 12:34:20.607224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30179 12:34:20.658933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30181 12:34:20.659410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30182 12:34:20.711473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30184 12:34:20.711957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30185 12:34:20.749873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30186 12:34:20.750296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30188 12:34:20.796592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30189 12:34:20.797059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30191 12:34:20.849717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30192 12:34:20.850121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30194 12:34:20.911366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30196 12:34:20.911828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30197 12:34:20.972714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30198 12:34:20.973077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30200 12:34:21.026205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30201 12:34:21.026603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30203 12:34:21.067192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30205 12:34:21.067680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30206 12:34:21.106600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30208 12:34:21.107066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30209 12:34:21.149277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30210 12:34:21.149703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30212 12:34:21.208814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30214 12:34:21.209300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30215 12:34:21.254636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30216 12:34:21.255119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30218 12:34:21.296098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30219 12:34:21.296506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30221 12:34:21.340574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30222 12:34:21.341031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30224 12:34:21.386005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30226 12:34:21.386591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30227 12:34:21.426131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30228 12:34:21.426535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30230 12:34:21.467991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30232 12:34:21.468472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30233 12:34:21.509860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30235 12:34:21.510346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30236 12:34:21.553042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30237 12:34:21.553480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30239 12:34:21.597943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30240 12:34:21.598380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30242 12:34:21.642623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30243 12:34:21.643021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30245 12:34:21.682433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30246 12:34:21.682848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30248 12:34:21.721877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30250 12:34:21.722250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30251 12:34:21.774873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30252 12:34:21.775252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30254 12:34:21.809929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30255 12:34:21.810392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30257 12:34:21.843949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30258 12:34:21.844371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30260 12:34:21.881216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30261 12:34:21.881668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30263 12:34:21.929836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30264 12:34:21.930249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30266 12:34:21.977018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30267 12:34:21.977527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30269 12:34:22.026159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30271 12:34:22.026618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30272 12:34:22.065472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30274 12:34:22.065903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30275 12:34:22.107064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30277 12:34:22.107546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30278 12:34:22.184943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30279 12:34:22.185400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30281 12:34:22.226171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30282 12:34:22.226563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30284 12:34:22.270356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30286 12:34:22.270781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30287 12:34:22.309305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30289 12:34:22.309790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30290 12:34:22.346979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30291 12:34:22.347422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30293 12:34:22.382948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30294 12:34:22.383342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30296 12:34:22.417777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30297 12:34:22.418196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30299 12:34:22.458314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30300 12:34:22.458754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30302 12:34:22.497067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30304 12:34:22.497500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30305 12:34:22.534227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30306 12:34:22.534613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30308 12:34:22.578198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30309 12:34:22.578591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30311 12:34:22.613448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30312 12:34:22.613885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30314 12:34:22.657111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30316 12:34:22.657536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30317 12:34:22.705003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30318 12:34:22.705386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30320 12:34:22.752404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30321 12:34:22.752818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30323 12:34:22.789089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30324 12:34:22.789680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30326 12:34:22.830620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30328 12:34:22.831051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30329 12:34:22.888547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30331 12:34:22.889024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30332 12:34:22.942133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30333 12:34:22.942550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30335 12:34:22.990267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30337 12:34:22.990748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30338 12:34:23.036531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30340 12:34:23.037111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30341 12:34:23.077426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30342 12:34:23.077861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30344 12:34:23.117505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30345 12:34:23.117931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30347 12:34:23.157481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30348 12:34:23.157911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30350 12:34:23.196997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30352 12:34:23.197450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30353 12:34:23.237411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30355 12:34:23.237887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30356 12:34:23.276711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30357 12:34:23.277158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30359 12:34:23.316657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30361 12:34:23.317125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30362 12:34:23.358028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30363 12:34:23.358455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30365 12:34:23.398620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30366 12:34:23.398974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30368 12:34:23.440637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30369 12:34:23.441007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30371 12:34:23.484354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30373 12:34:23.484849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30374 12:34:23.526555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30375 12:34:23.527011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30377 12:34:23.573197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30379 12:34:23.573697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30380 12:34:23.619906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30381 12:34:23.620293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30383 12:34:23.661110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30384 12:34:23.661569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30386 12:34:23.713406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30387 12:34:23.713841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30389 12:34:23.761709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30390 12:34:23.762161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30392 12:34:23.807693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30393 12:34:23.808123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30395 12:34:23.855818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30396 12:34:23.856273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30398 12:34:23.904068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30399 12:34:23.904505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30401 12:34:23.949157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30402 12:34:23.949554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30404 12:34:23.994681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30406 12:34:23.995116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30407 12:34:24.033066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30408 12:34:24.033491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30410 12:34:24.072507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30412 12:34:24.072996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30413 12:34:24.113685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30414 12:34:24.114112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30416 12:34:24.158202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30418 12:34:24.158689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30419 12:34:24.210153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30421 12:34:24.210623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30422 12:34:24.248545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30424 12:34:24.249015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30425 12:34:24.285480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30426 12:34:24.285910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30428 12:34:24.324454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30429 12:34:24.324846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30431 12:34:24.361827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30432 12:34:24.362238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30434 12:34:24.400170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30436 12:34:24.400642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30437 12:34:24.437871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30438 12:34:24.438301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30440 12:34:24.485292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30441 12:34:24.485745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30443 12:34:24.530741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30444 12:34:24.531195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30446 12:34:24.574866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30447 12:34:24.575436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30449 12:34:24.612114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30450 12:34:24.612543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30452 12:34:24.654854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30454 12:34:24.655356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30455 12:34:24.697308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30457 12:34:24.697761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30458 12:34:24.742761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30460 12:34:24.743240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30461 12:34:24.782779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30462 12:34:24.783174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30464 12:34:24.818748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30466 12:34:24.819184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30467 12:34:24.857690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30469 12:34:24.858173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30470 12:34:24.898010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30471 12:34:24.898473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30473 12:34:24.936712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30475 12:34:24.937144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30476 12:34:24.978155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30477 12:34:24.978601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30479 12:34:25.028036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30480 12:34:25.028426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30482 12:34:25.072654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30484 12:34:25.073129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30485 12:34:25.125470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30487 12:34:25.125959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30488 12:34:25.169809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30489 12:34:25.170243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30491 12:34:25.220799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30492 12:34:25.221239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30494 12:34:25.273532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30495 12:34:25.273956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30497 12:34:25.321885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30498 12:34:25.322296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30500 12:34:25.361056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30501 12:34:25.361467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30503 12:34:25.401986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30504 12:34:25.402353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30506 12:34:25.441499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30507 12:34:25.441899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30509 12:34:25.481550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30510 12:34:25.482099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30512 12:34:25.526572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30514 12:34:25.527044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30515 12:34:25.566626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30516 12:34:25.567082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30518 12:34:25.608051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30520 12:34:25.608513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30521 12:34:25.646571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30522 12:34:25.646997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30524 12:34:25.686657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30525 12:34:25.687092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30527 12:34:25.726049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30529 12:34:25.726518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30530 12:34:25.769270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30531 12:34:25.769685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30533 12:34:25.814358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30534 12:34:25.814788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30536 12:34:25.861946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30537 12:34:25.862385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30539 12:34:25.910204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30540 12:34:25.910629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30542 12:34:25.966873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30543 12:34:25.967273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30545 12:34:26.024900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30546 12:34:26.025299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30548 12:34:26.082896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30550 12:34:26.083384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30551 12:34:26.131177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30553 12:34:26.131555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30554 12:34:26.173507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30555 12:34:26.173948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30557 12:34:26.217382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30559 12:34:26.217974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30560 12:34:26.264379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30561 12:34:26.264783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30563 12:34:26.309524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30564 12:34:26.310041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30566 12:34:26.352256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30567 12:34:26.352685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30569 12:34:26.408190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30570 12:34:26.408720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30572 12:34:26.445674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30573 12:34:26.446028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30575 12:34:26.502841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30576 12:34:26.503413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30578 12:34:26.561559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30579 12:34:26.562028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30581 12:34:26.604892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30582 12:34:26.605310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30584 12:34:26.655211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30586 12:34:26.655777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30587 12:34:26.705344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30588 12:34:26.705825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30590 12:34:26.753588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30591 12:34:26.754168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30593 12:34:26.804042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30594 12:34:26.804423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30596 12:34:26.841871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30598 12:34:26.842284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30599 12:34:26.879259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30601 12:34:26.879681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30602 12:34:26.924752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30603 12:34:26.925205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30605 12:34:26.964884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30606 12:34:26.965379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30608 12:34:27.004430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30610 12:34:27.005033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30611 12:34:27.044113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30612 12:34:27.044548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30614 12:34:27.086845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30615 12:34:27.087301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30617 12:34:27.128361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30618 12:34:27.128832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30620 12:34:27.168883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30622 12:34:27.169320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30623 12:34:27.205593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30624 12:34:27.206040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30626 12:34:27.257017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30627 12:34:27.257416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30629 12:34:27.314026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30630 12:34:27.314462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30632 12:34:27.350879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30633 12:34:27.351338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30635 12:34:27.401144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30637 12:34:27.401626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30638 12:34:27.449739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30639 12:34:27.450202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30641 12:34:27.487374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30643 12:34:27.487868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30644 12:34:27.522595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30645 12:34:27.523030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30647 12:34:27.560277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30648 12:34:27.560716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30650 12:34:27.598776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30652 12:34:27.599214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30653 12:34:27.635874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30655 12:34:27.636323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30656 12:34:27.678282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30658 12:34:27.678769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30659 12:34:27.724106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30660 12:34:27.724568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30662 12:34:27.762867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30663 12:34:27.763303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30665 12:34:27.805716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30667 12:34:27.806206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30668 12:34:27.851481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30670 12:34:27.851966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30671 12:34:27.899791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30672 12:34:27.900215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30674 12:34:27.949776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30675 12:34:27.950189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30677 12:34:27.984870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30678 12:34:27.985334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30680 12:34:28.027338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30682 12:34:28.027786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30683 12:34:28.072557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30684 12:34:28.072963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30686 12:34:28.112146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30688 12:34:28.112944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30689 12:34:28.148222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30691 12:34:28.148616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30692 12:34:28.185146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30694 12:34:28.185624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30695 12:34:28.232527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30696 12:34:28.232963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30698 12:34:28.275899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30699 12:34:28.276349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30701 12:34:28.310605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30703 12:34:28.311080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30704 12:34:28.351998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30705 12:34:28.352443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30707 12:34:28.389014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30708 12:34:28.389446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30710 12:34:28.428131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30711 12:34:28.428602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30713 12:34:28.468114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30715 12:34:28.468498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30716 12:34:28.513165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30717 12:34:28.513607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30719 12:34:28.553838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30721 12:34:28.554315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30722 12:34:28.594110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30724 12:34:28.594581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30725 12:34:28.632684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30727 12:34:28.633311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30728 12:34:28.674270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30730 12:34:28.674698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30731 12:34:28.713687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30732 12:34:28.714086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30734 12:34:28.765408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30735 12:34:28.765859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30737 12:34:28.816250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30738 12:34:28.816674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30740 12:34:28.859002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30741 12:34:28.859437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30743 12:34:28.898232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30744 12:34:28.898709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30746 12:34:28.938864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30748 12:34:28.939352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30749 12:34:28.981466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30750 12:34:28.981875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30752 12:34:29.020712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30754 12:34:29.021379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30755 12:34:29.059141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30757 12:34:29.059862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30758 12:34:29.098167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30760 12:34:29.098640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30761 12:34:29.141712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30762 12:34:29.142145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30764 12:34:29.179471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30766 12:34:29.179952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30767 12:34:29.217780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30768 12:34:29.218201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30770 12:34:29.263862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30771 12:34:29.264293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30773 12:34:29.302445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30774 12:34:29.302894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30776 12:34:29.340016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30777 12:34:29.340413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30779 12:34:29.381066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30780 12:34:29.381480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30782 12:34:29.417336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30783 12:34:29.417776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30785 12:34:29.453265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30786 12:34:29.453618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30788 12:34:29.489035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30789 12:34:29.489464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30791 12:34:29.525867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30792 12:34:29.526251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30794 12:34:29.565399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30796 12:34:29.566096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30797 12:34:29.604348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30799 12:34:29.604805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30800 12:34:29.638595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30801 12:34:29.639172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30803 12:34:29.678662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30804 12:34:29.679108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30806 12:34:29.720637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30807 12:34:29.721085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30809 12:34:29.759642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30811 12:34:29.760108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30812 12:34:29.804330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30813 12:34:29.804780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30815 12:34:29.843320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30817 12:34:29.844118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30818 12:34:29.885821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30819 12:34:29.886155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30821 12:34:29.930677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30823 12:34:29.931483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30824 12:34:29.966993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30825 12:34:29.967451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30827 12:34:30.013642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30828 12:34:30.014098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30830 12:34:30.073774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30831 12:34:30.074158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30833 12:34:30.121703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30834 12:34:30.122118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30836 12:34:30.157966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30837 12:34:30.158413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30839 12:34:30.197798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30841 12:34:30.198565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30842 12:34:30.237043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30844 12:34:30.237629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30845 12:34:30.275024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30846 12:34:30.275495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30848 12:34:30.314253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30849 12:34:30.314641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30851 12:34:30.358593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30852 12:34:30.359040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30854 12:34:30.411480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30856 12:34:30.412220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30857 12:34:30.464329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30858 12:34:30.464871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30860 12:34:30.514212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30861 12:34:30.514763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30863 12:34:30.555494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30865 12:34:30.556265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30866 12:34:30.597795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30868 12:34:30.598272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30869 12:34:30.639094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30871 12:34:30.639809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30872 12:34:30.687297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30874 12:34:30.687783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30875 12:34:30.733053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30876 12:34:30.733491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30878 12:34:30.777298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30880 12:34:30.777698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30881 12:34:30.817738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30882 12:34:30.818180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30884 12:34:30.873932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30885 12:34:30.874363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30887 12:34:30.922949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30888 12:34:30.923366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30890 12:34:30.973096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30891 12:34:30.973558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30893 12:34:31.011146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30895 12:34:31.011595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30896 12:34:31.052199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30897 12:34:31.052623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30899 12:34:31.097480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30901 12:34:31.097996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30902 12:34:31.141458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30903 12:34:31.141881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30905 12:34:31.184244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30906 12:34:31.184618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30908 12:34:31.230032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30909 12:34:31.230467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30911 12:34:31.285152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30912 12:34:31.285550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30914 12:34:31.328308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30915 12:34:31.328757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30917 12:34:31.373481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30918 12:34:31.374007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30920 12:34:31.417278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30921 12:34:31.417689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30923 12:34:31.470479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30925 12:34:31.470952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30926 12:34:31.529970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30927 12:34:31.530423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30929 12:34:31.574372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30930 12:34:31.574794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30932 12:34:31.626571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30933 12:34:31.627024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30935 12:34:31.670737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30936 12:34:31.671201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30938 12:34:31.711072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30939 12:34:31.711496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30941 12:34:31.754365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30943 12:34:31.754855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30944 12:34:31.798107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30945 12:34:31.798552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30947 12:34:31.854801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30948 12:34:31.855354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30950 12:34:31.892346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30952 12:34:31.892824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30953 12:34:31.930311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30954 12:34:31.930802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30956 12:34:31.975039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30958 12:34:31.975818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30959 12:34:32.014379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30961 12:34:32.014971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30962 12:34:32.052392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30963 12:34:32.052878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30965 12:34:32.092733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30967 12:34:32.093216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30968 12:34:32.131193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30970 12:34:32.131692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30971 12:34:32.178566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30972 12:34:32.178987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30974 12:34:32.221501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30975 12:34:32.221948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30977 12:34:32.266984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30979 12:34:32.267609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30980 12:34:32.310121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
30981 12:34:32.310502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
30983 12:34:32.359428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
30985 12:34:32.359926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
30986 12:34:32.424019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
30987 12:34:32.424421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
30989 12:34:32.462830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
30990 12:34:32.463254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
30992 12:34:32.502708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
30993 12:34:32.503118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
30995 12:34:32.546001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
30996 12:34:32.546412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
30998 12:34:32.597130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31000 12:34:32.597575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31001 12:34:32.637147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31003 12:34:32.637526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31004 12:34:32.676288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31005 12:34:32.676783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31007 12:34:32.714781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31009 12:34:32.715356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31010 12:34:32.758099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31011 12:34:32.758659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31013 12:34:32.799880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31014 12:34:32.800410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31016 12:34:32.843214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31018 12:34:32.843878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31019 12:34:32.886884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31020 12:34:32.887366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31022 12:34:32.932250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31023 12:34:32.932826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31025 12:34:32.973342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31026 12:34:32.973782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31028 12:34:33.021729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31029 12:34:33.022130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31031 12:34:33.066589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31033 12:34:33.067193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31034 12:34:33.107933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31035 12:34:33.108425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31037 12:34:33.146920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31038 12:34:33.147354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31040 12:34:33.186120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31041 12:34:33.186618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31043 12:34:33.240068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31044 12:34:33.240547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31046 12:34:33.291928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31048 12:34:33.292553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31049 12:34:33.342595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31050 12:34:33.343092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31052 12:34:33.396499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31053 12:34:33.396902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31055 12:34:33.446970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31056 12:34:33.447375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31058 12:34:33.492444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31059 12:34:33.492879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31061 12:34:33.529894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31062 12:34:33.530329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31064 12:34:33.568456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31066 12:34:33.568914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31067 12:34:33.611208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31069 12:34:33.611667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31070 12:34:33.652767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31071 12:34:33.653215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31073 12:34:33.693199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31074 12:34:33.693574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31076 12:34:33.736407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31077 12:34:33.736841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31079 12:34:33.790955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31080 12:34:33.791509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31082 12:34:33.831947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31083 12:34:33.832336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31085 12:34:33.870991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31086 12:34:33.871412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31088 12:34:33.909792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31089 12:34:33.910256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31091 12:34:33.945562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31093 12:34:33.946273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31094 12:34:33.980838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31095 12:34:33.981324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31097 12:34:34.017150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31098 12:34:34.017551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31100 12:34:34.062647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31101 12:34:34.063033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31103 12:34:34.098364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31105 12:34:34.099005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31106 12:34:34.134712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31108 12:34:34.135182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31109 12:34:34.173299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31110 12:34:34.173711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31112 12:34:34.212390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31114 12:34:34.212952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31115 12:34:34.263084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31117 12:34:34.263601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31118 12:34:34.322357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31119 12:34:34.322760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31121 12:34:34.366568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31123 12:34:34.367223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31124 12:34:34.413895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31126 12:34:34.414551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31127 12:34:34.452786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31129 12:34:34.453264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31130 12:34:34.500531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31132 12:34:34.500900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31133 12:34:34.540181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31134 12:34:34.540617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31136 12:34:34.590010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31137 12:34:34.590415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31139 12:34:34.650768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31141 12:34:34.651243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31142 12:34:34.696091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31143 12:34:34.696517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31145 12:34:34.735328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31147 12:34:34.735756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31148 12:34:34.780905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31150 12:34:34.781337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31151 12:34:34.832480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31152 12:34:34.832907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31154 12:34:34.872820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31155 12:34:34.873206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31157 12:34:34.913231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31158 12:34:34.913706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31160 12:34:34.955748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31161 12:34:34.956112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31163 12:34:35.009698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31164 12:34:35.010092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31166 12:34:35.066835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31168 12:34:35.067351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31169 12:34:35.118548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31170 12:34:35.118976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31172 12:34:35.153039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31173 12:34:35.153543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31175 12:34:35.185192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31176 12:34:35.185747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31178 12:34:35.217750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31179 12:34:35.218252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31181 12:34:35.251978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31183 12:34:35.252735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31184 12:34:35.284603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31185 12:34:35.285129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31187 12:34:35.317848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31189 12:34:35.318421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31190 12:34:35.352286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31191 12:34:35.352912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31193 12:34:35.386833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31195 12:34:35.387396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31196 12:34:35.420443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31197 12:34:35.420912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31199 12:34:35.457252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31201 12:34:35.458020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31202 12:34:35.493598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31203 12:34:35.494103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31205 12:34:35.529257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31206 12:34:35.529755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31208 12:34:35.563948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31209 12:34:35.564486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31211 12:34:35.599015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31212 12:34:35.599420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31214 12:34:35.634156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31215 12:34:35.634542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31217 12:34:35.679387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31219 12:34:35.679874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31220 12:34:35.733812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31221 12:34:35.734202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31223 12:34:35.778799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31224 12:34:35.779212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31226 12:34:35.819135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31228 12:34:35.819629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31229 12:34:35.866223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31230 12:34:35.866663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31232 12:34:35.905645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31233 12:34:35.906101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31235 12:34:35.943713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31236 12:34:35.944095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31238 12:34:35.980614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31240 12:34:35.981107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31241 12:34:36.016332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31243 12:34:36.016748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31244 12:34:36.055872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31246 12:34:36.056465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31247 12:34:36.089602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31248 12:34:36.090089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31250 12:34:36.126360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31252 12:34:36.127118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31253 12:34:36.164048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31255 12:34:36.164638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31256 12:34:36.204317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31257 12:34:36.204818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31259 12:34:36.253158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31261 12:34:36.253587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31262 12:34:36.288452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31264 12:34:36.289206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31265 12:34:36.339085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31267 12:34:36.339750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31268 12:34:36.386658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31270 12:34:36.387281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31271 12:34:36.427285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31273 12:34:36.427727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31274 12:34:36.460896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31275 12:34:36.461342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31277 12:34:36.496252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31279 12:34:36.497276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31280 12:34:36.532873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31282 12:34:36.533484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31283 12:34:36.571145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31285 12:34:36.571626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31286 12:34:36.616453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31287 12:34:36.617019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31289 12:34:36.653600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31291 12:34:36.654072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31292 12:34:36.696468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31293 12:34:36.696897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31295 12:34:36.736502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31296 12:34:36.736899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31298 12:34:36.774577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31299 12:34:36.774997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31301 12:34:36.815350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31303 12:34:36.815797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31304 12:34:36.862090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31305 12:34:36.862540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31307 12:34:36.898214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31309 12:34:36.898823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31310 12:34:36.935290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31312 12:34:36.936041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31313 12:34:36.982541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31314 12:34:36.983043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31316 12:34:37.016824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31317 12:34:37.017324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31319 12:34:37.058295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31320 12:34:37.058774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31322 12:34:37.092880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31323 12:34:37.093277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31325 12:34:37.135086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31326 12:34:37.135579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31328 12:34:37.172933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31330 12:34:37.173508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31331 12:34:37.213491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31332 12:34:37.214017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31334 12:34:37.256899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31335 12:34:37.257403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31337 12:34:37.291590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31338 12:34:37.292108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31340 12:34:37.330765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31341 12:34:37.331256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31343 12:34:37.369557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31344 12:34:37.370050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31346 12:34:37.405074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31347 12:34:37.405604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31349 12:34:37.438913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31351 12:34:37.439523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31352 12:34:37.472768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31353 12:34:37.473197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31355 12:34:37.536745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31356 12:34:37.537234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31358 12:34:37.582431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31359 12:34:37.582895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31361 12:34:37.618775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31362 12:34:37.619306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31364 12:34:37.651601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31365 12:34:37.652113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31367 12:34:37.684462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31369 12:34:37.684999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31370 12:34:37.722754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31371 12:34:37.723224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31373 12:34:37.773007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31374 12:34:37.773564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31376 12:34:37.810036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31377 12:34:37.810589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31379 12:34:37.849636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31380 12:34:37.850129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31382 12:34:37.899997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31383 12:34:37.900428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31385 12:34:37.936188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31386 12:34:37.936598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31388 12:34:37.969298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31389 12:34:37.969746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31391 12:34:38.002180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31392 12:34:38.002605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31394 12:34:38.042089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31395 12:34:38.042503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31397 12:34:38.083235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31398 12:34:38.083793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31400 12:34:38.115949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31401 12:34:38.116388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31403 12:34:38.150344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31404 12:34:38.150790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31406 12:34:38.183333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31408 12:34:38.184058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31409 12:34:38.227713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31411 12:34:38.228294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31412 12:34:38.261424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31414 12:34:38.262045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31415 12:34:38.295535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31417 12:34:38.295994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31418 12:34:38.330639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31419 12:34:38.331027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31421 12:34:38.364986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31422 12:34:38.365365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31424 12:34:38.402923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31425 12:34:38.403306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31427 12:34:38.437586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31429 12:34:38.437979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31430 12:34:38.472197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31431 12:34:38.472592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31433 12:34:38.507521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31435 12:34:38.507997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31436 12:34:38.552724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31438 12:34:38.553193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31439 12:34:38.586562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31440 12:34:38.587018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31442 12:34:38.620734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31443 12:34:38.621151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31445 12:34:38.653310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31446 12:34:38.653789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31448 12:34:38.685664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31449 12:34:38.686133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31451 12:34:38.721516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31452 12:34:38.722030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31454 12:34:38.758141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31455 12:34:38.758584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31457 12:34:38.793366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31458 12:34:38.793793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31460 12:34:38.830779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31461 12:34:38.831198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31463 12:34:38.864689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31464 12:34:38.865167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31466 12:34:38.899029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31468 12:34:38.899460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31469 12:34:38.931942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31470 12:34:38.932321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31472 12:34:38.966613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31473 12:34:38.967103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31475 12:34:39.000642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31476 12:34:39.001030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31478 12:34:39.033189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31479 12:34:39.033597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31481 12:34:39.078256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31483 12:34:39.078679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31484 12:34:39.122224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31485 12:34:39.122670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31487 12:34:39.160361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31489 12:34:39.160849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31490 12:34:39.195163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31492 12:34:39.195706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31493 12:34:39.241243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31494 12:34:39.241691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31496 12:34:39.274907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31498 12:34:39.275419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31499 12:34:39.306819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31500 12:34:39.307253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31502 12:34:39.340382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31503 12:34:39.340806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31505 12:34:39.375680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31506 12:34:39.376270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31508 12:34:39.412449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31509 12:34:39.412934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31511 12:34:39.447901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31512 12:34:39.448381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31514 12:34:39.481992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31515 12:34:39.482469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31517 12:34:39.513552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31518 12:34:39.513973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31520 12:34:39.545127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31522 12:34:39.545518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31523 12:34:39.578845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31525 12:34:39.579209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31526 12:34:39.612628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31528 12:34:39.613161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31529 12:34:39.646117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31531 12:34:39.646682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31532 12:34:39.679441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31534 12:34:39.680030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31535 12:34:39.722617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31536 12:34:39.723106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31538 12:34:39.766794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31539 12:34:39.767276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31541 12:34:39.809078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31543 12:34:39.809789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31544 12:34:39.842827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31545 12:34:39.843309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31547 12:34:39.877399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31549 12:34:39.878047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31550 12:34:39.912417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31552 12:34:39.912846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31553 12:34:39.947518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31555 12:34:39.947952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31556 12:34:39.987958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31558 12:34:39.988429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31559 12:34:40.025179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31561 12:34:40.025660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31562 12:34:40.062361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31563 12:34:40.062767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31565 12:34:40.096587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31566 12:34:40.096977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31568 12:34:40.149785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31570 12:34:40.150162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31571 12:34:40.195718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31572 12:34:40.196140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31574 12:34:40.231271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31576 12:34:40.231789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31577 12:34:40.266910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31579 12:34:40.267394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31580 12:34:40.301500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31582 12:34:40.301965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31583 12:34:40.336424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31584 12:34:40.336852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31586 12:34:40.378767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31587 12:34:40.379286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31589 12:34:40.418784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31590 12:34:40.419254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31592 12:34:40.454295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31593 12:34:40.454712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31595 12:34:40.495800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31596 12:34:40.496107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31598 12:34:40.537962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31599 12:34:40.538409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31601 12:34:40.572612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31602 12:34:40.573089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31604 12:34:40.606676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31605 12:34:40.607162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31607 12:34:40.649038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31608 12:34:40.649613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31610 12:34:40.685927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31611 12:34:40.686325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31613 12:34:40.729719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31614 12:34:40.730151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31616 12:34:40.763991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31617 12:34:40.764427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31619 12:34:40.797801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31620 12:34:40.798189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31622 12:34:40.833932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31623 12:34:40.834423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31625 12:34:40.874840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31626 12:34:40.875253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31628 12:34:40.912612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31629 12:34:40.913108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31631 12:34:40.953274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31633 12:34:40.954054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31634 12:34:41.002568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31636 12:34:41.003071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31637 12:34:41.044603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31639 12:34:41.044984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31640 12:34:41.080528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31641 12:34:41.080955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31643 12:34:41.115377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31645 12:34:41.115817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31646 12:34:41.156053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31647 12:34:41.156516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31649 12:34:41.189361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31650 12:34:41.189767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31652 12:34:41.222857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31653 12:34:41.223304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31655 12:34:41.255988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31656 12:34:41.256405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31658 12:34:41.288461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31659 12:34:41.288876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31661 12:34:41.322739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31662 12:34:41.323221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31664 12:34:41.357532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31665 12:34:41.358101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31667 12:34:41.394702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31668 12:34:41.395240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31670 12:34:41.438187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31671 12:34:41.438700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31673 12:34:41.482811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31674 12:34:41.483214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31676 12:34:41.516462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31677 12:34:41.516916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31679 12:34:41.554095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31681 12:34:41.554571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31682 12:34:41.589208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31684 12:34:41.589811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31685 12:34:41.621815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31686 12:34:41.622304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31688 12:34:41.655317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31690 12:34:41.655991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31691 12:34:41.688795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31692 12:34:41.689260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31694 12:34:41.721495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31695 12:34:41.721988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31697 12:34:41.754021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31699 12:34:41.754615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31700 12:34:41.787527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31702 12:34:41.788123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31703 12:34:41.821450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31705 12:34:41.822212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31706 12:34:41.857715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31708 12:34:41.858185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31709 12:34:41.892144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31710 12:34:41.892573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31712 12:34:41.927774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31714 12:34:41.928246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31715 12:34:41.961057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31717 12:34:41.961510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31718 12:34:41.996229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31719 12:34:41.996543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31721 12:34:42.031399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31723 12:34:42.031713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31724 12:34:42.071629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31725 12:34:42.071985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31727 12:34:42.105098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31729 12:34:42.105465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31730 12:34:42.138364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31731 12:34:42.138709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31733 12:34:42.171099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31735 12:34:42.171430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31736 12:34:42.204808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31737 12:34:42.205247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31739 12:34:42.240366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31740 12:34:42.240831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31742 12:34:42.272544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31744 12:34:42.273102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31745 12:34:42.305063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31746 12:34:42.305530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31748 12:34:42.341033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31750 12:34:42.341811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31751 12:34:42.376983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31752 12:34:42.377474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31754 12:34:42.415428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31756 12:34:42.416174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31757 12:34:42.457867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31758 12:34:42.458347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31760 12:34:42.499079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31761 12:34:42.499567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31763 12:34:42.532967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31765 12:34:42.533420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31766 12:34:42.566073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31768 12:34:42.566713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31769 12:34:42.599157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31771 12:34:42.599808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31772 12:34:42.648756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31774 12:34:42.649388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31775 12:34:42.681723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31776 12:34:42.682148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31778 12:34:42.716940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31779 12:34:42.717523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31781 12:34:42.760477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31782 12:34:42.760945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31784 12:34:42.809133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31785 12:34:42.809559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31787 12:34:42.854023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31788 12:34:42.854462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31790 12:34:42.888437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31791 12:34:42.888997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31793 12:34:42.923967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31794 12:34:42.924409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31796 12:34:42.957477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31797 12:34:42.957999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31799 12:34:42.993629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31800 12:34:42.994051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31802 12:34:43.028597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31803 12:34:43.029033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31805 12:34:43.066507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31807 12:34:43.066973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31808 12:34:43.102065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31809 12:34:43.102496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31811 12:34:43.138830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31812 12:34:43.139216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31814 12:34:43.178297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31816 12:34:43.179059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31817 12:34:43.212931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31818 12:34:43.213328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31820 12:34:43.249255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31821 12:34:43.249690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31823 12:34:43.285725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31825 12:34:43.286187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31826 12:34:43.321630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31828 12:34:43.322104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31829 12:34:43.361269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31830 12:34:43.361685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31832 12:34:43.396324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31833 12:34:43.396760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31835 12:34:43.432128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31836 12:34:43.432618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31838 12:34:43.467960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31839 12:34:43.468463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31841 12:34:43.501187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31843 12:34:43.501655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31844 12:34:43.534785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31845 12:34:43.535346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31847 12:34:43.568680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31848 12:34:43.569162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31850 12:34:43.602404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31851 12:34:43.602856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31853 12:34:43.637179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31854 12:34:43.637683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31856 12:34:43.672116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31858 12:34:43.672737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31859 12:34:43.708226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31860 12:34:43.708645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31862 12:34:43.745475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31864 12:34:43.745949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31865 12:34:43.779544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31867 12:34:43.780233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31868 12:34:43.813346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31869 12:34:43.813861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31871 12:34:43.847370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31873 12:34:43.848155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31874 12:34:43.889201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31875 12:34:43.889638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31877 12:34:43.924397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31879 12:34:43.924860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31880 12:34:43.958901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31881 12:34:43.959322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31883 12:34:43.994226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31884 12:34:43.994654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31886 12:34:44.028494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31888 12:34:44.028955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31889 12:34:44.065102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31891 12:34:44.065565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31892 12:34:44.100564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31893 12:34:44.101145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31895 12:34:44.134656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31897 12:34:44.135222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31898 12:34:44.168759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31899 12:34:44.169123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31901 12:34:44.202650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31902 12:34:44.203142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31904 12:34:44.235629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31905 12:34:44.236182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31907 12:34:44.269225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31908 12:34:44.269670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31910 12:34:44.303209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31912 12:34:44.303685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31913 12:34:44.336405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31914 12:34:44.336868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31916 12:34:44.370551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31918 12:34:44.371180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31919 12:34:44.404616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31920 12:34:44.405060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31922 12:34:44.438360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31923 12:34:44.438929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31925 12:34:44.474122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31927 12:34:44.474878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31928 12:34:44.509369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31930 12:34:44.510151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31931 12:34:44.544090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31932 12:34:44.544573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31934 12:34:44.577698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31935 12:34:44.578148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31937 12:34:44.613174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31939 12:34:44.613761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31940 12:34:44.648230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31941 12:34:44.648517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31943 12:34:44.684570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31944 12:34:44.684952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31946 12:34:44.721158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31947 12:34:44.721501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31949 12:34:44.757165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31951 12:34:44.757483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31952 12:34:44.799694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31954 12:34:44.800206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31955 12:34:44.844270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31956 12:34:44.844797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31958 12:34:44.877449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31959 12:34:44.877927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31961 12:34:44.924298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31963 12:34:44.924869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31964 12:34:44.956771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31965 12:34:44.957232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31967 12:34:44.989051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31969 12:34:44.989817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31970 12:34:45.022407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31972 12:34:45.022864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31973 12:34:45.054073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31974 12:34:45.054530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31976 12:34:45.086681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31978 12:34:45.087138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31979 12:34:45.120552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31980 12:34:45.120987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
31982 12:34:45.153718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
31984 12:34:45.154186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
31985 12:34:45.192689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
31987 12:34:45.193290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
31988 12:34:45.225248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
31989 12:34:45.225695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
31991 12:34:45.262180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
31992 12:34:45.262638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
31994 12:34:45.306781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
31995 12:34:45.307180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
31997 12:34:45.339989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
31998 12:34:45.340466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32000 12:34:45.372365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32001 12:34:45.372847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32003 12:34:45.405563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32004 12:34:45.406129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32006 12:34:45.440268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32007 12:34:45.440812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32009 12:34:45.477832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32011 12:34:45.478205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32012 12:34:45.527969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32013 12:34:45.528469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32015 12:34:45.562584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32016 12:34:45.563159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32018 12:34:45.597253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32019 12:34:45.597643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32021 12:34:45.632759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32022 12:34:45.633205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32024 12:34:45.666674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32025 12:34:45.667105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32027 12:34:45.702134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32028 12:34:45.702550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32030 12:34:45.736306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32031 12:34:45.736619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32033 12:34:45.770518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32035 12:34:45.771050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32036 12:34:45.804003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32037 12:34:45.804491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32039 12:34:45.837385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32040 12:34:45.837873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32042 12:34:45.872757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32044 12:34:45.873317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32045 12:34:45.908059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32046 12:34:45.908472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32048 12:34:45.944192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32050 12:34:45.944914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32051 12:34:45.988115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32052 12:34:45.988547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32054 12:34:46.026096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32056 12:34:46.026680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32057 12:34:46.061283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32059 12:34:46.061743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32060 12:34:46.094851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32062 12:34:46.095279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32063 12:34:46.128119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32065 12:34:46.128693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32066 12:34:46.161619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32068 12:34:46.162211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32069 12:34:46.194797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32070 12:34:46.195126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32072 12:34:46.227738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32073 12:34:46.228151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32075 12:34:46.260996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32077 12:34:46.261609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32078 12:34:46.293958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32080 12:34:46.294383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32081 12:34:46.328612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32083 12:34:46.329037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32084 12:34:46.360847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32085 12:34:46.361266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32087 12:34:46.395726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32089 12:34:46.396164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32090 12:34:46.429969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32091 12:34:46.430393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32093 12:34:46.462573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32095 12:34:46.463329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32096 12:34:46.494996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32098 12:34:46.495570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32099 12:34:46.526765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32101 12:34:46.527433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32102 12:34:46.558857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32103 12:34:46.559285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32105 12:34:46.591873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32106 12:34:46.592266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32108 12:34:46.626290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32109 12:34:46.626688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32111 12:34:46.659709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32112 12:34:46.660151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32114 12:34:46.693127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32115 12:34:46.693534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32117 12:34:46.726601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32118 12:34:46.727075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32120 12:34:46.760106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32121 12:34:46.760547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32123 12:34:46.794056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32125 12:34:46.794851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32126 12:34:46.826626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32127 12:34:46.827131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32129 12:34:46.859706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32130 12:34:46.860192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32132 12:34:46.891997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32133 12:34:46.892506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32135 12:34:46.925521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32136 12:34:46.925903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32138 12:34:46.958804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32139 12:34:46.959246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32141 12:34:46.991907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32142 12:34:46.992382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32144 12:34:47.024569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32146 12:34:47.025030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32147 12:34:47.056621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32148 12:34:47.057060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32150 12:34:47.089734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32152 12:34:47.090389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32153 12:34:47.122362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32155 12:34:47.123004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32156 12:34:47.154425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32157 12:34:47.154914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32159 12:34:47.187949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32160 12:34:47.188364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32162 12:34:47.222131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32163 12:34:47.222579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32165 12:34:47.257505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32167 12:34:47.257932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32168 12:34:47.292659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32169 12:34:47.293063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32171 12:34:47.326794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32173 12:34:47.327365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32174 12:34:47.360836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32175 12:34:47.361330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32177 12:34:47.395952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32178 12:34:47.396433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32180 12:34:47.434747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32182 12:34:47.435340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32183 12:34:47.466372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32184 12:34:47.466759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32186 12:34:47.499695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32187 12:34:47.500076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32189 12:34:47.531706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32190 12:34:47.532178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32192 12:34:47.563618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32193 12:34:47.564091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32195 12:34:47.597038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32197 12:34:47.597602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32198 12:34:47.629469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32199 12:34:47.629957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32201 12:34:47.662514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32202 12:34:47.662972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32204 12:34:47.697281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32206 12:34:47.697863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32207 12:34:47.747276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32209 12:34:47.747751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32210 12:34:47.781662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32212 12:34:47.782118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32213 12:34:47.818452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32215 12:34:47.818864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32216 12:34:47.859434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32218 12:34:47.860003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32219 12:34:47.910935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32221 12:34:47.911495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32222 12:34:47.944372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32224 12:34:47.944947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32225 12:34:47.976378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32226 12:34:47.976851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32228 12:34:48.024453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32230 12:34:48.025038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32231 12:34:48.058092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32232 12:34:48.058569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32234 12:34:48.092560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32236 12:34:48.093035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32237 12:34:48.128540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32239 12:34:48.129001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32240 12:34:48.164821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32242 12:34:48.165292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32243 12:34:48.198046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32244 12:34:48.198462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32246 12:34:48.230697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32247 12:34:48.231183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32249 12:34:48.263959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32250 12:34:48.264444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32252 12:34:48.309638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32253 12:34:48.310119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32255 12:34:48.344439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32256 12:34:48.344929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32258 12:34:48.381362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32259 12:34:48.381775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32261 12:34:48.417222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32263 12:34:48.417704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32264 12:34:48.452266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32265 12:34:48.452706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32267 12:34:48.486925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32269 12:34:48.487678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32270 12:34:48.518961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32271 12:34:48.519431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32273 12:34:48.554262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32275 12:34:48.555021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32276 12:34:48.586804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32278 12:34:48.587419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32279 12:34:48.620413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32280 12:34:48.620817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32282 12:34:48.653544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32283 12:34:48.653889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32285 12:34:48.686220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32286 12:34:48.686563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32288 12:34:48.718398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32289 12:34:48.718871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32291 12:34:48.750776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32292 12:34:48.751318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32294 12:34:48.783178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32296 12:34:48.783625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32297 12:34:48.816917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32299 12:34:48.817331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32300 12:34:48.852445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32301 12:34:48.852835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32303 12:34:48.888915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32304 12:34:48.889353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32306 12:34:48.924523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32307 12:34:48.925066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32309 12:34:48.961667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32310 12:34:48.962107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32312 12:34:49.005475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32313 12:34:49.005900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32315 12:34:49.045138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32316 12:34:49.045449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32318 12:34:49.089903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32320 12:34:49.090360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32321 12:34:49.125606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32322 12:34:49.126002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32324 12:34:49.160043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32325 12:34:49.160506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32327 12:34:49.193770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32328 12:34:49.194257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32330 12:34:49.226878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32332 12:34:49.227364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32333 12:34:49.260260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32335 12:34:49.260836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32336 12:34:49.296383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32338 12:34:49.297161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32339 12:34:49.345210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32341 12:34:49.345811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32342 12:34:49.389897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32343 12:34:49.390252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32345 12:34:49.429320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32346 12:34:49.429695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32348 12:34:49.471103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32349 12:34:49.471552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32351 12:34:49.516299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32352 12:34:49.516684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32354 12:34:49.573200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32355 12:34:49.573555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32357 12:34:49.612422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32358 12:34:49.612693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32360 12:34:49.656199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32362 12:34:49.656661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32363 12:34:49.688694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32365 12:34:49.689281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32366 12:34:49.720812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32367 12:34:49.721300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32369 12:34:49.753261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32370 12:34:49.753799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32372 12:34:49.785715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32374 12:34:49.786177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32375 12:34:49.822307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32376 12:34:49.822725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32378 12:34:49.874623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32379 12:34:49.875121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32381 12:34:49.916975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32382 12:34:49.917536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32384 12:34:49.952455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32385 12:34:49.952998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32387 12:34:49.988429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32389 12:34:49.989230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32390 12:34:50.025065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32392 12:34:50.025592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32393 12:34:50.060679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32394 12:34:50.061061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32396 12:34:50.096334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32398 12:34:50.097017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32399 12:34:50.129042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32400 12:34:50.129545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32402 12:34:50.162384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32403 12:34:50.162850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32405 12:34:50.196268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32406 12:34:50.196818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32408 12:34:50.232466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32409 12:34:50.233019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32411 12:34:50.277543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32412 12:34:50.278000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32414 12:34:50.317560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32415 12:34:50.317966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32417 12:34:50.357212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32419 12:34:50.357870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32420 12:34:50.393483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32422 12:34:50.393992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32423 12:34:50.428863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32424 12:34:50.429249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32426 12:34:50.470028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32427 12:34:50.470441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32429 12:34:50.508643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32430 12:34:50.509071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32432 12:34:50.550708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32433 12:34:50.551087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32435 12:34:50.588177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32436 12:34:50.588557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32438 12:34:50.635383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32440 12:34:50.635869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32441 12:34:50.674126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32443 12:34:50.674550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32444 12:34:50.709628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32445 12:34:50.710010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32447 12:34:50.746531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32448 12:34:50.746928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32450 12:34:50.784811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32451 12:34:50.785254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32453 12:34:50.826615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32455 12:34:50.827156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32456 12:34:50.863296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32458 12:34:50.864142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32459 12:34:50.902778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32460 12:34:50.903247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32462 12:34:50.944811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32463 12:34:50.945226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32465 12:34:50.981472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32466 12:34:50.981864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32468 12:34:51.025377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32469 12:34:51.025875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32471 12:34:51.065710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32472 12:34:51.066181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32474 12:34:51.098820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32476 12:34:51.099471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32477 12:34:51.133506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32478 12:34:51.134018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32480 12:34:51.168519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32481 12:34:51.168956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32483 12:34:51.208043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32484 12:34:51.208519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32486 12:34:51.234505 <47>[ 404.324293] systemd-journald[109]: Sent WATCHDOG=1 notification.
32487 12:34:51.254639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32488 12:34:51.255066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32490 12:34:51.309312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32491 12:34:51.309811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32493 12:34:51.360606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32494 12:34:51.361076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32496 12:34:51.397402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32497 12:34:51.397901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32499 12:34:51.439585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32501 12:34:51.440243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32502 12:34:51.472554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32503 12:34:51.472948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32505 12:34:51.505499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32506 12:34:51.505990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32508 12:34:51.543749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32509 12:34:51.544216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32511 12:34:51.576945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32512 12:34:51.577414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32514 12:34:51.609836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32515 12:34:51.610270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32517 12:34:51.642198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32518 12:34:51.642670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32520 12:34:51.674343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32521 12:34:51.674810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32523 12:34:51.716304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32524 12:34:51.716779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32526 12:34:51.771134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32528 12:34:51.771569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32529 12:34:51.813114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32530 12:34:51.813496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32532 12:34:51.847373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32534 12:34:51.847989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32535 12:34:51.881487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32537 12:34:51.881965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32538 12:34:51.915450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32540 12:34:51.915965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32541 12:34:51.948830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32542 12:34:51.949267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32544 12:34:51.982736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32546 12:34:51.983379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32547 12:34:52.018727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32548 12:34:52.019123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32550 12:34:52.054577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32551 12:34:52.054922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32553 12:34:52.099572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32555 12:34:52.100174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32556 12:34:52.135287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32558 12:34:52.135693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32559 12:34:52.169731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32560 12:34:52.170160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32562 12:34:52.203847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32563 12:34:52.204235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32565 12:34:52.248054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32566 12:34:52.248456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32568 12:34:52.292839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32569 12:34:52.293285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32571 12:34:52.330543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32572 12:34:52.330953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32574 12:34:52.366419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32575 12:34:52.366838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32577 12:34:52.401779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32578 12:34:52.402219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32580 12:34:52.436921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32582 12:34:52.437379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32583 12:34:52.473208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32585 12:34:52.473677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32586 12:34:52.506740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32587 12:34:52.507164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32589 12:34:52.540793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32590 12:34:52.541251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32592 12:34:52.574970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32594 12:34:52.575467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32595 12:34:52.614361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32597 12:34:52.614824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32598 12:34:52.649897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32599 12:34:52.650275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32601 12:34:52.683300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32603 12:34:52.683810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32604 12:34:52.722976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32605 12:34:52.723473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32607 12:34:52.760367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32609 12:34:52.761019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32610 12:34:52.792821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32611 12:34:52.793317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32613 12:34:52.827571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32615 12:34:52.828217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32616 12:34:52.888986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32617 12:34:52.889416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32619 12:34:52.924449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32620 12:34:52.924888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32622 12:34:52.958664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32623 12:34:52.959103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32625 12:34:53.005563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32626 12:34:53.006014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32628 12:34:53.057773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32629 12:34:53.058181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32631 12:34:53.095924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32632 12:34:53.096315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32634 12:34:53.150709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32635 12:34:53.151107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32637 12:34:53.200159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32639 12:34:53.200638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32640 12:34:53.236743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32641 12:34:53.237215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32643 12:34:53.269961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32644 12:34:53.270393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32646 12:34:53.308806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32647 12:34:53.309380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32649 12:34:53.347510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32651 12:34:53.348263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32652 12:34:53.389185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32653 12:34:53.389630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32655 12:34:53.433043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32656 12:34:53.433562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32658 12:34:53.472168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32659 12:34:53.472595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32661 12:34:53.512371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32662 12:34:53.512770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32664 12:34:53.550941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32665 12:34:53.551328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32667 12:34:53.590125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32668 12:34:53.590615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32670 12:34:53.627405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32672 12:34:53.627886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32673 12:34:53.672907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32674 12:34:53.673342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32676 12:34:53.713031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32677 12:34:53.713400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32679 12:34:53.747339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32681 12:34:53.747749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32682 12:34:53.781547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32683 12:34:53.781963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32685 12:34:53.815414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32687 12:34:53.815832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32688 12:34:53.849841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32689 12:34:53.850269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32691 12:34:53.885721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32692 12:34:53.886142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32694 12:34:53.924223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32696 12:34:53.924695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32697 12:34:53.964771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32698 12:34:53.965281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32700 12:34:54.012114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32701 12:34:54.012594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32703 12:34:54.046824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32704 12:34:54.047343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32706 12:34:54.081851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32707 12:34:54.082255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32709 12:34:54.117404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32710 12:34:54.117869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32712 12:34:54.152260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32713 12:34:54.152662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32715 12:34:54.185518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32717 12:34:54.185949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32718 12:34:54.217602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32719 12:34:54.218079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32721 12:34:54.251491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32723 12:34:54.252102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32724 12:34:54.296305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32725 12:34:54.296728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32727 12:34:54.329563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32728 12:34:54.329988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32730 12:34:54.362982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32731 12:34:54.363413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32733 12:34:54.397340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32734 12:34:54.397759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32736 12:34:54.431254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32738 12:34:54.431658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32739 12:34:54.465612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32740 12:34:54.466018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32742 12:34:54.512572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32743 12:34:54.512960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32745 12:34:54.554327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32746 12:34:54.554753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32748 12:34:54.594060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32749 12:34:54.594467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32751 12:34:54.630762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32752 12:34:54.631089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32754 12:34:54.665671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32755 12:34:54.666012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32757 12:34:54.701128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32759 12:34:54.701817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32760 12:34:54.735432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32762 12:34:54.735968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32763 12:34:54.773024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32764 12:34:54.773386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32766 12:34:54.809031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32768 12:34:54.809613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32769 12:34:54.846872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32771 12:34:54.847252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32772 12:34:54.888080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32774 12:34:54.888382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32775 12:34:54.933223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32776 12:34:54.933704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32778 12:34:54.977397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32779 12:34:54.977855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32781 12:34:55.018648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32782 12:34:55.019074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32784 12:34:55.060658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32785 12:34:55.061017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32787 12:34:55.113083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32788 12:34:55.113434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32790 12:34:55.157187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32791 12:34:55.157593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32793 12:34:55.191948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32794 12:34:55.192338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32796 12:34:55.227371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32798 12:34:55.228110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32799 12:34:55.262347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32801 12:34:55.262813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32802 12:34:55.300456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32804 12:34:55.301041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32805 12:34:55.337868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32806 12:34:55.338350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32808 12:34:55.391262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32810 12:34:55.391666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32811 12:34:55.430006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32813 12:34:55.430609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32814 12:34:55.467879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32815 12:34:55.468359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32817 12:34:55.503795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32818 12:34:55.504223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32820 12:34:55.537090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32821 12:34:55.537509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32823 12:34:55.571878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32825 12:34:55.572333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32826 12:34:55.606015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32828 12:34:55.606403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32829 12:34:55.640722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32831 12:34:55.641182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32832 12:34:55.674735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32833 12:34:55.675163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32835 12:34:55.708700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32836 12:34:55.709089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32838 12:34:55.743399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32840 12:34:55.744145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32841 12:34:55.775727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32842 12:34:55.776106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32844 12:34:55.812199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32845 12:34:55.812650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32847 12:34:55.845551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32849 12:34:55.846127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32850 12:34:55.877518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32852 12:34:55.878100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32853 12:34:55.920749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32854 12:34:55.921187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32856 12:34:55.964163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32858 12:34:55.964538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32859 12:34:56.000269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32860 12:34:56.000690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32862 12:34:56.036561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32863 12:34:56.036966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32865 12:34:56.075801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32866 12:34:56.076232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32868 12:34:56.110548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32869 12:34:56.111058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32871 12:34:56.146336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32873 12:34:56.146719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32874 12:34:56.180129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32876 12:34:56.180554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32877 12:34:56.213369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32879 12:34:56.214028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32880 12:34:56.246025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32881 12:34:56.246440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32883 12:34:56.281883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32884 12:34:56.282508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32886 12:34:56.320674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32887 12:34:56.321202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32889 12:34:56.353359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32890 12:34:56.353914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32892 12:34:56.388015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32893 12:34:56.388576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32895 12:34:56.428050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32897 12:34:56.428434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32898 12:34:56.461753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32899 12:34:56.462297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32901 12:34:56.496620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32902 12:34:56.497086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32904 12:34:56.530261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32905 12:34:56.530737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32907 12:34:56.563653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32908 12:34:56.564139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32910 12:34:56.595904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32912 12:34:56.596298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32913 12:34:56.628409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32915 12:34:56.629059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32916 12:34:56.666743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32917 12:34:56.667287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32919 12:34:56.709358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32920 12:34:56.709952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32922 12:34:56.745146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32923 12:34:56.745614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32925 12:34:56.780639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32927 12:34:56.781102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32928 12:34:56.818888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32930 12:34:56.819410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32931 12:34:56.873026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32933 12:34:56.873643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32934 12:34:56.923649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32936 12:34:56.924334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32937 12:34:56.960779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32938 12:34:56.961065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32940 12:34:56.997581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32941 12:34:56.997869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32943 12:34:57.033512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32944 12:34:57.033901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32946 12:34:57.069449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32947 12:34:57.069843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32949 12:34:57.105682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32951 12:34:57.106127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32952 12:34:57.141941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32953 12:34:57.142317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32955 12:34:57.176783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32956 12:34:57.177226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32958 12:34:57.211866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32959 12:34:57.212290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32961 12:34:57.248577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32962 12:34:57.249028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32964 12:34:57.287124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32966 12:34:57.287765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32967 12:34:57.324365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32969 12:34:57.324972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32970 12:34:57.363185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32972 12:34:57.363559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32973 12:34:57.396573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32974 12:34:57.396958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32976 12:34:57.429010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32977 12:34:57.429473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32979 12:34:57.462699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32981 12:34:57.463201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
32982 12:34:57.506257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
32983 12:34:57.506681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
32985 12:34:57.542244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
32986 12:34:57.542660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
32988 12:34:57.595931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
32989 12:34:57.596387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
32991 12:34:57.641625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
32992 12:34:57.642052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
32994 12:34:57.687867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
32996 12:34:57.688383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
32997 12:34:57.723836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
32998 12:34:57.724279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33000 12:34:57.760241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33001 12:34:57.760669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33003 12:34:57.796586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33004 12:34:57.797009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33006 12:34:57.832082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33007 12:34:57.832592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33009 12:34:57.867193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33011 12:34:57.867875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33012 12:34:57.902867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33013 12:34:57.903323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33015 12:34:57.941373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33017 12:34:57.942034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33018 12:34:58.016681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33019 12:34:58.017152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33021 12:34:58.072531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33022 12:34:58.073040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33024 12:34:58.110018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33026 12:34:58.110785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33027 12:34:58.145610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33028 12:34:58.146191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33030 12:34:58.181565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33031 12:34:58.182025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33033 12:34:58.217404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33035 12:34:58.217966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33036 12:34:58.253579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33037 12:34:58.254046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33039 12:34:58.289448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33040 12:34:58.289918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33042 12:34:58.325590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33043 12:34:58.326040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33045 12:34:58.360583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33046 12:34:58.361032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33048 12:34:58.412242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33050 12:34:58.412731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33051 12:34:58.455762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33052 12:34:58.456167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33054 12:34:58.505462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33056 12:34:58.506219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33057 12:34:58.557879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33058 12:34:58.558342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33060 12:34:58.593061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33061 12:34:58.593511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33063 12:34:58.628208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33064 12:34:58.628656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33066 12:34:58.665675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33067 12:34:58.666085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33069 12:34:58.711970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33070 12:34:58.712417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33072 12:34:58.753602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33073 12:34:58.754055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33075 12:34:58.794349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33076 12:34:58.794801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33078 12:34:58.836068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33079 12:34:58.836573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33081 12:34:58.873099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33083 12:34:58.873581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33084 12:34:58.910106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33086 12:34:58.910578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33087 12:34:58.956996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33088 12:34:58.957390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33090 12:34:59.003725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33091 12:34:59.004165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33093 12:34:59.049698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33095 12:34:59.050162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33096 12:34:59.094910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33098 12:34:59.095393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33099 12:34:59.130058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33100 12:34:59.130488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33102 12:34:59.182764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33103 12:34:59.183155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33105 12:34:59.228105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33106 12:34:59.228535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33108 12:34:59.270714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33110 12:34:59.271350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33111 12:34:59.314490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33112 12:34:59.314888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33114 12:34:59.352220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33115 12:34:59.352604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33117 12:34:59.399909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33118 12:34:59.400379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33120 12:34:59.440878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33122 12:34:59.441338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33123 12:34:59.484919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33125 12:34:59.485350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33126 12:34:59.538091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33127 12:34:59.538496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33129 12:34:59.573636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33130 12:34:59.574035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33132 12:34:59.609480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33133 12:34:59.609798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33135 12:34:59.650793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33136 12:34:59.651175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33138 12:34:59.697521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33139 12:34:59.697943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33141 12:34:59.732071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33142 12:34:59.732494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33144 12:34:59.765767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33145 12:34:59.766192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33147 12:34:59.800264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33148 12:34:59.800643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33150 12:34:59.833539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33151 12:34:59.833965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33153 12:34:59.868454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33155 12:34:59.868854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33156 12:34:59.902600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33157 12:34:59.902997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33159 12:34:59.938528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33160 12:34:59.938886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33162 12:34:59.973815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33164 12:34:59.974368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33165 12:35:00.008475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33166 12:35:00.008871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33168 12:35:00.042318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33169 12:35:00.042737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33171 12:35:00.077317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33172 12:35:00.077733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33174 12:35:00.112277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33176 12:35:00.112890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33177 12:35:00.145470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33178 12:35:00.145920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33180 12:35:00.184078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33181 12:35:00.184538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33183 12:35:00.220627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33184 12:35:00.221078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33186 12:35:00.258662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33188 12:35:00.259353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33189 12:35:00.298609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33191 12:35:00.299134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33192 12:35:00.333066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33193 12:35:00.333551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33195 12:35:00.376795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33196 12:35:00.377215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33198 12:35:00.421624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33199 12:35:00.422187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33201 12:35:00.466701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33202 12:35:00.467115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33204 12:35:00.512404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33206 12:35:00.512846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33207 12:35:00.552658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33208 12:35:00.553060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33210 12:35:00.586414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33212 12:35:00.586876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33213 12:35:00.624658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33214 12:35:00.625111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33216 12:35:00.659703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33217 12:35:00.660130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33219 12:35:00.693810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33220 12:35:00.694237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33222 12:35:00.729800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33223 12:35:00.730244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33225 12:35:00.766091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33227 12:35:00.766561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33228 12:35:00.801208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33229 12:35:00.801662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33231 12:35:00.835474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33233 12:35:00.835937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33234 12:35:00.869343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33236 12:35:00.869932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33237 12:35:00.903357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33239 12:35:00.903843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33240 12:35:00.942967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33241 12:35:00.943430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33243 12:35:00.983381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33245 12:35:00.983872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33246 12:35:01.026252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33248 12:35:01.026718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33249 12:35:01.066103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33250 12:35:01.066504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33252 12:35:01.104243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33253 12:35:01.104688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33255 12:35:01.137376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33256 12:35:01.137821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33258 12:35:01.172208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33259 12:35:01.172571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33261 12:35:01.218576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33262 12:35:01.218997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33264 12:35:01.253033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33265 12:35:01.253450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33267 12:35:01.288086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33268 12:35:01.288508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33270 12:35:01.335036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33271 12:35:01.335468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33273 12:35:01.378679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33275 12:35:01.379438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33276 12:35:01.425171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33278 12:35:01.425666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33279 12:35:01.467457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33281 12:35:01.467910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33282 12:35:01.507758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33284 12:35:01.508226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33285 12:35:01.547988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33286 12:35:01.548449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33288 12:35:01.593264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33289 12:35:01.593821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33291 12:35:01.636330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33292 12:35:01.636765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33294 12:35:01.680776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33295 12:35:01.681238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33297 12:35:01.718720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33298 12:35:01.719152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33300 12:35:01.760702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33301 12:35:01.761134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33303 12:35:01.803412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33305 12:35:01.803874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33306 12:35:01.849803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33308 12:35:01.850227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33309 12:35:01.893821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33310 12:35:01.894324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33312 12:35:01.932269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33313 12:35:01.932658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33315 12:35:01.977728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33317 12:35:01.978443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33318 12:35:02.026900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33320 12:35:02.027478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33321 12:35:02.072537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33323 12:35:02.073027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33324 12:35:02.117791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33325 12:35:02.118243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33327 12:35:02.160680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33328 12:35:02.161061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33330 12:35:02.206213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33331 12:35:02.206641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33333 12:35:02.257547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33334 12:35:02.257993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33336 12:35:02.300053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33337 12:35:02.300493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33339 12:35:02.346950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33341 12:35:02.347433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33342 12:35:02.382929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33344 12:35:02.383411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33345 12:35:02.432715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33347 12:35:02.433425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33348 12:35:02.480466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33349 12:35:02.481013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33351 12:35:02.530895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33352 12:35:02.531316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33354 12:35:02.576688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33356 12:35:02.577077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33357 12:35:02.622415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33358 12:35:02.622859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33360 12:35:02.662095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33361 12:35:02.662492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33363 12:35:02.706115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33364 12:35:02.706508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33366 12:35:02.752345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33368 12:35:02.752994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33369 12:35:02.790670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33370 12:35:02.791046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33372 12:35:02.830885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33373 12:35:02.831337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33375 12:35:02.883523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33377 12:35:02.884239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33378 12:35:02.921574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33379 12:35:02.921984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33381 12:35:02.962400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33383 12:35:02.962811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33384 12:35:03.006212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33386 12:35:03.006773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33387 12:35:03.052336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33388 12:35:03.052749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33390 12:35:03.117466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33391 12:35:03.117902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33393 12:35:03.157467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33394 12:35:03.157891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33396 12:35:03.193192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33397 12:35:03.193642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33399 12:35:03.228235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33401 12:35:03.228741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33402 12:35:03.280678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33404 12:35:03.281112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33405 12:35:03.328277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33406 12:35:03.328678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33408 12:35:03.372374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33409 12:35:03.372771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33411 12:35:03.408192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33412 12:35:03.408616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33414 12:35:03.448372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33415 12:35:03.448777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33417 12:35:03.493963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33418 12:35:03.494352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33420 12:35:03.534726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33422 12:35:03.535204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33423 12:35:03.572761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33424 12:35:03.573156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33426 12:35:03.608591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33427 12:35:03.608999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33429 12:35:03.641493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33431 12:35:03.641978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33432 12:35:03.694757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33434 12:35:03.695241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33435 12:35:03.748865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33436 12:35:03.749244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33438 12:35:03.794731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33439 12:35:03.795224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33441 12:35:03.833723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33442 12:35:03.834129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33444 12:35:03.870123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33445 12:35:03.870561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33447 12:35:03.905829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33448 12:35:03.906250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33450 12:35:03.947210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33452 12:35:03.947794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33453 12:35:03.983146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33455 12:35:03.983801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33456 12:35:04.017386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33458 12:35:04.017832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33459 12:35:04.052580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33461 12:35:04.053062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33462 12:35:04.086719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33463 12:35:04.087131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33465 12:35:04.120634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33466 12:35:04.121089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33468 12:35:04.158397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33469 12:35:04.158819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33471 12:35:04.194537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33473 12:35:04.194892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33474 12:35:04.231990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33476 12:35:04.232437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33477 12:35:04.272676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33478 12:35:04.273105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33480 12:35:04.309371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33481 12:35:04.309773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33483 12:35:04.355050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33484 12:35:04.355483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33486 12:35:04.398303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33487 12:35:04.398700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33489 12:35:04.433732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33490 12:35:04.434230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33492 12:35:04.469389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33494 12:35:04.469993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33495 12:35:04.503491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33497 12:35:04.504070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33498 12:35:04.542891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33500 12:35:04.543311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33501 12:35:04.580883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33503 12:35:04.581543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33504 12:35:04.626132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33505 12:35:04.626666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33507 12:35:04.661124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33509 12:35:04.661890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33510 12:35:04.705139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33511 12:35:04.705687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33513 12:35:04.738862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33515 12:35:04.739349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33516 12:35:04.774755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33517 12:35:04.775203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33519 12:35:04.809496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33520 12:35:04.809944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33522 12:35:04.843278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33524 12:35:04.843962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33525 12:35:04.878272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33526 12:35:04.878839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33528 12:35:04.911826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33530 12:35:04.912285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33531 12:35:04.948237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33533 12:35:04.948895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33534 12:35:04.985953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33536 12:35:04.986396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33537 12:35:05.023373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33539 12:35:05.024131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33540 12:35:05.061435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33542 12:35:05.062041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33543 12:35:05.096681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33545 12:35:05.097101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33546 12:35:05.133786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33547 12:35:05.134148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33549 12:35:05.169363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33550 12:35:05.169925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33552 12:35:05.206110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33553 12:35:05.206599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33555 12:35:05.241666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33556 12:35:05.242138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33558 12:35:05.276718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33559 12:35:05.277180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33561 12:35:05.310656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33562 12:35:05.311234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33564 12:35:05.345795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33565 12:35:05.346187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33567 12:35:05.381123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33569 12:35:05.381508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33570 12:35:05.416805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33571 12:35:05.417191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33573 12:35:05.454616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33574 12:35:05.455033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33576 12:35:05.493817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33577 12:35:05.494217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33579 12:35:05.529183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33580 12:35:05.529575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33582 12:35:05.564106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33584 12:35:05.564533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33585 12:35:05.600890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33586 12:35:05.601414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33588 12:35:05.645037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33589 12:35:05.645461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33591 12:35:05.678405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33592 12:35:05.678911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33594 12:35:05.720179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33596 12:35:05.720846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33597 12:35:05.754247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33598 12:35:05.754734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33600 12:35:05.788870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33601 12:35:05.789296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33603 12:35:05.824407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33605 12:35:05.824991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33606 12:35:05.861117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33607 12:35:05.861564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33609 12:35:05.896305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33611 12:35:05.897066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33612 12:35:05.929815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33613 12:35:05.930311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33615 12:35:05.969230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33617 12:35:05.969832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33618 12:35:06.010435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33619 12:35:06.010976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33621 12:35:06.050174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33622 12:35:06.050589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33624 12:35:06.096006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33626 12:35:06.096458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33627 12:35:06.130833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33629 12:35:06.131314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33630 12:35:06.166361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33632 12:35:06.166980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33633 12:35:06.201755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33634 12:35:06.202217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33636 12:35:06.238177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33638 12:35:06.238692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33639 12:35:06.274786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33640 12:35:06.275337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33642 12:35:06.309599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33644 12:35:06.310369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33645 12:35:06.352868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33647 12:35:06.353522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33648 12:35:06.396661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33649 12:35:06.397209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33651 12:35:06.433431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33652 12:35:06.433999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33654 12:35:06.474546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33656 12:35:06.475160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33657 12:35:06.508740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33658 12:35:06.509180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33660 12:35:06.543057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33661 12:35:06.543486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33663 12:35:06.588077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33664 12:35:06.588562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33666 12:35:06.624558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33667 12:35:06.625110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33669 12:35:06.659392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33671 12:35:06.660143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33672 12:35:06.693327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33674 12:35:06.693920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33675 12:35:06.728228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33677 12:35:06.728990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33678 12:35:06.763030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33679 12:35:06.763591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33681 12:35:06.799995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33682 12:35:06.800527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33684 12:35:06.836869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33686 12:35:06.837486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33687 12:35:06.872450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33689 12:35:06.873118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33690 12:35:06.910987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33691 12:35:06.911416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33693 12:35:06.945879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33695 12:35:06.946652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33696 12:35:06.980815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33698 12:35:06.981278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33699 12:35:07.014700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33700 12:35:07.015187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33702 12:35:07.049902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33703 12:35:07.050382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33705 12:35:07.083698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33706 12:35:07.084176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33708 12:35:07.117357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33709 12:35:07.117799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33711 12:35:07.152132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33712 12:35:07.152571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33714 12:35:07.186444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33716 12:35:07.186913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33717 12:35:07.218333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33718 12:35:07.218738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33720 12:35:07.250458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33722 12:35:07.251103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33723 12:35:07.283325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33725 12:35:07.283960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33726 12:35:07.319859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33727 12:35:07.320339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33729 12:35:07.353818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33731 12:35:07.354421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33732 12:35:07.387890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33734 12:35:07.388455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33735 12:35:07.421821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33737 12:35:07.422390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33738 12:35:07.456460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33740 12:35:07.456924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33741 12:35:07.489781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33743 12:35:07.490345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33744 12:35:07.523538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33746 12:35:07.524009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33747 12:35:07.557515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33749 12:35:07.557990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33750 12:35:07.591112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33752 12:35:07.591592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33753 12:35:07.624344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33754 12:35:07.624764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33756 12:35:07.657294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33757 12:35:07.657691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33759 12:35:07.690498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33760 12:35:07.690981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33762 12:35:07.723240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33764 12:35:07.723829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33765 12:35:07.756849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33766 12:35:07.757293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33768 12:35:07.790002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33770 12:35:07.790602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33771 12:35:07.822551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33772 12:35:07.823020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33774 12:35:07.857367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33776 12:35:07.858208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33777 12:35:07.899967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33778 12:35:07.900448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33780 12:35:07.943776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33781 12:35:07.944287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33783 12:35:07.988667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33785 12:35:07.989315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33786 12:35:08.030131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33787 12:35:08.030538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33789 12:35:08.072043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33790 12:35:08.072522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33792 12:35:08.106791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33794 12:35:08.107654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33795 12:35:08.140664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33796 12:35:08.141084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33798 12:35:08.174470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33799 12:35:08.174909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33801 12:35:08.220509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33802 12:35:08.220984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33804 12:35:08.257107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33805 12:35:08.257505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33807 12:35:08.291092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33809 12:35:08.291738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33810 12:35:08.324437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33811 12:35:08.324912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33813 12:35:08.357410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33814 12:35:08.357811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33816 12:35:08.390903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33818 12:35:08.391320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33819 12:35:08.424694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33820 12:35:08.425191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33822 12:35:08.458620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33823 12:35:08.459120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33825 12:35:08.492274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33826 12:35:08.492705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33828 12:35:08.525266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33829 12:35:08.525682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33831 12:35:08.557948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33833 12:35:08.558513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33834 12:35:08.589731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33835 12:35:08.590188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33837 12:35:08.622865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33838 12:35:08.623312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33840 12:35:08.656144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33842 12:35:08.656710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33843 12:35:08.688857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33845 12:35:08.689326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33846 12:35:08.722858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33847 12:35:08.723286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33849 12:35:08.756745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33850 12:35:08.757165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33852 12:35:08.791992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33853 12:35:08.792370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33855 12:35:08.824519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33856 12:35:08.824913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33858 12:35:08.856579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33860 12:35:08.857177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33861 12:35:08.888894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33863 12:35:08.889461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33864 12:35:08.920393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33866 12:35:08.920949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33867 12:35:08.952544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33868 12:35:08.952976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33870 12:35:08.984827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33872 12:35:08.985425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33873 12:35:09.016578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33874 12:35:09.016985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33876 12:35:09.048378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33877 12:35:09.048783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33879 12:35:09.080226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33881 12:35:09.080674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33882 12:35:09.112334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33884 12:35:09.112951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33885 12:35:09.144356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33886 12:35:09.144816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33888 12:35:09.176423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33890 12:35:09.177047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33891 12:35:09.208055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33893 12:35:09.208641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33894 12:35:09.242590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33895 12:35:09.243067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33897 12:35:09.275672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33898 12:35:09.276163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33900 12:35:09.308698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33902 12:35:09.309293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33903 12:35:09.342043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33905 12:35:09.342517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33906 12:35:09.376187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33907 12:35:09.376629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33909 12:35:09.410550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33911 12:35:09.411155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33912 12:35:09.444472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33913 12:35:09.444891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33915 12:35:09.479895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33917 12:35:09.480264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33918 12:35:09.514123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33920 12:35:09.514716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33921 12:35:09.549283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33922 12:35:09.549773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33924 12:35:09.583632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33925 12:35:09.584128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33927 12:35:09.626945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33928 12:35:09.627448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33930 12:35:09.663509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33932 12:35:09.663982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33933 12:35:09.701075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33934 12:35:09.701515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33936 12:35:09.738804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33937 12:35:09.739287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33939 12:35:09.773454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33940 12:35:09.773929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33942 12:35:09.814117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33943 12:35:09.814552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33945 12:35:09.859115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33946 12:35:09.859662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33948 12:35:09.900209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33950 12:35:09.900794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33951 12:35:09.937325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33953 12:35:09.937992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33954 12:35:09.975195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33955 12:35:09.975745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33957 12:35:10.013015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33958 12:35:10.013404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33960 12:35:10.050884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33961 12:35:10.051274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33963 12:35:10.091069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33965 12:35:10.091798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33966 12:35:10.127530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33968 12:35:10.128232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33969 12:35:10.161559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33970 12:35:10.161998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33972 12:35:10.197164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33973 12:35:10.197625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33975 12:35:10.232425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33976 12:35:10.232898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33978 12:35:10.267634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33979 12:35:10.268170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33981 12:35:10.302445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33982 12:35:10.302918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33984 12:35:10.348208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
33986 12:35:10.348675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33987 12:35:10.388467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33988 12:35:10.388870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33990 12:35:10.426805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33991 12:35:10.427237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33993 12:35:10.462750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33994 12:35:10.463265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
33996 12:35:10.515067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33997 12:35:10.515492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33999 12:35:10.559269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34001 12:35:10.559906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34002 12:35:10.594457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34003 12:35:10.594912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34005 12:35:10.628218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34006 12:35:10.628667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34008 12:35:10.673062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34009 12:35:10.673378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34011 12:35:10.719364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34013 12:35:10.719866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34014 12:35:10.756183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34015 12:35:10.756587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34017 12:35:10.792496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34018 12:35:10.792852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34020 12:35:10.827739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34021 12:35:10.828063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34023 12:35:10.880332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34024 12:35:10.880657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34026 12:35:10.913275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34028 12:35:10.913902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34029 12:35:10.946928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34030 12:35:10.947417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34032 12:35:10.993363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34033 12:35:10.993835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34035 12:35:11.030058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34036 12:35:11.030553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34038 12:35:11.069178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34040 12:35:11.069842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34041 12:35:11.111897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34043 12:35:11.112342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34044 12:35:11.152899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34045 12:35:11.153321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34047 12:35:11.189959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34048 12:35:11.190419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34050 12:35:11.232234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34051 12:35:11.232775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34053 12:35:11.268846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34054 12:35:11.269407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34056 12:35:11.308639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34057 12:35:11.309063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34059 12:35:11.353587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34061 12:35:11.354212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34062 12:35:11.389010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34063 12:35:11.389457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34065 12:35:11.428937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34066 12:35:11.429368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34068 12:35:11.465406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34070 12:35:11.465883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34071 12:35:11.501416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34072 12:35:11.501919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34074 12:35:11.537275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34076 12:35:11.538059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34077 12:35:11.576460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34078 12:35:11.576901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34080 12:35:11.625697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34081 12:35:11.626164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34083 12:35:11.660485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34085 12:35:11.660901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34086 12:35:11.694715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34088 12:35:11.695382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34089 12:35:11.732486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34090 12:35:11.732981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34092 12:35:11.780352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34093 12:35:11.780840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34095 12:35:11.830221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34097 12:35:11.830676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34098 12:35:11.864281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34099 12:35:11.864698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34101 12:35:11.897048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34103 12:35:11.897505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34104 12:35:11.929711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34106 12:35:11.930166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34107 12:35:11.962567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34108 12:35:11.962992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34110 12:35:11.995140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34111 12:35:11.995566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34113 12:35:12.029081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34114 12:35:12.029579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34116 12:35:12.062265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34118 12:35:12.062733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34119 12:35:12.095392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34121 12:35:12.095860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34122 12:35:12.128220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34123 12:35:12.128700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34125 12:35:12.161056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34127 12:35:12.161521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34128 12:35:12.194848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34130 12:35:12.195336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34131 12:35:12.227458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34133 12:35:12.227916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34134 12:35:12.261417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34136 12:35:12.262087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34137 12:35:12.294016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34138 12:35:12.294430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34140 12:35:12.326433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34141 12:35:12.327001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34143 12:35:12.360575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34145 12:35:12.361364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34146 12:35:12.395222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34148 12:35:12.395699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34149 12:35:12.430228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34150 12:35:12.430664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34152 12:35:12.464539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34154 12:35:12.465002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34155 12:35:12.497573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34156 12:35:12.497986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34158 12:35:12.530113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34160 12:35:12.530534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34161 12:35:12.568241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34162 12:35:12.568662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34164 12:35:12.602041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34166 12:35:12.602496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34167 12:35:12.634894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34168 12:35:12.635321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34170 12:35:12.667156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34172 12:35:12.667602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34173 12:35:12.700070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34175 12:35:12.700524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34176 12:35:12.732628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34178 12:35:12.733089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34179 12:35:12.765524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34181 12:35:12.766176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34182 12:35:12.798522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34183 12:35:12.798994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34185 12:35:12.831741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34187 12:35:12.832207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34188 12:35:12.864423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34189 12:35:12.864837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34191 12:35:12.897023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34193 12:35:12.897592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34194 12:35:12.930085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34195 12:35:12.930572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34197 12:35:12.963546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34199 12:35:12.964277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34200 12:35:12.997022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34202 12:35:12.997490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34203 12:35:13.030672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34204 12:35:13.031121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34206 12:35:13.064453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34207 12:35:13.064898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34209 12:35:13.098597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34210 12:35:13.099021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34212 12:35:13.132234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34213 12:35:13.132654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34215 12:35:13.166112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34217 12:35:13.166563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34218 12:35:13.199859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34219 12:35:13.200234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34221 12:35:13.243099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34222 12:35:13.243477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34224 12:35:13.284108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34225 12:35:13.284558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34227 12:35:13.345577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34228 12:35:13.345963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34230 12:35:13.391040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34231 12:35:13.391437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34233 12:35:13.425091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34234 12:35:13.425563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34236 12:35:13.470930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34238 12:35:13.471737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34239 12:35:13.508159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34240 12:35:13.508619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34242 12:35:13.550091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34244 12:35:13.550569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34245 12:35:13.588511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34246 12:35:13.588943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34248 12:35:13.625275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34250 12:35:13.625760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34251 12:35:13.660175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34252 12:35:13.660628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34254 12:35:13.695913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34255 12:35:13.696389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34257 12:35:13.729457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34258 12:35:13.729850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34260 12:35:13.763402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34262 12:35:13.763823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34263 12:35:13.797955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34265 12:35:13.798391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34266 12:35:13.831857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34267 12:35:13.832216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34269 12:35:13.868938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34270 12:35:13.869363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34272 12:35:13.909884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34274 12:35:13.910306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34275 12:35:13.950005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34276 12:35:13.950438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34278 12:35:13.985600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34280 12:35:13.986046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34281 12:35:14.019508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34283 12:35:14.020012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34284 12:35:14.060154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34285 12:35:14.060593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34287 12:35:14.094797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34288 12:35:14.095271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34290 12:35:14.128552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34292 12:35:14.129026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34293 12:35:14.162246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34294 12:35:14.162715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34296 12:35:14.196567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34297 12:35:14.196976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34299 12:35:14.230797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34301 12:35:14.231276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34302 12:35:14.265119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34303 12:35:14.265563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34305 12:35:14.300070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34306 12:35:14.300558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34308 12:35:14.334150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34309 12:35:14.334716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34311 12:35:14.367773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34312 12:35:14.368261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34314 12:35:14.401953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34316 12:35:14.402691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34317 12:35:14.445088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34318 12:35:14.445560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34320 12:35:14.479708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34321 12:35:14.480129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34323 12:35:14.517214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34324 12:35:14.517589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34326 12:35:14.552171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34327 12:35:14.552560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34329 12:35:14.585483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34331 12:35:14.586311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34332 12:35:14.620325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34333 12:35:14.620834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34335 12:35:14.655888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34337 12:35:14.656223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34338 12:35:14.690914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34339 12:35:14.691359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34341 12:35:14.726061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34343 12:35:14.726568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34344 12:35:14.760611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34345 12:35:14.761094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34347 12:35:14.796177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34348 12:35:14.796576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34350 12:35:14.842883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34351 12:35:14.843347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34353 12:35:14.882073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34354 12:35:14.882470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34356 12:35:14.916902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34358 12:35:14.917375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34359 12:35:14.951042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34360 12:35:14.951472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34362 12:35:14.985607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34363 12:35:14.986038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34365 12:35:15.026817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34366 12:35:15.027247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34368 12:35:15.061388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34369 12:35:15.061813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34371 12:35:15.094579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34373 12:35:15.095190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34374 12:35:15.129673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34376 12:35:15.130262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34377 12:35:15.163931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34378 12:35:15.164422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34380 12:35:15.197058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34381 12:35:15.197543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34383 12:35:15.230549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34385 12:35:15.231161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34386 12:35:15.264200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34388 12:35:15.264769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34389 12:35:15.297456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34390 12:35:15.297937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34392 12:35:15.330666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34393 12:35:15.331147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34395 12:35:15.366837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34397 12:35:15.367321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34398 12:35:15.402028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34399 12:35:15.402456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34401 12:35:15.451846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34402 12:35:15.452267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34404 12:35:15.482874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34405 12:35:15.483261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34407 12:35:15.516025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34408 12:35:15.516397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34410 12:35:15.549909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34411 12:35:15.550304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34413 12:35:15.583670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34414 12:35:15.584013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34416 12:35:15.616596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34417 12:35:15.617015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34419 12:35:15.651684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34420 12:35:15.652103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34422 12:35:15.688770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34423 12:35:15.689190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34425 12:35:15.722328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34426 12:35:15.722735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34428 12:35:15.756193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34429 12:35:15.756612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34431 12:35:15.789537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34432 12:35:15.789921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34434 12:35:15.827764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34435 12:35:15.828186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34437 12:35:15.861157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34438 12:35:15.861576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34440 12:35:15.896247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34441 12:35:15.896664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34443 12:35:15.929619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34444 12:35:15.930010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34446 12:35:15.964265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34448 12:35:15.964731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34449 12:35:16.000648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34450 12:35:16.001032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34452 12:35:16.043842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34454 12:35:16.044309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34455 12:35:16.082064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34456 12:35:16.082461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34458 12:35:16.121507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34459 12:35:16.121940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34461 12:35:16.156732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34462 12:35:16.157151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34464 12:35:16.192315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34465 12:35:16.192736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34467 12:35:16.226030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34468 12:35:16.226471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34470 12:35:16.259998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34471 12:35:16.260424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34473 12:35:16.296670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34475 12:35:16.297132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34476 12:35:16.332611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34477 12:35:16.333117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34479 12:35:16.365948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34480 12:35:16.366415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34482 12:35:16.400342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34483 12:35:16.400810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34485 12:35:16.435436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34487 12:35:16.435849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34488 12:35:16.475845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34489 12:35:16.476189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34491 12:35:16.508017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34492 12:35:16.508491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34494 12:35:16.541217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34495 12:35:16.541698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34497 12:35:16.574597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34498 12:35:16.575013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34500 12:35:16.613066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34501 12:35:16.613538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34503 12:35:16.646058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34504 12:35:16.646544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34506 12:35:16.678481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34507 12:35:16.678877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34509 12:35:16.714175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34511 12:35:16.714757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34512 12:35:16.748094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34513 12:35:16.748518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34515 12:35:16.784850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34516 12:35:16.785272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34518 12:35:16.822191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34519 12:35:16.822761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34521 12:35:16.858780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34522 12:35:16.859210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34524 12:35:16.893200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34525 12:35:16.893604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34527 12:35:16.930088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34528 12:35:16.930531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34530 12:35:16.963414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34532 12:35:16.963896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34533 12:35:16.997854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34534 12:35:16.998270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34536 12:35:17.034579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34537 12:35:17.035020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34539 12:35:17.068085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34540 12:35:17.068584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34542 12:35:17.100827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34544 12:35:17.101272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34545 12:35:17.133436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34546 12:35:17.133881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34548 12:35:17.166063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34549 12:35:17.166545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34551 12:35:17.200469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34553 12:35:17.201050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34554 12:35:17.233202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34556 12:35:17.233792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34557 12:35:17.266042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34558 12:35:17.266498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34560 12:35:17.299383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34562 12:35:17.299949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34563 12:35:17.332678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34565 12:35:17.333138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34566 12:35:17.370068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34568 12:35:17.370557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34569 12:35:17.414280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34571 12:35:17.414769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34572 12:35:17.449479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34574 12:35:17.450115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34575 12:35:17.482800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34577 12:35:17.483579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34578 12:35:17.516164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34580 12:35:17.516632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34581 12:35:17.550123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34582 12:35:17.550553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34584 12:35:17.583619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34585 12:35:17.584042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34587 12:35:17.621148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34588 12:35:17.621569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34590 12:35:17.664247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34591 12:35:17.664693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34593 12:35:17.699279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34595 12:35:17.699713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34596 12:35:17.702162 + set +x
34597 12:35:17.702482 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 568971_1.1.3.5>
34598 12:35:17.702746 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 568971_1.1.3.5
34599 12:35:17.702829 Ending use of test pattern.
34600 12:35:17.702898 Ending test lava.1_kselftest-arm64_qemu (568971_1.1.3.5), duration 405.61
34602 12:35:17.706703 ok: lava_test_shell seems to have completed
34603 12:35:17.797341 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34604 12:35:17.802661 end: 3.1 lava-test-shell (duration 00:06:47) [common]
34605 12:35:17.803001 end: 3 lava-test-retry (duration 00:06:47) [common]
34606 12:35:17.803236 start: 4 finalize (timeout 00:01:59) [common]
34607 12:35:17.803430 start: 4.1 power-off (timeout 00:00:30) [common]
34608 12:35:17.803598 end: 4.1 power-off (duration 00:00:00) [common]
34609 12:35:17.803760 start: 4.2 read-feedback (timeout 00:01:59) [common]
34611 12:35:17.804437 Listened to connection for namespace 'common' for up to 1s
34612 12:35:18.805751 Finalising connection for namespace 'common'
34614 12:35:18.906723 / # poweroff
34615 12:35:18.907425 Already disconnected
34616 12:35:18.907663 poweroff
34617 12:35:19.309811 end: 4.2 read-feedback (duration 00:00:02) [common]
34618 12:35:19.310023 Already disconnected
34619 12:35:19.310116 end: 4 finalize (duration 00:00:02) [common]
34620 12:35:19.310252 Cleaning after the job
34621 12:35:19.310410 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/568971/deployimages-ngcjgsyl/kernel
34622 12:35:19.316486 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/568971/deployimages-ngcjgsyl/ramdisk
34623 12:35:19.327733 Stopping the qemu container lava-docker-qemu-568971-2.1.1-uyxkyom7uy
34624 12:35:20.207837 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/568971
34625 12:35:20.291210 Job finished correctly