Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 12:25:22.226630 lava-dispatcher, installed at version: 2023.05.1
2 12:25:22.226856 start: 0 validate
3 12:25:22.227062 Start time: 2023-06-06 12:25:22.227055+00:00 (UTC)
4 12:25:22.227193 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:25:22.227321 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:25:22.509266 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:25:22.509454 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:25:55.314884 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:25:55.315845 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:25:55.614322 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:25:55.615041 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:25:58.910352 validate duration: 36.68
14 12:25:58.911531 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:25:58.912039 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:25:58.912516 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:25:59.901076 Not decompressing ramdisk as can be used compressed.
18 12:25:59.901748 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 12:25:59.902236 saving as /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/ramdisk/rootfs.cpio.gz
20 12:25:59.902640 total size: 8186575 (7MB)
21 12:26:00.231540 progress 0% (0MB)
22 12:26:00.234338 progress 5% (0MB)
23 12:26:00.236615 progress 10% (0MB)
24 12:26:00.239094 progress 15% (1MB)
25 12:26:00.241269 progress 20% (1MB)
26 12:26:00.243875 progress 25% (1MB)
27 12:26:00.246116 progress 30% (2MB)
28 12:26:00.248458 progress 35% (2MB)
29 12:26:00.250758 progress 40% (3MB)
30 12:26:00.253237 progress 45% (3MB)
31 12:26:00.255566 progress 50% (3MB)
32 12:26:00.258070 progress 55% (4MB)
33 12:26:00.260384 progress 60% (4MB)
34 12:26:00.262888 progress 65% (5MB)
35 12:26:00.265140 progress 70% (5MB)
36 12:26:00.267818 progress 75% (5MB)
37 12:26:00.270323 progress 80% (6MB)
38 12:26:00.273178 progress 85% (6MB)
39 12:26:00.275603 progress 90% (7MB)
40 12:26:00.278153 progress 95% (7MB)
41 12:26:00.280456 progress 100% (7MB)
42 12:26:00.280731 7MB downloaded in 0.38s (20.65MB/s)
43 12:26:00.280886 end: 1.1.1 http-download (duration 00:00:01) [common]
45 12:26:00.281164 end: 1.1 download-retry (duration 00:00:01) [common]
46 12:26:00.281253 start: 1.2 download-retry (timeout 00:09:59) [common]
47 12:26:00.281341 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 12:26:00.281476 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:26:00.281581 saving as /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/kernel/Image
50 12:26:00.281644 total size: 45746688 (43MB)
51 12:26:00.281722 No compression specified
52 12:26:00.283140 progress 0% (0MB)
53 12:26:00.295823 progress 5% (2MB)
54 12:26:00.307596 progress 10% (4MB)
55 12:26:00.319423 progress 15% (6MB)
56 12:26:00.331324 progress 20% (8MB)
57 12:26:00.343138 progress 25% (10MB)
58 12:26:00.354985 progress 30% (13MB)
59 12:26:00.367187 progress 35% (15MB)
60 12:26:00.378932 progress 40% (17MB)
61 12:26:00.390745 progress 45% (19MB)
62 12:26:00.402706 progress 50% (21MB)
63 12:26:00.414285 progress 55% (24MB)
64 12:26:00.425960 progress 60% (26MB)
65 12:26:00.437607 progress 65% (28MB)
66 12:26:00.449233 progress 70% (30MB)
67 12:26:00.460870 progress 75% (32MB)
68 12:26:00.472376 progress 80% (34MB)
69 12:26:00.484034 progress 85% (37MB)
70 12:26:00.495627 progress 90% (39MB)
71 12:26:00.507181 progress 95% (41MB)
72 12:26:00.518699 progress 100% (43MB)
73 12:26:00.518866 43MB downloaded in 0.24s (183.91MB/s)
74 12:26:00.519026 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:26:00.519272 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:26:00.519377 start: 1.3 download-retry (timeout 00:09:58) [common]
78 12:26:00.519475 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 12:26:00.519619 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:26:00.519694 saving as /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/dtb/mt8192-asurada-spherion-r0.dtb
81 12:26:00.519759 total size: 46924 (0MB)
82 12:26:00.519822 No compression specified
83 12:26:00.520960 progress 69% (0MB)
84 12:26:00.521241 progress 100% (0MB)
85 12:26:00.521400 0MB downloaded in 0.00s (27.31MB/s)
86 12:26:00.521530 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:26:00.521766 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:26:00.521855 start: 1.4 download-retry (timeout 00:09:58) [common]
90 12:26:00.521943 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 12:26:00.522065 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:26:00.522138 saving as /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/modules/modules.tar
93 12:26:00.522202 total size: 8539116 (8MB)
94 12:26:00.522266 Using unxz to decompress xz
95 12:26:00.525767 progress 0% (0MB)
96 12:26:00.548539 progress 5% (0MB)
97 12:26:00.576559 progress 10% (0MB)
98 12:26:00.601297 progress 15% (1MB)
99 12:26:00.630496 progress 20% (1MB)
100 12:26:00.656669 progress 25% (2MB)
101 12:26:00.683894 progress 30% (2MB)
102 12:26:00.711381 progress 35% (2MB)
103 12:26:00.738112 progress 40% (3MB)
104 12:26:00.764717 progress 45% (3MB)
105 12:26:00.793073 progress 50% (4MB)
106 12:26:00.819586 progress 55% (4MB)
107 12:26:00.846643 progress 60% (4MB)
108 12:26:00.874143 progress 65% (5MB)
109 12:26:00.901348 progress 70% (5MB)
110 12:26:00.932276 progress 75% (6MB)
111 12:26:00.963294 progress 80% (6MB)
112 12:26:00.987292 progress 85% (6MB)
113 12:26:01.012689 progress 90% (7MB)
114 12:26:01.039058 progress 95% (7MB)
115 12:26:01.064863 progress 100% (8MB)
116 12:26:01.070919 8MB downloaded in 0.55s (14.84MB/s)
117 12:26:01.071271 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:26:01.071594 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:26:01.071698 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:26:01.071801 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:26:01.071889 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:26:01.071993 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:26:01.072232 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_
125 12:26:01.072373 makedir: /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin
126 12:26:01.072495 makedir: /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/tests
127 12:26:01.072603 makedir: /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/results
128 12:26:01.072726 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-add-keys
129 12:26:01.072899 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-add-sources
130 12:26:01.073076 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-background-process-start
131 12:26:01.073221 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-background-process-stop
132 12:26:01.073353 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-common-functions
133 12:26:01.073480 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-echo-ipv4
134 12:26:01.073613 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-install-packages
135 12:26:01.073743 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-installed-packages
136 12:26:01.073868 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-os-build
137 12:26:01.073992 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-probe-channel
138 12:26:01.074125 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-probe-ip
139 12:26:01.074250 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-target-ip
140 12:26:01.074373 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-target-mac
141 12:26:01.074497 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-target-storage
142 12:26:01.074635 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-case
143 12:26:01.074760 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-event
144 12:26:01.074884 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-feedback
145 12:26:01.075011 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-raise
146 12:26:01.075144 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-reference
147 12:26:01.075271 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-runner
148 12:26:01.075424 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-set
149 12:26:01.075559 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-test-shell
150 12:26:01.075694 Updating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-install-packages (oe)
151 12:26:01.081157 Updating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/bin/lava-installed-packages (oe)
152 12:26:01.081324 Creating /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/environment
153 12:26:01.081441 LAVA metadata
154 12:26:01.081522 - LAVA_JOB_ID=10605768
155 12:26:01.081592 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:26:01.081724 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 12:26:01.081805 skipped lava-vland-overlay
158 12:26:01.081888 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:26:01.081976 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 12:26:01.082042 skipped lava-multinode-overlay
161 12:26:01.082123 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:26:01.082217 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 12:26:01.082315 Loading test definitions
164 12:26:01.082415 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:58) [common]
165 12:26:01.082494 Using /lava-10605768 at stage 0
166 12:26:01.082845 uuid=10605768_1.5.2.3.1 testdef=None
167 12:26:01.082941 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:26:01.083033 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
169 12:26:01.083647 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:26:01.083892 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
172 12:26:01.084558 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:26:01.084812 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
175 12:26:01.085443 runner path: /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/0/tests/0_dmesg test_uuid 10605768_1.5.2.3.1
176 12:26:01.085604 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:26:01.085851 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:58) [common]
179 12:26:01.085927 Using /lava-10605768 at stage 1
180 12:26:01.086251 uuid=10605768_1.5.2.3.5 testdef=None
181 12:26:01.086345 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:26:01.086439 start: 1.5.2.3.6 test-overlay (timeout 00:09:58) [common]
183 12:26:01.086931 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:26:01.087225 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:58) [common]
186 12:26:01.088467 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 12:26:01.088789 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:58) [common]
189 12:26:01.090670 runner path: /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/1/tests/1_bootrr test_uuid 10605768_1.5.2.3.5
190 12:26:01.090886 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:26:01.091237 Creating lava-test-runner.conf files
193 12:26:01.091360 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/0 for stage 0
194 12:26:01.091491 - 0_dmesg
195 12:26:01.091615 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605768/lava-overlay-ryio3tp_/lava-10605768/1 for stage 1
196 12:26:01.091737 - 1_bootrr
197 12:26:01.091882 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 12:26:01.092014 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
199 12:26:01.100755 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:26:01.100913 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
201 12:26:01.101034 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:26:01.101144 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 12:26:01.101259 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
204 12:26:01.374583 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:26:01.374978 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
206 12:26:01.375141 extracting modules file /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605768/extract-overlay-ramdisk-r211v7uf/ramdisk
207 12:26:01.626481 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:26:01.626703 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
209 12:26:01.626839 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605768/compress-overlay-enuf5_ra/overlay-1.5.2.4.tar.gz to ramdisk
210 12:26:01.626923 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605768/compress-overlay-enuf5_ra/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605768/extract-overlay-ramdisk-r211v7uf/ramdisk
211 12:26:01.635750 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:26:01.635921 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
213 12:26:01.636030 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:26:01.636124 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
215 12:26:01.636211 Building ramdisk /var/lib/lava/dispatcher/tmp/10605768/extract-overlay-ramdisk-r211v7uf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605768/extract-overlay-ramdisk-r211v7uf/ramdisk
216 12:26:02.340438 >> 143719 blocks
217 12:26:04.869353 rename /var/lib/lava/dispatcher/tmp/10605768/extract-overlay-ramdisk-r211v7uf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/ramdisk/ramdisk.cpio.gz
218 12:26:04.869900 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:26:04.870089 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
220 12:26:04.870240 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
221 12:26:04.870409 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/kernel/Image'
222 12:26:19.536567 Returned 0 in 14 seconds
223 12:26:19.637187 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/kernel/image.itb
224 12:26:20.446801 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:26:20.447195 output: Created: Tue Jun 6 13:26:20 2023
226 12:26:20.447318 output: Image 0 (kernel-1)
227 12:26:20.447423 output: Description:
228 12:26:20.447544 output: Created: Tue Jun 6 13:26:20 2023
229 12:26:20.447622 output: Type: Kernel Image
230 12:26:20.447693 output: Compression: lzma compressed
231 12:26:20.447761 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
232 12:26:20.447826 output: Architecture: AArch64
233 12:26:20.447886 output: OS: Linux
234 12:26:20.447946 output: Load Address: 0x00000000
235 12:26:20.448011 output: Entry Point: 0x00000000
236 12:26:20.448073 output: Hash algo: crc32
237 12:26:20.448130 output: Hash value: a26c3f91
238 12:26:20.448186 output: Image 1 (fdt-1)
239 12:26:20.448249 output: Description: mt8192-asurada-spherion-r0
240 12:26:20.448313 output: Created: Tue Jun 6 13:26:20 2023
241 12:26:20.448372 output: Type: Flat Device Tree
242 12:26:20.448437 output: Compression: uncompressed
243 12:26:20.448503 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 12:26:20.448588 output: Architecture: AArch64
245 12:26:20.448674 output: Hash algo: crc32
246 12:26:20.448761 output: Hash value: 1df858fa
247 12:26:20.448850 output: Image 2 (ramdisk-1)
248 12:26:20.448935 output: Description: unavailable
249 12:26:20.449023 output: Created: Tue Jun 6 13:26:20 2023
250 12:26:20.449108 output: Type: RAMDisk Image
251 12:26:20.449205 output: Compression: Unknown Compression
252 12:26:20.449290 output: Data Size: 21220870 Bytes = 20723.51 KiB = 20.24 MiB
253 12:26:20.449379 output: Architecture: AArch64
254 12:26:20.449464 output: OS: Linux
255 12:26:20.449554 output: Load Address: unavailable
256 12:26:20.449638 output: Entry Point: unavailable
257 12:26:20.449723 output: Hash algo: crc32
258 12:26:20.449807 output: Hash value: 671f678c
259 12:26:20.449900 output: Default Configuration: 'conf-1'
260 12:26:20.449985 output: Configuration 0 (conf-1)
261 12:26:20.450069 output: Description: mt8192-asurada-spherion-r0
262 12:26:20.450160 output: Kernel: kernel-1
263 12:26:20.450246 output: Init Ramdisk: ramdisk-1
264 12:26:20.450340 output: FDT: fdt-1
265 12:26:20.450428 output: Loadables: kernel-1
266 12:26:20.450513 output:
267 12:26:20.450756 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
268 12:26:20.450887 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
269 12:26:20.451031 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
270 12:26:20.451168 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
271 12:26:20.451284 No LXC device requested
272 12:26:20.451407 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:26:20.451536 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
274 12:26:20.451675 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:26:20.451792 Checking files for TFTP limit of 4294967296 bytes.
276 12:26:20.452552 end: 1 tftp-deploy (duration 00:00:22) [common]
277 12:26:20.452716 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:26:20.452827 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:26:20.452970 substitutions:
280 12:26:20.453047 - {DTB}: 10605768/tftp-deploy-w2z48eio/dtb/mt8192-asurada-spherion-r0.dtb
281 12:26:20.453146 - {INITRD}: 10605768/tftp-deploy-w2z48eio/ramdisk/ramdisk.cpio.gz
282 12:26:20.453214 - {KERNEL}: 10605768/tftp-deploy-w2z48eio/kernel/Image
283 12:26:20.453276 - {LAVA_MAC}: None
284 12:26:20.453344 - {PRESEED_CONFIG}: None
285 12:26:20.453403 - {PRESEED_LOCAL}: None
286 12:26:20.453461 - {RAMDISK}: 10605768/tftp-deploy-w2z48eio/ramdisk/ramdisk.cpio.gz
287 12:26:20.453524 - {ROOT_PART}: None
288 12:26:20.453582 - {ROOT}: None
289 12:26:20.453639 - {SERVER_IP}: 192.168.201.1
290 12:26:20.453695 - {TEE}: None
291 12:26:20.453753 Parsed boot commands:
292 12:26:20.453828 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:26:20.454016 Parsed boot commands: tftpboot 192.168.201.1 10605768/tftp-deploy-w2z48eio/kernel/image.itb 10605768/tftp-deploy-w2z48eio/kernel/cmdline
294 12:26:20.454111 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:26:20.454200 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:26:20.454306 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:26:20.454413 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:26:20.454488 Not connected, no need to disconnect.
299 12:26:20.454574 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:26:20.454683 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:26:20.454793 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
302 12:26:20.458879 Setting prompt string to ['lava-test: # ']
303 12:26:20.459641 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:26:20.459763 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:26:20.459878 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:26:20.459974 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:26:20.460183 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
308 12:26:25.593675 >> Command sent successfully.
309 12:26:25.596391 Returned 0 in 5 seconds
310 12:26:25.696827 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:26:25.697173 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:26:25.697286 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:26:25.697401 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:26:25.697507 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:26:25.697627 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:26:25.698044 [Enter `^Ec?' for help]
318 12:26:25.871697
319 12:26:25.871862
320 12:26:25.871940 F0: 102B 0000
321 12:26:25.872008
322 12:26:25.872071 F3: 1001 0000 [0200]
323 12:26:25.875370
324 12:26:25.875464 F3: 1001 0000
325 12:26:25.875535
326 12:26:25.875603 F7: 102D 0000
327 12:26:25.875669
328 12:26:25.878480 F1: 0000 0000
329 12:26:25.878557
330 12:26:25.878621 V0: 0000 0000 [0001]
331 12:26:25.878683
332 12:26:25.881606 00: 0007 8000
333 12:26:25.881703
334 12:26:25.881773 01: 0000 0000
335 12:26:25.881841
336 12:26:25.884760 BP: 0C00 0209 [0000]
337 12:26:25.884851
338 12:26:25.884923 G0: 1182 0000
339 12:26:25.884990
340 12:26:25.889152 EC: 0000 0021 [4000]
341 12:26:25.889276
342 12:26:25.889382 S7: 0000 0000 [0000]
343 12:26:25.889478
344 12:26:25.892271 CC: 0000 0000 [0001]
345 12:26:25.892385
346 12:26:25.892492 T0: 0000 0040 [010F]
347 12:26:25.892593
348 12:26:25.892706 Jump to BL
349 12:26:25.892822
350 12:26:25.918798
351 12:26:25.919004
352 12:26:25.919116
353 12:26:25.926262 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:26:25.930034 ARM64: Exception handlers installed.
355 12:26:25.933555 ARM64: Testing exception
356 12:26:25.936702 ARM64: Done test exception
357 12:26:25.943531 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:26:25.953397 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:26:25.960233 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:26:25.970132 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:26:25.977173 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:26:25.983214 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:26:25.995738 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:26:26.002568 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:26:26.031523 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:26:26.031754 WDT: Last reset was cold boot
367 12:26:26.031897 SPI1(PAD0) initialized at 2873684 Hz
368 12:26:26.032215 SPI5(PAD0) initialized at 992727 Hz
369 12:26:26.035211 VBOOT: Loading verstage.
370 12:26:26.041977 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:26:26.045127 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:26:26.048286 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:26:26.051464 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:26:26.059500 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:26:26.065632 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:26:26.077040 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 12:26:26.077194
378 12:26:26.077276
379 12:26:26.086890 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:26:26.089786 ARM64: Exception handlers installed.
381 12:26:26.093547 ARM64: Testing exception
382 12:26:26.093669 ARM64: Done test exception
383 12:26:26.100262 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:26:26.103286 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:26:26.119050 Probing TPM: . done!
386 12:26:26.119236 TPM ready after 0 ms
387 12:26:26.126401 Connected to device vid:did:rid of 1ae0:0028:00
388 12:26:26.133560 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 12:26:26.190683 Initialized TPM device CR50 revision 0
390 12:26:26.203185 tlcl_send_startup: Startup return code is 0
391 12:26:26.203381 TPM: setup succeeded
392 12:26:26.214367 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:26:26.223079 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:26:26.235370 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:26:26.245555 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:26:26.249231 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:26:26.252925 in-header: 03 07 00 00 08 00 00 00
398 12:26:26.256783 in-data: aa e4 47 04 13 02 00 00
399 12:26:26.259845 Chrome EC: UHEPI supported
400 12:26:26.267272 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:26:26.270951 in-header: 03 ad 00 00 08 00 00 00
402 12:26:26.271110 in-data: 00 20 20 08 00 00 00 00
403 12:26:26.274111 Phase 1
404 12:26:26.278555 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:26:26.282188 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:26:26.289653 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:26:26.292573 Recovery requested (1009000e)
408 12:26:26.301410 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:26:26.307579 tlcl_extend: response is 0
410 12:26:26.317497 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:26:26.323665 tlcl_extend: response is 0
412 12:26:26.330393 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:26:26.350390 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 12:26:26.356844 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:26:26.357042
416 12:26:26.357160
417 12:26:26.367470 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:26:26.371212 ARM64: Exception handlers installed.
419 12:26:26.371408 ARM64: Testing exception
420 12:26:26.374827 ARM64: Done test exception
421 12:26:26.396122 pmic_efuse_setting: Set efuses in 11 msecs
422 12:26:26.399194 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:26:26.406080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:26:26.409323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:26:26.416062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:26:26.419244 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:26:26.422937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:26:26.430482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:26:26.434179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:26:26.437665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:26:26.445073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:26:26.448811 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:26:26.452420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:26:26.456482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:26:26.463679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:26:26.467254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:26:26.474522 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:26:26.478007 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:26:26.485101 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:26:26.492739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:26:26.496321 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:26:26.504208 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:26:26.508008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:26:26.514981 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:26:26.519272 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:26:26.522345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:26:26.529920 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:26:26.536978 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:26:26.540678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:26:26.544474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:26:26.548229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:26:26.555291 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:26:26.559577 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:26:26.563092 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:26:26.570295 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:26:26.573885 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:26:26.581767 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:26:26.585365 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:26:26.588959 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:26:26.596547 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:26:26.600358 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:26:26.603963 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:26:26.607690 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:26:26.611380 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:26:26.618892 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:26:26.622855 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:26:26.626541 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:26:26.630322 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:26:26.634053 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:26:26.637254 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:26:26.640955 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:26:26.644781 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:26:26.652277 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:26:26.659866 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:26:26.667118 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:26:26.670562 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:26:26.681946 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:26:26.688654 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:26:26.692500 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:26:26.696419 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:26:26.703053 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:26:26.710525 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
483 12:26:26.714209 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:26:26.717766 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
485 12:26:26.721558 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:26:26.732673 [RTC]rtc_get_frequency_meter,154: input=15, output=790
487 12:26:26.742538 [RTC]rtc_get_frequency_meter,154: input=23, output=979
488 12:26:26.752137 [RTC]rtc_get_frequency_meter,154: input=19, output=885
489 12:26:26.761517 [RTC]rtc_get_frequency_meter,154: input=17, output=837
490 12:26:26.771028 [RTC]rtc_get_frequency_meter,154: input=16, output=813
491 12:26:26.781115 [RTC]rtc_get_frequency_meter,154: input=15, output=789
492 12:26:26.790785 [RTC]rtc_get_frequency_meter,154: input=16, output=813
493 12:26:26.793646 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
494 12:26:26.801458 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
495 12:26:26.804640 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 12:26:26.808455 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 12:26:26.811857 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 12:26:26.815384 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 12:26:26.819145 ADC[4]: Raw value=902066 ID=7
500 12:26:26.823237 ADC[3]: Raw value=213336 ID=1
501 12:26:26.823389 RAM Code: 0x71
502 12:26:26.826462 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 12:26:26.834038 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 12:26:26.841008 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 12:26:26.848459 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 12:26:26.852219 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 12:26:26.855982 in-header: 03 07 00 00 08 00 00 00
508 12:26:26.859837 in-data: aa e4 47 04 13 02 00 00
509 12:26:26.859961 Chrome EC: UHEPI supported
510 12:26:26.866722 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 12:26:26.870440 in-header: 03 ed 00 00 08 00 00 00
512 12:26:26.874071 in-data: 80 20 60 08 00 00 00 00
513 12:26:26.877825 MRC: failed to locate region type 0.
514 12:26:26.885218 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 12:26:26.888839 DRAM-K: Running full calibration
516 12:26:26.892877 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 12:26:26.896631 header.status = 0x0
518 12:26:26.900292 header.version = 0x6 (expected: 0x6)
519 12:26:26.903244 header.size = 0xd00 (expected: 0xd00)
520 12:26:26.903398 header.flags = 0x0
521 12:26:26.910506 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 12:26:26.928515 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 12:26:26.935335 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 12:26:26.939144 dram_init: ddr_geometry: 2
525 12:26:26.939293 [EMI] MDL number = 2
526 12:26:26.942891 [EMI] Get MDL freq = 0
527 12:26:26.943031 dram_init: ddr_type: 0
528 12:26:26.946528 is_discrete_lpddr4: 1
529 12:26:26.950318 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 12:26:26.950494
531 12:26:26.950601
532 12:26:26.950740 [Bian_co] ETT version 0.0.0.1
533 12:26:26.957287 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 12:26:26.957470
535 12:26:26.961194 dramc_set_vcore_voltage set vcore to 650000
536 12:26:26.961329 Read voltage for 800, 4
537 12:26:26.964430 Vio18 = 0
538 12:26:26.964552 Vcore = 650000
539 12:26:26.964651 Vdram = 0
540 12:26:26.967613 Vddq = 0
541 12:26:26.967709 Vmddr = 0
542 12:26:26.970766 dram_init: config_dvfs: 1
543 12:26:26.974622 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 12:26:26.980910 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 12:26:26.984481 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
546 12:26:26.987589 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
547 12:26:26.991154 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
548 12:26:26.994448 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
549 12:26:26.997648 MEM_TYPE=3, freq_sel=18
550 12:26:27.001048 sv_algorithm_assistance_LP4_1600
551 12:26:27.004017 ============ PULL DRAM RESETB DOWN ============
552 12:26:27.007747 ========== PULL DRAM RESETB DOWN end =========
553 12:26:27.014214 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 12:26:27.017371 ===================================
555 12:26:27.020910 LPDDR4 DRAM CONFIGURATION
556 12:26:27.021068 ===================================
557 12:26:27.024642 EX_ROW_EN[0] = 0x0
558 12:26:27.027620 EX_ROW_EN[1] = 0x0
559 12:26:27.027765 LP4Y_EN = 0x0
560 12:26:27.031231 WORK_FSP = 0x0
561 12:26:27.031377 WL = 0x2
562 12:26:27.034356 RL = 0x2
563 12:26:27.034465 BL = 0x2
564 12:26:27.037378 RPST = 0x0
565 12:26:27.037594 RD_PRE = 0x0
566 12:26:27.041196 WR_PRE = 0x1
567 12:26:27.041436 WR_PST = 0x0
568 12:26:27.044130 DBI_WR = 0x0
569 12:26:27.044342 DBI_RD = 0x0
570 12:26:27.047751 OTF = 0x1
571 12:26:27.050894 ===================================
572 12:26:27.054592 ===================================
573 12:26:27.054755 ANA top config
574 12:26:27.057753 ===================================
575 12:26:27.060836 DLL_ASYNC_EN = 0
576 12:26:27.064671 ALL_SLAVE_EN = 1
577 12:26:27.067859 NEW_RANK_MODE = 1
578 12:26:27.067976 DLL_IDLE_MODE = 1
579 12:26:27.070894 LP45_APHY_COMB_EN = 1
580 12:26:27.074562 TX_ODT_DIS = 1
581 12:26:27.077756 NEW_8X_MODE = 1
582 12:26:27.080918 ===================================
583 12:26:27.084619 ===================================
584 12:26:27.087882 data_rate = 1600
585 12:26:27.088027 CKR = 1
586 12:26:27.091042 DQ_P2S_RATIO = 8
587 12:26:27.094201 ===================================
588 12:26:27.097892 CA_P2S_RATIO = 8
589 12:26:27.100856 DQ_CA_OPEN = 0
590 12:26:27.104133 DQ_SEMI_OPEN = 0
591 12:26:27.107480 CA_SEMI_OPEN = 0
592 12:26:27.107653 CA_FULL_RATE = 0
593 12:26:27.110833 DQ_CKDIV4_EN = 1
594 12:26:27.114329 CA_CKDIV4_EN = 1
595 12:26:27.117429 CA_PREDIV_EN = 0
596 12:26:27.121021 PH8_DLY = 0
597 12:26:27.121151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 12:26:27.124687 DQ_AAMCK_DIV = 4
599 12:26:27.127613 CA_AAMCK_DIV = 4
600 12:26:27.130680 CA_ADMCK_DIV = 4
601 12:26:27.134296 DQ_TRACK_CA_EN = 0
602 12:26:27.137932 CA_PICK = 800
603 12:26:27.140900 CA_MCKIO = 800
604 12:26:27.140999 MCKIO_SEMI = 0
605 12:26:27.144640 PLL_FREQ = 3068
606 12:26:27.148441 DQ_UI_PI_RATIO = 32
607 12:26:27.152207 CA_UI_PI_RATIO = 0
608 12:26:27.155886 ===================================
609 12:26:27.156042 ===================================
610 12:26:27.159851 memory_type:LPDDR4
611 12:26:27.163542 GP_NUM : 10
612 12:26:27.163688 SRAM_EN : 1
613 12:26:27.167260 MD32_EN : 0
614 12:26:27.171021 ===================================
615 12:26:27.171163 [ANA_INIT] >>>>>>>>>>>>>>
616 12:26:27.174859 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 12:26:27.178597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 12:26:27.181704 ===================================
619 12:26:27.184931 data_rate = 1600,PCW = 0X7600
620 12:26:27.188706 ===================================
621 12:26:27.191821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 12:26:27.194951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 12:26:27.201826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 12:26:27.205277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 12:26:27.208371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 12:26:27.212010 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 12:26:27.214885 [ANA_INIT] flow start
628 12:26:27.218446 [ANA_INIT] PLL >>>>>>>>
629 12:26:27.218586 [ANA_INIT] PLL <<<<<<<<
630 12:26:27.221982 [ANA_INIT] MIDPI >>>>>>>>
631 12:26:27.224944 [ANA_INIT] MIDPI <<<<<<<<
632 12:26:27.225085 [ANA_INIT] DLL >>>>>>>>
633 12:26:27.228564 [ANA_INIT] flow end
634 12:26:27.232119 ============ LP4 DIFF to SE enter ============
635 12:26:27.235209 ============ LP4 DIFF to SE exit ============
636 12:26:27.238197 [ANA_INIT] <<<<<<<<<<<<<
637 12:26:27.241825 [Flow] Enable top DCM control >>>>>
638 12:26:27.245458 [Flow] Enable top DCM control <<<<<
639 12:26:27.248343 Enable DLL master slave shuffle
640 12:26:27.255305 ==============================================================
641 12:26:27.255459 Gating Mode config
642 12:26:27.261610 ==============================================================
643 12:26:27.261745 Config description:
644 12:26:27.271958 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 12:26:27.278882 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 12:26:27.284983 SELPH_MODE 0: By rank 1: By Phase
647 12:26:27.288763 ==============================================================
648 12:26:27.291963 GAT_TRACK_EN = 1
649 12:26:27.295627 RX_GATING_MODE = 2
650 12:26:27.298835 RX_GATING_TRACK_MODE = 2
651 12:26:27.302091 SELPH_MODE = 1
652 12:26:27.305184 PICG_EARLY_EN = 1
653 12:26:27.308841 VALID_LAT_VALUE = 1
654 12:26:27.311910 ==============================================================
655 12:26:27.315462 Enter into Gating configuration >>>>
656 12:26:27.318753 Exit from Gating configuration <<<<
657 12:26:27.322113 Enter into DVFS_PRE_config >>>>>
658 12:26:27.335303 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 12:26:27.338944 Exit from DVFS_PRE_config <<<<<
660 12:26:27.341892 Enter into PICG configuration >>>>
661 12:26:27.342018 Exit from PICG configuration <<<<
662 12:26:27.345740 [RX_INPUT] configuration >>>>>
663 12:26:27.349059 [RX_INPUT] configuration <<<<<
664 12:26:27.355691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 12:26:27.358755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 12:26:27.366286 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 12:26:27.373192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 12:26:27.379534 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 12:26:27.386356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 12:26:27.389481 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 12:26:27.393348 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 12:26:27.396388 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 12:26:27.399531 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 12:26:27.406383 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 12:26:27.409481 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 12:26:27.413107 ===================================
677 12:26:27.416513 LPDDR4 DRAM CONFIGURATION
678 12:26:27.420023 ===================================
679 12:26:27.420184 EX_ROW_EN[0] = 0x0
680 12:26:27.423068 EX_ROW_EN[1] = 0x0
681 12:26:27.423191 LP4Y_EN = 0x0
682 12:26:27.426312 WORK_FSP = 0x0
683 12:26:27.426436 WL = 0x2
684 12:26:27.429911 RL = 0x2
685 12:26:27.430033 BL = 0x2
686 12:26:27.433256 RPST = 0x0
687 12:26:27.433373 RD_PRE = 0x0
688 12:26:27.436696 WR_PRE = 0x1
689 12:26:27.436816 WR_PST = 0x0
690 12:26:27.439760 DBI_WR = 0x0
691 12:26:27.439878 DBI_RD = 0x0
692 12:26:27.443264 OTF = 0x1
693 12:26:27.446260 ===================================
694 12:26:27.449946 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 12:26:27.452967 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 12:26:27.460348 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:26:27.463269 ===================================
698 12:26:27.463412 LPDDR4 DRAM CONFIGURATION
699 12:26:27.466463 ===================================
700 12:26:27.470138 EX_ROW_EN[0] = 0x10
701 12:26:27.473310 EX_ROW_EN[1] = 0x0
702 12:26:27.473433 LP4Y_EN = 0x0
703 12:26:27.476881 WORK_FSP = 0x0
704 12:26:27.477000 WL = 0x2
705 12:26:27.480037 RL = 0x2
706 12:26:27.480129 BL = 0x2
707 12:26:27.483054 RPST = 0x0
708 12:26:27.483149 RD_PRE = 0x0
709 12:26:27.486814 WR_PRE = 0x1
710 12:26:27.486903 WR_PST = 0x0
711 12:26:27.489932 DBI_WR = 0x0
712 12:26:27.490025 DBI_RD = 0x0
713 12:26:27.493573 OTF = 0x1
714 12:26:27.496787 ===================================
715 12:26:27.503616 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 12:26:27.506807 nWR fixed to 40
717 12:26:27.506922 [ModeRegInit_LP4] CH0 RK0
718 12:26:27.509911 [ModeRegInit_LP4] CH0 RK1
719 12:26:27.513723 [ModeRegInit_LP4] CH1 RK0
720 12:26:27.513835 [ModeRegInit_LP4] CH1 RK1
721 12:26:27.516701 match AC timing 13
722 12:26:27.519791 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 12:26:27.523454 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 12:26:27.530159 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 12:26:27.533181 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 12:26:27.540496 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 12:26:27.540622 [EMI DOE] emi_dcm 0
728 12:26:27.543544 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 12:26:27.546785 ==
730 12:26:27.550308 Dram Type= 6, Freq= 0, CH_0, rank 0
731 12:26:27.553350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 12:26:27.553479 ==
733 12:26:27.557024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 12:26:27.563638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 12:26:27.573624 [CA 0] Center 37 (7~68) winsize 62
736 12:26:27.576754 [CA 1] Center 37 (6~68) winsize 63
737 12:26:27.579946 [CA 2] Center 35 (5~66) winsize 62
738 12:26:27.583854 [CA 3] Center 34 (4~65) winsize 62
739 12:26:27.586907 [CA 4] Center 34 (3~65) winsize 63
740 12:26:27.590094 [CA 5] Center 34 (4~64) winsize 61
741 12:26:27.590220
742 12:26:27.593689 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 12:26:27.593840
744 12:26:27.596780 [CATrainingPosCal] consider 1 rank data
745 12:26:27.599994 u2DelayCellTimex100 = 270/100 ps
746 12:26:27.603794 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
747 12:26:27.606977 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
748 12:26:27.613366 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
749 12:26:27.617038 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
750 12:26:27.620077 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
751 12:26:27.623250 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
752 12:26:27.623401
753 12:26:27.627038 CA PerBit enable=1, Macro0, CA PI delay=34
754 12:26:27.627165
755 12:26:27.630043 [CBTSetCACLKResult] CA Dly = 34
756 12:26:27.630169 CS Dly: 5 (0~36)
757 12:26:27.630275 ==
758 12:26:27.633836 Dram Type= 6, Freq= 0, CH_0, rank 1
759 12:26:27.640128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 12:26:27.640297 ==
761 12:26:27.643842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 12:26:27.650031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 12:26:27.659438 [CA 0] Center 37 (6~68) winsize 63
764 12:26:27.662889 [CA 1] Center 37 (7~68) winsize 62
765 12:26:27.666444 [CA 2] Center 35 (5~66) winsize 62
766 12:26:27.670059 [CA 3] Center 35 (4~66) winsize 63
767 12:26:27.673069 [CA 4] Center 34 (4~65) winsize 62
768 12:26:27.676279 [CA 5] Center 33 (3~64) winsize 62
769 12:26:27.676424
770 12:26:27.679843 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 12:26:27.679974
772 12:26:27.682809 [CATrainingPosCal] consider 2 rank data
773 12:26:27.686628 u2DelayCellTimex100 = 270/100 ps
774 12:26:27.689721 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
775 12:26:27.692875 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
776 12:26:27.696565 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
777 12:26:27.703017 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
778 12:26:27.706177 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
779 12:26:27.710069 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
780 12:26:27.710220
781 12:26:27.713178 CA PerBit enable=1, Macro0, CA PI delay=34
782 12:26:27.713306
783 12:26:27.716297 [CBTSetCACLKResult] CA Dly = 34
784 12:26:27.716422 CS Dly: 6 (0~38)
785 12:26:27.716525
786 12:26:27.719726 ----->DramcWriteLeveling(PI) begin...
787 12:26:27.719883 ==
788 12:26:27.723276 Dram Type= 6, Freq= 0, CH_0, rank 0
789 12:26:27.730464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 12:26:27.730602 ==
791 12:26:27.733260 Write leveling (Byte 0): 27 => 27
792 12:26:27.736860 Write leveling (Byte 1): 28 => 28
793 12:26:27.737004 DramcWriteLeveling(PI) end<-----
794 12:26:27.737114
795 12:26:27.737221 ==
796 12:26:27.740485 Dram Type= 6, Freq= 0, CH_0, rank 0
797 12:26:27.746991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 12:26:27.747161 ==
799 12:26:27.750281 [Gating] SW mode calibration
800 12:26:27.757201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 12:26:27.760848 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 12:26:27.764262 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 12:26:27.770626 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 12:26:27.774071 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
805 12:26:27.777482 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:26:27.784201 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:26:27.787236 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:26:27.791051 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:26:27.797372 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:26:27.800424 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:26:27.803800 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:26:27.810591 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:26:27.813840 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:26:27.816984 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:26:27.823872 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:26:27.826909 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:26:27.830247 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:26:27.836933 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:26:27.840578 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 12:26:27.843628 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
821 12:26:27.850443 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:26:27.853586 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:26:27.857434 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:26:27.860619 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:26:27.866836 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:26:27.870194 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:26:27.873540 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:26:27.880337 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:26:27.883827 0 9 12 | B1->B0 | 2828 3030 | 1 0 | (0 0) (0 0)
830 12:26:27.887076 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 12:26:27.893743 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 12:26:27.897245 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 12:26:27.900475 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 12:26:27.906874 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 12:26:27.910546 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
836 12:26:27.913700 0 10 8 | B1->B0 | 3434 3232 | 0 0 | (1 0) (0 0)
837 12:26:27.920146 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
838 12:26:27.924023 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:26:27.927060 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:26:27.933946 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:26:27.937014 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:26:27.941101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:26:27.946860 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:26:27.950585 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
845 12:26:27.953666 0 11 12 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
846 12:26:27.957307 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:26:27.963606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:26:27.967267 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 12:26:27.970539 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:26:27.976838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 12:26:27.980482 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 12:26:27.983966 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 12:26:27.990656 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 12:26:27.993693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:26:27.997008 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:26:28.003614 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:26:28.007360 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:26:28.010552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 12:26:28.017542 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 12:26:28.020734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 12:26:28.023855 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 12:26:28.030845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 12:26:28.033971 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 12:26:28.037173 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 12:26:28.043985 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 12:26:28.047059 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 12:26:28.050627 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 12:26:28.053642 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 12:26:28.060698 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
870 12:26:28.063701 Total UI for P1: 0, mck2ui 16
871 12:26:28.066819 best dqsien dly found for B0: ( 0, 14, 10)
872 12:26:28.070574 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 12:26:28.073784 Total UI for P1: 0, mck2ui 16
874 12:26:28.076823 best dqsien dly found for B1: ( 0, 14, 12)
875 12:26:28.080575 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
876 12:26:28.083570 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
877 12:26:28.083681
878 12:26:28.087329 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
879 12:26:28.093757 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
880 12:26:28.093893 [Gating] SW calibration Done
881 12:26:28.093970 ==
882 12:26:28.096826 Dram Type= 6, Freq= 0, CH_0, rank 0
883 12:26:28.103583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 12:26:28.103755 ==
885 12:26:28.103882 RX Vref Scan: 0
886 12:26:28.103985
887 12:26:28.107180 RX Vref 0 -> 0, step: 1
888 12:26:28.107318
889 12:26:28.110355 RX Delay -130 -> 252, step: 16
890 12:26:28.113382 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
891 12:26:28.117239 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
892 12:26:28.120337 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
893 12:26:28.123578 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
894 12:26:28.130466 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
895 12:26:28.133484 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
896 12:26:28.137292 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
897 12:26:28.140510 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
898 12:26:28.143591 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
899 12:26:28.150770 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
900 12:26:28.153913 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
901 12:26:28.157504 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
902 12:26:28.160603 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
903 12:26:28.163793 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
904 12:26:28.170885 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
905 12:26:28.173865 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
906 12:26:28.174079 ==
907 12:26:28.177027 Dram Type= 6, Freq= 0, CH_0, rank 0
908 12:26:28.180841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 12:26:28.181026 ==
910 12:26:28.183983 DQS Delay:
911 12:26:28.184161 DQS0 = 0, DQS1 = 0
912 12:26:28.184272 DQM Delay:
913 12:26:28.187139 DQM0 = 88, DQM1 = 82
914 12:26:28.187308 DQ Delay:
915 12:26:28.190321 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
916 12:26:28.194145 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
917 12:26:28.197212 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
918 12:26:28.200743 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
919 12:26:28.200893
920 12:26:28.201003
921 12:26:28.201101 ==
922 12:26:28.203816 Dram Type= 6, Freq= 0, CH_0, rank 0
923 12:26:28.210386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 12:26:28.210545 ==
925 12:26:28.210655
926 12:26:28.210752
927 12:26:28.210847 TX Vref Scan disable
928 12:26:28.214061 == TX Byte 0 ==
929 12:26:28.217486 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
930 12:26:28.220605 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
931 12:26:28.223834 == TX Byte 1 ==
932 12:26:28.227551 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
933 12:26:28.230676 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
934 12:26:28.233858 ==
935 12:26:28.237481 Dram Type= 6, Freq= 0, CH_0, rank 0
936 12:26:28.240686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 12:26:28.240862 ==
938 12:26:28.253301 TX Vref=22, minBit 7, minWin=26, winSum=438
939 12:26:28.256415 TX Vref=24, minBit 1, minWin=27, winSum=441
940 12:26:28.260217 TX Vref=26, minBit 3, minWin=27, winSum=442
941 12:26:28.263072 TX Vref=28, minBit 7, minWin=27, winSum=447
942 12:26:28.266785 TX Vref=30, minBit 12, minWin=27, winSum=454
943 12:26:28.273056 TX Vref=32, minBit 3, minWin=27, winSum=452
944 12:26:28.276321 [TxChooseVref] Worse bit 12, Min win 27, Win sum 454, Final Vref 30
945 12:26:28.276468
946 12:26:28.280066 Final TX Range 1 Vref 30
947 12:26:28.280200
948 12:26:28.280336 ==
949 12:26:28.283049 Dram Type= 6, Freq= 0, CH_0, rank 0
950 12:26:28.286805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 12:26:28.286936 ==
952 12:26:28.289999
953 12:26:28.290124
954 12:26:28.290235 TX Vref Scan disable
955 12:26:28.293080 == TX Byte 0 ==
956 12:26:28.296811 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
957 12:26:28.300022 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
958 12:26:28.303694 == TX Byte 1 ==
959 12:26:28.306666 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
960 12:26:28.310067 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
961 12:26:28.310175
962 12:26:28.313640 [DATLAT]
963 12:26:28.313745 Freq=800, CH0 RK0
964 12:26:28.313818
965 12:26:28.316674 DATLAT Default: 0xa
966 12:26:28.316771 0, 0xFFFF, sum = 0
967 12:26:28.320152 1, 0xFFFF, sum = 0
968 12:26:28.320286 2, 0xFFFF, sum = 0
969 12:26:28.323319 3, 0xFFFF, sum = 0
970 12:26:28.323488 4, 0xFFFF, sum = 0
971 12:26:28.326726 5, 0xFFFF, sum = 0
972 12:26:28.326861 6, 0xFFFF, sum = 0
973 12:26:28.330276 7, 0xFFFF, sum = 0
974 12:26:28.330391 8, 0xFFFF, sum = 0
975 12:26:28.333422 9, 0x0, sum = 1
976 12:26:28.333537 10, 0x0, sum = 2
977 12:26:28.337070 11, 0x0, sum = 3
978 12:26:28.337176 12, 0x0, sum = 4
979 12:26:28.340194 best_step = 10
980 12:26:28.340292
981 12:26:28.340362 ==
982 12:26:28.343980 Dram Type= 6, Freq= 0, CH_0, rank 0
983 12:26:28.347127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 12:26:28.347262 ==
985 12:26:28.350238 RX Vref Scan: 1
986 12:26:28.350386
987 12:26:28.350490 Set Vref Range= 32 -> 127
988 12:26:28.350588
989 12:26:28.353467 RX Vref 32 -> 127, step: 1
990 12:26:28.353610
991 12:26:28.357227 RX Delay -95 -> 252, step: 8
992 12:26:28.357382
993 12:26:28.360335 Set Vref, RX VrefLevel [Byte0]: 32
994 12:26:28.363933 [Byte1]: 32
995 12:26:28.364091
996 12:26:28.367511 Set Vref, RX VrefLevel [Byte0]: 33
997 12:26:28.370730 [Byte1]: 33
998 12:26:28.370888
999 12:26:28.373917 Set Vref, RX VrefLevel [Byte0]: 34
1000 12:26:28.377618 [Byte1]: 34
1001 12:26:28.381348
1002 12:26:28.381514 Set Vref, RX VrefLevel [Byte0]: 35
1003 12:26:28.384359 [Byte1]: 35
1004 12:26:28.388903
1005 12:26:28.389060 Set Vref, RX VrefLevel [Byte0]: 36
1006 12:26:28.391837 [Byte1]: 36
1007 12:26:28.396887
1008 12:26:28.397044 Set Vref, RX VrefLevel [Byte0]: 37
1009 12:26:28.400069 [Byte1]: 37
1010 12:26:28.403785
1011 12:26:28.403953 Set Vref, RX VrefLevel [Byte0]: 38
1012 12:26:28.407549 [Byte1]: 38
1013 12:26:28.411679
1014 12:26:28.411842 Set Vref, RX VrefLevel [Byte0]: 39
1015 12:26:28.415109 [Byte1]: 39
1016 12:26:28.418870
1017 12:26:28.422459 Set Vref, RX VrefLevel [Byte0]: 40
1018 12:26:28.422632 [Byte1]: 40
1019 12:26:28.426736
1020 12:26:28.426903 Set Vref, RX VrefLevel [Byte0]: 41
1021 12:26:28.430433 [Byte1]: 41
1022 12:26:28.434570
1023 12:26:28.434715 Set Vref, RX VrefLevel [Byte0]: 42
1024 12:26:28.437547 [Byte1]: 42
1025 12:26:28.442071
1026 12:26:28.442235 Set Vref, RX VrefLevel [Byte0]: 43
1027 12:26:28.445205 [Byte1]: 43
1028 12:26:28.449542
1029 12:26:28.449703 Set Vref, RX VrefLevel [Byte0]: 44
1030 12:26:28.452596 [Byte1]: 44
1031 12:26:28.457047
1032 12:26:28.457202 Set Vref, RX VrefLevel [Byte0]: 45
1033 12:26:28.460109 [Byte1]: 45
1034 12:26:28.464474
1035 12:26:28.464601 Set Vref, RX VrefLevel [Byte0]: 46
1036 12:26:28.468228 [Byte1]: 46
1037 12:26:28.472498
1038 12:26:28.472637 Set Vref, RX VrefLevel [Byte0]: 47
1039 12:26:28.475674 [Byte1]: 47
1040 12:26:28.479937
1041 12:26:28.480077 Set Vref, RX VrefLevel [Byte0]: 48
1042 12:26:28.483002 [Byte1]: 48
1043 12:26:28.487363
1044 12:26:28.487464 Set Vref, RX VrefLevel [Byte0]: 49
1045 12:26:28.491135 [Byte1]: 49
1046 12:26:28.494789
1047 12:26:28.498685 Set Vref, RX VrefLevel [Byte0]: 50
1048 12:26:28.498792 [Byte1]: 50
1049 12:26:28.503042
1050 12:26:28.503138 Set Vref, RX VrefLevel [Byte0]: 51
1051 12:26:28.506096 [Byte1]: 51
1052 12:26:28.510410
1053 12:26:28.510551 Set Vref, RX VrefLevel [Byte0]: 52
1054 12:26:28.513633 [Byte1]: 52
1055 12:26:28.517856
1056 12:26:28.518004 Set Vref, RX VrefLevel [Byte0]: 53
1057 12:26:28.521509 [Byte1]: 53
1058 12:26:28.525541
1059 12:26:28.525689 Set Vref, RX VrefLevel [Byte0]: 54
1060 12:26:28.528959 [Byte1]: 54
1061 12:26:28.533159
1062 12:26:28.533305 Set Vref, RX VrefLevel [Byte0]: 55
1063 12:26:28.536317 [Byte1]: 55
1064 12:26:28.540471
1065 12:26:28.540612 Set Vref, RX VrefLevel [Byte0]: 56
1066 12:26:28.543917 [Byte1]: 56
1067 12:26:28.548018
1068 12:26:28.548166 Set Vref, RX VrefLevel [Byte0]: 57
1069 12:26:28.551643 [Byte1]: 57
1070 12:26:28.556031
1071 12:26:28.556181 Set Vref, RX VrefLevel [Byte0]: 58
1072 12:26:28.559181 [Byte1]: 58
1073 12:26:28.563542
1074 12:26:28.563653 Set Vref, RX VrefLevel [Byte0]: 59
1075 12:26:28.566608 [Byte1]: 59
1076 12:26:28.570997
1077 12:26:28.571109 Set Vref, RX VrefLevel [Byte0]: 60
1078 12:26:28.574531 [Byte1]: 60
1079 12:26:28.578901
1080 12:26:28.579020 Set Vref, RX VrefLevel [Byte0]: 61
1081 12:26:28.581985 [Byte1]: 61
1082 12:26:28.586419
1083 12:26:28.586568 Set Vref, RX VrefLevel [Byte0]: 62
1084 12:26:28.589467 [Byte1]: 62
1085 12:26:28.593827
1086 12:26:28.593973 Set Vref, RX VrefLevel [Byte0]: 63
1087 12:26:28.596995 [Byte1]: 63
1088 12:26:28.601392
1089 12:26:28.601541 Set Vref, RX VrefLevel [Byte0]: 64
1090 12:26:28.604478 [Byte1]: 64
1091 12:26:28.608834
1092 12:26:28.608970 Set Vref, RX VrefLevel [Byte0]: 65
1093 12:26:28.612625 [Byte1]: 65
1094 12:26:28.616318
1095 12:26:28.616447 Set Vref, RX VrefLevel [Byte0]: 66
1096 12:26:28.620043 [Byte1]: 66
1097 12:26:28.624356
1098 12:26:28.624510 Set Vref, RX VrefLevel [Byte0]: 67
1099 12:26:28.627190 [Byte1]: 67
1100 12:26:28.631955
1101 12:26:28.632073 Set Vref, RX VrefLevel [Byte0]: 68
1102 12:26:28.634875 [Byte1]: 68
1103 12:26:28.639212
1104 12:26:28.639357 Set Vref, RX VrefLevel [Byte0]: 69
1105 12:26:28.642858 [Byte1]: 69
1106 12:26:28.647161
1107 12:26:28.647301 Set Vref, RX VrefLevel [Byte0]: 70
1108 12:26:28.650097 [Byte1]: 70
1109 12:26:28.654758
1110 12:26:28.654940 Set Vref, RX VrefLevel [Byte0]: 71
1111 12:26:28.657938 [Byte1]: 71
1112 12:26:28.661953
1113 12:26:28.662100 Set Vref, RX VrefLevel [Byte0]: 72
1114 12:26:28.665637 [Byte1]: 72
1115 12:26:28.670051
1116 12:26:28.670209 Set Vref, RX VrefLevel [Byte0]: 73
1117 12:26:28.673153 [Byte1]: 73
1118 12:26:28.677541
1119 12:26:28.677704 Set Vref, RX VrefLevel [Byte0]: 74
1120 12:26:28.680517 [Byte1]: 74
1121 12:26:28.684870
1122 12:26:28.685012 Set Vref, RX VrefLevel [Byte0]: 75
1123 12:26:28.688101 [Byte1]: 75
1124 12:26:28.692572
1125 12:26:28.692728 Final RX Vref Byte 0 = 60 to rank0
1126 12:26:28.696225 Final RX Vref Byte 1 = 58 to rank0
1127 12:26:28.699295 Final RX Vref Byte 0 = 60 to rank1
1128 12:26:28.702554 Final RX Vref Byte 1 = 58 to rank1==
1129 12:26:28.705651 Dram Type= 6, Freq= 0, CH_0, rank 0
1130 12:26:28.712584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 12:26:28.712732 ==
1132 12:26:28.712847 DQS Delay:
1133 12:26:28.712948 DQS0 = 0, DQS1 = 0
1134 12:26:28.715621 DQM Delay:
1135 12:26:28.715748 DQM0 = 87, DQM1 = 78
1136 12:26:28.719428 DQ Delay:
1137 12:26:28.722548 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1138 12:26:28.722659 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1139 12:26:28.725767 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =76
1140 12:26:28.732359 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1141 12:26:28.732474
1142 12:26:28.732546
1143 12:26:28.739502 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1144 12:26:28.742225 CH0 RK0: MR19=606, MR18=2910
1145 12:26:28.749077 CH0_RK0: MR19=0x606, MR18=0x2910, DQSOSC=399, MR23=63, INC=92, DEC=61
1146 12:26:28.749218
1147 12:26:28.752793 ----->DramcWriteLeveling(PI) begin...
1148 12:26:28.752935 ==
1149 12:26:28.755710 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 12:26:28.759218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 12:26:28.759376 ==
1152 12:26:28.762826 Write leveling (Byte 0): 31 => 31
1153 12:26:28.765702 Write leveling (Byte 1): 28 => 28
1154 12:26:28.769351 DramcWriteLeveling(PI) end<-----
1155 12:26:28.769465
1156 12:26:28.769538 ==
1157 12:26:28.772495 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 12:26:28.776215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 12:26:28.776313 ==
1160 12:26:28.779265 [Gating] SW mode calibration
1161 12:26:28.785786 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1162 12:26:28.792623 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1163 12:26:28.796402 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 12:26:28.799549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1165 12:26:28.805976 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1166 12:26:28.850025 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:26:28.850371 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:26:28.850456 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:26:28.850524 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:26:28.850608 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:26:28.850688 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:26:28.850940 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:26:28.851022 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:26:28.851095 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:26:28.851343 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:26:28.893955 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:26:28.894538 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:26:28.894633 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:26:28.894893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1180 12:26:28.894998 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1181 12:26:28.895101 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1182 12:26:28.895195 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:26:28.895288 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:26:28.895408 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:26:28.895515 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:26:28.938229 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:26:28.938401 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:26:28.938479 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:26:28.938746 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1190 12:26:28.938848 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1191 12:26:28.938955 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 12:26:28.939048 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 12:26:28.939149 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 12:26:28.939543 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 12:26:28.939649 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 12:26:28.942705 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 12:26:28.945804 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
1198 12:26:28.949283 0 10 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
1199 12:26:28.956134 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 12:26:28.959063 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:26:28.962685 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:26:28.965757 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:26:28.972352 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:26:28.975956 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1205 12:26:28.979652 0 11 8 | B1->B0 | 2d2d 3e3e | 0 0 | (1 1) (0 0)
1206 12:26:28.985855 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1207 12:26:28.989779 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 12:26:28.993343 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 12:26:28.996921 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:26:29.003196 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 12:26:29.007491 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:26:29.010722 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1213 12:26:29.013780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1214 12:26:29.020645 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:26:29.023802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:26:29.027385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:26:29.033898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:26:29.037487 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:26:29.040566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:26:29.047388 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:26:29.050590 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:26:29.054164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:26:29.060851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:26:29.064022 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:26:29.067096 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:26:29.073853 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:26:29.077486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:26:29.080651 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1229 12:26:29.086899 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1230 12:26:29.087107 Total UI for P1: 0, mck2ui 16
1231 12:26:29.093877 best dqsien dly found for B0: ( 0, 14, 4)
1232 12:26:29.096944 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 12:26:29.100569 Total UI for P1: 0, mck2ui 16
1234 12:26:29.103583 best dqsien dly found for B1: ( 0, 14, 8)
1235 12:26:29.107297 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1236 12:26:29.110426 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1237 12:26:29.110514
1238 12:26:29.113619 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1239 12:26:29.117340 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1240 12:26:29.120473 [Gating] SW calibration Done
1241 12:26:29.120559 ==
1242 12:26:29.123623 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 12:26:29.126806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 12:26:29.126922 ==
1245 12:26:29.130532 RX Vref Scan: 0
1246 12:26:29.130634
1247 12:26:29.133857 RX Vref 0 -> 0, step: 1
1248 12:26:29.133945
1249 12:26:29.134013 RX Delay -130 -> 252, step: 16
1250 12:26:29.140633 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1251 12:26:29.143704 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1252 12:26:29.147340 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1253 12:26:29.150509 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1254 12:26:29.153751 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1255 12:26:29.160331 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1256 12:26:29.163855 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1257 12:26:29.167113 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1258 12:26:29.170243 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1259 12:26:29.173957 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1260 12:26:29.180186 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1261 12:26:29.183766 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1262 12:26:29.187195 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1263 12:26:29.190099 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1264 12:26:29.193837 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1265 12:26:29.200326 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1266 12:26:29.200517 ==
1267 12:26:29.204022 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 12:26:29.206951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 12:26:29.207108 ==
1270 12:26:29.207226 DQS Delay:
1271 12:26:29.210083 DQS0 = 0, DQS1 = 0
1272 12:26:29.210219 DQM Delay:
1273 12:26:29.213850 DQM0 = 86, DQM1 = 76
1274 12:26:29.213999 DQ Delay:
1275 12:26:29.216899 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1276 12:26:29.220098 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
1277 12:26:29.232440 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1278 12:26:29.232797 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1279 12:26:29.232914
1280 12:26:29.233013
1281 12:26:29.233107 ==
1282 12:26:29.233202 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 12:26:29.233869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 12:26:29.233981 ==
1285 12:26:29.237063
1286 12:26:29.237176
1287 12:26:29.237275 TX Vref Scan disable
1288 12:26:29.240098 == TX Byte 0 ==
1289 12:26:29.243796 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1290 12:26:29.247079 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1291 12:26:29.250021 == TX Byte 1 ==
1292 12:26:29.253760 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1293 12:26:29.256840 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1294 12:26:29.256957 ==
1295 12:26:29.260535 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 12:26:29.266591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 12:26:29.266713 ==
1298 12:26:29.279286 TX Vref=22, minBit 8, minWin=27, winSum=445
1299 12:26:29.282922 TX Vref=24, minBit 8, minWin=27, winSum=447
1300 12:26:29.285971 TX Vref=26, minBit 12, minWin=27, winSum=453
1301 12:26:29.289081 TX Vref=28, minBit 12, minWin=27, winSum=452
1302 12:26:29.292729 TX Vref=30, minBit 5, minWin=28, winSum=459
1303 12:26:29.299203 TX Vref=32, minBit 4, minWin=28, winSum=458
1304 12:26:29.302878 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
1305 12:26:29.302995
1306 12:26:29.306032 Final TX Range 1 Vref 30
1307 12:26:29.306146
1308 12:26:29.306246 ==
1309 12:26:29.309390 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 12:26:29.312857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 12:26:29.312978 ==
1312 12:26:29.315940
1313 12:26:29.316051
1314 12:26:29.316148 TX Vref Scan disable
1315 12:26:29.319732 == TX Byte 0 ==
1316 12:26:29.322794 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1317 12:26:29.326016 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1318 12:26:29.329774 == TX Byte 1 ==
1319 12:26:29.333253 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1320 12:26:29.336129 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1321 12:26:29.339167
1322 12:26:29.339273 [DATLAT]
1323 12:26:29.339375 Freq=800, CH0 RK1
1324 12:26:29.339473
1325 12:26:29.342984 DATLAT Default: 0xa
1326 12:26:29.343099 0, 0xFFFF, sum = 0
1327 12:26:29.346015 1, 0xFFFF, sum = 0
1328 12:26:29.346131 2, 0xFFFF, sum = 0
1329 12:26:29.349405 3, 0xFFFF, sum = 0
1330 12:26:29.349522 4, 0xFFFF, sum = 0
1331 12:26:29.352981 5, 0xFFFF, sum = 0
1332 12:26:29.356137 6, 0xFFFF, sum = 0
1333 12:26:29.356254 7, 0xFFFF, sum = 0
1334 12:26:29.359131 8, 0xFFFF, sum = 0
1335 12:26:29.359247 9, 0x0, sum = 1
1336 12:26:29.359355 10, 0x0, sum = 2
1337 12:26:29.362978 11, 0x0, sum = 3
1338 12:26:29.363090 12, 0x0, sum = 4
1339 12:26:29.365913 best_step = 10
1340 12:26:29.366029
1341 12:26:29.366127 ==
1342 12:26:29.369721 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 12:26:29.372794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 12:26:29.372903 ==
1345 12:26:29.376403 RX Vref Scan: 0
1346 12:26:29.376514
1347 12:26:29.376615 RX Vref 0 -> 0, step: 1
1348 12:26:29.376707
1349 12:26:29.379231 RX Delay -95 -> 252, step: 8
1350 12:26:29.386482 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1351 12:26:29.389461 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1352 12:26:29.392525 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1353 12:26:29.396303 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1354 12:26:29.399803 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1355 12:26:29.406522 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1356 12:26:29.409540 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1357 12:26:29.412994 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1358 12:26:29.415956 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1359 12:26:29.419527 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1360 12:26:29.426417 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1361 12:26:29.429567 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1362 12:26:29.432744 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1363 12:26:29.435870 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1364 12:26:29.439273 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1365 12:26:29.445941 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1366 12:26:29.446053 ==
1367 12:26:29.449780 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 12:26:29.452787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 12:26:29.452898 ==
1370 12:26:29.452993 DQS Delay:
1371 12:26:29.455928 DQS0 = 0, DQS1 = 0
1372 12:26:29.456036 DQM Delay:
1373 12:26:29.459590 DQM0 = 87, DQM1 = 77
1374 12:26:29.459697 DQ Delay:
1375 12:26:29.462683 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1376 12:26:29.466369 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1377 12:26:29.469537 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1378 12:26:29.472680 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1379 12:26:29.472790
1380 12:26:29.472885
1381 12:26:29.479541 [DQSOSCAuto] RK1, (LSB)MR18= 0x331b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
1382 12:26:29.482685 CH0 RK1: MR19=606, MR18=331B
1383 12:26:29.489514 CH0_RK1: MR19=0x606, MR18=0x331B, DQSOSC=396, MR23=63, INC=94, DEC=62
1384 12:26:29.492688 [RxdqsGatingPostProcess] freq 800
1385 12:26:29.499371 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1386 12:26:29.499488 Pre-setting of DQS Precalculation
1387 12:26:29.505929 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1388 12:26:29.506052 ==
1389 12:26:29.509360 Dram Type= 6, Freq= 0, CH_1, rank 0
1390 12:26:29.512932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 12:26:29.513049 ==
1392 12:26:29.519448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 12:26:29.526201 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 12:26:29.534179 [CA 0] Center 36 (6~66) winsize 61
1395 12:26:29.537972 [CA 1] Center 36 (6~67) winsize 62
1396 12:26:29.540909 [CA 2] Center 34 (5~64) winsize 60
1397 12:26:29.544145 [CA 3] Center 33 (3~64) winsize 62
1398 12:26:29.547879 [CA 4] Center 34 (4~65) winsize 62
1399 12:26:29.550957 [CA 5] Center 33 (3~64) winsize 62
1400 12:26:29.551075
1401 12:26:29.554228 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1402 12:26:29.554340
1403 12:26:29.557280 [CATrainingPosCal] consider 1 rank data
1404 12:26:29.561144 u2DelayCellTimex100 = 270/100 ps
1405 12:26:29.564180 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1406 12:26:29.567303 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1407 12:26:29.574083 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1408 12:26:29.577590 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1409 12:26:29.580914 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 12:26:29.584054 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1411 12:26:29.584169
1412 12:26:29.587229 CA PerBit enable=1, Macro0, CA PI delay=33
1413 12:26:29.587341
1414 12:26:29.590954 [CBTSetCACLKResult] CA Dly = 33
1415 12:26:29.591067 CS Dly: 4 (0~35)
1416 12:26:29.594351 ==
1417 12:26:29.594465 Dram Type= 6, Freq= 0, CH_1, rank 1
1418 12:26:29.601060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 12:26:29.601179 ==
1420 12:26:29.604166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 12:26:29.610807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 12:26:29.620289 [CA 0] Center 36 (6~66) winsize 61
1423 12:26:29.623876 [CA 1] Center 36 (6~66) winsize 61
1424 12:26:29.626991 [CA 2] Center 34 (4~64) winsize 61
1425 12:26:29.630571 [CA 3] Center 33 (3~64) winsize 62
1426 12:26:29.633497 [CA 4] Center 34 (3~65) winsize 63
1427 12:26:29.637205 [CA 5] Center 33 (3~64) winsize 62
1428 12:26:29.637333
1429 12:26:29.640268 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1430 12:26:29.640386
1431 12:26:29.644027 [CATrainingPosCal] consider 2 rank data
1432 12:26:29.647842 u2DelayCellTimex100 = 270/100 ps
1433 12:26:29.651524 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1434 12:26:29.655285 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1435 12:26:29.659070 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1436 12:26:29.662265 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1437 12:26:29.666119 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1438 12:26:29.669925 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1439 12:26:29.670060
1440 12:26:29.672851 CA PerBit enable=1, Macro0, CA PI delay=33
1441 12:26:29.672974
1442 12:26:29.676553 [CBTSetCACLKResult] CA Dly = 33
1443 12:26:29.680283 CS Dly: 5 (0~37)
1444 12:26:29.680415
1445 12:26:29.683297 ----->DramcWriteLeveling(PI) begin...
1446 12:26:29.683430 ==
1447 12:26:29.686546 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 12:26:29.689792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 12:26:29.689914 ==
1450 12:26:29.693506 Write leveling (Byte 0): 26 => 26
1451 12:26:29.696673 Write leveling (Byte 1): 28 => 28
1452 12:26:29.700152 DramcWriteLeveling(PI) end<-----
1453 12:26:29.700272
1454 12:26:29.700377 ==
1455 12:26:29.703537 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 12:26:29.706433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 12:26:29.706525 ==
1458 12:26:29.710133 [Gating] SW mode calibration
1459 12:26:29.716827 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1460 12:26:29.723398 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1461 12:26:29.726390 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 12:26:29.729929 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1463 12:26:29.733558 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:26:29.740231 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:26:29.743484 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1466 12:26:29.746641 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:26:29.753521 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:26:29.756631 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:26:29.760335 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:26:29.766941 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:26:29.769976 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:26:29.773674 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:26:29.779930 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1474 12:26:29.783668 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:26:29.786800 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1476 12:26:29.793483 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:26:29.796655 0 8 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1478 12:26:29.799969 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1479 12:26:29.806791 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1480 12:26:29.810241 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:26:29.813762 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1482 12:26:29.816797 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1483 12:26:29.823335 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:26:29.827063 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:26:29.829979 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:26:29.836981 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:26:29.840400 0 9 8 | B1->B0 | 2424 2626 | 0 1 | (0 0) (0 0)
1488 12:26:29.843353 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1489 12:26:29.850284 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 12:26:29.853399 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 12:26:29.857018 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1492 12:26:29.863309 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:26:29.867128 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1494 12:26:29.870160 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 12:26:29.877027 0 10 8 | B1->B0 | 2d2d 2e2e | 0 1 | (1 0) (1 0)
1496 12:26:29.880060 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:26:29.883216 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:26:29.890028 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:26:29.893796 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:26:29.896968 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:26:29.903645 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:26:29.906775 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:26:29.909887 0 11 8 | B1->B0 | 3434 3232 | 0 1 | (1 1) (0 0)
1504 12:26:29.913566 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 12:26:29.919966 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 12:26:29.923464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 12:26:29.926419 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 12:26:29.933118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:26:29.936625 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:26:29.940137 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:26:29.946615 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1512 12:26:29.950077 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:26:29.953635 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:26:29.959903 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:26:29.963593 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:26:29.966717 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:26:29.973613 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:26:29.976689 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:26:29.979925 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:26:29.986699 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:26:29.989829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:26:29.993485 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:26:29.999810 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:26:30.003466 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:26:30.006650 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:26:30.010350 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:26:30.017299 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 12:26:30.020288 Total UI for P1: 0, mck2ui 16
1529 12:26:30.023233 best dqsien dly found for B0: ( 0, 14, 6)
1530 12:26:30.026830 Total UI for P1: 0, mck2ui 16
1531 12:26:30.030230 best dqsien dly found for B1: ( 0, 14, 6)
1532 12:26:30.033840 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1533 12:26:30.036963 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1534 12:26:30.037097
1535 12:26:30.040404 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1536 12:26:30.043359 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1537 12:26:30.046945 [Gating] SW calibration Done
1538 12:26:30.047083 ==
1539 12:26:30.050048 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 12:26:30.053568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 12:26:30.053702 ==
1542 12:26:30.056741 RX Vref Scan: 0
1543 12:26:30.056873
1544 12:26:30.056990 RX Vref 0 -> 0, step: 1
1545 12:26:30.057102
1546 12:26:30.059989 RX Delay -130 -> 252, step: 16
1547 12:26:30.063745 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1548 12:26:30.070025 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1549 12:26:30.073763 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1550 12:26:30.076910 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1551 12:26:30.079957 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1552 12:26:30.083717 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1553 12:26:30.090492 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1554 12:26:30.093516 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1555 12:26:30.096665 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1556 12:26:30.100383 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1557 12:26:30.103551 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1558 12:26:30.110349 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1559 12:26:30.113402 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1560 12:26:30.117058 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1561 12:26:30.120172 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1562 12:26:30.123896 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1563 12:26:30.127117 ==
1564 12:26:30.127251 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 12:26:30.133594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 12:26:30.133723 ==
1567 12:26:30.133839 DQS Delay:
1568 12:26:30.137091 DQS0 = 0, DQS1 = 0
1569 12:26:30.137222 DQM Delay:
1570 12:26:30.140252 DQM0 = 85, DQM1 = 75
1571 12:26:30.140376 DQ Delay:
1572 12:26:30.143807 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1573 12:26:30.146756 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1574 12:26:30.150326 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1575 12:26:30.153451 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1576 12:26:30.153551
1577 12:26:30.153620
1578 12:26:30.153683 ==
1579 12:26:30.157065 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 12:26:30.160541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 12:26:30.160664 ==
1582 12:26:30.160765
1583 12:26:30.160859
1584 12:26:30.163600 TX Vref Scan disable
1585 12:26:30.167154 == TX Byte 0 ==
1586 12:26:30.170491 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1587 12:26:30.173645 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1588 12:26:30.176756 == TX Byte 1 ==
1589 12:26:30.180465 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1590 12:26:30.183587 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1591 12:26:30.183723 ==
1592 12:26:30.187195 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 12:26:30.190319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 12:26:30.190462 ==
1595 12:26:30.204390 TX Vref=22, minBit 0, minWin=27, winSum=440
1596 12:26:30.208146 TX Vref=24, minBit 7, minWin=27, winSum=446
1597 12:26:30.211142 TX Vref=26, minBit 4, minWin=27, winSum=445
1598 12:26:30.214871 TX Vref=28, minBit 13, minWin=27, winSum=451
1599 12:26:30.217951 TX Vref=30, minBit 2, minWin=28, winSum=454
1600 12:26:30.224989 TX Vref=32, minBit 3, minWin=28, winSum=455
1601 12:26:30.228151 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 32
1602 12:26:30.228323
1603 12:26:30.232034 Final TX Range 1 Vref 32
1604 12:26:30.232200
1605 12:26:30.232306 ==
1606 12:26:30.235655 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 12:26:30.238677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 12:26:30.238827 ==
1609 12:26:30.238938
1610 12:26:30.239038
1611 12:26:30.242184 TX Vref Scan disable
1612 12:26:30.245313 == TX Byte 0 ==
1613 12:26:30.248812 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1614 12:26:30.251900 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1615 12:26:30.255354 == TX Byte 1 ==
1616 12:26:30.258536 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1617 12:26:30.262114 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1618 12:26:30.262250
1619 12:26:30.265650 [DATLAT]
1620 12:26:30.265782 Freq=800, CH1 RK0
1621 12:26:30.265884
1622 12:26:30.268642 DATLAT Default: 0xa
1623 12:26:30.268763 0, 0xFFFF, sum = 0
1624 12:26:30.272242 1, 0xFFFF, sum = 0
1625 12:26:30.272385 2, 0xFFFF, sum = 0
1626 12:26:30.275824 3, 0xFFFF, sum = 0
1627 12:26:30.275961 4, 0xFFFF, sum = 0
1628 12:26:30.278688 5, 0xFFFF, sum = 0
1629 12:26:30.278825 6, 0xFFFF, sum = 0
1630 12:26:30.281852 7, 0xFFFF, sum = 0
1631 12:26:30.281975 8, 0xFFFF, sum = 0
1632 12:26:30.285485 9, 0x0, sum = 1
1633 12:26:30.285608 10, 0x0, sum = 2
1634 12:26:30.288649 11, 0x0, sum = 3
1635 12:26:30.288772 12, 0x0, sum = 4
1636 12:26:30.292325 best_step = 10
1637 12:26:30.292441
1638 12:26:30.292543 ==
1639 12:26:30.295372 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 12:26:30.299127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 12:26:30.299244 ==
1642 12:26:30.299344 RX Vref Scan: 1
1643 12:26:30.299450
1644 12:26:30.302224 Set Vref Range= 32 -> 127
1645 12:26:30.302337
1646 12:26:30.305495 RX Vref 32 -> 127, step: 1
1647 12:26:30.305609
1648 12:26:30.309310 RX Delay -111 -> 252, step: 8
1649 12:26:30.309421
1650 12:26:30.312450 Set Vref, RX VrefLevel [Byte0]: 32
1651 12:26:30.315556 [Byte1]: 32
1652 12:26:30.315670
1653 12:26:30.318669 Set Vref, RX VrefLevel [Byte0]: 33
1654 12:26:30.322542 [Byte1]: 33
1655 12:26:30.322657
1656 12:26:30.325687 Set Vref, RX VrefLevel [Byte0]: 34
1657 12:26:30.328926 [Byte1]: 34
1658 12:26:30.333183
1659 12:26:30.333298 Set Vref, RX VrefLevel [Byte0]: 35
1660 12:26:30.336328 [Byte1]: 35
1661 12:26:30.340601
1662 12:26:30.340725 Set Vref, RX VrefLevel [Byte0]: 36
1663 12:26:30.343708 [Byte1]: 36
1664 12:26:30.347852
1665 12:26:30.347971 Set Vref, RX VrefLevel [Byte0]: 37
1666 12:26:30.351194 [Byte1]: 37
1667 12:26:30.355870
1668 12:26:30.355987 Set Vref, RX VrefLevel [Byte0]: 38
1669 12:26:30.359341 [Byte1]: 38
1670 12:26:30.363826
1671 12:26:30.363943 Set Vref, RX VrefLevel [Byte0]: 39
1672 12:26:30.366751 [Byte1]: 39
1673 12:26:30.371040
1674 12:26:30.371153 Set Vref, RX VrefLevel [Byte0]: 40
1675 12:26:30.374631 [Byte1]: 40
1676 12:26:30.378544
1677 12:26:30.378632 Set Vref, RX VrefLevel [Byte0]: 41
1678 12:26:30.382079 [Byte1]: 41
1679 12:26:30.386123
1680 12:26:30.386210 Set Vref, RX VrefLevel [Byte0]: 42
1681 12:26:30.389861 [Byte1]: 42
1682 12:26:30.394246
1683 12:26:30.394331 Set Vref, RX VrefLevel [Byte0]: 43
1684 12:26:30.397311 [Byte1]: 43
1685 12:26:30.401777
1686 12:26:30.401861 Set Vref, RX VrefLevel [Byte0]: 44
1687 12:26:30.404835 [Byte1]: 44
1688 12:26:30.409159
1689 12:26:30.409246 Set Vref, RX VrefLevel [Byte0]: 45
1690 12:26:30.413043 [Byte1]: 45
1691 12:26:30.416782
1692 12:26:30.416865 Set Vref, RX VrefLevel [Byte0]: 46
1693 12:26:30.419985 [Byte1]: 46
1694 12:26:30.424317
1695 12:26:30.424402 Set Vref, RX VrefLevel [Byte0]: 47
1696 12:26:30.428084 [Byte1]: 47
1697 12:26:30.432480
1698 12:26:30.432567 Set Vref, RX VrefLevel [Byte0]: 48
1699 12:26:30.435678 [Byte1]: 48
1700 12:26:30.440111
1701 12:26:30.440195 Set Vref, RX VrefLevel [Byte0]: 49
1702 12:26:30.443206 [Byte1]: 49
1703 12:26:30.447874
1704 12:26:30.448014 Set Vref, RX VrefLevel [Byte0]: 50
1705 12:26:30.450754 [Byte1]: 50
1706 12:26:30.455116
1707 12:26:30.455262 Set Vref, RX VrefLevel [Byte0]: 51
1708 12:26:30.458582 [Byte1]: 51
1709 12:26:30.462681
1710 12:26:30.462779 Set Vref, RX VrefLevel [Byte0]: 52
1711 12:26:30.466266 [Byte1]: 52
1712 12:26:30.470760
1713 12:26:30.470845 Set Vref, RX VrefLevel [Byte0]: 53
1714 12:26:30.473658 [Byte1]: 53
1715 12:26:30.477977
1716 12:26:30.478061 Set Vref, RX VrefLevel [Byte0]: 54
1717 12:26:30.481677 [Byte1]: 54
1718 12:26:30.485755
1719 12:26:30.485839 Set Vref, RX VrefLevel [Byte0]: 55
1720 12:26:30.489418 [Byte1]: 55
1721 12:26:30.493484
1722 12:26:30.493569 Set Vref, RX VrefLevel [Byte0]: 56
1723 12:26:30.496485 [Byte1]: 56
1724 12:26:30.500958
1725 12:26:30.501042 Set Vref, RX VrefLevel [Byte0]: 57
1726 12:26:30.504676 [Byte1]: 57
1727 12:26:30.509032
1728 12:26:30.509116 Set Vref, RX VrefLevel [Byte0]: 58
1729 12:26:30.512236 [Byte1]: 58
1730 12:26:30.516531
1731 12:26:30.516615 Set Vref, RX VrefLevel [Byte0]: 59
1732 12:26:30.519679 [Byte1]: 59
1733 12:26:30.524060
1734 12:26:30.524146 Set Vref, RX VrefLevel [Byte0]: 60
1735 12:26:30.527083 [Byte1]: 60
1736 12:26:30.531497
1737 12:26:30.531586 Set Vref, RX VrefLevel [Byte0]: 61
1738 12:26:30.534758 [Byte1]: 61
1739 12:26:30.539124
1740 12:26:30.539210 Set Vref, RX VrefLevel [Byte0]: 62
1741 12:26:30.542849 [Byte1]: 62
1742 12:26:30.547184
1743 12:26:30.547270 Set Vref, RX VrefLevel [Byte0]: 63
1744 12:26:30.550235 [Byte1]: 63
1745 12:26:30.554624
1746 12:26:30.554711 Set Vref, RX VrefLevel [Byte0]: 64
1747 12:26:30.557765 [Byte1]: 64
1748 12:26:30.562410
1749 12:26:30.562496 Set Vref, RX VrefLevel [Byte0]: 65
1750 12:26:30.565428 [Byte1]: 65
1751 12:26:30.570155
1752 12:26:30.570241 Set Vref, RX VrefLevel [Byte0]: 66
1753 12:26:30.573147 [Byte1]: 66
1754 12:26:30.577295
1755 12:26:30.577381 Set Vref, RX VrefLevel [Byte0]: 67
1756 12:26:30.581017 [Byte1]: 67
1757 12:26:30.585285
1758 12:26:30.585371 Set Vref, RX VrefLevel [Byte0]: 68
1759 12:26:30.588259 [Byte1]: 68
1760 12:26:30.592960
1761 12:26:30.593057 Set Vref, RX VrefLevel [Byte0]: 69
1762 12:26:30.595878 [Byte1]: 69
1763 12:26:30.600560
1764 12:26:30.600645 Set Vref, RX VrefLevel [Byte0]: 70
1765 12:26:30.603647 [Byte1]: 70
1766 12:26:30.608233
1767 12:26:30.608318 Set Vref, RX VrefLevel [Byte0]: 71
1768 12:26:30.611149 [Byte1]: 71
1769 12:26:30.616115
1770 12:26:30.616205 Set Vref, RX VrefLevel [Byte0]: 72
1771 12:26:30.619269 [Byte1]: 72
1772 12:26:30.623608
1773 12:26:30.623693 Set Vref, RX VrefLevel [Byte0]: 73
1774 12:26:30.626754 [Byte1]: 73
1775 12:26:30.631204
1776 12:26:30.631290 Set Vref, RX VrefLevel [Byte0]: 74
1777 12:26:30.634327 [Byte1]: 74
1778 12:26:30.638611
1779 12:26:30.638741 Set Vref, RX VrefLevel [Byte0]: 75
1780 12:26:30.641823 [Byte1]: 75
1781 12:26:30.645996
1782 12:26:30.646125 Set Vref, RX VrefLevel [Byte0]: 76
1783 12:26:30.649728 [Byte1]: 76
1784 12:26:30.654159
1785 12:26:30.654286 Set Vref, RX VrefLevel [Byte0]: 77
1786 12:26:30.657335 [Byte1]: 77
1787 12:26:30.661686
1788 12:26:30.661812 Set Vref, RX VrefLevel [Byte0]: 78
1789 12:26:30.664903 [Byte1]: 78
1790 12:26:30.669005
1791 12:26:30.669130 Set Vref, RX VrefLevel [Byte0]: 79
1792 12:26:30.672593 [Byte1]: 79
1793 12:26:30.676981
1794 12:26:30.677107 Set Vref, RX VrefLevel [Byte0]: 80
1795 12:26:30.680085 [Byte1]: 80
1796 12:26:30.684434
1797 12:26:30.684559 Final RX Vref Byte 0 = 66 to rank0
1798 12:26:30.688075 Final RX Vref Byte 1 = 57 to rank0
1799 12:26:30.691050 Final RX Vref Byte 0 = 66 to rank1
1800 12:26:30.694285 Final RX Vref Byte 1 = 57 to rank1==
1801 12:26:30.697815 Dram Type= 6, Freq= 0, CH_1, rank 0
1802 12:26:30.704159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 12:26:30.704293 ==
1804 12:26:30.704412 DQS Delay:
1805 12:26:30.707693 DQS0 = 0, DQS1 = 0
1806 12:26:30.707819 DQM Delay:
1807 12:26:30.707933 DQM0 = 84, DQM1 = 74
1808 12:26:30.711271 DQ Delay:
1809 12:26:30.714501 DQ0 =92, DQ1 =76, DQ2 =76, DQ3 =80
1810 12:26:30.717586 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1811 12:26:30.721445 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1812 12:26:30.724541 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1813 12:26:30.724668
1814 12:26:30.724783
1815 12:26:30.731479 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fa, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1816 12:26:30.733993 CH1 RK0: MR19=605, MR18=26FA
1817 12:26:30.740810 CH1_RK0: MR19=0x605, MR18=0x26FA, DQSOSC=400, MR23=63, INC=92, DEC=61
1818 12:26:30.740942
1819 12:26:30.744607 ----->DramcWriteLeveling(PI) begin...
1820 12:26:30.744738 ==
1821 12:26:30.747664 Dram Type= 6, Freq= 0, CH_1, rank 1
1822 12:26:30.750793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 12:26:30.750921 ==
1824 12:26:30.753886 Write leveling (Byte 0): 27 => 27
1825 12:26:30.757777 Write leveling (Byte 1): 27 => 27
1826 12:26:30.760984 DramcWriteLeveling(PI) end<-----
1827 12:26:30.761113
1828 12:26:30.761228 ==
1829 12:26:30.764144 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 12:26:30.767815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 12:26:30.767944 ==
1832 12:26:30.770945 [Gating] SW mode calibration
1833 12:26:30.777269 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1834 12:26:30.784353 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1835 12:26:30.787293 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1836 12:26:30.790694 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1837 12:26:30.797879 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1838 12:26:30.800930 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:26:30.804011 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:26:30.810971 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:26:30.814403 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:26:30.817546 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:26:30.824292 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:26:30.827446 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:26:30.830561 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1846 12:26:30.837341 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1847 12:26:30.841068 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1848 12:26:30.844058 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:26:30.851101 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1850 12:26:30.854143 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:26:30.857903 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1852 12:26:30.864057 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1853 12:26:30.867170 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1854 12:26:30.870955 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:26:30.877183 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:26:30.880988 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:26:30.884219 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:26:30.887186 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:26:30.894233 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1860 12:26:30.897193 0 9 4 | B1->B0 | 2322 2828 | 1 0 | (0 0) (0 0)
1861 12:26:30.900818 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1862 12:26:30.907365 0 9 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1863 12:26:30.910417 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 12:26:30.913980 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1865 12:26:30.920519 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1866 12:26:30.924119 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1867 12:26:30.927232 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1868 12:26:30.933603 0 10 4 | B1->B0 | 3030 2e2e | 0 0 | (1 0) (0 0)
1869 12:26:30.937201 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1870 12:26:30.940512 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:26:30.947262 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:26:30.950317 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:26:30.954042 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1874 12:26:30.960336 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:26:30.964009 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:26:30.967111 0 11 4 | B1->B0 | 2f2f 3838 | 0 0 | (1 1) (1 1)
1877 12:26:30.974028 0 11 8 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1878 12:26:30.977055 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 12:26:30.980766 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 12:26:30.986997 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 12:26:30.990194 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 12:26:30.993820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 12:26:31.000703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1884 12:26:31.003554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1885 12:26:31.007255 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1886 12:26:31.010251 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 12:26:31.016909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 12:26:31.020593 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 12:26:31.023972 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 12:26:31.030703 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 12:26:31.033787 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 12:26:31.036909 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 12:26:31.043943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 12:26:31.047051 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 12:26:31.050754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 12:26:31.056945 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 12:26:31.060733 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 12:26:31.063914 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 12:26:31.070295 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 12:26:31.073534 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1901 12:26:31.077220 Total UI for P1: 0, mck2ui 16
1902 12:26:31.080281 best dqsien dly found for B0: ( 0, 14, 2)
1903 12:26:31.084056 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 12:26:31.087242 Total UI for P1: 0, mck2ui 16
1905 12:26:31.090350 best dqsien dly found for B1: ( 0, 14, 4)
1906 12:26:31.094139 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1907 12:26:31.097210 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1908 12:26:31.097303
1909 12:26:31.100229 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1910 12:26:31.107227 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1911 12:26:31.107325 [Gating] SW calibration Done
1912 12:26:31.107413 ==
1913 12:26:31.110133 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 12:26:31.116812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 12:26:31.116913 ==
1916 12:26:31.116985 RX Vref Scan: 0
1917 12:26:31.117049
1918 12:26:31.120334 RX Vref 0 -> 0, step: 1
1919 12:26:31.120458
1920 12:26:31.123906 RX Delay -130 -> 252, step: 16
1921 12:26:31.126919 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1922 12:26:31.130518 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1923 12:26:31.133466 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1924 12:26:31.140210 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1925 12:26:31.143977 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1926 12:26:31.147157 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1927 12:26:31.150283 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1928 12:26:31.154072 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1929 12:26:31.157261 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1930 12:26:31.164166 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1931 12:26:31.167196 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1932 12:26:31.170326 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1933 12:26:31.173982 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1934 12:26:31.177056 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1935 12:26:31.184020 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1936 12:26:31.187103 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1937 12:26:31.187217 ==
1938 12:26:31.190216 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 12:26:31.193866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 12:26:31.193968 ==
1941 12:26:31.197015 DQS Delay:
1942 12:26:31.197112 DQS0 = 0, DQS1 = 0
1943 12:26:31.197182 DQM Delay:
1944 12:26:31.200739 DQM0 = 80, DQM1 = 77
1945 12:26:31.200829 DQ Delay:
1946 12:26:31.203723 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1947 12:26:31.206770 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1948 12:26:31.210310 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1949 12:26:31.213819 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1950 12:26:31.213911
1951 12:26:31.213981
1952 12:26:31.214046 ==
1953 12:26:31.216752 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:26:31.223377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:26:31.223602 ==
1956 12:26:31.223742
1957 12:26:31.223869
1958 12:26:31.223986 TX Vref Scan disable
1959 12:26:31.227968 == TX Byte 0 ==
1960 12:26:31.230603 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1961 12:26:31.237179 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1962 12:26:31.237355 == TX Byte 1 ==
1963 12:26:31.240257 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1964 12:26:31.246884 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1965 12:26:31.247146 ==
1966 12:26:31.250755 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 12:26:31.253807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 12:26:31.254009 ==
1969 12:26:31.266227 TX Vref=22, minBit 1, minWin=27, winSum=441
1970 12:26:31.270017 TX Vref=24, minBit 1, minWin=27, winSum=444
1971 12:26:31.273094 TX Vref=26, minBit 9, minWin=27, winSum=445
1972 12:26:31.276148 TX Vref=28, minBit 12, minWin=27, winSum=449
1973 12:26:31.279379 TX Vref=30, minBit 12, minWin=27, winSum=450
1974 12:26:31.283158 TX Vref=32, minBit 0, minWin=28, winSum=451
1975 12:26:31.289992 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1976 12:26:31.290176
1977 12:26:31.293179 Final TX Range 1 Vref 32
1978 12:26:31.293347
1979 12:26:31.293498 ==
1980 12:26:31.296244 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:26:31.299409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:26:31.299570 ==
1983 12:26:31.299716
1984 12:26:31.303011
1985 12:26:31.303165 TX Vref Scan disable
1986 12:26:31.306095 == TX Byte 0 ==
1987 12:26:31.309828 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1988 12:26:31.313000 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1989 12:26:31.316182 == TX Byte 1 ==
1990 12:26:31.319778 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1991 12:26:31.322796 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1992 12:26:31.326140
1993 12:26:31.326316 [DATLAT]
1994 12:26:31.326465 Freq=800, CH1 RK1
1995 12:26:31.326615
1996 12:26:31.329829 DATLAT Default: 0xa
1997 12:26:31.330008 0, 0xFFFF, sum = 0
1998 12:26:31.344146 1, 0xFFFF, sum = 0
1999 12:26:31.344271 2, 0xFFFF, sum = 0
2000 12:26:31.344369 3, 0xFFFF, sum = 0
2001 12:26:31.344433 4, 0xFFFF, sum = 0
2002 12:26:31.344525 5, 0xFFFF, sum = 0
2003 12:26:31.344585 6, 0xFFFF, sum = 0
2004 12:26:31.344645 7, 0xFFFF, sum = 0
2005 12:26:31.346214 8, 0xFFFF, sum = 0
2006 12:26:31.346287 9, 0x0, sum = 1
2007 12:26:31.346349 10, 0x0, sum = 2
2008 12:26:31.349818 11, 0x0, sum = 3
2009 12:26:31.349905 12, 0x0, sum = 4
2010 12:26:31.352875 best_step = 10
2011 12:26:31.352960
2012 12:26:31.353027 ==
2013 12:26:31.356513 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 12:26:31.359686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 12:26:31.359854 ==
2016 12:26:31.363229 RX Vref Scan: 0
2017 12:26:31.363445
2018 12:26:31.363595 RX Vref 0 -> 0, step: 1
2019 12:26:31.363741
2020 12:26:31.366484 RX Delay -95 -> 252, step: 8
2021 12:26:31.373334 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2022 12:26:31.376392 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2023 12:26:31.379648 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2024 12:26:31.383152 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2025 12:26:31.386334 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2026 12:26:31.393207 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2027 12:26:31.396383 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2028 12:26:31.399459 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2029 12:26:31.403211 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2030 12:26:31.406280 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2031 12:26:31.413276 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2032 12:26:31.416353 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2033 12:26:31.419496 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2034 12:26:31.423214 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2035 12:26:31.426293 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2036 12:26:31.433079 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2037 12:26:31.433199 ==
2038 12:26:31.436253 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 12:26:31.439838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 12:26:31.439944 ==
2041 12:26:31.440016 DQS Delay:
2042 12:26:31.442686 DQS0 = 0, DQS1 = 0
2043 12:26:31.442805 DQM Delay:
2044 12:26:31.446227 DQM0 = 79, DQM1 = 75
2045 12:26:31.446342 DQ Delay:
2046 12:26:31.449844 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =76
2047 12:26:31.452782 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =72
2048 12:26:31.456219 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2049 12:26:31.459274 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2050 12:26:31.459394
2051 12:26:31.459463
2052 12:26:31.469339 [DQSOSCAuto] RK1, (LSB)MR18= 0x212c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2053 12:26:31.469485 CH1 RK1: MR19=606, MR18=212C
2054 12:26:31.476288 CH1_RK1: MR19=0x606, MR18=0x212C, DQSOSC=398, MR23=63, INC=93, DEC=62
2055 12:26:31.479339 [RxdqsGatingPostProcess] freq 800
2056 12:26:31.486233 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2057 12:26:31.489556 Pre-setting of DQS Precalculation
2058 12:26:31.493199 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2059 12:26:31.499424 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2060 12:26:31.506221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2061 12:26:31.506359
2062 12:26:31.506473
2063 12:26:31.509329 [Calibration Summary] 1600 Mbps
2064 12:26:31.513037 CH 0, Rank 0
2065 12:26:31.513168 SW Impedance : PASS
2066 12:26:31.516132 DUTY Scan : NO K
2067 12:26:31.519254 ZQ Calibration : PASS
2068 12:26:31.519388 Jitter Meter : NO K
2069 12:26:31.523084 CBT Training : PASS
2070 12:26:31.526156 Write leveling : PASS
2071 12:26:31.526283 RX DQS gating : PASS
2072 12:26:31.529267 RX DQ/DQS(RDDQC) : PASS
2073 12:26:31.529402 TX DQ/DQS : PASS
2074 12:26:31.532949 RX DATLAT : PASS
2075 12:26:31.535901 RX DQ/DQS(Engine): PASS
2076 12:26:31.536028 TX OE : NO K
2077 12:26:31.539365 All Pass.
2078 12:26:31.539492
2079 12:26:31.539607 CH 0, Rank 1
2080 12:26:31.542813 SW Impedance : PASS
2081 12:26:31.542942 DUTY Scan : NO K
2082 12:26:31.545831 ZQ Calibration : PASS
2083 12:26:31.549539 Jitter Meter : NO K
2084 12:26:31.549667 CBT Training : PASS
2085 12:26:31.552715 Write leveling : PASS
2086 12:26:31.556299 RX DQS gating : PASS
2087 12:26:31.556390 RX DQ/DQS(RDDQC) : PASS
2088 12:26:31.559192 TX DQ/DQS : PASS
2089 12:26:31.562753 RX DATLAT : PASS
2090 12:26:31.562831 RX DQ/DQS(Engine): PASS
2091 12:26:31.565798 TX OE : NO K
2092 12:26:31.565886 All Pass.
2093 12:26:31.565956
2094 12:26:31.569328 CH 1, Rank 0
2095 12:26:31.569415 SW Impedance : PASS
2096 12:26:31.572458 DUTY Scan : NO K
2097 12:26:31.576090 ZQ Calibration : PASS
2098 12:26:31.576185 Jitter Meter : NO K
2099 12:26:31.579206 CBT Training : PASS
2100 12:26:31.582929 Write leveling : PASS
2101 12:26:31.583015 RX DQS gating : PASS
2102 12:26:31.586042 RX DQ/DQS(RDDQC) : PASS
2103 12:26:31.586138 TX DQ/DQS : PASS
2104 12:26:31.589355 RX DATLAT : PASS
2105 12:26:31.593024 RX DQ/DQS(Engine): PASS
2106 12:26:31.593112 TX OE : NO K
2107 12:26:31.596150 All Pass.
2108 12:26:31.596236
2109 12:26:31.596304 CH 1, Rank 1
2110 12:26:31.599330 SW Impedance : PASS
2111 12:26:31.599430 DUTY Scan : NO K
2112 12:26:31.602988 ZQ Calibration : PASS
2113 12:26:31.606115 Jitter Meter : NO K
2114 12:26:31.606204 CBT Training : PASS
2115 12:26:31.609836 Write leveling : PASS
2116 12:26:31.612869 RX DQS gating : PASS
2117 12:26:31.612958 RX DQ/DQS(RDDQC) : PASS
2118 12:26:31.615951 TX DQ/DQS : PASS
2119 12:26:31.619764 RX DATLAT : PASS
2120 12:26:31.619851 RX DQ/DQS(Engine): PASS
2121 12:26:31.622973 TX OE : NO K
2122 12:26:31.623101 All Pass.
2123 12:26:31.623171
2124 12:26:31.626113 DramC Write-DBI off
2125 12:26:31.629243 PER_BANK_REFRESH: Hybrid Mode
2126 12:26:31.629331 TX_TRACKING: ON
2127 12:26:31.632950 [GetDramInforAfterCalByMRR] Vendor 6.
2128 12:26:31.636109 [GetDramInforAfterCalByMRR] Revision 606.
2129 12:26:31.639216 [GetDramInforAfterCalByMRR] Revision 2 0.
2130 12:26:31.642891 MR0 0x3b3b
2131 12:26:31.643005 MR8 0x5151
2132 12:26:31.646387 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 12:26:31.646473
2134 12:26:31.646540 MR0 0x3b3b
2135 12:26:31.648959 MR8 0x5151
2136 12:26:31.652725 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 12:26:31.652829
2138 12:26:31.659080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2139 12:26:31.666126 [FAST_K] Save calibration result to emmc
2140 12:26:31.669058 [FAST_K] Save calibration result to emmc
2141 12:26:31.669144 dram_init: config_dvfs: 1
2142 12:26:31.672665 dramc_set_vcore_voltage set vcore to 662500
2143 12:26:31.675823 Read voltage for 1200, 2
2144 12:26:31.675909 Vio18 = 0
2145 12:26:31.679482 Vcore = 662500
2146 12:26:31.679568 Vdram = 0
2147 12:26:31.679636 Vddq = 0
2148 12:26:31.682474 Vmddr = 0
2149 12:26:31.686261 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2150 12:26:31.693004 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2151 12:26:31.693091 MEM_TYPE=3, freq_sel=15
2152 12:26:31.696257 sv_algorithm_assistance_LP4_1600
2153 12:26:31.702408 ============ PULL DRAM RESETB DOWN ============
2154 12:26:31.706139 ========== PULL DRAM RESETB DOWN end =========
2155 12:26:31.709286 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2156 12:26:31.712369 ===================================
2157 12:26:31.716166 LPDDR4 DRAM CONFIGURATION
2158 12:26:31.719093 ===================================
2159 12:26:31.722779 EX_ROW_EN[0] = 0x0
2160 12:26:31.722862 EX_ROW_EN[1] = 0x0
2161 12:26:31.725847 LP4Y_EN = 0x0
2162 12:26:31.725931 WORK_FSP = 0x0
2163 12:26:31.728974 WL = 0x4
2164 12:26:31.729060 RL = 0x4
2165 12:26:31.732691 BL = 0x2
2166 12:26:31.732801 RPST = 0x0
2167 12:26:31.735881 RD_PRE = 0x0
2168 12:26:31.735964 WR_PRE = 0x1
2169 12:26:31.738887 WR_PST = 0x0
2170 12:26:31.738997 DBI_WR = 0x0
2171 12:26:31.742759 DBI_RD = 0x0
2172 12:26:31.742873 OTF = 0x1
2173 12:26:31.745885 ===================================
2174 12:26:31.748918 ===================================
2175 12:26:31.752351 ANA top config
2176 12:26:31.755849 ===================================
2177 12:26:31.755933 DLL_ASYNC_EN = 0
2178 12:26:31.759322 ALL_SLAVE_EN = 0
2179 12:26:31.763084 NEW_RANK_MODE = 1
2180 12:26:31.766016 DLL_IDLE_MODE = 1
2181 12:26:31.769505 LP45_APHY_COMB_EN = 1
2182 12:26:31.769589 TX_ODT_DIS = 1
2183 12:26:31.772465 NEW_8X_MODE = 1
2184 12:26:31.775876 ===================================
2185 12:26:31.779325 ===================================
2186 12:26:31.782390 data_rate = 2400
2187 12:26:31.785918 CKR = 1
2188 12:26:31.788986 DQ_P2S_RATIO = 8
2189 12:26:31.792783 ===================================
2190 12:26:31.792868 CA_P2S_RATIO = 8
2191 12:26:31.796172 DQ_CA_OPEN = 0
2192 12:26:31.799019 DQ_SEMI_OPEN = 0
2193 12:26:31.802615 CA_SEMI_OPEN = 0
2194 12:26:31.805627 CA_FULL_RATE = 0
2195 12:26:31.808747 DQ_CKDIV4_EN = 0
2196 12:26:31.808867 CA_CKDIV4_EN = 0
2197 12:26:31.812510 CA_PREDIV_EN = 0
2198 12:26:31.815754 PH8_DLY = 17
2199 12:26:31.818988 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2200 12:26:31.822648 DQ_AAMCK_DIV = 4
2201 12:26:31.825747 CA_AAMCK_DIV = 4
2202 12:26:31.825858 CA_ADMCK_DIV = 4
2203 12:26:31.828822 DQ_TRACK_CA_EN = 0
2204 12:26:31.832531 CA_PICK = 1200
2205 12:26:31.835559 CA_MCKIO = 1200
2206 12:26:31.839224 MCKIO_SEMI = 0
2207 12:26:31.842369 PLL_FREQ = 2366
2208 12:26:31.845388 DQ_UI_PI_RATIO = 32
2209 12:26:31.849112 CA_UI_PI_RATIO = 0
2210 12:26:31.849218 ===================================
2211 12:26:31.852203 ===================================
2212 12:26:31.856063 memory_type:LPDDR4
2213 12:26:31.858924 GP_NUM : 10
2214 12:26:31.859027 SRAM_EN : 1
2215 12:26:31.862474 MD32_EN : 0
2216 12:26:31.866073 ===================================
2217 12:26:31.868809 [ANA_INIT] >>>>>>>>>>>>>>
2218 12:26:31.872474 <<<<<< [CONFIGURE PHASE]: ANA_TX
2219 12:26:31.875677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2220 12:26:31.879155 ===================================
2221 12:26:31.879245 data_rate = 2400,PCW = 0X5b00
2222 12:26:31.882780 ===================================
2223 12:26:31.885620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2224 12:26:31.892494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 12:26:31.898927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2226 12:26:31.902078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2227 12:26:31.905850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2228 12:26:31.908983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2229 12:26:31.912050 [ANA_INIT] flow start
2230 12:26:31.912136 [ANA_INIT] PLL >>>>>>>>
2231 12:26:31.915696 [ANA_INIT] PLL <<<<<<<<
2232 12:26:31.918905 [ANA_INIT] MIDPI >>>>>>>>
2233 12:26:31.922025 [ANA_INIT] MIDPI <<<<<<<<
2234 12:26:31.922111 [ANA_INIT] DLL >>>>>>>>
2235 12:26:31.925751 [ANA_INIT] DLL <<<<<<<<
2236 12:26:31.928810 [ANA_INIT] flow end
2237 12:26:31.931983 ============ LP4 DIFF to SE enter ============
2238 12:26:31.935664 ============ LP4 DIFF to SE exit ============
2239 12:26:31.938917 [ANA_INIT] <<<<<<<<<<<<<
2240 12:26:31.942011 [Flow] Enable top DCM control >>>>>
2241 12:26:31.945692 [Flow] Enable top DCM control <<<<<
2242 12:26:31.948916 Enable DLL master slave shuffle
2243 12:26:31.952769 ==============================================================
2244 12:26:31.955892 Gating Mode config
2245 12:26:31.958917 ==============================================================
2246 12:26:31.962033 Config description:
2247 12:26:31.972410 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2248 12:26:31.978954 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2249 12:26:31.982398 SELPH_MODE 0: By rank 1: By Phase
2250 12:26:31.988539 ==============================================================
2251 12:26:31.992125 GAT_TRACK_EN = 1
2252 12:26:31.995736 RX_GATING_MODE = 2
2253 12:26:31.998958 RX_GATING_TRACK_MODE = 2
2254 12:26:32.001818 SELPH_MODE = 1
2255 12:26:32.005151 PICG_EARLY_EN = 1
2256 12:26:32.005238 VALID_LAT_VALUE = 1
2257 12:26:32.012275 ==============================================================
2258 12:26:32.015318 Enter into Gating configuration >>>>
2259 12:26:32.018975 Exit from Gating configuration <<<<
2260 12:26:32.022097 Enter into DVFS_PRE_config >>>>>
2261 12:26:32.032058 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2262 12:26:32.035202 Exit from DVFS_PRE_config <<<<<
2263 12:26:32.038899 Enter into PICG configuration >>>>
2264 12:26:32.041991 Exit from PICG configuration <<<<
2265 12:26:32.045675 [RX_INPUT] configuration >>>>>
2266 12:26:32.048921 [RX_INPUT] configuration <<<<<
2267 12:26:32.051922 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2268 12:26:32.058806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2269 12:26:32.065557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2270 12:26:32.071747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2271 12:26:32.078590 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2272 12:26:32.082014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2273 12:26:32.088989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2274 12:26:32.092075 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2275 12:26:32.095103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2276 12:26:32.098611 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2277 12:26:32.105104 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2278 12:26:32.108550 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 12:26:32.112037 ===================================
2280 12:26:32.115589 LPDDR4 DRAM CONFIGURATION
2281 12:26:32.118451 ===================================
2282 12:26:32.118542 EX_ROW_EN[0] = 0x0
2283 12:26:32.121973 EX_ROW_EN[1] = 0x0
2284 12:26:32.122051 LP4Y_EN = 0x0
2285 12:26:32.125181 WORK_FSP = 0x0
2286 12:26:32.125256 WL = 0x4
2287 12:26:32.128849 RL = 0x4
2288 12:26:32.128957 BL = 0x2
2289 12:26:32.132058 RPST = 0x0
2290 12:26:32.132139 RD_PRE = 0x0
2291 12:26:32.135174 WR_PRE = 0x1
2292 12:26:32.135276 WR_PST = 0x0
2293 12:26:32.138268 DBI_WR = 0x0
2294 12:26:32.141991 DBI_RD = 0x0
2295 12:26:32.142066 OTF = 0x1
2296 12:26:32.145160 ===================================
2297 12:26:32.148218 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2298 12:26:32.151911 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2299 12:26:32.158214 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 12:26:32.161974 ===================================
2301 12:26:32.165086 LPDDR4 DRAM CONFIGURATION
2302 12:26:32.168757 ===================================
2303 12:26:32.168832 EX_ROW_EN[0] = 0x10
2304 12:26:32.171882 EX_ROW_EN[1] = 0x0
2305 12:26:32.171955 LP4Y_EN = 0x0
2306 12:26:32.174992 WORK_FSP = 0x0
2307 12:26:32.175064 WL = 0x4
2308 12:26:32.178890 RL = 0x4
2309 12:26:32.178961 BL = 0x2
2310 12:26:32.181817 RPST = 0x0
2311 12:26:32.181887 RD_PRE = 0x0
2312 12:26:32.184948 WR_PRE = 0x1
2313 12:26:32.185035 WR_PST = 0x0
2314 12:26:32.188507 DBI_WR = 0x0
2315 12:26:32.188592 DBI_RD = 0x0
2316 12:26:32.191864 OTF = 0x1
2317 12:26:32.194879 ===================================
2318 12:26:32.201631 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2319 12:26:32.201718 ==
2320 12:26:32.205159 Dram Type= 6, Freq= 0, CH_0, rank 0
2321 12:26:32.208704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2322 12:26:32.208817 ==
2323 12:26:32.211574 [Duty_Offset_Calibration]
2324 12:26:32.211669 B0:2 B1:-1 CA:1
2325 12:26:32.211739
2326 12:26:32.215233 [DutyScan_Calibration_Flow] k_type=0
2327 12:26:32.225160
2328 12:26:32.225246 ==CLK 0==
2329 12:26:32.227982 Final CLK duty delay cell = -4
2330 12:26:32.231539 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2331 12:26:32.234593 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2332 12:26:32.238533 [-4] AVG Duty = 4953%(X100)
2333 12:26:32.238613
2334 12:26:32.241619 CH0 CLK Duty spec in!! Max-Min= 156%
2335 12:26:32.244786 [DutyScan_Calibration_Flow] ====Done====
2336 12:26:32.244865
2337 12:26:32.247971 [DutyScan_Calibration_Flow] k_type=1
2338 12:26:32.263541
2339 12:26:32.263629 ==DQS 0 ==
2340 12:26:32.266844 Final DQS duty delay cell = 0
2341 12:26:32.270589 [0] MAX Duty = 5125%(X100), DQS PI = 48
2342 12:26:32.273801 [0] MIN Duty = 5000%(X100), DQS PI = 14
2343 12:26:32.273914 [0] AVG Duty = 5062%(X100)
2344 12:26:32.276848
2345 12:26:32.276929 ==DQS 1 ==
2346 12:26:32.280527 Final DQS duty delay cell = -4
2347 12:26:32.283721 [-4] MAX Duty = 5124%(X100), DQS PI = 16
2348 12:26:32.286847 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2349 12:26:32.290602 [-4] AVG Duty = 5062%(X100)
2350 12:26:32.290689
2351 12:26:32.293843 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2352 12:26:32.293920
2353 12:26:32.297098 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2354 12:26:32.300322 [DutyScan_Calibration_Flow] ====Done====
2355 12:26:32.300408
2356 12:26:32.304116 [DutyScan_Calibration_Flow] k_type=3
2357 12:26:32.320712
2358 12:26:32.320832 ==DQM 0 ==
2359 12:26:32.324016 Final DQM duty delay cell = 0
2360 12:26:32.327477 [0] MAX Duty = 5000%(X100), DQS PI = 54
2361 12:26:32.330879 [0] MIN Duty = 4907%(X100), DQS PI = 0
2362 12:26:32.330994 [0] AVG Duty = 4953%(X100)
2363 12:26:32.331094
2364 12:26:32.334311 ==DQM 1 ==
2365 12:26:32.337269 Final DQM duty delay cell = 0
2366 12:26:32.340864 [0] MAX Duty = 5156%(X100), DQS PI = 62
2367 12:26:32.344034 [0] MIN Duty = 4969%(X100), DQS PI = 10
2368 12:26:32.344145 [0] AVG Duty = 5062%(X100)
2369 12:26:32.344240
2370 12:26:32.347569 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2371 12:26:32.350684
2372 12:26:32.354413 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2373 12:26:32.357544 [DutyScan_Calibration_Flow] ====Done====
2374 12:26:32.357653
2375 12:26:32.360804 [DutyScan_Calibration_Flow] k_type=2
2376 12:26:32.376172
2377 12:26:32.376285 ==DQ 0 ==
2378 12:26:32.379268 Final DQ duty delay cell = -4
2379 12:26:32.383140 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2380 12:26:32.386213 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2381 12:26:32.389448 [-4] AVG Duty = 4953%(X100)
2382 12:26:32.389557
2383 12:26:32.389653 ==DQ 1 ==
2384 12:26:32.393161 Final DQ duty delay cell = 0
2385 12:26:32.396233 [0] MAX Duty = 5031%(X100), DQS PI = 18
2386 12:26:32.399323 [0] MIN Duty = 4907%(X100), DQS PI = 46
2387 12:26:32.403094 [0] AVG Duty = 4969%(X100)
2388 12:26:32.403205
2389 12:26:32.406179 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2390 12:26:32.406288
2391 12:26:32.409632 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2392 12:26:32.412847 [DutyScan_Calibration_Flow] ====Done====
2393 12:26:32.412958 ==
2394 12:26:32.416358 Dram Type= 6, Freq= 0, CH_1, rank 0
2395 12:26:32.419781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2396 12:26:32.419871 ==
2397 12:26:32.422768 [Duty_Offset_Calibration]
2398 12:26:32.422855 B0:1 B1:1 CA:2
2399 12:26:32.422925
2400 12:26:32.426446 [DutyScan_Calibration_Flow] k_type=0
2401 12:26:32.436782
2402 12:26:32.436878 ==CLK 0==
2403 12:26:32.440265 Final CLK duty delay cell = 0
2404 12:26:32.443341 [0] MAX Duty = 5125%(X100), DQS PI = 24
2405 12:26:32.446687 [0] MIN Duty = 4969%(X100), DQS PI = 40
2406 12:26:32.446800 [0] AVG Duty = 5047%(X100)
2407 12:26:32.450087
2408 12:26:32.450203 CH1 CLK Duty spec in!! Max-Min= 156%
2409 12:26:32.456728 [DutyScan_Calibration_Flow] ====Done====
2410 12:26:32.456843
2411 12:26:32.459835 [DutyScan_Calibration_Flow] k_type=1
2412 12:26:32.475631
2413 12:26:32.475747 ==DQS 0 ==
2414 12:26:32.479370 Final DQS duty delay cell = 0
2415 12:26:32.482483 [0] MAX Duty = 5031%(X100), DQS PI = 20
2416 12:26:32.485709 [0] MIN Duty = 4813%(X100), DQS PI = 50
2417 12:26:32.489436 [0] AVG Duty = 4922%(X100)
2418 12:26:32.489546
2419 12:26:32.489638 ==DQS 1 ==
2420 12:26:32.492518 Final DQS duty delay cell = 0
2421 12:26:32.496303 [0] MAX Duty = 5062%(X100), DQS PI = 36
2422 12:26:32.499473 [0] MIN Duty = 4907%(X100), DQS PI = 16
2423 12:26:32.499584 [0] AVG Duty = 4984%(X100)
2424 12:26:32.502585
2425 12:26:32.506297 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2426 12:26:32.506409
2427 12:26:32.509424 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2428 12:26:32.512539 [DutyScan_Calibration_Flow] ====Done====
2429 12:26:32.512649
2430 12:26:32.516261 [DutyScan_Calibration_Flow] k_type=3
2431 12:26:32.532958
2432 12:26:32.533090 ==DQM 0 ==
2433 12:26:32.535853 Final DQM duty delay cell = 0
2434 12:26:32.539417 [0] MAX Duty = 5093%(X100), DQS PI = 18
2435 12:26:32.542876 [0] MIN Duty = 4907%(X100), DQS PI = 48
2436 12:26:32.542990 [0] AVG Duty = 5000%(X100)
2437 12:26:32.545986
2438 12:26:32.546101 ==DQM 1 ==
2439 12:26:32.549464 Final DQM duty delay cell = 0
2440 12:26:32.552450 [0] MAX Duty = 5156%(X100), DQS PI = 62
2441 12:26:32.556025 [0] MIN Duty = 4938%(X100), DQS PI = 22
2442 12:26:32.559394 [0] AVG Duty = 5047%(X100)
2443 12:26:32.559507
2444 12:26:32.562950 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2445 12:26:32.563061
2446 12:26:32.566122 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2447 12:26:32.569347 [DutyScan_Calibration_Flow] ====Done====
2448 12:26:32.569435
2449 12:26:32.573001 [DutyScan_Calibration_Flow] k_type=2
2450 12:26:32.589253
2451 12:26:32.589341 ==DQ 0 ==
2452 12:26:32.592319 Final DQ duty delay cell = 0
2453 12:26:32.596171 [0] MAX Duty = 5124%(X100), DQS PI = 18
2454 12:26:32.599183 [0] MIN Duty = 4969%(X100), DQS PI = 12
2455 12:26:32.599296 [0] AVG Duty = 5046%(X100)
2456 12:26:32.599392
2457 12:26:32.602430 ==DQ 1 ==
2458 12:26:32.605659 Final DQ duty delay cell = 0
2459 12:26:32.609373 [0] MAX Duty = 5093%(X100), DQS PI = 8
2460 12:26:32.612598 [0] MIN Duty = 5031%(X100), DQS PI = 2
2461 12:26:32.612685 [0] AVG Duty = 5062%(X100)
2462 12:26:32.612753
2463 12:26:32.615704 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2464 12:26:32.615789
2465 12:26:32.619534 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2466 12:26:32.622685 [DutyScan_Calibration_Flow] ====Done====
2467 12:26:32.627857 nWR fixed to 30
2468 12:26:32.631415 [ModeRegInit_LP4] CH0 RK0
2469 12:26:32.631509 [ModeRegInit_LP4] CH0 RK1
2470 12:26:32.634841 [ModeRegInit_LP4] CH1 RK0
2471 12:26:32.638105 [ModeRegInit_LP4] CH1 RK1
2472 12:26:32.638191 match AC timing 7
2473 12:26:32.644621 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2474 12:26:32.648224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2475 12:26:32.651308 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2476 12:26:32.657966 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2477 12:26:32.661494 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2478 12:26:32.661604 ==
2479 12:26:32.664813 Dram Type= 6, Freq= 0, CH_0, rank 0
2480 12:26:32.667724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 12:26:32.667808 ==
2482 12:26:32.674808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 12:26:32.681219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 12:26:32.689256 [CA 0] Center 40 (10~71) winsize 62
2485 12:26:32.692477 [CA 1] Center 39 (9~70) winsize 62
2486 12:26:32.695627 [CA 2] Center 36 (6~67) winsize 62
2487 12:26:32.698731 [CA 3] Center 35 (5~66) winsize 62
2488 12:26:32.702579 [CA 4] Center 35 (5~65) winsize 61
2489 12:26:32.705560 [CA 5] Center 34 (4~65) winsize 62
2490 12:26:32.705648
2491 12:26:32.708785 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2492 12:26:32.708877
2493 12:26:32.712469 [CATrainingPosCal] consider 1 rank data
2494 12:26:32.715548 u2DelayCellTimex100 = 270/100 ps
2495 12:26:32.719302 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2496 12:26:32.722476 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2497 12:26:32.729285 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2498 12:26:32.732503 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2499 12:26:32.735553 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2500 12:26:32.739213 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2501 12:26:32.739300
2502 12:26:32.742749 CA PerBit enable=1, Macro0, CA PI delay=34
2503 12:26:32.742837
2504 12:26:32.745677 [CBTSetCACLKResult] CA Dly = 34
2505 12:26:32.745768 CS Dly: 7 (0~38)
2506 12:26:32.745838 ==
2507 12:26:32.749103 Dram Type= 6, Freq= 0, CH_0, rank 1
2508 12:26:32.755626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 12:26:32.755748 ==
2510 12:26:32.759171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 12:26:32.765601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2512 12:26:32.774971 [CA 0] Center 39 (9~70) winsize 62
2513 12:26:32.778569 [CA 1] Center 40 (10~70) winsize 61
2514 12:26:32.781568 [CA 2] Center 36 (6~67) winsize 62
2515 12:26:32.784716 [CA 3] Center 36 (5~67) winsize 63
2516 12:26:32.788430 [CA 4] Center 34 (4~65) winsize 62
2517 12:26:32.791540 [CA 5] Center 34 (4~64) winsize 61
2518 12:26:32.791620
2519 12:26:32.794655 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2520 12:26:32.794742
2521 12:26:32.798425 [CATrainingPosCal] consider 2 rank data
2522 12:26:32.801506 u2DelayCellTimex100 = 270/100 ps
2523 12:26:32.804757 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2524 12:26:32.811578 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2525 12:26:32.814660 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2526 12:26:32.818400 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2527 12:26:32.821630 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2528 12:26:32.824817 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2529 12:26:32.824940
2530 12:26:32.828565 CA PerBit enable=1, Macro0, CA PI delay=34
2531 12:26:32.828686
2532 12:26:32.831755 [CBTSetCACLKResult] CA Dly = 34
2533 12:26:32.831889 CS Dly: 8 (0~41)
2534 12:26:32.832015
2535 12:26:32.838452 ----->DramcWriteLeveling(PI) begin...
2536 12:26:32.838584 ==
2537 12:26:32.841609 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 12:26:32.845139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 12:26:32.845271 ==
2540 12:26:32.848304 Write leveling (Byte 0): 31 => 31
2541 12:26:32.851435 Write leveling (Byte 1): 28 => 28
2542 12:26:32.854997 DramcWriteLeveling(PI) end<-----
2543 12:26:32.855127
2544 12:26:32.855242 ==
2545 12:26:32.857926 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 12:26:32.861912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 12:26:32.862042 ==
2548 12:26:32.864869 [Gating] SW mode calibration
2549 12:26:32.871853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2550 12:26:32.878228 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2551 12:26:32.881662 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 12:26:32.885337 0 15 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2553 12:26:32.888312 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2554 12:26:32.895118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 12:26:32.898219 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 12:26:32.902001 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 12:26:32.908305 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 12:26:32.912016 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2559 12:26:32.915089 1 0 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2560 12:26:32.921990 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2561 12:26:32.925079 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 12:26:32.928229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 12:26:32.934915 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 12:26:32.938048 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 12:26:32.941794 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 12:26:32.948497 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 12:26:32.951490 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2568 12:26:32.954695 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2569 12:26:32.961475 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 12:26:32.965072 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 12:26:32.967995 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 12:26:32.975014 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 12:26:32.977982 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 12:26:32.981530 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 12:26:32.985059 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2576 12:26:32.991618 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:26:32.994603 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:26:32.997997 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 12:26:33.004716 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 12:26:33.008385 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 12:26:33.011569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 12:26:33.018425 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 12:26:33.021627 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 12:26:33.024727 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 12:26:33.031631 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 12:26:33.034751 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 12:26:33.038457 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 12:26:33.044589 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 12:26:33.047832 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 12:26:33.051318 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 12:26:33.058181 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2592 12:26:33.061280 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 12:26:33.065131 Total UI for P1: 0, mck2ui 16
2594 12:26:33.068153 best dqsien dly found for B0: ( 1, 4, 0)
2595 12:26:33.071225 Total UI for P1: 0, mck2ui 16
2596 12:26:33.074830 best dqsien dly found for B1: ( 1, 4, 0)
2597 12:26:33.077821 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2598 12:26:33.081302 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2599 12:26:33.081388
2600 12:26:33.084789 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2601 12:26:33.087826 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2602 12:26:33.091464 [Gating] SW calibration Done
2603 12:26:33.091549 ==
2604 12:26:33.094463 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 12:26:33.098032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 12:26:33.098140 ==
2607 12:26:33.101575 RX Vref Scan: 0
2608 12:26:33.101659
2609 12:26:33.101745 RX Vref 0 -> 0, step: 1
2610 12:26:33.105052
2611 12:26:33.105139 RX Delay -40 -> 252, step: 8
2612 12:26:33.111783 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2613 12:26:33.114828 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2614 12:26:33.117883 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2615 12:26:33.121639 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2616 12:26:33.124684 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2617 12:26:33.127820 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2618 12:26:33.134757 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2619 12:26:33.137810 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2620 12:26:33.141465 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2621 12:26:33.144566 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2622 12:26:33.148407 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2623 12:26:33.154711 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2624 12:26:33.158217 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2625 12:26:33.161193 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2626 12:26:33.164393 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2627 12:26:33.168172 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2628 12:26:33.171161 ==
2629 12:26:33.174789 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 12:26:33.178050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 12:26:33.178142 ==
2632 12:26:33.178212 DQS Delay:
2633 12:26:33.181132 DQS0 = 0, DQS1 = 0
2634 12:26:33.181221 DQM Delay:
2635 12:26:33.184978 DQM0 = 115, DQM1 = 107
2636 12:26:33.185106 DQ Delay:
2637 12:26:33.187741 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2638 12:26:33.191505 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2639 12:26:33.194721 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2640 12:26:33.197708 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2641 12:26:33.197818
2642 12:26:33.197891
2643 12:26:33.197955 ==
2644 12:26:33.201451 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 12:26:33.208204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 12:26:33.208313 ==
2647 12:26:33.208418
2648 12:26:33.208524
2649 12:26:33.208627 TX Vref Scan disable
2650 12:26:33.210995 == TX Byte 0 ==
2651 12:26:33.214544 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2652 12:26:33.218110 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2653 12:26:33.221415 == TX Byte 1 ==
2654 12:26:33.224554 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2655 12:26:33.231528 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2656 12:26:33.231674 ==
2657 12:26:33.234647 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 12:26:33.237707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 12:26:33.237830 ==
2660 12:26:33.249604 TX Vref=22, minBit 1, minWin=24, winSum=417
2661 12:26:33.252667 TX Vref=24, minBit 5, minWin=25, winSum=425
2662 12:26:33.255841 TX Vref=26, minBit 1, minWin=25, winSum=429
2663 12:26:33.259573 TX Vref=28, minBit 0, minWin=26, winSum=436
2664 12:26:33.262603 TX Vref=30, minBit 7, minWin=26, winSum=436
2665 12:26:33.265764 TX Vref=32, minBit 1, minWin=26, winSum=436
2666 12:26:33.272630 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 28
2667 12:26:33.272723
2668 12:26:33.276358 Final TX Range 1 Vref 28
2669 12:26:33.276453
2670 12:26:33.276542 ==
2671 12:26:33.279510 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 12:26:33.282578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 12:26:33.282672 ==
2674 12:26:33.282761
2675 12:26:33.282865
2676 12:26:33.286182 TX Vref Scan disable
2677 12:26:33.289338 == TX Byte 0 ==
2678 12:26:33.292492 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2679 12:26:33.296106 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2680 12:26:33.299607 == TX Byte 1 ==
2681 12:26:33.302532 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2682 12:26:33.306012 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2683 12:26:33.306127
2684 12:26:33.309434 [DATLAT]
2685 12:26:33.309522 Freq=1200, CH0 RK0
2686 12:26:33.309611
2687 12:26:33.313206 DATLAT Default: 0xd
2688 12:26:33.313316 0, 0xFFFF, sum = 0
2689 12:26:33.316167 1, 0xFFFF, sum = 0
2690 12:26:33.316277 2, 0xFFFF, sum = 0
2691 12:26:33.319589 3, 0xFFFF, sum = 0
2692 12:26:33.319685 4, 0xFFFF, sum = 0
2693 12:26:33.322740 5, 0xFFFF, sum = 0
2694 12:26:33.322828 6, 0xFFFF, sum = 0
2695 12:26:33.326295 7, 0xFFFF, sum = 0
2696 12:26:33.326384 8, 0xFFFF, sum = 0
2697 12:26:33.329365 9, 0xFFFF, sum = 0
2698 12:26:33.332507 10, 0xFFFF, sum = 0
2699 12:26:33.332626 11, 0xFFFF, sum = 0
2700 12:26:33.336353 12, 0x0, sum = 1
2701 12:26:33.336444 13, 0x0, sum = 2
2702 12:26:33.336520 14, 0x0, sum = 3
2703 12:26:33.339313 15, 0x0, sum = 4
2704 12:26:33.339402 best_step = 13
2705 12:26:33.339472
2706 12:26:33.339537 ==
2707 12:26:33.342439 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 12:26:33.349226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 12:26:33.349362 ==
2710 12:26:33.349480 RX Vref Scan: 1
2711 12:26:33.349591
2712 12:26:33.352895 Set Vref Range= 32 -> 127
2713 12:26:33.353021
2714 12:26:33.355977 RX Vref 32 -> 127, step: 1
2715 12:26:33.356101
2716 12:26:33.359579 RX Delay -21 -> 252, step: 4
2717 12:26:33.359705
2718 12:26:33.362602 Set Vref, RX VrefLevel [Byte0]: 32
2719 12:26:33.366263 [Byte1]: 32
2720 12:26:33.366385
2721 12:26:33.369338 Set Vref, RX VrefLevel [Byte0]: 33
2722 12:26:33.372402 [Byte1]: 33
2723 12:26:33.372537
2724 12:26:33.376205 Set Vref, RX VrefLevel [Byte0]: 34
2725 12:26:33.379208 [Byte1]: 34
2726 12:26:33.383897
2727 12:26:33.384070 Set Vref, RX VrefLevel [Byte0]: 35
2728 12:26:33.386898 [Byte1]: 35
2729 12:26:33.391293
2730 12:26:33.391441 Set Vref, RX VrefLevel [Byte0]: 36
2731 12:26:33.398089 [Byte1]: 36
2732 12:26:33.398243
2733 12:26:33.401093 Set Vref, RX VrefLevel [Byte0]: 37
2734 12:26:33.404315 [Byte1]: 37
2735 12:26:33.404463
2736 12:26:33.407525 Set Vref, RX VrefLevel [Byte0]: 38
2737 12:26:33.411296 [Byte1]: 38
2738 12:26:33.415531
2739 12:26:33.415688 Set Vref, RX VrefLevel [Byte0]: 39
2740 12:26:33.418747 [Byte1]: 39
2741 12:26:33.422743
2742 12:26:33.422845 Set Vref, RX VrefLevel [Byte0]: 40
2743 12:26:33.426238 [Byte1]: 40
2744 12:26:33.430787
2745 12:26:33.430923 Set Vref, RX VrefLevel [Byte0]: 41
2746 12:26:33.434518 [Byte1]: 41
2747 12:26:33.439122
2748 12:26:33.439243 Set Vref, RX VrefLevel [Byte0]: 42
2749 12:26:33.442312 [Byte1]: 42
2750 12:26:33.446526
2751 12:26:33.446612 Set Vref, RX VrefLevel [Byte0]: 43
2752 12:26:33.450171 [Byte1]: 43
2753 12:26:33.454527
2754 12:26:33.454620 Set Vref, RX VrefLevel [Byte0]: 44
2755 12:26:33.458326 [Byte1]: 44
2756 12:26:33.462602
2757 12:26:33.462704 Set Vref, RX VrefLevel [Byte0]: 45
2758 12:26:33.465693 [Byte1]: 45
2759 12:26:33.470524
2760 12:26:33.470618 Set Vref, RX VrefLevel [Byte0]: 46
2761 12:26:33.474302 [Byte1]: 46
2762 12:26:33.478623
2763 12:26:33.478723 Set Vref, RX VrefLevel [Byte0]: 47
2764 12:26:33.481825 [Byte1]: 47
2765 12:26:33.486278
2766 12:26:33.486373 Set Vref, RX VrefLevel [Byte0]: 48
2767 12:26:33.490018 [Byte1]: 48
2768 12:26:33.494518
2769 12:26:33.494642 Set Vref, RX VrefLevel [Byte0]: 49
2770 12:26:33.497585 [Byte1]: 49
2771 12:26:33.502652
2772 12:26:33.502748 Set Vref, RX VrefLevel [Byte0]: 50
2773 12:26:33.505660 [Byte1]: 50
2774 12:26:33.510121
2775 12:26:33.510243 Set Vref, RX VrefLevel [Byte0]: 51
2776 12:26:33.513828 [Byte1]: 51
2777 12:26:33.518241
2778 12:26:33.518365 Set Vref, RX VrefLevel [Byte0]: 52
2779 12:26:33.521447 [Byte1]: 52
2780 12:26:33.526302
2781 12:26:33.526427 Set Vref, RX VrefLevel [Byte0]: 53
2782 12:26:33.529080 [Byte1]: 53
2783 12:26:33.533926
2784 12:26:33.534041 Set Vref, RX VrefLevel [Byte0]: 54
2785 12:26:33.537146 [Byte1]: 54
2786 12:26:33.542024
2787 12:26:33.542154 Set Vref, RX VrefLevel [Byte0]: 55
2788 12:26:33.545497 [Byte1]: 55
2789 12:26:33.549623
2790 12:26:33.549743 Set Vref, RX VrefLevel [Byte0]: 56
2791 12:26:33.553224 [Byte1]: 56
2792 12:26:33.557603
2793 12:26:33.557724 Set Vref, RX VrefLevel [Byte0]: 57
2794 12:26:33.561334 [Byte1]: 57
2795 12:26:33.565594
2796 12:26:33.565712 Set Vref, RX VrefLevel [Byte0]: 58
2797 12:26:33.568932 [Byte1]: 58
2798 12:26:33.573793
2799 12:26:33.573910 Set Vref, RX VrefLevel [Byte0]: 59
2800 12:26:33.576822 [Byte1]: 59
2801 12:26:33.581828
2802 12:26:33.581947 Set Vref, RX VrefLevel [Byte0]: 60
2803 12:26:33.584947 [Byte1]: 60
2804 12:26:33.589393
2805 12:26:33.589504 Set Vref, RX VrefLevel [Byte0]: 61
2806 12:26:33.593147 [Byte1]: 61
2807 12:26:33.597316
2808 12:26:33.597433 Set Vref, RX VrefLevel [Byte0]: 62
2809 12:26:33.600406 [Byte1]: 62
2810 12:26:33.605451
2811 12:26:33.605562 Set Vref, RX VrefLevel [Byte0]: 63
2812 12:26:33.608574 [Byte1]: 63
2813 12:26:33.613386
2814 12:26:33.613506 Set Vref, RX VrefLevel [Byte0]: 64
2815 12:26:33.616506 [Byte1]: 64
2816 12:26:33.621466
2817 12:26:33.621585 Set Vref, RX VrefLevel [Byte0]: 65
2818 12:26:33.624554 [Byte1]: 65
2819 12:26:33.628921
2820 12:26:33.629035 Set Vref, RX VrefLevel [Byte0]: 66
2821 12:26:33.632407 [Byte1]: 66
2822 12:26:33.636903
2823 12:26:33.637024 Set Vref, RX VrefLevel [Byte0]: 67
2824 12:26:33.640574 [Byte1]: 67
2825 12:26:33.645176
2826 12:26:33.645296 Set Vref, RX VrefLevel [Byte0]: 68
2827 12:26:33.648590 [Byte1]: 68
2828 12:26:33.652728
2829 12:26:33.652845 Final RX Vref Byte 0 = 55 to rank0
2830 12:26:33.656236 Final RX Vref Byte 1 = 53 to rank0
2831 12:26:33.659236 Final RX Vref Byte 0 = 55 to rank1
2832 12:26:33.662446 Final RX Vref Byte 1 = 53 to rank1==
2833 12:26:33.666069 Dram Type= 6, Freq= 0, CH_0, rank 0
2834 12:26:33.672902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 12:26:33.673071 ==
2836 12:26:33.673173 DQS Delay:
2837 12:26:33.675944 DQS0 = 0, DQS1 = 0
2838 12:26:33.676063 DQM Delay:
2839 12:26:33.676159 DQM0 = 114, DQM1 = 105
2840 12:26:33.679709 DQ Delay:
2841 12:26:33.682545 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2842 12:26:33.685738 DQ4 =114, DQ5 =110, DQ6 =120, DQ7 =122
2843 12:26:33.689477 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =96
2844 12:26:33.692459 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2845 12:26:33.692573
2846 12:26:33.692670
2847 12:26:33.702491 [DQSOSCAuto] RK0, (LSB)MR18= 0xfceb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2848 12:26:33.702634 CH0 RK0: MR19=303, MR18=FCEB
2849 12:26:33.708716 CH0_RK0: MR19=0x303, MR18=0xFCEB, DQSOSC=411, MR23=63, INC=38, DEC=25
2850 12:26:33.708843
2851 12:26:33.712439 ----->DramcWriteLeveling(PI) begin...
2852 12:26:33.712553 ==
2853 12:26:33.715453 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 12:26:33.722287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 12:26:33.722393 ==
2856 12:26:33.725940 Write leveling (Byte 0): 33 => 33
2857 12:26:33.726069 Write leveling (Byte 1): 28 => 28
2858 12:26:33.729088 DramcWriteLeveling(PI) end<-----
2859 12:26:33.729190
2860 12:26:33.732160 ==
2861 12:26:33.732288 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 12:26:33.739016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 12:26:33.739183 ==
2864 12:26:33.742295 [Gating] SW mode calibration
2865 12:26:33.749018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2866 12:26:33.752120 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2867 12:26:33.759162 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2868 12:26:33.762158 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2869 12:26:33.765839 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 12:26:33.772517 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 12:26:33.775690 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 12:26:33.778887 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 12:26:33.785547 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2874 12:26:33.788537 0 15 28 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
2875 12:26:33.792265 1 0 0 | B1->B0 | 2f2f 2a2a | 0 0 | (1 0) (0 0)
2876 12:26:33.795418 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2877 12:26:33.802202 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 12:26:33.805306 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 12:26:33.809041 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 12:26:33.815302 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 12:26:33.819031 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2882 12:26:33.822110 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2883 12:26:33.828887 1 1 0 | B1->B0 | 3636 4141 | 0 0 | (0 0) (0 0)
2884 12:26:33.832028 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2885 12:26:33.835642 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 12:26:33.842504 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 12:26:33.845594 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 12:26:33.849179 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 12:26:33.855803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 12:26:33.858818 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2891 12:26:33.862371 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2892 12:26:33.869267 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2893 12:26:33.872257 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:26:33.875382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:26:33.882481 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:26:33.885592 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:26:33.889095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 12:26:33.895277 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 12:26:33.899070 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 12:26:33.902325 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 12:26:33.905916 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 12:26:33.912100 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 12:26:33.915863 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 12:26:33.918947 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 12:26:33.925561 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2906 12:26:33.928650 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2907 12:26:33.931906 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2908 12:26:33.935556 Total UI for P1: 0, mck2ui 16
2909 12:26:33.938562 best dqsien dly found for B0: ( 1, 3, 26)
2910 12:26:33.945246 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 12:26:33.945450 Total UI for P1: 0, mck2ui 16
2912 12:26:33.952042 best dqsien dly found for B1: ( 1, 4, 0)
2913 12:26:33.955736 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2914 12:26:33.958466 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2915 12:26:33.958599
2916 12:26:33.962072 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2917 12:26:33.965524 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2918 12:26:33.969147 [Gating] SW calibration Done
2919 12:26:33.969350 ==
2920 12:26:33.972017 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 12:26:33.975778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 12:26:33.976001 ==
2923 12:26:33.978580 RX Vref Scan: 0
2924 12:26:33.978763
2925 12:26:33.978908 RX Vref 0 -> 0, step: 1
2926 12:26:33.979048
2927 12:26:33.982491 RX Delay -40 -> 252, step: 8
2928 12:26:33.985540 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2929 12:26:33.991849 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2930 12:26:33.995505 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2931 12:26:33.998568 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2932 12:26:34.002339 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2933 12:26:34.005549 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2934 12:26:34.012313 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2935 12:26:34.015292 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2936 12:26:34.018445 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2937 12:26:34.022244 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2938 12:26:34.025361 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2939 12:26:34.028418 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2940 12:26:34.035272 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2941 12:26:34.038412 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2942 12:26:34.042105 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2943 12:26:34.045203 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2944 12:26:34.045418 ==
2945 12:26:34.048317 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 12:26:34.055199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 12:26:34.055464 ==
2948 12:26:34.055624 DQS Delay:
2949 12:26:34.058419 DQS0 = 0, DQS1 = 0
2950 12:26:34.058621 DQM Delay:
2951 12:26:34.061957 DQM0 = 115, DQM1 = 106
2952 12:26:34.062162 DQ Delay:
2953 12:26:34.065395 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2954 12:26:34.068243 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2955 12:26:34.071736 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2956 12:26:34.075246 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2957 12:26:34.075472
2958 12:26:34.075625
2959 12:26:34.075750 ==
2960 12:26:34.078751 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 12:26:34.081750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 12:26:34.085156 ==
2963 12:26:34.085373
2964 12:26:34.085528
2965 12:26:34.085644 TX Vref Scan disable
2966 12:26:34.088316 == TX Byte 0 ==
2967 12:26:34.092191 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2968 12:26:34.095310 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2969 12:26:34.098330 == TX Byte 1 ==
2970 12:26:34.102029 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2971 12:26:34.105180 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2972 12:26:34.105391 ==
2973 12:26:34.108775 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 12:26:34.114905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 12:26:34.115150 ==
2976 12:26:34.126314 TX Vref=22, minBit 1, minWin=25, winSum=424
2977 12:26:34.130042 TX Vref=24, minBit 1, minWin=26, winSum=425
2978 12:26:34.133028 TX Vref=26, minBit 2, minWin=26, winSum=430
2979 12:26:34.136783 TX Vref=28, minBit 3, minWin=26, winSum=432
2980 12:26:34.139967 TX Vref=30, minBit 3, minWin=26, winSum=434
2981 12:26:34.143069 TX Vref=32, minBit 3, minWin=26, winSum=433
2982 12:26:34.149720 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 30
2983 12:26:34.149929
2984 12:26:34.152923 Final TX Range 1 Vref 30
2985 12:26:34.153061
2986 12:26:34.153137 ==
2987 12:26:34.156581 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 12:26:34.159664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 12:26:34.159812 ==
2990 12:26:34.159890
2991 12:26:34.159955
2992 12:26:34.163233 TX Vref Scan disable
2993 12:26:34.166362 == TX Byte 0 ==
2994 12:26:34.169928 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2995 12:26:34.173200 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2996 12:26:34.176714 == TX Byte 1 ==
2997 12:26:34.179809 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2998 12:26:34.183296 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2999 12:26:34.183458
3000 12:26:34.186746 [DATLAT]
3001 12:26:34.186884 Freq=1200, CH0 RK1
3002 12:26:34.186958
3003 12:26:34.190059 DATLAT Default: 0xd
3004 12:26:34.190187 0, 0xFFFF, sum = 0
3005 12:26:34.193135 1, 0xFFFF, sum = 0
3006 12:26:34.193287 2, 0xFFFF, sum = 0
3007 12:26:34.196973 3, 0xFFFF, sum = 0
3008 12:26:34.197118 4, 0xFFFF, sum = 0
3009 12:26:34.200008 5, 0xFFFF, sum = 0
3010 12:26:34.200149 6, 0xFFFF, sum = 0
3011 12:26:34.203776 7, 0xFFFF, sum = 0
3012 12:26:34.203998 8, 0xFFFF, sum = 0
3013 12:26:34.206724 9, 0xFFFF, sum = 0
3014 12:26:34.206918 10, 0xFFFF, sum = 0
3015 12:26:34.209871 11, 0xFFFF, sum = 0
3016 12:26:34.210075 12, 0x0, sum = 1
3017 12:26:34.213419 13, 0x0, sum = 2
3018 12:26:34.213624 14, 0x0, sum = 3
3019 12:26:34.216400 15, 0x0, sum = 4
3020 12:26:34.216588 best_step = 13
3021 12:26:34.216723
3022 12:26:34.216844 ==
3023 12:26:34.220299 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 12:26:34.226658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 12:26:34.226816 ==
3026 12:26:34.226890 RX Vref Scan: 0
3027 12:26:34.226976
3028 12:26:34.230363 RX Vref 0 -> 0, step: 1
3029 12:26:34.230501
3030 12:26:34.233753 RX Delay -21 -> 252, step: 4
3031 12:26:34.236854 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3032 12:26:34.240497 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3033 12:26:34.246555 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3034 12:26:34.250359 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3035 12:26:34.253446 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3036 12:26:34.256585 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3037 12:26:34.260336 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3038 12:26:34.263388 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3039 12:26:34.270199 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3040 12:26:34.273222 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3041 12:26:34.277085 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3042 12:26:34.279810 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3043 12:26:34.283746 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3044 12:26:34.290283 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3045 12:26:34.293225 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3046 12:26:34.296801 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3047 12:26:34.297022 ==
3048 12:26:34.300278 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 12:26:34.303456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 12:26:34.303605 ==
3051 12:26:34.307191 DQS Delay:
3052 12:26:34.307330 DQS0 = 0, DQS1 = 0
3053 12:26:34.310074 DQM Delay:
3054 12:26:34.310199 DQM0 = 113, DQM1 = 105
3055 12:26:34.313264 DQ Delay:
3056 12:26:34.316901 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3057 12:26:34.319937 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122
3058 12:26:34.323708 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =96
3059 12:26:34.326709 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3060 12:26:34.326847
3061 12:26:34.326922
3062 12:26:34.333341 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3063 12:26:34.337062 CH0 RK1: MR19=403, MR18=4F6
3064 12:26:34.343252 CH0_RK1: MR19=0x403, MR18=0x4F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3065 12:26:34.347002 [RxdqsGatingPostProcess] freq 1200
3066 12:26:34.350186 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3067 12:26:34.353297 best DQS0 dly(2T, 0.5T) = (0, 12)
3068 12:26:34.356986 best DQS1 dly(2T, 0.5T) = (0, 12)
3069 12:26:34.360163 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3070 12:26:34.363905 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3071 12:26:34.366815 best DQS0 dly(2T, 0.5T) = (0, 11)
3072 12:26:34.370061 best DQS1 dly(2T, 0.5T) = (0, 12)
3073 12:26:34.373701 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3074 12:26:34.376898 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3075 12:26:34.380016 Pre-setting of DQS Precalculation
3076 12:26:34.383801 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3077 12:26:34.383998 ==
3078 12:26:34.386735 Dram Type= 6, Freq= 0, CH_1, rank 0
3079 12:26:34.393778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 12:26:34.393993 ==
3081 12:26:34.396765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3082 12:26:34.403774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3083 12:26:34.411941 [CA 0] Center 38 (8~68) winsize 61
3084 12:26:34.415660 [CA 1] Center 38 (8~68) winsize 61
3085 12:26:34.418434 [CA 2] Center 35 (5~65) winsize 61
3086 12:26:34.422154 [CA 3] Center 34 (4~65) winsize 62
3087 12:26:34.425166 [CA 4] Center 34 (4~65) winsize 62
3088 12:26:34.428954 [CA 5] Center 34 (4~64) winsize 61
3089 12:26:34.429149
3090 12:26:34.432034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3091 12:26:34.432195
3092 12:26:34.435246 [CATrainingPosCal] consider 1 rank data
3093 12:26:34.438324 u2DelayCellTimex100 = 270/100 ps
3094 12:26:34.442061 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3095 12:26:34.445258 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3096 12:26:34.452121 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3097 12:26:34.455192 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3098 12:26:34.458325 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3099 12:26:34.462015 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3100 12:26:34.462210
3101 12:26:34.465131 CA PerBit enable=1, Macro0, CA PI delay=34
3102 12:26:34.465293
3103 12:26:34.468698 [CBTSetCACLKResult] CA Dly = 34
3104 12:26:34.468870 CS Dly: 6 (0~37)
3105 12:26:34.468981 ==
3106 12:26:34.471852 Dram Type= 6, Freq= 0, CH_1, rank 1
3107 12:26:34.478554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 12:26:34.478758 ==
3109 12:26:34.481709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3110 12:26:34.488622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3111 12:26:34.497721 [CA 0] Center 38 (8~68) winsize 61
3112 12:26:34.500978 [CA 1] Center 38 (8~68) winsize 61
3113 12:26:34.504472 [CA 2] Center 34 (4~65) winsize 62
3114 12:26:34.507386 [CA 3] Center 34 (4~65) winsize 62
3115 12:26:34.510994 [CA 4] Center 34 (4~65) winsize 62
3116 12:26:34.513892 [CA 5] Center 33 (3~64) winsize 62
3117 12:26:34.514070
3118 12:26:34.517472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3119 12:26:34.517651
3120 12:26:34.520866 [CATrainingPosCal] consider 2 rank data
3121 12:26:34.524286 u2DelayCellTimex100 = 270/100 ps
3122 12:26:34.527288 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3123 12:26:34.531032 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3124 12:26:34.537841 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3125 12:26:34.540965 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3126 12:26:34.544128 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3127 12:26:34.547249 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3128 12:26:34.547447
3129 12:26:34.550928 CA PerBit enable=1, Macro0, CA PI delay=34
3130 12:26:34.551120
3131 12:26:34.553995 [CBTSetCACLKResult] CA Dly = 34
3132 12:26:34.554166 CS Dly: 7 (0~40)
3133 12:26:34.554277
3134 12:26:34.557741 ----->DramcWriteLeveling(PI) begin...
3135 12:26:34.560919 ==
3136 12:26:34.561091 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 12:26:34.567532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 12:26:34.567737 ==
3139 12:26:34.570677 Write leveling (Byte 0): 25 => 25
3140 12:26:34.574426 Write leveling (Byte 1): 30 => 30
3141 12:26:34.574607 DramcWriteLeveling(PI) end<-----
3142 12:26:34.577551
3143 12:26:34.577715 ==
3144 12:26:34.581146 Dram Type= 6, Freq= 0, CH_1, rank 0
3145 12:26:34.584566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 12:26:34.584749 ==
3147 12:26:34.587575 [Gating] SW mode calibration
3148 12:26:34.594355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3149 12:26:34.597474 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3150 12:26:34.604381 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3151 12:26:34.607850 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3152 12:26:34.610788 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 12:26:34.617660 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 12:26:34.621098 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 12:26:34.624593 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 12:26:34.630802 0 15 24 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3157 12:26:34.634391 0 15 28 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
3158 12:26:34.637907 1 0 0 | B1->B0 | 2323 2929 | 0 0 | (1 0) (1 1)
3159 12:26:34.644201 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3160 12:26:34.647919 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 12:26:34.650858 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 12:26:34.657615 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 12:26:34.660894 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 12:26:34.663930 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 12:26:34.670788 1 0 28 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
3166 12:26:34.674039 1 1 0 | B1->B0 | 4444 3838 | 0 1 | (0 0) (0 0)
3167 12:26:34.677689 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 12:26:34.680737 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 12:26:34.687677 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 12:26:34.690662 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 12:26:34.694550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 12:26:34.700853 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 12:26:34.704525 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3174 12:26:34.707464 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3175 12:26:34.714389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:26:34.717375 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:26:34.720757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:26:34.727704 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:26:34.731100 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:26:34.734544 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:26:34.740864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 12:26:34.744259 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 12:26:34.747740 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 12:26:34.754680 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 12:26:34.757785 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 12:26:34.760905 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 12:26:34.764697 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 12:26:34.770858 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 12:26:34.774061 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3190 12:26:34.777663 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3191 12:26:34.781284 Total UI for P1: 0, mck2ui 16
3192 12:26:34.784411 best dqsien dly found for B1: ( 1, 3, 30)
3193 12:26:34.791241 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 12:26:34.791462 Total UI for P1: 0, mck2ui 16
3195 12:26:34.797723 best dqsien dly found for B0: ( 1, 3, 30)
3196 12:26:34.801230 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3197 12:26:34.804416 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3198 12:26:34.804554
3199 12:26:34.807551 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3200 12:26:34.811128 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3201 12:26:34.814425 [Gating] SW calibration Done
3202 12:26:34.814567 ==
3203 12:26:34.818020 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 12:26:34.821133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 12:26:34.821286 ==
3206 12:26:34.824949 RX Vref Scan: 0
3207 12:26:34.825098
3208 12:26:34.825172 RX Vref 0 -> 0, step: 1
3209 12:26:34.825239
3210 12:26:34.827909 RX Delay -40 -> 252, step: 8
3211 12:26:34.830897 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3212 12:26:34.838046 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3213 12:26:34.840847 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3214 12:26:34.844437 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3215 12:26:34.847953 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3216 12:26:34.850798 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3217 12:26:34.858014 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3218 12:26:34.861133 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3219 12:26:34.864171 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3220 12:26:34.867874 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3221 12:26:34.871022 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3222 12:26:34.877911 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3223 12:26:34.880968 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3224 12:26:34.884597 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3225 12:26:34.887600 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3226 12:26:34.891340 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3227 12:26:34.891543 ==
3228 12:26:34.894333 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 12:26:34.901207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 12:26:34.901358 ==
3231 12:26:34.901429 DQS Delay:
3232 12:26:34.904255 DQS0 = 0, DQS1 = 0
3233 12:26:34.904362 DQM Delay:
3234 12:26:34.907589 DQM0 = 116, DQM1 = 109
3235 12:26:34.907695 DQ Delay:
3236 12:26:34.911240 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3237 12:26:34.914494 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3238 12:26:34.917688 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3239 12:26:34.921284 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3240 12:26:34.921409
3241 12:26:34.921478
3242 12:26:34.921541 ==
3243 12:26:34.924426 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 12:26:34.927391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 12:26:34.931278 ==
3246 12:26:34.931492
3247 12:26:34.931587
3248 12:26:34.931650 TX Vref Scan disable
3249 12:26:34.934355 == TX Byte 0 ==
3250 12:26:34.937873 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3251 12:26:34.940913 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3252 12:26:34.944594 == TX Byte 1 ==
3253 12:26:34.947502 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3254 12:26:34.950863 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3255 12:26:34.954349 ==
3256 12:26:34.954497 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 12:26:34.960729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 12:26:34.960906 ==
3259 12:26:34.972310 TX Vref=22, minBit 1, minWin=24, winSum=410
3260 12:26:34.975890 TX Vref=24, minBit 2, minWin=25, winSum=415
3261 12:26:34.978943 TX Vref=26, minBit 0, minWin=26, winSum=421
3262 12:26:34.982098 TX Vref=28, minBit 0, minWin=26, winSum=424
3263 12:26:34.985696 TX Vref=30, minBit 0, minWin=26, winSum=425
3264 12:26:34.988665 TX Vref=32, minBit 13, minWin=25, winSum=425
3265 12:26:34.995437 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
3266 12:26:34.995609
3267 12:26:34.998659 Final TX Range 1 Vref 30
3268 12:26:34.998782
3269 12:26:34.998854 ==
3270 12:26:35.002370 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 12:26:35.005444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 12:26:35.005571 ==
3273 12:26:35.005642
3274 12:26:35.009299
3275 12:26:35.009428 TX Vref Scan disable
3276 12:26:35.012362 == TX Byte 0 ==
3277 12:26:35.016088 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3278 12:26:35.019257 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3279 12:26:35.022236 == TX Byte 1 ==
3280 12:26:35.025431 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3281 12:26:35.029183 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3282 12:26:35.029326
3283 12:26:35.032277 [DATLAT]
3284 12:26:35.032396 Freq=1200, CH1 RK0
3285 12:26:35.032466
3286 12:26:35.035959 DATLAT Default: 0xd
3287 12:26:35.036120 0, 0xFFFF, sum = 0
3288 12:26:35.038940 1, 0xFFFF, sum = 0
3289 12:26:35.039080 2, 0xFFFF, sum = 0
3290 12:26:35.041982 3, 0xFFFF, sum = 0
3291 12:26:35.042084 4, 0xFFFF, sum = 0
3292 12:26:35.045812 5, 0xFFFF, sum = 0
3293 12:26:35.045920 6, 0xFFFF, sum = 0
3294 12:26:35.049000 7, 0xFFFF, sum = 0
3295 12:26:35.049102 8, 0xFFFF, sum = 0
3296 12:26:35.052671 9, 0xFFFF, sum = 0
3297 12:26:35.055575 10, 0xFFFF, sum = 0
3298 12:26:35.055709 11, 0xFFFF, sum = 0
3299 12:26:35.059077 12, 0x0, sum = 1
3300 12:26:35.059235 13, 0x0, sum = 2
3301 12:26:35.059343 14, 0x0, sum = 3
3302 12:26:35.062827 15, 0x0, sum = 4
3303 12:26:35.062949 best_step = 13
3304 12:26:35.063051
3305 12:26:35.063153 ==
3306 12:26:35.065574 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 12:26:35.072201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 12:26:35.072358 ==
3309 12:26:35.072465 RX Vref Scan: 1
3310 12:26:35.072564
3311 12:26:35.075586 Set Vref Range= 32 -> 127
3312 12:26:35.075717
3313 12:26:35.079345 RX Vref 32 -> 127, step: 1
3314 12:26:35.079492
3315 12:26:35.082330 RX Delay -21 -> 252, step: 4
3316 12:26:35.082434
3317 12:26:35.086104 Set Vref, RX VrefLevel [Byte0]: 32
3318 12:26:35.089271 [Byte1]: 32
3319 12:26:35.089406
3320 12:26:35.092316 Set Vref, RX VrefLevel [Byte0]: 33
3321 12:26:35.095978 [Byte1]: 33
3322 12:26:35.096116
3323 12:26:35.099092 Set Vref, RX VrefLevel [Byte0]: 34
3324 12:26:35.102224 [Byte1]: 34
3325 12:26:35.106628
3326 12:26:35.106745 Set Vref, RX VrefLevel [Byte0]: 35
3327 12:26:35.109664 [Byte1]: 35
3328 12:26:35.114139
3329 12:26:35.114273 Set Vref, RX VrefLevel [Byte0]: 36
3330 12:26:35.117851 [Byte1]: 36
3331 12:26:35.122150
3332 12:26:35.122285 Set Vref, RX VrefLevel [Byte0]: 37
3333 12:26:35.125929 [Byte1]: 37
3334 12:26:35.130414
3335 12:26:35.130558 Set Vref, RX VrefLevel [Byte0]: 38
3336 12:26:35.133500 [Byte1]: 38
3337 12:26:35.137875
3338 12:26:35.138014 Set Vref, RX VrefLevel [Byte0]: 39
3339 12:26:35.141448 [Byte1]: 39
3340 12:26:35.146257
3341 12:26:35.146419 Set Vref, RX VrefLevel [Byte0]: 40
3342 12:26:35.149410 [Byte1]: 40
3343 12:26:35.153726
3344 12:26:35.157331 Set Vref, RX VrefLevel [Byte0]: 41
3345 12:26:35.157455 [Byte1]: 41
3346 12:26:35.161758
3347 12:26:35.161871 Set Vref, RX VrefLevel [Byte0]: 42
3348 12:26:35.165155 [Byte1]: 42
3349 12:26:35.169850
3350 12:26:35.170011 Set Vref, RX VrefLevel [Byte0]: 43
3351 12:26:35.173395 [Byte1]: 43
3352 12:26:35.177500
3353 12:26:35.177637 Set Vref, RX VrefLevel [Byte0]: 44
3354 12:26:35.180992 [Byte1]: 44
3355 12:26:35.185808
3356 12:26:35.185932 Set Vref, RX VrefLevel [Byte0]: 45
3357 12:26:35.188908 [Byte1]: 45
3358 12:26:35.193810
3359 12:26:35.193959 Set Vref, RX VrefLevel [Byte0]: 46
3360 12:26:35.196901 [Byte1]: 46
3361 12:26:35.201186
3362 12:26:35.201345 Set Vref, RX VrefLevel [Byte0]: 47
3363 12:26:35.204950 [Byte1]: 47
3364 12:26:35.209258
3365 12:26:35.209406 Set Vref, RX VrefLevel [Byte0]: 48
3366 12:26:35.212406 [Byte1]: 48
3367 12:26:35.217368
3368 12:26:35.217488 Set Vref, RX VrefLevel [Byte0]: 49
3369 12:26:35.220386 [Byte1]: 49
3370 12:26:35.225357
3371 12:26:35.225514 Set Vref, RX VrefLevel [Byte0]: 50
3372 12:26:35.228516 [Byte1]: 50
3373 12:26:35.232969
3374 12:26:35.233127 Set Vref, RX VrefLevel [Byte0]: 51
3375 12:26:35.236648 [Byte1]: 51
3376 12:26:35.241090
3377 12:26:35.241252 Set Vref, RX VrefLevel [Byte0]: 52
3378 12:26:35.244164 [Byte1]: 52
3379 12:26:35.249011
3380 12:26:35.249162 Set Vref, RX VrefLevel [Byte0]: 53
3381 12:26:35.252076 [Byte1]: 53
3382 12:26:35.257159
3383 12:26:35.257341 Set Vref, RX VrefLevel [Byte0]: 54
3384 12:26:35.260210 [Byte1]: 54
3385 12:26:35.264479
3386 12:26:35.264676 Set Vref, RX VrefLevel [Byte0]: 55
3387 12:26:35.268122 [Byte1]: 55
3388 12:26:35.272837
3389 12:26:35.273028 Set Vref, RX VrefLevel [Byte0]: 56
3390 12:26:35.276204 [Byte1]: 56
3391 12:26:35.280717
3392 12:26:35.280901 Set Vref, RX VrefLevel [Byte0]: 57
3393 12:26:35.284093 [Byte1]: 57
3394 12:26:35.288898
3395 12:26:35.289056 Set Vref, RX VrefLevel [Byte0]: 58
3396 12:26:35.291712 [Byte1]: 58
3397 12:26:35.296465
3398 12:26:35.296606 Set Vref, RX VrefLevel [Byte0]: 59
3399 12:26:35.300094 [Byte1]: 59
3400 12:26:35.304322
3401 12:26:35.304444 Set Vref, RX VrefLevel [Byte0]: 60
3402 12:26:35.308031 [Byte1]: 60
3403 12:26:35.312378
3404 12:26:35.312550 Set Vref, RX VrefLevel [Byte0]: 61
3405 12:26:35.315325 [Byte1]: 61
3406 12:26:35.320406
3407 12:26:35.320554 Set Vref, RX VrefLevel [Byte0]: 62
3408 12:26:35.323409 [Byte1]: 62
3409 12:26:35.328402
3410 12:26:35.328525 Set Vref, RX VrefLevel [Byte0]: 63
3411 12:26:35.331461 [Byte1]: 63
3412 12:26:35.335941
3413 12:26:35.336146 Set Vref, RX VrefLevel [Byte0]: 64
3414 12:26:35.339881 [Byte1]: 64
3415 12:26:35.344114
3416 12:26:35.344279 Set Vref, RX VrefLevel [Byte0]: 65
3417 12:26:35.347194 [Byte1]: 65
3418 12:26:35.352141
3419 12:26:35.352281 Set Vref, RX VrefLevel [Byte0]: 66
3420 12:26:35.355049 [Byte1]: 66
3421 12:26:35.360160
3422 12:26:35.360308 Set Vref, RX VrefLevel [Byte0]: 67
3423 12:26:35.363217 [Byte1]: 67
3424 12:26:35.367606
3425 12:26:35.367721 Set Vref, RX VrefLevel [Byte0]: 68
3426 12:26:35.371214 [Byte1]: 68
3427 12:26:35.376159
3428 12:26:35.376348 Set Vref, RX VrefLevel [Byte0]: 69
3429 12:26:35.379090 [Byte1]: 69
3430 12:26:35.383579
3431 12:26:35.383711 Set Vref, RX VrefLevel [Byte0]: 70
3432 12:26:35.387113 [Byte1]: 70
3433 12:26:35.391304
3434 12:26:35.391470 Final RX Vref Byte 0 = 57 to rank0
3435 12:26:35.395116 Final RX Vref Byte 1 = 45 to rank0
3436 12:26:35.398202 Final RX Vref Byte 0 = 57 to rank1
3437 12:26:35.401703 Final RX Vref Byte 1 = 45 to rank1==
3438 12:26:35.404663 Dram Type= 6, Freq= 0, CH_1, rank 0
3439 12:26:35.411323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 12:26:35.411482 ==
3441 12:26:35.411561 DQS Delay:
3442 12:26:35.411627 DQS0 = 0, DQS1 = 0
3443 12:26:35.414540 DQM Delay:
3444 12:26:35.414631 DQM0 = 116, DQM1 = 107
3445 12:26:35.418350 DQ Delay:
3446 12:26:35.421392 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3447 12:26:35.424594 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3448 12:26:35.428317 DQ8 =94, DQ9 =94, DQ10 =110, DQ11 =102
3449 12:26:35.431480 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3450 12:26:35.431607
3451 12:26:35.431701
3452 12:26:35.437855 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3453 12:26:35.441683 CH1 RK0: MR19=403, MR18=1E6
3454 12:26:35.447967 CH1_RK0: MR19=0x403, MR18=0x1E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3455 12:26:35.448107
3456 12:26:35.451617 ----->DramcWriteLeveling(PI) begin...
3457 12:26:35.451731 ==
3458 12:26:35.454763 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 12:26:35.458298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 12:26:35.458456 ==
3461 12:26:35.461360 Write leveling (Byte 0): 27 => 27
3462 12:26:35.464463 Write leveling (Byte 1): 29 => 29
3463 12:26:35.468164 DramcWriteLeveling(PI) end<-----
3464 12:26:35.468327
3465 12:26:35.468448 ==
3466 12:26:35.471293 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 12:26:35.477717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 12:26:35.477857 ==
3469 12:26:35.477935 [Gating] SW mode calibration
3470 12:26:35.487688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3471 12:26:35.491368 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3472 12:26:35.494523 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3473 12:26:35.501271 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 12:26:35.504819 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 12:26:35.507904 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 12:26:35.515048 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 12:26:35.518051 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 12:26:35.521694 0 15 24 | B1->B0 | 3535 2525 | 0 0 | (0 0) (1 0)
3479 12:26:35.528025 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3480 12:26:35.531025 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3481 12:26:35.534795 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 12:26:35.541083 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3483 12:26:35.544945 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 12:26:35.548063 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 12:26:35.555075 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3486 12:26:35.558161 1 0 24 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
3487 12:26:35.561244 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 12:26:35.564842 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 12:26:35.571050 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 12:26:35.574820 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 12:26:35.577991 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 12:26:35.584332 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 12:26:35.587586 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3494 12:26:35.591193 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3495 12:26:35.597616 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3496 12:26:35.601077 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:26:35.604697 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:26:35.611165 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:26:35.614384 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:26:35.618042 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:26:35.624128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 12:26:35.627682 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:26:35.630805 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 12:26:35.637856 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 12:26:35.640944 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 12:26:35.644281 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 12:26:35.650603 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 12:26:35.654364 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 12:26:35.657680 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3510 12:26:35.664448 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3511 12:26:35.667542 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3512 12:26:35.670540 Total UI for P1: 0, mck2ui 16
3513 12:26:35.673702 best dqsien dly found for B0: ( 1, 3, 22)
3514 12:26:35.677757 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 12:26:35.680706 Total UI for P1: 0, mck2ui 16
3516 12:26:35.683823 best dqsien dly found for B1: ( 1, 3, 26)
3517 12:26:35.686904 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3518 12:26:35.690806 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3519 12:26:35.690979
3520 12:26:35.697011 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3521 12:26:35.700602 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3522 12:26:35.703860 [Gating] SW calibration Done
3523 12:26:35.704007 ==
3524 12:26:35.706971 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 12:26:35.710448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 12:26:35.710616 ==
3527 12:26:35.710735 RX Vref Scan: 0
3528 12:26:35.710832
3529 12:26:35.713977 RX Vref 0 -> 0, step: 1
3530 12:26:35.714122
3531 12:26:35.716966 RX Delay -40 -> 252, step: 8
3532 12:26:35.720449 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3533 12:26:35.723569 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3534 12:26:35.727310 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3535 12:26:35.734209 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3536 12:26:35.737337 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3537 12:26:35.740400 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3538 12:26:35.744442 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3539 12:26:35.747434 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3540 12:26:35.753673 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3541 12:26:35.756883 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3542 12:26:35.760539 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3543 12:26:35.763680 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3544 12:26:35.767363 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3545 12:26:35.773526 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3546 12:26:35.777164 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3547 12:26:35.780390 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3548 12:26:35.780582 ==
3549 12:26:35.783571 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 12:26:35.786888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 12:26:35.787075 ==
3552 12:26:35.790031 DQS Delay:
3553 12:26:35.790199 DQS0 = 0, DQS1 = 0
3554 12:26:35.793862 DQM Delay:
3555 12:26:35.794055 DQM0 = 115, DQM1 = 107
3556 12:26:35.797080 DQ Delay:
3557 12:26:35.800057 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3558 12:26:35.803787 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3559 12:26:35.806958 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3560 12:26:35.810019 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3561 12:26:35.810208
3562 12:26:35.810344
3563 12:26:35.810470 ==
3564 12:26:35.813138 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 12:26:35.816568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 12:26:35.816749 ==
3567 12:26:35.816889
3568 12:26:35.817014
3569 12:26:35.820061 TX Vref Scan disable
3570 12:26:35.823566 == TX Byte 0 ==
3571 12:26:35.826370 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 12:26:35.830030 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 12:26:35.833557 == TX Byte 1 ==
3574 12:26:35.836682 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3575 12:26:35.839819 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3576 12:26:35.839981 ==
3577 12:26:35.843432 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 12:26:35.846608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 12:26:35.849808 ==
3580 12:26:35.859789 TX Vref=22, minBit 1, minWin=25, winSum=420
3581 12:26:35.863000 TX Vref=24, minBit 1, minWin=25, winSum=425
3582 12:26:35.866859 TX Vref=26, minBit 1, minWin=26, winSum=434
3583 12:26:35.869860 TX Vref=28, minBit 2, minWin=26, winSum=432
3584 12:26:35.872952 TX Vref=30, minBit 4, minWin=26, winSum=436
3585 12:26:35.879899 TX Vref=32, minBit 1, minWin=26, winSum=435
3586 12:26:35.883006 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 30
3587 12:26:35.883172
3588 12:26:35.886315 Final TX Range 1 Vref 30
3589 12:26:35.886462
3590 12:26:35.886567 ==
3591 12:26:35.889937 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 12:26:35.893057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 12:26:35.893214 ==
3594 12:26:35.896245
3595 12:26:35.896390
3596 12:26:35.896501 TX Vref Scan disable
3597 12:26:35.899959 == TX Byte 0 ==
3598 12:26:35.903024 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3599 12:26:35.906523 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3600 12:26:35.909717 == TX Byte 1 ==
3601 12:26:35.912796 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3602 12:26:35.919629 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3603 12:26:35.919840
3604 12:26:35.919980 [DATLAT]
3605 12:26:35.920103 Freq=1200, CH1 RK1
3606 12:26:35.920224
3607 12:26:35.923052 DATLAT Default: 0xd
3608 12:26:35.923161 0, 0xFFFF, sum = 0
3609 12:26:35.926487 1, 0xFFFF, sum = 0
3610 12:26:35.929694 2, 0xFFFF, sum = 0
3611 12:26:35.929843 3, 0xFFFF, sum = 0
3612 12:26:35.932718 4, 0xFFFF, sum = 0
3613 12:26:35.932878 5, 0xFFFF, sum = 0
3614 12:26:35.935723 6, 0xFFFF, sum = 0
3615 12:26:35.935858 7, 0xFFFF, sum = 0
3616 12:26:35.939498 8, 0xFFFF, sum = 0
3617 12:26:35.939637 9, 0xFFFF, sum = 0
3618 12:26:35.942537 10, 0xFFFF, sum = 0
3619 12:26:35.942654 11, 0xFFFF, sum = 0
3620 12:26:35.946241 12, 0x0, sum = 1
3621 12:26:35.946369 13, 0x0, sum = 2
3622 12:26:35.949400 14, 0x0, sum = 3
3623 12:26:35.949519 15, 0x0, sum = 4
3624 12:26:35.952400 best_step = 13
3625 12:26:35.952533
3626 12:26:35.952608 ==
3627 12:26:35.956229 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 12:26:35.959203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 12:26:35.959322 ==
3630 12:26:35.959472 RX Vref Scan: 0
3631 12:26:35.959548
3632 12:26:35.962413 RX Vref 0 -> 0, step: 1
3633 12:26:35.962543
3634 12:26:35.966246 RX Delay -21 -> 252, step: 4
3635 12:26:35.969447 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3636 12:26:35.975694 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3637 12:26:35.979609 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3638 12:26:35.982513 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3639 12:26:35.985658 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3640 12:26:35.988848 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3641 12:26:35.995816 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3642 12:26:35.998873 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3643 12:26:36.002546 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3644 12:26:36.005631 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3645 12:26:36.008795 iDelay=191, Bit 10, Center 108 (43 ~ 174) 132
3646 12:26:36.015567 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3647 12:26:36.019512 iDelay=191, Bit 12, Center 116 (55 ~ 178) 124
3648 12:26:36.022446 iDelay=191, Bit 13, Center 116 (51 ~ 182) 132
3649 12:26:36.025600 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3650 12:26:36.028704 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3651 12:26:36.032160 ==
3652 12:26:36.035712 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 12:26:36.038755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 12:26:36.038918 ==
3655 12:26:36.039028 DQS Delay:
3656 12:26:36.042221 DQS0 = 0, DQS1 = 0
3657 12:26:36.042352 DQM Delay:
3658 12:26:36.045381 DQM0 = 113, DQM1 = 108
3659 12:26:36.045524 DQ Delay:
3660 12:26:36.048454 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3661 12:26:36.052217 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3662 12:26:36.055464 DQ8 =96, DQ9 =96, DQ10 =108, DQ11 =100
3663 12:26:36.058515 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3664 12:26:36.058687
3665 12:26:36.058797
3666 12:26:36.068725 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3667 12:26:36.071915 CH1 RK1: MR19=304, MR18=FB02
3668 12:26:36.075063 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3669 12:26:36.078697 [RxdqsGatingPostProcess] freq 1200
3670 12:26:36.084910 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3671 12:26:36.088418 best DQS0 dly(2T, 0.5T) = (0, 11)
3672 12:26:36.091582 best DQS1 dly(2T, 0.5T) = (0, 11)
3673 12:26:36.095279 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3674 12:26:36.098401 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3675 12:26:36.101554 best DQS0 dly(2T, 0.5T) = (0, 11)
3676 12:26:36.105374 best DQS1 dly(2T, 0.5T) = (0, 11)
3677 12:26:36.108404 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3678 12:26:36.112155 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3679 12:26:36.115107 Pre-setting of DQS Precalculation
3680 12:26:36.118183 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3681 12:26:36.125275 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3682 12:26:36.131537 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3683 12:26:36.131734
3684 12:26:36.135355
3685 12:26:36.135514 [Calibration Summary] 2400 Mbps
3686 12:26:36.138236 CH 0, Rank 0
3687 12:26:36.138398 SW Impedance : PASS
3688 12:26:36.142090 DUTY Scan : NO K
3689 12:26:36.144869 ZQ Calibration : PASS
3690 12:26:36.145022 Jitter Meter : NO K
3691 12:26:36.148459 CBT Training : PASS
3692 12:26:36.152063 Write leveling : PASS
3693 12:26:36.152234 RX DQS gating : PASS
3694 12:26:36.155100 RX DQ/DQS(RDDQC) : PASS
3695 12:26:36.158098 TX DQ/DQS : PASS
3696 12:26:36.158247 RX DATLAT : PASS
3697 12:26:36.161753 RX DQ/DQS(Engine): PASS
3698 12:26:36.165209 TX OE : NO K
3699 12:26:36.165383 All Pass.
3700 12:26:36.165492
3701 12:26:36.165590 CH 0, Rank 1
3702 12:26:36.168332 SW Impedance : PASS
3703 12:26:36.171387 DUTY Scan : NO K
3704 12:26:36.171534 ZQ Calibration : PASS
3705 12:26:36.175215 Jitter Meter : NO K
3706 12:26:36.175398 CBT Training : PASS
3707 12:26:36.178226 Write leveling : PASS
3708 12:26:36.181453 RX DQS gating : PASS
3709 12:26:36.181604 RX DQ/DQS(RDDQC) : PASS
3710 12:26:36.185163 TX DQ/DQS : PASS
3711 12:26:36.188212 RX DATLAT : PASS
3712 12:26:36.188373 RX DQ/DQS(Engine): PASS
3713 12:26:36.191657 TX OE : NO K
3714 12:26:36.191810 All Pass.
3715 12:26:36.191919
3716 12:26:36.195121 CH 1, Rank 0
3717 12:26:36.195257 SW Impedance : PASS
3718 12:26:36.198230 DUTY Scan : NO K
3719 12:26:36.201414 ZQ Calibration : PASS
3720 12:26:36.201561 Jitter Meter : NO K
3721 12:26:36.205122 CBT Training : PASS
3722 12:26:36.208287 Write leveling : PASS
3723 12:26:36.208442 RX DQS gating : PASS
3724 12:26:36.211143 RX DQ/DQS(RDDQC) : PASS
3725 12:26:36.214870 TX DQ/DQS : PASS
3726 12:26:36.215040 RX DATLAT : PASS
3727 12:26:36.218024 RX DQ/DQS(Engine): PASS
3728 12:26:36.218162 TX OE : NO K
3729 12:26:36.221522 All Pass.
3730 12:26:36.221667
3731 12:26:36.221773 CH 1, Rank 1
3732 12:26:36.224605 SW Impedance : PASS
3733 12:26:36.224743 DUTY Scan : NO K
3734 12:26:36.228227 ZQ Calibration : PASS
3735 12:26:36.231306 Jitter Meter : NO K
3736 12:26:36.231461 CBT Training : PASS
3737 12:26:36.234409 Write leveling : PASS
3738 12:26:36.238164 RX DQS gating : PASS
3739 12:26:36.238352 RX DQ/DQS(RDDQC) : PASS
3740 12:26:36.241297 TX DQ/DQS : PASS
3741 12:26:36.244354 RX DATLAT : PASS
3742 12:26:36.244514 RX DQ/DQS(Engine): PASS
3743 12:26:36.247931 TX OE : NO K
3744 12:26:36.248082 All Pass.
3745 12:26:36.248188
3746 12:26:36.251276 DramC Write-DBI off
3747 12:26:36.254612 PER_BANK_REFRESH: Hybrid Mode
3748 12:26:36.254771 TX_TRACKING: ON
3749 12:26:36.264279 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3750 12:26:36.267973 [FAST_K] Save calibration result to emmc
3751 12:26:36.270982 dramc_set_vcore_voltage set vcore to 650000
3752 12:26:36.274542 Read voltage for 600, 5
3753 12:26:36.274712 Vio18 = 0
3754 12:26:36.274822 Vcore = 650000
3755 12:26:36.277696 Vdram = 0
3756 12:26:36.277848 Vddq = 0
3757 12:26:36.277952 Vmddr = 0
3758 12:26:36.284553 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3759 12:26:36.287771 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3760 12:26:36.290948 MEM_TYPE=3, freq_sel=19
3761 12:26:36.294027 sv_algorithm_assistance_LP4_1600
3762 12:26:36.297691 ============ PULL DRAM RESETB DOWN ============
3763 12:26:36.300772 ========== PULL DRAM RESETB DOWN end =========
3764 12:26:36.307676 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3765 12:26:36.310874 ===================================
3766 12:26:36.314517 LPDDR4 DRAM CONFIGURATION
3767 12:26:36.317678 ===================================
3768 12:26:36.317847 EX_ROW_EN[0] = 0x0
3769 12:26:36.320841 EX_ROW_EN[1] = 0x0
3770 12:26:36.320987 LP4Y_EN = 0x0
3771 12:26:36.324389 WORK_FSP = 0x0
3772 12:26:36.324539 WL = 0x2
3773 12:26:36.327296 RL = 0x2
3774 12:26:36.327445 BL = 0x2
3775 12:26:36.331200 RPST = 0x0
3776 12:26:36.331397 RD_PRE = 0x0
3777 12:26:36.334178 WR_PRE = 0x1
3778 12:26:36.334337 WR_PST = 0x0
3779 12:26:36.337273 DBI_WR = 0x0
3780 12:26:36.337425 DBI_RD = 0x0
3781 12:26:36.340472 OTF = 0x1
3782 12:26:36.344154 ===================================
3783 12:26:36.347210 ===================================
3784 12:26:36.347411 ANA top config
3785 12:26:36.351033 ===================================
3786 12:26:36.354008 DLL_ASYNC_EN = 0
3787 12:26:36.357528 ALL_SLAVE_EN = 1
3788 12:26:36.360797 NEW_RANK_MODE = 1
3789 12:26:36.360960 DLL_IDLE_MODE = 1
3790 12:26:36.364066 LP45_APHY_COMB_EN = 1
3791 12:26:36.367484 TX_ODT_DIS = 1
3792 12:26:36.370306 NEW_8X_MODE = 1
3793 12:26:36.373996 ===================================
3794 12:26:36.376911 ===================================
3795 12:26:36.380390 data_rate = 1200
3796 12:26:36.383912 CKR = 1
3797 12:26:36.384075 DQ_P2S_RATIO = 8
3798 12:26:36.386951 ===================================
3799 12:26:36.390716 CA_P2S_RATIO = 8
3800 12:26:36.393701 DQ_CA_OPEN = 0
3801 12:26:36.396758 DQ_SEMI_OPEN = 0
3802 12:26:36.400350 CA_SEMI_OPEN = 0
3803 12:26:36.400502 CA_FULL_RATE = 0
3804 12:26:36.403516 DQ_CKDIV4_EN = 1
3805 12:26:36.407253 CA_CKDIV4_EN = 1
3806 12:26:36.410447 CA_PREDIV_EN = 0
3807 12:26:36.413522 PH8_DLY = 0
3808 12:26:36.416841 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3809 12:26:36.416969 DQ_AAMCK_DIV = 4
3810 12:26:36.420528 CA_AAMCK_DIV = 4
3811 12:26:36.423571 CA_ADMCK_DIV = 4
3812 12:26:36.427228 DQ_TRACK_CA_EN = 0
3813 12:26:36.430239 CA_PICK = 600
3814 12:26:36.433815 CA_MCKIO = 600
3815 12:26:36.436822 MCKIO_SEMI = 0
3816 12:26:36.436949 PLL_FREQ = 2288
3817 12:26:36.440530 DQ_UI_PI_RATIO = 32
3818 12:26:36.443766 CA_UI_PI_RATIO = 0
3819 12:26:36.446877 ===================================
3820 12:26:36.450032 ===================================
3821 12:26:36.453800 memory_type:LPDDR4
3822 12:26:36.453944 GP_NUM : 10
3823 12:26:36.457007 SRAM_EN : 1
3824 12:26:36.460095 MD32_EN : 0
3825 12:26:36.463731 ===================================
3826 12:26:36.463888 [ANA_INIT] >>>>>>>>>>>>>>
3827 12:26:36.467152 <<<<<< [CONFIGURE PHASE]: ANA_TX
3828 12:26:36.470522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3829 12:26:36.473329 ===================================
3830 12:26:36.476859 data_rate = 1200,PCW = 0X5800
3831 12:26:36.480342 ===================================
3832 12:26:36.483845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3833 12:26:36.490270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3834 12:26:36.493285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 12:26:36.500601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3836 12:26:36.503732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3837 12:26:36.506721 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3838 12:26:36.509894 [ANA_INIT] flow start
3839 12:26:36.510027 [ANA_INIT] PLL >>>>>>>>
3840 12:26:36.513647 [ANA_INIT] PLL <<<<<<<<
3841 12:26:36.516775 [ANA_INIT] MIDPI >>>>>>>>
3842 12:26:36.516907 [ANA_INIT] MIDPI <<<<<<<<
3843 12:26:36.520032 [ANA_INIT] DLL >>>>>>>>
3844 12:26:36.523184 [ANA_INIT] flow end
3845 12:26:36.526850 ============ LP4 DIFF to SE enter ============
3846 12:26:36.529851 ============ LP4 DIFF to SE exit ============
3847 12:26:36.533454 [ANA_INIT] <<<<<<<<<<<<<
3848 12:26:36.536425 [Flow] Enable top DCM control >>>>>
3849 12:26:36.540042 [Flow] Enable top DCM control <<<<<
3850 12:26:36.543153 Enable DLL master slave shuffle
3851 12:26:36.546312 ==============================================================
3852 12:26:36.550016 Gating Mode config
3853 12:26:36.556811 ==============================================================
3854 12:26:36.556966 Config description:
3855 12:26:36.566685 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3856 12:26:36.573200 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3857 12:26:36.576199 SELPH_MODE 0: By rank 1: By Phase
3858 12:26:36.582787 ==============================================================
3859 12:26:36.586270 GAT_TRACK_EN = 1
3860 12:26:36.589344 RX_GATING_MODE = 2
3861 12:26:36.593119 RX_GATING_TRACK_MODE = 2
3862 12:26:36.596283 SELPH_MODE = 1
3863 12:26:36.599352 PICG_EARLY_EN = 1
3864 12:26:36.602964 VALID_LAT_VALUE = 1
3865 12:26:36.605944 ==============================================================
3866 12:26:36.609659 Enter into Gating configuration >>>>
3867 12:26:36.612854 Exit from Gating configuration <<<<
3868 12:26:36.615901 Enter into DVFS_PRE_config >>>>>
3869 12:26:36.629559 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3870 12:26:36.629759 Exit from DVFS_PRE_config <<<<<
3871 12:26:36.632719 Enter into PICG configuration >>>>
3872 12:26:36.635797 Exit from PICG configuration <<<<
3873 12:26:36.639344 [RX_INPUT] configuration >>>>>
3874 12:26:36.642912 [RX_INPUT] configuration <<<<<
3875 12:26:36.649142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3876 12:26:36.652859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3877 12:26:36.659110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3878 12:26:36.666104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3879 12:26:36.672872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 12:26:36.679388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 12:26:36.682347 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3882 12:26:36.685935 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3883 12:26:36.689175 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3884 12:26:36.695937 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3885 12:26:36.698998 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3886 12:26:36.702613 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 12:26:36.705632 ===================================
3888 12:26:36.709297 LPDDR4 DRAM CONFIGURATION
3889 12:26:36.712402 ===================================
3890 12:26:36.712582 EX_ROW_EN[0] = 0x0
3891 12:26:36.715449 EX_ROW_EN[1] = 0x0
3892 12:26:36.719162 LP4Y_EN = 0x0
3893 12:26:36.719332 WORK_FSP = 0x0
3894 12:26:36.722263 WL = 0x2
3895 12:26:36.722387 RL = 0x2
3896 12:26:36.725363 BL = 0x2
3897 12:26:36.725560 RPST = 0x0
3898 12:26:36.729109 RD_PRE = 0x0
3899 12:26:36.729235 WR_PRE = 0x1
3900 12:26:36.732313 WR_PST = 0x0
3901 12:26:36.732455 DBI_WR = 0x0
3902 12:26:36.735423 DBI_RD = 0x0
3903 12:26:36.735572 OTF = 0x1
3904 12:26:36.738701 ===================================
3905 12:26:36.742382 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3906 12:26:36.748822 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3907 12:26:36.751995 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3908 12:26:36.755832 ===================================
3909 12:26:36.758874 LPDDR4 DRAM CONFIGURATION
3910 12:26:36.761969 ===================================
3911 12:26:36.762153 EX_ROW_EN[0] = 0x10
3912 12:26:36.765165 EX_ROW_EN[1] = 0x0
3913 12:26:36.768939 LP4Y_EN = 0x0
3914 12:26:36.769130 WORK_FSP = 0x0
3915 12:26:36.771979 WL = 0x2
3916 12:26:36.772185 RL = 0x2
3917 12:26:36.775514 BL = 0x2
3918 12:26:36.775702 RPST = 0x0
3919 12:26:36.778707 RD_PRE = 0x0
3920 12:26:36.778880 WR_PRE = 0x1
3921 12:26:36.781888 WR_PST = 0x0
3922 12:26:36.782100 DBI_WR = 0x0
3923 12:26:36.785533 DBI_RD = 0x0
3924 12:26:36.785734 OTF = 0x1
3925 12:26:36.788634 ===================================
3926 12:26:36.795342 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3927 12:26:36.799613 nWR fixed to 30
3928 12:26:36.802515 [ModeRegInit_LP4] CH0 RK0
3929 12:26:36.802708 [ModeRegInit_LP4] CH0 RK1
3930 12:26:36.806393 [ModeRegInit_LP4] CH1 RK0
3931 12:26:36.809321 [ModeRegInit_LP4] CH1 RK1
3932 12:26:36.809505 match AC timing 17
3933 12:26:36.815833 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3934 12:26:36.818785 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3935 12:26:36.822663 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3936 12:26:36.828789 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3937 12:26:36.832529 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3938 12:26:36.832732 ==
3939 12:26:36.835743 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 12:26:36.838775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 12:26:36.838965 ==
3942 12:26:36.845580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 12:26:36.852218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3944 12:26:36.855379 [CA 0] Center 36 (6~66) winsize 61
3945 12:26:36.859089 [CA 1] Center 36 (6~66) winsize 61
3946 12:26:36.862179 [CA 2] Center 34 (4~65) winsize 62
3947 12:26:36.865264 [CA 3] Center 34 (4~64) winsize 61
3948 12:26:36.869081 [CA 4] Center 34 (4~64) winsize 61
3949 12:26:36.872155 [CA 5] Center 33 (3~64) winsize 62
3950 12:26:36.872337
3951 12:26:36.875204 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3952 12:26:36.875384
3953 12:26:36.879011 [CATrainingPosCal] consider 1 rank data
3954 12:26:36.882148 u2DelayCellTimex100 = 270/100 ps
3955 12:26:36.885345 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3956 12:26:36.888371 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 12:26:36.892142 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 12:26:36.895148 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3959 12:26:36.898724 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3960 12:26:36.905514 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 12:26:36.905671
3962 12:26:36.908501 CA PerBit enable=1, Macro0, CA PI delay=33
3963 12:26:36.908617
3964 12:26:36.911362 [CBTSetCACLKResult] CA Dly = 33
3965 12:26:36.911476 CS Dly: 5 (0~36)
3966 12:26:36.911550 ==
3967 12:26:36.915167 Dram Type= 6, Freq= 0, CH_0, rank 1
3968 12:26:36.921904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 12:26:36.922061 ==
3970 12:26:36.924778 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 12:26:36.931382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3972 12:26:36.934510 [CA 0] Center 35 (5~66) winsize 62
3973 12:26:36.938251 [CA 1] Center 35 (5~66) winsize 62
3974 12:26:36.941480 [CA 2] Center 34 (4~65) winsize 62
3975 12:26:36.944581 [CA 3] Center 34 (4~65) winsize 62
3976 12:26:36.948269 [CA 4] Center 33 (3~64) winsize 62
3977 12:26:36.951292 [CA 5] Center 33 (3~64) winsize 62
3978 12:26:36.951514
3979 12:26:36.954929 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3980 12:26:36.955109
3981 12:26:36.958185 [CATrainingPosCal] consider 2 rank data
3982 12:26:36.961280 u2DelayCellTimex100 = 270/100 ps
3983 12:26:36.964347 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3984 12:26:36.971203 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 12:26:36.974277 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 12:26:36.978018 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3987 12:26:36.981103 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3988 12:26:36.984837 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 12:26:36.984959
3990 12:26:36.987905 CA PerBit enable=1, Macro0, CA PI delay=33
3991 12:26:36.988019
3992 12:26:36.991096 [CBTSetCACLKResult] CA Dly = 33
3993 12:26:36.991227 CS Dly: 5 (0~36)
3994 12:26:36.991340
3995 12:26:36.994718 ----->DramcWriteLeveling(PI) begin...
3996 12:26:36.998082 ==
3997 12:26:37.000937 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 12:26:37.004491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 12:26:37.004646 ==
4000 12:26:37.008121 Write leveling (Byte 0): 33 => 33
4001 12:26:37.011305 Write leveling (Byte 1): 29 => 29
4002 12:26:37.014620 DramcWriteLeveling(PI) end<-----
4003 12:26:37.014782
4004 12:26:37.014887 ==
4005 12:26:37.017669 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 12:26:37.021414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 12:26:37.021579 ==
4008 12:26:37.024331 [Gating] SW mode calibration
4009 12:26:37.030821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4010 12:26:37.037805 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4011 12:26:37.040811 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 12:26:37.044607 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 12:26:37.047617 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 12:26:37.054507 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 12:26:37.057615 0 9 16 | B1->B0 | 3131 2525 | 1 0 | (1 0) (1 1)
4016 12:26:37.061206 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 12:26:37.067948 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 12:26:37.071141 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 12:26:37.074286 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 12:26:37.081039 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 12:26:37.084695 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 12:26:37.087956 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 12:26:37.094230 0 10 16 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
4024 12:26:37.097965 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4025 12:26:37.101093 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 12:26:37.107287 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 12:26:37.110906 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 12:26:37.113927 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 12:26:37.120757 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 12:26:37.124380 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 12:26:37.127191 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4032 12:26:37.133819 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:26:37.137378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:26:37.140950 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:26:37.147665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:26:37.150965 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:26:37.154103 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:26:37.160402 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:26:37.164111 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:26:37.167287 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:26:37.174127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 12:26:37.177129 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 12:26:37.180317 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 12:26:37.187284 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:26:37.190365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:26:37.193422 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:26:37.200222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4048 12:26:37.204008 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 12:26:37.207234 Total UI for P1: 0, mck2ui 16
4050 12:26:37.210100 best dqsien dly found for B0: ( 0, 13, 16)
4051 12:26:37.213217 Total UI for P1: 0, mck2ui 16
4052 12:26:37.216980 best dqsien dly found for B1: ( 0, 13, 16)
4053 12:26:37.219948 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4054 12:26:37.223516 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4055 12:26:37.223659
4056 12:26:37.226592 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4057 12:26:37.230123 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4058 12:26:37.233469 [Gating] SW calibration Done
4059 12:26:37.233625 ==
4060 12:26:37.236462 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 12:26:37.240057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 12:26:37.240221 ==
4063 12:26:37.243162 RX Vref Scan: 0
4064 12:26:37.243322
4065 12:26:37.246621 RX Vref 0 -> 0, step: 1
4066 12:26:37.246739
4067 12:26:37.246813 RX Delay -230 -> 252, step: 16
4068 12:26:37.253394 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4069 12:26:37.257180 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4070 12:26:37.260249 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4071 12:26:37.263245 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4072 12:26:37.269925 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4073 12:26:37.273068 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4074 12:26:37.276849 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4075 12:26:37.279967 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4076 12:26:37.283050 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4077 12:26:37.289845 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4078 12:26:37.293597 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4079 12:26:37.296599 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4080 12:26:37.299753 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4081 12:26:37.306673 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4082 12:26:37.309743 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4083 12:26:37.312886 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4084 12:26:37.313049 ==
4085 12:26:37.316583 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 12:26:37.322792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 12:26:37.322976 ==
4088 12:26:37.323112 DQS Delay:
4089 12:26:37.323237 DQS0 = 0, DQS1 = 0
4090 12:26:37.326398 DQM Delay:
4091 12:26:37.326584 DQM0 = 40, DQM1 = 32
4092 12:26:37.329382 DQ Delay:
4093 12:26:37.333199 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4094 12:26:37.336090 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4095 12:26:37.339575 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4096 12:26:37.343055 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4097 12:26:37.343242
4098 12:26:37.343356
4099 12:26:37.343455 ==
4100 12:26:37.346069 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 12:26:37.349649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 12:26:37.349822 ==
4103 12:26:37.349925
4104 12:26:37.350022
4105 12:26:37.352705 TX Vref Scan disable
4106 12:26:37.352845 == TX Byte 0 ==
4107 12:26:37.359168 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4108 12:26:37.362933 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4109 12:26:37.363108 == TX Byte 1 ==
4110 12:26:37.369071 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4111 12:26:37.372595 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4112 12:26:37.372734 ==
4113 12:26:37.375894 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 12:26:37.379607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 12:26:37.379753 ==
4116 12:26:37.379831
4117 12:26:37.382693
4118 12:26:37.382838 TX Vref Scan disable
4119 12:26:37.386400 == TX Byte 0 ==
4120 12:26:37.389405 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4121 12:26:37.396286 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4122 12:26:37.396444 == TX Byte 1 ==
4123 12:26:37.399677 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4124 12:26:37.405713 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4125 12:26:37.405867
4126 12:26:37.405941 [DATLAT]
4127 12:26:37.406006 Freq=600, CH0 RK0
4128 12:26:37.406068
4129 12:26:37.408844 DATLAT Default: 0x9
4130 12:26:37.412639 0, 0xFFFF, sum = 0
4131 12:26:37.412781 1, 0xFFFF, sum = 0
4132 12:26:37.415584 2, 0xFFFF, sum = 0
4133 12:26:37.415711 3, 0xFFFF, sum = 0
4134 12:26:37.419295 4, 0xFFFF, sum = 0
4135 12:26:37.419458 5, 0xFFFF, sum = 0
4136 12:26:37.422511 6, 0xFFFF, sum = 0
4137 12:26:37.422640 7, 0xFFFF, sum = 0
4138 12:26:37.425551 8, 0x0, sum = 1
4139 12:26:37.425681 9, 0x0, sum = 2
4140 12:26:37.425778 10, 0x0, sum = 3
4141 12:26:37.429322 11, 0x0, sum = 4
4142 12:26:37.429461 best_step = 9
4143 12:26:37.429560
4144 12:26:37.429643 ==
4145 12:26:37.432390 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 12:26:37.439079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 12:26:37.439263 ==
4148 12:26:37.439386 RX Vref Scan: 1
4149 12:26:37.439481
4150 12:26:37.442236 RX Vref 0 -> 0, step: 1
4151 12:26:37.442370
4152 12:26:37.445821 RX Delay -195 -> 252, step: 8
4153 12:26:37.445965
4154 12:26:37.448879 Set Vref, RX VrefLevel [Byte0]: 55
4155 12:26:37.452165 [Byte1]: 53
4156 12:26:37.452302
4157 12:26:37.455299 Final RX Vref Byte 0 = 55 to rank0
4158 12:26:37.458974 Final RX Vref Byte 1 = 53 to rank0
4159 12:26:37.462040 Final RX Vref Byte 0 = 55 to rank1
4160 12:26:37.465666 Final RX Vref Byte 1 = 53 to rank1==
4161 12:26:37.468585 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 12:26:37.472162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 12:26:37.472309 ==
4164 12:26:37.475093 DQS Delay:
4165 12:26:37.475256 DQS0 = 0, DQS1 = 0
4166 12:26:37.478875 DQM Delay:
4167 12:26:37.479048 DQM0 = 42, DQM1 = 35
4168 12:26:37.481922 DQ Delay:
4169 12:26:37.482076 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4170 12:26:37.485035 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4171 12:26:37.488773 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4172 12:26:37.491854 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4173 12:26:37.492022
4174 12:26:37.492129
4175 12:26:37.501890 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c1a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4176 12:26:37.505431 CH0 RK0: MR19=808, MR18=3C1A
4177 12:26:37.511831 CH0_RK0: MR19=0x808, MR18=0x3C1A, DQSOSC=398, MR23=63, INC=165, DEC=110
4178 12:26:37.512064
4179 12:26:37.514943 ----->DramcWriteLeveling(PI) begin...
4180 12:26:37.515126 ==
4181 12:26:37.518620 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 12:26:37.522095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 12:26:37.522267 ==
4184 12:26:37.524997 Write leveling (Byte 0): 32 => 32
4185 12:26:37.528751 Write leveling (Byte 1): 31 => 31
4186 12:26:37.531865 DramcWriteLeveling(PI) end<-----
4187 12:26:37.532006
4188 12:26:37.532080 ==
4189 12:26:37.534936 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 12:26:37.538621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 12:26:37.538794 ==
4192 12:26:37.541666 [Gating] SW mode calibration
4193 12:26:37.548634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4194 12:26:37.554970 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4195 12:26:37.558947 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 12:26:37.561436 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 12:26:37.568108 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 12:26:37.571965 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4199 12:26:37.575025 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4200 12:26:37.581580 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 12:26:37.585268 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 12:26:37.588404 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 12:26:37.594640 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 12:26:37.597961 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 12:26:37.601489 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 12:26:37.608390 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4207 12:26:37.611477 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4208 12:26:37.614555 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 12:26:37.621556 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 12:26:37.624644 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 12:26:37.628388 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 12:26:37.635094 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 12:26:37.638141 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4214 12:26:37.641760 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4215 12:26:37.644703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4216 12:26:37.651538 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:26:37.654551 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:26:37.658331 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:26:37.664867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:26:37.667826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:26:37.671396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 12:26:37.678207 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:26:37.681214 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 12:26:37.684862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:26:37.691521 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 12:26:37.694707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 12:26:37.697858 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:26:37.704769 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 12:26:37.707808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4230 12:26:37.711445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4231 12:26:37.717600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4232 12:26:37.717801 Total UI for P1: 0, mck2ui 16
4233 12:26:37.724537 best dqsien dly found for B0: ( 0, 13, 10)
4234 12:26:37.727626 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4235 12:26:37.730852 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 12:26:37.734064 Total UI for P1: 0, mck2ui 16
4237 12:26:37.737642 best dqsien dly found for B1: ( 0, 13, 18)
4238 12:26:37.740854 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4239 12:26:37.743965 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4240 12:26:37.744192
4241 12:26:37.750599 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4242 12:26:37.754263 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4243 12:26:37.757378 [Gating] SW calibration Done
4244 12:26:37.757524 ==
4245 12:26:37.760590 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 12:26:37.763806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 12:26:37.763947 ==
4248 12:26:37.764027 RX Vref Scan: 0
4249 12:26:37.764102
4250 12:26:37.767097 RX Vref 0 -> 0, step: 1
4251 12:26:37.767279
4252 12:26:37.770837 RX Delay -230 -> 252, step: 16
4253 12:26:37.774273 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4254 12:26:37.777107 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4255 12:26:37.784144 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4256 12:26:37.787584 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4257 12:26:37.790479 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4258 12:26:37.793993 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4259 12:26:37.800586 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4260 12:26:37.803702 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4261 12:26:37.807281 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4262 12:26:37.810351 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4263 12:26:37.817115 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4264 12:26:37.820122 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4265 12:26:37.823276 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4266 12:26:37.826906 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4267 12:26:37.833241 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4268 12:26:37.836978 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4269 12:26:37.837119 ==
4270 12:26:37.840042 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 12:26:37.843247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 12:26:37.843427 ==
4273 12:26:37.846959 DQS Delay:
4274 12:26:37.847110 DQS0 = 0, DQS1 = 0
4275 12:26:37.847210 DQM Delay:
4276 12:26:37.849997 DQM0 = 41, DQM1 = 34
4277 12:26:37.850103 DQ Delay:
4278 12:26:37.853426 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4279 12:26:37.856563 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4280 12:26:37.859741 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4281 12:26:37.863573 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4282 12:26:37.863726
4283 12:26:37.863804
4284 12:26:37.863868 ==
4285 12:26:37.866614 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 12:26:37.873302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 12:26:37.873510 ==
4288 12:26:37.873621
4289 12:26:37.873720
4290 12:26:37.873818 TX Vref Scan disable
4291 12:26:37.876599 == TX Byte 0 ==
4292 12:26:37.880392 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4293 12:26:37.887011 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4294 12:26:37.887216 == TX Byte 1 ==
4295 12:26:37.890085 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4296 12:26:37.896819 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4297 12:26:37.897022 ==
4298 12:26:37.900392 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 12:26:37.903296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 12:26:37.903498 ==
4301 12:26:37.903603
4302 12:26:37.903687
4303 12:26:37.906936 TX Vref Scan disable
4304 12:26:37.909889 == TX Byte 0 ==
4305 12:26:37.913152 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4306 12:26:37.916917 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4307 12:26:37.920001 == TX Byte 1 ==
4308 12:26:37.923094 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4309 12:26:37.926915 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4310 12:26:37.927077
4311 12:26:37.927149 [DATLAT]
4312 12:26:37.930017 Freq=600, CH0 RK1
4313 12:26:37.930171
4314 12:26:37.930244 DATLAT Default: 0x9
4315 12:26:37.933076 0, 0xFFFF, sum = 0
4316 12:26:37.933223 1, 0xFFFF, sum = 0
4317 12:26:37.936346 2, 0xFFFF, sum = 0
4318 12:26:37.940067 3, 0xFFFF, sum = 0
4319 12:26:37.940226 4, 0xFFFF, sum = 0
4320 12:26:37.943144 5, 0xFFFF, sum = 0
4321 12:26:37.943296 6, 0xFFFF, sum = 0
4322 12:26:37.946842 7, 0xFFFF, sum = 0
4323 12:26:37.946999 8, 0x0, sum = 1
4324 12:26:37.949858 9, 0x0, sum = 2
4325 12:26:37.950005 10, 0x0, sum = 3
4326 12:26:37.950080 11, 0x0, sum = 4
4327 12:26:37.953466 best_step = 9
4328 12:26:37.953608
4329 12:26:37.953678 ==
4330 12:26:37.956472 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 12:26:37.960215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 12:26:37.960385 ==
4333 12:26:37.963240 RX Vref Scan: 0
4334 12:26:37.963423
4335 12:26:37.963500 RX Vref 0 -> 0, step: 1
4336 12:26:37.963564
4337 12:26:37.966381 RX Delay -195 -> 252, step: 8
4338 12:26:37.973813 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4339 12:26:37.976836 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4340 12:26:37.980344 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4341 12:26:37.983884 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4342 12:26:37.990597 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4343 12:26:37.993363 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4344 12:26:37.997049 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4345 12:26:37.999951 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4346 12:26:38.006606 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4347 12:26:38.010052 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4348 12:26:38.013611 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4349 12:26:38.016673 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4350 12:26:38.023500 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4351 12:26:38.026693 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4352 12:26:38.029821 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4353 12:26:38.033627 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4354 12:26:38.033826 ==
4355 12:26:38.036617 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 12:26:38.042897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 12:26:38.043119 ==
4358 12:26:38.043233 DQS Delay:
4359 12:26:38.046597 DQS0 = 0, DQS1 = 0
4360 12:26:38.046809 DQM Delay:
4361 12:26:38.046929 DQM0 = 40, DQM1 = 33
4362 12:26:38.049582 DQ Delay:
4363 12:26:38.053333 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4364 12:26:38.056435 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4365 12:26:38.059460 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4366 12:26:38.063102 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =44
4367 12:26:38.063311
4368 12:26:38.063436
4369 12:26:38.069835 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4370 12:26:38.073130 CH0 RK1: MR19=808, MR18=4729
4371 12:26:38.079336 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4372 12:26:38.082962 [RxdqsGatingPostProcess] freq 600
4373 12:26:38.086270 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4374 12:26:38.089538 Pre-setting of DQS Precalculation
4375 12:26:38.096059 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4376 12:26:38.096218 ==
4377 12:26:38.099557 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 12:26:38.102589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 12:26:38.102779 ==
4380 12:26:38.109354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 12:26:38.115701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 12:26:38.119053 [CA 0] Center 35 (5~66) winsize 62
4383 12:26:38.122668 [CA 1] Center 35 (5~66) winsize 62
4384 12:26:38.125732 [CA 2] Center 33 (3~64) winsize 62
4385 12:26:38.128828 [CA 3] Center 33 (3~64) winsize 62
4386 12:26:38.132577 [CA 4] Center 33 (3~64) winsize 62
4387 12:26:38.135604 [CA 5] Center 33 (2~64) winsize 63
4388 12:26:38.135799
4389 12:26:38.138664 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 12:26:38.138848
4391 12:26:38.142578 [CATrainingPosCal] consider 1 rank data
4392 12:26:38.145546 u2DelayCellTimex100 = 270/100 ps
4393 12:26:38.148798 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 12:26:38.152557 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 12:26:38.155740 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 12:26:38.158911 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 12:26:38.161984 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 12:26:38.165593 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4399 12:26:38.165792
4400 12:26:38.172234 CA PerBit enable=1, Macro0, CA PI delay=33
4401 12:26:38.172444
4402 12:26:38.172554 [CBTSetCACLKResult] CA Dly = 33
4403 12:26:38.175489 CS Dly: 5 (0~36)
4404 12:26:38.175653 ==
4405 12:26:38.179206 Dram Type= 6, Freq= 0, CH_1, rank 1
4406 12:26:38.182423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 12:26:38.182608 ==
4408 12:26:38.189128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 12:26:38.195739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4410 12:26:38.199298 [CA 0] Center 35 (5~66) winsize 62
4411 12:26:38.202492 [CA 1] Center 35 (5~66) winsize 62
4412 12:26:38.205394 [CA 2] Center 34 (3~65) winsize 63
4413 12:26:38.209049 [CA 3] Center 33 (3~64) winsize 62
4414 12:26:38.211975 [CA 4] Center 34 (3~65) winsize 63
4415 12:26:38.215570 [CA 5] Center 33 (3~64) winsize 62
4416 12:26:38.215751
4417 12:26:38.219151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4418 12:26:38.219320
4419 12:26:38.222001 [CATrainingPosCal] consider 2 rank data
4420 12:26:38.225530 u2DelayCellTimex100 = 270/100 ps
4421 12:26:38.229105 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 12:26:38.232256 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4423 12:26:38.235379 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4424 12:26:38.239068 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 12:26:38.242191 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 12:26:38.245409 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 12:26:38.245573
4428 12:26:38.251774 CA PerBit enable=1, Macro0, CA PI delay=33
4429 12:26:38.251941
4430 12:26:38.255363 [CBTSetCACLKResult] CA Dly = 33
4431 12:26:38.255515 CS Dly: 5 (0~36)
4432 12:26:38.255589
4433 12:26:38.258560 ----->DramcWriteLeveling(PI) begin...
4434 12:26:38.258704 ==
4435 12:26:38.261747 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 12:26:38.265533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 12:26:38.268596 ==
4438 12:26:38.268751 Write leveling (Byte 0): 30 => 30
4439 12:26:38.272170 Write leveling (Byte 1): 30 => 30
4440 12:26:38.275286 DramcWriteLeveling(PI) end<-----
4441 12:26:38.275458
4442 12:26:38.275534 ==
4443 12:26:38.278298 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 12:26:38.285416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 12:26:38.285585 ==
4446 12:26:38.285657 [Gating] SW mode calibration
4447 12:26:38.295099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4448 12:26:38.298201 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4449 12:26:38.304699 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4450 12:26:38.308260 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4451 12:26:38.311402 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4452 12:26:38.314959 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
4453 12:26:38.321699 0 9 16 | B1->B0 | 2b2b 2828 | 1 0 | (1 1) (1 1)
4454 12:26:38.324869 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4455 12:26:38.328458 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 12:26:38.334984 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4457 12:26:38.338074 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 12:26:38.341287 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 12:26:38.348236 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 12:26:38.351486 0 10 12 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
4461 12:26:38.354582 0 10 16 | B1->B0 | 4343 4242 | 0 0 | (0 0) (0 0)
4462 12:26:38.361398 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 12:26:38.365097 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 12:26:38.368362 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 12:26:38.374927 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 12:26:38.378012 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 12:26:38.381251 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 12:26:38.387977 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 12:26:38.391142 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4470 12:26:38.394857 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:26:38.401047 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:26:38.404729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:26:38.407814 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:26:38.414500 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:26:38.418072 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:26:38.420974 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:26:38.427636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:26:38.430857 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:26:38.434397 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:26:38.440825 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:26:38.444488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:26:38.447456 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:26:38.454291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:26:38.457425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:26:38.461211 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4486 12:26:38.464419 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 12:26:38.467558 Total UI for P1: 0, mck2ui 16
4488 12:26:38.471299 best dqsien dly found for B0: ( 0, 13, 16)
4489 12:26:38.474493 Total UI for P1: 0, mck2ui 16
4490 12:26:38.477456 best dqsien dly found for B1: ( 0, 13, 16)
4491 12:26:38.481023 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4492 12:26:38.487453 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4493 12:26:38.487610
4494 12:26:38.491150 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4495 12:26:38.494212 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4496 12:26:38.497366 [Gating] SW calibration Done
4497 12:26:38.497510 ==
4498 12:26:38.500968 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 12:26:38.504145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 12:26:38.504284 ==
4501 12:26:38.507246 RX Vref Scan: 0
4502 12:26:38.507409
4503 12:26:38.507488 RX Vref 0 -> 0, step: 1
4504 12:26:38.507553
4505 12:26:38.511083 RX Delay -230 -> 252, step: 16
4506 12:26:38.514078 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4507 12:26:38.521160 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4508 12:26:38.524039 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4509 12:26:38.527652 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4510 12:26:38.530665 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4511 12:26:38.534440 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4512 12:26:38.541195 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4513 12:26:38.544145 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4514 12:26:38.547612 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4515 12:26:38.550596 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4516 12:26:38.557423 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4517 12:26:38.560551 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4518 12:26:38.564265 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4519 12:26:38.567298 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4520 12:26:38.574128 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4521 12:26:38.577246 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4522 12:26:38.577415 ==
4523 12:26:38.581136 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 12:26:38.583875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 12:26:38.584014 ==
4526 12:26:38.587494 DQS Delay:
4527 12:26:38.587632 DQS0 = 0, DQS1 = 0
4528 12:26:38.587729 DQM Delay:
4529 12:26:38.590743 DQM0 = 40, DQM1 = 33
4530 12:26:38.590871 DQ Delay:
4531 12:26:38.593803 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4532 12:26:38.597444 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =33
4533 12:26:38.600473 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4534 12:26:38.604051 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4535 12:26:38.604238
4536 12:26:38.604321
4537 12:26:38.604387 ==
4538 12:26:38.607108 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 12:26:38.614004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 12:26:38.614158 ==
4541 12:26:38.614231
4542 12:26:38.614296
4543 12:26:38.614357 TX Vref Scan disable
4544 12:26:38.617255 == TX Byte 0 ==
4545 12:26:38.620758 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 12:26:38.627001 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 12:26:38.627165 == TX Byte 1 ==
4548 12:26:38.630470 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4549 12:26:38.636917 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4550 12:26:38.637088 ==
4551 12:26:38.640537 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 12:26:38.643535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 12:26:38.643780 ==
4554 12:26:38.643902
4555 12:26:38.644003
4556 12:26:38.647156 TX Vref Scan disable
4557 12:26:38.647393 == TX Byte 0 ==
4558 12:26:38.653616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4559 12:26:38.657028 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4560 12:26:38.660624 == TX Byte 1 ==
4561 12:26:38.663653 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4562 12:26:38.666798 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4563 12:26:38.666932
4564 12:26:38.667007 [DATLAT]
4565 12:26:38.670530 Freq=600, CH1 RK0
4566 12:26:38.670654
4567 12:26:38.670726 DATLAT Default: 0x9
4568 12:26:38.673684 0, 0xFFFF, sum = 0
4569 12:26:38.676805 1, 0xFFFF, sum = 0
4570 12:26:38.677043 2, 0xFFFF, sum = 0
4571 12:26:38.680599 3, 0xFFFF, sum = 0
4572 12:26:38.680744 4, 0xFFFF, sum = 0
4573 12:26:38.683628 5, 0xFFFF, sum = 0
4574 12:26:38.683747 6, 0xFFFF, sum = 0
4575 12:26:38.686864 7, 0xFFFF, sum = 0
4576 12:26:38.686983 8, 0x0, sum = 1
4577 12:26:38.689786 9, 0x0, sum = 2
4578 12:26:38.689991 10, 0x0, sum = 3
4579 12:26:38.690137 11, 0x0, sum = 4
4580 12:26:38.693905 best_step = 9
4581 12:26:38.694140
4582 12:26:38.694293 ==
4583 12:26:38.696647 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 12:26:38.699754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 12:26:38.699878 ==
4586 12:26:38.703464 RX Vref Scan: 1
4587 12:26:38.703671
4588 12:26:38.703817 RX Vref 0 -> 0, step: 1
4589 12:26:38.706590
4590 12:26:38.706807 RX Delay -195 -> 252, step: 8
4591 12:26:38.706956
4592 12:26:38.709808 Set Vref, RX VrefLevel [Byte0]: 57
4593 12:26:38.712986 [Byte1]: 45
4594 12:26:38.717438
4595 12:26:38.717580 Final RX Vref Byte 0 = 57 to rank0
4596 12:26:38.721154 Final RX Vref Byte 1 = 45 to rank0
4597 12:26:38.724188 Final RX Vref Byte 0 = 57 to rank1
4598 12:26:38.727244 Final RX Vref Byte 1 = 45 to rank1==
4599 12:26:38.730969 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 12:26:38.737320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 12:26:38.737510 ==
4602 12:26:38.737618 DQS Delay:
4603 12:26:38.740893 DQS0 = 0, DQS1 = 0
4604 12:26:38.741060 DQM Delay:
4605 12:26:38.741162 DQM0 = 40, DQM1 = 32
4606 12:26:38.743997 DQ Delay:
4607 12:26:38.747793 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4608 12:26:38.750589 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4609 12:26:38.754065 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4610 12:26:38.757257 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =36
4611 12:26:38.757458
4612 12:26:38.757575
4613 12:26:38.763769 [DQSOSCAuto] RK0, (LSB)MR18= 0x4309, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4614 12:26:38.767245 CH1 RK0: MR19=808, MR18=4309
4615 12:26:38.773540 CH1_RK0: MR19=0x808, MR18=0x4309, DQSOSC=397, MR23=63, INC=166, DEC=110
4616 12:26:38.773748
4617 12:26:38.777256 ----->DramcWriteLeveling(PI) begin...
4618 12:26:38.777465 ==
4619 12:26:38.780328 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 12:26:38.783539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 12:26:38.783723 ==
4622 12:26:38.786543 Write leveling (Byte 0): 31 => 31
4623 12:26:38.790283 Write leveling (Byte 1): 30 => 30
4624 12:26:38.793215 DramcWriteLeveling(PI) end<-----
4625 12:26:38.793405
4626 12:26:38.793521 ==
4627 12:26:38.796515 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 12:26:38.800385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 12:26:38.803497 ==
4630 12:26:38.803670 [Gating] SW mode calibration
4631 12:26:38.813306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4632 12:26:38.816356 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4633 12:26:38.820136 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 12:26:38.826973 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 12:26:38.829984 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4636 12:26:38.833283 0 9 12 | B1->B0 | 3030 2929 | 0 0 | (0 0) (1 1)
4637 12:26:38.840207 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
4638 12:26:38.843162 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 12:26:38.846276 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 12:26:38.853038 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 12:26:38.856643 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4642 12:26:38.859527 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 12:26:38.866210 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4644 12:26:38.869292 0 10 12 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (0 0)
4645 12:26:38.872890 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4646 12:26:38.879803 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 12:26:38.882773 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 12:26:38.885844 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 12:26:38.892733 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 12:26:38.895777 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 12:26:38.899259 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 12:26:38.906078 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4653 12:26:38.909177 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:26:38.912980 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:26:38.919197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:26:38.922445 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:26:38.925635 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:26:38.932326 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:26:38.936115 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:26:38.939156 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:26:38.945739 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 12:26:38.949124 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 12:26:38.952622 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 12:26:38.955656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:26:38.962647 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:26:38.965673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:26:38.969271 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4668 12:26:38.975795 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4669 12:26:38.978947 Total UI for P1: 0, mck2ui 16
4670 12:26:38.982489 best dqsien dly found for B0: ( 0, 13, 8)
4671 12:26:38.985537 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 12:26:38.989400 Total UI for P1: 0, mck2ui 16
4673 12:26:38.992502 best dqsien dly found for B1: ( 0, 13, 14)
4674 12:26:38.995578 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4675 12:26:38.998811 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4676 12:26:38.998975
4677 12:26:39.002241 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4678 12:26:39.005812 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4679 12:26:39.008931 [Gating] SW calibration Done
4680 12:26:39.009114 ==
4681 12:26:39.012649 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 12:26:39.018946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 12:26:39.019147 ==
4684 12:26:39.019260 RX Vref Scan: 0
4685 12:26:39.019362
4686 12:26:39.022057 RX Vref 0 -> 0, step: 1
4687 12:26:39.022186
4688 12:26:39.025228 RX Delay -230 -> 252, step: 16
4689 12:26:39.029008 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4690 12:26:39.032065 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4691 12:26:39.035259 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4692 12:26:39.042207 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4693 12:26:39.045345 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4694 12:26:39.048551 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4695 12:26:39.052221 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4696 12:26:39.058563 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4697 12:26:39.062015 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4698 12:26:39.065496 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4699 12:26:39.068335 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4700 12:26:39.071815 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4701 12:26:39.078273 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4702 12:26:39.081824 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4703 12:26:39.085463 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4704 12:26:39.088660 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4705 12:26:39.091786 ==
4706 12:26:39.091965 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 12:26:39.098589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 12:26:39.098785 ==
4709 12:26:39.098894 DQS Delay:
4710 12:26:39.101787 DQS0 = 0, DQS1 = 0
4711 12:26:39.101927 DQM Delay:
4712 12:26:39.104888 DQM0 = 37, DQM1 = 34
4713 12:26:39.105050 DQ Delay:
4714 12:26:39.108357 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4715 12:26:39.111382 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4716 12:26:39.115095 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4717 12:26:39.118151 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4718 12:26:39.118332
4719 12:26:39.118446
4720 12:26:39.118544 ==
4721 12:26:39.121333 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 12:26:39.125137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 12:26:39.125301 ==
4724 12:26:39.125412
4725 12:26:39.125510
4726 12:26:39.128186 TX Vref Scan disable
4727 12:26:39.131392 == TX Byte 0 ==
4728 12:26:39.134910 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4729 12:26:39.138065 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4730 12:26:39.141770 == TX Byte 1 ==
4731 12:26:39.144812 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4732 12:26:39.147813 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4733 12:26:39.148008 ==
4734 12:26:39.151545 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 12:26:39.157746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 12:26:39.157947 ==
4737 12:26:39.158062
4738 12:26:39.158160
4739 12:26:39.158257 TX Vref Scan disable
4740 12:26:39.162035 == TX Byte 0 ==
4741 12:26:39.165471 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4742 12:26:39.172343 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4743 12:26:39.172556 == TX Byte 1 ==
4744 12:26:39.175207 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4745 12:26:39.181795 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4746 12:26:39.181956
4747 12:26:39.182032 [DATLAT]
4748 12:26:39.182096 Freq=600, CH1 RK1
4749 12:26:39.182157
4750 12:26:39.185284 DATLAT Default: 0x9
4751 12:26:39.185397 0, 0xFFFF, sum = 0
4752 12:26:39.188917 1, 0xFFFF, sum = 0
4753 12:26:39.189065 2, 0xFFFF, sum = 0
4754 12:26:39.191936 3, 0xFFFF, sum = 0
4755 12:26:39.195209 4, 0xFFFF, sum = 0
4756 12:26:39.195404 5, 0xFFFF, sum = 0
4757 12:26:39.198433 6, 0xFFFF, sum = 0
4758 12:26:39.198584 7, 0xFFFF, sum = 0
4759 12:26:39.202099 8, 0x0, sum = 1
4760 12:26:39.202255 9, 0x0, sum = 2
4761 12:26:39.202332 10, 0x0, sum = 3
4762 12:26:39.205231 11, 0x0, sum = 4
4763 12:26:39.205347 best_step = 9
4764 12:26:39.205419
4765 12:26:39.205482 ==
4766 12:26:39.208281 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 12:26:39.215028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 12:26:39.215198 ==
4769 12:26:39.215275 RX Vref Scan: 0
4770 12:26:39.215340
4771 12:26:39.218161 RX Vref 0 -> 0, step: 1
4772 12:26:39.218304
4773 12:26:39.221971 RX Delay -179 -> 252, step: 8
4774 12:26:39.225130 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4775 12:26:39.232002 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4776 12:26:39.235138 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4777 12:26:39.238198 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4778 12:26:39.241387 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4779 12:26:39.248294 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4780 12:26:39.251309 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4781 12:26:39.255050 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4782 12:26:39.258247 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4783 12:26:39.261263 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4784 12:26:39.268058 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4785 12:26:39.271477 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4786 12:26:39.274999 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4787 12:26:39.278456 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4788 12:26:39.284724 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4789 12:26:39.287876 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4790 12:26:39.288045 ==
4791 12:26:39.291539 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 12:26:39.294614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 12:26:39.294798 ==
4794 12:26:39.298312 DQS Delay:
4795 12:26:39.298506 DQS0 = 0, DQS1 = 0
4796 12:26:39.298621 DQM Delay:
4797 12:26:39.301323 DQM0 = 38, DQM1 = 31
4798 12:26:39.301464 DQ Delay:
4799 12:26:39.304924 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4800 12:26:39.307985 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4801 12:26:39.311667 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4802 12:26:39.314773 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4803 12:26:39.314957
4804 12:26:39.315067
4805 12:26:39.324473 [DQSOSCAuto] RK1, (LSB)MR18= 0x3444, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4806 12:26:39.324679 CH1 RK1: MR19=808, MR18=3444
4807 12:26:39.331284 CH1_RK1: MR19=0x808, MR18=0x3444, DQSOSC=396, MR23=63, INC=167, DEC=111
4808 12:26:39.334524 [RxdqsGatingPostProcess] freq 600
4809 12:26:39.341116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4810 12:26:39.344388 Pre-setting of DQS Precalculation
4811 12:26:39.348237 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4812 12:26:39.354570 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4813 12:26:39.364485 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4814 12:26:39.364644
4815 12:26:39.364715
4816 12:26:39.367645 [Calibration Summary] 1200 Mbps
4817 12:26:39.367778 CH 0, Rank 0
4818 12:26:39.370671 SW Impedance : PASS
4819 12:26:39.370782 DUTY Scan : NO K
4820 12:26:39.374414 ZQ Calibration : PASS
4821 12:26:39.377467 Jitter Meter : NO K
4822 12:26:39.377628 CBT Training : PASS
4823 12:26:39.381200 Write leveling : PASS
4824 12:26:39.384037 RX DQS gating : PASS
4825 12:26:39.384165 RX DQ/DQS(RDDQC) : PASS
4826 12:26:39.387504 TX DQ/DQS : PASS
4827 12:26:39.390441 RX DATLAT : PASS
4828 12:26:39.390628 RX DQ/DQS(Engine): PASS
4829 12:26:39.394232 TX OE : NO K
4830 12:26:39.394428 All Pass.
4831 12:26:39.394541
4832 12:26:39.397225 CH 0, Rank 1
4833 12:26:39.397363 SW Impedance : PASS
4834 12:26:39.400926 DUTY Scan : NO K
4835 12:26:39.401082 ZQ Calibration : PASS
4836 12:26:39.403884 Jitter Meter : NO K
4837 12:26:39.407520 CBT Training : PASS
4838 12:26:39.407707 Write leveling : PASS
4839 12:26:39.410588 RX DQS gating : PASS
4840 12:26:39.414222 RX DQ/DQS(RDDQC) : PASS
4841 12:26:39.414376 TX DQ/DQS : PASS
4842 12:26:39.417131 RX DATLAT : PASS
4843 12:26:39.420823 RX DQ/DQS(Engine): PASS
4844 12:26:39.420976 TX OE : NO K
4845 12:26:39.423681 All Pass.
4846 12:26:39.423822
4847 12:26:39.423895 CH 1, Rank 0
4848 12:26:39.427369 SW Impedance : PASS
4849 12:26:39.427512 DUTY Scan : NO K
4850 12:26:39.430428 ZQ Calibration : PASS
4851 12:26:39.434206 Jitter Meter : NO K
4852 12:26:39.434359 CBT Training : PASS
4853 12:26:39.437379 Write leveling : PASS
4854 12:26:39.440426 RX DQS gating : PASS
4855 12:26:39.440596 RX DQ/DQS(RDDQC) : PASS
4856 12:26:39.444126 TX DQ/DQS : PASS
4857 12:26:39.447324 RX DATLAT : PASS
4858 12:26:39.447495 RX DQ/DQS(Engine): PASS
4859 12:26:39.450381 TX OE : NO K
4860 12:26:39.450532 All Pass.
4861 12:26:39.450603
4862 12:26:39.453553 CH 1, Rank 1
4863 12:26:39.453705 SW Impedance : PASS
4864 12:26:39.457238 DUTY Scan : NO K
4865 12:26:39.457414 ZQ Calibration : PASS
4866 12:26:39.460372 Jitter Meter : NO K
4867 12:26:39.463373 CBT Training : PASS
4868 12:26:39.463510 Write leveling : PASS
4869 12:26:39.466607 RX DQS gating : PASS
4870 12:26:39.469663 RX DQ/DQS(RDDQC) : PASS
4871 12:26:39.469837 TX DQ/DQS : PASS
4872 12:26:39.473405 RX DATLAT : PASS
4873 12:26:39.476579 RX DQ/DQS(Engine): PASS
4874 12:26:39.476736 TX OE : NO K
4875 12:26:39.480288 All Pass.
4876 12:26:39.480460
4877 12:26:39.480560 DramC Write-DBI off
4878 12:26:39.483261 PER_BANK_REFRESH: Hybrid Mode
4879 12:26:39.486436 TX_TRACKING: ON
4880 12:26:39.493039 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4881 12:26:39.496523 [FAST_K] Save calibration result to emmc
4882 12:26:39.500211 dramc_set_vcore_voltage set vcore to 662500
4883 12:26:39.503391 Read voltage for 933, 3
4884 12:26:39.503530 Vio18 = 0
4885 12:26:39.506396 Vcore = 662500
4886 12:26:39.506509 Vdram = 0
4887 12:26:39.506580 Vddq = 0
4888 12:26:39.509850 Vmddr = 0
4889 12:26:39.513066 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4890 12:26:39.519587 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4891 12:26:39.519778 MEM_TYPE=3, freq_sel=17
4892 12:26:39.523238 sv_algorithm_assistance_LP4_1600
4893 12:26:39.529866 ============ PULL DRAM RESETB DOWN ============
4894 12:26:39.532978 ========== PULL DRAM RESETB DOWN end =========
4895 12:26:39.536166 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4896 12:26:39.539367 ===================================
4897 12:26:39.542988 LPDDR4 DRAM CONFIGURATION
4898 12:26:39.546099 ===================================
4899 12:26:39.549234 EX_ROW_EN[0] = 0x0
4900 12:26:39.549388 EX_ROW_EN[1] = 0x0
4901 12:26:39.552944 LP4Y_EN = 0x0
4902 12:26:39.553117 WORK_FSP = 0x0
4903 12:26:39.556060 WL = 0x3
4904 12:26:39.556167 RL = 0x3
4905 12:26:39.559200 BL = 0x2
4906 12:26:39.559303 RPST = 0x0
4907 12:26:39.563027 RD_PRE = 0x0
4908 12:26:39.563205 WR_PRE = 0x1
4909 12:26:39.566221 WR_PST = 0x0
4910 12:26:39.566364 DBI_WR = 0x0
4911 12:26:39.569354 DBI_RD = 0x0
4912 12:26:39.569477 OTF = 0x1
4913 12:26:39.573035 ===================================
4914 12:26:39.576074 ===================================
4915 12:26:39.579184 ANA top config
4916 12:26:39.582946 ===================================
4917 12:26:39.586179 DLL_ASYNC_EN = 0
4918 12:26:39.586360 ALL_SLAVE_EN = 1
4919 12:26:39.589261 NEW_RANK_MODE = 1
4920 12:26:39.592968 DLL_IDLE_MODE = 1
4921 12:26:39.595965 LP45_APHY_COMB_EN = 1
4922 12:26:39.596129 TX_ODT_DIS = 1
4923 12:26:39.599515 NEW_8X_MODE = 1
4924 12:26:39.602722 ===================================
4925 12:26:39.605837 ===================================
4926 12:26:39.609503 data_rate = 1866
4927 12:26:39.612458 CKR = 1
4928 12:26:39.616121 DQ_P2S_RATIO = 8
4929 12:26:39.619004 ===================================
4930 12:26:39.622613 CA_P2S_RATIO = 8
4931 12:26:39.622756 DQ_CA_OPEN = 0
4932 12:26:39.625898 DQ_SEMI_OPEN = 0
4933 12:26:39.629077 CA_SEMI_OPEN = 0
4934 12:26:39.632499 CA_FULL_RATE = 0
4935 12:26:39.636115 DQ_CKDIV4_EN = 1
4936 12:26:39.639245 CA_CKDIV4_EN = 1
4937 12:26:39.639396 CA_PREDIV_EN = 0
4938 12:26:39.642310 PH8_DLY = 0
4939 12:26:39.645905 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4940 12:26:39.649059 DQ_AAMCK_DIV = 4
4941 12:26:39.652096 CA_AAMCK_DIV = 4
4942 12:26:39.655885 CA_ADMCK_DIV = 4
4943 12:26:39.656034 DQ_TRACK_CA_EN = 0
4944 12:26:39.658938 CA_PICK = 933
4945 12:26:39.662081 CA_MCKIO = 933
4946 12:26:39.665810 MCKIO_SEMI = 0
4947 12:26:39.668853 PLL_FREQ = 3732
4948 12:26:39.672576 DQ_UI_PI_RATIO = 32
4949 12:26:39.675731 CA_UI_PI_RATIO = 0
4950 12:26:39.678841 ===================================
4951 12:26:39.682561 ===================================
4952 12:26:39.682808 memory_type:LPDDR4
4953 12:26:39.685740 GP_NUM : 10
4954 12:26:39.685958 SRAM_EN : 1
4955 12:26:39.688863 MD32_EN : 0
4956 12:26:39.692101 ===================================
4957 12:26:39.695807 [ANA_INIT] >>>>>>>>>>>>>>
4958 12:26:39.698982 <<<<<< [CONFIGURE PHASE]: ANA_TX
4959 12:26:39.701982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4960 12:26:39.705656 ===================================
4961 12:26:39.708589 data_rate = 1866,PCW = 0X8f00
4962 12:26:39.712068 ===================================
4963 12:26:39.715700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4964 12:26:39.718735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4965 12:26:39.725401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4966 12:26:39.728553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4967 12:26:39.732142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4968 12:26:39.735394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4969 12:26:39.738418 [ANA_INIT] flow start
4970 12:26:39.741956 [ANA_INIT] PLL >>>>>>>>
4971 12:26:39.742162 [ANA_INIT] PLL <<<<<<<<
4972 12:26:39.745065 [ANA_INIT] MIDPI >>>>>>>>
4973 12:26:39.749288 [ANA_INIT] MIDPI <<<<<<<<
4974 12:26:39.749453 [ANA_INIT] DLL >>>>>>>>
4975 12:26:39.751838 [ANA_INIT] flow end
4976 12:26:39.755758 ============ LP4 DIFF to SE enter ============
4977 12:26:39.758797 ============ LP4 DIFF to SE exit ============
4978 12:26:39.761795 [ANA_INIT] <<<<<<<<<<<<<
4979 12:26:39.765531 [Flow] Enable top DCM control >>>>>
4980 12:26:39.768647 [Flow] Enable top DCM control <<<<<
4981 12:26:39.771836 Enable DLL master slave shuffle
4982 12:26:39.778541 ==============================================================
4983 12:26:39.778699 Gating Mode config
4984 12:26:39.785392 ==============================================================
4985 12:26:39.788444 Config description:
4986 12:26:39.795321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4987 12:26:39.801538 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4988 12:26:39.808391 SELPH_MODE 0: By rank 1: By Phase
4989 12:26:39.812139 ==============================================================
4990 12:26:39.814926 GAT_TRACK_EN = 1
4991 12:26:39.818285 RX_GATING_MODE = 2
4992 12:26:39.821895 RX_GATING_TRACK_MODE = 2
4993 12:26:39.824878 SELPH_MODE = 1
4994 12:26:39.828520 PICG_EARLY_EN = 1
4995 12:26:39.831912 VALID_LAT_VALUE = 1
4996 12:26:39.838416 ==============================================================
4997 12:26:39.841354 Enter into Gating configuration >>>>
4998 12:26:39.844854 Exit from Gating configuration <<<<
4999 12:26:39.848488 Enter into DVFS_PRE_config >>>>>
5000 12:26:39.858512 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5001 12:26:39.861722 Exit from DVFS_PRE_config <<<<<
5002 12:26:39.864767 Enter into PICG configuration >>>>
5003 12:26:39.867807 Exit from PICG configuration <<<<
5004 12:26:39.871633 [RX_INPUT] configuration >>>>>
5005 12:26:39.871868 [RX_INPUT] configuration <<<<<
5006 12:26:39.877857 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5007 12:26:39.884626 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5008 12:26:39.888301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 12:26:39.894554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 12:26:39.901518 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 12:26:39.908290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 12:26:39.911428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5013 12:26:39.914493 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5014 12:26:39.921095 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5015 12:26:39.924689 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5016 12:26:39.928094 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5017 12:26:39.934818 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5018 12:26:39.937549 ===================================
5019 12:26:39.937740 LPDDR4 DRAM CONFIGURATION
5020 12:26:39.941068 ===================================
5021 12:26:39.944506 EX_ROW_EN[0] = 0x0
5022 12:26:39.944635 EX_ROW_EN[1] = 0x0
5023 12:26:39.947570 LP4Y_EN = 0x0
5024 12:26:39.947710 WORK_FSP = 0x0
5025 12:26:39.950990 WL = 0x3
5026 12:26:39.954484 RL = 0x3
5027 12:26:39.954618 BL = 0x2
5028 12:26:39.957962 RPST = 0x0
5029 12:26:39.958112 RD_PRE = 0x0
5030 12:26:39.960896 WR_PRE = 0x1
5031 12:26:39.961004 WR_PST = 0x0
5032 12:26:39.964146 DBI_WR = 0x0
5033 12:26:39.964291 DBI_RD = 0x0
5034 12:26:39.967961 OTF = 0x1
5035 12:26:39.971043 ===================================
5036 12:26:39.974144 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5037 12:26:39.977951 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5038 12:26:39.981033 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 12:26:39.984123 ===================================
5040 12:26:39.987284 LPDDR4 DRAM CONFIGURATION
5041 12:26:39.991094 ===================================
5042 12:26:39.994153 EX_ROW_EN[0] = 0x10
5043 12:26:39.994312 EX_ROW_EN[1] = 0x0
5044 12:26:39.997327 LP4Y_EN = 0x0
5045 12:26:39.997460 WORK_FSP = 0x0
5046 12:26:40.001035 WL = 0x3
5047 12:26:40.001172 RL = 0x3
5048 12:26:40.004232 BL = 0x2
5049 12:26:40.004381 RPST = 0x0
5050 12:26:40.007307 RD_PRE = 0x0
5051 12:26:40.011055 WR_PRE = 0x1
5052 12:26:40.011216 WR_PST = 0x0
5053 12:26:40.014182 DBI_WR = 0x0
5054 12:26:40.014305 DBI_RD = 0x0
5055 12:26:40.017309 OTF = 0x1
5056 12:26:40.021155 ===================================
5057 12:26:40.024212 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5058 12:26:40.029237 nWR fixed to 30
5059 12:26:40.032444 [ModeRegInit_LP4] CH0 RK0
5060 12:26:40.032649 [ModeRegInit_LP4] CH0 RK1
5061 12:26:40.036087 [ModeRegInit_LP4] CH1 RK0
5062 12:26:40.039687 [ModeRegInit_LP4] CH1 RK1
5063 12:26:40.039896 match AC timing 9
5064 12:26:40.046004 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5065 12:26:40.048923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5066 12:26:40.052479 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5067 12:26:40.059374 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5068 12:26:40.062367 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5069 12:26:40.062532 ==
5070 12:26:40.065922 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 12:26:40.068840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 12:26:40.068969 ==
5073 12:26:40.075849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 12:26:40.082098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5075 12:26:40.085742 [CA 0] Center 38 (8~69) winsize 62
5076 12:26:40.088849 [CA 1] Center 38 (7~69) winsize 63
5077 12:26:40.092448 [CA 2] Center 35 (5~66) winsize 62
5078 12:26:40.095578 [CA 3] Center 34 (4~65) winsize 62
5079 12:26:40.098707 [CA 4] Center 34 (4~65) winsize 62
5080 12:26:40.102510 [CA 5] Center 34 (4~64) winsize 61
5081 12:26:40.102695
5082 12:26:40.105613 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5083 12:26:40.105811
5084 12:26:40.108711 [CATrainingPosCal] consider 1 rank data
5085 12:26:40.112485 u2DelayCellTimex100 = 270/100 ps
5086 12:26:40.115602 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5087 12:26:40.118706 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5088 12:26:40.121905 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5089 12:26:40.125636 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5090 12:26:40.128812 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5091 12:26:40.132002 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5092 12:26:40.135712
5093 12:26:40.138756 CA PerBit enable=1, Macro0, CA PI delay=34
5094 12:26:40.138952
5095 12:26:40.142320 [CBTSetCACLKResult] CA Dly = 34
5096 12:26:40.142519 CS Dly: 6 (0~37)
5097 12:26:40.142635 ==
5098 12:26:40.145087 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 12:26:40.149117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 12:26:40.149318 ==
5101 12:26:40.155959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5102 12:26:40.161875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5103 12:26:40.165531 [CA 0] Center 38 (8~69) winsize 62
5104 12:26:40.168460 [CA 1] Center 38 (7~69) winsize 63
5105 12:26:40.172391 [CA 2] Center 35 (5~66) winsize 62
5106 12:26:40.175268 [CA 3] Center 35 (5~66) winsize 62
5107 12:26:40.178435 [CA 4] Center 34 (3~65) winsize 63
5108 12:26:40.182237 [CA 5] Center 33 (3~64) winsize 62
5109 12:26:40.182399
5110 12:26:40.185407 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5111 12:26:40.185541
5112 12:26:40.188468 [CATrainingPosCal] consider 2 rank data
5113 12:26:40.191813 u2DelayCellTimex100 = 270/100 ps
5114 12:26:40.195461 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5115 12:26:40.198674 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5116 12:26:40.201854 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5117 12:26:40.205147 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5118 12:26:40.208366 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5119 12:26:40.215281 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5120 12:26:40.215476
5121 12:26:40.218514 CA PerBit enable=1, Macro0, CA PI delay=34
5122 12:26:40.218632
5123 12:26:40.221718 [CBTSetCACLKResult] CA Dly = 34
5124 12:26:40.221831 CS Dly: 7 (0~39)
5125 12:26:40.221902
5126 12:26:40.225427 ----->DramcWriteLeveling(PI) begin...
5127 12:26:40.225582 ==
5128 12:26:40.228574 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 12:26:40.234867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 12:26:40.235023 ==
5131 12:26:40.238566 Write leveling (Byte 0): 31 => 31
5132 12:26:40.238720 Write leveling (Byte 1): 27 => 27
5133 12:26:40.241915 DramcWriteLeveling(PI) end<-----
5134 12:26:40.242063
5135 12:26:40.242134 ==
5136 12:26:40.245110 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 12:26:40.251567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 12:26:40.251728 ==
5139 12:26:40.255000 [Gating] SW mode calibration
5140 12:26:40.261563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5141 12:26:40.265352 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5142 12:26:40.272085 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
5143 12:26:40.275006 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5144 12:26:40.278598 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 12:26:40.285185 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 12:26:40.288296 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 12:26:40.291596 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 12:26:40.298462 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 12:26:40.301588 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5150 12:26:40.304754 0 15 0 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5151 12:26:40.311391 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 12:26:40.314595 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 12:26:40.318486 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 12:26:40.321613 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 12:26:40.328479 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 12:26:40.331585 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 12:26:40.334781 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5158 12:26:40.341122 1 0 0 | B1->B0 | 2e2e 3e3e | 0 0 | (0 0) (0 0)
5159 12:26:40.344925 1 0 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5160 12:26:40.347946 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 12:26:40.354872 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 12:26:40.358031 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 12:26:40.361078 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 12:26:40.367744 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 12:26:40.370871 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5166 12:26:40.374555 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 12:26:40.381345 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5168 12:26:40.384266 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:26:40.387979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:26:40.394388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:26:40.398218 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 12:26:40.401328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 12:26:40.407601 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 12:26:40.411381 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 12:26:40.414525 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:26:40.421441 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 12:26:40.424605 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:26:40.427717 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 12:26:40.434610 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:26:40.437805 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5181 12:26:40.440883 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:26:40.444587 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:26:40.450820 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5184 12:26:40.454553 Total UI for P1: 0, mck2ui 16
5185 12:26:40.457572 best dqsien dly found for B0: ( 1, 3, 2)
5186 12:26:40.461267 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 12:26:40.464310 Total UI for P1: 0, mck2ui 16
5188 12:26:40.467412 best dqsien dly found for B1: ( 1, 3, 4)
5189 12:26:40.471063 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5190 12:26:40.474118 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5191 12:26:40.474254
5192 12:26:40.477903 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5193 12:26:40.481087 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5194 12:26:40.484152 [Gating] SW calibration Done
5195 12:26:40.484280 ==
5196 12:26:40.488037 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 12:26:40.490736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 12:26:40.494332 ==
5199 12:26:40.494472 RX Vref Scan: 0
5200 12:26:40.494543
5201 12:26:40.497717 RX Vref 0 -> 0, step: 1
5202 12:26:40.497831
5203 12:26:40.500743 RX Delay -80 -> 252, step: 8
5204 12:26:40.504478 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5205 12:26:40.507664 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5206 12:26:40.510821 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5207 12:26:40.514582 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5208 12:26:40.517669 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5209 12:26:40.524572 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5210 12:26:40.527803 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5211 12:26:40.531028 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5212 12:26:40.534121 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5213 12:26:40.537788 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5214 12:26:40.541023 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5215 12:26:40.547829 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5216 12:26:40.551066 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5217 12:26:40.554166 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5218 12:26:40.557330 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5219 12:26:40.561177 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5220 12:26:40.561319 ==
5221 12:26:40.564131 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 12:26:40.571194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 12:26:40.571385 ==
5224 12:26:40.571463 DQS Delay:
5225 12:26:40.571528 DQS0 = 0, DQS1 = 0
5226 12:26:40.574224 DQM Delay:
5227 12:26:40.574327 DQM0 = 98, DQM1 = 87
5228 12:26:40.577215 DQ Delay:
5229 12:26:40.580779 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5230 12:26:40.584452 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5231 12:26:40.587548 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5232 12:26:40.591121 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5233 12:26:40.591295
5234 12:26:40.591412
5235 12:26:40.591496 ==
5236 12:26:40.594155 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 12:26:40.597278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 12:26:40.597448 ==
5239 12:26:40.597570
5240 12:26:40.597651
5241 12:26:40.600949 TX Vref Scan disable
5242 12:26:40.601101 == TX Byte 0 ==
5243 12:26:40.607328 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5244 12:26:40.611081 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5245 12:26:40.611249 == TX Byte 1 ==
5246 12:26:40.617938 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5247 12:26:40.621026 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5248 12:26:40.621191 ==
5249 12:26:40.624178 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 12:26:40.627240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 12:26:40.627421 ==
5252 12:26:40.630497
5253 12:26:40.630663
5254 12:26:40.630746 TX Vref Scan disable
5255 12:26:40.634320 == TX Byte 0 ==
5256 12:26:40.637433 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5257 12:26:40.640750 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5258 12:26:40.644499 == TX Byte 1 ==
5259 12:26:40.647555 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5260 12:26:40.650679 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5261 12:26:40.653892
5262 12:26:40.654038 [DATLAT]
5263 12:26:40.654111 Freq=933, CH0 RK0
5264 12:26:40.654175
5265 12:26:40.657620 DATLAT Default: 0xd
5266 12:26:40.657751 0, 0xFFFF, sum = 0
5267 12:26:40.660794 1, 0xFFFF, sum = 0
5268 12:26:40.660907 2, 0xFFFF, sum = 0
5269 12:26:40.663923 3, 0xFFFF, sum = 0
5270 12:26:40.667113 4, 0xFFFF, sum = 0
5271 12:26:40.667281 5, 0xFFFF, sum = 0
5272 12:26:40.670786 6, 0xFFFF, sum = 0
5273 12:26:40.670926 7, 0xFFFF, sum = 0
5274 12:26:40.673895 8, 0xFFFF, sum = 0
5275 12:26:40.674022 9, 0xFFFF, sum = 0
5276 12:26:40.677180 10, 0x0, sum = 1
5277 12:26:40.677308 11, 0x0, sum = 2
5278 12:26:40.680846 12, 0x0, sum = 3
5279 12:26:40.681083 13, 0x0, sum = 4
5280 12:26:40.681239 best_step = 11
5281 12:26:40.681365
5282 12:26:40.683735 ==
5283 12:26:40.687366 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 12:26:40.690580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:26:40.690708 ==
5286 12:26:40.690777 RX Vref Scan: 1
5287 12:26:40.690849
5288 12:26:40.693785 RX Vref 0 -> 0, step: 1
5289 12:26:40.693896
5290 12:26:40.697151 RX Delay -61 -> 252, step: 4
5291 12:26:40.697271
5292 12:26:40.700292 Set Vref, RX VrefLevel [Byte0]: 55
5293 12:26:40.704112 [Byte1]: 53
5294 12:26:40.704261
5295 12:26:40.707255 Final RX Vref Byte 0 = 55 to rank0
5296 12:26:40.710187 Final RX Vref Byte 1 = 53 to rank0
5297 12:26:40.713846 Final RX Vref Byte 0 = 55 to rank1
5298 12:26:40.717343 Final RX Vref Byte 1 = 53 to rank1==
5299 12:26:40.720112 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 12:26:40.723929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 12:26:40.727010 ==
5302 12:26:40.727148 DQS Delay:
5303 12:26:40.727257 DQS0 = 0, DQS1 = 0
5304 12:26:40.730221 DQM Delay:
5305 12:26:40.730333 DQM0 = 96, DQM1 = 89
5306 12:26:40.733340 DQ Delay:
5307 12:26:40.733485 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5308 12:26:40.736499 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5309 12:26:40.739845 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =82
5310 12:26:40.746808 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5311 12:26:40.746984
5312 12:26:40.747085
5313 12:26:40.753248 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5314 12:26:40.756914 CH0 RK0: MR19=504, MR18=11FC
5315 12:26:40.763268 CH0_RK0: MR19=0x504, MR18=0x11FC, DQSOSC=416, MR23=63, INC=62, DEC=41
5316 12:26:40.763438
5317 12:26:40.766532 ----->DramcWriteLeveling(PI) begin...
5318 12:26:40.766681 ==
5319 12:26:40.770333 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 12:26:40.773425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 12:26:40.773585 ==
5322 12:26:40.776474 Write leveling (Byte 0): 33 => 33
5323 12:26:40.780184 Write leveling (Byte 1): 29 => 29
5324 12:26:40.783363 DramcWriteLeveling(PI) end<-----
5325 12:26:40.783487
5326 12:26:40.783558 ==
5327 12:26:40.786374 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 12:26:40.790028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 12:26:40.790166 ==
5330 12:26:40.793419 [Gating] SW mode calibration
5331 12:26:40.799567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5332 12:26:40.806210 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5333 12:26:40.809716 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5334 12:26:40.813311 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5335 12:26:40.819873 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 12:26:40.823387 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 12:26:40.826435 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 12:26:40.833179 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 12:26:40.836400 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5340 12:26:40.840072 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5341 12:26:40.846530 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5342 12:26:40.849678 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 12:26:40.852894 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 12:26:40.859793 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 12:26:40.862919 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 12:26:40.865993 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 12:26:40.873030 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 12:26:40.876164 0 15 28 | B1->B0 | 2d2d 3636 | 1 0 | (0 0) (0 0)
5349 12:26:40.879965 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5350 12:26:40.886322 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 12:26:40.889388 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 12:26:40.892597 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 12:26:40.899335 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 12:26:40.902851 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 12:26:40.906025 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5356 12:26:40.912635 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5357 12:26:40.915986 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5358 12:26:40.919103 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:26:40.925857 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:26:40.929452 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:26:40.932490 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:26:40.939167 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:26:40.942268 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:26:40.946060 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:26:40.952327 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:26:40.956074 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 12:26:40.959187 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:26:40.965478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:26:40.968600 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:26:40.972498 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:26:40.979244 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5372 12:26:40.982280 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5373 12:26:40.986022 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5374 12:26:40.989078 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 12:26:40.992211 Total UI for P1: 0, mck2ui 16
5376 12:26:40.995304 best dqsien dly found for B0: ( 1, 2, 28)
5377 12:26:40.999123 Total UI for P1: 0, mck2ui 16
5378 12:26:41.002116 best dqsien dly found for B1: ( 1, 3, 2)
5379 12:26:41.005645 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5380 12:26:41.009115 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5381 12:26:41.012003
5382 12:26:41.015509 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5383 12:26:41.019030 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5384 12:26:41.022084 [Gating] SW calibration Done
5385 12:26:41.022226 ==
5386 12:26:41.025597 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 12:26:41.028678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 12:26:41.028829 ==
5389 12:26:41.028907 RX Vref Scan: 0
5390 12:26:41.028972
5391 12:26:41.032021 RX Vref 0 -> 0, step: 1
5392 12:26:41.032171
5393 12:26:41.035685 RX Delay -80 -> 252, step: 8
5394 12:26:41.038600 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5395 12:26:41.041627 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5396 12:26:41.048488 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5397 12:26:41.051670 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5398 12:26:41.055370 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5399 12:26:41.058562 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5400 12:26:41.061642 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5401 12:26:41.064888 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5402 12:26:41.071705 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5403 12:26:41.074755 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5404 12:26:41.077986 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5405 12:26:41.081726 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5406 12:26:41.084872 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5407 12:26:41.091640 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5408 12:26:41.094808 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5409 12:26:41.097912 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5410 12:26:41.098088 ==
5411 12:26:41.101879 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 12:26:41.105092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 12:26:41.105237 ==
5414 12:26:41.108091 DQS Delay:
5415 12:26:41.108209 DQS0 = 0, DQS1 = 0
5416 12:26:41.108282 DQM Delay:
5417 12:26:41.111816 DQM0 = 96, DQM1 = 87
5418 12:26:41.111941 DQ Delay:
5419 12:26:41.114674 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5420 12:26:41.118246 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =107
5421 12:26:41.121746 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5422 12:26:41.124646 DQ12 =87, DQ13 =95, DQ14 =99, DQ15 =95
5423 12:26:41.124782
5424 12:26:41.124854
5425 12:26:41.124918 ==
5426 12:26:41.128371 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 12:26:41.134445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 12:26:41.134597 ==
5429 12:26:41.134672
5430 12:26:41.134736
5431 12:26:41.134796 TX Vref Scan disable
5432 12:26:41.138858 == TX Byte 0 ==
5433 12:26:41.142049 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5434 12:26:41.145503 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5435 12:26:41.148376 == TX Byte 1 ==
5436 12:26:41.152013 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5437 12:26:41.158221 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5438 12:26:41.158381 ==
5439 12:26:41.161372 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 12:26:41.165201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 12:26:41.165359 ==
5442 12:26:41.165473
5443 12:26:41.165568
5444 12:26:41.168274 TX Vref Scan disable
5445 12:26:41.168432 == TX Byte 0 ==
5446 12:26:41.175262 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5447 12:26:41.178429 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5448 12:26:41.178559 == TX Byte 1 ==
5449 12:26:41.185348 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5450 12:26:41.188488 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5451 12:26:41.188616
5452 12:26:41.188688 [DATLAT]
5453 12:26:41.191523 Freq=933, CH0 RK1
5454 12:26:41.191633
5455 12:26:41.191702 DATLAT Default: 0xb
5456 12:26:41.194641 0, 0xFFFF, sum = 0
5457 12:26:41.194785 1, 0xFFFF, sum = 0
5458 12:26:41.197904 2, 0xFFFF, sum = 0
5459 12:26:41.198030 3, 0xFFFF, sum = 0
5460 12:26:41.201809 4, 0xFFFF, sum = 0
5461 12:26:41.204934 5, 0xFFFF, sum = 0
5462 12:26:41.205069 6, 0xFFFF, sum = 0
5463 12:26:41.208017 7, 0xFFFF, sum = 0
5464 12:26:41.208138 8, 0xFFFF, sum = 0
5465 12:26:41.211766 9, 0xFFFF, sum = 0
5466 12:26:41.211894 10, 0x0, sum = 1
5467 12:26:41.214948 11, 0x0, sum = 2
5468 12:26:41.215066 12, 0x0, sum = 3
5469 12:26:41.215139 13, 0x0, sum = 4
5470 12:26:41.218328 best_step = 11
5471 12:26:41.218441
5472 12:26:41.218512 ==
5473 12:26:41.221361 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 12:26:41.224725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 12:26:41.224874 ==
5476 12:26:41.228323 RX Vref Scan: 0
5477 12:26:41.228471
5478 12:26:41.228543 RX Vref 0 -> 0, step: 1
5479 12:26:41.231254
5480 12:26:41.231380 RX Delay -61 -> 252, step: 4
5481 12:26:41.239141 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5482 12:26:41.242219 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5483 12:26:41.245922 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5484 12:26:41.249128 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5485 12:26:41.252149 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5486 12:26:41.255670 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5487 12:26:41.262018 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5488 12:26:41.265756 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5489 12:26:41.268923 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5490 12:26:41.272062 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5491 12:26:41.275708 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5492 12:26:41.282207 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5493 12:26:41.285262 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5494 12:26:41.289131 iDelay=199, Bit 13, Center 96 (11 ~ 182) 172
5495 12:26:41.292128 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5496 12:26:41.295244 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5497 12:26:41.295478 ==
5498 12:26:41.299028 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 12:26:41.305447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 12:26:41.305607 ==
5501 12:26:41.305679 DQS Delay:
5502 12:26:41.308570 DQS0 = 0, DQS1 = 0
5503 12:26:41.308679 DQM Delay:
5504 12:26:41.308752 DQM0 = 95, DQM1 = 88
5505 12:26:41.312316 DQ Delay:
5506 12:26:41.315285 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5507 12:26:41.318461 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5508 12:26:41.322209 DQ8 =82, DQ9 =76, DQ10 =88, DQ11 =78
5509 12:26:41.325322 DQ12 =92, DQ13 =96, DQ14 =98, DQ15 =98
5510 12:26:41.325470
5511 12:26:41.325572
5512 12:26:41.332112 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5513 12:26:41.335345 CH0 RK1: MR19=505, MR18=1906
5514 12:26:41.342153 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5515 12:26:41.345193 [RxdqsGatingPostProcess] freq 933
5516 12:26:41.348812 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5517 12:26:41.352003 best DQS0 dly(2T, 0.5T) = (0, 11)
5518 12:26:41.354914 best DQS1 dly(2T, 0.5T) = (0, 11)
5519 12:26:41.358731 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5520 12:26:41.361675 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5521 12:26:41.365482 best DQS0 dly(2T, 0.5T) = (0, 10)
5522 12:26:41.368624 best DQS1 dly(2T, 0.5T) = (0, 11)
5523 12:26:41.371798 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5524 12:26:41.374884 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5525 12:26:41.378808 Pre-setting of DQS Precalculation
5526 12:26:41.381759 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5527 12:26:41.381914 ==
5528 12:26:41.384995 Dram Type= 6, Freq= 0, CH_1, rank 0
5529 12:26:41.391877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 12:26:41.392038 ==
5531 12:26:41.394985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 12:26:41.401829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5533 12:26:41.405021 [CA 0] Center 36 (6~67) winsize 62
5534 12:26:41.408194 [CA 1] Center 36 (6~67) winsize 62
5535 12:26:41.411957 [CA 2] Center 34 (4~64) winsize 61
5536 12:26:41.414965 [CA 3] Center 34 (4~64) winsize 61
5537 12:26:41.418059 [CA 4] Center 34 (4~65) winsize 62
5538 12:26:41.421905 [CA 5] Center 33 (3~64) winsize 62
5539 12:26:41.422048
5540 12:26:41.425203 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5541 12:26:41.425327
5542 12:26:41.428211 [CATrainingPosCal] consider 1 rank data
5543 12:26:41.431400 u2DelayCellTimex100 = 270/100 ps
5544 12:26:41.435226 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5545 12:26:41.438366 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5546 12:26:41.444822 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 12:26:41.448434 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5548 12:26:41.451577 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5549 12:26:41.455302 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5550 12:26:41.455461
5551 12:26:41.458424 CA PerBit enable=1, Macro0, CA PI delay=33
5552 12:26:41.458544
5553 12:26:41.461377 [CBTSetCACLKResult] CA Dly = 33
5554 12:26:41.461498 CS Dly: 4 (0~35)
5555 12:26:41.461569 ==
5556 12:26:41.464604 Dram Type= 6, Freq= 0, CH_1, rank 1
5557 12:26:41.471621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 12:26:41.471826 ==
5559 12:26:41.474733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 12:26:41.481753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5561 12:26:41.484868 [CA 0] Center 36 (6~67) winsize 62
5562 12:26:41.488095 [CA 1] Center 36 (6~67) winsize 62
5563 12:26:41.491837 [CA 2] Center 33 (3~64) winsize 62
5564 12:26:41.494967 [CA 3] Center 33 (3~64) winsize 62
5565 12:26:41.498076 [CA 4] Center 34 (4~64) winsize 61
5566 12:26:41.501942 [CA 5] Center 32 (2~63) winsize 62
5567 12:26:41.502120
5568 12:26:41.505029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5569 12:26:41.505181
5570 12:26:41.507900 [CATrainingPosCal] consider 2 rank data
5571 12:26:41.511168 u2DelayCellTimex100 = 270/100 ps
5572 12:26:41.514980 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5573 12:26:41.521293 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5574 12:26:41.524535 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5575 12:26:41.527757 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5576 12:26:41.530984 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5577 12:26:41.534796 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5578 12:26:41.534972
5579 12:26:41.537883 CA PerBit enable=1, Macro0, CA PI delay=33
5580 12:26:41.538028
5581 12:26:41.541031 [CBTSetCACLKResult] CA Dly = 33
5582 12:26:41.541180 CS Dly: 5 (0~38)
5583 12:26:41.544810
5584 12:26:41.547709 ----->DramcWriteLeveling(PI) begin...
5585 12:26:41.547869 ==
5586 12:26:41.551210 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 12:26:41.554325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 12:26:41.554463 ==
5589 12:26:41.558064 Write leveling (Byte 0): 27 => 27
5590 12:26:41.561251 Write leveling (Byte 1): 30 => 30
5591 12:26:41.564847 DramcWriteLeveling(PI) end<-----
5592 12:26:41.564989
5593 12:26:41.565066 ==
5594 12:26:41.567932 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 12:26:41.570832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 12:26:41.570945 ==
5597 12:26:41.574414 [Gating] SW mode calibration
5598 12:26:41.581158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5599 12:26:41.587557 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5600 12:26:41.591232 0 14 0 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
5601 12:26:41.594498 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5602 12:26:41.600793 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 12:26:41.604597 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5604 12:26:41.607560 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 12:26:41.614315 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 12:26:41.617518 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
5607 12:26:41.621161 0 14 28 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
5608 12:26:41.627380 0 15 0 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
5609 12:26:41.631206 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 12:26:41.634265 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 12:26:41.637583 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 12:26:41.643972 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 12:26:41.647624 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5614 12:26:41.650660 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 12:26:41.657526 0 15 28 | B1->B0 | 3030 2c2c | 0 1 | (1 1) (0 0)
5616 12:26:41.660666 1 0 0 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
5617 12:26:41.664350 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 12:26:41.670427 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 12:26:41.674144 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 12:26:41.677141 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 12:26:41.683740 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 12:26:41.687316 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 12:26:41.691029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 12:26:41.697322 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5625 12:26:41.700398 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:26:41.704281 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:26:41.710683 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:26:41.713761 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:26:41.717408 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:26:41.723742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:26:41.727444 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:26:41.730794 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:26:41.737577 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:26:41.740639 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:26:41.743688 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:26:41.750625 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:26:41.753908 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:26:41.757028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:26:41.763970 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5640 12:26:41.766816 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 12:26:41.770592 Total UI for P1: 0, mck2ui 16
5642 12:26:41.773470 best dqsien dly found for B0: ( 1, 2, 28)
5643 12:26:41.777206 Total UI for P1: 0, mck2ui 16
5644 12:26:41.780277 best dqsien dly found for B1: ( 1, 2, 28)
5645 12:26:41.783942 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5646 12:26:41.787157 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5647 12:26:41.787324
5648 12:26:41.790122 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5649 12:26:41.793774 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5650 12:26:41.796962 [Gating] SW calibration Done
5651 12:26:41.797144 ==
5652 12:26:41.799921 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 12:26:41.803138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 12:26:41.803296 ==
5655 12:26:41.807083 RX Vref Scan: 0
5656 12:26:41.807235
5657 12:26:41.810189 RX Vref 0 -> 0, step: 1
5658 12:26:41.810329
5659 12:26:41.810428 RX Delay -80 -> 252, step: 8
5660 12:26:41.816810 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5661 12:26:41.820591 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5662 12:26:41.823263 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5663 12:26:41.827133 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5664 12:26:41.830277 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5665 12:26:41.833413 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5666 12:26:41.840296 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5667 12:26:41.843459 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5668 12:26:41.846636 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5669 12:26:41.850263 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5670 12:26:41.853531 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5671 12:26:41.856602 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5672 12:26:41.863021 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5673 12:26:41.866286 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5674 12:26:41.869949 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5675 12:26:41.872887 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5676 12:26:41.873043 ==
5677 12:26:41.876330 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 12:26:41.880199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 12:26:41.883171 ==
5680 12:26:41.883321 DQS Delay:
5681 12:26:41.883422 DQS0 = 0, DQS1 = 0
5682 12:26:41.886732 DQM Delay:
5683 12:26:41.886875 DQM0 = 96, DQM1 = 88
5684 12:26:41.889786 DQ Delay:
5685 12:26:41.893417 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5686 12:26:41.896372 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5687 12:26:41.900114 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5688 12:26:41.903255 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5689 12:26:41.903388
5690 12:26:41.903462
5691 12:26:41.903525 ==
5692 12:26:41.906487 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 12:26:41.909731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 12:26:41.909884 ==
5695 12:26:41.909988
5696 12:26:41.910081
5697 12:26:41.912856 TX Vref Scan disable
5698 12:26:41.913006 == TX Byte 0 ==
5699 12:26:41.919875 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5700 12:26:41.922814 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5701 12:26:41.922949 == TX Byte 1 ==
5702 12:26:41.929548 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5703 12:26:41.932791 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5704 12:26:41.932934 ==
5705 12:26:41.936425 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 12:26:41.939603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 12:26:41.939730 ==
5708 12:26:41.939806
5709 12:26:41.939870
5710 12:26:41.942872 TX Vref Scan disable
5711 12:26:41.945862 == TX Byte 0 ==
5712 12:26:41.949806 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5713 12:26:41.952990 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5714 12:26:41.956169 == TX Byte 1 ==
5715 12:26:41.959168 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5716 12:26:41.962452 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5717 12:26:41.962609
5718 12:26:41.966206 [DATLAT]
5719 12:26:41.966353 Freq=933, CH1 RK0
5720 12:26:41.966453
5721 12:26:41.969296 DATLAT Default: 0xd
5722 12:26:41.969424 0, 0xFFFF, sum = 0
5723 12:26:41.972517 1, 0xFFFF, sum = 0
5724 12:26:41.972628 2, 0xFFFF, sum = 0
5725 12:26:41.976200 3, 0xFFFF, sum = 0
5726 12:26:41.976348 4, 0xFFFF, sum = 0
5727 12:26:41.979194 5, 0xFFFF, sum = 0
5728 12:26:41.979343 6, 0xFFFF, sum = 0
5729 12:26:41.982852 7, 0xFFFF, sum = 0
5730 12:26:41.983001 8, 0xFFFF, sum = 0
5731 12:26:41.985953 9, 0xFFFF, sum = 0
5732 12:26:41.986071 10, 0x0, sum = 1
5733 12:26:41.989027 11, 0x0, sum = 2
5734 12:26:41.989150 12, 0x0, sum = 3
5735 12:26:41.992832 13, 0x0, sum = 4
5736 12:26:41.992970 best_step = 11
5737 12:26:41.993043
5738 12:26:41.993112 ==
5739 12:26:41.996045 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 12:26:42.002523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 12:26:42.002679 ==
5742 12:26:42.002759 RX Vref Scan: 1
5743 12:26:42.002825
5744 12:26:42.006235 RX Vref 0 -> 0, step: 1
5745 12:26:42.006362
5746 12:26:42.009235 RX Delay -61 -> 252, step: 4
5747 12:26:42.009357
5748 12:26:42.012427 Set Vref, RX VrefLevel [Byte0]: 57
5749 12:26:42.015599 [Byte1]: 45
5750 12:26:42.015730
5751 12:26:42.019281 Final RX Vref Byte 0 = 57 to rank0
5752 12:26:42.022352 Final RX Vref Byte 1 = 45 to rank0
5753 12:26:42.026149 Final RX Vref Byte 0 = 57 to rank1
5754 12:26:42.028971 Final RX Vref Byte 1 = 45 to rank1==
5755 12:26:42.032155 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 12:26:42.035818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 12:26:42.035956 ==
5758 12:26:42.038978 DQS Delay:
5759 12:26:42.039115 DQS0 = 0, DQS1 = 0
5760 12:26:42.042032 DQM Delay:
5761 12:26:42.042136 DQM0 = 97, DQM1 = 90
5762 12:26:42.042203 DQ Delay:
5763 12:26:42.045835 DQ0 =100, DQ1 =90, DQ2 =88, DQ3 =96
5764 12:26:42.049034 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5765 12:26:42.052074 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =86
5766 12:26:42.055286 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =94
5767 12:26:42.055487
5768 12:26:42.059166
5769 12:26:42.065440 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5770 12:26:42.068647 CH1 RK0: MR19=504, MR18=13F0
5771 12:26:42.075718 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5772 12:26:42.075922
5773 12:26:42.078806 ----->DramcWriteLeveling(PI) begin...
5774 12:26:42.078957 ==
5775 12:26:42.081909 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 12:26:42.085688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 12:26:42.085869 ==
5778 12:26:42.088720 Write leveling (Byte 0): 28 => 28
5779 12:26:42.092232 Write leveling (Byte 1): 28 => 28
5780 12:26:42.095243 DramcWriteLeveling(PI) end<-----
5781 12:26:42.095416
5782 12:26:42.095527 ==
5783 12:26:42.098931 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 12:26:42.102031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 12:26:42.102191 ==
5786 12:26:42.105127 [Gating] SW mode calibration
5787 12:26:42.112275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5788 12:26:42.118514 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5789 12:26:42.121601 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 12:26:42.125442 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5791 12:26:42.131792 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5792 12:26:42.135265 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 12:26:42.138822 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5794 12:26:42.145137 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5795 12:26:42.148235 0 14 24 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
5796 12:26:42.152071 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5797 12:26:42.158321 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5798 12:26:42.161567 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 12:26:42.164715 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 12:26:42.171711 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5801 12:26:42.175467 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5802 12:26:42.178419 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5803 12:26:42.184786 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
5804 12:26:42.188610 0 15 28 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
5805 12:26:42.191532 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 12:26:42.198349 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 12:26:42.201934 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 12:26:42.204865 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 12:26:42.211626 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 12:26:42.214630 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5811 12:26:42.218245 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5812 12:26:42.225138 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5813 12:26:42.228205 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:26:42.231288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:26:42.235119 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:26:42.241312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:26:42.244623 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:26:42.248391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:26:42.254736 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:26:42.258049 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:26:42.261132 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:26:42.268056 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:26:42.271240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:26:42.274338 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:26:42.281254 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:26:42.284545 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:26:42.288347 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5828 12:26:42.291515 Total UI for P1: 0, mck2ui 16
5829 12:26:42.294356 best dqsien dly found for B0: ( 1, 2, 22)
5830 12:26:42.301036 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 12:26:42.301189 Total UI for P1: 0, mck2ui 16
5832 12:26:42.308178 best dqsien dly found for B1: ( 1, 2, 26)
5833 12:26:42.311032 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5834 12:26:42.314610 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5835 12:26:42.314747
5836 12:26:42.317841 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5837 12:26:42.321511 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5838 12:26:42.324617 [Gating] SW calibration Done
5839 12:26:42.324739 ==
5840 12:26:42.327589 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 12:26:42.331224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 12:26:42.331398 ==
5843 12:26:42.334218 RX Vref Scan: 0
5844 12:26:42.334356
5845 12:26:42.334447 RX Vref 0 -> 0, step: 1
5846 12:26:42.334529
5847 12:26:42.338002 RX Delay -80 -> 252, step: 8
5848 12:26:42.341130 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5849 12:26:42.348072 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5850 12:26:42.351030 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5851 12:26:42.354770 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5852 12:26:42.357877 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5853 12:26:42.361027 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5854 12:26:42.364704 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5855 12:26:42.370963 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5856 12:26:42.374043 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5857 12:26:42.377113 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5858 12:26:42.380867 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5859 12:26:42.384149 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5860 12:26:42.387236 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5861 12:26:42.394128 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5862 12:26:42.397217 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5863 12:26:42.401007 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5864 12:26:42.401139 ==
5865 12:26:42.404140 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 12:26:42.407219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 12:26:42.407329 ==
5868 12:26:42.410274 DQS Delay:
5869 12:26:42.410369 DQS0 = 0, DQS1 = 0
5870 12:26:42.413927 DQM Delay:
5871 12:26:42.414036 DQM0 = 94, DQM1 = 90
5872 12:26:42.414127 DQ Delay:
5873 12:26:42.417404 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5874 12:26:42.420354 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5875 12:26:42.423524 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5876 12:26:42.427168 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5877 12:26:42.427279
5878 12:26:42.427387
5879 12:26:42.430108 ==
5880 12:26:42.433802 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 12:26:42.436808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 12:26:42.436950 ==
5883 12:26:42.437055
5884 12:26:42.437155
5885 12:26:42.440422 TX Vref Scan disable
5886 12:26:42.440525 == TX Byte 0 ==
5887 12:26:42.443322 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5888 12:26:42.450379 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5889 12:26:42.450505 == TX Byte 1 ==
5890 12:26:42.453558 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5891 12:26:42.459874 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5892 12:26:42.460035 ==
5893 12:26:42.463653 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 12:26:42.466956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 12:26:42.467083 ==
5896 12:26:42.467183
5897 12:26:42.467275
5898 12:26:42.470035 TX Vref Scan disable
5899 12:26:42.473236 == TX Byte 0 ==
5900 12:26:42.477016 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5901 12:26:42.480093 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5902 12:26:42.483947 == TX Byte 1 ==
5903 12:26:42.487133 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 12:26:42.490303 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 12:26:42.490423
5906 12:26:42.490518 [DATLAT]
5907 12:26:42.493466 Freq=933, CH1 RK1
5908 12:26:42.493574
5909 12:26:42.497263 DATLAT Default: 0xb
5910 12:26:42.497357 0, 0xFFFF, sum = 0
5911 12:26:42.500363 1, 0xFFFF, sum = 0
5912 12:26:42.500455 2, 0xFFFF, sum = 0
5913 12:26:42.503521 3, 0xFFFF, sum = 0
5914 12:26:42.503619 4, 0xFFFF, sum = 0
5915 12:26:42.506698 5, 0xFFFF, sum = 0
5916 12:26:42.506820 6, 0xFFFF, sum = 0
5917 12:26:42.510530 7, 0xFFFF, sum = 0
5918 12:26:42.510630 8, 0xFFFF, sum = 0
5919 12:26:42.513469 9, 0xFFFF, sum = 0
5920 12:26:42.513627 10, 0x0, sum = 1
5921 12:26:42.516780 11, 0x0, sum = 2
5922 12:26:42.516881 12, 0x0, sum = 3
5923 12:26:42.520508 13, 0x0, sum = 4
5924 12:26:42.520608 best_step = 11
5925 12:26:42.520677
5926 12:26:42.520739 ==
5927 12:26:42.523370 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 12:26:42.526850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 12:26:42.526976 ==
5930 12:26:42.530036 RX Vref Scan: 0
5931 12:26:42.530132
5932 12:26:42.533697 RX Vref 0 -> 0, step: 1
5933 12:26:42.533804
5934 12:26:42.533875 RX Delay -61 -> 252, step: 4
5935 12:26:42.541442 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5936 12:26:42.544455 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5937 12:26:42.547973 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5938 12:26:42.551052 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5939 12:26:42.554510 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5940 12:26:42.560934 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5941 12:26:42.564710 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5942 12:26:42.567900 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5943 12:26:42.571171 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5944 12:26:42.574300 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5945 12:26:42.577531 iDelay=199, Bit 10, Center 94 (7 ~ 182) 176
5946 12:26:42.584463 iDelay=199, Bit 11, Center 84 (-1 ~ 170) 172
5947 12:26:42.587817 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5948 12:26:42.590856 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5949 12:26:42.593956 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5950 12:26:42.597131 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5951 12:26:42.600860 ==
5952 12:26:42.604007 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 12:26:42.607836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 12:26:42.607956 ==
5955 12:26:42.608027 DQS Delay:
5956 12:26:42.610829 DQS0 = 0, DQS1 = 0
5957 12:26:42.610926 DQM Delay:
5958 12:26:42.614045 DQM0 = 95, DQM1 = 90
5959 12:26:42.614146 DQ Delay:
5960 12:26:42.617222 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =94
5961 12:26:42.620935 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5962 12:26:42.624061 DQ8 =78, DQ9 =78, DQ10 =94, DQ11 =84
5963 12:26:42.627701 DQ12 =96, DQ13 =100, DQ14 =98, DQ15 =98
5964 12:26:42.627812
5965 12:26:42.627884
5966 12:26:42.634187 [DQSOSCAuto] RK1, (LSB)MR18= 0xd15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
5967 12:26:42.637137 CH1 RK1: MR19=505, MR18=D15
5968 12:26:42.643796 CH1_RK1: MR19=0x505, MR18=0xD15, DQSOSC=415, MR23=63, INC=62, DEC=41
5969 12:26:42.647301 [RxdqsGatingPostProcess] freq 933
5970 12:26:42.650788 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5971 12:26:42.654199 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 12:26:42.657192 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 12:26:42.660765 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 12:26:42.664065 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 12:26:42.667019 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 12:26:42.670662 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 12:26:42.673822 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 12:26:42.676994 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 12:26:42.680916 Pre-setting of DQS Precalculation
5980 12:26:42.683987 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5981 12:26:42.694017 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5982 12:26:42.700981 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5983 12:26:42.701122
5984 12:26:42.701235
5985 12:26:42.704224 [Calibration Summary] 1866 Mbps
5986 12:26:42.704330 CH 0, Rank 0
5987 12:26:42.707442 SW Impedance : PASS
5988 12:26:42.707530 DUTY Scan : NO K
5989 12:26:42.710469 ZQ Calibration : PASS
5990 12:26:42.713586 Jitter Meter : NO K
5991 12:26:42.713682 CBT Training : PASS
5992 12:26:42.717392 Write leveling : PASS
5993 12:26:42.720553 RX DQS gating : PASS
5994 12:26:42.720652 RX DQ/DQS(RDDQC) : PASS
5995 12:26:42.723797 TX DQ/DQS : PASS
5996 12:26:42.726910 RX DATLAT : PASS
5997 12:26:42.727032 RX DQ/DQS(Engine): PASS
5998 12:26:42.730722 TX OE : NO K
5999 12:26:42.730830 All Pass.
6000 12:26:42.730928
6001 12:26:42.733909 CH 0, Rank 1
6002 12:26:42.734011 SW Impedance : PASS
6003 12:26:42.736978 DUTY Scan : NO K
6004 12:26:42.740597 ZQ Calibration : PASS
6005 12:26:42.740725 Jitter Meter : NO K
6006 12:26:42.744207 CBT Training : PASS
6007 12:26:42.744308 Write leveling : PASS
6008 12:26:42.747184 RX DQS gating : PASS
6009 12:26:42.750363 RX DQ/DQS(RDDQC) : PASS
6010 12:26:42.750471 TX DQ/DQS : PASS
6011 12:26:42.753803 RX DATLAT : PASS
6012 12:26:42.757347 RX DQ/DQS(Engine): PASS
6013 12:26:42.757471 TX OE : NO K
6014 12:26:42.760243 All Pass.
6015 12:26:42.760360
6016 12:26:42.760442 CH 1, Rank 0
6017 12:26:42.763782 SW Impedance : PASS
6018 12:26:42.763917 DUTY Scan : NO K
6019 12:26:42.767218 ZQ Calibration : PASS
6020 12:26:42.770152 Jitter Meter : NO K
6021 12:26:42.770337 CBT Training : PASS
6022 12:26:42.773471 Write leveling : PASS
6023 12:26:42.777109 RX DQS gating : PASS
6024 12:26:42.777213 RX DQ/DQS(RDDQC) : PASS
6025 12:26:42.780119 TX DQ/DQS : PASS
6026 12:26:42.783864 RX DATLAT : PASS
6027 12:26:42.783961 RX DQ/DQS(Engine): PASS
6028 12:26:42.787009 TX OE : NO K
6029 12:26:42.787107 All Pass.
6030 12:26:42.787178
6031 12:26:42.790182 CH 1, Rank 1
6032 12:26:42.790271 SW Impedance : PASS
6033 12:26:42.794014 DUTY Scan : NO K
6034 12:26:42.794112 ZQ Calibration : PASS
6035 12:26:42.797064 Jitter Meter : NO K
6036 12:26:42.800281 CBT Training : PASS
6037 12:26:42.800381 Write leveling : PASS
6038 12:26:42.803502 RX DQS gating : PASS
6039 12:26:42.806889 RX DQ/DQS(RDDQC) : PASS
6040 12:26:42.807022 TX DQ/DQS : PASS
6041 12:26:42.810663 RX DATLAT : PASS
6042 12:26:42.813835 RX DQ/DQS(Engine): PASS
6043 12:26:42.813933 TX OE : NO K
6044 12:26:42.817124 All Pass.
6045 12:26:42.817218
6046 12:26:42.817287 DramC Write-DBI off
6047 12:26:42.820758 PER_BANK_REFRESH: Hybrid Mode
6048 12:26:42.820859 TX_TRACKING: ON
6049 12:26:42.830287 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6050 12:26:42.833385 [FAST_K] Save calibration result to emmc
6051 12:26:42.837201 dramc_set_vcore_voltage set vcore to 650000
6052 12:26:42.840444 Read voltage for 400, 6
6053 12:26:42.840574 Vio18 = 0
6054 12:26:42.843307 Vcore = 650000
6055 12:26:42.843431 Vdram = 0
6056 12:26:42.843531 Vddq = 0
6057 12:26:42.846881 Vmddr = 0
6058 12:26:42.850507 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6059 12:26:42.857035 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6060 12:26:42.857183 MEM_TYPE=3, freq_sel=20
6061 12:26:42.860044 sv_algorithm_assistance_LP4_800
6062 12:26:42.863575 ============ PULL DRAM RESETB DOWN ============
6063 12:26:42.870070 ========== PULL DRAM RESETB DOWN end =========
6064 12:26:42.873081 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6065 12:26:42.876509 ===================================
6066 12:26:42.879963 LPDDR4 DRAM CONFIGURATION
6067 12:26:42.883768 ===================================
6068 12:26:42.883913 EX_ROW_EN[0] = 0x0
6069 12:26:42.886649 EX_ROW_EN[1] = 0x0
6070 12:26:42.889825 LP4Y_EN = 0x0
6071 12:26:42.889926 WORK_FSP = 0x0
6072 12:26:42.893072 WL = 0x2
6073 12:26:42.893167 RL = 0x2
6074 12:26:42.896696 BL = 0x2
6075 12:26:42.896792 RPST = 0x0
6076 12:26:42.899688 RD_PRE = 0x0
6077 12:26:42.899780 WR_PRE = 0x1
6078 12:26:42.903572 WR_PST = 0x0
6079 12:26:42.903671 DBI_WR = 0x0
6080 12:26:42.906645 DBI_RD = 0x0
6081 12:26:42.906740 OTF = 0x1
6082 12:26:42.909787 ===================================
6083 12:26:42.912835 ===================================
6084 12:26:42.916567 ANA top config
6085 12:26:42.919755 ===================================
6086 12:26:42.919867 DLL_ASYNC_EN = 0
6087 12:26:42.922895 ALL_SLAVE_EN = 1
6088 12:26:42.926663 NEW_RANK_MODE = 1
6089 12:26:42.929810 DLL_IDLE_MODE = 1
6090 12:26:42.932964 LP45_APHY_COMB_EN = 1
6091 12:26:42.933071 TX_ODT_DIS = 1
6092 12:26:42.936167 NEW_8X_MODE = 1
6093 12:26:42.939910 ===================================
6094 12:26:42.943120 ===================================
6095 12:26:42.946228 data_rate = 800
6096 12:26:42.949937 CKR = 1
6097 12:26:42.953079 DQ_P2S_RATIO = 4
6098 12:26:42.956284 ===================================
6099 12:26:42.956397 CA_P2S_RATIO = 4
6100 12:26:42.959896 DQ_CA_OPEN = 0
6101 12:26:42.962804 DQ_SEMI_OPEN = 1
6102 12:26:42.966471 CA_SEMI_OPEN = 1
6103 12:26:42.969691 CA_FULL_RATE = 0
6104 12:26:42.973256 DQ_CKDIV4_EN = 0
6105 12:26:42.973363 CA_CKDIV4_EN = 1
6106 12:26:42.976365 CA_PREDIV_EN = 0
6107 12:26:42.979936 PH8_DLY = 0
6108 12:26:42.982703 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6109 12:26:42.986216 DQ_AAMCK_DIV = 0
6110 12:26:42.989362 CA_AAMCK_DIV = 0
6111 12:26:42.989475 CA_ADMCK_DIV = 4
6112 12:26:42.992979 DQ_TRACK_CA_EN = 0
6113 12:26:42.996049 CA_PICK = 800
6114 12:26:42.999155 CA_MCKIO = 400
6115 12:26:43.002973 MCKIO_SEMI = 400
6116 12:26:43.006091 PLL_FREQ = 3016
6117 12:26:43.009693 DQ_UI_PI_RATIO = 32
6118 12:26:43.012440 CA_UI_PI_RATIO = 32
6119 12:26:43.016257 ===================================
6120 12:26:43.019280 ===================================
6121 12:26:43.019407 memory_type:LPDDR4
6122 12:26:43.022440 GP_NUM : 10
6123 12:26:43.025538 SRAM_EN : 1
6124 12:26:43.025629 MD32_EN : 0
6125 12:26:43.029338 ===================================
6126 12:26:43.032489 [ANA_INIT] >>>>>>>>>>>>>>
6127 12:26:43.035605 <<<<<< [CONFIGURE PHASE]: ANA_TX
6128 12:26:43.038758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6129 12:26:43.042525 ===================================
6130 12:26:43.045761 data_rate = 800,PCW = 0X7400
6131 12:26:43.048891 ===================================
6132 12:26:43.051986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6133 12:26:43.055713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 12:26:43.069013 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 12:26:43.072501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6136 12:26:43.075460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6137 12:26:43.078493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6138 12:26:43.082251 [ANA_INIT] flow start
6139 12:26:43.082389 [ANA_INIT] PLL >>>>>>>>
6140 12:26:43.085160 [ANA_INIT] PLL <<<<<<<<
6141 12:26:43.088850 [ANA_INIT] MIDPI >>>>>>>>
6142 12:26:43.091632 [ANA_INIT] MIDPI <<<<<<<<
6143 12:26:43.091760 [ANA_INIT] DLL >>>>>>>>
6144 12:26:43.095185 [ANA_INIT] flow end
6145 12:26:43.098806 ============ LP4 DIFF to SE enter ============
6146 12:26:43.101945 ============ LP4 DIFF to SE exit ============
6147 12:26:43.105471 [ANA_INIT] <<<<<<<<<<<<<
6148 12:26:43.108778 [Flow] Enable top DCM control >>>>>
6149 12:26:43.111879 [Flow] Enable top DCM control <<<<<
6150 12:26:43.115103 Enable DLL master slave shuffle
6151 12:26:43.122036 ==============================================================
6152 12:26:43.122164 Gating Mode config
6153 12:26:43.128373 ==============================================================
6154 12:26:43.128503 Config description:
6155 12:26:43.138201 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6156 12:26:43.145087 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6157 12:26:43.151971 SELPH_MODE 0: By rank 1: By Phase
6158 12:26:43.155184 ==============================================================
6159 12:26:43.158202 GAT_TRACK_EN = 0
6160 12:26:43.161965 RX_GATING_MODE = 2
6161 12:26:43.165157 RX_GATING_TRACK_MODE = 2
6162 12:26:43.168274 SELPH_MODE = 1
6163 12:26:43.171510 PICG_EARLY_EN = 1
6164 12:26:43.174709 VALID_LAT_VALUE = 1
6165 12:26:43.178134 ==============================================================
6166 12:26:43.181719 Enter into Gating configuration >>>>
6167 12:26:43.184705 Exit from Gating configuration <<<<
6168 12:26:43.188358 Enter into DVFS_PRE_config >>>>>
6169 12:26:43.201486 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6170 12:26:43.205243 Exit from DVFS_PRE_config <<<<<
6171 12:26:43.208162 Enter into PICG configuration >>>>
6172 12:26:43.208278 Exit from PICG configuration <<<<
6173 12:26:43.211795 [RX_INPUT] configuration >>>>>
6174 12:26:43.214983 [RX_INPUT] configuration <<<<<
6175 12:26:43.221382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6176 12:26:43.225043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6177 12:26:43.231137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 12:26:43.238091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 12:26:43.244501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 12:26:43.251412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 12:26:43.254557 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6182 12:26:43.258411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6183 12:26:43.261504 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6184 12:26:43.267803 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6185 12:26:43.271490 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6186 12:26:43.274677 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 12:26:43.278372 ===================================
6188 12:26:43.281518 LPDDR4 DRAM CONFIGURATION
6189 12:26:43.284951 ===================================
6190 12:26:43.287819 EX_ROW_EN[0] = 0x0
6191 12:26:43.287921 EX_ROW_EN[1] = 0x0
6192 12:26:43.291461 LP4Y_EN = 0x0
6193 12:26:43.291556 WORK_FSP = 0x0
6194 12:26:43.294539 WL = 0x2
6195 12:26:43.294668 RL = 0x2
6196 12:26:43.298165 BL = 0x2
6197 12:26:43.298297 RPST = 0x0
6198 12:26:43.301184 RD_PRE = 0x0
6199 12:26:43.301337 WR_PRE = 0x1
6200 12:26:43.304458 WR_PST = 0x0
6201 12:26:43.304621 DBI_WR = 0x0
6202 12:26:43.308047 DBI_RD = 0x0
6203 12:26:43.308212 OTF = 0x1
6204 12:26:43.311539 ===================================
6205 12:26:43.318174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6206 12:26:43.321213 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6207 12:26:43.324473 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 12:26:43.327729 ===================================
6209 12:26:43.330871 LPDDR4 DRAM CONFIGURATION
6210 12:26:43.334636 ===================================
6211 12:26:43.337973 EX_ROW_EN[0] = 0x10
6212 12:26:43.338101 EX_ROW_EN[1] = 0x0
6213 12:26:43.340901 LP4Y_EN = 0x0
6214 12:26:43.340997 WORK_FSP = 0x0
6215 12:26:43.344679 WL = 0x2
6216 12:26:43.344776 RL = 0x2
6217 12:26:43.347776 BL = 0x2
6218 12:26:43.347872 RPST = 0x0
6219 12:26:43.351048 RD_PRE = 0x0
6220 12:26:43.351142 WR_PRE = 0x1
6221 12:26:43.354125 WR_PST = 0x0
6222 12:26:43.354217 DBI_WR = 0x0
6223 12:26:43.357945 DBI_RD = 0x0
6224 12:26:43.358057 OTF = 0x1
6225 12:26:43.361026 ===================================
6226 12:26:43.367277 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6227 12:26:43.372202 nWR fixed to 30
6228 12:26:43.375314 [ModeRegInit_LP4] CH0 RK0
6229 12:26:43.375461 [ModeRegInit_LP4] CH0 RK1
6230 12:26:43.378577 [ModeRegInit_LP4] CH1 RK0
6231 12:26:43.382319 [ModeRegInit_LP4] CH1 RK1
6232 12:26:43.382436 match AC timing 19
6233 12:26:43.388534 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6234 12:26:43.392149 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6235 12:26:43.395021 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6236 12:26:43.401938 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6237 12:26:43.405103 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6238 12:26:43.405243 ==
6239 12:26:43.408785 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 12:26:43.411714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 12:26:43.411844 ==
6242 12:26:43.418370 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 12:26:43.425172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6244 12:26:43.428193 [CA 0] Center 36 (8~64) winsize 57
6245 12:26:43.431495 [CA 1] Center 36 (8~64) winsize 57
6246 12:26:43.434748 [CA 2] Center 36 (8~64) winsize 57
6247 12:26:43.438097 [CA 3] Center 36 (8~64) winsize 57
6248 12:26:43.441892 [CA 4] Center 36 (8~64) winsize 57
6249 12:26:43.442009 [CA 5] Center 36 (8~64) winsize 57
6250 12:26:43.442087
6251 12:26:43.448320 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6252 12:26:43.448442
6253 12:26:43.451449 [CATrainingPosCal] consider 1 rank data
6254 12:26:43.454716 u2DelayCellTimex100 = 270/100 ps
6255 12:26:43.457966 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:26:43.461109 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:26:43.464507 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:26:43.467645 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:26:43.471248 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:26:43.474291 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:26:43.474446
6262 12:26:43.478144 CA PerBit enable=1, Macro0, CA PI delay=36
6263 12:26:43.478290
6264 12:26:43.481370 [CBTSetCACLKResult] CA Dly = 36
6265 12:26:43.484525 CS Dly: 1 (0~32)
6266 12:26:43.484669 ==
6267 12:26:43.487782 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 12:26:43.491110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 12:26:43.491248 ==
6270 12:26:43.497934 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 12:26:43.504685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6272 12:26:43.507692 [CA 0] Center 36 (8~64) winsize 57
6273 12:26:43.510995 [CA 1] Center 36 (8~64) winsize 57
6274 12:26:43.511144 [CA 2] Center 36 (8~64) winsize 57
6275 12:26:43.514084 [CA 3] Center 36 (8~64) winsize 57
6276 12:26:43.517791 [CA 4] Center 36 (8~64) winsize 57
6277 12:26:43.520938 [CA 5] Center 36 (8~64) winsize 57
6278 12:26:43.521082
6279 12:26:43.523859 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6280 12:26:43.527378
6281 12:26:43.530577 [CATrainingPosCal] consider 2 rank data
6282 12:26:43.530724 u2DelayCellTimex100 = 270/100 ps
6283 12:26:43.537382 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:26:43.540430 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:26:43.543675 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 12:26:43.546854 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 12:26:43.550573 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:26:43.553913 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 12:26:43.554072
6290 12:26:43.556951 CA PerBit enable=1, Macro0, CA PI delay=36
6291 12:26:43.557096
6292 12:26:43.560199 [CBTSetCACLKResult] CA Dly = 36
6293 12:26:43.563425 CS Dly: 1 (0~32)
6294 12:26:43.563569
6295 12:26:43.567284 ----->DramcWriteLeveling(PI) begin...
6296 12:26:43.567439 ==
6297 12:26:43.570538 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 12:26:43.573754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 12:26:43.573900 ==
6300 12:26:43.576876 Write leveling (Byte 0): 40 => 8
6301 12:26:43.580035 Write leveling (Byte 1): 32 => 0
6302 12:26:43.583940 DramcWriteLeveling(PI) end<-----
6303 12:26:43.584095
6304 12:26:43.584201 ==
6305 12:26:43.586966 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 12:26:43.590234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 12:26:43.590380 ==
6308 12:26:43.593410 [Gating] SW mode calibration
6309 12:26:43.600414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6310 12:26:43.607125 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6311 12:26:43.610620 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 12:26:43.613726 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 12:26:43.620091 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 12:26:43.623129 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 12:26:43.626935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 12:26:43.633679 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 12:26:43.636786 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 12:26:43.640104 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 12:26:43.646490 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 12:26:43.649654 Total UI for P1: 0, mck2ui 16
6321 12:26:43.653104 best dqsien dly found for B0: ( 0, 14, 24)
6322 12:26:43.653260 Total UI for P1: 0, mck2ui 16
6323 12:26:43.659381 best dqsien dly found for B1: ( 0, 14, 24)
6324 12:26:43.662662 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6325 12:26:43.666434 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6326 12:26:43.666585
6327 12:26:43.669652 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 12:26:43.672841 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 12:26:43.676155 [Gating] SW calibration Done
6330 12:26:43.676306 ==
6331 12:26:43.679999 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 12:26:43.682991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 12:26:43.683138 ==
6334 12:26:43.687144 RX Vref Scan: 0
6335 12:26:43.687297
6336 12:26:43.687411 RX Vref 0 -> 0, step: 1
6337 12:26:43.689918
6338 12:26:43.690038 RX Delay -410 -> 252, step: 16
6339 12:26:43.696300 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6340 12:26:43.699308 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6341 12:26:43.703220 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6342 12:26:43.706355 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6343 12:26:43.712630 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6344 12:26:43.716121 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6345 12:26:43.719619 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6346 12:26:43.722840 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6347 12:26:43.729542 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6348 12:26:43.732595 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6349 12:26:43.736106 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6350 12:26:43.739736 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6351 12:26:43.746350 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6352 12:26:43.749392 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6353 12:26:43.753126 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6354 12:26:43.755880 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6355 12:26:43.759137 ==
6356 12:26:43.762910 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 12:26:43.766153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 12:26:43.766305 ==
6359 12:26:43.766417 DQS Delay:
6360 12:26:43.769263 DQS0 = 35, DQS1 = 51
6361 12:26:43.769384 DQM Delay:
6362 12:26:43.772499 DQM0 = 6, DQM1 = 10
6363 12:26:43.772604 DQ Delay:
6364 12:26:43.775900 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6365 12:26:43.779112 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6366 12:26:43.782329 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6367 12:26:43.786277 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6368 12:26:43.786438
6369 12:26:43.786515
6370 12:26:43.786598 ==
6371 12:26:43.789171 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 12:26:43.792303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 12:26:43.792423 ==
6374 12:26:43.792499
6375 12:26:43.792564
6376 12:26:43.795587 TX Vref Scan disable
6377 12:26:43.795690 == TX Byte 0 ==
6378 12:26:43.802470 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 12:26:43.805645 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 12:26:43.805767 == TX Byte 1 ==
6381 12:26:43.812273 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 12:26:43.815460 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 12:26:43.815575 ==
6384 12:26:43.819215 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:26:43.822275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:26:43.822426 ==
6387 12:26:43.822528
6388 12:26:43.822621
6389 12:26:43.825966 TX Vref Scan disable
6390 12:26:43.826080 == TX Byte 0 ==
6391 12:26:43.832267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 12:26:43.836075 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 12:26:43.836214 == TX Byte 1 ==
6394 12:26:43.842904 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6395 12:26:43.845763 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6396 12:26:43.845887
6397 12:26:43.845961 [DATLAT]
6398 12:26:43.848879 Freq=400, CH0 RK0
6399 12:26:43.848983
6400 12:26:43.849055 DATLAT Default: 0xf
6401 12:26:43.852530 0, 0xFFFF, sum = 0
6402 12:26:43.852643 1, 0xFFFF, sum = 0
6403 12:26:43.855682 2, 0xFFFF, sum = 0
6404 12:26:43.855845 3, 0xFFFF, sum = 0
6405 12:26:43.859001 4, 0xFFFF, sum = 0
6406 12:26:43.859111 5, 0xFFFF, sum = 0
6407 12:26:43.862347 6, 0xFFFF, sum = 0
6408 12:26:43.862455 7, 0xFFFF, sum = 0
6409 12:26:43.866290 8, 0xFFFF, sum = 0
6410 12:26:43.866406 9, 0xFFFF, sum = 0
6411 12:26:43.869315 10, 0xFFFF, sum = 0
6412 12:26:43.872451 11, 0xFFFF, sum = 0
6413 12:26:43.872594 12, 0xFFFF, sum = 0
6414 12:26:43.875646 13, 0x0, sum = 1
6415 12:26:43.875746 14, 0x0, sum = 2
6416 12:26:43.878809 15, 0x0, sum = 3
6417 12:26:43.878931 16, 0x0, sum = 4
6418 12:26:43.879029 best_step = 14
6419 12:26:43.879120
6420 12:26:43.882651 ==
6421 12:26:43.885893 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 12:26:43.889067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 12:26:43.889210 ==
6424 12:26:43.889317 RX Vref Scan: 1
6425 12:26:43.889411
6426 12:26:43.892162 RX Vref 0 -> 0, step: 1
6427 12:26:43.892263
6428 12:26:43.895285 RX Delay -343 -> 252, step: 8
6429 12:26:43.895397
6430 12:26:43.899118 Set Vref, RX VrefLevel [Byte0]: 55
6431 12:26:43.902236 [Byte1]: 53
6432 12:26:43.905930
6433 12:26:43.906075 Final RX Vref Byte 0 = 55 to rank0
6434 12:26:43.909228 Final RX Vref Byte 1 = 53 to rank0
6435 12:26:43.912296 Final RX Vref Byte 0 = 55 to rank1
6436 12:26:43.915587 Final RX Vref Byte 1 = 53 to rank1==
6437 12:26:43.918884 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 12:26:43.925671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 12:26:43.925829 ==
6440 12:26:43.925966 DQS Delay:
6441 12:26:43.928824 DQS0 = 44, DQS1 = 60
6442 12:26:43.928933 DQM Delay:
6443 12:26:43.929013 DQM0 = 11, DQM1 = 15
6444 12:26:43.932336 DQ Delay:
6445 12:26:43.935276 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6446 12:26:43.938533 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6447 12:26:43.942207 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6448 12:26:43.945241 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6449 12:26:43.945364
6450 12:26:43.945436
6451 12:26:43.951884 [DQSOSCAuto] RK0, (LSB)MR18= 0x8856, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6452 12:26:43.955541 CH0 RK0: MR19=C0C, MR18=8856
6453 12:26:43.962133 CH0_RK0: MR19=0xC0C, MR18=0x8856, DQSOSC=392, MR23=63, INC=384, DEC=256
6454 12:26:43.962308 ==
6455 12:26:43.965268 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 12:26:43.968465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 12:26:43.968603 ==
6458 12:26:43.971715 [Gating] SW mode calibration
6459 12:26:43.978814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6460 12:26:43.985407 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6461 12:26:43.988465 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 12:26:43.991642 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 12:26:43.998419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 12:26:44.001427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 12:26:44.005218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 12:26:44.011524 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 12:26:44.014710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 12:26:44.018544 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 12:26:44.024969 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 12:26:44.025142 Total UI for P1: 0, mck2ui 16
6471 12:26:44.031528 best dqsien dly found for B0: ( 0, 14, 24)
6472 12:26:44.031694 Total UI for P1: 0, mck2ui 16
6473 12:26:44.037981 best dqsien dly found for B1: ( 0, 14, 24)
6474 12:26:44.041479 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6475 12:26:44.044881 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6476 12:26:44.045028
6477 12:26:44.048101 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 12:26:44.050912 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 12:26:44.054640 [Gating] SW calibration Done
6480 12:26:44.054790 ==
6481 12:26:44.057860 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 12:26:44.061470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 12:26:44.061591 ==
6484 12:26:44.064647 RX Vref Scan: 0
6485 12:26:44.064747
6486 12:26:44.064815 RX Vref 0 -> 0, step: 1
6487 12:26:44.064886
6488 12:26:44.067802 RX Delay -410 -> 252, step: 16
6489 12:26:44.074293 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6490 12:26:44.078177 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6491 12:26:44.081595 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6492 12:26:44.084551 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6493 12:26:44.091387 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6494 12:26:44.094431 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6495 12:26:44.097564 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6496 12:26:44.101366 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6497 12:26:44.107494 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6498 12:26:44.111377 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6499 12:26:44.114180 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6500 12:26:44.117836 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6501 12:26:44.124100 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6502 12:26:44.127909 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6503 12:26:44.131070 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6504 12:26:44.134112 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6505 12:26:44.137242 ==
6506 12:26:44.140978 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 12:26:44.144055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 12:26:44.144188 ==
6509 12:26:44.144259 DQS Delay:
6510 12:26:44.147689 DQS0 = 43, DQS1 = 51
6511 12:26:44.147808 DQM Delay:
6512 12:26:44.150490 DQM0 = 11, DQM1 = 10
6513 12:26:44.150629 DQ Delay:
6514 12:26:44.154059 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6515 12:26:44.157189 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6516 12:26:44.161009 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6517 12:26:44.163938 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6518 12:26:44.164064
6519 12:26:44.164177
6520 12:26:44.164246 ==
6521 12:26:44.167295 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 12:26:44.170669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 12:26:44.170796 ==
6524 12:26:44.170869
6525 12:26:44.170967
6526 12:26:44.173761 TX Vref Scan disable
6527 12:26:44.173862 == TX Byte 0 ==
6528 12:26:44.180737 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6529 12:26:44.183850 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6530 12:26:44.183962 == TX Byte 1 ==
6531 12:26:44.190792 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6532 12:26:44.193890 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6533 12:26:44.194021 ==
6534 12:26:44.197131 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 12:26:44.200840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 12:26:44.201001 ==
6537 12:26:44.201105
6538 12:26:44.201186
6539 12:26:44.204149 TX Vref Scan disable
6540 12:26:44.204270 == TX Byte 0 ==
6541 12:26:44.210803 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6542 12:26:44.214066 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6543 12:26:44.214201 == TX Byte 1 ==
6544 12:26:44.220885 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6545 12:26:44.223879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6546 12:26:44.224023
6547 12:26:44.224097 [DATLAT]
6548 12:26:44.226872 Freq=400, CH0 RK1
6549 12:26:44.226989
6550 12:26:44.227061 DATLAT Default: 0xe
6551 12:26:44.230152 0, 0xFFFF, sum = 0
6552 12:26:44.230296 1, 0xFFFF, sum = 0
6553 12:26:44.233456 2, 0xFFFF, sum = 0
6554 12:26:44.233601 3, 0xFFFF, sum = 0
6555 12:26:44.237111 4, 0xFFFF, sum = 0
6556 12:26:44.237329 5, 0xFFFF, sum = 0
6557 12:26:44.240248 6, 0xFFFF, sum = 0
6558 12:26:44.240375 7, 0xFFFF, sum = 0
6559 12:26:44.243333 8, 0xFFFF, sum = 0
6560 12:26:44.243461 9, 0xFFFF, sum = 0
6561 12:26:44.247097 10, 0xFFFF, sum = 0
6562 12:26:44.250217 11, 0xFFFF, sum = 0
6563 12:26:44.250378 12, 0xFFFF, sum = 0
6564 12:26:44.253179 13, 0x0, sum = 1
6565 12:26:44.253316 14, 0x0, sum = 2
6566 12:26:44.256825 15, 0x0, sum = 3
6567 12:26:44.256971 16, 0x0, sum = 4
6568 12:26:44.257070 best_step = 14
6569 12:26:44.257152
6570 12:26:44.260310 ==
6571 12:26:44.260439 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 12:26:44.267050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 12:26:44.267234 ==
6574 12:26:44.267335 RX Vref Scan: 0
6575 12:26:44.267421
6576 12:26:44.270192 RX Vref 0 -> 0, step: 1
6577 12:26:44.270332
6578 12:26:44.273235 RX Delay -343 -> 252, step: 8
6579 12:26:44.279951 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6580 12:26:44.283768 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6581 12:26:44.286882 iDelay=217, Bit 2, Center -32 (-271 ~ 208) 480
6582 12:26:44.290012 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6583 12:26:44.297193 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6584 12:26:44.300100 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6585 12:26:44.303237 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6586 12:26:44.306405 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6587 12:26:44.313197 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6588 12:26:44.316703 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6589 12:26:44.320055 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6590 12:26:44.326786 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6591 12:26:44.329981 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6592 12:26:44.333111 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6593 12:26:44.336390 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6594 12:26:44.343192 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6595 12:26:44.343403 ==
6596 12:26:44.346412 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 12:26:44.349640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 12:26:44.349812 ==
6599 12:26:44.349925 DQS Delay:
6600 12:26:44.353268 DQS0 = 48, DQS1 = 56
6601 12:26:44.353423 DQM Delay:
6602 12:26:44.356340 DQM0 = 14, DQM1 = 10
6603 12:26:44.356516 DQ Delay:
6604 12:26:44.359510 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =12
6605 12:26:44.363124 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6606 12:26:44.366481 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =0
6607 12:26:44.370011 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =20
6608 12:26:44.370157
6609 12:26:44.370228
6610 12:26:44.376642 [DQSOSCAuto] RK1, (LSB)MR18= 0x9466, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6611 12:26:44.379591 CH0 RK1: MR19=C0C, MR18=9466
6612 12:26:44.386278 CH0_RK1: MR19=0xC0C, MR18=0x9466, DQSOSC=391, MR23=63, INC=386, DEC=257
6613 12:26:44.389619 [RxdqsGatingPostProcess] freq 400
6614 12:26:44.396349 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6615 12:26:44.399652 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 12:26:44.399783 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 12:26:44.402790 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 12:26:44.406522 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 12:26:44.409762 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 12:26:44.412867 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 12:26:44.416459 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 12:26:44.419537 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 12:26:44.422719 Pre-setting of DQS Precalculation
6624 12:26:44.429620 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6625 12:26:44.429788 ==
6626 12:26:44.432833 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 12:26:44.436465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 12:26:44.436600 ==
6629 12:26:44.442779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 12:26:44.446586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 12:26:44.449693 [CA 0] Center 36 (8~64) winsize 57
6632 12:26:44.452905 [CA 1] Center 36 (8~64) winsize 57
6633 12:26:44.456550 [CA 2] Center 36 (8~64) winsize 57
6634 12:26:44.459873 [CA 3] Center 36 (8~64) winsize 57
6635 12:26:44.462940 [CA 4] Center 36 (8~64) winsize 57
6636 12:26:44.465989 [CA 5] Center 36 (8~64) winsize 57
6637 12:26:44.466116
6638 12:26:44.469804 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 12:26:44.469943
6640 12:26:44.472703 [CATrainingPosCal] consider 1 rank data
6641 12:26:44.476254 u2DelayCellTimex100 = 270/100 ps
6642 12:26:44.479128 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:26:44.482702 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:26:44.489423 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:26:44.492886 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:26:44.495874 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:26:44.498952 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:26:44.499079
6649 12:26:44.502846 CA PerBit enable=1, Macro0, CA PI delay=36
6650 12:26:44.502972
6651 12:26:44.505995 [CBTSetCACLKResult] CA Dly = 36
6652 12:26:44.506112 CS Dly: 1 (0~32)
6653 12:26:44.506192 ==
6654 12:26:44.509124 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 12:26:44.516153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 12:26:44.516308 ==
6657 12:26:44.519269 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 12:26:44.526010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6659 12:26:44.529143 [CA 0] Center 36 (8~64) winsize 57
6660 12:26:44.532314 [CA 1] Center 36 (8~64) winsize 57
6661 12:26:44.535994 [CA 2] Center 36 (8~64) winsize 57
6662 12:26:44.539144 [CA 3] Center 36 (8~64) winsize 57
6663 12:26:44.542268 [CA 4] Center 36 (8~64) winsize 57
6664 12:26:44.545881 [CA 5] Center 36 (8~64) winsize 57
6665 12:26:44.545997
6666 12:26:44.548940 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6667 12:26:44.549035
6668 12:26:44.552248 [CATrainingPosCal] consider 2 rank data
6669 12:26:44.555364 u2DelayCellTimex100 = 270/100 ps
6670 12:26:44.558550 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:26:44.562396 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:26:44.565517 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 12:26:44.568748 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 12:26:44.571937 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:26:44.578876 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 12:26:44.579033
6677 12:26:44.581782 CA PerBit enable=1, Macro0, CA PI delay=36
6678 12:26:44.581888
6679 12:26:44.585401 [CBTSetCACLKResult] CA Dly = 36
6680 12:26:44.585547 CS Dly: 1 (0~32)
6681 12:26:44.585622
6682 12:26:44.588941 ----->DramcWriteLeveling(PI) begin...
6683 12:26:44.589051 ==
6684 12:26:44.591981 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 12:26:44.598826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 12:26:44.599025 ==
6687 12:26:44.599141 Write leveling (Byte 0): 40 => 8
6688 12:26:44.601676 Write leveling (Byte 1): 40 => 8
6689 12:26:44.605423 DramcWriteLeveling(PI) end<-----
6690 12:26:44.605593
6691 12:26:44.605702 ==
6692 12:26:44.608364 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 12:26:44.615362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 12:26:44.615554 ==
6695 12:26:44.618578 [Gating] SW mode calibration
6696 12:26:44.624995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6697 12:26:44.628084 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6698 12:26:44.634992 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6699 12:26:44.638196 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 12:26:44.641952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 12:26:44.648276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 12:26:44.652061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 12:26:44.655164 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 12:26:44.658234 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 12:26:44.665063 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 12:26:44.668155 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 12:26:44.671949 Total UI for P1: 0, mck2ui 16
6708 12:26:44.674985 best dqsien dly found for B0: ( 0, 14, 24)
6709 12:26:44.678113 Total UI for P1: 0, mck2ui 16
6710 12:26:44.681294 best dqsien dly found for B1: ( 0, 14, 24)
6711 12:26:44.685139 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6712 12:26:44.688333 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6713 12:26:44.688492
6714 12:26:44.691271 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 12:26:44.698354 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 12:26:44.698553 [Gating] SW calibration Done
6717 12:26:44.698671 ==
6718 12:26:44.701727 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 12:26:44.708246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 12:26:44.708438 ==
6721 12:26:44.708551 RX Vref Scan: 0
6722 12:26:44.708652
6723 12:26:44.711185 RX Vref 0 -> 0, step: 1
6724 12:26:44.711310
6725 12:26:44.714713 RX Delay -410 -> 252, step: 16
6726 12:26:44.718299 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6727 12:26:44.721365 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6728 12:26:44.728365 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6729 12:26:44.731545 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6730 12:26:44.734467 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6731 12:26:44.737713 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6732 12:26:44.744594 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6733 12:26:44.747792 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6734 12:26:44.751036 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6735 12:26:44.754677 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6736 12:26:44.761485 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6737 12:26:44.764652 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6738 12:26:44.767958 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6739 12:26:44.771054 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6740 12:26:44.777886 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6741 12:26:44.780973 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6742 12:26:44.781094 ==
6743 12:26:44.783982 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 12:26:44.787745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 12:26:44.787862 ==
6746 12:26:44.790948 DQS Delay:
6747 12:26:44.791049 DQS0 = 51, DQS1 = 59
6748 12:26:44.794089 DQM Delay:
6749 12:26:44.794189 DQM0 = 19, DQM1 = 16
6750 12:26:44.794260 DQ Delay:
6751 12:26:44.797806 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6752 12:26:44.801036 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6753 12:26:44.803907 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6754 12:26:44.807360 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6755 12:26:44.807494
6756 12:26:44.807597
6757 12:26:44.807682 ==
6758 12:26:44.810849 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 12:26:44.817784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 12:26:44.817919 ==
6761 12:26:44.817992
6762 12:26:44.818055
6763 12:26:44.818115 TX Vref Scan disable
6764 12:26:44.820842 == TX Byte 0 ==
6765 12:26:44.824202 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 12:26:44.827259 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 12:26:44.830751 == TX Byte 1 ==
6768 12:26:44.834320 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 12:26:44.837486 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 12:26:44.840547 ==
6771 12:26:44.840690 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:26:44.847538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:26:44.847719 ==
6774 12:26:44.847821
6775 12:26:44.847919
6776 12:26:44.850706 TX Vref Scan disable
6777 12:26:44.850823 == TX Byte 0 ==
6778 12:26:44.853976 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 12:26:44.860711 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 12:26:44.860943 == TX Byte 1 ==
6781 12:26:44.863998 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 12:26:44.866984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 12:26:44.871010
6784 12:26:44.871163 [DATLAT]
6785 12:26:44.871267 Freq=400, CH1 RK0
6786 12:26:44.871370
6787 12:26:44.873864 DATLAT Default: 0xf
6788 12:26:44.873982 0, 0xFFFF, sum = 0
6789 12:26:44.876947 1, 0xFFFF, sum = 0
6790 12:26:44.877078 2, 0xFFFF, sum = 0
6791 12:26:44.880731 3, 0xFFFF, sum = 0
6792 12:26:44.880860 4, 0xFFFF, sum = 0
6793 12:26:44.883851 5, 0xFFFF, sum = 0
6794 12:26:44.887034 6, 0xFFFF, sum = 0
6795 12:26:44.887162 7, 0xFFFF, sum = 0
6796 12:26:44.890843 8, 0xFFFF, sum = 0
6797 12:26:44.890974 9, 0xFFFF, sum = 0
6798 12:26:44.893966 10, 0xFFFF, sum = 0
6799 12:26:44.894091 11, 0xFFFF, sum = 0
6800 12:26:44.896923 12, 0xFFFF, sum = 0
6801 12:26:44.897052 13, 0x0, sum = 1
6802 12:26:44.900680 14, 0x0, sum = 2
6803 12:26:44.900796 15, 0x0, sum = 3
6804 12:26:44.903802 16, 0x0, sum = 4
6805 12:26:44.903934 best_step = 14
6806 12:26:44.904035
6807 12:26:44.904106 ==
6808 12:26:44.906909 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 12:26:44.910606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 12:26:44.910712 ==
6811 12:26:44.913519 RX Vref Scan: 1
6812 12:26:44.913618
6813 12:26:44.917137 RX Vref 0 -> 0, step: 1
6814 12:26:44.917237
6815 12:26:44.917332 RX Delay -359 -> 252, step: 8
6816 12:26:44.920439
6817 12:26:44.920589 Set Vref, RX VrefLevel [Byte0]: 57
6818 12:26:44.924048 [Byte1]: 45
6819 12:26:44.929363
6820 12:26:44.929510 Final RX Vref Byte 0 = 57 to rank0
6821 12:26:44.932903 Final RX Vref Byte 1 = 45 to rank0
6822 12:26:44.935631 Final RX Vref Byte 0 = 57 to rank1
6823 12:26:44.939315 Final RX Vref Byte 1 = 45 to rank1==
6824 12:26:44.942417 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 12:26:44.949336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 12:26:44.949478 ==
6827 12:26:44.949556 DQS Delay:
6828 12:26:44.952515 DQS0 = 48, DQS1 = 60
6829 12:26:44.952617 DQM Delay:
6830 12:26:44.952695 DQM0 = 12, DQM1 = 12
6831 12:26:44.955780 DQ Delay:
6832 12:26:44.959460 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6833 12:26:44.959578 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6834 12:26:44.962749 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6835 12:26:44.965857 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6836 12:26:44.965999
6837 12:26:44.968998
6838 12:26:44.975862 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6839 12:26:44.978982 CH1 RK0: MR19=C0C, MR18=8B32
6840 12:26:44.985848 CH1_RK0: MR19=0xC0C, MR18=0x8B32, DQSOSC=392, MR23=63, INC=384, DEC=256
6841 12:26:44.985986 ==
6842 12:26:44.989020 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 12:26:44.992174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 12:26:44.992273 ==
6845 12:26:44.995344 [Gating] SW mode calibration
6846 12:26:45.002302 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6847 12:26:45.009109 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6848 12:26:45.012275 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 12:26:45.015319 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 12:26:45.022291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 12:26:45.025860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 12:26:45.028715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 12:26:45.035263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 12:26:45.038802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 12:26:45.042234 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 12:26:45.048527 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 12:26:45.048682 Total UI for P1: 0, mck2ui 16
6858 12:26:45.052203 best dqsien dly found for B0: ( 0, 14, 24)
6859 12:26:45.055226 Total UI for P1: 0, mck2ui 16
6860 12:26:45.058349 best dqsien dly found for B1: ( 0, 14, 24)
6861 12:26:45.065174 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6862 12:26:45.068164 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6863 12:26:45.068285
6864 12:26:45.072076 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 12:26:45.075194 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 12:26:45.078793 [Gating] SW calibration Done
6867 12:26:45.078902 ==
6868 12:26:45.081908 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 12:26:45.085193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 12:26:45.085295 ==
6871 12:26:45.088440 RX Vref Scan: 0
6872 12:26:45.088538
6873 12:26:45.088608 RX Vref 0 -> 0, step: 1
6874 12:26:45.088671
6875 12:26:45.091707 RX Delay -410 -> 252, step: 16
6876 12:26:45.095701 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6877 12:26:45.101776 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6878 12:26:45.104997 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6879 12:26:45.108765 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6880 12:26:45.111986 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6881 12:26:45.118321 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6882 12:26:45.122137 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6883 12:26:45.125220 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6884 12:26:45.128566 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6885 12:26:45.135086 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6886 12:26:45.138180 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6887 12:26:45.141607 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6888 12:26:45.145083 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6889 12:26:45.151789 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6890 12:26:45.155346 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6891 12:26:45.158334 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6892 12:26:45.158543 ==
6893 12:26:45.161875 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 12:26:45.168579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 12:26:45.168782 ==
6896 12:26:45.168897 DQS Delay:
6897 12:26:45.171716 DQS0 = 43, DQS1 = 51
6898 12:26:45.171846 DQM Delay:
6899 12:26:45.171951 DQM0 = 9, DQM1 = 9
6900 12:26:45.174842 DQ Delay:
6901 12:26:45.174970 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6902 12:26:45.178689 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6903 12:26:45.181817 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6904 12:26:45.184980 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6905 12:26:45.185091
6906 12:26:45.185161
6907 12:26:45.185224 ==
6908 12:26:45.188181 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 12:26:45.195067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 12:26:45.195243 ==
6911 12:26:45.195343
6912 12:26:45.195434
6913 12:26:45.198104 TX Vref Scan disable
6914 12:26:45.198213 == TX Byte 0 ==
6915 12:26:45.201307 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 12:26:45.205018 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 12:26:45.208254 == TX Byte 1 ==
6918 12:26:45.211326 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6919 12:26:45.214681 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6920 12:26:45.217911 ==
6921 12:26:45.221730 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 12:26:45.224770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 12:26:45.224905 ==
6924 12:26:45.224979
6925 12:26:45.225043
6926 12:26:45.227966 TX Vref Scan disable
6927 12:26:45.228078 == TX Byte 0 ==
6928 12:26:45.231234 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6929 12:26:45.237936 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6930 12:26:45.238106 == TX Byte 1 ==
6931 12:26:45.240984 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6932 12:26:45.247892 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6933 12:26:45.248043
6934 12:26:45.248142 [DATLAT]
6935 12:26:45.248226 Freq=400, CH1 RK1
6936 12:26:45.248308
6937 12:26:45.251337 DATLAT Default: 0xe
6938 12:26:45.251448 0, 0xFFFF, sum = 0
6939 12:26:45.254276 1, 0xFFFF, sum = 0
6940 12:26:45.257880 2, 0xFFFF, sum = 0
6941 12:26:45.258037 3, 0xFFFF, sum = 0
6942 12:26:45.261180 4, 0xFFFF, sum = 0
6943 12:26:45.261333 5, 0xFFFF, sum = 0
6944 12:26:45.264836 6, 0xFFFF, sum = 0
6945 12:26:45.265024 7, 0xFFFF, sum = 0
6946 12:26:45.267901 8, 0xFFFF, sum = 0
6947 12:26:45.268045 9, 0xFFFF, sum = 0
6948 12:26:45.271016 10, 0xFFFF, sum = 0
6949 12:26:45.271141 11, 0xFFFF, sum = 0
6950 12:26:45.274149 12, 0xFFFF, sum = 0
6951 12:26:45.274254 13, 0x0, sum = 1
6952 12:26:45.277927 14, 0x0, sum = 2
6953 12:26:45.278035 15, 0x0, sum = 3
6954 12:26:45.281060 16, 0x0, sum = 4
6955 12:26:45.281157 best_step = 14
6956 12:26:45.281228
6957 12:26:45.281293 ==
6958 12:26:45.284276 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 12:26:45.287375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 12:26:45.291210 ==
6961 12:26:45.291326 RX Vref Scan: 0
6962 12:26:45.291428
6963 12:26:45.294212 RX Vref 0 -> 0, step: 1
6964 12:26:45.294341
6965 12:26:45.297503 RX Delay -343 -> 252, step: 8
6966 12:26:45.300749 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6967 12:26:45.307584 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6968 12:26:45.310734 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6969 12:26:45.313923 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6970 12:26:45.317790 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6971 12:26:45.323825 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6972 12:26:45.327488 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6973 12:26:45.330786 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6974 12:26:45.333840 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6975 12:26:45.340916 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6976 12:26:45.343897 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6977 12:26:45.347021 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6978 12:26:45.353981 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6979 12:26:45.357092 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6980 12:26:45.360430 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6981 12:26:45.364087 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6982 12:26:45.364214 ==
6983 12:26:45.367097 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 12:26:45.373656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 12:26:45.373797 ==
6986 12:26:45.373898 DQS Delay:
6987 12:26:45.377151 DQS0 = 52, DQS1 = 60
6988 12:26:45.377302 DQM Delay:
6989 12:26:45.380219 DQM0 = 13, DQM1 = 14
6990 12:26:45.380333 DQ Delay:
6991 12:26:45.383789 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6992 12:26:45.386843 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6993 12:26:45.387012 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6994 12:26:45.393777 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6995 12:26:45.393906
6996 12:26:45.394007
6997 12:26:45.400756 [DQSOSCAuto] RK1, (LSB)MR18= 0x748a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6998 12:26:45.403972 CH1 RK1: MR19=C0C, MR18=748A
6999 12:26:45.410171 CH1_RK1: MR19=0xC0C, MR18=0x748A, DQSOSC=392, MR23=63, INC=384, DEC=256
7000 12:26:45.413518 [RxdqsGatingPostProcess] freq 400
7001 12:26:45.417283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7002 12:26:45.420399 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 12:26:45.423563 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 12:26:45.427203 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 12:26:45.430383 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 12:26:45.433549 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 12:26:45.437291 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 12:26:45.440564 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 12:26:45.443615 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 12:26:45.447201 Pre-setting of DQS Precalculation
7011 12:26:45.450257 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7012 12:26:45.457443 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7013 12:26:45.467161 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7014 12:26:45.467359
7015 12:26:45.467475
7016 12:26:45.467570 [Calibration Summary] 800 Mbps
7017 12:26:45.470329 CH 0, Rank 0
7018 12:26:45.474002 SW Impedance : PASS
7019 12:26:45.474153 DUTY Scan : NO K
7020 12:26:45.477164 ZQ Calibration : PASS
7021 12:26:45.477291 Jitter Meter : NO K
7022 12:26:45.480270 CBT Training : PASS
7023 12:26:45.484045 Write leveling : PASS
7024 12:26:45.484170 RX DQS gating : PASS
7025 12:26:45.487102 RX DQ/DQS(RDDQC) : PASS
7026 12:26:45.490312 TX DQ/DQS : PASS
7027 12:26:45.490431 RX DATLAT : PASS
7028 12:26:45.493850 RX DQ/DQS(Engine): PASS
7029 12:26:45.496933 TX OE : NO K
7030 12:26:45.497060 All Pass.
7031 12:26:45.497171
7032 12:26:45.497262 CH 0, Rank 1
7033 12:26:45.500709 SW Impedance : PASS
7034 12:26:45.503852 DUTY Scan : NO K
7035 12:26:45.503946 ZQ Calibration : PASS
7036 12:26:45.507092 Jitter Meter : NO K
7037 12:26:45.510128 CBT Training : PASS
7038 12:26:45.510217 Write leveling : NO K
7039 12:26:45.513934 RX DQS gating : PASS
7040 12:26:45.517141 RX DQ/DQS(RDDQC) : PASS
7041 12:26:45.517253 TX DQ/DQS : PASS
7042 12:26:45.520157 RX DATLAT : PASS
7043 12:26:45.520246 RX DQ/DQS(Engine): PASS
7044 12:26:45.524064 TX OE : NO K
7045 12:26:45.524203 All Pass.
7046 12:26:45.524329
7047 12:26:45.527187 CH 1, Rank 0
7048 12:26:45.527307 SW Impedance : PASS
7049 12:26:45.530403 DUTY Scan : NO K
7050 12:26:45.533467 ZQ Calibration : PASS
7051 12:26:45.533580 Jitter Meter : NO K
7052 12:26:45.537194 CBT Training : PASS
7053 12:26:45.540305 Write leveling : PASS
7054 12:26:45.540410 RX DQS gating : PASS
7055 12:26:45.543337 RX DQ/DQS(RDDQC) : PASS
7056 12:26:45.546671 TX DQ/DQS : PASS
7057 12:26:45.546782 RX DATLAT : PASS
7058 12:26:45.550554 RX DQ/DQS(Engine): PASS
7059 12:26:45.553565 TX OE : NO K
7060 12:26:45.553667 All Pass.
7061 12:26:45.553735
7062 12:26:45.553798 CH 1, Rank 1
7063 12:26:45.557100 SW Impedance : PASS
7064 12:26:45.560295 DUTY Scan : NO K
7065 12:26:45.560412 ZQ Calibration : PASS
7066 12:26:45.563275 Jitter Meter : NO K
7067 12:26:45.566967 CBT Training : PASS
7068 12:26:45.567073 Write leveling : NO K
7069 12:26:45.570083 RX DQS gating : PASS
7070 12:26:45.573136 RX DQ/DQS(RDDQC) : PASS
7071 12:26:45.573232 TX DQ/DQS : PASS
7072 12:26:45.576418 RX DATLAT : PASS
7073 12:26:45.576531 RX DQ/DQS(Engine): PASS
7074 12:26:45.579894 TX OE : NO K
7075 12:26:45.579987 All Pass.
7076 12:26:45.580056
7077 12:26:45.583340 DramC Write-DBI off
7078 12:26:45.586378 PER_BANK_REFRESH: Hybrid Mode
7079 12:26:45.586493 TX_TRACKING: ON
7080 12:26:45.596651 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7081 12:26:45.599628 [FAST_K] Save calibration result to emmc
7082 12:26:45.603290 dramc_set_vcore_voltage set vcore to 725000
7083 12:26:45.606362 Read voltage for 1600, 0
7084 12:26:45.606460 Vio18 = 0
7085 12:26:45.609530 Vcore = 725000
7086 12:26:45.609622 Vdram = 0
7087 12:26:45.609693 Vddq = 0
7088 12:26:45.609757 Vmddr = 0
7089 12:26:45.616558 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7090 12:26:45.622972 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7091 12:26:45.623109 MEM_TYPE=3, freq_sel=13
7092 12:26:45.626083 sv_algorithm_assistance_LP4_3733
7093 12:26:45.629935 ============ PULL DRAM RESETB DOWN ============
7094 12:26:45.635999 ========== PULL DRAM RESETB DOWN end =========
7095 12:26:45.639920 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7096 12:26:45.643038 ===================================
7097 12:26:45.646163 LPDDR4 DRAM CONFIGURATION
7098 12:26:45.649360 ===================================
7099 12:26:45.649465 EX_ROW_EN[0] = 0x0
7100 12:26:45.652664 EX_ROW_EN[1] = 0x0
7101 12:26:45.652758 LP4Y_EN = 0x0
7102 12:26:45.656322 WORK_FSP = 0x1
7103 12:26:45.656414 WL = 0x5
7104 12:26:45.659327 RL = 0x5
7105 12:26:45.659448 BL = 0x2
7106 12:26:45.662993 RPST = 0x0
7107 12:26:45.666207 RD_PRE = 0x0
7108 12:26:45.666303 WR_PRE = 0x1
7109 12:26:45.669358 WR_PST = 0x1
7110 12:26:45.669454 DBI_WR = 0x0
7111 12:26:45.673152 DBI_RD = 0x0
7112 12:26:45.673276 OTF = 0x1
7113 12:26:45.676255 ===================================
7114 12:26:45.679297 ===================================
7115 12:26:45.679409 ANA top config
7116 12:26:45.682912 ===================================
7117 12:26:45.686264 DLL_ASYNC_EN = 0
7118 12:26:45.689175 ALL_SLAVE_EN = 0
7119 12:26:45.692600 NEW_RANK_MODE = 1
7120 12:26:45.696168 DLL_IDLE_MODE = 1
7121 12:26:45.696288 LP45_APHY_COMB_EN = 1
7122 12:26:45.699280 TX_ODT_DIS = 0
7123 12:26:45.702885 NEW_8X_MODE = 1
7124 12:26:45.705868 ===================================
7125 12:26:45.709572 ===================================
7126 12:26:45.712697 data_rate = 3200
7127 12:26:45.716079 CKR = 1
7128 12:26:45.716192 DQ_P2S_RATIO = 8
7129 12:26:45.719136 ===================================
7130 12:26:45.722890 CA_P2S_RATIO = 8
7131 12:26:45.726086 DQ_CA_OPEN = 0
7132 12:26:45.729304 DQ_SEMI_OPEN = 0
7133 12:26:45.732455 CA_SEMI_OPEN = 0
7134 12:26:45.736054 CA_FULL_RATE = 0
7135 12:26:45.736151 DQ_CKDIV4_EN = 0
7136 12:26:45.739214 CA_CKDIV4_EN = 0
7137 12:26:45.742296 CA_PREDIV_EN = 0
7138 12:26:45.746173 PH8_DLY = 12
7139 12:26:45.749393 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7140 12:26:45.752485 DQ_AAMCK_DIV = 4
7141 12:26:45.752597 CA_AAMCK_DIV = 4
7142 12:26:45.756195 CA_ADMCK_DIV = 4
7143 12:26:45.759261 DQ_TRACK_CA_EN = 0
7144 12:26:45.762326 CA_PICK = 1600
7145 12:26:45.765937 CA_MCKIO = 1600
7146 12:26:45.768908 MCKIO_SEMI = 0
7147 12:26:45.772825 PLL_FREQ = 3068
7148 12:26:45.772919 DQ_UI_PI_RATIO = 32
7149 12:26:45.776166 CA_UI_PI_RATIO = 0
7150 12:26:45.779039 ===================================
7151 12:26:45.782229 ===================================
7152 12:26:45.786041 memory_type:LPDDR4
7153 12:26:45.789229 GP_NUM : 10
7154 12:26:45.789354 SRAM_EN : 1
7155 12:26:45.792276 MD32_EN : 0
7156 12:26:45.795688 ===================================
7157 12:26:45.799062 [ANA_INIT] >>>>>>>>>>>>>>
7158 12:26:45.799165 <<<<<< [CONFIGURE PHASE]: ANA_TX
7159 12:26:45.805548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7160 12:26:45.808640 ===================================
7161 12:26:45.808768 data_rate = 3200,PCW = 0X7600
7162 12:26:45.812163 ===================================
7163 12:26:45.815762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7164 12:26:45.822100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 12:26:45.829136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 12:26:45.832164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7167 12:26:45.835366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7168 12:26:45.838465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7169 12:26:45.841639 [ANA_INIT] flow start
7170 12:26:45.841740 [ANA_INIT] PLL >>>>>>>>
7171 12:26:45.845364 [ANA_INIT] PLL <<<<<<<<
7172 12:26:45.848425 [ANA_INIT] MIDPI >>>>>>>>
7173 12:26:45.851732 [ANA_INIT] MIDPI <<<<<<<<
7174 12:26:45.851837 [ANA_INIT] DLL >>>>>>>>
7175 12:26:45.855318 [ANA_INIT] DLL <<<<<<<<
7176 12:26:45.855432 [ANA_INIT] flow end
7177 12:26:45.861744 ============ LP4 DIFF to SE enter ============
7178 12:26:45.865354 ============ LP4 DIFF to SE exit ============
7179 12:26:45.868703 [ANA_INIT] <<<<<<<<<<<<<
7180 12:26:45.871922 [Flow] Enable top DCM control >>>>>
7181 12:26:45.874871 [Flow] Enable top DCM control <<<<<
7182 12:26:45.878701 Enable DLL master slave shuffle
7183 12:26:45.881781 ==============================================================
7184 12:26:45.884812 Gating Mode config
7185 12:26:45.888746 ==============================================================
7186 12:26:45.891877 Config description:
7187 12:26:45.901491 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7188 12:26:45.908479 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7189 12:26:45.911403 SELPH_MODE 0: By rank 1: By Phase
7190 12:26:45.918225 ==============================================================
7191 12:26:45.921829 GAT_TRACK_EN = 1
7192 12:26:45.924979 RX_GATING_MODE = 2
7193 12:26:45.928066 RX_GATING_TRACK_MODE = 2
7194 12:26:45.931753 SELPH_MODE = 1
7195 12:26:45.935069 PICG_EARLY_EN = 1
7196 12:26:45.935203 VALID_LAT_VALUE = 1
7197 12:26:45.941471 ==============================================================
7198 12:26:45.944738 Enter into Gating configuration >>>>
7199 12:26:45.948009 Exit from Gating configuration <<<<
7200 12:26:45.951677 Enter into DVFS_PRE_config >>>>>
7201 12:26:45.961699 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7202 12:26:45.964970 Exit from DVFS_PRE_config <<<<<
7203 12:26:45.967913 Enter into PICG configuration >>>>
7204 12:26:45.971631 Exit from PICG configuration <<<<
7205 12:26:45.974670 [RX_INPUT] configuration >>>>>
7206 12:26:45.978380 [RX_INPUT] configuration <<<<<
7207 12:26:45.981482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7208 12:26:45.987943 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7209 12:26:45.994354 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 12:26:46.001390 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 12:26:46.007638 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 12:26:46.014452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 12:26:46.017933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7214 12:26:46.021274 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7215 12:26:46.024174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7216 12:26:46.030678 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7217 12:26:46.034504 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7218 12:26:46.037454 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 12:26:46.040631 ===================================
7220 12:26:46.044280 LPDDR4 DRAM CONFIGURATION
7221 12:26:46.047461 ===================================
7222 12:26:46.047556 EX_ROW_EN[0] = 0x0
7223 12:26:46.050812 EX_ROW_EN[1] = 0x0
7224 12:26:46.053859 LP4Y_EN = 0x0
7225 12:26:46.053962 WORK_FSP = 0x1
7226 12:26:46.057110 WL = 0x5
7227 12:26:46.057206 RL = 0x5
7228 12:26:46.060891 BL = 0x2
7229 12:26:46.061004 RPST = 0x0
7230 12:26:46.063976 RD_PRE = 0x0
7231 12:26:46.064071 WR_PRE = 0x1
7232 12:26:46.067120 WR_PST = 0x1
7233 12:26:46.067213 DBI_WR = 0x0
7234 12:26:46.070926 DBI_RD = 0x0
7235 12:26:46.071054 OTF = 0x1
7236 12:26:46.074123 ===================================
7237 12:26:46.077208 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7238 12:26:46.084077 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7239 12:26:46.087155 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 12:26:46.090351 ===================================
7241 12:26:46.094057 LPDDR4 DRAM CONFIGURATION
7242 12:26:46.097251 ===================================
7243 12:26:46.097393 EX_ROW_EN[0] = 0x10
7244 12:26:46.100427 EX_ROW_EN[1] = 0x0
7245 12:26:46.100538 LP4Y_EN = 0x0
7246 12:26:46.104339 WORK_FSP = 0x1
7247 12:26:46.107271 WL = 0x5
7248 12:26:46.107394 RL = 0x5
7249 12:26:46.110396 BL = 0x2
7250 12:26:46.110486 RPST = 0x0
7251 12:26:46.113576 RD_PRE = 0x0
7252 12:26:46.113698 WR_PRE = 0x1
7253 12:26:46.117363 WR_PST = 0x1
7254 12:26:46.117479 DBI_WR = 0x0
7255 12:26:46.120561 DBI_RD = 0x0
7256 12:26:46.120664 OTF = 0x1
7257 12:26:46.123443 ===================================
7258 12:26:46.130029 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7259 12:26:46.130194 ==
7260 12:26:46.133558 Dram Type= 6, Freq= 0, CH_0, rank 0
7261 12:26:46.137207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7262 12:26:46.137304 ==
7263 12:26:46.139919 [Duty_Offset_Calibration]
7264 12:26:46.143311 B0:2 B1:-1 CA:1
7265 12:26:46.143425
7266 12:26:46.146406 [DutyScan_Calibration_Flow] k_type=0
7267 12:26:46.154581
7268 12:26:46.154733 ==CLK 0==
7269 12:26:46.158335 Final CLK duty delay cell = -4
7270 12:26:46.161432 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7271 12:26:46.164672 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7272 12:26:46.167815 [-4] AVG Duty = 4922%(X100)
7273 12:26:46.167934
7274 12:26:46.170857 CH0 CLK Duty spec in!! Max-Min= 156%
7275 12:26:46.174577 [DutyScan_Calibration_Flow] ====Done====
7276 12:26:46.174693
7277 12:26:46.177683 [DutyScan_Calibration_Flow] k_type=1
7278 12:26:46.193985
7279 12:26:46.194141 ==DQS 0 ==
7280 12:26:46.197679 Final DQS duty delay cell = 0
7281 12:26:46.200878 [0] MAX Duty = 5125%(X100), DQS PI = 54
7282 12:26:46.204003 [0] MIN Duty = 5000%(X100), DQS PI = 16
7283 12:26:46.207308 [0] AVG Duty = 5062%(X100)
7284 12:26:46.207422
7285 12:26:46.207492 ==DQS 1 ==
7286 12:26:46.210461 Final DQS duty delay cell = -4
7287 12:26:46.213635 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7288 12:26:46.216914 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7289 12:26:46.220665 [-4] AVG Duty = 5046%(X100)
7290 12:26:46.220780
7291 12:26:46.223566 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7292 12:26:46.223658
7293 12:26:46.227059 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7294 12:26:46.230230 [DutyScan_Calibration_Flow] ====Done====
7295 12:26:46.230326
7296 12:26:46.233510 [DutyScan_Calibration_Flow] k_type=3
7297 12:26:46.251470
7298 12:26:46.251624 ==DQM 0 ==
7299 12:26:46.254775 Final DQM duty delay cell = 0
7300 12:26:46.258401 [0] MAX Duty = 5000%(X100), DQS PI = 20
7301 12:26:46.261498 [0] MIN Duty = 4875%(X100), DQS PI = 6
7302 12:26:46.264690 [0] AVG Duty = 4937%(X100)
7303 12:26:46.264799
7304 12:26:46.264870 ==DQM 1 ==
7305 12:26:46.268305 Final DQM duty delay cell = 0
7306 12:26:46.271695 [0] MAX Duty = 5156%(X100), DQS PI = 56
7307 12:26:46.274842 [0] MIN Duty = 4969%(X100), DQS PI = 18
7308 12:26:46.274946 [0] AVG Duty = 5062%(X100)
7309 12:26:46.278532
7310 12:26:46.281617 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7311 12:26:46.281715
7312 12:26:46.284907 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7313 12:26:46.288009 [DutyScan_Calibration_Flow] ====Done====
7314 12:26:46.288116
7315 12:26:46.291802 [DutyScan_Calibration_Flow] k_type=2
7316 12:26:46.308217
7317 12:26:46.308370 ==DQ 0 ==
7318 12:26:46.311229 Final DQ duty delay cell = -4
7319 12:26:46.314538 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7320 12:26:46.317718 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7321 12:26:46.321477 [-4] AVG Duty = 4922%(X100)
7322 12:26:46.321568
7323 12:26:46.321632 ==DQ 1 ==
7324 12:26:46.324825 Final DQ duty delay cell = 0
7325 12:26:46.327875 [0] MAX Duty = 5031%(X100), DQS PI = 14
7326 12:26:46.331116 [0] MIN Duty = 4938%(X100), DQS PI = 8
7327 12:26:46.331237 [0] AVG Duty = 4984%(X100)
7328 12:26:46.334476
7329 12:26:46.337804 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7330 12:26:46.337890
7331 12:26:46.341361 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7332 12:26:46.344453 [DutyScan_Calibration_Flow] ====Done====
7333 12:26:46.344539 ==
7334 12:26:46.348067 Dram Type= 6, Freq= 0, CH_1, rank 0
7335 12:26:46.351424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7336 12:26:46.351557 ==
7337 12:26:46.354499 [Duty_Offset_Calibration]
7338 12:26:46.354591 B0:1 B1:1 CA:2
7339 12:26:46.354658
7340 12:26:46.357505 [DutyScan_Calibration_Flow] k_type=0
7341 12:26:46.368235
7342 12:26:46.368384 ==CLK 0==
7343 12:26:46.371818 Final CLK duty delay cell = 0
7344 12:26:46.374896 [0] MAX Duty = 5187%(X100), DQS PI = 26
7345 12:26:46.378178 [0] MIN Duty = 4938%(X100), DQS PI = 48
7346 12:26:46.381277 [0] AVG Duty = 5062%(X100)
7347 12:26:46.381376
7348 12:26:46.385038 CH1 CLK Duty spec in!! Max-Min= 249%
7349 12:26:46.388280 [DutyScan_Calibration_Flow] ====Done====
7350 12:26:46.388404
7351 12:26:46.391324 [DutyScan_Calibration_Flow] k_type=1
7352 12:26:46.408472
7353 12:26:46.408648 ==DQS 0 ==
7354 12:26:46.411599 Final DQS duty delay cell = 0
7355 12:26:46.414757 [0] MAX Duty = 5062%(X100), DQS PI = 20
7356 12:26:46.418423 [0] MIN Duty = 4813%(X100), DQS PI = 50
7357 12:26:46.418532 [0] AVG Duty = 4937%(X100)
7358 12:26:46.421478
7359 12:26:46.421571 ==DQS 1 ==
7360 12:26:46.424662 Final DQS duty delay cell = 0
7361 12:26:46.428318 [0] MAX Duty = 5062%(X100), DQS PI = 56
7362 12:26:46.431463 [0] MIN Duty = 4938%(X100), DQS PI = 14
7363 12:26:46.434522 [0] AVG Duty = 5000%(X100)
7364 12:26:46.434618
7365 12:26:46.438239 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7366 12:26:46.438338
7367 12:26:46.441410 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7368 12:26:46.444513 [DutyScan_Calibration_Flow] ====Done====
7369 12:26:46.444610
7370 12:26:46.447750 [DutyScan_Calibration_Flow] k_type=3
7371 12:26:46.464698
7372 12:26:46.464854 ==DQM 0 ==
7373 12:26:46.468430 Final DQM duty delay cell = 0
7374 12:26:46.471601 [0] MAX Duty = 5187%(X100), DQS PI = 20
7375 12:26:46.474625 [0] MIN Duty = 4844%(X100), DQS PI = 50
7376 12:26:46.478431 [0] AVG Duty = 5015%(X100)
7377 12:26:46.478568
7378 12:26:46.478724 ==DQM 1 ==
7379 12:26:46.481641 Final DQM duty delay cell = 0
7380 12:26:46.484942 [0] MAX Duty = 5156%(X100), DQS PI = 10
7381 12:26:46.488675 [0] MIN Duty = 4875%(X100), DQS PI = 22
7382 12:26:46.492122 [0] AVG Duty = 5015%(X100)
7383 12:26:46.492225
7384 12:26:46.495102 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7385 12:26:46.495193
7386 12:26:46.498126 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7387 12:26:46.501230 [DutyScan_Calibration_Flow] ====Done====
7388 12:26:46.501326
7389 12:26:46.504426 [DutyScan_Calibration_Flow] k_type=2
7390 12:26:46.521840
7391 12:26:46.521991 ==DQ 0 ==
7392 12:26:46.525022 Final DQ duty delay cell = 0
7393 12:26:46.528828 [0] MAX Duty = 5156%(X100), DQS PI = 20
7394 12:26:46.531989 [0] MIN Duty = 4907%(X100), DQS PI = 54
7395 12:26:46.535137 [0] AVG Duty = 5031%(X100)
7396 12:26:46.535228
7397 12:26:46.535295 ==DQ 1 ==
7398 12:26:46.538300 Final DQ duty delay cell = 0
7399 12:26:46.541799 [0] MAX Duty = 5093%(X100), DQS PI = 6
7400 12:26:46.545038 [0] MIN Duty = 5031%(X100), DQS PI = 0
7401 12:26:46.545127 [0] AVG Duty = 5062%(X100)
7402 12:26:46.548023
7403 12:26:46.551973 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7404 12:26:46.552075
7405 12:26:46.555015 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7406 12:26:46.557975 [DutyScan_Calibration_Flow] ====Done====
7407 12:26:46.561429 nWR fixed to 30
7408 12:26:46.561556 [ModeRegInit_LP4] CH0 RK0
7409 12:26:46.564847 [ModeRegInit_LP4] CH0 RK1
7410 12:26:46.568146 [ModeRegInit_LP4] CH1 RK0
7411 12:26:46.571706 [ModeRegInit_LP4] CH1 RK1
7412 12:26:46.571804 match AC timing 5
7413 12:26:46.574706 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7414 12:26:46.581354 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7415 12:26:46.585044 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7416 12:26:46.588188 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7417 12:26:46.595177 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7418 12:26:46.595343 [MiockJmeterHQA]
7419 12:26:46.595439
7420 12:26:46.598346 [DramcMiockJmeter] u1RxGatingPI = 0
7421 12:26:46.601487 0 : 4253, 4026
7422 12:26:46.601591 4 : 4252, 4027
7423 12:26:46.601662 8 : 4252, 4027
7424 12:26:46.604457 12 : 4252, 4027
7425 12:26:46.604554 16 : 4252, 4027
7426 12:26:46.607736 20 : 4253, 4026
7427 12:26:46.607830 24 : 4255, 4029
7428 12:26:46.611507 28 : 4363, 4138
7429 12:26:46.611648 32 : 4252, 4027
7430 12:26:46.614758 36 : 4252, 4027
7431 12:26:46.614870 40 : 4253, 4027
7432 12:26:46.614965 44 : 4255, 4029
7433 12:26:46.617945 48 : 4253, 4027
7434 12:26:46.618042 52 : 4363, 4138
7435 12:26:46.621098 56 : 4363, 4137
7436 12:26:46.621199 60 : 4252, 4027
7437 12:26:46.625034 64 : 4252, 4027
7438 12:26:46.625142 68 : 4253, 4026
7439 12:26:46.628054 72 : 4253, 4026
7440 12:26:46.628161 76 : 4253, 4029
7441 12:26:46.628252 80 : 4361, 4137
7442 12:26:46.631154 84 : 4252, 4027
7443 12:26:46.631254 88 : 4250, 4026
7444 12:26:46.634868 92 : 4250, 4027
7445 12:26:46.634971 96 : 4252, 3306
7446 12:26:46.638063 100 : 4250, 0
7447 12:26:46.638159 104 : 4250, 0
7448 12:26:46.638231 108 : 4363, 0
7449 12:26:46.641251 112 : 4360, 0
7450 12:26:46.641349 116 : 4363, 0
7451 12:26:46.644261 120 : 4250, 0
7452 12:26:46.644358 124 : 4250, 0
7453 12:26:46.644438 128 : 4250, 0
7454 12:26:46.648159 132 : 4250, 0
7455 12:26:46.648264 136 : 4250, 0
7456 12:26:46.648336 140 : 4361, 0
7457 12:26:46.651284 144 : 4250, 0
7458 12:26:46.651407 148 : 4250, 0
7459 12:26:46.654473 152 : 4250, 0
7460 12:26:46.654566 156 : 4253, 0
7461 12:26:46.654654 160 : 4361, 0
7462 12:26:46.657739 164 : 4250, 0
7463 12:26:46.657838 168 : 4361, 0
7464 12:26:46.660960 172 : 4250, 0
7465 12:26:46.661102 176 : 4360, 0
7466 12:26:46.661209 180 : 4250, 0
7467 12:26:46.664706 184 : 4250, 0
7468 12:26:46.664849 188 : 4250, 0
7469 12:26:46.667651 192 : 4361, 0
7470 12:26:46.667775 196 : 4361, 0
7471 12:26:46.667879 200 : 4250, 0
7472 12:26:46.670728 204 : 4250, 0
7473 12:26:46.670853 208 : 4250, 0
7474 12:26:46.674284 212 : 4253, 95
7475 12:26:46.674417 216 : 4250, 3826
7476 12:26:46.674523 220 : 4250, 4026
7477 12:26:46.677646 224 : 4361, 4137
7478 12:26:46.677771 228 : 4250, 4026
7479 12:26:46.681090 232 : 4250, 4027
7480 12:26:46.681221 236 : 4360, 4138
7481 12:26:46.684149 240 : 4250, 4026
7482 12:26:46.684283 244 : 4250, 4027
7483 12:26:46.687720 248 : 4363, 4139
7484 12:26:46.687852 252 : 4250, 4027
7485 12:26:46.690727 256 : 4250, 4027
7486 12:26:46.690854 260 : 4250, 4027
7487 12:26:46.694235 264 : 4252, 4029
7488 12:26:46.694368 268 : 4250, 4027
7489 12:26:46.697255 272 : 4250, 4027
7490 12:26:46.697390 276 : 4363, 4137
7491 12:26:46.697496 280 : 4250, 4026
7492 12:26:46.700616 284 : 4250, 4027
7493 12:26:46.700744 288 : 4360, 4138
7494 12:26:46.704255 292 : 4250, 4027
7495 12:26:46.704386 296 : 4250, 4027
7496 12:26:46.707289 300 : 4363, 4139
7497 12:26:46.707422 304 : 4250, 4027
7498 12:26:46.711011 308 : 4250, 4027
7499 12:26:46.711143 312 : 4250, 4027
7500 12:26:46.714223 316 : 4253, 4029
7501 12:26:46.714344 320 : 4250, 4027
7502 12:26:46.717292 324 : 4250, 4027
7503 12:26:46.717414 328 : 4361, 4137
7504 12:26:46.721146 332 : 4250, 3114
7505 12:26:46.721283 336 : 4250, 93
7506 12:26:46.721389
7507 12:26:46.724259 MIOCK jitter meter ch=0
7508 12:26:46.724379
7509 12:26:46.727336 1T = (336-100) = 236 dly cells
7510 12:26:46.730510 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7511 12:26:46.730629 ==
7512 12:26:46.734238 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 12:26:46.740490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 12:26:46.740639 ==
7515 12:26:46.744333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 12:26:46.751167 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 12:26:46.754339 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 12:26:46.760723 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 12:26:46.768172 [CA 0] Center 44 (14~75) winsize 62
7520 12:26:46.771337 [CA 1] Center 44 (14~74) winsize 61
7521 12:26:46.775113 [CA 2] Center 39 (10~68) winsize 59
7522 12:26:46.778233 [CA 3] Center 39 (10~68) winsize 59
7523 12:26:46.781237 [CA 4] Center 37 (7~67) winsize 61
7524 12:26:46.785151 [CA 5] Center 37 (7~67) winsize 61
7525 12:26:46.785302
7526 12:26:46.788032 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 12:26:46.788200
7528 12:26:46.794873 [CATrainingPosCal] consider 1 rank data
7529 12:26:46.795042 u2DelayCellTimex100 = 275/100 ps
7530 12:26:46.801746 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7531 12:26:46.804781 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7532 12:26:46.807799 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7533 12:26:46.811521 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7534 12:26:46.814740 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7535 12:26:46.817854 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7536 12:26:46.817982
7537 12:26:46.821544 CA PerBit enable=1, Macro0, CA PI delay=37
7538 12:26:46.821670
7539 12:26:46.824768 [CBTSetCACLKResult] CA Dly = 37
7540 12:26:46.827939 CS Dly: 11 (0~42)
7541 12:26:46.830990 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 12:26:46.834102 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 12:26:46.834240 ==
7544 12:26:46.837923 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 12:26:46.844743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 12:26:46.844911 ==
7547 12:26:46.847909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 12:26:46.854400 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 12:26:46.857524 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 12:26:46.864348 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 12:26:46.871960 [CA 0] Center 44 (14~75) winsize 62
7552 12:26:46.875583 [CA 1] Center 44 (14~75) winsize 62
7553 12:26:46.878820 [CA 2] Center 40 (11~69) winsize 59
7554 12:26:46.881818 [CA 3] Center 39 (10~69) winsize 60
7555 12:26:46.885413 [CA 4] Center 38 (9~68) winsize 60
7556 12:26:46.888710 [CA 5] Center 37 (7~67) winsize 61
7557 12:26:46.888849
7558 12:26:46.891770 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 12:26:46.891893
7560 12:26:46.898391 [CATrainingPosCal] consider 2 rank data
7561 12:26:46.898549 u2DelayCellTimex100 = 275/100 ps
7562 12:26:46.905151 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7563 12:26:46.908293 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7564 12:26:46.912064 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7565 12:26:46.915139 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7566 12:26:46.918304 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7567 12:26:46.922004 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7568 12:26:46.922151
7569 12:26:46.925017 CA PerBit enable=1, Macro0, CA PI delay=37
7570 12:26:46.925140
7571 12:26:46.928760 [CBTSetCACLKResult] CA Dly = 37
7572 12:26:46.931796 CS Dly: 11 (0~43)
7573 12:26:46.934887 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 12:26:46.938539 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 12:26:46.938677
7576 12:26:46.941675 ----->DramcWriteLeveling(PI) begin...
7577 12:26:46.941801 ==
7578 12:26:46.945389 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 12:26:46.951649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 12:26:46.951804 ==
7581 12:26:46.954826 Write leveling (Byte 0): 29 => 29
7582 12:26:46.958470 Write leveling (Byte 1): 28 => 28
7583 12:26:46.958619 DramcWriteLeveling(PI) end<-----
7584 12:26:46.958725
7585 12:26:46.961391 ==
7586 12:26:46.961510 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 12:26:46.968255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 12:26:46.968421 ==
7589 12:26:46.971904 [Gating] SW mode calibration
7590 12:26:46.978253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 12:26:46.981904 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 12:26:46.988122 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 12:26:46.991667 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 12:26:46.994793 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 12:26:47.001860 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 12:26:47.004726 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 12:26:47.008301 1 4 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7598 12:26:47.015104 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
7599 12:26:47.018129 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 12:26:47.021740 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 12:26:47.028022 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 12:26:47.031835 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 12:26:47.035080 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 12:26:47.038436 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
7605 12:26:47.045250 1 5 20 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
7606 12:26:47.048326 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7607 12:26:47.051589 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 12:26:47.058452 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 12:26:47.061276 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 12:26:47.064989 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 12:26:47.071241 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 12:26:47.074945 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7613 12:26:47.078142 1 6 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7614 12:26:47.084959 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7615 12:26:47.088178 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 12:26:47.091216 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 12:26:47.097995 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 12:26:47.101135 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 12:26:47.104983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 12:26:47.111007 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 12:26:47.114608 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7622 12:26:47.118207 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:26:47.124267 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:26:47.128005 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:26:47.131205 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:26:47.137525 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:26:47.141158 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:26:47.144259 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:26:47.151231 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:26:47.154177 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 12:26:47.157363 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 12:26:47.164213 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 12:26:47.167156 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:26:47.171013 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:26:47.177188 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:26:47.180473 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:26:47.184241 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 12:26:47.187329 Total UI for P1: 0, mck2ui 16
7639 12:26:47.190506 best dqsien dly found for B0: ( 1, 9, 18)
7640 12:26:47.197367 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 12:26:47.200418 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 12:26:47.203994 Total UI for P1: 0, mck2ui 16
7643 12:26:47.207161 best dqsien dly found for B1: ( 1, 9, 22)
7644 12:26:47.210406 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7645 12:26:47.214043 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7646 12:26:47.214176
7647 12:26:47.217249 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7648 12:26:47.220956 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7649 12:26:47.223832 [Gating] SW calibration Done
7650 12:26:47.223961 ==
7651 12:26:47.227670 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 12:26:47.230638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 12:26:47.230797 ==
7654 12:26:47.233897 RX Vref Scan: 0
7655 12:26:47.234018
7656 12:26:47.237462 RX Vref 0 -> 0, step: 1
7657 12:26:47.237593
7658 12:26:47.237696 RX Delay 0 -> 252, step: 8
7659 12:26:47.243695 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7660 12:26:47.247507 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7661 12:26:47.250671 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7662 12:26:47.253732 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7663 12:26:47.257531 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7664 12:26:47.263983 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7665 12:26:47.267110 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7666 12:26:47.270741 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7667 12:26:47.273762 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7668 12:26:47.276913 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7669 12:26:47.284006 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7670 12:26:47.287173 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7671 12:26:47.290347 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7672 12:26:47.293658 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7673 12:26:47.297219 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7674 12:26:47.304023 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7675 12:26:47.304188 ==
7676 12:26:47.306936 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 12:26:47.310162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 12:26:47.310295 ==
7679 12:26:47.310400 DQS Delay:
7680 12:26:47.313935 DQS0 = 0, DQS1 = 0
7681 12:26:47.314063 DQM Delay:
7682 12:26:47.317074 DQM0 = 132, DQM1 = 124
7683 12:26:47.317207 DQ Delay:
7684 12:26:47.320360 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7685 12:26:47.323478 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7686 12:26:47.327100 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7687 12:26:47.330026 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7688 12:26:47.333570
7689 12:26:47.333681
7690 12:26:47.333753 ==
7691 12:26:47.337270 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 12:26:47.340377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 12:26:47.340482 ==
7694 12:26:47.340554
7695 12:26:47.340617
7696 12:26:47.343319 TX Vref Scan disable
7697 12:26:47.343433 == TX Byte 0 ==
7698 12:26:47.350089 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7699 12:26:47.353730 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7700 12:26:47.353845 == TX Byte 1 ==
7701 12:26:47.360048 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7702 12:26:47.363195 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7703 12:26:47.363363 ==
7704 12:26:47.367193 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 12:26:47.370091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 12:26:47.370227 ==
7707 12:26:47.384633
7708 12:26:47.387725 TX Vref early break, caculate TX vref
7709 12:26:47.391367 TX Vref=16, minBit 1, minWin=21, winSum=358
7710 12:26:47.394748 TX Vref=18, minBit 7, minWin=21, winSum=368
7711 12:26:47.397987 TX Vref=20, minBit 7, minWin=22, winSum=381
7712 12:26:47.401061 TX Vref=22, minBit 1, minWin=23, winSum=389
7713 12:26:47.404300 TX Vref=24, minBit 1, minWin=23, winSum=395
7714 12:26:47.411017 TX Vref=26, minBit 7, minWin=23, winSum=409
7715 12:26:47.414154 TX Vref=28, minBit 1, minWin=23, winSum=420
7716 12:26:47.417545 TX Vref=30, minBit 7, minWin=25, winSum=419
7717 12:26:47.420759 TX Vref=32, minBit 4, minWin=24, winSum=412
7718 12:26:47.424532 TX Vref=34, minBit 0, minWin=24, winSum=403
7719 12:26:47.430814 TX Vref=36, minBit 0, minWin=24, winSum=388
7720 12:26:47.433936 [TxChooseVref] Worse bit 7, Min win 25, Win sum 419, Final Vref 30
7721 12:26:47.434054
7722 12:26:47.437415 Final TX Range 0 Vref 30
7723 12:26:47.437511
7724 12:26:47.437582 ==
7725 12:26:47.440433 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 12:26:47.443953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 12:26:47.444097 ==
7728 12:26:47.447022
7729 12:26:47.447120
7730 12:26:47.447189 TX Vref Scan disable
7731 12:26:47.453710 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7732 12:26:47.453826 == TX Byte 0 ==
7733 12:26:47.457421 u2DelayCellOfst[0]=17 cells (5 PI)
7734 12:26:47.460550 u2DelayCellOfst[1]=21 cells (6 PI)
7735 12:26:47.463755 u2DelayCellOfst[2]=10 cells (3 PI)
7736 12:26:47.466894 u2DelayCellOfst[3]=14 cells (4 PI)
7737 12:26:47.470793 u2DelayCellOfst[4]=10 cells (3 PI)
7738 12:26:47.473977 u2DelayCellOfst[5]=0 cells (0 PI)
7739 12:26:47.477126 u2DelayCellOfst[6]=21 cells (6 PI)
7740 12:26:47.480175 u2DelayCellOfst[7]=21 cells (6 PI)
7741 12:26:47.483722 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7742 12:26:47.486862 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7743 12:26:47.490052 == TX Byte 1 ==
7744 12:26:47.493992 u2DelayCellOfst[8]=0 cells (0 PI)
7745 12:26:47.497036 u2DelayCellOfst[9]=0 cells (0 PI)
7746 12:26:47.500194 u2DelayCellOfst[10]=7 cells (2 PI)
7747 12:26:47.503319 u2DelayCellOfst[11]=0 cells (0 PI)
7748 12:26:47.507262 u2DelayCellOfst[12]=14 cells (4 PI)
7749 12:26:47.507414 u2DelayCellOfst[13]=14 cells (4 PI)
7750 12:26:47.510172 u2DelayCellOfst[14]=17 cells (5 PI)
7751 12:26:47.513873 u2DelayCellOfst[15]=10 cells (3 PI)
7752 12:26:47.520008 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7753 12:26:47.523091 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7754 12:26:47.523227 DramC Write-DBI on
7755 12:26:47.526840 ==
7756 12:26:47.530005 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 12:26:47.533180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 12:26:47.533287 ==
7759 12:26:47.533366
7760 12:26:47.533432
7761 12:26:47.536425 TX Vref Scan disable
7762 12:26:47.536516 == TX Byte 0 ==
7763 12:26:47.543150 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
7764 12:26:47.543317 == TX Byte 1 ==
7765 12:26:47.546718 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7766 12:26:47.549798 DramC Write-DBI off
7767 12:26:47.549906
7768 12:26:47.549976 [DATLAT]
7769 12:26:47.553458 Freq=1600, CH0 RK0
7770 12:26:47.553567
7771 12:26:47.553637 DATLAT Default: 0xf
7772 12:26:47.556556 0, 0xFFFF, sum = 0
7773 12:26:47.556648 1, 0xFFFF, sum = 0
7774 12:26:47.559701 2, 0xFFFF, sum = 0
7775 12:26:47.559799 3, 0xFFFF, sum = 0
7776 12:26:47.563319 4, 0xFFFF, sum = 0
7777 12:26:47.563436 5, 0xFFFF, sum = 0
7778 12:26:47.566438 6, 0xFFFF, sum = 0
7779 12:26:47.569638 7, 0xFFFF, sum = 0
7780 12:26:47.569739 8, 0xFFFF, sum = 0
7781 12:26:47.573324 9, 0xFFFF, sum = 0
7782 12:26:47.573420 10, 0xFFFF, sum = 0
7783 12:26:47.576443 11, 0xFFFF, sum = 0
7784 12:26:47.576537 12, 0xFFFF, sum = 0
7785 12:26:47.579555 13, 0xFFFF, sum = 0
7786 12:26:47.579647 14, 0x0, sum = 1
7787 12:26:47.583227 15, 0x0, sum = 2
7788 12:26:47.583369 16, 0x0, sum = 3
7789 12:26:47.586210 17, 0x0, sum = 4
7790 12:26:47.586301 best_step = 15
7791 12:26:47.586370
7792 12:26:47.586434 ==
7793 12:26:47.589877 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 12:26:47.592964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 12:26:47.593059 ==
7796 12:26:47.596165 RX Vref Scan: 1
7797 12:26:47.596277
7798 12:26:47.599315 Set Vref Range= 24 -> 127
7799 12:26:47.599444
7800 12:26:47.599542 RX Vref 24 -> 127, step: 1
7801 12:26:47.602640
7802 12:26:47.602728 RX Delay 11 -> 252, step: 4
7803 12:26:47.602796
7804 12:26:47.606463 Set Vref, RX VrefLevel [Byte0]: 24
7805 12:26:47.609581 [Byte1]: 24
7806 12:26:47.613353
7807 12:26:47.613449 Set Vref, RX VrefLevel [Byte0]: 25
7808 12:26:47.616372 [Byte1]: 25
7809 12:26:47.620688
7810 12:26:47.620793 Set Vref, RX VrefLevel [Byte0]: 26
7811 12:26:47.623653 [Byte1]: 26
7812 12:26:47.628109
7813 12:26:47.628241 Set Vref, RX VrefLevel [Byte0]: 27
7814 12:26:47.631956 [Byte1]: 27
7815 12:26:47.635788
7816 12:26:47.635895 Set Vref, RX VrefLevel [Byte0]: 28
7817 12:26:47.639534 [Byte1]: 28
7818 12:26:47.643313
7819 12:26:47.643455 Set Vref, RX VrefLevel [Byte0]: 29
7820 12:26:47.646958 [Byte1]: 29
7821 12:26:47.651281
7822 12:26:47.651399 Set Vref, RX VrefLevel [Byte0]: 30
7823 12:26:47.654834 [Byte1]: 30
7824 12:26:47.658933
7825 12:26:47.659033 Set Vref, RX VrefLevel [Byte0]: 31
7826 12:26:47.661813 [Byte1]: 31
7827 12:26:47.666040
7828 12:26:47.666187 Set Vref, RX VrefLevel [Byte0]: 32
7829 12:26:47.669782 [Byte1]: 32
7830 12:26:47.674125
7831 12:26:47.674257 Set Vref, RX VrefLevel [Byte0]: 33
7832 12:26:47.677327 [Byte1]: 33
7833 12:26:47.681783
7834 12:26:47.681875 Set Vref, RX VrefLevel [Byte0]: 34
7835 12:26:47.684976 [Byte1]: 34
7836 12:26:47.689458
7837 12:26:47.689554 Set Vref, RX VrefLevel [Byte0]: 35
7838 12:26:47.692462 [Byte1]: 35
7839 12:26:47.697152
7840 12:26:47.697255 Set Vref, RX VrefLevel [Byte0]: 36
7841 12:26:47.700087 [Byte1]: 36
7842 12:26:47.704632
7843 12:26:47.704735 Set Vref, RX VrefLevel [Byte0]: 37
7844 12:26:47.707821 [Byte1]: 37
7845 12:26:47.712067
7846 12:26:47.712162 Set Vref, RX VrefLevel [Byte0]: 38
7847 12:26:47.715183 [Byte1]: 38
7848 12:26:47.719531
7849 12:26:47.719658 Set Vref, RX VrefLevel [Byte0]: 39
7850 12:26:47.723203 [Byte1]: 39
7851 12:26:47.727420
7852 12:26:47.727517 Set Vref, RX VrefLevel [Byte0]: 40
7853 12:26:47.730567 [Byte1]: 40
7854 12:26:47.735158
7855 12:26:47.735277 Set Vref, RX VrefLevel [Byte0]: 41
7856 12:26:47.738186 [Byte1]: 41
7857 12:26:47.742656
7858 12:26:47.742746 Set Vref, RX VrefLevel [Byte0]: 42
7859 12:26:47.745778 [Byte1]: 42
7860 12:26:47.750139
7861 12:26:47.750258 Set Vref, RX VrefLevel [Byte0]: 43
7862 12:26:47.753613 [Byte1]: 43
7863 12:26:47.757598
7864 12:26:47.757693 Set Vref, RX VrefLevel [Byte0]: 44
7865 12:26:47.761026 [Byte1]: 44
7866 12:26:47.765183
7867 12:26:47.765300 Set Vref, RX VrefLevel [Byte0]: 45
7868 12:26:47.768870 [Byte1]: 45
7869 12:26:47.773032
7870 12:26:47.773133 Set Vref, RX VrefLevel [Byte0]: 46
7871 12:26:47.776067 [Byte1]: 46
7872 12:26:47.780452
7873 12:26:47.780553 Set Vref, RX VrefLevel [Byte0]: 47
7874 12:26:47.783622 [Byte1]: 47
7875 12:26:47.788072
7876 12:26:47.788167 Set Vref, RX VrefLevel [Byte0]: 48
7877 12:26:47.791248 [Byte1]: 48
7878 12:26:47.796037
7879 12:26:47.796132 Set Vref, RX VrefLevel [Byte0]: 49
7880 12:26:47.799188 [Byte1]: 49
7881 12:26:47.803485
7882 12:26:47.803580 Set Vref, RX VrefLevel [Byte0]: 50
7883 12:26:47.806809 [Byte1]: 50
7884 12:26:47.811105
7885 12:26:47.811197 Set Vref, RX VrefLevel [Byte0]: 51
7886 12:26:47.814239 [Byte1]: 51
7887 12:26:47.818665
7888 12:26:47.818760 Set Vref, RX VrefLevel [Byte0]: 52
7889 12:26:47.821823 [Byte1]: 52
7890 12:26:47.826144
7891 12:26:47.826240 Set Vref, RX VrefLevel [Byte0]: 53
7892 12:26:47.829358 [Byte1]: 53
7893 12:26:47.833556
7894 12:26:47.833652 Set Vref, RX VrefLevel [Byte0]: 54
7895 12:26:47.837347 [Byte1]: 54
7896 12:26:47.841424
7897 12:26:47.841521 Set Vref, RX VrefLevel [Byte0]: 55
7898 12:26:47.845101 [Byte1]: 55
7899 12:26:47.848908
7900 12:26:47.849006 Set Vref, RX VrefLevel [Byte0]: 56
7901 12:26:47.852547 [Byte1]: 56
7902 12:26:47.857047
7903 12:26:47.857153 Set Vref, RX VrefLevel [Byte0]: 57
7904 12:26:47.860304 [Byte1]: 57
7905 12:26:47.864373
7906 12:26:47.864519 Set Vref, RX VrefLevel [Byte0]: 58
7907 12:26:47.867369 [Byte1]: 58
7908 12:26:47.872130
7909 12:26:47.872244 Set Vref, RX VrefLevel [Byte0]: 59
7910 12:26:47.875183 [Byte1]: 59
7911 12:26:47.879614
7912 12:26:47.879775 Set Vref, RX VrefLevel [Byte0]: 60
7913 12:26:47.882675 [Byte1]: 60
7914 12:26:47.887068
7915 12:26:47.887189 Set Vref, RX VrefLevel [Byte0]: 61
7916 12:26:47.890808 [Byte1]: 61
7917 12:26:47.894595
7918 12:26:47.894685 Set Vref, RX VrefLevel [Byte0]: 62
7919 12:26:47.897761 [Byte1]: 62
7920 12:26:47.902636
7921 12:26:47.902755 Set Vref, RX VrefLevel [Byte0]: 63
7922 12:26:47.905759 [Byte1]: 63
7923 12:26:47.910107
7924 12:26:47.910222 Set Vref, RX VrefLevel [Byte0]: 64
7925 12:26:47.913250 [Byte1]: 64
7926 12:26:47.917444
7927 12:26:47.917566 Set Vref, RX VrefLevel [Byte0]: 65
7928 12:26:47.920710 [Byte1]: 65
7929 12:26:47.925097
7930 12:26:47.928337 Set Vref, RX VrefLevel [Byte0]: 66
7931 12:26:47.928428 [Byte1]: 66
7932 12:26:47.932620
7933 12:26:47.932709 Set Vref, RX VrefLevel [Byte0]: 67
7934 12:26:47.936241 [Byte1]: 67
7935 12:26:47.940681
7936 12:26:47.940776 Set Vref, RX VrefLevel [Byte0]: 68
7937 12:26:47.943816 [Byte1]: 68
7938 12:26:47.948318
7939 12:26:47.948412 Set Vref, RX VrefLevel [Byte0]: 69
7940 12:26:47.951508 [Byte1]: 69
7941 12:26:47.956006
7942 12:26:47.956122 Set Vref, RX VrefLevel [Byte0]: 70
7943 12:26:47.959105 [Byte1]: 70
7944 12:26:47.963599
7945 12:26:47.963732 Set Vref, RX VrefLevel [Byte0]: 71
7946 12:26:47.966773 [Byte1]: 71
7947 12:26:47.971120
7948 12:26:47.971258 Set Vref, RX VrefLevel [Byte0]: 72
7949 12:26:47.974262 [Byte1]: 72
7950 12:26:47.978360
7951 12:26:47.978474 Set Vref, RX VrefLevel [Byte0]: 73
7952 12:26:47.981938 [Byte1]: 73
7953 12:26:47.986302
7954 12:26:47.986483 Set Vref, RX VrefLevel [Byte0]: 74
7955 12:26:47.989184 [Byte1]: 74
7956 12:26:47.994040
7957 12:26:47.994204 Set Vref, RX VrefLevel [Byte0]: 75
7958 12:26:47.997451 [Byte1]: 75
7959 12:26:48.001003
7960 12:26:48.001149 Set Vref, RX VrefLevel [Byte0]: 76
7961 12:26:48.004732 [Byte1]: 76
7962 12:26:48.009170
7963 12:26:48.009309 Final RX Vref Byte 0 = 55 to rank0
7964 12:26:48.012391 Final RX Vref Byte 1 = 61 to rank0
7965 12:26:48.015550 Final RX Vref Byte 0 = 55 to rank1
7966 12:26:48.018776 Final RX Vref Byte 1 = 61 to rank1==
7967 12:26:48.021898 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 12:26:48.029003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 12:26:48.029131 ==
7970 12:26:48.029207 DQS Delay:
7971 12:26:48.032177 DQS0 = 0, DQS1 = 0
7972 12:26:48.032256 DQM Delay:
7973 12:26:48.032320 DQM0 = 129, DQM1 = 121
7974 12:26:48.035483 DQ Delay:
7975 12:26:48.038739 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7976 12:26:48.042269 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7977 12:26:48.045580 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7978 12:26:48.048593 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7979 12:26:48.048686
7980 12:26:48.048750
7981 12:26:48.048814
7982 12:26:48.051840 [DramC_TX_OE_Calibration] TA2
7983 12:26:48.055078 Original DQ_B0 (3 6) =30, OEN = 27
7984 12:26:48.058856 Original DQ_B1 (3 6) =30, OEN = 27
7985 12:26:48.061998 24, 0x0, End_B0=24 End_B1=24
7986 12:26:48.062080 25, 0x0, End_B0=25 End_B1=25
7987 12:26:48.065367 26, 0x0, End_B0=26 End_B1=26
7988 12:26:48.068532 27, 0x0, End_B0=27 End_B1=27
7989 12:26:48.071686 28, 0x0, End_B0=28 End_B1=28
7990 12:26:48.074994 29, 0x0, End_B0=29 End_B1=29
7991 12:26:48.075070 30, 0x0, End_B0=30 End_B1=30
7992 12:26:48.078852 31, 0x4141, End_B0=30 End_B1=30
7993 12:26:48.081879 Byte0 end_step=30 best_step=27
7994 12:26:48.085241 Byte1 end_step=30 best_step=27
7995 12:26:48.088691 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 12:26:48.091687 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 12:26:48.091779
7998 12:26:48.091846
7999 12:26:48.098328 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8000 12:26:48.101931 CH0 RK0: MR19=303, MR18=1206
8001 12:26:48.108575 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
8002 12:26:48.108726
8003 12:26:48.111725 ----->DramcWriteLeveling(PI) begin...
8004 12:26:48.111826 ==
8005 12:26:48.114848 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 12:26:48.118516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 12:26:48.118643 ==
8008 12:26:48.121777 Write leveling (Byte 0): 33 => 33
8009 12:26:48.125052 Write leveling (Byte 1): 26 => 26
8010 12:26:48.128668 DramcWriteLeveling(PI) end<-----
8011 12:26:48.128752
8012 12:26:48.128818 ==
8013 12:26:48.131796 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 12:26:48.135066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 12:26:48.135143 ==
8016 12:26:48.138182 [Gating] SW mode calibration
8017 12:26:48.144769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 12:26:48.151346 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 12:26:48.154705 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:26:48.158423 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 12:26:48.164875 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 12:26:48.167953 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8023 12:26:48.171157 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8024 12:26:48.178276 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8025 12:26:48.181387 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 12:26:48.184508 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 12:26:48.191227 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 12:26:48.194828 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 12:26:48.197810 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8030 12:26:48.204891 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8031 12:26:48.208120 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8032 12:26:48.211009 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8033 12:26:48.217735 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8034 12:26:48.221378 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 12:26:48.224338 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 12:26:48.231243 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 12:26:48.234457 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8038 12:26:48.237692 1 6 12 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
8039 12:26:48.244651 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8040 12:26:48.247748 1 6 20 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8041 12:26:48.250761 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 12:26:48.257826 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:26:48.260789 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 12:26:48.264658 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 12:26:48.270925 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 12:26:48.274658 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 12:26:48.277910 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8048 12:26:48.284208 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 12:26:48.287996 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:26:48.291048 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:26:48.297373 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:26:48.301205 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:26:48.304337 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:26:48.307710 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:26:48.314095 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:26:48.317736 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:26:48.320868 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:26:48.327385 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:26:48.330841 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:26:48.334037 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:26:48.341287 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 12:26:48.344388 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 12:26:48.347551 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8064 12:26:48.350628 Total UI for P1: 0, mck2ui 16
8065 12:26:48.353838 best dqsien dly found for B0: ( 1, 9, 10)
8066 12:26:48.360605 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 12:26:48.364347 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 12:26:48.367752 Total UI for P1: 0, mck2ui 16
8069 12:26:48.370798 best dqsien dly found for B1: ( 1, 9, 20)
8070 12:26:48.373831 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8071 12:26:48.377627 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8072 12:26:48.377715
8073 12:26:48.380923 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8074 12:26:48.384107 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8075 12:26:48.387209 [Gating] SW calibration Done
8076 12:26:48.387333 ==
8077 12:26:48.390311 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 12:26:48.397210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 12:26:48.397299 ==
8080 12:26:48.397367 RX Vref Scan: 0
8081 12:26:48.397430
8082 12:26:48.400437 RX Vref 0 -> 0, step: 1
8083 12:26:48.400545
8084 12:26:48.403627 RX Delay 0 -> 252, step: 8
8085 12:26:48.406865 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8086 12:26:48.410076 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8087 12:26:48.413708 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8088 12:26:48.416699 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8089 12:26:48.423300 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8090 12:26:48.427051 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8091 12:26:48.429995 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8092 12:26:48.433179 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8093 12:26:48.436580 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8094 12:26:48.443227 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8095 12:26:48.446452 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8096 12:26:48.450213 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8097 12:26:48.453411 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8098 12:26:48.460101 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8099 12:26:48.463099 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8100 12:26:48.466892 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8101 12:26:48.467018 ==
8102 12:26:48.470109 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 12:26:48.473364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 12:26:48.473473 ==
8105 12:26:48.476425 DQS Delay:
8106 12:26:48.476536 DQS0 = 0, DQS1 = 0
8107 12:26:48.479672 DQM Delay:
8108 12:26:48.479748 DQM0 = 131, DQM1 = 124
8109 12:26:48.479849 DQ Delay:
8110 12:26:48.486694 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8111 12:26:48.489848 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8112 12:26:48.493032 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8113 12:26:48.496086 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8114 12:26:48.496167
8115 12:26:48.496246
8116 12:26:48.496321 ==
8117 12:26:48.499961 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 12:26:48.503123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 12:26:48.503205 ==
8120 12:26:48.503270
8121 12:26:48.503330
8122 12:26:48.506309 TX Vref Scan disable
8123 12:26:48.509504 == TX Byte 0 ==
8124 12:26:48.513400 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8125 12:26:48.516537 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8126 12:26:48.519669 == TX Byte 1 ==
8127 12:26:48.522849 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8128 12:26:48.526319 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8129 12:26:48.526403 ==
8130 12:26:48.529246 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:26:48.533053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:26:48.536069 ==
8133 12:26:48.549019
8134 12:26:48.552655 TX Vref early break, caculate TX vref
8135 12:26:48.555828 TX Vref=16, minBit 9, minWin=21, winSum=365
8136 12:26:48.559505 TX Vref=18, minBit 9, minWin=22, winSum=374
8137 12:26:48.562723 TX Vref=20, minBit 0, minWin=23, winSum=386
8138 12:26:48.565684 TX Vref=22, minBit 0, minWin=24, winSum=397
8139 12:26:48.569300 TX Vref=24, minBit 4, minWin=24, winSum=401
8140 12:26:48.575762 TX Vref=26, minBit 4, minWin=24, winSum=410
8141 12:26:48.579366 TX Vref=28, minBit 0, minWin=25, winSum=417
8142 12:26:48.582432 TX Vref=30, minBit 0, minWin=25, winSum=416
8143 12:26:48.585773 TX Vref=32, minBit 2, minWin=24, winSum=405
8144 12:26:48.588959 TX Vref=34, minBit 0, minWin=24, winSum=399
8145 12:26:48.592207 TX Vref=36, minBit 4, minWin=23, winSum=390
8146 12:26:48.599169 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8147 12:26:48.599307
8148 12:26:48.602363 Final TX Range 0 Vref 28
8149 12:26:48.602479
8150 12:26:48.602578 ==
8151 12:26:48.605577 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 12:26:48.608915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 12:26:48.609033 ==
8154 12:26:48.609132
8155 12:26:48.609226
8156 12:26:48.612586 TX Vref Scan disable
8157 12:26:48.618805 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8158 12:26:48.618932 == TX Byte 0 ==
8159 12:26:48.622435 u2DelayCellOfst[0]=14 cells (4 PI)
8160 12:26:48.625612 u2DelayCellOfst[1]=17 cells (5 PI)
8161 12:26:48.628762 u2DelayCellOfst[2]=10 cells (3 PI)
8162 12:26:48.632510 u2DelayCellOfst[3]=10 cells (3 PI)
8163 12:26:48.635473 u2DelayCellOfst[4]=10 cells (3 PI)
8164 12:26:48.639234 u2DelayCellOfst[5]=0 cells (0 PI)
8165 12:26:48.642222 u2DelayCellOfst[6]=17 cells (5 PI)
8166 12:26:48.645811 u2DelayCellOfst[7]=17 cells (5 PI)
8167 12:26:48.648800 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8168 12:26:48.652436 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8169 12:26:48.655593 == TX Byte 1 ==
8170 12:26:48.658857 u2DelayCellOfst[8]=0 cells (0 PI)
8171 12:26:48.662030 u2DelayCellOfst[9]=0 cells (0 PI)
8172 12:26:48.662154 u2DelayCellOfst[10]=3 cells (1 PI)
8173 12:26:48.665204 u2DelayCellOfst[11]=0 cells (0 PI)
8174 12:26:48.668973 u2DelayCellOfst[12]=10 cells (3 PI)
8175 12:26:48.671945 u2DelayCellOfst[13]=10 cells (3 PI)
8176 12:26:48.675688 u2DelayCellOfst[14]=14 cells (4 PI)
8177 12:26:48.678835 u2DelayCellOfst[15]=10 cells (3 PI)
8178 12:26:48.685094 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8179 12:26:48.688919 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8180 12:26:48.689046 DramC Write-DBI on
8181 12:26:48.689145 ==
8182 12:26:48.692164 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 12:26:48.698544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 12:26:48.698656 ==
8185 12:26:48.698752
8186 12:26:48.698843
8187 12:26:48.698932 TX Vref Scan disable
8188 12:26:48.702946 == TX Byte 0 ==
8189 12:26:48.706105 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8190 12:26:48.709161 == TX Byte 1 ==
8191 12:26:48.712424 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8192 12:26:48.716144 DramC Write-DBI off
8193 12:26:48.716256
8194 12:26:48.716325 [DATLAT]
8195 12:26:48.716390 Freq=1600, CH0 RK1
8196 12:26:48.716452
8197 12:26:48.719363 DATLAT Default: 0xf
8198 12:26:48.719490 0, 0xFFFF, sum = 0
8199 12:26:48.722508 1, 0xFFFF, sum = 0
8200 12:26:48.725644 2, 0xFFFF, sum = 0
8201 12:26:48.725717 3, 0xFFFF, sum = 0
8202 12:26:48.728858 4, 0xFFFF, sum = 0
8203 12:26:48.728930 5, 0xFFFF, sum = 0
8204 12:26:48.732583 6, 0xFFFF, sum = 0
8205 12:26:48.732672 7, 0xFFFF, sum = 0
8206 12:26:48.735665 8, 0xFFFF, sum = 0
8207 12:26:48.735755 9, 0xFFFF, sum = 0
8208 12:26:48.739276 10, 0xFFFF, sum = 0
8209 12:26:48.739373 11, 0xFFFF, sum = 0
8210 12:26:48.742250 12, 0xFFFF, sum = 0
8211 12:26:48.742332 13, 0xFFFF, sum = 0
8212 12:26:48.746070 14, 0x0, sum = 1
8213 12:26:48.746168 15, 0x0, sum = 2
8214 12:26:48.749079 16, 0x0, sum = 3
8215 12:26:48.749169 17, 0x0, sum = 4
8216 12:26:48.752575 best_step = 15
8217 12:26:48.752669
8218 12:26:48.752740 ==
8219 12:26:48.755645 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 12:26:48.759458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 12:26:48.759602 ==
8222 12:26:48.762399 RX Vref Scan: 0
8223 12:26:48.762585
8224 12:26:48.762715 RX Vref 0 -> 0, step: 1
8225 12:26:48.762859
8226 12:26:48.765618 RX Delay 11 -> 252, step: 4
8227 12:26:48.768899 iDelay=191, Bit 0, Center 128 (75 ~ 182) 108
8228 12:26:48.776216 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8229 12:26:48.779426 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8230 12:26:48.782493 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8231 12:26:48.785867 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8232 12:26:48.789156 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8233 12:26:48.795896 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8234 12:26:48.799172 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8235 12:26:48.802503 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8236 12:26:48.805946 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8237 12:26:48.809306 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8238 12:26:48.815946 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8239 12:26:48.819143 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8240 12:26:48.822459 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8241 12:26:48.825845 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8242 12:26:48.829208 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8243 12:26:48.831926 ==
8244 12:26:48.835754 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 12:26:48.839049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 12:26:48.839154 ==
8247 12:26:48.839249 DQS Delay:
8248 12:26:48.841901 DQS0 = 0, DQS1 = 0
8249 12:26:48.841989 DQM Delay:
8250 12:26:48.845187 DQM0 = 127, DQM1 = 122
8251 12:26:48.845275 DQ Delay:
8252 12:26:48.848894 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8253 12:26:48.851992 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8254 12:26:48.855183 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8255 12:26:48.859102 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8256 12:26:48.859208
8257 12:26:48.859318
8258 12:26:48.859432
8259 12:26:48.862398 [DramC_TX_OE_Calibration] TA2
8260 12:26:48.865470 Original DQ_B0 (3 6) =30, OEN = 27
8261 12:26:48.868670 Original DQ_B1 (3 6) =30, OEN = 27
8262 12:26:48.871856 24, 0x0, End_B0=24 End_B1=24
8263 12:26:48.875484 25, 0x0, End_B0=25 End_B1=25
8264 12:26:48.875587 26, 0x0, End_B0=26 End_B1=26
8265 12:26:48.878822 27, 0x0, End_B0=27 End_B1=27
8266 12:26:48.882082 28, 0x0, End_B0=28 End_B1=28
8267 12:26:48.885423 29, 0x0, End_B0=29 End_B1=29
8268 12:26:48.888859 30, 0x0, End_B0=30 End_B1=30
8269 12:26:48.888997 31, 0x4141, End_B0=30 End_B1=30
8270 12:26:48.892239 Byte0 end_step=30 best_step=27
8271 12:26:48.895670 Byte1 end_step=30 best_step=27
8272 12:26:48.898893 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 12:26:48.902196 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 12:26:48.902294
8275 12:26:48.902384
8276 12:26:48.908955 [DQSOSCAuto] RK1, (LSB)MR18= 0x1609, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
8277 12:26:48.912257 CH0 RK1: MR19=303, MR18=1609
8278 12:26:48.918829 CH0_RK1: MR19=0x303, MR18=0x1609, DQSOSC=398, MR23=63, INC=23, DEC=15
8279 12:26:48.922210 [RxdqsGatingPostProcess] freq 1600
8280 12:26:48.928909 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 12:26:48.929016 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 12:26:48.932211 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 12:26:48.935275 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 12:26:48.938549 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 12:26:48.941849 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 12:26:48.945227 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 12:26:48.948469 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 12:26:48.951725 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 12:26:48.954765 Pre-setting of DQS Precalculation
8290 12:26:48.958764 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 12:26:48.958870 ==
8292 12:26:48.962011 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 12:26:48.968270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 12:26:48.968384 ==
8295 12:26:48.971469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 12:26:48.978495 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 12:26:48.981707 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 12:26:48.988028 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 12:26:48.995879 [CA 0] Center 43 (14~72) winsize 59
8300 12:26:48.999274 [CA 1] Center 43 (14~72) winsize 59
8301 12:26:49.002488 [CA 2] Center 38 (9~67) winsize 59
8302 12:26:49.005784 [CA 3] Center 37 (8~66) winsize 59
8303 12:26:49.009222 [CA 4] Center 38 (9~68) winsize 60
8304 12:26:49.012488 [CA 5] Center 37 (8~66) winsize 59
8305 12:26:49.012574
8306 12:26:49.015797 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 12:26:49.015883
8308 12:26:49.019107 [CATrainingPosCal] consider 1 rank data
8309 12:26:49.022414 u2DelayCellTimex100 = 275/100 ps
8310 12:26:49.028498 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8311 12:26:49.031834 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8312 12:26:49.035185 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8313 12:26:49.038581 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8314 12:26:49.041813 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8315 12:26:49.045136 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8316 12:26:49.045219
8317 12:26:49.048631 CA PerBit enable=1, Macro0, CA PI delay=37
8318 12:26:49.048714
8319 12:26:49.051935 [CBTSetCACLKResult] CA Dly = 37
8320 12:26:49.055254 CS Dly: 9 (0~40)
8321 12:26:49.058426 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 12:26:49.062063 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 12:26:49.062146 ==
8324 12:26:49.065214 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 12:26:49.068997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 12:26:49.071615 ==
8327 12:26:49.075390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 12:26:49.078383 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 12:26:49.085314 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 12:26:49.088552 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 12:26:49.098971 [CA 0] Center 43 (14~72) winsize 59
8332 12:26:49.102257 [CA 1] Center 43 (14~72) winsize 59
8333 12:26:49.105658 [CA 2] Center 38 (9~67) winsize 59
8334 12:26:49.108827 [CA 3] Center 37 (8~67) winsize 60
8335 12:26:49.112125 [CA 4] Center 38 (8~68) winsize 61
8336 12:26:49.115499 [CA 5] Center 36 (7~66) winsize 60
8337 12:26:49.115612
8338 12:26:49.118791 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8339 12:26:49.118875
8340 12:26:49.125391 [CATrainingPosCal] consider 2 rank data
8341 12:26:49.125503 u2DelayCellTimex100 = 275/100 ps
8342 12:26:49.132108 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8343 12:26:49.135268 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8344 12:26:49.138491 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 12:26:49.141884 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8346 12:26:49.145246 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8347 12:26:49.148430 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8348 12:26:49.148522
8349 12:26:49.151876 CA PerBit enable=1, Macro0, CA PI delay=37
8350 12:26:49.151987
8351 12:26:49.155174 [CBTSetCACLKResult] CA Dly = 37
8352 12:26:49.158610 CS Dly: 10 (0~43)
8353 12:26:49.161879 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 12:26:49.165073 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 12:26:49.165156
8356 12:26:49.168323 ----->DramcWriteLeveling(PI) begin...
8357 12:26:49.168409 ==
8358 12:26:49.171919 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 12:26:49.178244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 12:26:49.178329 ==
8361 12:26:49.182122 Write leveling (Byte 0): 25 => 25
8362 12:26:49.182205 Write leveling (Byte 1): 28 => 28
8363 12:26:49.184666 DramcWriteLeveling(PI) end<-----
8364 12:26:49.184749
8365 12:26:49.188397 ==
8366 12:26:49.191617 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 12:26:49.194745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 12:26:49.194829 ==
8369 12:26:49.197863 [Gating] SW mode calibration
8370 12:26:49.204959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 12:26:49.208097 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 12:26:49.214631 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:26:49.217953 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:26:49.221227 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 12:26:49.227930 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 12:26:49.231240 1 4 16 | B1->B0 | 3030 2626 | 1 0 | (0 0) (0 0)
8377 12:26:49.234538 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:26:49.241107 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:26:49.244398 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:26:49.247744 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:26:49.254248 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 12:26:49.257547 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 12:26:49.260823 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8384 12:26:49.267532 1 5 16 | B1->B0 | 2f2f 3434 | 1 0 | (1 0) (0 0)
8385 12:26:49.270651 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8386 12:26:49.273860 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:26:49.281019 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:26:49.284214 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:26:49.287509 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 12:26:49.293898 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 12:26:49.297269 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8392 12:26:49.300495 1 6 16 | B1->B0 | 3e3e 3131 | 0 0 | (0 0) (0 0)
8393 12:26:49.307145 1 6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8394 12:26:49.310598 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:26:49.313951 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:26:49.320640 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:26:49.323946 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:26:49.327282 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:26:49.333940 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 12:26:49.337242 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 12:26:49.340593 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:26:49.347158 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:26:49.350480 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:26:49.353215 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:26:49.359915 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:26:49.363227 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:26:49.366581 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:26:49.373273 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:26:49.376656 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:26:49.379910 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:26:49.383225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:26:49.390244 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:26:49.393487 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:26:49.396700 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:26:49.403650 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 12:26:49.406866 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 12:26:49.409977 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 12:26:49.413215 Total UI for P1: 0, mck2ui 16
8419 12:26:49.416678 best dqsien dly found for B0: ( 1, 9, 14)
8420 12:26:49.419903 Total UI for P1: 0, mck2ui 16
8421 12:26:49.423232 best dqsien dly found for B1: ( 1, 9, 14)
8422 12:26:49.426593 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8423 12:26:49.429759 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8424 12:26:49.429846
8425 12:26:49.436580 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8426 12:26:49.439879 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8427 12:26:49.443075 [Gating] SW calibration Done
8428 12:26:49.443161 ==
8429 12:26:49.446356 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 12:26:49.450184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 12:26:49.450272 ==
8432 12:26:49.450340 RX Vref Scan: 0
8433 12:26:49.450420
8434 12:26:49.453515 RX Vref 0 -> 0, step: 1
8435 12:26:49.453600
8436 12:26:49.456852 RX Delay 0 -> 252, step: 8
8437 12:26:49.460111 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8438 12:26:49.463422 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8439 12:26:49.469482 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8440 12:26:49.472807 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8441 12:26:49.476114 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8442 12:26:49.480028 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8443 12:26:49.483174 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8444 12:26:49.486441 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8445 12:26:49.492691 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8446 12:26:49.496468 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8447 12:26:49.499974 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8448 12:26:49.502942 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8449 12:26:49.509426 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8450 12:26:49.513165 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8451 12:26:49.516433 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8452 12:26:49.519517 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8453 12:26:49.519625 ==
8454 12:26:49.522936 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 12:26:49.529467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 12:26:49.529604 ==
8457 12:26:49.529732 DQS Delay:
8458 12:26:49.529869 DQS0 = 0, DQS1 = 0
8459 12:26:49.532931 DQM Delay:
8460 12:26:49.533033 DQM0 = 134, DQM1 = 126
8461 12:26:49.535791 DQ Delay:
8462 12:26:49.539122 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8463 12:26:49.543146 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8464 12:26:49.545842 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8465 12:26:49.549172 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8466 12:26:49.549288
8467 12:26:49.549386
8468 12:26:49.549464 ==
8469 12:26:49.552589 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 12:26:49.556008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 12:26:49.559278 ==
8472 12:26:49.559369
8473 12:26:49.559516
8474 12:26:49.559661 TX Vref Scan disable
8475 12:26:49.562640 == TX Byte 0 ==
8476 12:26:49.565848 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8477 12:26:49.569240 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8478 12:26:49.572477 == TX Byte 1 ==
8479 12:26:49.575889 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8480 12:26:49.579130 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8481 12:26:49.579244 ==
8482 12:26:49.582443 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 12:26:49.589224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 12:26:49.589300 ==
8485 12:26:49.602053
8486 12:26:49.605338 TX Vref early break, caculate TX vref
8487 12:26:49.608483 TX Vref=16, minBit 8, minWin=21, winSum=362
8488 12:26:49.612350 TX Vref=18, minBit 8, minWin=21, winSum=368
8489 12:26:49.615440 TX Vref=20, minBit 8, minWin=21, winSum=380
8490 12:26:49.618726 TX Vref=22, minBit 8, minWin=23, winSum=390
8491 12:26:49.621737 TX Vref=24, minBit 8, minWin=23, winSum=398
8492 12:26:49.628910 TX Vref=26, minBit 5, minWin=24, winSum=411
8493 12:26:49.632240 TX Vref=28, minBit 8, minWin=25, winSum=418
8494 12:26:49.635487 TX Vref=30, minBit 8, minWin=25, winSum=414
8495 12:26:49.638860 TX Vref=32, minBit 0, minWin=25, winSum=411
8496 12:26:49.642317 TX Vref=34, minBit 0, minWin=24, winSum=399
8497 12:26:49.645612 TX Vref=36, minBit 0, minWin=23, winSum=388
8498 12:26:49.652045 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8499 12:26:49.652142
8500 12:26:49.655325 Final TX Range 0 Vref 28
8501 12:26:49.655425
8502 12:26:49.655495 ==
8503 12:26:49.658746 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 12:26:49.662172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 12:26:49.662279 ==
8506 12:26:49.662353
8507 12:26:49.662417
8508 12:26:49.665519 TX Vref Scan disable
8509 12:26:49.672122 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8510 12:26:49.672232 == TX Byte 0 ==
8511 12:26:49.675200 u2DelayCellOfst[0]=21 cells (6 PI)
8512 12:26:49.678571 u2DelayCellOfst[1]=14 cells (4 PI)
8513 12:26:49.681900 u2DelayCellOfst[2]=0 cells (0 PI)
8514 12:26:49.685087 u2DelayCellOfst[3]=10 cells (3 PI)
8515 12:26:49.688462 u2DelayCellOfst[4]=14 cells (4 PI)
8516 12:26:49.691881 u2DelayCellOfst[5]=21 cells (6 PI)
8517 12:26:49.695201 u2DelayCellOfst[6]=21 cells (6 PI)
8518 12:26:49.698527 u2DelayCellOfst[7]=10 cells (3 PI)
8519 12:26:49.701876 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8520 12:26:49.704989 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8521 12:26:49.708253 == TX Byte 1 ==
8522 12:26:49.712193 u2DelayCellOfst[8]=0 cells (0 PI)
8523 12:26:49.712283 u2DelayCellOfst[9]=7 cells (2 PI)
8524 12:26:49.715270 u2DelayCellOfst[10]=10 cells (3 PI)
8525 12:26:49.718541 u2DelayCellOfst[11]=7 cells (2 PI)
8526 12:26:49.721706 u2DelayCellOfst[12]=14 cells (4 PI)
8527 12:26:49.724763 u2DelayCellOfst[13]=17 cells (5 PI)
8528 12:26:49.728565 u2DelayCellOfst[14]=17 cells (5 PI)
8529 12:26:49.731858 u2DelayCellOfst[15]=17 cells (5 PI)
8530 12:26:49.735075 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8531 12:26:49.741572 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8532 12:26:49.741665 DramC Write-DBI on
8533 12:26:49.741772 ==
8534 12:26:49.744977 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 12:26:49.751658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 12:26:49.751748 ==
8537 12:26:49.751817
8538 12:26:49.751878
8539 12:26:49.751940 TX Vref Scan disable
8540 12:26:49.755588 == TX Byte 0 ==
8541 12:26:49.758972 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8542 12:26:49.762356 == TX Byte 1 ==
8543 12:26:49.765720 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8544 12:26:49.769064 DramC Write-DBI off
8545 12:26:49.769178
8546 12:26:49.769274 [DATLAT]
8547 12:26:49.769364 Freq=1600, CH1 RK0
8548 12:26:49.769453
8549 12:26:49.771648 DATLAT Default: 0xf
8550 12:26:49.775817 0, 0xFFFF, sum = 0
8551 12:26:49.775931 1, 0xFFFF, sum = 0
8552 12:26:49.778382 2, 0xFFFF, sum = 0
8553 12:26:49.778486 3, 0xFFFF, sum = 0
8554 12:26:49.781659 4, 0xFFFF, sum = 0
8555 12:26:49.781763 5, 0xFFFF, sum = 0
8556 12:26:49.784926 6, 0xFFFF, sum = 0
8557 12:26:49.785039 7, 0xFFFF, sum = 0
8558 12:26:49.788911 8, 0xFFFF, sum = 0
8559 12:26:49.789024 9, 0xFFFF, sum = 0
8560 12:26:49.791627 10, 0xFFFF, sum = 0
8561 12:26:49.791739 11, 0xFFFF, sum = 0
8562 12:26:49.794911 12, 0xFFFF, sum = 0
8563 12:26:49.795015 13, 0xFFFF, sum = 0
8564 12:26:49.798242 14, 0x0, sum = 1
8565 12:26:49.798355 15, 0x0, sum = 2
8566 12:26:49.801473 16, 0x0, sum = 3
8567 12:26:49.801579 17, 0x0, sum = 4
8568 12:26:49.805047 best_step = 15
8569 12:26:49.805132
8570 12:26:49.805198 ==
8571 12:26:49.808283 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 12:26:49.811495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 12:26:49.811598 ==
8574 12:26:49.814865 RX Vref Scan: 1
8575 12:26:49.814975
8576 12:26:49.815071 Set Vref Range= 24 -> 127
8577 12:26:49.815166
8578 12:26:49.817969 RX Vref 24 -> 127, step: 1
8579 12:26:49.818079
8580 12:26:49.821698 RX Delay 11 -> 252, step: 4
8581 12:26:49.821801
8582 12:26:49.824801 Set Vref, RX VrefLevel [Byte0]: 24
8583 12:26:49.828224 [Byte1]: 24
8584 12:26:49.828328
8585 12:26:49.832062 Set Vref, RX VrefLevel [Byte0]: 25
8586 12:26:49.834987 [Byte1]: 25
8587 12:26:49.838137
8588 12:26:49.838222 Set Vref, RX VrefLevel [Byte0]: 26
8589 12:26:49.841368 [Byte1]: 26
8590 12:26:49.845934
8591 12:26:49.846019 Set Vref, RX VrefLevel [Byte0]: 27
8592 12:26:49.849182 [Byte1]: 27
8593 12:26:49.853728
8594 12:26:49.853819 Set Vref, RX VrefLevel [Byte0]: 28
8595 12:26:49.856928 [Byte1]: 28
8596 12:26:49.860977
8597 12:26:49.861094 Set Vref, RX VrefLevel [Byte0]: 29
8598 12:26:49.864315 [Byte1]: 29
8599 12:26:49.869000
8600 12:26:49.869089 Set Vref, RX VrefLevel [Byte0]: 30
8601 12:26:49.872336 [Byte1]: 30
8602 12:26:49.876234
8603 12:26:49.876318 Set Vref, RX VrefLevel [Byte0]: 31
8604 12:26:49.879300 [Byte1]: 31
8605 12:26:49.884072
8606 12:26:49.884159 Set Vref, RX VrefLevel [Byte0]: 32
8607 12:26:49.887342 [Byte1]: 32
8608 12:26:49.892063
8609 12:26:49.892147 Set Vref, RX VrefLevel [Byte0]: 33
8610 12:26:49.894689 [Byte1]: 33
8611 12:26:49.899268
8612 12:26:49.899414 Set Vref, RX VrefLevel [Byte0]: 34
8613 12:26:49.902719 [Byte1]: 34
8614 12:26:49.906786
8615 12:26:49.906874 Set Vref, RX VrefLevel [Byte0]: 35
8616 12:26:49.910031 [Byte1]: 35
8617 12:26:49.914735
8618 12:26:49.914821 Set Vref, RX VrefLevel [Byte0]: 36
8619 12:26:49.917940 [Byte1]: 36
8620 12:26:49.921967
8621 12:26:49.922052 Set Vref, RX VrefLevel [Byte0]: 37
8622 12:26:49.925183 [Byte1]: 37
8623 12:26:49.929564
8624 12:26:49.929648 Set Vref, RX VrefLevel [Byte0]: 38
8625 12:26:49.932765 [Byte1]: 38
8626 12:26:49.937137
8627 12:26:49.937223 Set Vref, RX VrefLevel [Byte0]: 39
8628 12:26:49.940821 [Byte1]: 39
8629 12:26:49.945115
8630 12:26:49.945200 Set Vref, RX VrefLevel [Byte0]: 40
8631 12:26:49.948199 [Byte1]: 40
8632 12:26:49.952548
8633 12:26:49.952647 Set Vref, RX VrefLevel [Byte0]: 41
8634 12:26:49.955858 [Byte1]: 41
8635 12:26:49.959975
8636 12:26:49.960060 Set Vref, RX VrefLevel [Byte0]: 42
8637 12:26:49.963334 [Byte1]: 42
8638 12:26:49.967939
8639 12:26:49.968039 Set Vref, RX VrefLevel [Byte0]: 43
8640 12:26:49.971216 [Byte1]: 43
8641 12:26:49.975208
8642 12:26:49.975336 Set Vref, RX VrefLevel [Byte0]: 44
8643 12:26:49.978511 [Byte1]: 44
8644 12:26:49.983020
8645 12:26:49.983152 Set Vref, RX VrefLevel [Byte0]: 45
8646 12:26:49.986317 [Byte1]: 45
8647 12:26:49.990394
8648 12:26:49.990518 Set Vref, RX VrefLevel [Byte0]: 46
8649 12:26:49.993739 [Byte1]: 46
8650 12:26:49.997859
8651 12:26:49.997937 Set Vref, RX VrefLevel [Byte0]: 47
8652 12:26:50.001270 [Byte1]: 47
8653 12:26:50.005881
8654 12:26:50.005967 Set Vref, RX VrefLevel [Byte0]: 48
8655 12:26:50.009158 [Byte1]: 48
8656 12:26:50.013650
8657 12:26:50.013735 Set Vref, RX VrefLevel [Byte0]: 49
8658 12:26:50.016943 [Byte1]: 49
8659 12:26:50.020958
8660 12:26:50.021040 Set Vref, RX VrefLevel [Byte0]: 50
8661 12:26:50.024259 [Byte1]: 50
8662 12:26:50.029347
8663 12:26:50.029432 Set Vref, RX VrefLevel [Byte0]: 51
8664 12:26:50.031606 [Byte1]: 51
8665 12:26:50.036146
8666 12:26:50.036235 Set Vref, RX VrefLevel [Byte0]: 52
8667 12:26:50.039376 [Byte1]: 52
8668 12:26:50.043882
8669 12:26:50.043977 Set Vref, RX VrefLevel [Byte0]: 53
8670 12:26:50.046921 [Byte1]: 53
8671 12:26:50.051352
8672 12:26:50.051450 Set Vref, RX VrefLevel [Byte0]: 54
8673 12:26:50.054531 [Byte1]: 54
8674 12:26:50.058849
8675 12:26:50.058962 Set Vref, RX VrefLevel [Byte0]: 55
8676 12:26:50.061943 [Byte1]: 55
8677 12:26:50.066628
8678 12:26:50.066708 Set Vref, RX VrefLevel [Byte0]: 56
8679 12:26:50.069920 [Byte1]: 56
8680 12:26:50.073935
8681 12:26:50.074021 Set Vref, RX VrefLevel [Byte0]: 57
8682 12:26:50.077280 [Byte1]: 57
8683 12:26:50.081930
8684 12:26:50.082036 Set Vref, RX VrefLevel [Byte0]: 58
8685 12:26:50.085082 [Byte1]: 58
8686 12:26:50.089620
8687 12:26:50.089707 Set Vref, RX VrefLevel [Byte0]: 59
8688 12:26:50.092818 [Byte1]: 59
8689 12:26:50.096878
8690 12:26:50.096956 Set Vref, RX VrefLevel [Byte0]: 60
8691 12:26:50.100211 [Byte1]: 60
8692 12:26:50.104886
8693 12:26:50.104961 Set Vref, RX VrefLevel [Byte0]: 61
8694 12:26:50.108082 [Byte1]: 61
8695 12:26:50.112137
8696 12:26:50.112211 Set Vref, RX VrefLevel [Byte0]: 62
8697 12:26:50.115474 [Byte1]: 62
8698 12:26:50.120211
8699 12:26:50.120298 Set Vref, RX VrefLevel [Byte0]: 63
8700 12:26:50.123533 [Byte1]: 63
8701 12:26:50.127583
8702 12:26:50.127672 Set Vref, RX VrefLevel [Byte0]: 64
8703 12:26:50.130965 [Byte1]: 64
8704 12:26:50.134942
8705 12:26:50.135037 Set Vref, RX VrefLevel [Byte0]: 65
8706 12:26:50.138166 [Byte1]: 65
8707 12:26:50.142572
8708 12:26:50.142660 Set Vref, RX VrefLevel [Byte0]: 66
8709 12:26:50.145767 [Byte1]: 66
8710 12:26:50.150127
8711 12:26:50.150214 Set Vref, RX VrefLevel [Byte0]: 67
8712 12:26:50.153978 [Byte1]: 67
8713 12:26:50.157762
8714 12:26:50.157859 Set Vref, RX VrefLevel [Byte0]: 68
8715 12:26:50.161613 [Byte1]: 68
8716 12:26:50.165339
8717 12:26:50.165428 Set Vref, RX VrefLevel [Byte0]: 69
8718 12:26:50.169196 [Byte1]: 69
8719 12:26:50.173207
8720 12:26:50.173345 Set Vref, RX VrefLevel [Byte0]: 70
8721 12:26:50.176557 [Byte1]: 70
8722 12:26:50.181189
8723 12:26:50.181275 Set Vref, RX VrefLevel [Byte0]: 71
8724 12:26:50.184029 [Byte1]: 71
8725 12:26:50.188672
8726 12:26:50.188759 Set Vref, RX VrefLevel [Byte0]: 72
8727 12:26:50.191902 [Byte1]: 72
8728 12:26:50.196340
8729 12:26:50.196427 Set Vref, RX VrefLevel [Byte0]: 73
8730 12:26:50.199578 [Byte1]: 73
8731 12:26:50.203596
8732 12:26:50.203682 Final RX Vref Byte 0 = 58 to rank0
8733 12:26:50.206933 Final RX Vref Byte 1 = 56 to rank0
8734 12:26:50.210271 Final RX Vref Byte 0 = 58 to rank1
8735 12:26:50.213510 Final RX Vref Byte 1 = 56 to rank1==
8736 12:26:50.216864 Dram Type= 6, Freq= 0, CH_1, rank 0
8737 12:26:50.223546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 12:26:50.223637 ==
8739 12:26:50.223705 DQS Delay:
8740 12:26:50.226977 DQS0 = 0, DQS1 = 0
8741 12:26:50.227063 DQM Delay:
8742 12:26:50.227131 DQM0 = 131, DQM1 = 124
8743 12:26:50.230386 DQ Delay:
8744 12:26:50.233734 DQ0 =136, DQ1 =124, DQ2 =120, DQ3 =130
8745 12:26:50.237069 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8746 12:26:50.240441 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8747 12:26:50.243687 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8748 12:26:50.243774
8749 12:26:50.243843
8750 12:26:50.243905
8751 12:26:50.246836 [DramC_TX_OE_Calibration] TA2
8752 12:26:50.249940 Original DQ_B0 (3 6) =30, OEN = 27
8753 12:26:50.253277 Original DQ_B1 (3 6) =30, OEN = 27
8754 12:26:50.256412 24, 0x0, End_B0=24 End_B1=24
8755 12:26:50.256494 25, 0x0, End_B0=25 End_B1=25
8756 12:26:50.259526 26, 0x0, End_B0=26 End_B1=26
8757 12:26:50.263235 27, 0x0, End_B0=27 End_B1=27
8758 12:26:50.266565 28, 0x0, End_B0=28 End_B1=28
8759 12:26:50.269637 29, 0x0, End_B0=29 End_B1=29
8760 12:26:50.269725 30, 0x0, End_B0=30 End_B1=30
8761 12:26:50.273433 31, 0x4141, End_B0=30 End_B1=30
8762 12:26:50.276697 Byte0 end_step=30 best_step=27
8763 12:26:50.280004 Byte1 end_step=30 best_step=27
8764 12:26:50.283474 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 12:26:50.286831 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 12:26:50.286912
8767 12:26:50.287011
8768 12:26:50.292857 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8769 12:26:50.296817 CH1 RK0: MR19=303, MR18=1400
8770 12:26:50.303295 CH1_RK0: MR19=0x303, MR18=0x1400, DQSOSC=399, MR23=63, INC=23, DEC=15
8771 12:26:50.303420
8772 12:26:50.306592 ----->DramcWriteLeveling(PI) begin...
8773 12:26:50.306672 ==
8774 12:26:50.309933 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 12:26:50.313225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 12:26:50.313313 ==
8777 12:26:50.316528 Write leveling (Byte 0): 24 => 24
8778 12:26:50.319934 Write leveling (Byte 1): 25 => 25
8779 12:26:50.323171 DramcWriteLeveling(PI) end<-----
8780 12:26:50.323278
8781 12:26:50.323379 ==
8782 12:26:50.326473 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 12:26:50.329821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 12:26:50.329906 ==
8785 12:26:50.333223 [Gating] SW mode calibration
8786 12:26:50.339285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8787 12:26:50.345951 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8788 12:26:50.349318 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 12:26:50.355969 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 12:26:50.359242 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8791 12:26:50.363079 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
8792 12:26:50.369356 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8793 12:26:50.372654 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 12:26:50.375894 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 12:26:50.382773 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 12:26:50.386147 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 12:26:50.389426 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8798 12:26:50.395928 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
8799 12:26:50.399231 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8800 12:26:50.402589 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8801 12:26:50.405766 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:26:50.412547 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 12:26:50.415885 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 12:26:50.421754 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 12:26:50.425748 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 12:26:50.429090 1 6 8 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
8807 12:26:50.431783 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8808 12:26:50.438447 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:26:50.441790 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 12:26:50.445169 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 12:26:50.451887 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 12:26:50.455266 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 12:26:50.458773 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 12:26:50.464932 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8815 12:26:50.468727 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8816 12:26:50.472198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8817 12:26:50.478309 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:26:50.481662 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:26:50.485385 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:26:50.491953 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:26:50.495195 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:26:50.498519 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:26:50.505169 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:26:50.508336 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:26:50.511469 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:26:50.518183 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:26:50.521524 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:26:50.524804 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 12:26:50.531476 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 12:26:50.534876 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8831 12:26:50.538262 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8832 12:26:50.541610 Total UI for P1: 0, mck2ui 16
8833 12:26:50.544355 best dqsien dly found for B0: ( 1, 9, 8)
8834 12:26:50.551054 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 12:26:50.551140 Total UI for P1: 0, mck2ui 16
8836 12:26:50.557918 best dqsien dly found for B1: ( 1, 9, 10)
8837 12:26:50.561276 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8838 12:26:50.564510 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8839 12:26:50.564595
8840 12:26:50.567851 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8841 12:26:50.571308 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8842 12:26:50.574551 [Gating] SW calibration Done
8843 12:26:50.574638 ==
8844 12:26:50.577595 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 12:26:50.580805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 12:26:50.580891 ==
8847 12:26:50.584687 RX Vref Scan: 0
8848 12:26:50.584772
8849 12:26:50.584840 RX Vref 0 -> 0, step: 1
8850 12:26:50.584903
8851 12:26:50.587891 RX Delay 0 -> 252, step: 8
8852 12:26:50.591062 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8853 12:26:50.597885 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8854 12:26:50.601175 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8855 12:26:50.604455 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8856 12:26:50.607823 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8857 12:26:50.610602 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8858 12:26:50.617135 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8859 12:26:50.621115 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8860 12:26:50.624480 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8861 12:26:50.627770 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8862 12:26:50.630490 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8863 12:26:50.637198 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8864 12:26:50.640647 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8865 12:26:50.643898 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8866 12:26:50.647237 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8867 12:26:50.653960 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8868 12:26:50.654046 ==
8869 12:26:50.657258 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 12:26:50.660517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 12:26:50.660602 ==
8872 12:26:50.660679 DQS Delay:
8873 12:26:50.663971 DQS0 = 0, DQS1 = 0
8874 12:26:50.664056 DQM Delay:
8875 12:26:50.667248 DQM0 = 132, DQM1 = 127
8876 12:26:50.667369 DQ Delay:
8877 12:26:50.670530 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8878 12:26:50.673784 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8879 12:26:50.676912 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8880 12:26:50.680221 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8881 12:26:50.680307
8882 12:26:50.680394
8883 12:26:50.680477 ==
8884 12:26:50.683787 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 12:26:50.690236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 12:26:50.690351 ==
8887 12:26:50.690440
8888 12:26:50.690519
8889 12:26:50.693425 TX Vref Scan disable
8890 12:26:50.693525 == TX Byte 0 ==
8891 12:26:50.697246 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8892 12:26:50.703696 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 12:26:50.703784 == TX Byte 1 ==
8894 12:26:50.706739 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8895 12:26:50.713449 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8896 12:26:50.713590 ==
8897 12:26:50.716873 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 12:26:50.719840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 12:26:50.719927 ==
8900 12:26:50.734305
8901 12:26:50.737674 TX Vref early break, caculate TX vref
8902 12:26:50.740340 TX Vref=16, minBit 0, minWin=23, winSum=385
8903 12:26:50.743726 TX Vref=18, minBit 9, minWin=23, winSum=397
8904 12:26:50.747020 TX Vref=20, minBit 6, minWin=24, winSum=403
8905 12:26:50.750488 TX Vref=22, minBit 0, minWin=25, winSum=412
8906 12:26:50.753817 TX Vref=24, minBit 0, minWin=25, winSum=420
8907 12:26:50.760358 TX Vref=26, minBit 8, minWin=25, winSum=428
8908 12:26:50.763687 TX Vref=28, minBit 5, minWin=25, winSum=431
8909 12:26:50.767005 TX Vref=30, minBit 5, minWin=25, winSum=429
8910 12:26:50.770250 TX Vref=32, minBit 0, minWin=25, winSum=420
8911 12:26:50.773621 TX Vref=34, minBit 5, minWin=24, winSum=412
8912 12:26:50.776857 TX Vref=36, minBit 0, minWin=23, winSum=406
8913 12:26:50.783909 [TxChooseVref] Worse bit 5, Min win 25, Win sum 431, Final Vref 28
8914 12:26:50.783998
8915 12:26:50.786917 Final TX Range 0 Vref 28
8916 12:26:50.787003
8917 12:26:50.787070 ==
8918 12:26:50.790553 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 12:26:50.793869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 12:26:50.793967 ==
8921 12:26:50.794036
8922 12:26:50.794098
8923 12:26:50.797133 TX Vref Scan disable
8924 12:26:50.803996 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8925 12:26:50.804082 == TX Byte 0 ==
8926 12:26:50.807173 u2DelayCellOfst[0]=17 cells (5 PI)
8927 12:26:50.810398 u2DelayCellOfst[1]=14 cells (4 PI)
8928 12:26:50.813594 u2DelayCellOfst[2]=0 cells (0 PI)
8929 12:26:50.816637 u2DelayCellOfst[3]=7 cells (2 PI)
8930 12:26:50.820486 u2DelayCellOfst[4]=10 cells (3 PI)
8931 12:26:50.823215 u2DelayCellOfst[5]=17 cells (5 PI)
8932 12:26:50.827018 u2DelayCellOfst[6]=17 cells (5 PI)
8933 12:26:50.830491 u2DelayCellOfst[7]=7 cells (2 PI)
8934 12:26:50.833234 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8935 12:26:50.836547 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8936 12:26:50.839826 == TX Byte 1 ==
8937 12:26:50.843871 u2DelayCellOfst[8]=0 cells (0 PI)
8938 12:26:50.843957 u2DelayCellOfst[9]=3 cells (1 PI)
8939 12:26:50.846555 u2DelayCellOfst[10]=10 cells (3 PI)
8940 12:26:50.849903 u2DelayCellOfst[11]=3 cells (1 PI)
8941 12:26:50.853322 u2DelayCellOfst[12]=10 cells (3 PI)
8942 12:26:50.856654 u2DelayCellOfst[13]=14 cells (4 PI)
8943 12:26:50.859988 u2DelayCellOfst[14]=17 cells (5 PI)
8944 12:26:50.863300 u2DelayCellOfst[15]=14 cells (4 PI)
8945 12:26:50.869950 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8946 12:26:50.873339 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8947 12:26:50.873432 DramC Write-DBI on
8948 12:26:50.873500 ==
8949 12:26:50.876702 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 12:26:50.883403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 12:26:50.883514 ==
8952 12:26:50.883585
8953 12:26:50.883648
8954 12:26:50.883708 TX Vref Scan disable
8955 12:26:50.887277 == TX Byte 0 ==
8956 12:26:50.890785 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8957 12:26:50.893968 == TX Byte 1 ==
8958 12:26:50.897133 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8959 12:26:50.900331 DramC Write-DBI off
8960 12:26:50.900437
8961 12:26:50.900536 [DATLAT]
8962 12:26:50.900602 Freq=1600, CH1 RK1
8963 12:26:50.900663
8964 12:26:50.903345 DATLAT Default: 0xf
8965 12:26:50.907378 0, 0xFFFF, sum = 0
8966 12:26:50.907499 1, 0xFFFF, sum = 0
8967 12:26:50.910318 2, 0xFFFF, sum = 0
8968 12:26:50.910396 3, 0xFFFF, sum = 0
8969 12:26:50.913625 4, 0xFFFF, sum = 0
8970 12:26:50.913705 5, 0xFFFF, sum = 0
8971 12:26:50.916739 6, 0xFFFF, sum = 0
8972 12:26:50.916815 7, 0xFFFF, sum = 0
8973 12:26:50.920375 8, 0xFFFF, sum = 0
8974 12:26:50.920450 9, 0xFFFF, sum = 0
8975 12:26:50.923429 10, 0xFFFF, sum = 0
8976 12:26:50.923541 11, 0xFFFF, sum = 0
8977 12:26:50.926792 12, 0xFFFF, sum = 0
8978 12:26:50.926882 13, 0xFFFF, sum = 0
8979 12:26:50.930082 14, 0x0, sum = 1
8980 12:26:50.930175 15, 0x0, sum = 2
8981 12:26:50.933219 16, 0x0, sum = 3
8982 12:26:50.933319 17, 0x0, sum = 4
8983 12:26:50.936581 best_step = 15
8984 12:26:50.936686
8985 12:26:50.936772 ==
8986 12:26:50.940350 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 12:26:50.943633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 12:26:50.943748 ==
8989 12:26:50.946939 RX Vref Scan: 0
8990 12:26:50.947013
8991 12:26:50.947077 RX Vref 0 -> 0, step: 1
8992 12:26:50.947139
8993 12:26:50.950335 RX Delay 11 -> 252, step: 4
8994 12:26:50.956479 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8995 12:26:50.960013 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8996 12:26:50.963223 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8997 12:26:50.966543 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8998 12:26:50.969970 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8999 12:26:50.976761 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9000 12:26:50.980053 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9001 12:26:50.983330 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9002 12:26:50.986540 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9003 12:26:50.989809 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9004 12:26:50.996536 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9005 12:26:51.000016 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9006 12:26:51.003115 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9007 12:26:51.006183 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9008 12:26:51.009409 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9009 12:26:51.016400 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9010 12:26:51.016538 ==
9011 12:26:51.019331 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 12:26:51.022656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 12:26:51.022738 ==
9014 12:26:51.022836 DQS Delay:
9015 12:26:51.026320 DQS0 = 0, DQS1 = 0
9016 12:26:51.026423 DQM Delay:
9017 12:26:51.029595 DQM0 = 129, DQM1 = 126
9018 12:26:51.029683 DQ Delay:
9019 12:26:51.032687 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9020 12:26:51.035845 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9021 12:26:51.039684 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9022 12:26:51.042893 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
9023 12:26:51.043019
9024 12:26:51.046279
9025 12:26:51.046397
9026 12:26:51.046492 [DramC_TX_OE_Calibration] TA2
9027 12:26:51.049653 Original DQ_B0 (3 6) =30, OEN = 27
9028 12:26:51.052964 Original DQ_B1 (3 6) =30, OEN = 27
9029 12:26:51.056338 24, 0x0, End_B0=24 End_B1=24
9030 12:26:51.059632 25, 0x0, End_B0=25 End_B1=25
9031 12:26:51.062949 26, 0x0, End_B0=26 End_B1=26
9032 12:26:51.063039 27, 0x0, End_B0=27 End_B1=27
9033 12:26:51.066443 28, 0x0, End_B0=28 End_B1=28
9034 12:26:51.069584 29, 0x0, End_B0=29 End_B1=29
9035 12:26:51.072399 30, 0x0, End_B0=30 End_B1=30
9036 12:26:51.075663 31, 0x4141, End_B0=30 End_B1=30
9037 12:26:51.075752 Byte0 end_step=30 best_step=27
9038 12:26:51.079479 Byte1 end_step=30 best_step=27
9039 12:26:51.082990 Byte0 TX OE(2T, 0.5T) = (3, 3)
9040 12:26:51.085640 Byte1 TX OE(2T, 0.5T) = (3, 3)
9041 12:26:51.085731
9042 12:26:51.085799
9043 12:26:51.092332 [DQSOSCAuto] RK1, (LSB)MR18= 0xe13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
9044 12:26:51.095759 CH1 RK1: MR19=303, MR18=E13
9045 12:26:51.102251 CH1_RK1: MR19=0x303, MR18=0xE13, DQSOSC=400, MR23=63, INC=23, DEC=15
9046 12:26:51.105576 [RxdqsGatingPostProcess] freq 1600
9047 12:26:51.112565 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9048 12:26:51.115761 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 12:26:51.115905 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 12:26:51.119100 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 12:26:51.122133 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 12:26:51.125467 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 12:26:51.128658 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 12:26:51.132543 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 12:26:51.135532 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 12:26:51.138863 Pre-setting of DQS Precalculation
9057 12:26:51.142222 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9058 12:26:51.151905 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9059 12:26:51.158647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9060 12:26:51.158734
9061 12:26:51.158802
9062 12:26:51.161939 [Calibration Summary] 3200 Mbps
9063 12:26:51.162019 CH 0, Rank 0
9064 12:26:51.165174 SW Impedance : PASS
9065 12:26:51.165252 DUTY Scan : NO K
9066 12:26:51.169113 ZQ Calibration : PASS
9067 12:26:51.172477 Jitter Meter : NO K
9068 12:26:51.172571 CBT Training : PASS
9069 12:26:51.175754 Write leveling : PASS
9070 12:26:51.179053 RX DQS gating : PASS
9071 12:26:51.179152 RX DQ/DQS(RDDQC) : PASS
9072 12:26:51.181786 TX DQ/DQS : PASS
9073 12:26:51.185232 RX DATLAT : PASS
9074 12:26:51.185338 RX DQ/DQS(Engine): PASS
9075 12:26:51.188518 TX OE : PASS
9076 12:26:51.188636 All Pass.
9077 12:26:51.188752
9078 12:26:51.192004 CH 0, Rank 1
9079 12:26:51.192131 SW Impedance : PASS
9080 12:26:51.195200 DUTY Scan : NO K
9081 12:26:51.198591 ZQ Calibration : PASS
9082 12:26:51.198741 Jitter Meter : NO K
9083 12:26:51.201998 CBT Training : PASS
9084 12:26:51.202173 Write leveling : PASS
9085 12:26:51.205348 RX DQS gating : PASS
9086 12:26:51.208882 RX DQ/DQS(RDDQC) : PASS
9087 12:26:51.209080 TX DQ/DQS : PASS
9088 12:26:51.212277 RX DATLAT : PASS
9089 12:26:51.215421 RX DQ/DQS(Engine): PASS
9090 12:26:51.215615 TX OE : PASS
9091 12:26:51.218545 All Pass.
9092 12:26:51.218738
9093 12:26:51.218884 CH 1, Rank 0
9094 12:26:51.222240 SW Impedance : PASS
9095 12:26:51.222420 DUTY Scan : NO K
9096 12:26:51.225353 ZQ Calibration : PASS
9097 12:26:51.228536 Jitter Meter : NO K
9098 12:26:51.228772 CBT Training : PASS
9099 12:26:51.232220 Write leveling : PASS
9100 12:26:51.234957 RX DQS gating : PASS
9101 12:26:51.235108 RX DQ/DQS(RDDQC) : PASS
9102 12:26:51.238693 TX DQ/DQS : PASS
9103 12:26:51.241830 RX DATLAT : PASS
9104 12:26:51.241946 RX DQ/DQS(Engine): PASS
9105 12:26:51.244993 TX OE : PASS
9106 12:26:51.245109 All Pass.
9107 12:26:51.245200
9108 12:26:51.248580 CH 1, Rank 1
9109 12:26:51.248686 SW Impedance : PASS
9110 12:26:51.251960 DUTY Scan : NO K
9111 12:26:51.255153 ZQ Calibration : PASS
9112 12:26:51.255265 Jitter Meter : NO K
9113 12:26:51.258614 CBT Training : PASS
9114 12:26:51.261231 Write leveling : PASS
9115 12:26:51.261338 RX DQS gating : PASS
9116 12:26:51.264679 RX DQ/DQS(RDDQC) : PASS
9117 12:26:51.264800 TX DQ/DQS : PASS
9118 12:26:51.267960 RX DATLAT : PASS
9119 12:26:51.271280 RX DQ/DQS(Engine): PASS
9120 12:26:51.271427 TX OE : PASS
9121 12:26:51.274705 All Pass.
9122 12:26:51.274870
9123 12:26:51.275096 DramC Write-DBI on
9124 12:26:51.278073 PER_BANK_REFRESH: Hybrid Mode
9125 12:26:51.281329 TX_TRACKING: ON
9126 12:26:51.288626 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9127 12:26:51.297907 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9128 12:26:51.305179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9129 12:26:51.307926 [FAST_K] Save calibration result to emmc
9130 12:26:51.311273 sync common calibartion params.
9131 12:26:51.311391 sync cbt_mode0:1, 1:1
9132 12:26:51.314727 dram_init: ddr_geometry: 2
9133 12:26:51.317960 dram_init: ddr_geometry: 2
9134 12:26:51.321394 dram_init: ddr_geometry: 2
9135 12:26:51.321483 0:dram_rank_size:100000000
9136 12:26:51.324600 1:dram_rank_size:100000000
9137 12:26:51.331184 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9138 12:26:51.331283 DFS_SHUFFLE_HW_MODE: ON
9139 12:26:51.337622 dramc_set_vcore_voltage set vcore to 725000
9140 12:26:51.337715 Read voltage for 1600, 0
9141 12:26:51.341210 Vio18 = 0
9142 12:26:51.341299 Vcore = 725000
9143 12:26:51.341368 Vdram = 0
9144 12:26:51.341433 Vddq = 0
9145 12:26:51.344457 Vmddr = 0
9146 12:26:51.344544 switch to 3200 Mbps bootup
9147 12:26:51.347538 [DramcRunTimeConfig]
9148 12:26:51.347661 PHYPLL
9149 12:26:51.351400 DPM_CONTROL_AFTERK: ON
9150 12:26:51.351489 PER_BANK_REFRESH: ON
9151 12:26:51.354450 REFRESH_OVERHEAD_REDUCTION: ON
9152 12:26:51.357498 CMD_PICG_NEW_MODE: OFF
9153 12:26:51.357585 XRTWTW_NEW_MODE: ON
9154 12:26:51.361324 XRTRTR_NEW_MODE: ON
9155 12:26:51.361403 TX_TRACKING: ON
9156 12:26:51.364633 RDSEL_TRACKING: OFF
9157 12:26:51.367875 DQS Precalculation for DVFS: ON
9158 12:26:51.367955 RX_TRACKING: OFF
9159 12:26:51.371218 HW_GATING DBG: ON
9160 12:26:51.371328 ZQCS_ENABLE_LP4: ON
9161 12:26:51.374533 RX_PICG_NEW_MODE: ON
9162 12:26:51.374609 TX_PICG_NEW_MODE: ON
9163 12:26:51.377910 ENABLE_RX_DCM_DPHY: ON
9164 12:26:51.381141 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9165 12:26:51.384519 DUMMY_READ_FOR_TRACKING: OFF
9166 12:26:51.387920 !!! SPM_CONTROL_AFTERK: OFF
9167 12:26:51.388031 !!! SPM could not control APHY
9168 12:26:51.391196 IMPEDANCE_TRACKING: ON
9169 12:26:51.391283 TEMP_SENSOR: ON
9170 12:26:51.394525 HW_SAVE_FOR_SR: OFF
9171 12:26:51.397843 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9172 12:26:51.401167 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9173 12:26:51.404547 Read ODT Tracking: ON
9174 12:26:51.404636 Refresh Rate DeBounce: ON
9175 12:26:51.407871 DFS_NO_QUEUE_FLUSH: ON
9176 12:26:51.411196 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9177 12:26:51.414569 ENABLE_DFS_RUNTIME_MRW: OFF
9178 12:26:51.414664 DDR_RESERVE_NEW_MODE: ON
9179 12:26:51.417878 MR_CBT_SWITCH_FREQ: ON
9180 12:26:51.420489 =========================
9181 12:26:51.438373 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9182 12:26:51.441291 dram_init: ddr_geometry: 2
9183 12:26:51.459668 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9184 12:26:51.463281 dram_init: dram init end (result: 0)
9185 12:26:51.470098 DRAM-K: Full calibration passed in 24570 msecs
9186 12:26:51.473491 MRC: failed to locate region type 0.
9187 12:26:51.473622 DRAM rank0 size:0x100000000,
9188 12:26:51.476805 DRAM rank1 size=0x100000000
9189 12:26:51.486229 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9190 12:26:51.493443 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9191 12:26:51.499858 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9192 12:26:51.509196 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9193 12:26:51.509328 DRAM rank0 size:0x100000000,
9194 12:26:51.513142 DRAM rank1 size=0x100000000
9195 12:26:51.513277 CBMEM:
9196 12:26:51.515926 IMD: root @ 0xfffff000 254 entries.
9197 12:26:51.519213 IMD: root @ 0xffffec00 62 entries.
9198 12:26:51.522698 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9199 12:26:51.529418 WARNING: RO_VPD is uninitialized or empty.
9200 12:26:51.532692 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9201 12:26:51.540182 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9202 12:26:51.553073 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9203 12:26:51.563906 BS: romstage times (exec / console): total (unknown) / 24075 ms
9204 12:26:51.564040
9205 12:26:51.564112
9206 12:26:51.574211 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9207 12:26:51.577289 ARM64: Exception handlers installed.
9208 12:26:51.581054 ARM64: Testing exception
9209 12:26:51.584413 ARM64: Done test exception
9210 12:26:51.584500 Enumerating buses...
9211 12:26:51.587750 Show all devs... Before device enumeration.
9212 12:26:51.590336 Root Device: enabled 1
9213 12:26:51.593938 CPU_CLUSTER: 0: enabled 1
9214 12:26:51.594022 CPU: 00: enabled 1
9215 12:26:51.597377 Compare with tree...
9216 12:26:51.597467 Root Device: enabled 1
9217 12:26:51.600741 CPU_CLUSTER: 0: enabled 1
9218 12:26:51.604108 CPU: 00: enabled 1
9219 12:26:51.604205 Root Device scanning...
9220 12:26:51.607511 scan_static_bus for Root Device
9221 12:26:51.610975 CPU_CLUSTER: 0 enabled
9222 12:26:51.613811 scan_static_bus for Root Device done
9223 12:26:51.617243 scan_bus: bus Root Device finished in 8 msecs
9224 12:26:51.617370 done
9225 12:26:51.623935 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9226 12:26:51.627328 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9227 12:26:51.634207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9228 12:26:51.636955 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9229 12:26:51.640365 Allocating resources...
9230 12:26:51.643870 Reading resources...
9231 12:26:51.647127 Root Device read_resources bus 0 link: 0
9232 12:26:51.647578 DRAM rank0 size:0x100000000,
9233 12:26:51.650454 DRAM rank1 size=0x100000000
9234 12:26:51.653855 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9235 12:26:51.656909 CPU: 00 missing read_resources
9236 12:26:51.663920 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9237 12:26:51.667131 Root Device read_resources bus 0 link: 0 done
9238 12:26:51.667625 Done reading resources.
9239 12:26:51.673922 Show resources in subtree (Root Device)...After reading.
9240 12:26:51.677348 Root Device child on link 0 CPU_CLUSTER: 0
9241 12:26:51.680371 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 12:26:51.690591 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 12:26:51.690994 CPU: 00
9244 12:26:51.693817 Root Device assign_resources, bus 0 link: 0
9245 12:26:51.697177 CPU_CLUSTER: 0 missing set_resources
9246 12:26:51.703311 Root Device assign_resources, bus 0 link: 0 done
9247 12:26:51.703729 Done setting resources.
9248 12:26:51.709898 Show resources in subtree (Root Device)...After assigning values.
9249 12:26:51.713282 Root Device child on link 0 CPU_CLUSTER: 0
9250 12:26:51.716693 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 12:26:51.726544 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 12:26:51.726632 CPU: 00
9253 12:26:51.729885 Done allocating resources.
9254 12:26:51.736762 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9255 12:26:51.736849 Enabling resources...
9256 12:26:51.736917 done.
9257 12:26:51.743469 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9258 12:26:51.743557 Initializing devices...
9259 12:26:51.746310 Root Device init
9260 12:26:51.746395 init hardware done!
9261 12:26:51.749619 0x00000018: ctrlr->caps
9262 12:26:51.753003 52.000 MHz: ctrlr->f_max
9263 12:26:51.753091 0.400 MHz: ctrlr->f_min
9264 12:26:51.756158 0x40ff8080: ctrlr->voltages
9265 12:26:51.759498 sclk: 390625
9266 12:26:51.759583 Bus Width = 1
9267 12:26:51.759649 sclk: 390625
9268 12:26:51.763224 Bus Width = 1
9269 12:26:51.763333 Early init status = 3
9270 12:26:51.769729 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9271 12:26:51.773342 in-header: 03 fc 00 00 01 00 00 00
9272 12:26:51.773758 in-data: 00
9273 12:26:51.779692 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9274 12:26:51.783087 in-header: 03 fd 00 00 00 00 00 00
9275 12:26:51.786247 in-data:
9276 12:26:51.789958 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9277 12:26:51.793651 in-header: 03 fc 00 00 01 00 00 00
9278 12:26:51.796744 in-data: 00
9279 12:26:51.800158 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9280 12:26:51.808179 in-header: 03 fd 00 00 00 00 00 00
9281 12:26:51.808588 in-data:
9282 12:26:51.811634 [SSUSB] Setting up USB HOST controller...
9283 12:26:51.815053 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9284 12:26:51.818270 [SSUSB] phy power-on done.
9285 12:26:51.821673 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9286 12:26:51.828435 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9287 12:26:51.831696 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9288 12:26:51.838020 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9289 12:26:51.844794 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9290 12:26:51.851024 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9291 12:26:51.857967 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9292 12:26:51.864682 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9293 12:26:51.867867 SPM: binary array size = 0x9dc
9294 12:26:51.871177 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9295 12:26:51.877698 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9296 12:26:51.884301 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9297 12:26:51.890601 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9298 12:26:51.893793 configure_display: Starting display init
9299 12:26:51.928321 anx7625_power_on_init: Init interface.
9300 12:26:51.931689 anx7625_disable_pd_protocol: Disabled PD feature.
9301 12:26:51.935044 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9302 12:26:51.962323 anx7625_start_dp_work: Secure OCM version=00
9303 12:26:51.965727 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9304 12:26:51.980878 sp_tx_get_edid_block: EDID Block = 1
9305 12:26:52.083479 Extracted contents:
9306 12:26:52.086988 header: 00 ff ff ff ff ff ff 00
9307 12:26:52.090055 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9308 12:26:52.093407 version: 01 04
9309 12:26:52.096375 basic params: 95 1f 11 78 0a
9310 12:26:52.100392 chroma info: 76 90 94 55 54 90 27 21 50 54
9311 12:26:52.103576 established: 00 00 00
9312 12:26:52.109937 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9313 12:26:52.113160 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9314 12:26:52.119700 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9315 12:26:52.126168 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9316 12:26:52.133018 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9317 12:26:52.136292 extensions: 00
9318 12:26:52.136377 checksum: fb
9319 12:26:52.136455
9320 12:26:52.139556 Manufacturer: IVO Model 57d Serial Number 0
9321 12:26:52.143005 Made week 0 of 2020
9322 12:26:52.143117 EDID version: 1.4
9323 12:26:52.145758 Digital display
9324 12:26:52.149025 6 bits per primary color channel
9325 12:26:52.149141 DisplayPort interface
9326 12:26:52.152470 Maximum image size: 31 cm x 17 cm
9327 12:26:52.156097 Gamma: 220%
9328 12:26:52.156192 Check DPMS levels
9329 12:26:52.159483 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9330 12:26:52.165553 First detailed timing is preferred timing
9331 12:26:52.165641 Established timings supported:
9332 12:26:52.168911 Standard timings supported:
9333 12:26:52.172291 Detailed timings
9334 12:26:52.175643 Hex of detail: 383680a07038204018303c0035ae10000019
9335 12:26:52.182280 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9336 12:26:52.185554 0780 0798 07c8 0820 hborder 0
9337 12:26:52.188959 0438 043b 0447 0458 vborder 0
9338 12:26:52.192161 -hsync -vsync
9339 12:26:52.192249 Did detailed timing
9340 12:26:52.198954 Hex of detail: 000000000000000000000000000000000000
9341 12:26:52.202188 Manufacturer-specified data, tag 0
9342 12:26:52.205371 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9343 12:26:52.209092 ASCII string: InfoVision
9344 12:26:52.212286 Hex of detail: 000000fe00523134304e574635205248200a
9345 12:26:52.215362 ASCII string: R140NWF5 RH
9346 12:26:52.215470 Checksum
9347 12:26:52.218575 Checksum: 0xfb (valid)
9348 12:26:52.221784 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9349 12:26:52.225692 DSI data_rate: 832800000 bps
9350 12:26:52.232170 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9351 12:26:52.235318 anx7625_parse_edid: pixelclock(138800).
9352 12:26:52.238791 hactive(1920), hsync(48), hfp(24), hbp(88)
9353 12:26:52.241969 vactive(1080), vsync(12), vfp(3), vbp(17)
9354 12:26:52.245410 anx7625_dsi_config: config dsi.
9355 12:26:52.251521 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9356 12:26:52.265340 anx7625_dsi_config: success to config DSI
9357 12:26:52.268676 anx7625_dp_start: MIPI phy setup OK.
9358 12:26:52.272004 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9359 12:26:52.275370 mtk_ddp_mode_set invalid vrefresh 60
9360 12:26:52.278159 main_disp_path_setup
9361 12:26:52.278248 ovl_layer_smi_id_en
9362 12:26:52.281393 ovl_layer_smi_id_en
9363 12:26:52.281509 ccorr_config
9364 12:26:52.281605 aal_config
9365 12:26:52.284748 gamma_config
9366 12:26:52.284863 postmask_config
9367 12:26:52.288149 dither_config
9368 12:26:52.291567 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9369 12:26:52.298270 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9370 12:26:52.301792 Root Device init finished in 552 msecs
9371 12:26:52.304622 CPU_CLUSTER: 0 init
9372 12:26:52.311877 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9373 12:26:52.315055 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9374 12:26:52.318234 APU_MBOX 0x190000b0 = 0x10001
9375 12:26:52.321475 APU_MBOX 0x190001b0 = 0x10001
9376 12:26:52.324682 APU_MBOX 0x190005b0 = 0x10001
9377 12:26:52.327849 APU_MBOX 0x190006b0 = 0x10001
9378 12:26:52.331697 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9379 12:26:52.344444 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9380 12:26:52.356719 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9381 12:26:52.363534 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9382 12:26:52.374969 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9383 12:26:52.383764 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9384 12:26:52.387059 CPU_CLUSTER: 0 init finished in 81 msecs
9385 12:26:52.390382 Devices initialized
9386 12:26:52.393972 Show all devs... After init.
9387 12:26:52.394097 Root Device: enabled 1
9388 12:26:52.397273 CPU_CLUSTER: 0: enabled 1
9389 12:26:52.400693 CPU: 00: enabled 1
9390 12:26:52.404038 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9391 12:26:52.407383 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9392 12:26:52.410678 ELOG: NV offset 0x57f000 size 0x1000
9393 12:26:52.417432 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9394 12:26:52.424111 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9395 12:26:52.427262 ELOG: Event(17) added with size 13 at 2023-06-06 12:27:03 UTC
9396 12:26:52.430458 out: cmd=0x121: 03 db 21 01 00 00 00 00
9397 12:26:52.435074 in-header: 03 db 00 00 2c 00 00 00
9398 12:26:52.448209 in-data: 84 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9399 12:26:52.455220 ELOG: Event(A1) added with size 10 at 2023-06-06 12:27:03 UTC
9400 12:26:52.461427 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9401 12:26:52.468364 ELOG: Event(A0) added with size 9 at 2023-06-06 12:27:03 UTC
9402 12:26:52.471742 elog_add_boot_reason: Logged dev mode boot
9403 12:26:52.475045 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9404 12:26:52.478337 Finalize devices...
9405 12:26:52.478418 Devices finalized
9406 12:26:52.484944 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9407 12:26:52.488355 Writing coreboot table at 0xffe64000
9408 12:26:52.491786 0. 000000000010a000-0000000000113fff: RAMSTAGE
9409 12:26:52.495112 1. 0000000040000000-00000000400fffff: RAM
9410 12:26:52.498411 2. 0000000040100000-000000004032afff: RAMSTAGE
9411 12:26:52.504666 3. 000000004032b000-00000000545fffff: RAM
9412 12:26:52.508566 4. 0000000054600000-000000005465ffff: BL31
9413 12:26:52.511774 5. 0000000054660000-00000000ffe63fff: RAM
9414 12:26:52.518385 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9415 12:26:52.521140 7. 0000000100000000-000000023fffffff: RAM
9416 12:26:52.521231 Passing 5 GPIOs to payload:
9417 12:26:52.527949 NAME | PORT | POLARITY | VALUE
9418 12:26:52.531175 EC in RW | 0x000000aa | low | undefined
9419 12:26:52.537890 EC interrupt | 0x00000005 | low | undefined
9420 12:26:52.541365 TPM interrupt | 0x000000ab | high | undefined
9421 12:26:52.544445 SD card detect | 0x00000011 | high | undefined
9422 12:26:52.551503 speaker enable | 0x00000093 | high | undefined
9423 12:26:52.554658 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9424 12:26:52.557954 in-header: 03 f9 00 00 02 00 00 00
9425 12:26:52.558041 in-data: 02 00
9426 12:26:52.561157 ADC[4]: Raw value=900959 ID=7
9427 12:26:52.564413 ADC[3]: Raw value=213336 ID=1
9428 12:26:52.567928 RAM Code: 0x71
9429 12:26:52.568015 ADC[6]: Raw value=74557 ID=0
9430 12:26:52.571353 ADC[5]: Raw value=212229 ID=1
9431 12:26:52.571442 SKU Code: 0x1
9432 12:26:52.578166 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9433 12:26:52.580864 coreboot table: 964 bytes.
9434 12:26:52.584278 IMD ROOT 0. 0xfffff000 0x00001000
9435 12:26:52.587756 IMD SMALL 1. 0xffffe000 0x00001000
9436 12:26:52.591134 RO MCACHE 2. 0xffffc000 0x00001104
9437 12:26:52.594523 CONSOLE 3. 0xfff7c000 0x00080000
9438 12:26:52.597822 FMAP 4. 0xfff7b000 0x00000452
9439 12:26:52.601170 TIME STAMP 5. 0xfff7a000 0x00000910
9440 12:26:52.604613 VBOOT WORK 6. 0xfff66000 0x00014000
9441 12:26:52.607263 RAMOOPS 7. 0xffe66000 0x00100000
9442 12:26:52.611314 COREBOOT 8. 0xffe64000 0x00002000
9443 12:26:52.611481 IMD small region:
9444 12:26:52.614391 IMD ROOT 0. 0xffffec00 0x00000400
9445 12:26:52.617224 VPD 1. 0xffffeba0 0x0000004c
9446 12:26:52.620652 MMC STATUS 2. 0xffffeb80 0x00000004
9447 12:26:52.627154 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9448 12:26:52.631216 Probing TPM: done!
9449 12:26:52.633913 Connected to device vid:did:rid of 1ae0:0028:00
9450 12:26:52.644123 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9451 12:26:52.647334 Initialized TPM device CR50 revision 0
9452 12:26:52.651740 Checking cr50 for pending updates
9453 12:26:52.654757 Reading cr50 TPM mode
9454 12:26:52.662996 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9455 12:26:52.669504 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9456 12:26:52.709727 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9457 12:26:52.713213 Checking segment from ROM address 0x40100000
9458 12:26:52.716538 Checking segment from ROM address 0x4010001c
9459 12:26:52.723174 Loading segment from ROM address 0x40100000
9460 12:26:52.723260 code (compression=0)
9461 12:26:52.732593 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9462 12:26:52.739429 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9463 12:26:52.739515 it's not compressed!
9464 12:26:52.746198 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9465 12:26:52.752801 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9466 12:26:52.770029 Loading segment from ROM address 0x4010001c
9467 12:26:52.770142 Entry Point 0x80000000
9468 12:26:52.773261 Loaded segments
9469 12:26:52.777026 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9470 12:26:52.783651 Jumping to boot code at 0x80000000(0xffe64000)
9471 12:26:52.790294 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9472 12:26:52.796915 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9473 12:26:52.804997 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9474 12:26:52.807806 Checking segment from ROM address 0x40100000
9475 12:26:52.811299 Checking segment from ROM address 0x4010001c
9476 12:26:52.818087 Loading segment from ROM address 0x40100000
9477 12:26:52.818173 code (compression=1)
9478 12:26:52.824832 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9479 12:26:52.834662 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9480 12:26:52.834749 using LZMA
9481 12:26:52.842741 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9482 12:26:52.849474 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9483 12:26:52.852734 Loading segment from ROM address 0x4010001c
9484 12:26:52.852819 Entry Point 0x54601000
9485 12:26:52.856640 Loaded segments
9486 12:26:52.860011 NOTICE: MT8192 bl31_setup
9487 12:26:52.866762 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9488 12:26:52.869924 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9489 12:26:52.873466 WARNING: region 0:
9490 12:26:52.876709 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 12:26:52.876796 WARNING: region 1:
9492 12:26:52.883211 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9493 12:26:52.886248 WARNING: region 2:
9494 12:26:52.890170 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9495 12:26:52.893439 WARNING: region 3:
9496 12:26:52.896805 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 12:26:52.899542 WARNING: region 4:
9498 12:26:52.906148 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 12:26:52.906234 WARNING: region 5:
9500 12:26:52.910150 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 12:26:52.912876 WARNING: region 6:
9502 12:26:52.916408 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 12:26:52.919651 WARNING: region 7:
9504 12:26:52.923019 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 12:26:52.929816 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9506 12:26:52.933233 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9507 12:26:52.936513 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9508 12:26:52.943281 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9509 12:26:52.946710 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9510 12:26:52.949457 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9511 12:26:52.956059 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9512 12:26:52.960084 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9513 12:26:52.966743 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9514 12:26:52.969511 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9515 12:26:52.972895 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9516 12:26:52.979934 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9517 12:26:52.983102 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9518 12:26:52.986034 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9519 12:26:52.993112 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9520 12:26:52.996254 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9521 12:26:53.003251 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9522 12:26:53.006641 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9523 12:26:53.010023 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9524 12:26:53.016122 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9525 12:26:53.019516 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9526 12:26:53.022837 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9527 12:26:53.029544 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9528 12:26:53.032882 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9529 12:26:53.039698 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9530 12:26:53.042834 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9531 12:26:53.046230 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9532 12:26:53.053000 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9533 12:26:53.056251 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9534 12:26:53.062932 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9535 12:26:53.066867 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9536 12:26:53.070165 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9537 12:26:53.076320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9538 12:26:53.079761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9539 12:26:53.083135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9540 12:26:53.086435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9541 12:26:53.093322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9542 12:26:53.096845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9543 12:26:53.100109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9544 12:26:53.103338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9545 12:26:53.106600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9546 12:26:53.113592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9547 12:26:53.116930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9548 12:26:53.120362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9549 12:26:53.123014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9550 12:26:53.130356 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9551 12:26:53.133730 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9552 12:26:53.137033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9553 12:26:53.143261 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9554 12:26:53.146427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9555 12:26:53.153366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9556 12:26:53.156784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9557 12:26:53.160046 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9558 12:26:53.166723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9559 12:26:53.170095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9560 12:26:53.176738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9561 12:26:53.180079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9562 12:26:53.183583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9563 12:26:53.190075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9564 12:26:53.193444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9565 12:26:53.200144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9566 12:26:53.203503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9567 12:26:53.210457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9568 12:26:53.213673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9569 12:26:53.220052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9570 12:26:53.223380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9571 12:26:53.226833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9572 12:26:53.233562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9573 12:26:53.236853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9574 12:26:53.243616 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9575 12:26:53.247026 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9576 12:26:53.253442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9577 12:26:53.256853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9578 12:26:53.260366 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9579 12:26:53.266874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9580 12:26:53.270347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9581 12:26:53.276858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9582 12:26:53.280150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9583 12:26:53.286926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9584 12:26:53.290347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9585 12:26:53.293812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9586 12:26:53.300600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9587 12:26:53.303230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9588 12:26:53.309954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9589 12:26:53.313361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9590 12:26:53.320214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9591 12:26:53.323370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9592 12:26:53.327109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9593 12:26:53.333457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9594 12:26:53.336859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9595 12:26:53.343654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9596 12:26:53.346864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9597 12:26:53.353476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9598 12:26:53.357372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9599 12:26:53.360179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9600 12:26:53.366963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9601 12:26:53.370332 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9602 12:26:53.373692 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9603 12:26:53.380425 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9604 12:26:53.383824 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9605 12:26:53.386628 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9606 12:26:53.393418 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9607 12:26:53.396740 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9608 12:26:53.399884 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9609 12:26:53.406613 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9610 12:26:53.409880 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9611 12:26:53.416772 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9612 12:26:53.419960 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9613 12:26:53.423731 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9614 12:26:53.430146 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9615 12:26:53.433265 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9616 12:26:53.440042 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9617 12:26:53.443316 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9618 12:26:53.446692 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9619 12:26:53.453362 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9620 12:26:53.456905 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9621 12:26:53.460142 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9622 12:26:53.466266 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9623 12:26:53.469715 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9624 12:26:53.473189 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9625 12:26:53.480056 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9626 12:26:53.483474 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9627 12:26:53.486861 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9628 12:26:53.490258 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9629 12:26:53.496962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9630 12:26:53.500345 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9631 12:26:53.503698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9632 12:26:53.510137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9633 12:26:53.513555 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9634 12:26:53.520284 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9635 12:26:53.523735 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9636 12:26:53.526979 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9637 12:26:53.533326 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9638 12:26:53.536485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9639 12:26:53.543566 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9640 12:26:53.546973 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9641 12:26:53.550413 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9642 12:26:53.556496 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9643 12:26:53.559899 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9644 12:26:53.566393 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9645 12:26:53.569793 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9646 12:26:53.573180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9647 12:26:53.580011 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9648 12:26:53.583135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9649 12:26:53.586711 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9650 12:26:53.593642 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9651 12:26:53.596913 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9652 12:26:53.603619 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9653 12:26:53.606889 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9654 12:26:53.610118 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9655 12:26:53.617282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9656 12:26:53.620567 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9657 12:26:53.623279 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9658 12:26:53.629864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9659 12:26:53.633207 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9660 12:26:53.640259 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9661 12:26:53.643295 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9662 12:26:53.646577 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9663 12:26:53.653739 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9664 12:26:53.657195 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9665 12:26:53.663287 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9666 12:26:53.666715 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9667 12:26:53.669987 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9668 12:26:53.676787 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9669 12:26:53.680011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9670 12:26:53.683540 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9671 12:26:53.690232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9672 12:26:53.692967 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9673 12:26:53.700177 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9674 12:26:53.702938 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9675 12:26:53.709933 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9676 12:26:53.713209 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9677 12:26:53.716402 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9678 12:26:53.722824 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9679 12:26:53.726294 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9680 12:26:53.729685 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9681 12:26:53.736295 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9682 12:26:53.739630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9683 12:26:53.746344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9684 12:26:53.749345 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9685 12:26:53.753343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9686 12:26:53.759599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9687 12:26:53.763046 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9688 12:26:53.769259 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9689 12:26:53.772680 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9690 12:26:53.775955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9691 12:26:53.782491 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9692 12:26:53.785935 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9693 12:26:53.792652 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9694 12:26:53.795993 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9695 12:26:53.799452 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9696 12:26:53.806085 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9697 12:26:53.809071 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9698 12:26:53.815625 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9699 12:26:53.819008 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9700 12:26:53.825947 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9701 12:26:53.829605 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9702 12:26:53.832521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9703 12:26:53.839257 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9704 12:26:53.842707 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9705 12:26:53.849004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9706 12:26:53.852219 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9707 12:26:53.855281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9708 12:26:53.862689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9709 12:26:53.866023 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9710 12:26:53.872127 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9711 12:26:53.875431 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9712 12:26:53.882090 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9713 12:26:53.885399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9714 12:26:53.888890 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9715 12:26:53.895239 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9716 12:26:53.898640 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9717 12:26:53.905434 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9718 12:26:53.908778 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9719 12:26:53.912223 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9720 12:26:53.918379 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9721 12:26:53.921515 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9722 12:26:53.928799 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9723 12:26:53.931999 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9724 12:26:53.938657 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9725 12:26:53.942155 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9726 12:26:53.945436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9727 12:26:53.951514 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9728 12:26:53.955087 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9729 12:26:53.961387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9730 12:26:53.964850 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9731 12:26:53.971418 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9732 12:26:53.974706 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9733 12:26:53.978004 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9734 12:26:53.984746 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9735 12:26:53.988196 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9736 12:26:53.991430 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9737 12:26:53.994685 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9738 12:26:53.998134 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9739 12:26:54.004912 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9740 12:26:54.007680 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9741 12:26:54.014296 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9742 12:26:54.017719 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9743 12:26:54.021093 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9744 12:26:54.027677 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9745 12:26:54.031236 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9746 12:26:54.034403 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9747 12:26:54.041677 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9748 12:26:54.045076 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9749 12:26:54.050966 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9750 12:26:54.054469 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9751 12:26:54.057894 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9752 12:26:54.064487 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9753 12:26:54.067849 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9754 12:26:54.071333 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9755 12:26:54.078009 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9756 12:26:54.080699 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9757 12:26:54.087472 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9758 12:26:54.090806 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9759 12:26:54.094327 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9760 12:26:54.101079 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9761 12:26:54.104494 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9762 12:26:54.107794 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9763 12:26:54.114667 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9764 12:26:54.117191 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9765 12:26:54.120596 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9766 12:26:54.127274 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9767 12:26:54.130677 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9768 12:26:54.134158 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9769 12:26:54.140994 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9770 12:26:54.143993 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9771 12:26:54.150692 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9772 12:26:54.154026 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9773 12:26:54.157456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9774 12:26:54.160753 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9775 12:26:54.167678 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9776 12:26:54.170721 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9777 12:26:54.174023 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9778 12:26:54.177354 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9779 12:26:54.184019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9780 12:26:54.187299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9781 12:26:54.190679 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9782 12:26:54.194063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9783 12:26:54.200874 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9784 12:26:54.203551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9785 12:26:54.207115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9786 12:26:54.210381 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9787 12:26:54.217287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9788 12:26:54.220694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9789 12:26:54.227026 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9790 12:26:54.230476 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9791 12:26:54.237184 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9792 12:26:54.240536 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9793 12:26:54.243827 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9794 12:26:54.250427 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9795 12:26:54.253598 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9796 12:26:54.260302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9797 12:26:54.263751 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9798 12:26:54.269802 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9799 12:26:54.273415 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9800 12:26:54.276671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9801 12:26:54.283247 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9802 12:26:54.286618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9803 12:26:54.289962 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9804 12:26:54.296498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9805 12:26:54.300494 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9806 12:26:54.307193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9807 12:26:54.309967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9808 12:26:54.316695 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9809 12:26:54.320126 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9810 12:26:54.323423 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9811 12:26:54.329942 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9812 12:26:54.333276 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9813 12:26:54.339839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9814 12:26:54.343297 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9815 12:26:54.346779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9816 12:26:54.353335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9817 12:26:54.356566 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9818 12:26:54.359898 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9819 12:26:54.366585 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9820 12:26:54.370069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9821 12:26:54.376844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9822 12:26:54.380054 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9823 12:26:54.386747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9824 12:26:54.389963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9825 12:26:54.393226 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9826 12:26:54.399998 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9827 12:26:54.403320 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9828 12:26:54.409968 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9829 12:26:54.413550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9830 12:26:54.416864 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9831 12:26:54.423722 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9832 12:26:54.427051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9833 12:26:54.433194 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9834 12:26:54.437023 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9835 12:26:54.440377 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9836 12:26:54.446421 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9837 12:26:54.449813 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9838 12:26:54.456618 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9839 12:26:54.459775 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9840 12:26:54.462913 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9841 12:26:54.469681 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9842 12:26:54.473194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9843 12:26:54.479969 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9844 12:26:54.483220 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9845 12:26:54.486738 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9846 12:26:54.493298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9847 12:26:54.496463 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9848 12:26:54.503163 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9849 12:26:54.506500 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9850 12:26:54.509980 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9851 12:26:54.515979 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9852 12:26:54.519488 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9853 12:26:54.526365 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9854 12:26:54.529073 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9855 12:26:54.535896 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9856 12:26:54.539233 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9857 12:26:54.543007 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9858 12:26:54.549298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9859 12:26:54.552709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9860 12:26:54.559723 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9861 12:26:54.563176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9862 12:26:54.569756 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9863 12:26:54.573171 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9864 12:26:54.575941 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9865 12:26:54.582815 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9866 12:26:54.586261 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9867 12:26:54.592677 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9868 12:26:54.596426 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9869 12:26:54.602656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9870 12:26:54.606157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9871 12:26:54.612285 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9872 12:26:54.615703 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9873 12:26:54.619511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9874 12:26:54.625576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9875 12:26:54.629059 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9876 12:26:54.635802 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9877 12:26:54.639221 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9878 12:26:54.645854 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9879 12:26:54.649067 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9880 12:26:54.652606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9881 12:26:54.659443 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9882 12:26:54.662166 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9883 12:26:54.668782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9884 12:26:54.672135 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9885 12:26:54.678649 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9886 12:26:54.682145 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9887 12:26:54.685560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9888 12:26:54.692208 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9889 12:26:54.695446 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9890 12:26:54.701905 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9891 12:26:54.705309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9892 12:26:54.712102 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9893 12:26:54.715405 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9894 12:26:54.718668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9895 12:26:54.725345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9896 12:26:54.728826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9897 12:26:54.735596 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9898 12:26:54.738971 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9899 12:26:54.745602 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9900 12:26:54.748293 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9901 12:26:54.752288 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9902 12:26:54.758690 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9903 12:26:54.762221 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9904 12:26:54.768356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9905 12:26:54.771605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9906 12:26:54.778692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9907 12:26:54.782130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9908 12:26:54.785030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9909 12:26:54.791777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9910 12:26:54.795165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9911 12:26:54.801620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9912 12:26:54.805015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9913 12:26:54.811649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9914 12:26:54.814833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9915 12:26:54.821699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9916 12:26:54.825132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9917 12:26:54.831773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9918 12:26:54.834613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9919 12:26:54.841287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9920 12:26:54.844753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9921 12:26:54.851673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9922 12:26:54.854730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9923 12:26:54.861546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9924 12:26:54.864711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9925 12:26:54.871628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9926 12:26:54.875097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9927 12:26:54.878257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9928 12:26:54.884820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9929 12:26:54.891651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9930 12:26:54.895125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9931 12:26:54.901096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9932 12:26:54.904773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9933 12:26:54.911225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9934 12:26:54.914667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9935 12:26:54.921463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9936 12:26:54.924746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9937 12:26:54.931501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9938 12:26:54.934692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9939 12:26:54.938032 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9940 12:26:54.941009 INFO: [APUAPC] vio 0
9941 12:26:54.943922 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9942 12:26:54.950894 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9943 12:26:54.953825 INFO: [APUAPC] D0_APC_0: 0x400510
9944 12:26:54.957445 INFO: [APUAPC] D0_APC_1: 0x0
9945 12:26:54.960918 INFO: [APUAPC] D0_APC_2: 0x1540
9946 12:26:54.961019 INFO: [APUAPC] D0_APC_3: 0x0
9947 12:26:54.963889 INFO: [APUAPC] D1_APC_0: 0xffffffff
9948 12:26:54.970902 INFO: [APUAPC] D1_APC_1: 0xffffffff
9949 12:26:54.971053 INFO: [APUAPC] D1_APC_2: 0x3fffff
9950 12:26:54.973884 INFO: [APUAPC] D1_APC_3: 0x0
9951 12:26:54.977270 INFO: [APUAPC] D2_APC_0: 0xffffffff
9952 12:26:54.980837 INFO: [APUAPC] D2_APC_1: 0xffffffff
9953 12:26:54.984235 INFO: [APUAPC] D2_APC_2: 0x3fffff
9954 12:26:54.987453 INFO: [APUAPC] D2_APC_3: 0x0
9955 12:26:54.990152 INFO: [APUAPC] D3_APC_0: 0xffffffff
9956 12:26:54.993662 INFO: [APUAPC] D3_APC_1: 0xffffffff
9957 12:26:54.997332 INFO: [APUAPC] D3_APC_2: 0x3fffff
9958 12:26:55.000159 INFO: [APUAPC] D3_APC_3: 0x0
9959 12:26:55.003541 INFO: [APUAPC] D4_APC_0: 0xffffffff
9960 12:26:55.006994 INFO: [APUAPC] D4_APC_1: 0xffffffff
9961 12:26:55.010495 INFO: [APUAPC] D4_APC_2: 0x3fffff
9962 12:26:55.013957 INFO: [APUAPC] D4_APC_3: 0x0
9963 12:26:55.016827 INFO: [APUAPC] D5_APC_0: 0xffffffff
9964 12:26:55.020702 INFO: [APUAPC] D5_APC_1: 0xffffffff
9965 12:26:55.023544 INFO: [APUAPC] D5_APC_2: 0x3fffff
9966 12:26:55.027119 INFO: [APUAPC] D5_APC_3: 0x0
9967 12:26:55.030670 INFO: [APUAPC] D6_APC_0: 0xffffffff
9968 12:26:55.033351 INFO: [APUAPC] D6_APC_1: 0xffffffff
9969 12:26:55.036843 INFO: [APUAPC] D6_APC_2: 0x3fffff
9970 12:26:55.040326 INFO: [APUAPC] D6_APC_3: 0x0
9971 12:26:55.043758 INFO: [APUAPC] D7_APC_0: 0xffffffff
9972 12:26:55.046590 INFO: [APUAPC] D7_APC_1: 0xffffffff
9973 12:26:55.050141 INFO: [APUAPC] D7_APC_2: 0x3fffff
9974 12:26:55.053582 INFO: [APUAPC] D7_APC_3: 0x0
9975 12:26:55.057025 INFO: [APUAPC] D8_APC_0: 0xffffffff
9976 12:26:55.060558 INFO: [APUAPC] D8_APC_1: 0xffffffff
9977 12:26:55.063942 INFO: [APUAPC] D8_APC_2: 0x3fffff
9978 12:26:55.066704 INFO: [APUAPC] D8_APC_3: 0x0
9979 12:26:55.069947 INFO: [APUAPC] D9_APC_0: 0xffffffff
9980 12:26:55.073284 INFO: [APUAPC] D9_APC_1: 0xffffffff
9981 12:26:55.076758 INFO: [APUAPC] D9_APC_2: 0x3fffff
9982 12:26:55.080190 INFO: [APUAPC] D9_APC_3: 0x0
9983 12:26:55.083517 INFO: [APUAPC] D10_APC_0: 0xffffffff
9984 12:26:55.086858 INFO: [APUAPC] D10_APC_1: 0xffffffff
9985 12:26:55.090068 INFO: [APUAPC] D10_APC_2: 0x3fffff
9986 12:26:55.093362 INFO: [APUAPC] D10_APC_3: 0x0
9987 12:26:55.096892 INFO: [APUAPC] D11_APC_0: 0xffffffff
9988 12:26:55.100370 INFO: [APUAPC] D11_APC_1: 0xffffffff
9989 12:26:55.103797 INFO: [APUAPC] D11_APC_2: 0x3fffff
9990 12:26:55.106434 INFO: [APUAPC] D11_APC_3: 0x0
9991 12:26:55.109954 INFO: [APUAPC] D12_APC_0: 0xffffffff
9992 12:26:55.113344 INFO: [APUAPC] D12_APC_1: 0xffffffff
9993 12:26:55.116506 INFO: [APUAPC] D12_APC_2: 0x3fffff
9994 12:26:55.120005 INFO: [APUAPC] D12_APC_3: 0x0
9995 12:26:55.123101 INFO: [APUAPC] D13_APC_0: 0xffffffff
9996 12:26:55.126557 INFO: [APUAPC] D13_APC_1: 0xffffffff
9997 12:26:55.129939 INFO: [APUAPC] D13_APC_2: 0x3fffff
9998 12:26:55.133321 INFO: [APUAPC] D13_APC_3: 0x0
9999 12:26:55.136690 INFO: [APUAPC] D14_APC_0: 0xffffffff
10000 12:26:55.140093 INFO: [APUAPC] D14_APC_1: 0xffffffff
10001 12:26:55.143260 INFO: [APUAPC] D14_APC_2: 0x3fffff
10002 12:26:55.146841 INFO: [APUAPC] D14_APC_3: 0x0
10003 12:26:55.150048 INFO: [APUAPC] D15_APC_0: 0xffffffff
10004 12:26:55.153467 INFO: [APUAPC] D15_APC_1: 0xffffffff
10005 12:26:55.156322 INFO: [APUAPC] D15_APC_2: 0x3fffff
10006 12:26:55.159687 INFO: [APUAPC] D15_APC_3: 0x0
10007 12:26:55.163184 INFO: [APUAPC] APC_CON: 0x4
10008 12:26:55.166415 INFO: [NOCDAPC] D0_APC_0: 0x0
10009 12:26:55.169974 INFO: [NOCDAPC] D0_APC_1: 0x0
10010 12:26:55.170062 INFO: [NOCDAPC] D1_APC_0: 0x0
10011 12:26:55.173353 INFO: [NOCDAPC] D1_APC_1: 0xfff
10012 12:26:55.176563 INFO: [NOCDAPC] D2_APC_0: 0x0
10013 12:26:55.179837 INFO: [NOCDAPC] D2_APC_1: 0xfff
10014 12:26:55.183160 INFO: [NOCDAPC] D3_APC_0: 0x0
10015 12:26:55.186538 INFO: [NOCDAPC] D3_APC_1: 0xfff
10016 12:26:55.190016 INFO: [NOCDAPC] D4_APC_0: 0x0
10017 12:26:55.193310 INFO: [NOCDAPC] D4_APC_1: 0xfff
10018 12:26:55.196608 INFO: [NOCDAPC] D5_APC_0: 0x0
10019 12:26:55.199808 INFO: [NOCDAPC] D5_APC_1: 0xfff
10020 12:26:55.199894 INFO: [NOCDAPC] D6_APC_0: 0x0
10021 12:26:55.203220 INFO: [NOCDAPC] D6_APC_1: 0xfff
10022 12:26:55.206598 INFO: [NOCDAPC] D7_APC_0: 0x0
10023 12:26:55.209929 INFO: [NOCDAPC] D7_APC_1: 0xfff
10024 12:26:55.213354 INFO: [NOCDAPC] D8_APC_0: 0x0
10025 12:26:55.216569 INFO: [NOCDAPC] D8_APC_1: 0xfff
10026 12:26:55.219731 INFO: [NOCDAPC] D9_APC_0: 0x0
10027 12:26:55.223238 INFO: [NOCDAPC] D9_APC_1: 0xfff
10028 12:26:55.226423 INFO: [NOCDAPC] D10_APC_0: 0x0
10029 12:26:55.229881 INFO: [NOCDAPC] D10_APC_1: 0xfff
10030 12:26:55.232798 INFO: [NOCDAPC] D11_APC_0: 0x0
10031 12:26:55.236194 INFO: [NOCDAPC] D11_APC_1: 0xfff
10032 12:26:55.236278 INFO: [NOCDAPC] D12_APC_0: 0x0
10033 12:26:55.239634 INFO: [NOCDAPC] D12_APC_1: 0xfff
10034 12:26:55.243063 INFO: [NOCDAPC] D13_APC_0: 0x0
10035 12:26:55.246290 INFO: [NOCDAPC] D13_APC_1: 0xfff
10036 12:26:55.249506 INFO: [NOCDAPC] D14_APC_0: 0x0
10037 12:26:55.252994 INFO: [NOCDAPC] D14_APC_1: 0xfff
10038 12:26:55.256353 INFO: [NOCDAPC] D15_APC_0: 0x0
10039 12:26:55.259798 INFO: [NOCDAPC] D15_APC_1: 0xfff
10040 12:26:55.263142 INFO: [NOCDAPC] APC_CON: 0x4
10041 12:26:55.266634 INFO: [APUAPC] set_apusys_apc done
10042 12:26:55.269403 INFO: [DEVAPC] devapc_init done
10043 12:26:55.272789 INFO: GICv3 without legacy support detected.
10044 12:26:55.276248 INFO: ARM GICv3 driver initialized in EL3
10045 12:26:55.279614 INFO: Maximum SPI INTID supported: 639
10046 12:26:55.286183 INFO: BL31: Initializing runtime services
10047 12:26:55.289643 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10048 12:26:55.293046 INFO: SPM: enable CPC mode
10049 12:26:55.299836 INFO: mcdi ready for mcusys-off-idle and system suspend
10050 12:26:55.303296 INFO: BL31: Preparing for EL3 exit to normal world
10051 12:26:55.305935 INFO: Entry point address = 0x80000000
10052 12:26:55.309372 INFO: SPSR = 0x8
10053 12:26:55.314711
10054 12:26:55.314854
10055 12:26:55.314948
10056 12:26:55.318052 Starting depthcharge on Spherion...
10057 12:26:55.318161
10058 12:26:55.318256 Wipe memory regions:
10059 12:26:55.318346
10060 12:26:55.319170 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10061 12:26:55.319298 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10062 12:26:55.319449 Setting prompt string to ['asurada:']
10063 12:26:55.319545 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10064 12:26:55.320744 [0x00000040000000, 0x00000054600000)
10065 12:26:55.443315
10066 12:26:55.443462 [0x00000054660000, 0x00000080000000)
10067 12:26:55.704124
10068 12:26:55.704878 [0x000000821a7280, 0x000000ffe64000)
10069 12:26:56.448992
10070 12:26:56.449224 [0x00000100000000, 0x00000240000000)
10071 12:26:58.339393
10072 12:26:58.342437 Initializing XHCI USB controller at 0x11200000.
10073 12:26:59.380380
10074 12:26:59.383691 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10075 12:26:59.383804
10076 12:26:59.383894
10077 12:26:59.383978
10078 12:26:59.384292 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 12:26:59.484864 asurada: tftpboot 192.168.201.1 10605768/tftp-deploy-w2z48eio/kernel/image.itb 10605768/tftp-deploy-w2z48eio/kernel/cmdline
10081 12:26:59.485459 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10082 12:26:59.485986 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10083 12:26:59.490124 tftpboot 192.168.201.1 10605768/tftp-deploy-w2z48eio/kernel/image.itp-deploy-w2z48eio/kernel/cmdline
10084 12:26:59.490572
10085 12:26:59.490919 Waiting for link
10086 12:26:59.650554
10087 12:26:59.651061 R8152: Initializing
10088 12:26:59.651428
10089 12:26:59.653843 Version 6 (ocp_data = 5c30)
10090 12:26:59.654279
10091 12:26:59.657093 R8152: Done initializing
10092 12:26:59.657529
10093 12:26:59.657915 Adding net device
10094 12:27:01.575098
10095 12:27:01.575744 done.
10096 12:27:01.576110
10097 12:27:01.576433 MAC: 00:24:32:30:78:52
10098 12:27:01.576744
10099 12:27:01.577728 Sending DHCP discover... done.
10100 12:27:01.578163
10101 12:27:02.440877 Waiting for reply... done.
10102 12:27:02.441391
10103 12:27:02.441746 Sending DHCP request... done.
10104 12:27:02.449842
10105 12:27:02.460380 Waiting for reply... done.
10106 12:27:02.461187
10107 12:27:02.461800 My ip is 192.168.201.14
10108 12:27:02.462353
10109 12:27:02.501269 The DHCP server ip is 192.168.201.1
10110 12:27:02.501460
10111 12:27:02.501796 TFTP server IP predefined by user: 192.168.201.1
10112 12:27:02.501913
10113 12:27:02.502013 Bootfile predefined by user: 10605768/tftp-deploy-w2z48eio/kernel/image.itb
10114 12:27:02.502119
10115 12:27:02.502213 Sending tftp read request... done.
10116 12:27:02.502309
10117 12:27:02.502407 Waiting for the transfer...
10118 12:27:02.502496
10119 12:27:03.006313 00000000 ################################################################
10120 12:27:03.006477
10121 12:27:03.524396 00080000 ################################################################
10122 12:27:03.524561
10123 12:27:04.038317 00100000 ################################################################
10124 12:27:04.038487
10125 12:27:04.553180 00180000 ################################################################
10126 12:27:04.553324
10127 12:27:05.068810 00200000 ################################################################
10128 12:27:05.068962
10129 12:27:05.583579 00280000 ################################################################
10130 12:27:05.583756
10131 12:27:06.099149 00300000 ################################################################
10132 12:27:06.099315
10133 12:27:06.615022 00380000 ################################################################
10134 12:27:06.615199
10135 12:27:07.127453 00400000 ################################################################
10136 12:27:07.127601
10137 12:27:07.637480 00480000 ################################################################
10138 12:27:07.637654
10139 12:27:08.161183 00500000 ################################################################
10140 12:27:08.161332
10141 12:27:08.682769 00580000 ################################################################
10142 12:27:08.682953
10143 12:27:09.207342 00600000 ################################################################
10144 12:27:09.207492
10145 12:27:09.733769 00680000 ################################################################
10146 12:27:09.733943
10147 12:27:10.258572 00700000 ################################################################
10148 12:27:10.258742
10149 12:27:10.779248 00780000 ################################################################
10150 12:27:10.779421
10151 12:27:11.310303 00800000 ################################################################
10152 12:27:11.310471
10153 12:27:11.842386 00880000 ################################################################
10154 12:27:11.842535
10155 12:27:12.368006 00900000 ################################################################
10156 12:27:12.368142
10157 12:27:12.891838 00980000 ################################################################
10158 12:27:12.891976
10159 12:27:13.423993 00a00000 ################################################################
10160 12:27:13.424134
10161 12:27:13.952668 00a80000 ################################################################
10162 12:27:13.952811
10163 12:27:14.478991 00b00000 ################################################################
10164 12:27:14.479134
10165 12:27:15.005754 00b80000 ################################################################
10166 12:27:15.005944
10167 12:27:15.545549 00c00000 ################################################################
10168 12:27:15.545687
10169 12:27:16.071957 00c80000 ################################################################
10170 12:27:16.072093
10171 12:27:16.651471 00d00000 ################################################################
10172 12:27:16.651619
10173 12:27:17.200221 00d80000 ################################################################
10174 12:27:17.200379
10175 12:27:17.739189 00e00000 ################################################################
10176 12:27:17.739329
10177 12:27:18.269885 00e80000 ################################################################
10178 12:27:18.270061
10179 12:27:18.797341 00f00000 ################################################################
10180 12:27:18.797484
10181 12:27:19.323050 00f80000 ################################################################
10182 12:27:19.323192
10183 12:27:19.863428 01000000 ################################################################
10184 12:27:19.863575
10185 12:27:20.406969 01080000 ################################################################
10186 12:27:20.407189
10187 12:27:20.946085 01100000 ################################################################
10188 12:27:20.946218
10189 12:27:21.595446 01180000 ################################################################
10190 12:27:21.595972
10191 12:27:22.203562 01200000 ################################################################
10192 12:27:22.204144
10193 12:27:22.820765 01280000 ################################################################
10194 12:27:22.820941
10195 12:27:23.442889 01300000 ################################################################
10196 12:27:23.443178
10197 12:27:24.084849 01380000 ################################################################
10198 12:27:24.085586
10199 12:27:24.729145 01400000 ################################################################
10200 12:27:24.729671
10201 12:27:25.377814 01480000 ################################################################
10202 12:27:25.378323
10203 12:27:26.043166 01500000 ################################################################
10204 12:27:26.043849
10205 12:27:26.743854 01580000 ################################################################
10206 12:27:26.744385
10207 12:27:27.470652 01600000 ################################################################
10208 12:27:27.471231
10209 12:27:28.157684 01680000 ################################################################
10210 12:27:28.158239
10211 12:27:28.829718 01700000 ################################################################
10212 12:27:28.830508
10213 12:27:29.466797 01780000 ################################################################
10214 12:27:29.467281
10215 12:27:30.091207 01800000 ################################################################
10216 12:27:30.091840
10217 12:27:30.744849 01880000 ################################################################
10218 12:27:30.745558
10219 12:27:31.398595 01900000 ################################################################
10220 12:27:31.399102
10221 12:27:32.044218 01980000 ################################################################
10222 12:27:32.044757
10223 12:27:32.626597 01a00000 ################################################################
10224 12:27:32.626839
10225 12:27:33.218097 01a80000 ################################################################
10226 12:27:33.218244
10227 12:27:33.806764 01b00000 ################################################################
10228 12:27:33.806908
10229 12:27:34.340986 01b80000 ################################################################
10230 12:27:34.341151
10231 12:27:34.890114 01c00000 ################################################################
10232 12:27:34.890257
10233 12:27:35.437780 01c80000 ################################################################
10234 12:27:35.437920
10235 12:27:35.979926 01d00000 ################################################################
10236 12:27:35.980073
10237 12:27:36.419306 01d80000 #################################################### done.
10238 12:27:36.419475
10239 12:27:36.422617 The bootfile was 31356578 bytes long.
10240 12:27:36.422706
10241 12:27:36.425928 Sending tftp read request... done.
10242 12:27:36.426086
10243 12:27:36.426245 Waiting for the transfer...
10244 12:27:36.426417
10245 12:27:36.428995 00000000 # done.
10246 12:27:36.429134
10247 12:27:36.435998 Command line loaded dynamically from TFTP file: 10605768/tftp-deploy-w2z48eio/kernel/cmdline
10248 12:27:36.436086
10249 12:27:36.449136 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10250 12:27:36.449244
10251 12:27:36.449327 Loading FIT.
10252 12:27:36.449390
10253 12:27:36.452396 Image ramdisk-1 has 21220870 bytes.
10254 12:27:36.452529
10255 12:27:36.455416 Image fdt-1 has 46924 bytes.
10256 12:27:36.455494
10257 12:27:36.458994 Image kernel-1 has 10086749 bytes.
10258 12:27:36.459094
10259 12:27:36.465881 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 12:27:36.465975
10261 12:27:36.485295 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 12:27:36.485392
10263 12:27:36.489213 Choosing best match conf-1 for compat google,spherion-rev2.
10264 12:27:36.493695
10265 12:27:36.498116 Connected to device vid:did:rid of 1ae0:0028:00
10266 12:27:36.505712
10267 12:27:36.509011 tpm_get_response: command 0x17b, return code 0x0
10268 12:27:36.509101
10269 12:27:36.512265 ec_init: CrosEC protocol v3 supported (256, 248)
10270 12:27:36.516068
10271 12:27:36.519379 tpm_cleanup: add release locality here.
10272 12:27:36.519481
10273 12:27:36.519567 Shutting down all USB controllers.
10274 12:27:36.522608
10275 12:27:36.522710 Removing current net device
10276 12:27:36.522798
10277 12:27:36.529091 Exiting depthcharge with code 4 at timestamp: 70607129
10278 12:27:36.529179
10279 12:27:36.532929 LZMA decompressing kernel-1 to 0x821a6718
10280 12:27:36.533023
10281 12:27:36.536134 LZMA decompressing kernel-1 to 0x40000000
10282 12:27:37.802687
10283 12:27:37.802870 jumping to kernel
10284 12:27:37.803652 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10285 12:27:37.803796 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10286 12:27:37.803965 Setting prompt string to ['Linux version [0-9]']
10287 12:27:37.804127 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 12:27:37.804243 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 12:27:37.884790
10290 12:27:37.888038 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 12:27:37.891510 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10292 12:27:37.891610 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 12:27:37.891707 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10294 12:27:37.891803 Using line separator: #'\n'#
10295 12:27:37.891867 No login prompt set.
10296 12:27:37.891948 Parsing kernel messages
10297 12:27:37.892012 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10298 12:27:37.892125 [login-action] Waiting for messages, (timeout 00:03:43)
10299 12:27:37.910999 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10300 12:27:37.914242 [ 0.000000] random: crng init done
10301 12:27:37.921291 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10302 12:27:37.921412 [ 0.000000] efi: UEFI not found.
10303 12:27:37.931038 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10304 12:27:37.938138 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10305 12:27:37.947677 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10306 12:27:37.957795 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10307 12:27:37.964161 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10308 12:27:37.967906 [ 0.000000] printk: bootconsole [mtk8250] enabled
10309 12:27:37.976783 [ 0.000000] NUMA: No NUMA configuration found
10310 12:27:37.983070 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10311 12:27:37.989962 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10312 12:27:37.990055 [ 0.000000] Zone ranges:
10313 12:27:37.996394 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10314 12:27:37.999490 [ 0.000000] DMA32 empty
10315 12:27:38.006661 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10316 12:27:38.009866 [ 0.000000] Movable zone start for each node
10317 12:27:38.013041 [ 0.000000] Early memory node ranges
10318 12:27:38.020072 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10319 12:27:38.026531 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10320 12:27:38.033022 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10321 12:27:38.039673 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10322 12:27:38.046123 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10323 12:27:38.052888 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10324 12:27:38.108961 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10325 12:27:38.115529 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10326 12:27:38.122497 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10327 12:27:38.125658 [ 0.000000] psci: probing for conduit method from DT.
10328 12:27:38.132103 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10329 12:27:38.135429 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10330 12:27:38.141895 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10331 12:27:38.145743 [ 0.000000] psci: SMC Calling Convention v1.2
10332 12:27:38.152040 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10333 12:27:38.155605 [ 0.000000] Detected VIPT I-cache on CPU0
10334 12:27:38.162020 [ 0.000000] CPU features: detected: GIC system register CPU interface
10335 12:27:38.168564 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10336 12:27:38.175587 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10337 12:27:38.181963 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10338 12:27:38.188358 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10339 12:27:38.198512 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10340 12:27:38.201637 [ 0.000000] alternatives: applying boot alternatives
10341 12:27:38.208149 [ 0.000000] Fallback order for Node 0: 0
10342 12:27:38.215357 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10343 12:27:38.218607 [ 0.000000] Policy zone: Normal
10344 12:27:38.228132 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10345 12:27:38.238445 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10346 12:27:38.250178 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10347 12:27:38.259574 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10348 12:27:38.266624 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10349 12:27:38.269790 <6>[ 0.000000] software IO TLB: area num 8.
10350 12:27:38.326664 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10351 12:27:38.475811 <6>[ 0.000000] Memory: 7952216K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400552K reserved, 32768K cma-reserved)
10352 12:27:38.482542 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10353 12:27:38.489057 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10354 12:27:38.492603 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10355 12:27:38.498899 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10356 12:27:38.505871 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10357 12:27:38.509087 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10358 12:27:38.518824 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10359 12:27:38.525292 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10360 12:27:38.529178 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10361 12:27:38.536840 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10362 12:27:38.540061 <6>[ 0.000000] GICv3: 608 SPIs implemented
10363 12:27:38.546729 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10364 12:27:38.549979 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10365 12:27:38.553218 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10366 12:27:38.563582 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10367 12:27:38.573347 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10368 12:27:38.586288 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10369 12:27:38.593481 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10370 12:27:38.602126 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10371 12:27:38.615722 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10372 12:27:38.622155 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10373 12:27:38.628623 <6>[ 0.009178] Console: colour dummy device 80x25
10374 12:27:38.638965 <6>[ 0.013934] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10375 12:27:38.645489 <6>[ 0.024441] pid_max: default: 32768 minimum: 301
10376 12:27:38.648803 <6>[ 0.029344] LSM: Security Framework initializing
10377 12:27:38.655484 <6>[ 0.034313] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10378 12:27:38.665277 <6>[ 0.042175] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10379 12:27:38.674950 <6>[ 0.051654] cblist_init_generic: Setting adjustable number of callback queues.
10380 12:27:38.678830 <6>[ 0.059105] cblist_init_generic: Setting shift to 3 and lim to 1.
10381 12:27:38.685050 <6>[ 0.065484] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 12:27:38.692015 <6>[ 0.071892] rcu: Hierarchical SRCU implementation.
10383 12:27:38.698398 <6>[ 0.076937] rcu: Max phase no-delay instances is 1000.
10384 12:27:38.705092 <6>[ 0.083957] EFI services will not be available.
10385 12:27:38.708506 <6>[ 0.088923] smp: Bringing up secondary CPUs ...
10386 12:27:38.715906 <6>[ 0.094004] Detected VIPT I-cache on CPU1
10387 12:27:38.722296 <6>[ 0.094077] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10388 12:27:38.728895 <6>[ 0.094110] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10389 12:27:38.732158 <6>[ 0.094430] Detected VIPT I-cache on CPU2
10390 12:27:38.739273 <6>[ 0.094472] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10391 12:27:38.749131 <6>[ 0.094487] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10392 12:27:38.752381 <6>[ 0.094733] Detected VIPT I-cache on CPU3
10393 12:27:38.758511 <6>[ 0.094779] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10394 12:27:38.765085 <6>[ 0.094793] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10395 12:27:38.768370 <6>[ 0.095097] CPU features: detected: Spectre-v4
10396 12:27:38.775618 <6>[ 0.095104] CPU features: detected: Spectre-BHB
10397 12:27:38.778810 <6>[ 0.095110] Detected PIPT I-cache on CPU4
10398 12:27:38.785027 <6>[ 0.095167] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10399 12:27:38.791945 <6>[ 0.095183] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10400 12:27:38.798304 <6>[ 0.095478] Detected PIPT I-cache on CPU5
10401 12:27:38.804959 <6>[ 0.095542] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10402 12:27:38.811259 <6>[ 0.095559] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10403 12:27:38.815130 <6>[ 0.095842] Detected PIPT I-cache on CPU6
10404 12:27:38.821561 <6>[ 0.095907] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10405 12:27:38.828437 <6>[ 0.095923] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10406 12:27:38.834957 <6>[ 0.096222] Detected PIPT I-cache on CPU7
10407 12:27:38.841327 <6>[ 0.096287] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10408 12:27:38.847896 <6>[ 0.096303] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10409 12:27:38.851138 <6>[ 0.096349] smp: Brought up 1 node, 8 CPUs
10410 12:27:38.857748 <6>[ 0.237687] SMP: Total of 8 processors activated.
10411 12:27:38.861633 <6>[ 0.242608] CPU features: detected: 32-bit EL0 Support
10412 12:27:38.871435 <6>[ 0.247972] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10413 12:27:38.878092 <6>[ 0.256772] CPU features: detected: Common not Private translations
10414 12:27:38.884999 <6>[ 0.263247] CPU features: detected: CRC32 instructions
10415 12:27:38.888185 <6>[ 0.268632] CPU features: detected: RCpc load-acquire (LDAPR)
10416 12:27:38.894636 <6>[ 0.274592] CPU features: detected: LSE atomic instructions
10417 12:27:38.900875 <6>[ 0.280373] CPU features: detected: Privileged Access Never
10418 12:27:38.907774 <6>[ 0.286189] CPU features: detected: RAS Extension Support
10419 12:27:38.914621 <6>[ 0.291797] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10420 12:27:38.917748 <6>[ 0.299019] CPU: All CPU(s) started at EL2
10421 12:27:38.924060 <6>[ 0.303335] alternatives: applying system-wide alternatives
10422 12:27:38.933603 <6>[ 0.314029] devtmpfs: initialized
10423 12:27:38.945772 <6>[ 0.322878] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10424 12:27:38.955417 <6>[ 0.332844] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10425 12:27:38.962103 <6>[ 0.340853] pinctrl core: initialized pinctrl subsystem
10426 12:27:38.965431 <6>[ 0.347517] DMI not present or invalid.
10427 12:27:38.972044 <6>[ 0.351924] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10428 12:27:38.981857 <6>[ 0.358784] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10429 12:27:38.988349 <6>[ 0.366368] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10430 12:27:38.998421 <6>[ 0.374581] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10431 12:27:39.001591 <6>[ 0.382826] audit: initializing netlink subsys (disabled)
10432 12:27:39.012060 <5>[ 0.388516] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10433 12:27:39.018365 <6>[ 0.389231] thermal_sys: Registered thermal governor 'step_wise'
10434 12:27:39.025293 <6>[ 0.396482] thermal_sys: Registered thermal governor 'power_allocator'
10435 12:27:39.028457 <6>[ 0.402737] cpuidle: using governor menu
10436 12:27:39.034617 <6>[ 0.413691] NET: Registered PF_QIPCRTR protocol family
10437 12:27:39.041640 <6>[ 0.419167] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10438 12:27:39.045008 <6>[ 0.426271] ASID allocator initialised with 32768 entries
10439 12:27:39.052096 <6>[ 0.432848] Serial: AMBA PL011 UART driver
10440 12:27:39.060646 <4>[ 0.441521] Trying to register duplicate clock ID: 134
10441 12:27:39.114715 <6>[ 0.498634] KASLR enabled
10442 12:27:39.129121 <6>[ 0.506331] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10443 12:27:39.135548 <6>[ 0.513342] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10444 12:27:39.142598 <6>[ 0.519829] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10445 12:27:39.148953 <6>[ 0.526833] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10446 12:27:39.155482 <6>[ 0.533320] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10447 12:27:39.162070 <6>[ 0.540322] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10448 12:27:39.168704 <6>[ 0.546808] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10449 12:27:39.175897 <6>[ 0.553814] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10450 12:27:39.179218 <6>[ 0.561298] ACPI: Interpreter disabled.
10451 12:27:39.187041 <6>[ 0.567736] iommu: Default domain type: Translated
10452 12:27:39.193598 <6>[ 0.572848] iommu: DMA domain TLB invalidation policy: strict mode
10453 12:27:39.197379 <5>[ 0.579504] SCSI subsystem initialized
10454 12:27:39.203734 <6>[ 0.583745] usbcore: registered new interface driver usbfs
10455 12:27:39.210494 <6>[ 0.589475] usbcore: registered new interface driver hub
10456 12:27:39.213624 <6>[ 0.595031] usbcore: registered new device driver usb
10457 12:27:39.220538 <6>[ 0.601136] pps_core: LinuxPPS API ver. 1 registered
10458 12:27:39.230729 <6>[ 0.606327] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10459 12:27:39.234061 <6>[ 0.615671] PTP clock support registered
10460 12:27:39.237187 <6>[ 0.619909] EDAC MC: Ver: 3.0.0
10461 12:27:39.244849 <6>[ 0.625105] FPGA manager framework
10462 12:27:39.248016 <6>[ 0.628783] Advanced Linux Sound Architecture Driver Initialized.
10463 12:27:39.251926 <6>[ 0.635546] vgaarb: loaded
10464 12:27:39.258483 <6>[ 0.638712] clocksource: Switched to clocksource arch_sys_counter
10465 12:27:39.265059 <5>[ 0.645158] VFS: Disk quotas dquot_6.6.0
10466 12:27:39.271538 <6>[ 0.649349] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10467 12:27:39.274808 <6>[ 0.656541] pnp: PnP ACPI: disabled
10468 12:27:39.282678 <6>[ 0.663260] NET: Registered PF_INET protocol family
10469 12:27:39.292396 <6>[ 0.668865] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10470 12:27:39.304091 <6>[ 0.681078] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10471 12:27:39.313723 <6>[ 0.689905] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10472 12:27:39.320537 <6>[ 0.697871] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10473 12:27:39.327309 <6>[ 0.706569] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10474 12:27:39.339180 <6>[ 0.716280] TCP: Hash tables configured (established 65536 bind 65536)
10475 12:27:39.345564 <6>[ 0.723139] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 12:27:39.352580 <6>[ 0.730338] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10477 12:27:39.358968 <6>[ 0.738043] NET: Registered PF_UNIX/PF_LOCAL protocol family
10478 12:27:39.365731 <6>[ 0.744208] RPC: Registered named UNIX socket transport module.
10479 12:27:39.369033 <6>[ 0.750361] RPC: Registered udp transport module.
10480 12:27:39.375493 <6>[ 0.755292] RPC: Registered tcp transport module.
10481 12:27:39.382038 <6>[ 0.760222] RPC: Registered tcp NFSv4.1 backchannel transport module.
10482 12:27:39.385369 <6>[ 0.766886] PCI: CLS 0 bytes, default 64
10483 12:27:39.388624 <6>[ 0.771272] Unpacking initramfs...
10484 12:27:39.399152 <6>[ 0.775070] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10485 12:27:39.405617 <6>[ 0.783708] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10486 12:27:39.412639 <6>[ 0.792533] kvm [1]: IPA Size Limit: 40 bits
10487 12:27:39.415203 <6>[ 0.797060] kvm [1]: GICv3: no GICV resource entry
10488 12:27:39.422104 <6>[ 0.802081] kvm [1]: disabling GICv2 emulation
10489 12:27:39.428863 <6>[ 0.806767] kvm [1]: GIC system register CPU interface enabled
10490 12:27:39.432113 <6>[ 0.812931] kvm [1]: vgic interrupt IRQ18
10491 12:27:39.438262 <6>[ 0.817286] kvm [1]: VHE mode initialized successfully
10492 12:27:39.441940 <5>[ 0.823692] Initialise system trusted keyrings
10493 12:27:39.448423 <6>[ 0.828482] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10494 12:27:39.458411 <6>[ 0.838508] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10495 12:27:39.464781 <5>[ 0.844901] NFS: Registering the id_resolver key type
10496 12:27:39.468148 <5>[ 0.850200] Key type id_resolver registered
10497 12:27:39.474640 <5>[ 0.854618] Key type id_legacy registered
10498 12:27:39.481101 <6>[ 0.858896] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10499 12:27:39.487680 <6>[ 0.865818] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10500 12:27:39.494726 <6>[ 0.873522] 9p: Installing v9fs 9p2000 file system support
10501 12:27:39.531376 <5>[ 0.912101] Key type asymmetric registered
10502 12:27:39.535037 <5>[ 0.916436] Asymmetric key parser 'x509' registered
10503 12:27:39.545113 <6>[ 0.921602] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10504 12:27:39.548335 <6>[ 0.929217] io scheduler mq-deadline registered
10505 12:27:39.551533 <6>[ 0.933978] io scheduler kyber registered
10506 12:27:39.570194 <6>[ 0.951031] EINJ: ACPI disabled.
10507 12:27:39.602109 <4>[ 0.976345] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 12:27:39.611893 <4>[ 0.986977] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10509 12:27:39.626868 <6>[ 1.007654] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10510 12:27:39.634884 <6>[ 1.015681] printk: console [ttyS0] disabled
10511 12:27:39.663327 <6>[ 1.040330] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10512 12:27:39.669710 <6>[ 1.049795] printk: console [ttyS0] enabled
10513 12:27:39.673016 <6>[ 1.049795] printk: console [ttyS0] enabled
10514 12:27:39.679567 <6>[ 1.058688] printk: bootconsole [mtk8250] disabled
10515 12:27:39.682793 <6>[ 1.058688] printk: bootconsole [mtk8250] disabled
10516 12:27:39.689394 <6>[ 1.069969] SuperH (H)SCI(F) driver initialized
10517 12:27:39.692611 <6>[ 1.075255] msm_serial: driver initialized
10518 12:27:39.707028 <6>[ 1.084224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10519 12:27:39.717209 <6>[ 1.092778] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10520 12:27:39.723591 <6>[ 1.101324] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10521 12:27:39.733813 <6>[ 1.109953] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10522 12:27:39.743509 <6>[ 1.118658] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10523 12:27:39.750421 <6>[ 1.127371] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10524 12:27:39.759926 <6>[ 1.135913] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10525 12:27:39.766385 <6>[ 1.144726] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10526 12:27:39.776864 <6>[ 1.153273] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10527 12:27:39.787981 <6>[ 1.168842] loop: module loaded
10528 12:27:39.794595 <6>[ 1.174866] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10529 12:27:39.817334 <4>[ 1.198091] mtk-pmic-keys: Failed to locate of_node [id: -1]
10530 12:27:39.824343 <6>[ 1.204917] megasas: 07.719.03.00-rc1
10531 12:27:39.833962 <6>[ 1.214421] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10532 12:27:39.841833 <6>[ 1.222082] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10533 12:27:39.857858 <6>[ 1.238541] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10534 12:27:39.918834 <6>[ 1.292544] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10535 12:27:40.283992 <6>[ 1.664834] Freeing initrd memory: 20720K
10536 12:27:40.300126 <6>[ 1.680587] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10537 12:27:40.310754 <6>[ 1.691383] tun: Universal TUN/TAP device driver, 1.6
10538 12:27:40.313839 <6>[ 1.697426] thunder_xcv, ver 1.0
10539 12:27:40.317183 <6>[ 1.700927] thunder_bgx, ver 1.0
10540 12:27:40.320508 <6>[ 1.704423] nicpf, ver 1.0
10541 12:27:40.330920 <6>[ 1.708437] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10542 12:27:40.334116 <6>[ 1.715913] hns3: Copyright (c) 2017 Huawei Corporation.
10543 12:27:40.340851 <6>[ 1.721498] hclge is initializing
10544 12:27:40.344128 <6>[ 1.725074] e1000: Intel(R) PRO/1000 Network Driver
10545 12:27:40.351355 <6>[ 1.730202] e1000: Copyright (c) 1999-2006 Intel Corporation.
10546 12:27:40.354547 <6>[ 1.736213] e1000e: Intel(R) PRO/1000 Network Driver
10547 12:27:40.361332 <6>[ 1.741429] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10548 12:27:40.367577 <6>[ 1.747616] igb: Intel(R) Gigabit Ethernet Network Driver
10549 12:27:40.374556 <6>[ 1.753266] igb: Copyright (c) 2007-2014 Intel Corporation.
10550 12:27:40.380680 <6>[ 1.759102] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10551 12:27:40.387546 <6>[ 1.765620] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10552 12:27:40.390757 <6>[ 1.772076] sky2: driver version 1.30
10553 12:27:40.397169 <6>[ 1.777051] VFIO - User Level meta-driver version: 0.3
10554 12:27:40.404839 <6>[ 1.785264] usbcore: registered new interface driver usb-storage
10555 12:27:40.411437 <6>[ 1.791707] usbcore: registered new device driver onboard-usb-hub
10556 12:27:40.419838 <6>[ 1.800800] mt6397-rtc mt6359-rtc: registered as rtc0
10557 12:27:40.430161 <6>[ 1.806265] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:27:51 UTC (1686054471)
10558 12:27:40.433509 <6>[ 1.815857] i2c_dev: i2c /dev entries driver
10559 12:27:40.450395 <6>[ 1.827546] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10560 12:27:40.456842 <6>[ 1.837729] sdhci: Secure Digital Host Controller Interface driver
10561 12:27:40.463785 <6>[ 1.844166] sdhci: Copyright(c) Pierre Ossman
10562 12:27:40.470582 <6>[ 1.849559] Synopsys Designware Multimedia Card Interface Driver
10563 12:27:40.473650 <6>[ 1.856181] mmc0: CQHCI version 5.10
10564 12:27:40.480566 <6>[ 1.856717] sdhci-pltfm: SDHCI platform and OF driver helper
10565 12:27:40.487399 <6>[ 1.868274] ledtrig-cpu: registered to indicate activity on CPUs
10566 12:27:40.498065 <6>[ 1.875715] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10567 12:27:40.501914 <6>[ 1.883131] usbcore: registered new interface driver usbhid
10568 12:27:40.508510 <6>[ 1.888964] usbhid: USB HID core driver
10569 12:27:40.515030 <6>[ 1.893223] spi_master spi0: will run message pump with realtime priority
10570 12:27:40.557077 <6>[ 1.931173] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10571 12:27:40.575562 <6>[ 1.946062] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10572 12:27:40.578728 <6>[ 1.959628] mmc0: Command Queue Engine enabled
10573 12:27:40.586133 <6>[ 1.961819] cros-ec-spi spi0.0: Chrome EC device registered
10574 12:27:40.589252 <6>[ 1.964371] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10575 12:27:40.596846 <6>[ 1.977502] mmcblk0: mmc0:0001 DA4128 116 GiB
10576 12:27:40.608265 <6>[ 1.985800] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10577 12:27:40.614818 <6>[ 1.989441] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10578 12:27:40.621373 <6>[ 1.997170] NET: Registered PF_PACKET protocol family
10579 12:27:40.625289 <6>[ 2.002369] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10580 12:27:40.631876 <6>[ 2.006457] 9pnet: Installing 9P2000 support
10581 12:27:40.635192 <6>[ 2.012215] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10582 12:27:40.641698 <5>[ 2.016134] Key type dns_resolver registered
10583 12:27:40.648425 <6>[ 2.021891] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10584 12:27:40.651679 <6>[ 2.026334] registered taskstats version 1
10585 12:27:40.654846 <5>[ 2.036734] Loading compiled-in X.509 certificates
10586 12:27:40.689367 <4>[ 2.063348] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 12:27:40.699089 <4>[ 2.074036] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 12:27:40.709099 <3>[ 2.086802] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10589 12:27:40.721438 <6>[ 2.102256] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10590 12:27:40.728586 <6>[ 2.109015] xhci-mtk 11200000.usb: xHCI Host Controller
10591 12:27:40.735110 <6>[ 2.114515] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10592 12:27:40.744734 <6>[ 2.122359] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10593 12:27:40.751958 <6>[ 2.131816] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10594 12:27:40.758321 <6>[ 2.138033] xhci-mtk 11200000.usb: xHCI Host Controller
10595 12:27:40.764748 <6>[ 2.143535] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10596 12:27:40.771851 <6>[ 2.151192] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10597 12:27:40.778702 <6>[ 2.159110] hub 1-0:1.0: USB hub found
10598 12:27:40.781861 <6>[ 2.163150] hub 1-0:1.0: 1 port detected
10599 12:27:40.788272 <6>[ 2.167512] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10600 12:27:40.795724 <6>[ 2.176136] hub 2-0:1.0: USB hub found
10601 12:27:40.798783 <6>[ 2.180153] hub 2-0:1.0: 1 port detected
10602 12:27:40.806455 <6>[ 2.187227] mtk-msdc 11f70000.mmc: Got CD GPIO
10603 12:27:40.823759 <6>[ 2.200971] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10604 12:27:40.830300 <6>[ 2.209001] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10605 12:27:40.840604 <4>[ 2.216966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10606 12:27:40.850500 <6>[ 2.226632] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10607 12:27:40.857169 <6>[ 2.234715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10608 12:27:40.863802 <6>[ 2.242762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10609 12:27:40.873614 <6>[ 2.250685] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10610 12:27:40.880036 <6>[ 2.258506] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10611 12:27:40.890080 <6>[ 2.266328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10612 12:27:40.900243 <6>[ 2.276966] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10613 12:27:40.906778 <6>[ 2.285335] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10614 12:27:40.916275 <6>[ 2.293691] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10615 12:27:40.923279 <6>[ 2.302035] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10616 12:27:40.933136 <6>[ 2.310380] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10617 12:27:40.943016 <6>[ 2.318725] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10618 12:27:40.949504 <6>[ 2.327069] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10619 12:27:40.959095 <6>[ 2.335413] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10620 12:27:40.965774 <6>[ 2.343756] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10621 12:27:40.975742 <6>[ 2.352100] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10622 12:27:40.982815 <6>[ 2.360444] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10623 12:27:40.992290 <6>[ 2.368788] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10624 12:27:40.999105 <6>[ 2.377132] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10625 12:27:41.009238 <6>[ 2.385476] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10626 12:27:41.015407 <6>[ 2.393819] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10627 12:27:41.022323 <6>[ 2.402773] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10628 12:27:41.029498 <6>[ 2.410288] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10629 12:27:41.036626 <6>[ 2.417417] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10630 12:27:41.047151 <6>[ 2.424573] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10631 12:27:41.053586 <6>[ 2.431907] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10632 12:27:41.063878 <6>[ 2.438857] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10633 12:27:41.070391 <6>[ 2.448000] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10634 12:27:41.080130 <6>[ 2.457130] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10635 12:27:41.090544 <6>[ 2.466432] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10636 12:27:41.100088 <6>[ 2.475906] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10637 12:27:41.110138 <6>[ 2.485380] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10638 12:27:41.116740 <6>[ 2.494507] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10639 12:27:41.126805 <6>[ 2.504007] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10640 12:27:41.136572 <6>[ 2.513135] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10641 12:27:41.146353 <6>[ 2.522436] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10642 12:27:41.156738 <6>[ 2.532603] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10643 12:27:41.166938 <6>[ 2.544468] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10644 12:27:41.189611 <6>[ 2.566984] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10645 12:27:41.217099 <6>[ 2.597546] hub 2-1:1.0: USB hub found
10646 12:27:41.220121 <6>[ 2.601945] hub 2-1:1.0: 3 ports detected
10647 12:27:41.341432 <6>[ 2.718919] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10648 12:27:41.495868 <6>[ 2.876620] hub 1-1:1.0: USB hub found
10649 12:27:41.499014 <6>[ 2.881046] hub 1-1:1.0: 4 ports detected
10650 12:27:41.577390 <6>[ 2.955225] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10651 12:27:41.821257 <6>[ 3.198981] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10652 12:27:41.954467 <6>[ 3.335255] hub 1-1.4:1.0: USB hub found
10653 12:27:41.957495 <6>[ 3.339961] hub 1-1.4:1.0: 2 ports detected
10654 12:27:42.257377 <6>[ 3.634982] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10655 12:27:42.449626 <6>[ 3.826982] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10656 12:27:53.441835 <6>[ 14.827530] ALSA device list:
10657 12:27:53.448531 <6>[ 14.830786] No soundcards found.
10658 12:27:53.460831 <6>[ 14.843183] Freeing unused kernel memory: 8384K
10659 12:27:53.463986 <6>[ 14.848116] Run /init as init process
10660 12:27:53.490130 Starting syslogd: OK
10661 12:27:53.494050 Starting klogd: OK
10662 12:27:53.503700 Running sysctl: OK
10663 12:27:53.513388 Populating /dev using udev: <30>[ 14.894555] udevd[186]: starting version 3.2.9
10664 12:27:53.520719 <27>[ 14.902667] udevd[186]: specified user 'tss' unknown
10665 12:27:53.527146 <27>[ 14.908125] udevd[186]: specified group 'tss' unknown
10666 12:27:53.533742 <30>[ 14.914559] udevd[187]: starting eudev-3.2.9
10667 12:27:53.562869 <27>[ 14.944770] udevd[187]: specified user 'tss' unknown
10668 12:27:53.569553 <27>[ 14.950146] udevd[187]: specified group 'tss' unknown
10669 12:27:53.752965 <6>[ 15.131511] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10670 12:27:53.797359 <6>[ 15.179421] remoteproc remoteproc0: scp is available
10671 12:27:53.806902 <4>[ 15.185112] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10672 12:27:53.814099 <6>[ 15.194971] remoteproc remoteproc0: powering up scp
10673 12:27:53.823928 <4>[ 15.200187] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10674 12:27:53.830506 <3>[ 15.210370] remoteproc remoteproc0: request_firmware failed: -2
10675 12:27:53.836951 <4>[ 15.217763] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10676 12:27:53.847750 <4>[ 15.226450] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10677 12:27:53.854451 <6>[ 15.226793] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10678 12:27:53.864070 <6>[ 15.242186] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10679 12:27:53.873991 <6>[ 15.250977] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10680 12:27:53.880859 <6>[ 15.253313] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10681 12:27:53.887213 <3>[ 15.253751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 12:27:53.896690 <3>[ 15.253769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 12:27:53.903299 <3>[ 15.253778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 12:27:53.913178 <3>[ 15.253849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 12:27:53.920489 <3>[ 15.253857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 12:27:53.930175 <3>[ 15.253863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:27:53.936620 <3>[ 15.253871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 12:27:53.943796 <3>[ 15.253877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:27:53.953515 <3>[ 15.253939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 12:27:53.960060 <3>[ 15.253991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 12:27:53.969855 <3>[ 15.253998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 12:27:53.976679 <3>[ 15.254004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 12:27:53.984088 <3>[ 15.254056] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 12:27:53.994081 <3>[ 15.254063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 12:27:54.000836 <3>[ 15.254069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 12:27:54.010600 <3>[ 15.254075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 12:27:54.017188 <3>[ 15.254081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 12:27:54.026910 <3>[ 15.254122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 12:27:54.030252 <6>[ 15.266528] mc: Linux media interface: v0.10
10700 12:27:54.036810 <6>[ 15.269000] usbcore: registered new interface driver r8152
10701 12:27:54.046528 <4>[ 15.296023] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10702 12:27:54.050400 <4>[ 15.296023] Fallback method does not support PEC.
10703 12:27:54.060134 <6>[ 15.299495] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10704 12:27:54.069850 <6>[ 15.299793] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10705 12:27:54.076057 <3>[ 15.326037] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10706 12:27:54.086134 <6>[ 15.342949] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10707 12:27:54.095851 <3>[ 15.371070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10708 12:27:54.102996 <6>[ 15.383155] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10709 12:27:54.109766 <6>[ 15.389175] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10710 12:27:54.116240 <6>[ 15.389799] videodev: Linux video capture interface: v2.00
10711 12:27:54.122656 <6>[ 15.405972] usbcore: registered new interface driver cdc_ether
10712 12:27:54.125870 <6>[ 15.413321] pci_bus 0000:00: root bus resource [bus 00-ff]
10713 12:27:54.132362 <6>[ 15.438310] usbcore: registered new interface driver r8153_ecm
10714 12:27:54.142454 <4>[ 15.440406] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10715 12:27:54.149031 <4>[ 15.440418] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10716 12:27:54.159531 <6>[ 15.447315] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10717 12:27:54.169235 <6>[ 15.447322] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10718 12:27:54.175808 <6>[ 15.447395] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10719 12:27:54.179088 <6>[ 15.457792] Bluetooth: Core ver 2.22
10720 12:27:54.185735 <6>[ 15.458457] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10721 12:27:54.199032 <6>[ 15.459836] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10722 12:27:54.202186 <6>[ 15.460066] usbcore: registered new interface driver uvcvideo
10723 12:27:54.211935 <6>[ 15.465176] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10724 12:27:54.215734 <6>[ 15.465271] pci 0000:00:00.0: supports D1 D2
10725 12:27:54.222181 <6>[ 15.474613] NET: Registered PF_BLUETOOTH protocol family
10726 12:27:54.228639 <6>[ 15.483266] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10727 12:27:54.235144 <6>[ 15.485133] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10728 12:27:54.242224 <6>[ 15.490510] Bluetooth: HCI device and connection manager initialized
10729 12:27:54.248811 <6>[ 15.497402] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10730 12:27:54.255319 <6>[ 15.498061] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10731 12:27:54.258628 <6>[ 15.498944] r8152 2-1.3:1.0 eth0: v1.12.13
10732 12:27:54.265115 <6>[ 15.503083] Bluetooth: HCI socket layer initialized
10733 12:27:54.271503 <6>[ 15.503771] remoteproc remoteproc0: powering up scp
10734 12:27:54.281425 <4>[ 15.503817] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10735 12:27:54.284614 <3>[ 15.503826] remoteproc remoteproc0: request_firmware failed: -2
10736 12:27:54.294620 <3>[ 15.503829] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10737 12:27:54.301156 <6>[ 15.509156] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10738 12:27:54.307849 <6>[ 15.514870] Bluetooth: L2CAP socket layer initialized
10739 12:27:54.314588 <6>[ 15.520964] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10740 12:27:54.317708 <6>[ 15.530000] Bluetooth: SCO socket layer initialized
10741 12:27:54.327476 <6>[ 15.538079] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10742 12:27:54.331316 <6>[ 15.591391] usbcore: registered new interface driver btusb
10743 12:27:54.344012 <4>[ 15.592317] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10744 12:27:54.347232 <3>[ 15.592326] Bluetooth: hci0: Failed to load firmware file (-2)
10745 12:27:54.354385 <3>[ 15.592329] Bluetooth: hci0: Failed to set up firmware (-2)
10746 12:27:54.363739 <4>[ 15.592333] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10747 12:27:54.370929 <6>[ 15.598294] pci 0000:01:00.0: supports D1 D2
10748 12:27:54.377322 <6>[ 15.756816] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 12:27:54.396311 <6>[ 15.774972] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10750 12:27:54.402741 <6>[ 15.781880] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10751 12:27:54.409213 <6>[ 15.789972] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10752 12:27:54.419461 <6>[ 15.797981] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10753 12:27:54.426207 <6>[ 15.805989] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10754 12:27:54.436056 <6>[ 15.813996] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10755 12:27:54.439308 <6>[ 15.822004] pci 0000:00:00.0: PCI bridge to [bus 01]
10756 12:27:54.449044 <6>[ 15.827224] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10757 12:27:54.455680 <6>[ 15.835429] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10758 12:27:54.462232 <6>[ 15.842639] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10759 12:27:54.468764 <6>[ 15.849184] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10760 12:27:54.487038 <5>[ 15.866112] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10761 12:27:54.519043 <5>[ 15.898056] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10762 12:27:54.525548 <4>[ 15.904946] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10763 12:27:54.532193 <6>[ 15.913837] cfg80211: failed to load regulatory.db
10764 12:27:54.576790 <6>[ 15.956016] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10765 12:27:54.583759 <6>[ 15.963625] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10766 12:27:54.608162 <6>[ 15.990449] mt7921e 0000:01:00.0: ASIC revision: 79610010
10767 12:27:54.714704 <4>[ 16.090467] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 12:27:54.721894 done
10769 12:27:54.736493 Saving random seed: OK
10770 12:27:54.751784 Starting network: OK
10771 12:27:54.789440 Starting dropbear sshd: <6>[ 16.171482] NET: Registered PF_INET6 protocol family
10772 12:27:54.795968 <6>[ 16.178240] Segment Routing with IPv6
10773 12:27:54.799219 <6>[ 16.182214] In-situ OAM (IOAM) with IPv6
10774 12:27:54.802941 OK
10775 12:27:54.812796 /bin/sh: can't access tty; job control turned off
10776 12:27:54.813122 Matched prompt #10: / #
10778 12:27:54.813384 Setting prompt string to ['/ #']
10779 12:27:54.813516 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10781 12:27:54.813839 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10782 12:27:54.813959 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10783 12:27:54.814061 Setting prompt string to ['/ #']
10784 12:27:54.814163 Forcing a shell prompt, looking for ['/ #']
10786 12:27:54.864426 / #
10787 12:27:54.864622 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10788 12:27:54.864726 Waiting using forced prompt support (timeout 00:02:30)
10789 12:27:54.864831 <4>[ 16.213209] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 12:27:54.869877
10791 12:27:54.870176 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10792 12:27:54.870283 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10793 12:27:54.870399 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10794 12:27:54.870494 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
10795 12:27:54.870584 end: 2 depthcharge-action (duration 00:01:34) [common]
10796 12:27:54.870687 start: 3 lava-test-retry (timeout 00:01:00) [common]
10797 12:27:54.870779 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10798 12:27:54.870865 Using namespace: common
10800 12:27:54.971175 / # #
10801 12:27:54.971419 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10802 12:27:54.971595 #<4>[ 16.333108] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10803 12:27:54.976468
10804 12:27:54.976748 Using /lava-10605768
10806 12:27:55.077094 / # export SHELL=/bin/sh
10807 12:27:55.077304 export SHELL=/bin/sh<4>[ 16.453026] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 12:27:55.119426
10810 12:27:55.219980 / # . /lava-10605768/environment
10811 12:27:55.220219 . /lava-10605768/environment<4>[ 16.573287] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 12:27:55.224763
10814 12:27:55.325260 / # /lava-10605768/bin/lava-test-runner /lava-10605768/0
10815 12:27:55.325459 Test shell timeout: 10s (minimum of the action and connection timeout)
10816 12:27:55.325888 /lava-10605768/bin/lava-test-runner /lava-10605768/0<4>[ 16.693176] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 12:27:55.330692
10818 12:27:55.371425 + export 'TESTRUN_ID=0_dmesg'
10819 12:27:55.371564 +<8>[ 16.737294] <LAVA_SIGNAL_STARTRUN 0_dmesg 10605768_1.5.2.3.1>
10820 12:27:55.371638 cd /lava-10605768/0/tests/0_dmesg
10821 12:27:55.371709 + cat uuid
10822 12:27:55.371948 Received signal: <STARTRUN> 0_dmesg 10605768_1.5.2.3.1
10823 12:27:55.372022 Starting test lava.0_dmesg (10605768_1.5.2.3.1)
10824 12:27:55.372105 Skipping test definition patterns.
10825 12:27:55.372217 + UUID=10605768_1.5.2.3.1
10826 12:27:55.372284 + set +x
10827 12:27:55.372352 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10828 12:27:55.379614 <8>[ 16.757555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10829 12:27:55.379927 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10831 12:27:55.398874 <8>[ 16.778014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10832 12:27:55.399146 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10834 12:27:55.419932 <8>[ 16.798904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10835 12:27:55.420204 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10837 12:27:55.423910 + set +x
10838 12:27:55.427152 <8>[ 16.809966] <LAVA_SIGNAL_ENDRUN 0_dmesg 10605768_1.5.2.3.1>
10839 12:27:55.427372 Received signal: <ENDRUN> 0_dmesg 10605768_1.5.2.3.1
10840 12:27:55.427465 Ending use of test pattern.
10841 12:27:55.427534 Ending test lava.0_dmesg (10605768_1.5.2.3.1), duration 0.06
10843 12:27:55.440691 <4>[ 16.813330] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10844 12:27:55.443955 <LAVA_TEST_RUNNER EXIT>
10845 12:27:55.444213 ok: lava_test_shell seems to have completed
10846 12:27:55.444325 alert: pass
crit: pass
emerg: pass
10847 12:27:55.444422 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10848 12:27:55.444512 end: 3 lava-test-retry (duration 00:00:01) [common]
10849 12:27:55.444600 start: 4 lava-test-retry (timeout 00:01:00) [common]
10850 12:27:55.444686 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10851 12:27:55.444753 Using namespace: common
10853 12:27:55.545108 / # #
10854 12:27:55.545327 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10855 12:27:55.545480 Using /lava-10605768
10857 12:27:55.645779 export SHELL=/bin/sh
10858 12:27:55.645989 #
10859 12:27:55.646067 / # <4>[ 16.936837] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 12:27:55.746575 export SHELL=/bin/sh. /lava-10605768/environment
10862 12:27:55.746798
10863 12:27:55.746874 / # <4>[ 17.056974] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 12:27:55.847384 . /lava-10605768/environment/lava-10605768/bin/lava-test-runner /lava-10605768/1
10866 12:27:55.847558 Test shell timeout: 10s (minimum of the action and connection timeout)
10867 12:27:55.847679
10868 12:27:55.847753 / # <4>[ 17.177119] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 12:27:55.852864 /lava-10605768/bin/lava-test-runner /lava-10605768/1
10870 12:27:55.899446 + export 'TESTRUN_ID=1_bootrr'
10871 12:27:55.899583 <8>[ 17.256861] <LAVA_SIGNAL_STARTRUN 1_bootrr 10605768_1.5.2.3.5>
10872 12:27:55.899665 + cd /lava-10605768/1/tests/1_bootrr
10873 12:27:55.899738 + cat uuid
10874 12:27:55.899802 + UUID=10605768_1.5.2.3.5
10875 12:27:55.899865 + set +x
10876 12:27:55.899927 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10605768/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10877 12:27:55.900180 Received signal: <STARTRUN> 1_bootrr 10605768_1.5.2.3.5
10878 12:27:55.900279 Starting test lava.1_bootrr (10605768_1.5.2.3.5)
10879 12:27:55.900385 Skipping test definition patterns.
10880 12:27:55.900490 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10882 12:27:55.902323 <8>[ 17.279854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10883 12:27:55.902436
10884 12:27:55.902537 + cd /opt/bootrr/libexec/bootrr
10885 12:27:55.905476 + sh helpers/bootrr-auto
10886 12:27:55.908846 /lava-10605768/1/../bin/lava-test-case
10887 12:27:55.920829 <3>[ 17.303098] mt7921e 0000:01:00.0: hardware init failed
10888 12:27:55.924104 /lava-10605768/1/../bin/lava-test-case
10889 12:27:55.933898 <8>[ 17.312607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10890 12:27:55.934177 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10892 12:27:55.938475 /usr/bin/tpm2_getcap
10893 12:27:55.974407 /lava-10605768/1/../bin/lava-test-case
10894 12:27:55.980645 <8>[ 17.360641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10895 12:27:55.980916 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10897 12:27:55.998781 /lava-10605768/1/../bin/lava-test-case
10898 12:27:56.005232 <8>[ 17.384198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10899 12:27:56.005494 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10901 12:27:56.016891 /lava-10605768/1/../bin/lava-test-case
10902 12:27:56.023685 <8>[ 17.402494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10903 12:27:56.023989 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10905 12:27:56.035433 /lava-10605768/1/../bin/lava-test-case
10906 12:27:56.042048 <8>[ 17.421011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10907 12:27:56.042313 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10909 12:27:56.053207 /lava-10605768/1/../bin/lava-test-case
10910 12:27:56.059779 <8>[ 17.438941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10911 12:27:56.060047 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10913 12:27:56.071767 /lava-10605768/1/../bin/lava-test-case
10914 12:27:56.077753 <8>[ 17.457220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10915 12:27:56.078047 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10917 12:27:56.087630 /lava-10605768/1/../bin/lava-test-case
10918 12:27:56.094075 <8>[ 17.473177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10919 12:27:56.094336 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10921 12:27:56.106548 /lava-10605768/1/../bin/lava-test-case
10922 12:27:56.113124 <8>[ 17.492226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10923 12:27:56.113395 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10925 12:27:56.122234 /lava-10605768/1/../bin/lava-test-case
10926 12:27:56.128842 <8>[ 17.507455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10927 12:27:56.129149 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10929 12:27:56.141147 /lava-10605768/1/../bin/lava-test-case
10930 12:27:56.148099 <8>[ 17.527480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10931 12:27:56.148365 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10933 12:27:56.160241 /lava-10605768/1/../bin/lava-test-case
10934 12:27:56.166640 <8>[ 17.545877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10935 12:27:56.166906 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10937 12:27:56.178997 /lava-10605768/1/../bin/lava-test-case
10938 12:27:56.185720 <8>[ 17.565190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10939 12:27:56.186016 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10941 12:27:56.198117 /lava-10605768/1/../bin/lava-test-case
10942 12:27:56.204660 <8>[ 17.584045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10943 12:27:56.204969 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10945 12:27:56.215159 /lava-10605768/1/../bin/lava-test-case
10946 12:27:56.221698 <8>[ 17.601105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10947 12:27:56.221993 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10949 12:27:56.233596 /lava-10605768/1/../bin/lava-test-case
10950 12:27:56.239980 <8>[ 17.619274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10951 12:27:56.240275 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10953 12:27:56.249354 /lava-10605768/1/../bin/lava-test-case
10954 12:27:56.255910 <8>[ 17.635413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10955 12:27:56.256205 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10957 12:27:56.267748 /lava-10605768/1/../bin/lava-test-case
10958 12:27:56.274412 <8>[ 17.653812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10959 12:27:56.274677 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10961 12:27:56.283692 /lava-10605768/1/../bin/lava-test-case
10962 12:27:56.290224 <8>[ 17.669171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10963 12:27:56.290526 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10965 12:27:56.301747 /lava-10605768/1/../bin/lava-test-case
10966 12:27:56.308166 <8>[ 17.687411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10967 12:27:56.308428 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10969 12:27:56.317434 /lava-10605768/1/../bin/lava-test-case
10970 12:27:56.324016 <8>[ 17.702839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10971 12:27:56.324311 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10973 12:27:56.335894 /lava-10605768/1/../bin/lava-test-case
10974 12:27:56.342305 <8>[ 17.721240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10975 12:27:56.342564 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10977 12:27:56.351872 /lava-10605768/1/../bin/lava-test-case
10978 12:27:56.357959 <8>[ 17.737719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10979 12:27:56.358219 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10981 12:27:56.370214 /lava-10605768/1/../bin/lava-test-case
10982 12:27:56.376631 <8>[ 17.755712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10983 12:27:56.376949 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10985 12:27:56.388966 /lava-10605768/1/../bin/lava-test-case
10986 12:27:56.395482 <8>[ 17.774558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10987 12:27:56.395751 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10989 12:27:56.404605 /lava-10605768/1/../bin/lava-test-case
10990 12:27:56.411065 <8>[ 17.790302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10991 12:27:56.411329 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10993 12:27:56.424196 /lava-10605768/1/../bin/lava-test-case
10994 12:27:56.430124 <8>[ 17.809463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10995 12:27:56.430393 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10997 12:27:56.439146 /lava-10605768/1/../bin/lava-test-case
10998 12:27:56.446029 <8>[ 17.825005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10999 12:27:56.446320 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11001 12:27:56.457759 /lava-10605768/1/../bin/lava-test-case
11002 12:27:56.464339 <8>[ 17.843517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11003 12:27:56.464628 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11005 12:27:56.475165 /lava-10605768/1/../bin/lava-test-case
11006 12:27:56.481823 <8>[ 17.860901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11007 12:27:56.482098 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11009 12:27:56.493915 /lava-10605768/1/../bin/lava-test-case
11010 12:27:56.500454 <8>[ 17.879831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11011 12:27:56.500721 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11013 12:27:56.512124 /lava-10605768/1/../bin/lava-test-case
11014 12:27:56.518630 <8>[ 17.898140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11015 12:27:56.518902 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11017 12:27:56.528641 /lava-10605768/1/../bin/lava-test-case
11018 12:27:56.535368 <8>[ 17.914565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11019 12:27:56.535644 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11021 12:27:56.547288 /lava-10605768/1/../bin/lava-test-case
11022 12:27:56.553692 <8>[ 17.932882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11023 12:27:56.553958 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11025 12:27:56.565191 /lava-10605768/1/../bin/lava-test-case
11026 12:27:56.571729 <8>[ 17.950544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11027 12:27:56.571992 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11029 12:27:56.580739 /lava-10605768/1/../bin/lava-test-case
11030 12:27:56.587620 <8>[ 17.966891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11031 12:27:56.587890 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11033 12:27:56.598849 /lava-10605768/1/../bin/lava-test-case
11034 12:27:56.605456 <8>[ 17.984841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11035 12:27:56.605740 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11037 12:27:56.615207 /lava-10605768/1/../bin/lava-test-case
11038 12:27:56.621905 <8>[ 18.000989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11039 12:27:56.622184 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11041 12:27:56.633258 /lava-10605768/1/../bin/lava-test-case
11042 12:27:56.639853 <8>[ 18.019418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11043 12:27:56.640142 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11045 12:27:56.649023 /lava-10605768/1/../bin/lava-test-case
11046 12:27:56.655701 <8>[ 18.034941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11047 12:27:56.655969 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11049 12:27:56.667342 /lava-10605768/1/../bin/lava-test-case
11050 12:27:56.673933 <8>[ 18.053364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11051 12:27:56.674194 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11053 12:27:56.683388 /lava-10605768/1/../bin/lava-test-case
11054 12:27:56.689658 <8>[ 18.068880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11055 12:27:56.689962 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11057 12:27:56.703204 /lava-10605768/1/../bin/lava-test-case
11058 12:27:56.709469 <8>[ 18.088648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11059 12:27:56.709778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11061 12:27:56.719302 /lava-10605768/1/../bin/lava-test-case
11062 12:27:56.726185 <8>[ 18.105021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11063 12:27:56.726521 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11065 12:27:56.737360 /lava-10605768/1/../bin/lava-test-case
11066 12:27:56.743880 <8>[ 18.123031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11067 12:27:56.744181 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11069 12:27:56.753002 /lava-10605768/1/../bin/lava-test-case
11070 12:27:56.759409 <8>[ 18.139379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11071 12:27:56.759729 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11073 12:27:56.771208 /lava-10605768/1/../bin/lava-test-case
11074 12:27:56.777204 <8>[ 18.156975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11075 12:27:56.777513 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11077 12:27:56.786440 /lava-10605768/1/../bin/lava-test-case
11078 12:27:56.792837 <8>[ 18.172187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11079 12:27:56.793154 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11081 12:27:56.805458 /lava-10605768/1/../bin/lava-test-case
11082 12:27:56.812121 <8>[ 18.190997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11083 12:27:56.812467 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11085 12:27:56.822712 /lava-10605768/1/../bin/lava-test-case
11086 12:27:56.829388 <8>[ 18.208533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11087 12:27:56.829704 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11089 12:27:57.841080 /lava-10605768/1/../bin/lava-test-case
11090 12:27:57.847108 <8>[ 19.228247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11091 12:27:57.847442 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11093 12:27:58.860786 /lava-10605768/1/../bin/lava-test-case
11094 12:27:58.867245 <8>[ 20.247335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11095 12:27:58.867590 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11096 12:27:58.867700 Bad test result: blocked
11097 12:27:58.877045 /lava-10605768/1/../bin/lava-test-case
11098 12:27:58.883670 <8>[ 20.263573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11099 12:27:58.883997 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11101 12:27:58.895603 /lava-10605768/1/../bin/lava-test-case
11102 12:27:58.902038 <8>[ 20.281916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11103 12:27:58.902376 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11105 12:27:58.913764 /lava-10605768/1/../bin/lava-test-case
11106 12:27:58.920179 <8>[ 20.299468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11107 12:27:58.920464 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11109 12:27:58.930984 /lava-10605768/1/../bin/lava-test-case
11110 12:27:58.937310 <8>[ 20.316924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11111 12:27:58.937626 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11113 12:27:58.948271 /lava-10605768/1/../bin/lava-test-case
11114 12:27:58.955266 <8>[ 20.334402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11115 12:27:58.955587 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11117 12:27:58.966230 /lava-10605768/1/../bin/lava-test-case
11118 12:27:58.972902 <8>[ 20.352450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11119 12:27:58.973228 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11121 12:27:58.981676 /lava-10605768/1/../bin/lava-test-case
11122 12:27:58.988233 <8>[ 20.368126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11123 12:27:58.988578 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11125 12:27:58.999596 /lava-10605768/1/../bin/lava-test-case
11126 12:27:59.006081 <8>[ 20.385823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11127 12:27:59.006386 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11129 12:27:59.016928 /lava-10605768/1/../bin/lava-test-case
11130 12:27:59.023245 <8>[ 20.402869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11131 12:27:59.023568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11133 12:27:59.032263 /lava-10605768/1/../bin/lava-test-case
11134 12:27:59.039162 <8>[ 20.418424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11135 12:27:59.039484 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11137 12:27:59.050584 /lava-10605768/1/../bin/lava-test-case
11138 12:27:59.057560 <8>[ 20.436936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11139 12:27:59.057878 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11141 12:27:59.066579 /lava-10605768/1/../bin/lava-test-case
11142 12:27:59.073414 <8>[ 20.453052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11143 12:27:59.073717 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11145 12:27:59.085626 /lava-10605768/1/../bin/lava-test-case
11146 12:27:59.092339 <8>[ 20.471362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11147 12:27:59.092651 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11149 12:27:59.101461 /lava-10605768/1/../bin/lava-test-case
11150 12:27:59.107839 <8>[ 20.487597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11151 12:27:59.108139 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11153 12:27:59.120141 /lava-10605768/1/../bin/lava-test-case
11154 12:27:59.126477 <8>[ 20.505893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11155 12:27:59.126816 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11157 12:27:59.138341 /lava-10605768/1/../bin/lava-test-case
11158 12:27:59.145135 <8>[ 20.524377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11159 12:27:59.145447 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11161 12:27:59.156361 /lava-10605768/1/../bin/lava-test-case
11162 12:27:59.162685 <8>[ 20.542378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11163 12:27:59.163006 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11165 12:27:59.173789 /lava-10605768/1/../bin/lava-test-case
11166 12:27:59.180566 <8>[ 20.559992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11167 12:27:59.180894 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11169 12:27:59.191438 /lava-10605768/1/../bin/lava-test-case
11170 12:27:59.197500 <8>[ 20.577605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11171 12:27:59.197826 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11173 12:27:59.208970 /lava-10605768/1/../bin/lava-test-case
11174 12:27:59.216040 <8>[ 20.594981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11175 12:27:59.216357 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11177 12:27:59.226865 /lava-10605768/1/../bin/lava-test-case
11178 12:27:59.233057 <8>[ 20.612962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11179 12:27:59.233403 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11181 12:27:59.245045 /lava-10605768/1/../bin/lava-test-case
11182 12:27:59.251358 <8>[ 20.630359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11183 12:27:59.251662 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11185 12:27:59.262268 /lava-10605768/1/../bin/lava-test-case
11186 12:27:59.269021 <8>[ 20.648390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11187 12:27:59.269308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11189 12:27:59.280739 /lava-10605768/1/../bin/lava-test-case
11190 12:27:59.287257 <8>[ 20.666435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11191 12:27:59.287574 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11193 12:27:59.298043 /lava-10605768/1/../bin/lava-test-case
11194 12:27:59.304374 <8>[ 20.684798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11195 12:27:59.304684 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11197 12:27:59.316362 /lava-10605768/1/../bin/lava-test-case
11198 12:27:59.323112 <8>[ 20.702523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11199 12:27:59.323480 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11201 12:27:59.334317 /lava-10605768/1/../bin/lava-test-case
11202 12:27:59.340779 <8>[ 20.720411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11203 12:27:59.341140 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11205 12:27:59.351503 /lava-10605768/1/../bin/lava-test-case
11206 12:27:59.358437 <8>[ 20.737963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11207 12:27:59.358729 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11209 12:27:59.369267 /lava-10605768/1/../bin/lava-test-case
11210 12:27:59.375607 <8>[ 20.755763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11211 12:27:59.375900 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11213 12:27:59.384677 /lava-10605768/1/../bin/lava-test-case
11214 12:27:59.391606 <8>[ 20.771582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11215 12:27:59.391876 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11217 12:27:59.403022 /lava-10605768/1/../bin/lava-test-case
11218 12:27:59.409870 <8>[ 20.789752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11219 12:27:59.410141 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11221 12:27:59.418859 /lava-10605768/1/../bin/lava-test-case
11222 12:27:59.425666 <8>[ 20.805018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11223 12:27:59.425927 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11225 12:27:59.436536 /lava-10605768/1/../bin/lava-test-case
11226 12:27:59.442871 <8>[ 20.822935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11227 12:27:59.443134 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11229 12:27:59.451909 /lava-10605768/1/../bin/lava-test-case
11230 12:27:59.458352 <8>[ 20.838302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11231 12:27:59.458612 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11233 12:27:59.470326 /lava-10605768/1/../bin/lava-test-case
11234 12:27:59.477305 <8>[ 20.857002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11235 12:27:59.477614 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11237 12:27:59.487013 /lava-10605768/1/../bin/lava-test-case
11238 12:27:59.493644 <8>[ 20.873178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11239 12:27:59.493945 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11241 12:27:59.505431 /lava-10605768/1/../bin/lava-test-case
11242 12:27:59.512229 <8>[ 20.891376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11243 12:27:59.512529 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11245 12:27:59.520767 /lava-10605768/1/../bin/lava-test-case
11246 12:27:59.527587 <8>[ 20.907433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11247 12:27:59.527860 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11249 12:27:59.539456 /lava-10605768/1/../bin/lava-test-case
11250 12:27:59.545781 <8>[ 20.925648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11251 12:27:59.546079 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11253 12:27:59.554642 /lava-10605768/1/../bin/lava-test-case
11254 12:27:59.561712 <8>[ 20.940857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11255 12:27:59.561978 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11257 12:27:59.573316 /lava-10605768/1/../bin/lava-test-case
11258 12:27:59.579779 <8>[ 20.959170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11259 12:27:59.580074 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11261 12:27:59.591419 /lava-10605768/1/../bin/lava-test-case
11262 12:27:59.597697 <8>[ 20.977483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11263 12:27:59.597988 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11265 12:27:59.606688 /lava-10605768/1/../bin/lava-test-case
11266 12:27:59.613763 <8>[ 20.993100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11267 12:27:59.614054 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11269 12:27:59.624610 /lava-10605768/1/../bin/lava-test-case
11270 12:27:59.631217 <8>[ 21.011025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11271 12:27:59.631533 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11273 12:27:59.641090 /lava-10605768/1/../bin/lava-test-case
11274 12:27:59.647500 <8>[ 21.026849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11275 12:27:59.647791 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11277 12:27:59.659140 /lava-10605768/1/../bin/lava-test-case
11278 12:27:59.665335 <8>[ 21.045218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11279 12:27:59.665638 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11281 12:27:59.673760 /lava-10605768/1/../bin/lava-test-case
11282 12:27:59.680098 <8>[ 21.060668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11283 12:27:59.680387 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11285 12:28:00.694130 /lava-10605768/1/../bin/lava-test-case
11286 12:28:00.700783 <8>[ 22.080821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11287 12:28:00.701063 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11289 12:28:00.709892 /lava-10605768/1/../bin/lava-test-case
11290 12:28:00.716663 <8>[ 22.096404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11291 12:28:00.716927 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11293 12:28:01.729624 /lava-10605768/1/../bin/lava-test-case
11294 12:28:01.736606 <8>[ 23.117079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11295 12:28:01.736894 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11297 12:28:01.746048 /lava-10605768/1/../bin/lava-test-case
11298 12:28:01.753043 <8>[ 23.132741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11299 12:28:01.753317 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11301 12:28:02.767554 /lava-10605768/1/../bin/lava-test-case
11302 12:28:02.774321 <8>[ 24.155603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11303 12:28:02.774591 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11305 12:28:02.784888 /lava-10605768/1/../bin/lava-test-case
11306 12:28:02.791504 <8>[ 24.171302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11307 12:28:02.791763 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11309 12:28:03.805583 /lava-10605768/1/../bin/lava-test-case
11310 12:28:03.811707 <8>[ 25.192548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11311 12:28:03.811982 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11313 12:28:03.820750 /lava-10605768/1/../bin/lava-test-case
11314 12:28:03.827054 <8>[ 25.207409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11315 12:28:03.827318 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11317 12:28:04.840316 /lava-10605768/1/../bin/lava-test-case
11318 12:28:04.847344 <8>[ 26.228740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11319 12:28:04.847680 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11321 12:28:04.858086 /lava-10605768/1/../bin/lava-test-case
11322 12:28:04.864455 <8>[ 26.244343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11323 12:28:04.864740 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11325 12:28:05.877727 /lava-10605768/1/../bin/lava-test-case
11326 12:28:05.885074 <8>[ 27.265394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11327 12:28:05.885392 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11329 12:28:05.894454 /lava-10605768/1/../bin/lava-test-case
11330 12:28:05.900958 <8>[ 27.281620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11331 12:28:05.901249 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11333 12:28:06.914208 /lava-10605768/1/../bin/lava-test-case
11334 12:28:06.921176 <8>[ 28.301845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11335 12:28:06.921485 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11337 12:28:06.930675 /lava-10605768/1/../bin/lava-test-case
11338 12:28:06.936632 <8>[ 28.317184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11339 12:28:06.936905 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11341 12:28:06.946044 /lava-10605768/1/../bin/lava-test-case
11342 12:28:06.953023 <8>[ 28.333739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11343 12:28:06.953292 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11345 12:28:07.968201 /lava-10605768/1/../bin/lava-test-case
11346 12:28:07.974558 <8>[ 29.356147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11347 12:28:07.974857 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11349 12:28:07.985316 /lava-10605768/1/../bin/lava-test-case
11350 12:28:07.991563 <8>[ 29.372520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11351 12:28:07.991866 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11353 12:28:08.004308 /lava-10605768/1/../bin/lava-test-case
11354 12:28:08.010525 <8>[ 29.391929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11355 12:28:08.010821 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11357 12:28:08.020812 /lava-10605768/1/../bin/lava-test-case
11358 12:28:08.027532 <8>[ 29.407955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11359 12:28:08.027806 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11361 12:28:08.039510 /lava-10605768/1/../bin/lava-test-case
11362 12:28:08.045853 <8>[ 29.426982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11363 12:28:08.046145 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11365 12:28:08.057368 /lava-10605768/1/../bin/lava-test-case
11366 12:28:08.064358 <8>[ 29.445005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11367 12:28:08.064663 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11369 12:28:08.075893 /lava-10605768/1/../bin/lava-test-case
11370 12:28:08.082355 <8>[ 29.463462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11371 12:28:08.082665 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11373 12:28:08.091981 /lava-10605768/1/../bin/lava-test-case
11374 12:28:08.098734 <8>[ 29.479416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11375 12:28:08.099047 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11377 12:28:08.112174 /lava-10605768/1/../bin/lava-test-case
11378 12:28:08.118184 <8>[ 29.498910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11379 12:28:08.118484 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11381 12:28:08.129547 /lava-10605768/1/../bin/lava-test-case
11382 12:28:08.135656 <8>[ 29.516810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11383 12:28:08.135962 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11385 12:28:08.145809 /lava-10605768/1/../bin/lava-test-case
11386 12:28:08.152510 <8>[ 29.533560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11387 12:28:08.152833 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11389 12:28:08.164807 /lava-10605768/1/../bin/lava-test-case
11390 12:28:08.171215 <8>[ 29.551933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11391 12:28:08.171533 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11393 12:28:08.180973 /lava-10605768/1/../bin/lava-test-case
11394 12:28:08.187815 <8>[ 29.568636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11395 12:28:08.188111 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11397 12:28:08.200009 /lava-10605768/1/../bin/lava-test-case
11398 12:28:08.206707 <8>[ 29.587486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11399 12:28:08.207004 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11401 12:28:08.216394 /lava-10605768/1/../bin/lava-test-case
11402 12:28:08.222619 <8>[ 29.603468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11403 12:28:08.222923 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11405 12:28:08.235031 /lava-10605768/1/../bin/lava-test-case
11406 12:28:08.241699 <8>[ 29.622330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11407 12:28:08.241959 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11409 12:28:08.251577 /lava-10605768/1/../bin/lava-test-case
11410 12:28:08.258289 <8>[ 29.638613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11411 12:28:08.258593 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11413 12:28:08.270855 /lava-10605768/1/../bin/lava-test-case
11414 12:28:08.277251 <8>[ 29.658137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11415 12:28:08.277545 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11417 12:28:08.287375 /lava-10605768/1/../bin/lava-test-case
11418 12:28:08.293639 <8>[ 29.674260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11419 12:28:08.293980 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11421 12:28:08.305783 /lava-10605768/1/../bin/lava-test-case
11422 12:28:08.312709 <8>[ 29.693133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11423 12:28:08.313006 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11425 12:28:08.321691 /lava-10605768/1/../bin/lava-test-case
11426 12:28:08.328052 <8>[ 29.708894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11427 12:28:08.328344 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11429 12:28:09.342139 /lava-10605768/1/../bin/lava-test-case
11430 12:28:09.348977 <8>[ 30.730199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11431 12:28:09.349275 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11433 12:28:10.362271 /lava-10605768/1/../bin/lava-test-case
11434 12:28:10.368523 <8>[ 31.750186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11435 12:28:10.368801 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11437 12:28:10.377908 /lava-10605768/1/../bin/lava-test-case
11438 12:28:10.384240 <8>[ 31.765313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11439 12:28:10.384544 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11441 12:28:10.396308 /lava-10605768/1/../bin/lava-test-case
11442 12:28:10.402916 <8>[ 31.783960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11443 12:28:10.403215 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11445 12:28:10.412453 /lava-10605768/1/../bin/lava-test-case
11446 12:28:10.419278 <8>[ 31.799879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11447 12:28:10.419596 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11449 12:28:10.431099 /lava-10605768/1/../bin/lava-test-case
11450 12:28:10.438081 <8>[ 31.818217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11451 12:28:10.438374 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11453 12:28:10.447123 /lava-10605768/1/../bin/lava-test-case
11454 12:28:10.454239 <8>[ 31.834827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11455 12:28:10.454531 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11457 12:28:10.465220 /lava-10605768/1/../bin/lava-test-case
11458 12:28:10.471647 <8>[ 31.852399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11459 12:28:10.471938 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11461 12:28:10.480440 /lava-10605768/1/../bin/lava-test-case
11462 12:28:10.486656 <8>[ 31.867989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11463 12:28:10.486950 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11465 12:28:10.498036 /lava-10605768/1/../bin/lava-test-case
11466 12:28:10.505143 <8>[ 31.885520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11467 12:28:10.505413 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11469 12:28:10.513567 /lava-10605768/1/../bin/lava-test-case
11470 12:28:10.520265 <8>[ 31.901470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11471 12:28:10.520528 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11473 12:28:10.531377 /lava-10605768/1/../bin/lava-test-case
11474 12:28:10.538386 <8>[ 31.918894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11475 12:28:10.538702 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11477 12:28:10.547296 /lava-10605768/1/../bin/lava-test-case
11478 12:28:10.553586 <8>[ 31.934448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11479 12:28:10.553887 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11481 12:28:10.565351 /lava-10605768/1/../bin/lava-test-case
11482 12:28:10.572253 <8>[ 31.953672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11483 12:28:10.572545 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11485 12:28:10.581685 /lava-10605768/1/../bin/lava-test-case
11486 12:28:10.588203 <8>[ 31.969317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11487 12:28:10.588458 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11489 12:28:10.600109 /lava-10605768/1/../bin/lava-test-case
11490 12:28:10.606901 <8>[ 31.988241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11491 12:28:10.607166 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11493 12:28:10.616006 /lava-10605768/1/../bin/lava-test-case
11494 12:28:10.622557 <8>[ 32.003354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11495 12:28:10.622820 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11497 12:28:10.634066 /lava-10605768/1/../bin/lava-test-case
11498 12:28:10.640334 <8>[ 32.022012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11499 12:28:10.640600 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11501 12:28:10.649491 /lava-10605768/1/../bin/lava-test-case
11502 12:28:10.656585 <8>[ 32.037324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11503 12:28:10.656854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11505 12:28:10.668185 /lava-10605768/1/../bin/lava-test-case
11506 12:28:10.674500 <8>[ 32.055775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11507 12:28:10.674783 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11509 12:28:10.683427 /lava-10605768/1/../bin/lava-test-case
11510 12:28:10.690031 <8>[ 32.071307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11511 12:28:10.690325 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11513 12:28:10.702243 /lava-10605768/1/../bin/lava-test-case
11514 12:28:10.708623 <8>[ 32.089707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11515 12:28:10.708931 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11517 12:28:11.719969 /lava-10605768/1/../bin/lava-test-case
11518 12:28:11.726527 <8>[ 33.109006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11519 12:28:11.726840 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11521 12:28:12.740309 /lava-10605768/1/../bin/lava-test-case
11522 12:28:12.746698 <8>[ 34.128442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11523 12:28:12.746985 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11524 12:28:12.747110 Bad test result: blocked
11525 12:28:12.756186 /lava-10605768/1/../bin/lava-test-case
11526 12:28:12.763133 <8>[ 34.144841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11527 12:28:12.763446 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11529 12:28:13.777321 /lava-10605768/1/../bin/lava-test-case
11530 12:28:13.784276 <8>[ 35.165961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11531 12:28:13.784585 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11533 12:28:13.792669 /lava-10605768/1/../bin/lava-test-case
11534 12:28:13.799523 <8>[ 35.181420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11535 12:28:13.799822 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11537 12:28:13.811576 /lava-10605768/1/../bin/lava-test-case
11538 12:28:13.818161 <8>[ 35.200044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11539 12:28:13.818455 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11541 12:28:13.829786 /lava-10605768/1/../bin/lava-test-case
11542 12:28:13.836445 <8>[ 35.217697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11543 12:28:13.836737 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11545 12:28:13.844919 /lava-10605768/1/../bin/lava-test-case
11546 12:28:13.851578 <8>[ 35.233161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11547 12:28:13.851886 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11549 12:28:13.864055 /lava-10605768/1/../bin/lava-test-case
11550 12:28:13.870236 <8>[ 35.251598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11551 12:28:13.870501 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11553 12:28:13.879338 /lava-10605768/1/../bin/lava-test-case
11554 12:28:13.885466 <8>[ 35.267435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11555 12:28:13.885728 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11557 12:28:14.899479 /lava-10605768/1/../bin/lava-test-case
11558 12:28:14.905990 <8>[ 36.287666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11559 12:28:14.906298 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11561 12:28:14.915731 /lava-10605768/1/../bin/lava-test-case
11562 12:28:14.921865 <8>[ 36.304101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11563 12:28:14.922165 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11565 12:28:15.935432 /lava-10605768/1/../bin/lava-test-case
11566 12:28:15.942291 <8>[ 37.324176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11567 12:28:15.942623 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11569 12:28:15.951298 /lava-10605768/1/../bin/lava-test-case
11570 12:28:15.957452 <8>[ 37.339144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11571 12:28:15.957782 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11573 12:28:16.970352 /lava-10605768/1/../bin/lava-test-case
11574 12:28:16.977409 <8>[ 38.359138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11575 12:28:16.977718 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11577 12:28:16.986894 /lava-10605768/1/../bin/lava-test-case
11578 12:28:16.993081 <8>[ 38.374832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11579 12:28:16.993340 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11581 12:28:18.007279 /lava-10605768/1/../bin/lava-test-case
11582 12:28:18.013680 <8>[ 39.396466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11583 12:28:18.013954 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11585 12:28:18.024066 /lava-10605768/1/../bin/lava-test-case
11586 12:28:18.030786 <8>[ 39.412692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11587 12:28:18.031080 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11589 12:28:18.042385 /lava-10605768/1/../bin/lava-test-case
11590 12:28:18.048284 <8>[ 39.430803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11591 12:28:18.048554 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11593 12:28:18.059295 /lava-10605768/1/../bin/lava-test-case
11594 12:28:18.065700 <8>[ 39.448230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11595 12:28:18.066026 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11597 12:28:18.075486 /lava-10605768/1/../bin/lava-test-case
11598 12:28:18.082040 <8>[ 39.463885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11599 12:28:18.082338 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11601 12:28:18.093991 /lava-10605768/1/../bin/lava-test-case
11602 12:28:18.100287 <8>[ 39.482251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11603 12:28:18.100580 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11605 12:28:18.109613 /lava-10605768/1/../bin/lava-test-case
11606 12:28:18.116320 <8>[ 39.497643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11607 12:28:18.116613 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11609 12:28:18.128561 /lava-10605768/1/../bin/lava-test-case
11610 12:28:18.135207 <8>[ 39.516981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11611 12:28:18.135517 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11613 12:28:18.144804 /lava-10605768/1/../bin/lava-test-case
11614 12:28:18.151169 <8>[ 39.533024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11615 12:28:18.151434 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11617 12:28:19.165405 /lava-10605768/1/../bin/lava-test-case
11618 12:28:19.172878 <8>[ 40.555191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11619 12:28:19.173190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11621 12:28:19.177127 + set +x
11622 12:28:19.180397 Received signal: <ENDRUN> 1_bootrr 10605768_1.5.2.3.5
11623 12:28:19.180519 Ending use of test pattern.
11624 12:28:19.180618 Ending test lava.1_bootrr (10605768_1.5.2.3.5), duration 23.28
11626 12:28:19.183504 <8>[ 40.565408] <LAVA_SIGNAL_ENDRUN 1_bootrr 10605768_1.5.2.3.5>
11627 12:28:19.183614 <LAVA_TEST_RUNNER EXIT>
11628 12:28:19.183888 ok: lava_test_shell seems to have completed
11629 12:28:19.186238 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11630 12:28:19.186459 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11631 12:28:19.186582 end: 4 lava-test-retry (duration 00:00:24) [common]
11632 12:28:19.186713 start: 5 finalize (timeout 00:07:40) [common]
11633 12:28:19.186841 start: 5.1 power-off (timeout 00:00:30) [common]
11634 12:28:19.187135 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11635 12:28:19.264309 >> Command sent successfully.
11636 12:28:19.267149 Returned 0 in 0 seconds
11637 12:28:19.367506 end: 5.1 power-off (duration 00:00:00) [common]
11639 12:28:19.367855 start: 5.2 read-feedback (timeout 00:07:40) [common]
11640 12:28:19.368114 Listened to connection for namespace 'common' for up to 1s
11641 12:28:19.368398 Listened to connection for namespace 'common' for up to 1s
11642 12:28:20.369037 Finalising connection for namespace 'common'
11643 12:28:20.369260 Disconnecting from shell: Finalise
11644 12:28:20.369378 / #
11645 12:28:20.469719 end: 5.2 read-feedback (duration 00:00:01) [common]
11646 12:28:20.469952 end: 5 finalize (duration 00:00:01) [common]
11647 12:28:20.470117 Cleaning after the job
11648 12:28:20.470263 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/ramdisk
11649 12:28:20.472874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/kernel
11650 12:28:20.478768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/dtb
11651 12:28:20.478949 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605768/tftp-deploy-w2z48eio/modules
11652 12:28:20.484326 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605768
11653 12:28:20.522155 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605768
11654 12:28:20.522338 Job finished correctly