Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 30
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 23
1 12:29:18.729250 lava-dispatcher, installed at version: 2023.05.1
2 12:29:18.729455 start: 0 validate
3 12:29:18.729583 Start time: 2023-06-06 12:29:18.729575+00:00 (UTC)
4 12:29:18.729705 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:29:18.729834 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:29:19.022554 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:29:19.023394 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:29:19.319686 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:29:19.320504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:29:19.619172 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:29:19.619926 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:29:19.912469 validate duration: 1.18
14 12:29:19.912769 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:29:19.912868 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:29:19.912954 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:29:19.913079 Not decompressing ramdisk as can be used compressed.
18 12:29:19.913163 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 12:29:19.913228 saving as /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/ramdisk/rootfs.cpio.gz
20 12:29:19.913290 total size: 43394293 (41MB)
21 12:29:19.914303 progress 0% (0MB)
22 12:29:19.925379 progress 5% (2MB)
23 12:29:19.936283 progress 10% (4MB)
24 12:29:19.947316 progress 15% (6MB)
25 12:29:19.958256 progress 20% (8MB)
26 12:29:19.969478 progress 25% (10MB)
27 12:29:19.980399 progress 30% (12MB)
28 12:29:19.991265 progress 35% (14MB)
29 12:29:20.002148 progress 40% (16MB)
30 12:29:20.013050 progress 45% (18MB)
31 12:29:20.024122 progress 50% (20MB)
32 12:29:20.035279 progress 55% (22MB)
33 12:29:20.046498 progress 60% (24MB)
34 12:29:20.057568 progress 65% (26MB)
35 12:29:20.068959 progress 70% (29MB)
36 12:29:20.079929 progress 75% (31MB)
37 12:29:20.090758 progress 80% (33MB)
38 12:29:20.101860 progress 85% (35MB)
39 12:29:20.112848 progress 90% (37MB)
40 12:29:20.123772 progress 95% (39MB)
41 12:29:20.134520 progress 100% (41MB)
42 12:29:20.134713 41MB downloaded in 0.22s (186.90MB/s)
43 12:29:20.134931 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:29:20.135187 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:29:20.135276 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:29:20.135364 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:29:20.135500 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:29:20.135575 saving as /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/kernel/Image
50 12:29:20.135638 total size: 45746688 (43MB)
51 12:29:20.135700 No compression specified
52 12:29:20.136816 progress 0% (0MB)
53 12:29:20.148535 progress 5% (2MB)
54 12:29:20.160418 progress 10% (4MB)
55 12:29:20.172062 progress 15% (6MB)
56 12:29:20.183604 progress 20% (8MB)
57 12:29:20.195168 progress 25% (10MB)
58 12:29:20.206883 progress 30% (13MB)
59 12:29:20.218404 progress 35% (15MB)
60 12:29:20.229935 progress 40% (17MB)
61 12:29:20.241622 progress 45% (19MB)
62 12:29:20.253601 progress 50% (21MB)
63 12:29:20.265307 progress 55% (24MB)
64 12:29:20.277037 progress 60% (26MB)
65 12:29:20.288638 progress 65% (28MB)
66 12:29:20.300230 progress 70% (30MB)
67 12:29:20.312032 progress 75% (32MB)
68 12:29:20.323431 progress 80% (34MB)
69 12:29:20.335014 progress 85% (37MB)
70 12:29:20.346547 progress 90% (39MB)
71 12:29:20.358190 progress 95% (41MB)
72 12:29:20.369878 progress 100% (43MB)
73 12:29:20.370062 43MB downloaded in 0.23s (186.11MB/s)
74 12:29:20.370222 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:29:20.370522 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:29:20.370609 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:29:20.370699 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:29:20.370869 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:29:20.370941 saving as /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/dtb/mt8192-asurada-spherion-r0.dtb
81 12:29:20.371004 total size: 46924 (0MB)
82 12:29:20.371072 No compression specified
83 12:29:20.372216 progress 69% (0MB)
84 12:29:20.372560 progress 100% (0MB)
85 12:29:20.372716 0MB downloaded in 0.00s (26.17MB/s)
86 12:29:20.372886 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:29:20.373123 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:29:20.373208 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:29:20.373290 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:29:20.373398 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:29:20.373467 saving as /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/modules/modules.tar
93 12:29:20.373528 total size: 8539116 (8MB)
94 12:29:20.373588 Using unxz to decompress xz
95 12:29:20.377301 progress 0% (0MB)
96 12:29:20.399035 progress 5% (0MB)
97 12:29:20.424105 progress 10% (0MB)
98 12:29:20.447347 progress 15% (1MB)
99 12:29:20.474976 progress 20% (1MB)
100 12:29:20.501345 progress 25% (2MB)
101 12:29:20.527931 progress 30% (2MB)
102 12:29:20.555341 progress 35% (2MB)
103 12:29:20.583153 progress 40% (3MB)
104 12:29:20.610549 progress 45% (3MB)
105 12:29:20.639113 progress 50% (4MB)
106 12:29:20.665338 progress 55% (4MB)
107 12:29:20.692743 progress 60% (4MB)
108 12:29:20.720650 progress 65% (5MB)
109 12:29:20.746747 progress 70% (5MB)
110 12:29:20.773397 progress 75% (6MB)
111 12:29:20.805309 progress 80% (6MB)
112 12:29:20.827987 progress 85% (6MB)
113 12:29:20.852444 progress 90% (7MB)
114 12:29:20.877361 progress 95% (7MB)
115 12:29:20.902076 progress 100% (8MB)
116 12:29:20.907745 8MB downloaded in 0.53s (15.24MB/s)
117 12:29:20.908058 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:29:20.908328 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:29:20.908422 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:29:20.908523 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:29:20.908613 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:29:20.908704 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:29:20.908982 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv
125 12:29:20.909112 makedir: /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin
126 12:29:20.909216 makedir: /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/tests
127 12:29:20.909349 makedir: /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/results
128 12:29:20.909465 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-add-keys
129 12:29:20.909611 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-add-sources
130 12:29:20.909738 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-background-process-start
131 12:29:20.909867 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-background-process-stop
132 12:29:20.909993 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-common-functions
133 12:29:20.910117 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-echo-ipv4
134 12:29:20.910240 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-install-packages
135 12:29:20.910362 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-installed-packages
136 12:29:20.910482 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-os-build
137 12:29:20.910609 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-probe-channel
138 12:29:20.910731 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-probe-ip
139 12:29:20.910892 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-target-ip
140 12:29:20.911016 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-target-mac
141 12:29:20.911137 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-target-storage
142 12:29:20.911392 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-case
143 12:29:20.911553 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-event
144 12:29:20.911675 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-feedback
145 12:29:20.911798 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-raise
146 12:29:20.911924 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-reference
147 12:29:20.912047 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-runner
148 12:29:20.912169 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-set
149 12:29:20.912292 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-test-shell
150 12:29:20.912415 Updating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-install-packages (oe)
151 12:29:20.912571 Updating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/bin/lava-installed-packages (oe)
152 12:29:20.912697 Creating /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/environment
153 12:29:20.912802 LAVA metadata
154 12:29:20.912878 - LAVA_JOB_ID=10605798
155 12:29:20.912945 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:29:20.913052 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:29:20.913122 skipped lava-vland-overlay
158 12:29:20.913238 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:29:20.913352 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:29:20.913416 skipped lava-multinode-overlay
161 12:29:20.913491 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:29:20.913572 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:29:20.913648 Loading test definitions
164 12:29:20.913737 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:29:20.913811 Using /lava-10605798 at stage 0
166 12:29:20.914189 uuid=10605798_1.5.2.3.1 testdef=None
167 12:29:20.914280 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:29:20.914370 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:29:20.914924 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:29:20.915148 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:29:20.915800 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:29:20.916036 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:29:20.916676 runner path: /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/0/tests/0_igt-gpu-panfrost test_uuid 10605798_1.5.2.3.1
176 12:29:20.916858 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:29:20.917069 Creating lava-test-runner.conf files
179 12:29:20.917135 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605798/lava-overlay-1y0504gv/lava-10605798/0 for stage 0
180 12:29:20.917249 - 0_igt-gpu-panfrost
181 12:29:20.917390 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:29:20.917474 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:29:20.924584 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:29:20.924714 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:29:20.924807 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:29:20.924898 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:29:20.924991 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:29:22.296706 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:29:22.297109 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:29:22.297246 extracting modules file /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605798/extract-overlay-ramdisk-t_3uwb7n/ramdisk
191 12:29:22.524137 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:29:22.524306 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:29:22.524404 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605798/compress-overlay-ny96vcan/overlay-1.5.2.4.tar.gz to ramdisk
194 12:29:22.524479 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605798/compress-overlay-ny96vcan/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605798/extract-overlay-ramdisk-t_3uwb7n/ramdisk
195 12:29:22.531073 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:29:22.531202 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:29:22.531302 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:29:22.531395 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:29:22.531483 Building ramdisk /var/lib/lava/dispatcher/tmp/10605798/extract-overlay-ramdisk-t_3uwb7n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605798/extract-overlay-ramdisk-t_3uwb7n/ramdisk
200 12:29:23.429257 >> 369045 blocks
201 12:29:29.637113 rename /var/lib/lava/dispatcher/tmp/10605798/extract-overlay-ramdisk-t_3uwb7n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/ramdisk/ramdisk.cpio.gz
202 12:29:29.637721 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:29:29.637937 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 12:29:29.638119 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 12:29:29.638317 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/kernel/Image'
206 12:29:41.605617 Returned 0 in 11 seconds
207 12:29:41.706300 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/kernel/image.itb
208 12:29:42.614078 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:29:42.614446 output: Created: Tue Jun 6 13:29:42 2023
210 12:29:42.614595 output: Image 0 (kernel-1)
211 12:29:42.614690 output: Description:
212 12:29:42.614784 output: Created: Tue Jun 6 13:29:42 2023
213 12:29:42.614901 output: Type: Kernel Image
214 12:29:42.614963 output: Compression: lzma compressed
215 12:29:42.615024 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
216 12:29:42.615084 output: Architecture: AArch64
217 12:29:42.615142 output: OS: Linux
218 12:29:42.615208 output: Load Address: 0x00000000
219 12:29:42.615299 output: Entry Point: 0x00000000
220 12:29:42.615359 output: Hash algo: crc32
221 12:29:42.615414 output: Hash value: a26c3f91
222 12:29:42.615467 output: Image 1 (fdt-1)
223 12:29:42.615545 output: Description: mt8192-asurada-spherion-r0
224 12:29:42.615638 output: Created: Tue Jun 6 13:29:42 2023
225 12:29:42.615722 output: Type: Flat Device Tree
226 12:29:42.615805 output: Compression: uncompressed
227 12:29:42.615887 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:29:42.615970 output: Architecture: AArch64
229 12:29:42.616052 output: Hash algo: crc32
230 12:29:42.616133 output: Hash value: 1df858fa
231 12:29:42.616216 output: Image 2 (ramdisk-1)
232 12:29:42.616298 output: Description: unavailable
233 12:29:42.616380 output: Created: Tue Jun 6 13:29:42 2023
234 12:29:42.616462 output: Type: RAMDisk Image
235 12:29:42.616544 output: Compression: Unknown Compression
236 12:29:42.616626 output: Data Size: 56352159 Bytes = 55031.41 KiB = 53.74 MiB
237 12:29:42.616709 output: Architecture: AArch64
238 12:29:42.616791 output: OS: Linux
239 12:29:42.616872 output: Load Address: unavailable
240 12:29:42.616954 output: Entry Point: unavailable
241 12:29:42.617036 output: Hash algo: crc32
242 12:29:42.617119 output: Hash value: a4de2359
243 12:29:42.617194 output: Default Configuration: 'conf-1'
244 12:29:42.617290 output: Configuration 0 (conf-1)
245 12:29:42.617372 output: Description: mt8192-asurada-spherion-r0
246 12:29:42.617454 output: Kernel: kernel-1
247 12:29:42.617536 output: Init Ramdisk: ramdisk-1
248 12:29:42.617617 output: FDT: fdt-1
249 12:29:42.617698 output: Loadables: kernel-1
250 12:29:42.617780 output:
251 12:29:42.618004 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:29:42.618130 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:29:42.618266 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:29:42.618394 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 12:29:42.618495 No LXC device requested
256 12:29:42.618604 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:29:42.618723 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 12:29:42.618834 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:29:42.618966 Checking files for TFTP limit of 4294967296 bytes.
260 12:29:42.619596 end: 1 tftp-deploy (duration 00:00:23) [common]
261 12:29:42.619702 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:29:42.619796 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:29:42.619919 substitutions:
264 12:29:42.619986 - {DTB}: 10605798/tftp-deploy-baj79x3r/dtb/mt8192-asurada-spherion-r0.dtb
265 12:29:42.620051 - {INITRD}: 10605798/tftp-deploy-baj79x3r/ramdisk/ramdisk.cpio.gz
266 12:29:42.620110 - {KERNEL}: 10605798/tftp-deploy-baj79x3r/kernel/Image
267 12:29:42.620167 - {LAVA_MAC}: None
268 12:29:42.620223 - {PRESEED_CONFIG}: None
269 12:29:42.620278 - {PRESEED_LOCAL}: None
270 12:29:42.620333 - {RAMDISK}: 10605798/tftp-deploy-baj79x3r/ramdisk/ramdisk.cpio.gz
271 12:29:42.620388 - {ROOT_PART}: None
272 12:29:42.620442 - {ROOT}: None
273 12:29:42.620497 - {SERVER_IP}: 192.168.201.1
274 12:29:42.620554 - {TEE}: None
275 12:29:42.620674 Parsed boot commands:
276 12:29:42.620760 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:29:42.620926 Parsed boot commands: tftpboot 192.168.201.1 10605798/tftp-deploy-baj79x3r/kernel/image.itb 10605798/tftp-deploy-baj79x3r/kernel/cmdline
278 12:29:42.621016 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:29:42.621105 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:29:42.621196 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:29:42.621283 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:29:42.621365 Not connected, no need to disconnect.
283 12:29:42.621473 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:29:42.621554 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:29:42.621624 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 12:29:42.625059 Setting prompt string to ['lava-test: # ']
287 12:29:42.625405 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:29:42.625514 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:29:42.625610 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:29:42.625702 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:29:42.625902 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 12:29:47.756796 >> Command sent successfully.
293 12:29:47.759252 Returned 0 in 5 seconds
294 12:29:47.859651 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:29:47.860240 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:29:47.860341 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:29:47.860431 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:29:47.860502 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:29:47.860574 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:29:47.860846 [Enter `^Ec?' for help]
302 12:29:48.032074
303 12:29:48.032230
304 12:29:48.032310 F0: 102B 0000
305 12:29:48.032376
306 12:29:48.032438 F3: 1001 0000 [0200]
307 12:29:48.032498
308 12:29:48.035821 F3: 1001 0000
309 12:29:48.035907
310 12:29:48.035977 F7: 102D 0000
311 12:29:48.036042
312 12:29:48.036104 F1: 0000 0000
313 12:29:48.039622
314 12:29:48.039707 V0: 0000 0000 [0001]
315 12:29:48.039777
316 12:29:48.039841 00: 0007 8000
317 12:29:48.039906
318 12:29:48.043321 01: 0000 0000
319 12:29:48.043425
320 12:29:48.043507 BP: 0C00 0209 [0000]
321 12:29:48.043570
322 12:29:48.046960 G0: 1182 0000
323 12:29:48.047045
324 12:29:48.047112 EC: 0000 0021 [4000]
325 12:29:48.047177
326 12:29:48.051028 S7: 0000 0000 [0000]
327 12:29:48.051113
328 12:29:48.051181 CC: 0000 0000 [0001]
329 12:29:48.051245
330 12:29:48.054435 T0: 0000 0040 [010F]
331 12:29:48.054522
332 12:29:48.054591 Jump to BL
333 12:29:48.054653
334 12:29:48.078982
335 12:29:48.079095
336 12:29:48.079192
337 12:29:48.086044 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:29:48.089188 ARM64: Exception handlers installed.
339 12:29:48.092609 ARM64: Testing exception
340 12:29:48.096013 ARM64: Done test exception
341 12:29:48.103591 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:29:48.114311 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:29:48.121602 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:29:48.131710 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:29:48.138507 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:29:48.144533 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:29:48.155531 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:29:48.162421 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:29:48.181815 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:29:48.185476 WDT: Last reset was cold boot
351 12:29:48.188429 SPI1(PAD0) initialized at 2873684 Hz
352 12:29:48.192079 SPI5(PAD0) initialized at 992727 Hz
353 12:29:48.195106 VBOOT: Loading verstage.
354 12:29:48.201472 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:29:48.205073 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:29:48.208517 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:29:48.211444 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:29:48.219632 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:29:48.225766 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:29:48.237025 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
361 12:29:48.237126
362 12:29:48.237196
363 12:29:48.246917 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:29:48.249966 ARM64: Exception handlers installed.
365 12:29:48.253652 ARM64: Testing exception
366 12:29:48.253731 ARM64: Done test exception
367 12:29:48.260459 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:29:48.263467 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:29:48.277485 Probing TPM: . done!
370 12:29:48.277606 TPM ready after 0 ms
371 12:29:48.284306 Connected to device vid:did:rid of 1ae0:0028:00
372 12:29:48.294411 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:29:48.294506 Initialized TPM device CR50 revision 0
374 12:29:48.346022 tlcl_send_startup: Startup return code is 0
375 12:29:48.346169 TPM: setup succeeded
376 12:29:48.356873 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:29:48.366031 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:29:48.377430 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:29:48.386904 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:29:48.390042 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:29:48.393390 in-header: 03 07 00 00 08 00 00 00
382 12:29:48.396389 in-data: aa e4 47 04 13 02 00 00
383 12:29:48.400004 Chrome EC: UHEPI supported
384 12:29:48.407747 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:29:48.411145 in-header: 03 9d 00 00 08 00 00 00
386 12:29:48.414569 in-data: 10 20 20 08 00 00 00 00
387 12:29:48.414687 Phase 1
388 12:29:48.418271 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:29:48.425829 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:29:48.433259 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:29:48.433351 Recovery requested (1009000e)
392 12:29:48.441553 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:29:48.446953 tlcl_extend: response is 0
394 12:29:48.454796 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:29:48.460360 tlcl_extend: response is 0
396 12:29:48.466404 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:29:48.488094 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
398 12:29:48.495539 BS: bootblock times (exec / console): total (unknown) / 149 ms
399 12:29:48.495641
400 12:29:48.495711
401 12:29:48.502956 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:29:48.506631 ARM64: Exception handlers installed.
403 12:29:48.510692 ARM64: Testing exception
404 12:29:48.510779 ARM64: Done test exception
405 12:29:48.532931 pmic_efuse_setting: Set efuses in 11 msecs
406 12:29:48.536503 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:29:48.543887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:29:48.547586 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:29:48.550822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:29:48.558078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:29:48.561854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:29:48.565057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:29:48.572106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:29:48.575909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:29:48.579072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:29:48.585690 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:29:48.588799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:29:48.595490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:29:48.599189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:29:48.605692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:29:48.612152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:29:48.615567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:29:48.621966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:29:48.628489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:29:48.632505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:29:48.639423 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:29:48.642822 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:29:48.650182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:29:48.657065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:29:48.660262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:29:48.667437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:29:48.673933 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:29:48.677031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:29:48.680184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:29:48.686793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:29:48.690527 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:29:48.697898 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:29:48.700984 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:29:48.708330 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:29:48.711913 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:29:48.715668 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:29:48.723491 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:29:48.727258 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:29:48.730263 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:29:48.736800 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:29:48.740387 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:29:48.743770 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:29:48.750255 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:29:48.753873 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:29:48.757013 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:29:48.763786 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:29:48.766770 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:29:48.770436 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:29:48.777043 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:29:48.780140 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:29:48.783901 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:29:48.786949 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:29:48.796749 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:29:48.803395 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:29:48.810126 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:29:48.816812 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:29:48.826779 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:29:48.829767 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:29:48.833379 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:29:48.839703 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:29:48.846851 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 12:29:48.849866 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:29:48.857370 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:29:48.860391 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:29:48.870275 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 12:29:48.873372 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 12:29:48.879870 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 12:29:48.883528 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 12:29:48.886702 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 12:29:48.889814 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 12:29:48.893373 ADC[4]: Raw value=899260 ID=7
477 12:29:48.896338 ADC[3]: Raw value=212330 ID=1
478 12:29:48.900052 RAM Code: 0x71
479 12:29:48.902932 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 12:29:48.906753 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 12:29:48.916652 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 12:29:48.923359 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 12:29:48.926405 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 12:29:48.930121 in-header: 03 07 00 00 08 00 00 00
485 12:29:48.933014 in-data: aa e4 47 04 13 02 00 00
486 12:29:48.936540 Chrome EC: UHEPI supported
487 12:29:48.943803 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 12:29:48.947575 in-header: 03 d5 00 00 08 00 00 00
489 12:29:48.950817 in-data: 98 20 60 08 00 00 00 00
490 12:29:48.950924 MRC: failed to locate region type 0.
491 12:29:48.958003 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 12:29:48.961434 DRAM-K: Running full calibration
493 12:29:48.968090 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 12:29:48.971276 header.status = 0x0
495 12:29:48.975061 header.version = 0x6 (expected: 0x6)
496 12:29:48.978795 header.size = 0xd00 (expected: 0xd00)
497 12:29:48.978925 header.flags = 0x0
498 12:29:48.985048 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 12:29:49.002765 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
500 12:29:49.010287 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 12:29:49.010374 dram_init: ddr_geometry: 2
502 12:29:49.014125 [EMI] MDL number = 2
503 12:29:49.018217 [EMI] Get MDL freq = 0
504 12:29:49.018303 dram_init: ddr_type: 0
505 12:29:49.021711 is_discrete_lpddr4: 1
506 12:29:49.025627 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 12:29:49.025711
508 12:29:49.025779
509 12:29:49.025843 [Bian_co] ETT version 0.0.0.1
510 12:29:49.032837 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 12:29:49.032923
512 12:29:49.036372 dramc_set_vcore_voltage set vcore to 650000
513 12:29:49.036503 Read voltage for 800, 4
514 12:29:49.039943 Vio18 = 0
515 12:29:49.040026 Vcore = 650000
516 12:29:49.040094 Vdram = 0
517 12:29:49.040157 Vddq = 0
518 12:29:49.043570 Vmddr = 0
519 12:29:49.043654 dram_init: config_dvfs: 1
520 12:29:49.051266 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 12:29:49.055017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 12:29:49.059113 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 12:29:49.062754 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 12:29:49.066252 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 12:29:49.069920 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 12:29:49.073578 MEM_TYPE=3, freq_sel=18
527 12:29:49.073663 sv_algorithm_assistance_LP4_1600
528 12:29:49.081116 ============ PULL DRAM RESETB DOWN ============
529 12:29:49.084558 ========== PULL DRAM RESETB DOWN end =========
530 12:29:49.087566 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 12:29:49.091172 ===================================
532 12:29:49.094298 LPDDR4 DRAM CONFIGURATION
533 12:29:49.098112 ===================================
534 12:29:49.098196 EX_ROW_EN[0] = 0x0
535 12:29:49.101173 EX_ROW_EN[1] = 0x0
536 12:29:49.104142 LP4Y_EN = 0x0
537 12:29:49.104226 WORK_FSP = 0x0
538 12:29:49.107639 WL = 0x2
539 12:29:49.107724 RL = 0x2
540 12:29:49.111420 BL = 0x2
541 12:29:49.111504 RPST = 0x0
542 12:29:49.114420 RD_PRE = 0x0
543 12:29:49.114554 WR_PRE = 0x1
544 12:29:49.117739 WR_PST = 0x0
545 12:29:49.117822 DBI_WR = 0x0
546 12:29:49.120771 DBI_RD = 0x0
547 12:29:49.120854 OTF = 0x1
548 12:29:49.124464 ===================================
549 12:29:49.127555 ===================================
550 12:29:49.130697 ANA top config
551 12:29:49.134267 ===================================
552 12:29:49.137310 DLL_ASYNC_EN = 0
553 12:29:49.137393 ALL_SLAVE_EN = 1
554 12:29:49.140563 NEW_RANK_MODE = 1
555 12:29:49.144193 DLL_IDLE_MODE = 1
556 12:29:49.147117 LP45_APHY_COMB_EN = 1
557 12:29:49.147196 TX_ODT_DIS = 1
558 12:29:49.150742 NEW_8X_MODE = 1
559 12:29:49.154251 ===================================
560 12:29:49.157288 ===================================
561 12:29:49.160341 data_rate = 1600
562 12:29:49.163930 CKR = 1
563 12:29:49.167457 DQ_P2S_RATIO = 8
564 12:29:49.170406 ===================================
565 12:29:49.174009 CA_P2S_RATIO = 8
566 12:29:49.174092 DQ_CA_OPEN = 0
567 12:29:49.177084 DQ_SEMI_OPEN = 0
568 12:29:49.180696 CA_SEMI_OPEN = 0
569 12:29:49.183761 CA_FULL_RATE = 0
570 12:29:49.186825 DQ_CKDIV4_EN = 1
571 12:29:49.190798 CA_CKDIV4_EN = 1
572 12:29:49.190932 CA_PREDIV_EN = 0
573 12:29:49.194035 PH8_DLY = 0
574 12:29:49.197013 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 12:29:49.200479 DQ_AAMCK_DIV = 4
576 12:29:49.203462 CA_AAMCK_DIV = 4
577 12:29:49.207160 CA_ADMCK_DIV = 4
578 12:29:49.207244 DQ_TRACK_CA_EN = 0
579 12:29:49.210643 CA_PICK = 800
580 12:29:49.214035 CA_MCKIO = 800
581 12:29:49.216891 MCKIO_SEMI = 0
582 12:29:49.220569 PLL_FREQ = 3068
583 12:29:49.223777 DQ_UI_PI_RATIO = 32
584 12:29:49.226806 CA_UI_PI_RATIO = 0
585 12:29:49.230590 ===================================
586 12:29:49.233085 ===================================
587 12:29:49.233169 memory_type:LPDDR4
588 12:29:49.236884 GP_NUM : 10
589 12:29:49.239930 SRAM_EN : 1
590 12:29:49.240014 MD32_EN : 0
591 12:29:49.243067 ===================================
592 12:29:49.246383 [ANA_INIT] >>>>>>>>>>>>>>
593 12:29:49.249866 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 12:29:49.253333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 12:29:49.256311 ===================================
596 12:29:49.259815 data_rate = 1600,PCW = 0X7600
597 12:29:49.263314 ===================================
598 12:29:49.266818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:29:49.269725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 12:29:49.276775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 12:29:49.279669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 12:29:49.283267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 12:29:49.287030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 12:29:49.290710 [ANA_INIT] flow start
605 12:29:49.290794 [ANA_INIT] PLL >>>>>>>>
606 12:29:49.293838 [ANA_INIT] PLL <<<<<<<<
607 12:29:49.297608 [ANA_INIT] MIDPI >>>>>>>>
608 12:29:49.297693 [ANA_INIT] MIDPI <<<<<<<<
609 12:29:49.301265 [ANA_INIT] DLL >>>>>>>>
610 12:29:49.304451 [ANA_INIT] flow end
611 12:29:49.308070 ============ LP4 DIFF to SE enter ============
612 12:29:49.312202 ============ LP4 DIFF to SE exit ============
613 12:29:49.315853 [ANA_INIT] <<<<<<<<<<<<<
614 12:29:49.315938 [Flow] Enable top DCM control >>>>>
615 12:29:49.319629 [Flow] Enable top DCM control <<<<<
616 12:29:49.323291 Enable DLL master slave shuffle
617 12:29:49.330139 ==============================================================
618 12:29:49.330225 Gating Mode config
619 12:29:49.337026 ==============================================================
620 12:29:49.337111 Config description:
621 12:29:49.346779 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 12:29:49.353496 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 12:29:49.360248 SELPH_MODE 0: By rank 1: By Phase
624 12:29:49.363660 ==============================================================
625 12:29:49.366797 GAT_TRACK_EN = 1
626 12:29:49.370182 RX_GATING_MODE = 2
627 12:29:49.373460 RX_GATING_TRACK_MODE = 2
628 12:29:49.376858 SELPH_MODE = 1
629 12:29:49.380161 PICG_EARLY_EN = 1
630 12:29:49.383008 VALID_LAT_VALUE = 1
631 12:29:49.389934 ==============================================================
632 12:29:49.393002 Enter into Gating configuration >>>>
633 12:29:49.396673 Exit from Gating configuration <<<<
634 12:29:49.396782 Enter into DVFS_PRE_config >>>>>
635 12:29:49.410301 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 12:29:49.412980 Exit from DVFS_PRE_config <<<<<
637 12:29:49.416337 Enter into PICG configuration >>>>
638 12:29:49.419976 Exit from PICG configuration <<<<
639 12:29:49.420062 [RX_INPUT] configuration >>>>>
640 12:29:49.423012 [RX_INPUT] configuration <<<<<
641 12:29:49.430144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 12:29:49.432967 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 12:29:49.439647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 12:29:49.446071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 12:29:49.452881 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 12:29:49.460270 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 12:29:49.463477 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 12:29:49.467350 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 12:29:49.470758 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 12:29:49.474370 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 12:29:49.478007 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 12:29:49.485191 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 12:29:49.488511 ===================================
654 12:29:49.488620 LPDDR4 DRAM CONFIGURATION
655 12:29:49.492460 ===================================
656 12:29:49.495910 EX_ROW_EN[0] = 0x0
657 12:29:49.496013 EX_ROW_EN[1] = 0x0
658 12:29:49.499509 LP4Y_EN = 0x0
659 12:29:49.499587 WORK_FSP = 0x0
660 12:29:49.503305 WL = 0x2
661 12:29:49.503434 RL = 0x2
662 12:29:49.506440 BL = 0x2
663 12:29:49.506559 RPST = 0x0
664 12:29:49.510160 RD_PRE = 0x0
665 12:29:49.510277 WR_PRE = 0x1
666 12:29:49.513670 WR_PST = 0x0
667 12:29:49.513784 DBI_WR = 0x0
668 12:29:49.517549 DBI_RD = 0x0
669 12:29:49.517638 OTF = 0x1
670 12:29:49.520833 ===================================
671 12:29:49.524906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 12:29:49.528011 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 12:29:49.532079 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 12:29:49.535585 ===================================
675 12:29:49.539334 LPDDR4 DRAM CONFIGURATION
676 12:29:49.542976 ===================================
677 12:29:49.543064 EX_ROW_EN[0] = 0x10
678 12:29:49.547062 EX_ROW_EN[1] = 0x0
679 12:29:49.547143 LP4Y_EN = 0x0
680 12:29:49.550563 WORK_FSP = 0x0
681 12:29:49.550666 WL = 0x2
682 12:29:49.554434 RL = 0x2
683 12:29:49.554511 BL = 0x2
684 12:29:49.557559 RPST = 0x0
685 12:29:49.557631 RD_PRE = 0x0
686 12:29:49.561788 WR_PRE = 0x1
687 12:29:49.561885 WR_PST = 0x0
688 12:29:49.565488 DBI_WR = 0x0
689 12:29:49.565566 DBI_RD = 0x0
690 12:29:49.569138 OTF = 0x1
691 12:29:49.569213 ===================================
692 12:29:49.576070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 12:29:49.580609 nWR fixed to 40
694 12:29:49.584697 [ModeRegInit_LP4] CH0 RK0
695 12:29:49.584786 [ModeRegInit_LP4] CH0 RK1
696 12:29:49.588232 [ModeRegInit_LP4] CH1 RK0
697 12:29:49.588345 [ModeRegInit_LP4] CH1 RK1
698 12:29:49.591696 match AC timing 13
699 12:29:49.595292 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 12:29:49.598719 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 12:29:49.606058 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 12:29:49.608999 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 12:29:49.612825 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 12:29:49.616470 [EMI DOE] emi_dcm 0
705 12:29:49.619950 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 12:29:49.620044 ==
707 12:29:49.623803 Dram Type= 6, Freq= 0, CH_0, rank 0
708 12:29:49.627407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 12:29:49.627498 ==
710 12:29:49.634959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 12:29:49.638169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 12:29:49.648737 [CA 0] Center 38 (7~69) winsize 63
713 12:29:49.652491 [CA 1] Center 37 (7~68) winsize 62
714 12:29:49.656243 [CA 2] Center 36 (6~66) winsize 61
715 12:29:49.659922 [CA 3] Center 35 (5~66) winsize 62
716 12:29:49.663678 [CA 4] Center 34 (4~65) winsize 62
717 12:29:49.663778 [CA 5] Center 34 (4~65) winsize 62
718 12:29:49.667410
719 12:29:49.671114 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 12:29:49.671203
721 12:29:49.671294 [CATrainingPosCal] consider 1 rank data
722 12:29:49.674761 u2DelayCellTimex100 = 270/100 ps
723 12:29:49.678521 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 12:29:49.682157 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 12:29:49.685564 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
726 12:29:49.689549 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 12:29:49.693295 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 12:29:49.696788 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 12:29:49.696868
730 12:29:49.700731 CA PerBit enable=1, Macro0, CA PI delay=34
731 12:29:49.700810
732 12:29:49.704428 [CBTSetCACLKResult] CA Dly = 34
733 12:29:49.704514 CS Dly: 5 (0~36)
734 12:29:49.708030 ==
735 12:29:49.708118 Dram Type= 6, Freq= 0, CH_0, rank 1
736 12:29:49.715446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 12:29:49.715578 ==
738 12:29:49.719456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 12:29:49.725730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 12:29:49.734325 [CA 0] Center 38 (7~69) winsize 63
741 12:29:49.737816 [CA 1] Center 38 (7~69) winsize 63
742 12:29:49.742250 [CA 2] Center 35 (5~66) winsize 62
743 12:29:49.745034 [CA 3] Center 35 (5~66) winsize 62
744 12:29:49.748836 [CA 4] Center 34 (4~65) winsize 62
745 12:29:49.752260 [CA 5] Center 34 (3~65) winsize 63
746 12:29:49.752354
747 12:29:49.756103 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 12:29:49.756193
749 12:29:49.759630 [CATrainingPosCal] consider 2 rank data
750 12:29:49.763315 u2DelayCellTimex100 = 270/100 ps
751 12:29:49.766380 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 12:29:49.769503 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 12:29:49.773200 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
754 12:29:49.776334 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 12:29:49.779929 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 12:29:49.783008 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 12:29:49.783097
758 12:29:49.786106 CA PerBit enable=1, Macro0, CA PI delay=34
759 12:29:49.789793
760 12:29:49.789881 [CBTSetCACLKResult] CA Dly = 34
761 12:29:49.792890 CS Dly: 6 (0~38)
762 12:29:49.792979
763 12:29:49.796294 ----->DramcWriteLeveling(PI) begin...
764 12:29:49.796385 ==
765 12:29:49.799802 Dram Type= 6, Freq= 0, CH_0, rank 0
766 12:29:49.802758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 12:29:49.802855 ==
768 12:29:49.806275 Write leveling (Byte 0): 32 => 32
769 12:29:49.809812 Write leveling (Byte 1): 31 => 31
770 12:29:49.812779 DramcWriteLeveling(PI) end<-----
771 12:29:49.812867
772 12:29:49.812957 ==
773 12:29:49.816400 Dram Type= 6, Freq= 0, CH_0, rank 0
774 12:29:49.819344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 12:29:49.822882 ==
776 12:29:49.822969 [Gating] SW mode calibration
777 12:29:49.829459 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 12:29:49.836159 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 12:29:49.839046 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 12:29:49.846033 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 12:29:49.849155 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 12:29:49.852321 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 12:29:49.859174 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 12:29:49.862275 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 12:29:49.865922 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:29:49.872696 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:29:49.876456 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:29:49.880088 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:29:49.883870 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:29:49.887592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:29:49.894349 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:29:49.897343 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:29:49.901021 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:29:49.904590 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:29:49.911647 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:29:49.914724 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:29:49.918187 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 12:29:49.924767 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:29:49.927658 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:29:49.930956 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:29:49.937689 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:29:49.941289 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:29:49.944235 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:29:49.950963 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:29:49.954423 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:29:49.957556 0 9 12 | B1->B0 | 2625 3232 | 1 1 | (0 0) (1 1)
807 12:29:49.964658 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 12:29:49.967465 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 12:29:49.971234 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 12:29:49.977241 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 12:29:49.980916 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:29:49.983991 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
813 12:29:49.990784 0 10 8 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
814 12:29:49.993932 0 10 12 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
815 12:29:49.997130 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:29:50.003839 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:29:50.007376 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:29:50.010860 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:29:50.017324 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:29:50.020743 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:29:50.024168 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
822 12:29:50.030544 0 11 12 | B1->B0 | 3737 3f3f | 0 0 | (0 0) (0 0)
823 12:29:50.033988 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 12:29:50.037522 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 12:29:50.044138 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 12:29:50.047138 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 12:29:50.050573 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:29:50.056887 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:29:50.060467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 12:29:50.063543 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 12:29:50.070381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:29:50.073818 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:29:50.077208 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:29:50.083726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:29:50.087175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:29:50.090155 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:29:50.093920 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:29:50.100518 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:29:50.103396 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:29:50.107163 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:29:50.113339 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:29:50.116834 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:29:50.119799 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:29:50.126432 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:29:50.129891 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 12:29:50.133179 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
847 12:29:50.140145 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:29:50.143052 Total UI for P1: 0, mck2ui 16
849 12:29:50.146402 best dqsien dly found for B0: ( 0, 14, 10)
850 12:29:50.150007 Total UI for P1: 0, mck2ui 16
851 12:29:50.152885 best dqsien dly found for B1: ( 0, 14, 12)
852 12:29:50.156585 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
853 12:29:50.159670 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 12:29:50.159755
855 12:29:50.163025 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 12:29:50.166551 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 12:29:50.169454 [Gating] SW calibration Done
858 12:29:50.169538 ==
859 12:29:50.173264 Dram Type= 6, Freq= 0, CH_0, rank 0
860 12:29:50.176434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 12:29:50.176519 ==
862 12:29:50.179491 RX Vref Scan: 0
863 12:29:50.179576
864 12:29:50.183098 RX Vref 0 -> 0, step: 1
865 12:29:50.183182
866 12:29:50.183250 RX Delay -130 -> 252, step: 16
867 12:29:50.189374 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 12:29:50.193031 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 12:29:50.196218 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 12:29:50.199797 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 12:29:50.202939 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 12:29:50.209758 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 12:29:50.212834 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 12:29:50.215837 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 12:29:50.219526 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 12:29:50.222549 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 12:29:50.229521 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 12:29:50.232560 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 12:29:50.236060 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 12:29:50.239330 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 12:29:50.245722 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 12:29:50.249426 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 12:29:50.249512 ==
884 12:29:50.252903 Dram Type= 6, Freq= 0, CH_0, rank 0
885 12:29:50.255857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 12:29:50.255942 ==
887 12:29:50.256010 DQS Delay:
888 12:29:50.259346 DQS0 = 0, DQS1 = 0
889 12:29:50.259430 DQM Delay:
890 12:29:50.262452 DQM0 = 81, DQM1 = 69
891 12:29:50.262536 DQ Delay:
892 12:29:50.266128 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 12:29:50.269212 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 12:29:50.272415 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 12:29:50.275898 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 12:29:50.275983
897 12:29:50.276050
898 12:29:50.276112 ==
899 12:29:50.279642 Dram Type= 6, Freq= 0, CH_0, rank 0
900 12:29:50.282850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 12:29:50.282951 ==
902 12:29:50.285919
903 12:29:50.286004
904 12:29:50.286071 TX Vref Scan disable
905 12:29:50.289555 == TX Byte 0 ==
906 12:29:50.292702 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 12:29:50.295780 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 12:29:50.299428 == TX Byte 1 ==
909 12:29:50.302485 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 12:29:50.306207 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 12:29:50.306292 ==
912 12:29:50.309247 Dram Type= 6, Freq= 0, CH_0, rank 0
913 12:29:50.316109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 12:29:50.316210 ==
915 12:29:50.327840 TX Vref=22, minBit 11, minWin=26, winSum=434
916 12:29:50.331223 TX Vref=24, minBit 0, minWin=27, winSum=437
917 12:29:50.334357 TX Vref=26, minBit 14, minWin=26, winSum=437
918 12:29:50.337805 TX Vref=28, minBit 9, minWin=27, winSum=441
919 12:29:50.341495 TX Vref=30, minBit 10, minWin=26, winSum=439
920 12:29:50.348173 TX Vref=32, minBit 9, minWin=26, winSum=439
921 12:29:50.351128 [TxChooseVref] Worse bit 9, Min win 27, Win sum 441, Final Vref 28
922 12:29:50.351213
923 12:29:50.354635 Final TX Range 1 Vref 28
924 12:29:50.354719
925 12:29:50.354786 ==
926 12:29:50.358362 Dram Type= 6, Freq= 0, CH_0, rank 0
927 12:29:50.360958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 12:29:50.364437 ==
929 12:29:50.364521
930 12:29:50.364588
931 12:29:50.364648 TX Vref Scan disable
932 12:29:50.368136 == TX Byte 0 ==
933 12:29:50.371294 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
934 12:29:50.377856 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
935 12:29:50.377940 == TX Byte 1 ==
936 12:29:50.381544 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 12:29:50.387901 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 12:29:50.387985
939 12:29:50.388053 [DATLAT]
940 12:29:50.388123 Freq=800, CH0 RK0
941 12:29:50.388184
942 12:29:50.391613 DATLAT Default: 0xa
943 12:29:50.391698 0, 0xFFFF, sum = 0
944 12:29:50.394392 1, 0xFFFF, sum = 0
945 12:29:50.394502 2, 0xFFFF, sum = 0
946 12:29:50.398069 3, 0xFFFF, sum = 0
947 12:29:50.401186 4, 0xFFFF, sum = 0
948 12:29:50.401297 5, 0xFFFF, sum = 0
949 12:29:50.404268 6, 0xFFFF, sum = 0
950 12:29:50.404379 7, 0xFFFF, sum = 0
951 12:29:50.407989 8, 0xFFFF, sum = 0
952 12:29:50.408073 9, 0x0, sum = 1
953 12:29:50.411031 10, 0x0, sum = 2
954 12:29:50.411148 11, 0x0, sum = 3
955 12:29:50.411248 12, 0x0, sum = 4
956 12:29:50.414109 best_step = 10
957 12:29:50.414218
958 12:29:50.414312 ==
959 12:29:50.417696 Dram Type= 6, Freq= 0, CH_0, rank 0
960 12:29:50.420798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 12:29:50.420902 ==
962 12:29:50.424090 RX Vref Scan: 1
963 12:29:50.424186
964 12:29:50.427850 Set Vref Range= 32 -> 127
965 12:29:50.427932
966 12:29:50.427998 RX Vref 32 -> 127, step: 1
967 12:29:50.428059
968 12:29:50.430915 RX Delay -111 -> 252, step: 8
969 12:29:50.430998
970 12:29:50.434443 Set Vref, RX VrefLevel [Byte0]: 32
971 12:29:50.437407 [Byte1]: 32
972 12:29:50.440787
973 12:29:50.440873 Set Vref, RX VrefLevel [Byte0]: 33
974 12:29:50.444358 [Byte1]: 33
975 12:29:50.448290
976 12:29:50.448399 Set Vref, RX VrefLevel [Byte0]: 34
977 12:29:50.451787 [Byte1]: 34
978 12:29:50.456397
979 12:29:50.456491 Set Vref, RX VrefLevel [Byte0]: 35
980 12:29:50.459325 [Byte1]: 35
981 12:29:50.464099
982 12:29:50.464208 Set Vref, RX VrefLevel [Byte0]: 36
983 12:29:50.467043 [Byte1]: 36
984 12:29:50.471632
985 12:29:50.471740 Set Vref, RX VrefLevel [Byte0]: 37
986 12:29:50.474443 [Byte1]: 37
987 12:29:50.479330
988 12:29:50.479413 Set Vref, RX VrefLevel [Byte0]: 38
989 12:29:50.482384 [Byte1]: 38
990 12:29:50.486481
991 12:29:50.486563 Set Vref, RX VrefLevel [Byte0]: 39
992 12:29:50.490154 [Byte1]: 39
993 12:29:50.494527
994 12:29:50.497483 Set Vref, RX VrefLevel [Byte0]: 40
995 12:29:50.497574 [Byte1]: 40
996 12:29:50.501897
997 12:29:50.501980 Set Vref, RX VrefLevel [Byte0]: 41
998 12:29:50.505038 [Byte1]: 41
999 12:29:50.509374
1000 12:29:50.509476 Set Vref, RX VrefLevel [Byte0]: 42
1001 12:29:50.513075 [Byte1]: 42
1002 12:29:50.517372
1003 12:29:50.517457 Set Vref, RX VrefLevel [Byte0]: 43
1004 12:29:50.520523 [Byte1]: 43
1005 12:29:50.524856
1006 12:29:50.524941 Set Vref, RX VrefLevel [Byte0]: 44
1007 12:29:50.528575 [Byte1]: 44
1008 12:29:50.533022
1009 12:29:50.533110 Set Vref, RX VrefLevel [Byte0]: 45
1010 12:29:50.535988 [Byte1]: 45
1011 12:29:50.540278
1012 12:29:50.540363 Set Vref, RX VrefLevel [Byte0]: 46
1013 12:29:50.543705 [Byte1]: 46
1014 12:29:50.548495
1015 12:29:50.548579 Set Vref, RX VrefLevel [Byte0]: 47
1016 12:29:50.551540 [Byte1]: 47
1017 12:29:50.555682
1018 12:29:50.555764 Set Vref, RX VrefLevel [Byte0]: 48
1019 12:29:50.559010 [Byte1]: 48
1020 12:29:50.563049
1021 12:29:50.563131 Set Vref, RX VrefLevel [Byte0]: 49
1022 12:29:50.566516 [Byte1]: 49
1023 12:29:50.570575
1024 12:29:50.570657 Set Vref, RX VrefLevel [Byte0]: 50
1025 12:29:50.574039 [Byte1]: 50
1026 12:29:50.578597
1027 12:29:50.578680 Set Vref, RX VrefLevel [Byte0]: 51
1028 12:29:50.581805 [Byte1]: 51
1029 12:29:50.586231
1030 12:29:50.586313 Set Vref, RX VrefLevel [Byte0]: 52
1031 12:29:50.589158 [Byte1]: 52
1032 12:29:50.593822
1033 12:29:50.593923 Set Vref, RX VrefLevel [Byte0]: 53
1034 12:29:50.596816 [Byte1]: 53
1035 12:29:50.601108
1036 12:29:50.601207 Set Vref, RX VrefLevel [Byte0]: 54
1037 12:29:50.604795 [Byte1]: 54
1038 12:29:50.609185
1039 12:29:50.609286 Set Vref, RX VrefLevel [Byte0]: 55
1040 12:29:50.612161 [Byte1]: 55
1041 12:29:50.616482
1042 12:29:50.616579 Set Vref, RX VrefLevel [Byte0]: 56
1043 12:29:50.620269 [Byte1]: 56
1044 12:29:50.624626
1045 12:29:50.624711 Set Vref, RX VrefLevel [Byte0]: 57
1046 12:29:50.627830 [Byte1]: 57
1047 12:29:50.632090
1048 12:29:50.632172 Set Vref, RX VrefLevel [Byte0]: 58
1049 12:29:50.635068 [Byte1]: 58
1050 12:29:50.639509
1051 12:29:50.639591 Set Vref, RX VrefLevel [Byte0]: 59
1052 12:29:50.643361 [Byte1]: 59
1053 12:29:50.647391
1054 12:29:50.647499 Set Vref, RX VrefLevel [Byte0]: 60
1055 12:29:50.650279 [Byte1]: 60
1056 12:29:50.655035
1057 12:29:50.655117 Set Vref, RX VrefLevel [Byte0]: 61
1058 12:29:50.658027 [Byte1]: 61
1059 12:29:50.662697
1060 12:29:50.662805 Set Vref, RX VrefLevel [Byte0]: 62
1061 12:29:50.665702 [Byte1]: 62
1062 12:29:50.669941
1063 12:29:50.670023 Set Vref, RX VrefLevel [Byte0]: 63
1064 12:29:50.673351 [Byte1]: 63
1065 12:29:50.678275
1066 12:29:50.678366 Set Vref, RX VrefLevel [Byte0]: 64
1067 12:29:50.680878 [Byte1]: 64
1068 12:29:50.685408
1069 12:29:50.685490 Set Vref, RX VrefLevel [Byte0]: 65
1070 12:29:50.688423 [Byte1]: 65
1071 12:29:50.693343
1072 12:29:50.693439 Set Vref, RX VrefLevel [Byte0]: 66
1073 12:29:50.696368 [Byte1]: 66
1074 12:29:50.700575
1075 12:29:50.700656 Set Vref, RX VrefLevel [Byte0]: 67
1076 12:29:50.703773 [Byte1]: 67
1077 12:29:50.708240
1078 12:29:50.708322 Set Vref, RX VrefLevel [Byte0]: 68
1079 12:29:50.712048 [Byte1]: 68
1080 12:29:50.716329
1081 12:29:50.716411 Set Vref, RX VrefLevel [Byte0]: 69
1082 12:29:50.719428 [Byte1]: 69
1083 12:29:50.723780
1084 12:29:50.723862 Set Vref, RX VrefLevel [Byte0]: 70
1085 12:29:50.726818 [Byte1]: 70
1086 12:29:50.731016
1087 12:29:50.731124 Set Vref, RX VrefLevel [Byte0]: 71
1088 12:29:50.734720 [Byte1]: 71
1089 12:29:50.739149
1090 12:29:50.739231 Set Vref, RX VrefLevel [Byte0]: 72
1091 12:29:50.742251 [Byte1]: 72
1092 12:29:50.746696
1093 12:29:50.746779 Set Vref, RX VrefLevel [Byte0]: 73
1094 12:29:50.749851 [Byte1]: 73
1095 12:29:50.754030
1096 12:29:50.754111 Set Vref, RX VrefLevel [Byte0]: 74
1097 12:29:50.757326 [Byte1]: 74
1098 12:29:50.762029
1099 12:29:50.762111 Set Vref, RX VrefLevel [Byte0]: 75
1100 12:29:50.765233 [Byte1]: 75
1101 12:29:50.769275
1102 12:29:50.769357 Set Vref, RX VrefLevel [Byte0]: 76
1103 12:29:50.772505 [Byte1]: 76
1104 12:29:50.777164
1105 12:29:50.777247 Set Vref, RX VrefLevel [Byte0]: 77
1106 12:29:50.780829 [Byte1]: 77
1107 12:29:50.784765
1108 12:29:50.784848 Set Vref, RX VrefLevel [Byte0]: 78
1109 12:29:50.788113 [Byte1]: 78
1110 12:29:50.792200
1111 12:29:50.792314 Set Vref, RX VrefLevel [Byte0]: 79
1112 12:29:50.795698 [Byte1]: 79
1113 12:29:50.799971
1114 12:29:50.800053 Set Vref, RX VrefLevel [Byte0]: 80
1115 12:29:50.803505 [Byte1]: 80
1116 12:29:50.807880
1117 12:29:50.807962 Final RX Vref Byte 0 = 58 to rank0
1118 12:29:50.811215 Final RX Vref Byte 1 = 62 to rank0
1119 12:29:50.814207 Final RX Vref Byte 0 = 58 to rank1
1120 12:29:50.817940 Final RX Vref Byte 1 = 62 to rank1==
1121 12:29:50.820996 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 12:29:50.827841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 12:29:50.827921 ==
1124 12:29:50.827986 DQS Delay:
1125 12:29:50.828044 DQS0 = 0, DQS1 = 0
1126 12:29:50.830863 DQM Delay:
1127 12:29:50.830949 DQM0 = 82, DQM1 = 68
1128 12:29:50.834498 DQ Delay:
1129 12:29:50.837740 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1130 12:29:50.840937 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1131 12:29:50.844071 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1132 12:29:50.847862 DQ12 =76, DQ13 =68, DQ14 =80, DQ15 =76
1133 12:29:50.847950
1134 12:29:50.848016
1135 12:29:50.854106 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1136 12:29:50.857238 CH0 RK0: MR19=606, MR18=2121
1137 12:29:50.864461 CH0_RK0: MR19=0x606, MR18=0x2121, DQSOSC=401, MR23=63, INC=91, DEC=61
1138 12:29:50.864583
1139 12:29:50.867472 ----->DramcWriteLeveling(PI) begin...
1140 12:29:50.867557 ==
1141 12:29:50.871133 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 12:29:50.873992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 12:29:50.874076 ==
1144 12:29:50.877628 Write leveling (Byte 0): 32 => 32
1145 12:29:50.880832 Write leveling (Byte 1): 28 => 28
1146 12:29:50.883738 DramcWriteLeveling(PI) end<-----
1147 12:29:50.883827
1148 12:29:50.883895 ==
1149 12:29:50.887492 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 12:29:50.890443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 12:29:50.890525 ==
1152 12:29:50.893996 [Gating] SW mode calibration
1153 12:29:50.900507 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 12:29:50.907150 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 12:29:50.910154 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 12:29:50.917097 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 12:29:50.920436 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 12:29:50.923319 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:29:50.930259 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:29:50.933294 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:29:50.936971 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:29:50.943202 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:29:50.947114 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:29:50.949979 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:29:50.956813 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:29:51.000769 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:29:51.000955 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:29:51.001055 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:29:51.001328 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:29:51.001401 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:29:51.002032 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:29:51.002301 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 12:29:51.002380 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1174 12:29:51.002464 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 12:29:51.002637 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:29:51.044989 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:29:51.045150 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:29:51.045221 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:29:51.045471 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:29:51.045537 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1181 12:29:51.045597 0 9 8 | B1->B0 | 2322 2c2c | 1 1 | (0 0) (1 1)
1182 12:29:51.045656 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1183 12:29:51.046224 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:29:51.046485 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:29:51.046566 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:29:51.078810 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:29:51.079008 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:29:51.079078 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
1189 12:29:51.079348 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
1190 12:29:51.079442 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1191 12:29:51.079517 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:29:51.079580 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:29:51.079895 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:29:51.083092 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:29:51.086169 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:29:51.092847 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1197 12:29:51.096391 0 11 8 | B1->B0 | 2d2d 3a3a | 1 0 | (0 0) (0 0)
1198 12:29:51.099442 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1199 12:29:51.105853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:29:51.109375 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:29:51.112871 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:29:51.116299 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:29:51.120261 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:29:51.127540 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 12:29:51.131403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 12:29:51.134308 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:29:51.141031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:29:51.144748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:29:51.148487 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:29:51.151735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:29:51.157854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:29:51.161577 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:29:51.164892 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:29:51.171150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:29:51.174823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:29:51.177800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:29:51.184525 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:29:51.188148 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:29:51.191283 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:29:51.197821 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 12:29:51.201366 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 12:29:51.204631 Total UI for P1: 0, mck2ui 16
1223 12:29:51.208155 best dqsien dly found for B0: ( 0, 14, 4)
1224 12:29:51.211228 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1225 12:29:51.217623 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 12:29:51.217781 Total UI for P1: 0, mck2ui 16
1227 12:29:51.224291 best dqsien dly found for B1: ( 0, 14, 10)
1228 12:29:51.227314 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1229 12:29:51.230949 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1230 12:29:51.231042
1231 12:29:51.233964 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1232 12:29:51.237543 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1233 12:29:51.240738 [Gating] SW calibration Done
1234 12:29:51.240831 ==
1235 12:29:51.243865 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 12:29:51.247690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 12:29:51.247780 ==
1238 12:29:51.250608 RX Vref Scan: 0
1239 12:29:51.250706
1240 12:29:51.250810 RX Vref 0 -> 0, step: 1
1241 12:29:51.250932
1242 12:29:51.254313 RX Delay -130 -> 252, step: 16
1243 12:29:51.260516 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1244 12:29:51.264076 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1245 12:29:51.267271 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1246 12:29:51.270853 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1247 12:29:51.273913 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1248 12:29:51.280826 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1249 12:29:51.283575 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1250 12:29:51.287318 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1251 12:29:51.290318 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1252 12:29:51.293942 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1253 12:29:51.300288 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1254 12:29:51.304010 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1255 12:29:51.306840 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1256 12:29:51.310060 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1257 12:29:51.313724 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1258 12:29:51.320270 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1259 12:29:51.320383 ==
1260 12:29:51.323759 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 12:29:51.326651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 12:29:51.326780 ==
1263 12:29:51.326904 DQS Delay:
1264 12:29:51.330394 DQS0 = 0, DQS1 = 0
1265 12:29:51.330480 DQM Delay:
1266 12:29:51.333606 DQM0 = 76, DQM1 = 69
1267 12:29:51.333691 DQ Delay:
1268 12:29:51.336801 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1269 12:29:51.340520 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1270 12:29:51.343774 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1271 12:29:51.346865 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1272 12:29:51.346964
1273 12:29:51.347029
1274 12:29:51.347088 ==
1275 12:29:51.350026 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 12:29:51.353588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 12:29:51.356599 ==
1278 12:29:51.356685
1279 12:29:51.356750
1280 12:29:51.356811 TX Vref Scan disable
1281 12:29:51.359729 == TX Byte 0 ==
1282 12:29:51.363338 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1283 12:29:51.366430 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1284 12:29:51.369623 == TX Byte 1 ==
1285 12:29:51.372736 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1286 12:29:51.376339 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1287 12:29:51.379443 ==
1288 12:29:51.383158 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 12:29:51.386162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 12:29:51.386250 ==
1291 12:29:51.399176 TX Vref=22, minBit 0, minWin=27, winSum=437
1292 12:29:51.402183 TX Vref=24, minBit 0, minWin=27, winSum=441
1293 12:29:51.405638 TX Vref=26, minBit 1, minWin=27, winSum=441
1294 12:29:51.409078 TX Vref=28, minBit 1, minWin=27, winSum=447
1295 12:29:51.411987 TX Vref=30, minBit 1, minWin=27, winSum=446
1296 12:29:51.418749 TX Vref=32, minBit 1, minWin=27, winSum=445
1297 12:29:51.422306 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1298 12:29:51.422408
1299 12:29:51.425290 Final TX Range 1 Vref 28
1300 12:29:51.425374
1301 12:29:51.425437 ==
1302 12:29:51.428710 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 12:29:51.432264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 12:29:51.435173 ==
1305 12:29:51.435258
1306 12:29:51.435321
1307 12:29:51.435380 TX Vref Scan disable
1308 12:29:51.438986 == TX Byte 0 ==
1309 12:29:51.442039 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1310 12:29:51.448616 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1311 12:29:51.448712 == TX Byte 1 ==
1312 12:29:51.452298 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1313 12:29:51.459024 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1314 12:29:51.459128
1315 12:29:51.459195 [DATLAT]
1316 12:29:51.459256 Freq=800, CH0 RK1
1317 12:29:51.459314
1318 12:29:51.462108 DATLAT Default: 0xa
1319 12:29:51.462192 0, 0xFFFF, sum = 0
1320 12:29:51.465276 1, 0xFFFF, sum = 0
1321 12:29:51.469003 2, 0xFFFF, sum = 0
1322 12:29:51.469090 3, 0xFFFF, sum = 0
1323 12:29:51.472027 4, 0xFFFF, sum = 0
1324 12:29:51.472111 5, 0xFFFF, sum = 0
1325 12:29:51.475348 6, 0xFFFF, sum = 0
1326 12:29:51.475433 7, 0xFFFF, sum = 0
1327 12:29:51.478799 8, 0xFFFF, sum = 0
1328 12:29:51.478908 9, 0x0, sum = 1
1329 12:29:51.482028 10, 0x0, sum = 2
1330 12:29:51.482110 11, 0x0, sum = 3
1331 12:29:51.482175 12, 0x0, sum = 4
1332 12:29:51.485393 best_step = 10
1333 12:29:51.485475
1334 12:29:51.485538 ==
1335 12:29:51.488591 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 12:29:51.492112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 12:29:51.492195 ==
1338 12:29:51.495445 RX Vref Scan: 0
1339 12:29:51.495526
1340 12:29:51.498277 RX Vref 0 -> 0, step: 1
1341 12:29:51.498360
1342 12:29:51.498424 RX Delay -111 -> 252, step: 8
1343 12:29:51.505599 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1344 12:29:51.508808 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1345 12:29:51.512310 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1346 12:29:51.515815 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1347 12:29:51.522019 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1348 12:29:51.525119 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1349 12:29:51.528516 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1350 12:29:51.531949 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1351 12:29:51.535333 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1352 12:29:51.541644 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1353 12:29:51.545336 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1354 12:29:51.548449 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1355 12:29:51.551565 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1356 12:29:51.554798 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1357 12:29:51.561564 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1358 12:29:51.565086 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1359 12:29:51.565183 ==
1360 12:29:51.568249 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 12:29:51.571337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 12:29:51.571423 ==
1363 12:29:51.575021 DQS Delay:
1364 12:29:51.575120 DQS0 = 0, DQS1 = 0
1365 12:29:51.575187 DQM Delay:
1366 12:29:51.578322 DQM0 = 79, DQM1 = 71
1367 12:29:51.578410 DQ Delay:
1368 12:29:51.581307 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1369 12:29:51.584483 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1370 12:29:51.588116 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1371 12:29:51.591344 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1372 12:29:51.591429
1373 12:29:51.591493
1374 12:29:51.601563 [DQSOSCAuto] RK1, (LSB)MR18= 0x4621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1375 12:29:51.604604 CH0 RK1: MR19=606, MR18=4621
1376 12:29:51.607844 CH0_RK1: MR19=0x606, MR18=0x4621, DQSOSC=392, MR23=63, INC=96, DEC=64
1377 12:29:51.611544 [RxdqsGatingPostProcess] freq 800
1378 12:29:51.617925 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 12:29:51.621241 Pre-setting of DQS Precalculation
1380 12:29:51.624428 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 12:29:51.627793 ==
1382 12:29:51.627884 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 12:29:51.634110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 12:29:51.634206 ==
1385 12:29:51.637485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 12:29:51.644318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 12:29:51.654060 [CA 0] Center 36 (6~66) winsize 61
1388 12:29:51.657232 [CA 1] Center 36 (6~67) winsize 62
1389 12:29:51.660897 [CA 2] Center 34 (5~64) winsize 60
1390 12:29:51.663906 [CA 3] Center 34 (4~64) winsize 61
1391 12:29:51.667428 [CA 4] Center 35 (5~65) winsize 61
1392 12:29:51.670505 [CA 5] Center 34 (4~64) winsize 61
1393 12:29:51.670593
1394 12:29:51.673984 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1395 12:29:51.674070
1396 12:29:51.677110 [CATrainingPosCal] consider 1 rank data
1397 12:29:51.680892 u2DelayCellTimex100 = 270/100 ps
1398 12:29:51.684032 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1399 12:29:51.690235 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1400 12:29:51.694057 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1401 12:29:51.697135 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 12:29:51.700593 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1403 12:29:51.703666 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1404 12:29:51.703757
1405 12:29:51.707388 CA PerBit enable=1, Macro0, CA PI delay=34
1406 12:29:51.707463
1407 12:29:51.710469 [CBTSetCACLKResult] CA Dly = 34
1408 12:29:51.710556 CS Dly: 5 (0~36)
1409 12:29:51.713643 ==
1410 12:29:51.713717 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 12:29:51.720448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 12:29:51.720553 ==
1413 12:29:51.723656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 12:29:51.730426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 12:29:51.740197 [CA 0] Center 36 (6~67) winsize 62
1416 12:29:51.743658 [CA 1] Center 37 (7~67) winsize 61
1417 12:29:51.746782 [CA 2] Center 35 (5~65) winsize 61
1418 12:29:51.750310 [CA 3] Center 33 (3~64) winsize 62
1419 12:29:51.753242 [CA 4] Center 34 (4~65) winsize 62
1420 12:29:51.756593 [CA 5] Center 33 (3~64) winsize 62
1421 12:29:51.756681
1422 12:29:51.760246 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1423 12:29:51.760331
1424 12:29:51.763461 [CATrainingPosCal] consider 2 rank data
1425 12:29:51.766550 u2DelayCellTimex100 = 270/100 ps
1426 12:29:51.770029 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1427 12:29:51.773412 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1428 12:29:51.777946 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1429 12:29:51.781125 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 12:29:51.784652 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 12:29:51.787807 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 12:29:51.787898
1433 12:29:51.794448 CA PerBit enable=1, Macro0, CA PI delay=34
1434 12:29:51.794567
1435 12:29:51.798062 [CBTSetCACLKResult] CA Dly = 34
1436 12:29:51.798155 CS Dly: 6 (0~38)
1437 12:29:51.798224
1438 12:29:51.801840 ----->DramcWriteLeveling(PI) begin...
1439 12:29:51.801949 ==
1440 12:29:51.805486 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 12:29:51.809212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 12:29:51.809315 ==
1443 12:29:51.812258 Write leveling (Byte 0): 28 => 28
1444 12:29:51.815539 Write leveling (Byte 1): 28 => 28
1445 12:29:51.818632 DramcWriteLeveling(PI) end<-----
1446 12:29:51.818739
1447 12:29:51.818845 ==
1448 12:29:51.822366 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:29:51.825450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 12:29:51.825547 ==
1451 12:29:51.829099 [Gating] SW mode calibration
1452 12:29:51.835306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 12:29:51.841786 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 12:29:51.845380 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 12:29:51.851815 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1456 12:29:51.855107 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:29:51.858617 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:29:51.864872 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:29:51.868428 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:29:51.871505 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:29:51.878468 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:29:51.881618 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:29:51.884584 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:29:51.888160 0 7 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1465 12:29:51.894823 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:29:51.897998 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:29:51.901718 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:29:51.907913 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:29:51.911441 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:29:51.914553 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1471 12:29:51.921305 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1472 12:29:51.924513 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1473 12:29:51.927505 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:29:51.934371 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:29:51.937961 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:29:51.941179 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:29:51.947791 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:29:51.951212 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:29:51.955085 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:29:51.961112 0 9 8 | B1->B0 | 2727 2424 | 0 1 | (0 0) (1 1)
1481 12:29:51.964651 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:29:51.967624 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:29:51.974351 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:29:51.978288 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:29:51.981150 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:29:51.987342 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 12:29:51.991032 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (0 0)
1488 12:29:51.994056 0 10 8 | B1->B0 | 2e2e 2c2c | 1 1 | (1 0) (1 0)
1489 12:29:52.000622 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:29:52.004340 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:29:52.007644 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:29:52.014188 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:29:52.017690 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:29:52.020817 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:29:52.027509 0 11 4 | B1->B0 | 2323 2424 | 1 0 | (0 0) (0 0)
1496 12:29:52.030693 0 11 8 | B1->B0 | 3838 3535 | 0 0 | (0 0) (1 1)
1497 12:29:52.034445 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:29:52.040590 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:29:52.044305 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:29:52.047226 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:29:52.054034 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:29:52.057438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 12:29:52.060484 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 12:29:52.067476 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1505 12:29:52.070470 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:29:52.073980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:29:52.077341 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:29:52.084182 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:29:52.086845 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:29:52.090661 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:29:52.096809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:29:52.100750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:29:52.103459 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:29:52.110210 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:29:52.113297 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:29:52.116932 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:29:52.123414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:29:52.126586 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:29:52.130262 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:29:52.136525 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1521 12:29:52.140236 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 12:29:52.143291 Total UI for P1: 0, mck2ui 16
1523 12:29:52.146407 best dqsien dly found for B0: ( 0, 14, 8)
1524 12:29:52.150136 Total UI for P1: 0, mck2ui 16
1525 12:29:52.152892 best dqsien dly found for B1: ( 0, 14, 8)
1526 12:29:52.157062 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1527 12:29:52.159770 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1528 12:29:52.159858
1529 12:29:52.162765 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 12:29:52.166248 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1531 12:29:52.169744 [Gating] SW calibration Done
1532 12:29:52.169832 ==
1533 12:29:52.173230 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 12:29:52.179534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 12:29:52.179637 ==
1536 12:29:52.179706 RX Vref Scan: 0
1537 12:29:52.179766
1538 12:29:52.182941 RX Vref 0 -> 0, step: 1
1539 12:29:52.183035
1540 12:29:52.186296 RX Delay -130 -> 252, step: 16
1541 12:29:52.189704 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1542 12:29:52.193170 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1543 12:29:52.195920 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1544 12:29:52.202503 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1545 12:29:52.206313 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1546 12:29:52.209180 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1547 12:29:52.212296 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1548 12:29:52.216080 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1549 12:29:52.222224 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1550 12:29:52.225758 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1551 12:29:52.229362 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1552 12:29:52.232516 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1553 12:29:52.235630 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1554 12:29:52.242485 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1555 12:29:52.245585 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1556 12:29:52.248738 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1557 12:29:52.248827 ==
1558 12:29:52.252504 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 12:29:52.255621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 12:29:52.255711 ==
1561 12:29:52.259303 DQS Delay:
1562 12:29:52.259393 DQS0 = 0, DQS1 = 0
1563 12:29:52.262400 DQM Delay:
1564 12:29:52.262487 DQM0 = 81, DQM1 = 71
1565 12:29:52.262573 DQ Delay:
1566 12:29:52.265447 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1567 12:29:52.268942 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1568 12:29:52.272403 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1569 12:29:52.275278 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1570 12:29:52.275367
1571 12:29:52.278772
1572 12:29:52.278878 ==
1573 12:29:52.282245 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 12:29:52.285230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 12:29:52.285318 ==
1576 12:29:52.285385
1577 12:29:52.285445
1578 12:29:52.288855 TX Vref Scan disable
1579 12:29:52.288941 == TX Byte 0 ==
1580 12:29:52.295240 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1581 12:29:52.298862 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1582 12:29:52.298959 == TX Byte 1 ==
1583 12:29:52.305623 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1584 12:29:52.308893 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1585 12:29:52.308994 ==
1586 12:29:52.311889 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 12:29:52.314964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 12:29:52.315052 ==
1589 12:29:52.328854 TX Vref=22, minBit 1, minWin=27, winSum=439
1590 12:29:52.331773 TX Vref=24, minBit 1, minWin=27, winSum=440
1591 12:29:52.335394 TX Vref=26, minBit 0, minWin=27, winSum=442
1592 12:29:52.338410 TX Vref=28, minBit 1, minWin=27, winSum=447
1593 12:29:52.341534 TX Vref=30, minBit 5, minWin=27, winSum=446
1594 12:29:52.348445 TX Vref=32, minBit 0, minWin=27, winSum=448
1595 12:29:52.352102 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 32
1596 12:29:52.352203
1597 12:29:52.355310 Final TX Range 1 Vref 32
1598 12:29:52.355423
1599 12:29:52.355517 ==
1600 12:29:52.358989 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 12:29:52.362045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 12:29:52.362137 ==
1603 12:29:52.362203
1604 12:29:52.365135
1605 12:29:52.365219 TX Vref Scan disable
1606 12:29:52.368318 == TX Byte 0 ==
1607 12:29:52.372297 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 12:29:52.374974 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 12:29:52.378470 == TX Byte 1 ==
1610 12:29:52.381802 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1611 12:29:52.388472 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1612 12:29:52.388590
1613 12:29:52.388685 [DATLAT]
1614 12:29:52.388782 Freq=800, CH1 RK0
1615 12:29:52.388882
1616 12:29:52.392034 DATLAT Default: 0xa
1617 12:29:52.392125 0, 0xFFFF, sum = 0
1618 12:29:52.395291 1, 0xFFFF, sum = 0
1619 12:29:52.395380 2, 0xFFFF, sum = 0
1620 12:29:52.398573 3, 0xFFFF, sum = 0
1621 12:29:52.401436 4, 0xFFFF, sum = 0
1622 12:29:52.401520 5, 0xFFFF, sum = 0
1623 12:29:52.404983 6, 0xFFFF, sum = 0
1624 12:29:52.405063 7, 0xFFFF, sum = 0
1625 12:29:52.408535 8, 0xFFFF, sum = 0
1626 12:29:52.408625 9, 0x0, sum = 1
1627 12:29:52.411532 10, 0x0, sum = 2
1628 12:29:52.411618 11, 0x0, sum = 3
1629 12:29:52.411686 12, 0x0, sum = 4
1630 12:29:52.414757 best_step = 10
1631 12:29:52.414897
1632 12:29:52.414964 ==
1633 12:29:52.418664 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 12:29:52.421477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 12:29:52.421571 ==
1636 12:29:52.424926 RX Vref Scan: 1
1637 12:29:52.425042
1638 12:29:52.425111 Set Vref Range= 32 -> 127
1639 12:29:52.428147
1640 12:29:52.428236 RX Vref 32 -> 127, step: 1
1641 12:29:52.428303
1642 12:29:52.431436 RX Delay -111 -> 252, step: 8
1643 12:29:52.431551
1644 12:29:52.435138 Set Vref, RX VrefLevel [Byte0]: 32
1645 12:29:52.438091 [Byte1]: 32
1646 12:29:52.438181
1647 12:29:52.441854 Set Vref, RX VrefLevel [Byte0]: 33
1648 12:29:52.444916 [Byte1]: 33
1649 12:29:52.448791
1650 12:29:52.448890 Set Vref, RX VrefLevel [Byte0]: 34
1651 12:29:52.452383 [Byte1]: 34
1652 12:29:52.456785
1653 12:29:52.456876 Set Vref, RX VrefLevel [Byte0]: 35
1654 12:29:52.459757 [Byte1]: 35
1655 12:29:52.464555
1656 12:29:52.464647 Set Vref, RX VrefLevel [Byte0]: 36
1657 12:29:52.467679 [Byte1]: 36
1658 12:29:52.472038
1659 12:29:52.472134 Set Vref, RX VrefLevel [Byte0]: 37
1660 12:29:52.475111 [Byte1]: 37
1661 12:29:52.479619
1662 12:29:52.479710 Set Vref, RX VrefLevel [Byte0]: 38
1663 12:29:52.482637 [Byte1]: 38
1664 12:29:52.487388
1665 12:29:52.487480 Set Vref, RX VrefLevel [Byte0]: 39
1666 12:29:52.490255 [Byte1]: 39
1667 12:29:52.495072
1668 12:29:52.495164 Set Vref, RX VrefLevel [Byte0]: 40
1669 12:29:52.498045 [Byte1]: 40
1670 12:29:52.502503
1671 12:29:52.502610 Set Vref, RX VrefLevel [Byte0]: 41
1672 12:29:52.506031 [Byte1]: 41
1673 12:29:52.509865
1674 12:29:52.509959 Set Vref, RX VrefLevel [Byte0]: 42
1675 12:29:52.513433 [Byte1]: 42
1676 12:29:52.518055
1677 12:29:52.518153 Set Vref, RX VrefLevel [Byte0]: 43
1678 12:29:52.521288 [Byte1]: 43
1679 12:29:52.525545
1680 12:29:52.525648 Set Vref, RX VrefLevel [Byte0]: 44
1681 12:29:52.529062 [Byte1]: 44
1682 12:29:52.533360
1683 12:29:52.533455 Set Vref, RX VrefLevel [Byte0]: 45
1684 12:29:52.536296 [Byte1]: 45
1685 12:29:52.540590
1686 12:29:52.540684 Set Vref, RX VrefLevel [Byte0]: 46
1687 12:29:52.544330 [Byte1]: 46
1688 12:29:52.548667
1689 12:29:52.548761 Set Vref, RX VrefLevel [Byte0]: 47
1690 12:29:52.551865 [Byte1]: 47
1691 12:29:52.556106
1692 12:29:52.556199 Set Vref, RX VrefLevel [Byte0]: 48
1693 12:29:52.559136 [Byte1]: 48
1694 12:29:52.563427
1695 12:29:52.563521 Set Vref, RX VrefLevel [Byte0]: 49
1696 12:29:52.567123 [Byte1]: 49
1697 12:29:52.571252
1698 12:29:52.571346 Set Vref, RX VrefLevel [Byte0]: 50
1699 12:29:52.574400 [Byte1]: 50
1700 12:29:52.579362
1701 12:29:52.579452 Set Vref, RX VrefLevel [Byte0]: 51
1702 12:29:52.582448 [Byte1]: 51
1703 12:29:52.587010
1704 12:29:52.587098 Set Vref, RX VrefLevel [Byte0]: 52
1705 12:29:52.589750 [Byte1]: 52
1706 12:29:52.594496
1707 12:29:52.594584 Set Vref, RX VrefLevel [Byte0]: 53
1708 12:29:52.597295 [Byte1]: 53
1709 12:29:52.602128
1710 12:29:52.604986 Set Vref, RX VrefLevel [Byte0]: 54
1711 12:29:52.605081 [Byte1]: 54
1712 12:29:52.609581
1713 12:29:52.609672 Set Vref, RX VrefLevel [Byte0]: 55
1714 12:29:52.612688 [Byte1]: 55
1715 12:29:52.617400
1716 12:29:52.617493 Set Vref, RX VrefLevel [Byte0]: 56
1717 12:29:52.620627 [Byte1]: 56
1718 12:29:52.624879
1719 12:29:52.624972 Set Vref, RX VrefLevel [Byte0]: 57
1720 12:29:52.627942 [Byte1]: 57
1721 12:29:52.632448
1722 12:29:52.632545 Set Vref, RX VrefLevel [Byte0]: 58
1723 12:29:52.635879 [Byte1]: 58
1724 12:29:52.640124
1725 12:29:52.640215 Set Vref, RX VrefLevel [Byte0]: 59
1726 12:29:52.643205 [Byte1]: 59
1727 12:29:52.647930
1728 12:29:52.648026 Set Vref, RX VrefLevel [Byte0]: 60
1729 12:29:52.651106 [Byte1]: 60
1730 12:29:52.655388
1731 12:29:52.655477 Set Vref, RX VrefLevel [Byte0]: 61
1732 12:29:52.658500 [Byte1]: 61
1733 12:29:52.662967
1734 12:29:52.663054 Set Vref, RX VrefLevel [Byte0]: 62
1735 12:29:52.666598 [Byte1]: 62
1736 12:29:52.670805
1737 12:29:52.670954 Set Vref, RX VrefLevel [Byte0]: 63
1738 12:29:52.673828 [Byte1]: 63
1739 12:29:52.678136
1740 12:29:52.678224 Set Vref, RX VrefLevel [Byte0]: 64
1741 12:29:52.681911 [Byte1]: 64
1742 12:29:52.686301
1743 12:29:52.686388 Set Vref, RX VrefLevel [Byte0]: 65
1744 12:29:52.689538 [Byte1]: 65
1745 12:29:52.693636
1746 12:29:52.693725 Set Vref, RX VrefLevel [Byte0]: 66
1747 12:29:52.696751 [Byte1]: 66
1748 12:29:52.701697
1749 12:29:52.701796 Set Vref, RX VrefLevel [Byte0]: 67
1750 12:29:52.704530 [Byte1]: 67
1751 12:29:52.708559
1752 12:29:52.708659 Set Vref, RX VrefLevel [Byte0]: 68
1753 12:29:52.712056 [Byte1]: 68
1754 12:29:52.716913
1755 12:29:52.717008 Set Vref, RX VrefLevel [Byte0]: 69
1756 12:29:52.719833 [Byte1]: 69
1757 12:29:52.723977
1758 12:29:52.724079 Set Vref, RX VrefLevel [Byte0]: 70
1759 12:29:52.727695 [Byte1]: 70
1760 12:29:52.731887
1761 12:29:52.731981 Set Vref, RX VrefLevel [Byte0]: 71
1762 12:29:52.735025 [Byte1]: 71
1763 12:29:52.739450
1764 12:29:52.739535 Set Vref, RX VrefLevel [Byte0]: 72
1765 12:29:52.742705 [Byte1]: 72
1766 12:29:52.746910
1767 12:29:52.746997 Set Vref, RX VrefLevel [Byte0]: 73
1768 12:29:52.750483 [Byte1]: 73
1769 12:29:52.754943
1770 12:29:52.755026 Set Vref, RX VrefLevel [Byte0]: 74
1771 12:29:52.758015 [Byte1]: 74
1772 12:29:52.762339
1773 12:29:52.762431 Final RX Vref Byte 0 = 63 to rank0
1774 12:29:52.766043 Final RX Vref Byte 1 = 53 to rank0
1775 12:29:52.768981 Final RX Vref Byte 0 = 63 to rank1
1776 12:29:52.772598 Final RX Vref Byte 1 = 53 to rank1==
1777 12:29:52.775725 Dram Type= 6, Freq= 0, CH_1, rank 0
1778 12:29:52.782429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 12:29:52.782537 ==
1780 12:29:52.782644 DQS Delay:
1781 12:29:52.782735 DQS0 = 0, DQS1 = 0
1782 12:29:52.785575 DQM Delay:
1783 12:29:52.785686 DQM0 = 79, DQM1 = 72
1784 12:29:52.789335 DQ Delay:
1785 12:29:52.792500 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1786 12:29:52.795420 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1787 12:29:52.795508 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1788 12:29:52.802212 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
1789 12:29:52.802315
1790 12:29:52.802401
1791 12:29:52.808783 [DQSOSCAuto] RK0, (LSB)MR18= 0x111c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1792 12:29:52.812344 CH1 RK0: MR19=606, MR18=111C
1793 12:29:52.819087 CH1_RK0: MR19=0x606, MR18=0x111C, DQSOSC=402, MR23=63, INC=91, DEC=60
1794 12:29:52.819204
1795 12:29:52.821876 ----->DramcWriteLeveling(PI) begin...
1796 12:29:52.821972 ==
1797 12:29:52.825351 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 12:29:52.828761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 12:29:52.828855 ==
1800 12:29:52.832379 Write leveling (Byte 0): 27 => 27
1801 12:29:52.835564 Write leveling (Byte 1): 27 => 27
1802 12:29:52.838539 DramcWriteLeveling(PI) end<-----
1803 12:29:52.838630
1804 12:29:52.838697 ==
1805 12:29:52.841686 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 12:29:52.845411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 12:29:52.845501 ==
1808 12:29:52.848984 [Gating] SW mode calibration
1809 12:29:52.855020 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1810 12:29:52.861900 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1811 12:29:52.865382 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1812 12:29:52.871908 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1813 12:29:52.874878 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:29:52.878720 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:29:52.881596 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:29:52.888427 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:29:52.891622 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:29:52.898332 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:29:52.901320 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:29:52.904987 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:29:52.911119 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:29:52.914745 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:29:52.917849 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:29:52.924447 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:29:52.928036 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:29:52.931315 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:29:52.934503 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:29:52.940980 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1829 12:29:52.944699 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:29:52.947890 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:29:52.954187 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:29:52.958186 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:29:52.961220 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:29:52.967847 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:29:52.971268 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:29:52.974315 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1837 12:29:52.981094 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1838 12:29:52.984222 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 12:29:52.987144 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 12:29:52.994082 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:29:52.997269 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:29:53.000347 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 12:29:53.007597 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 12:29:53.010720 0 10 4 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 0)
1845 12:29:53.013961 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1846 12:29:53.020432 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:29:53.023911 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:29:53.027478 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:29:53.033723 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:29:53.037248 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:29:53.040024 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:29:53.046958 0 11 4 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (1 1)
1853 12:29:53.049996 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1854 12:29:53.053844 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:29:53.060480 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 12:29:53.063463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 12:29:53.067142 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:29:53.073737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 12:29:53.076836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 12:29:53.079951 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1861 12:29:53.086763 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1862 12:29:53.089917 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:29:53.093497 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:29:53.099826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:29:53.103544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:29:53.106611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:29:53.113396 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:29:53.116551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:29:53.120306 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:29:53.126532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:29:53.130036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:29:53.132944 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:29:53.139977 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:29:53.143090 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:29:53.146621 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:29:53.152911 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1877 12:29:53.156300 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1878 12:29:53.160020 Total UI for P1: 0, mck2ui 16
1879 12:29:53.163068 best dqsien dly found for B0: ( 0, 14, 4)
1880 12:29:53.166069 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 12:29:53.169744 Total UI for P1: 0, mck2ui 16
1882 12:29:53.172801 best dqsien dly found for B1: ( 0, 14, 8)
1883 12:29:53.176018 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1884 12:29:53.179295 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1885 12:29:53.179410
1886 12:29:53.182472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1887 12:29:53.189178 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1888 12:29:53.189307 [Gating] SW calibration Done
1889 12:29:53.189404 ==
1890 12:29:53.192432 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 12:29:53.199606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 12:29:53.199714 ==
1893 12:29:53.199781 RX Vref Scan: 0
1894 12:29:53.199844
1895 12:29:53.202773 RX Vref 0 -> 0, step: 1
1896 12:29:53.202911
1897 12:29:53.206003 RX Delay -130 -> 252, step: 16
1898 12:29:53.209178 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1899 12:29:53.212809 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1900 12:29:53.215778 iDelay=206, Bit 2, Center 61 (-66 ~ 189) 256
1901 12:29:53.222711 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1902 12:29:53.225929 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1903 12:29:53.229042 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1904 12:29:53.232752 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1905 12:29:53.235829 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1906 12:29:53.242224 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1907 12:29:53.245729 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1908 12:29:53.249242 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1909 12:29:53.252617 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1910 12:29:53.256044 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1911 12:29:53.262115 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1912 12:29:53.265511 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1913 12:29:53.269040 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1914 12:29:53.269163 ==
1915 12:29:53.272582 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 12:29:53.275786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 12:29:53.275870 ==
1918 12:29:53.278947 DQS Delay:
1919 12:29:53.279034 DQS0 = 0, DQS1 = 0
1920 12:29:53.281924 DQM Delay:
1921 12:29:53.282032 DQM0 = 76, DQM1 = 71
1922 12:29:53.282127 DQ Delay:
1923 12:29:53.285529 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1924 12:29:53.288434 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1925 12:29:53.292327 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1926 12:29:53.295423 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1927 12:29:53.295517
1928 12:29:53.295583
1929 12:29:53.298960 ==
1930 12:29:53.302040 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 12:29:53.305232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 12:29:53.305325 ==
1933 12:29:53.305392
1934 12:29:53.305454
1935 12:29:53.309038 TX Vref Scan disable
1936 12:29:53.309126 == TX Byte 0 ==
1937 12:29:53.312044 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1938 12:29:53.318570 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1939 12:29:53.318705 == TX Byte 1 ==
1940 12:29:53.325432 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1941 12:29:53.328736 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1942 12:29:53.328836 ==
1943 12:29:53.331883 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 12:29:53.334849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 12:29:53.334976 ==
1946 12:29:53.348577 TX Vref=22, minBit 1, minWin=27, winSum=449
1947 12:29:53.352149 TX Vref=24, minBit 9, minWin=27, winSum=453
1948 12:29:53.355166 TX Vref=26, minBit 1, minWin=28, winSum=456
1949 12:29:53.358665 TX Vref=28, minBit 1, minWin=28, winSum=459
1950 12:29:53.361544 TX Vref=30, minBit 1, minWin=28, winSum=462
1951 12:29:53.368652 TX Vref=32, minBit 1, minWin=27, winSum=457
1952 12:29:53.371535 [TxChooseVref] Worse bit 1, Min win 28, Win sum 462, Final Vref 30
1953 12:29:53.371640
1954 12:29:53.375098 Final TX Range 1 Vref 30
1955 12:29:53.375188
1956 12:29:53.375254 ==
1957 12:29:53.378064 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 12:29:53.381707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 12:29:53.384798 ==
1960 12:29:53.384891
1961 12:29:53.384958
1962 12:29:53.385019 TX Vref Scan disable
1963 12:29:53.388899 == TX Byte 0 ==
1964 12:29:53.392068 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1965 12:29:53.398100 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1966 12:29:53.398210 == TX Byte 1 ==
1967 12:29:53.401574 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1968 12:29:53.407836 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1969 12:29:53.407942
1970 12:29:53.408014 [DATLAT]
1971 12:29:53.408076 Freq=800, CH1 RK1
1972 12:29:53.408137
1973 12:29:53.411655 DATLAT Default: 0xa
1974 12:29:53.411744 0, 0xFFFF, sum = 0
1975 12:29:53.414749 1, 0xFFFF, sum = 0
1976 12:29:53.414873 2, 0xFFFF, sum = 0
1977 12:29:53.417882 3, 0xFFFF, sum = 0
1978 12:29:53.421613 4, 0xFFFF, sum = 0
1979 12:29:53.421740 5, 0xFFFF, sum = 0
1980 12:29:53.424824 6, 0xFFFF, sum = 0
1981 12:29:53.424926 7, 0xFFFF, sum = 0
1982 12:29:53.428007 8, 0xFFFF, sum = 0
1983 12:29:53.428088 9, 0x0, sum = 1
1984 12:29:53.431471 10, 0x0, sum = 2
1985 12:29:53.431548 11, 0x0, sum = 3
1986 12:29:53.431640 12, 0x0, sum = 4
1987 12:29:53.434918 best_step = 10
1988 12:29:53.434998
1989 12:29:53.435061 ==
1990 12:29:53.438002 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 12:29:53.441180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 12:29:53.441284 ==
1993 12:29:53.444874 RX Vref Scan: 0
1994 12:29:53.444952
1995 12:29:53.445014 RX Vref 0 -> 0, step: 1
1996 12:29:53.447924
1997 12:29:53.447999 RX Delay -111 -> 252, step: 8
1998 12:29:53.454964 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1999 12:29:53.458463 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2000 12:29:53.461794 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2001 12:29:53.464802 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2002 12:29:53.471610 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2003 12:29:53.474697 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2004 12:29:53.478136 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2005 12:29:53.481480 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2006 12:29:53.485240 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2007 12:29:53.487954 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2008 12:29:53.494771 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2009 12:29:53.498393 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2010 12:29:53.501391 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2011 12:29:53.504547 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2012 12:29:53.511249 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2013 12:29:53.514275 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2014 12:29:53.514373 ==
2015 12:29:53.518055 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 12:29:53.521311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 12:29:53.521425 ==
2018 12:29:53.524290 DQS Delay:
2019 12:29:53.524389 DQS0 = 0, DQS1 = 0
2020 12:29:53.524456 DQM Delay:
2021 12:29:53.527900 DQM0 = 77, DQM1 = 73
2022 12:29:53.528014 DQ Delay:
2023 12:29:53.531034 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2024 12:29:53.534106 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2025 12:29:53.537869 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
2026 12:29:53.541062 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2027 12:29:53.541152
2028 12:29:53.541216
2029 12:29:53.550859 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d34, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2030 12:29:53.553889 CH1 RK1: MR19=606, MR18=1D34
2031 12:29:53.557842 CH1_RK1: MR19=0x606, MR18=0x1D34, DQSOSC=396, MR23=63, INC=94, DEC=62
2032 12:29:53.560854 [RxdqsGatingPostProcess] freq 800
2033 12:29:53.567322 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 12:29:53.570472 Pre-setting of DQS Precalculation
2035 12:29:53.574156 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 12:29:53.583971 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 12:29:53.590451 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 12:29:53.590576
2039 12:29:53.590648
2040 12:29:53.593882 [Calibration Summary] 1600 Mbps
2041 12:29:53.593971 CH 0, Rank 0
2042 12:29:53.597024 SW Impedance : PASS
2043 12:29:53.597113 DUTY Scan : NO K
2044 12:29:53.600484 ZQ Calibration : PASS
2045 12:29:53.603792 Jitter Meter : NO K
2046 12:29:53.603883 CBT Training : PASS
2047 12:29:53.607202 Write leveling : PASS
2048 12:29:53.610320 RX DQS gating : PASS
2049 12:29:53.610411 RX DQ/DQS(RDDQC) : PASS
2050 12:29:53.613811 TX DQ/DQS : PASS
2051 12:29:53.616901 RX DATLAT : PASS
2052 12:29:53.616989 RX DQ/DQS(Engine): PASS
2053 12:29:53.620774 TX OE : NO K
2054 12:29:53.620862 All Pass.
2055 12:29:53.620928
2056 12:29:53.623728 CH 0, Rank 1
2057 12:29:53.623817 SW Impedance : PASS
2058 12:29:53.626803 DUTY Scan : NO K
2059 12:29:53.630437 ZQ Calibration : PASS
2060 12:29:53.630530 Jitter Meter : NO K
2061 12:29:53.633511 CBT Training : PASS
2062 12:29:53.633601 Write leveling : PASS
2063 12:29:53.637174 RX DQS gating : PASS
2064 12:29:53.640319 RX DQ/DQS(RDDQC) : PASS
2065 12:29:53.640408 TX DQ/DQS : PASS
2066 12:29:53.643484 RX DATLAT : PASS
2067 12:29:53.646564 RX DQ/DQS(Engine): PASS
2068 12:29:53.646651 TX OE : NO K
2069 12:29:53.650222 All Pass.
2070 12:29:53.650310
2071 12:29:53.650377 CH 1, Rank 0
2072 12:29:53.653183 SW Impedance : PASS
2073 12:29:53.653269 DUTY Scan : NO K
2074 12:29:53.656931 ZQ Calibration : PASS
2075 12:29:53.659980 Jitter Meter : NO K
2076 12:29:53.660071 CBT Training : PASS
2077 12:29:53.662983 Write leveling : PASS
2078 12:29:53.666762 RX DQS gating : PASS
2079 12:29:53.666885 RX DQ/DQS(RDDQC) : PASS
2080 12:29:53.669822 TX DQ/DQS : PASS
2081 12:29:53.673309 RX DATLAT : PASS
2082 12:29:53.673400 RX DQ/DQS(Engine): PASS
2083 12:29:53.676818 TX OE : NO K
2084 12:29:53.676908 All Pass.
2085 12:29:53.676976
2086 12:29:53.679626 CH 1, Rank 1
2087 12:29:53.679711 SW Impedance : PASS
2088 12:29:53.683212 DUTY Scan : NO K
2089 12:29:53.686593 ZQ Calibration : PASS
2090 12:29:53.686685 Jitter Meter : NO K
2091 12:29:53.689508 CBT Training : PASS
2092 12:29:53.693176 Write leveling : PASS
2093 12:29:53.693268 RX DQS gating : PASS
2094 12:29:53.696649 RX DQ/DQS(RDDQC) : PASS
2095 12:29:53.696738 TX DQ/DQS : PASS
2096 12:29:53.699768 RX DATLAT : PASS
2097 12:29:53.703042 RX DQ/DQS(Engine): PASS
2098 12:29:53.703133 TX OE : NO K
2099 12:29:53.706075 All Pass.
2100 12:29:53.706164
2101 12:29:53.706230 DramC Write-DBI off
2102 12:29:53.709704 PER_BANK_REFRESH: Hybrid Mode
2103 12:29:53.713140 TX_TRACKING: ON
2104 12:29:53.715996 [GetDramInforAfterCalByMRR] Vendor 6.
2105 12:29:53.719605 [GetDramInforAfterCalByMRR] Revision 606.
2106 12:29:53.722586 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 12:29:53.722696 MR0 0x3b3b
2108 12:29:53.722762 MR8 0x5151
2109 12:29:53.729351 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 12:29:53.729451
2111 12:29:53.729518 MR0 0x3b3b
2112 12:29:53.729579 MR8 0x5151
2113 12:29:53.732925 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 12:29:53.733014
2115 12:29:53.742788 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 12:29:53.745956 [FAST_K] Save calibration result to emmc
2117 12:29:53.749010 [FAST_K] Save calibration result to emmc
2118 12:29:53.752756 dram_init: config_dvfs: 1
2119 12:29:53.755838 dramc_set_vcore_voltage set vcore to 662500
2120 12:29:53.759297 Read voltage for 1200, 2
2121 12:29:53.759416 Vio18 = 0
2122 12:29:53.762409 Vcore = 662500
2123 12:29:53.762520 Vdram = 0
2124 12:29:53.762615 Vddq = 0
2125 12:29:53.762709 Vmddr = 0
2126 12:29:53.769252 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 12:29:53.775623 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 12:29:53.775750 MEM_TYPE=3, freq_sel=15
2129 12:29:53.779077 sv_algorithm_assistance_LP4_1600
2130 12:29:53.782633 ============ PULL DRAM RESETB DOWN ============
2131 12:29:53.789121 ========== PULL DRAM RESETB DOWN end =========
2132 12:29:53.792078 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 12:29:53.795736 ===================================
2134 12:29:53.798931 LPDDR4 DRAM CONFIGURATION
2135 12:29:53.802124 ===================================
2136 12:29:53.802236 EX_ROW_EN[0] = 0x0
2137 12:29:53.805686 EX_ROW_EN[1] = 0x0
2138 12:29:53.805764 LP4Y_EN = 0x0
2139 12:29:53.808693 WORK_FSP = 0x0
2140 12:29:53.808784 WL = 0x4
2141 12:29:53.812784 RL = 0x4
2142 12:29:53.815488 BL = 0x2
2143 12:29:53.815577 RPST = 0x0
2144 12:29:53.819129 RD_PRE = 0x0
2145 12:29:53.819222 WR_PRE = 0x1
2146 12:29:53.822167 WR_PST = 0x0
2147 12:29:53.822253 DBI_WR = 0x0
2148 12:29:53.825598 DBI_RD = 0x0
2149 12:29:53.825691 OTF = 0x1
2150 12:29:53.828572 ===================================
2151 12:29:53.831749 ===================================
2152 12:29:53.835442 ANA top config
2153 12:29:53.838529 ===================================
2154 12:29:53.838647 DLL_ASYNC_EN = 0
2155 12:29:53.841929 ALL_SLAVE_EN = 0
2156 12:29:53.845207 NEW_RANK_MODE = 1
2157 12:29:53.848735 DLL_IDLE_MODE = 1
2158 12:29:53.848827 LP45_APHY_COMB_EN = 1
2159 12:29:53.851948 TX_ODT_DIS = 1
2160 12:29:53.855140 NEW_8X_MODE = 1
2161 12:29:53.858268 ===================================
2162 12:29:53.861869 ===================================
2163 12:29:53.865030 data_rate = 2400
2164 12:29:53.867997 CKR = 1
2165 12:29:53.871861 DQ_P2S_RATIO = 8
2166 12:29:53.874996 ===================================
2167 12:29:53.875091 CA_P2S_RATIO = 8
2168 12:29:53.878084 DQ_CA_OPEN = 0
2169 12:29:53.881206 DQ_SEMI_OPEN = 0
2170 12:29:53.884824 CA_SEMI_OPEN = 0
2171 12:29:53.888445 CA_FULL_RATE = 0
2172 12:29:53.891397 DQ_CKDIV4_EN = 0
2173 12:29:53.891493 CA_CKDIV4_EN = 0
2174 12:29:53.894732 CA_PREDIV_EN = 0
2175 12:29:53.897804 PH8_DLY = 17
2176 12:29:53.901712 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 12:29:53.904426 DQ_AAMCK_DIV = 4
2178 12:29:53.908127 CA_AAMCK_DIV = 4
2179 12:29:53.908214 CA_ADMCK_DIV = 4
2180 12:29:53.911173 DQ_TRACK_CA_EN = 0
2181 12:29:53.914694 CA_PICK = 1200
2182 12:29:53.917822 CA_MCKIO = 1200
2183 12:29:53.921402 MCKIO_SEMI = 0
2184 12:29:53.924409 PLL_FREQ = 2366
2185 12:29:53.927450 DQ_UI_PI_RATIO = 32
2186 12:29:53.930944 CA_UI_PI_RATIO = 0
2187 12:29:53.934468 ===================================
2188 12:29:53.937677 ===================================
2189 12:29:53.937795 memory_type:LPDDR4
2190 12:29:53.940737 GP_NUM : 10
2191 12:29:53.944383 SRAM_EN : 1
2192 12:29:53.944473 MD32_EN : 0
2193 12:29:53.947485 ===================================
2194 12:29:53.950700 [ANA_INIT] >>>>>>>>>>>>>>
2195 12:29:53.954335 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 12:29:53.957330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 12:29:53.960556 ===================================
2198 12:29:53.963761 data_rate = 2400,PCW = 0X5b00
2199 12:29:53.967218 ===================================
2200 12:29:53.970358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 12:29:53.974186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 12:29:53.980497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 12:29:53.983588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 12:29:53.987185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 12:29:53.990340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 12:29:53.994005 [ANA_INIT] flow start
2207 12:29:53.996965 [ANA_INIT] PLL >>>>>>>>
2208 12:29:53.997056 [ANA_INIT] PLL <<<<<<<<
2209 12:29:54.000538 [ANA_INIT] MIDPI >>>>>>>>
2210 12:29:54.003993 [ANA_INIT] MIDPI <<<<<<<<
2211 12:29:54.006808 [ANA_INIT] DLL >>>>>>>>
2212 12:29:54.006923 [ANA_INIT] DLL <<<<<<<<
2213 12:29:54.010342 [ANA_INIT] flow end
2214 12:29:54.013389 ============ LP4 DIFF to SE enter ============
2215 12:29:54.016992 ============ LP4 DIFF to SE exit ============
2216 12:29:54.020025 [ANA_INIT] <<<<<<<<<<<<<
2217 12:29:54.023556 [Flow] Enable top DCM control >>>>>
2218 12:29:54.026625 [Flow] Enable top DCM control <<<<<
2219 12:29:54.030200 Enable DLL master slave shuffle
2220 12:29:54.036830 ==============================================================
2221 12:29:54.036939 Gating Mode config
2222 12:29:54.043465 ==============================================================
2223 12:29:54.043570 Config description:
2224 12:29:54.053378 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 12:29:54.060296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 12:29:54.066498 SELPH_MODE 0: By rank 1: By Phase
2227 12:29:54.069777 ==============================================================
2228 12:29:54.073276 GAT_TRACK_EN = 1
2229 12:29:54.076442 RX_GATING_MODE = 2
2230 12:29:54.080244 RX_GATING_TRACK_MODE = 2
2231 12:29:54.083391 SELPH_MODE = 1
2232 12:29:54.086409 PICG_EARLY_EN = 1
2233 12:29:54.089494 VALID_LAT_VALUE = 1
2234 12:29:54.096160 ==============================================================
2235 12:29:54.099866 Enter into Gating configuration >>>>
2236 12:29:54.102654 Exit from Gating configuration <<<<
2237 12:29:54.102786 Enter into DVFS_PRE_config >>>>>
2238 12:29:54.116636 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 12:29:54.119620 Exit from DVFS_PRE_config <<<<<
2240 12:29:54.123011 Enter into PICG configuration >>>>
2241 12:29:54.126025 Exit from PICG configuration <<<<
2242 12:29:54.126156 [RX_INPUT] configuration >>>>>
2243 12:29:54.129608 [RX_INPUT] configuration <<<<<
2244 12:29:54.136424 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 12:29:54.139568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 12:29:54.145713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 12:29:54.152558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 12:29:54.158734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 12:29:54.165622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 12:29:54.168984 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 12:29:54.172365 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 12:29:54.179187 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 12:29:54.182409 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 12:29:54.185506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 12:29:54.191736 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 12:29:54.195255 ===================================
2257 12:29:54.195394 LPDDR4 DRAM CONFIGURATION
2258 12:29:54.198316 ===================================
2259 12:29:54.202116 EX_ROW_EN[0] = 0x0
2260 12:29:54.205082 EX_ROW_EN[1] = 0x0
2261 12:29:54.205192 LP4Y_EN = 0x0
2262 12:29:54.208591 WORK_FSP = 0x0
2263 12:29:54.208680 WL = 0x4
2264 12:29:54.211694 RL = 0x4
2265 12:29:54.211843 BL = 0x2
2266 12:29:54.215027 RPST = 0x0
2267 12:29:54.215116 RD_PRE = 0x0
2268 12:29:54.218570 WR_PRE = 0x1
2269 12:29:54.218659 WR_PST = 0x0
2270 12:29:54.221957 DBI_WR = 0x0
2271 12:29:54.222071 DBI_RD = 0x0
2272 12:29:54.224982 OTF = 0x1
2273 12:29:54.228598 ===================================
2274 12:29:54.231534 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 12:29:54.235127 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 12:29:54.241816 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 12:29:54.245298 ===================================
2278 12:29:54.245405 LPDDR4 DRAM CONFIGURATION
2279 12:29:54.248560 ===================================
2280 12:29:54.251882 EX_ROW_EN[0] = 0x10
2281 12:29:54.251975 EX_ROW_EN[1] = 0x0
2282 12:29:54.254693 LP4Y_EN = 0x0
2283 12:29:54.254807 WORK_FSP = 0x0
2284 12:29:54.258234 WL = 0x4
2285 12:29:54.261268 RL = 0x4
2286 12:29:54.261358 BL = 0x2
2287 12:29:54.264979 RPST = 0x0
2288 12:29:54.265068 RD_PRE = 0x0
2289 12:29:54.268089 WR_PRE = 0x1
2290 12:29:54.268175 WR_PST = 0x0
2291 12:29:54.271200 DBI_WR = 0x0
2292 12:29:54.271288 DBI_RD = 0x0
2293 12:29:54.274955 OTF = 0x1
2294 12:29:54.277948 ===================================
2295 12:29:54.284691 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 12:29:54.284829 ==
2297 12:29:54.287806 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 12:29:54.291573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 12:29:54.291667 ==
2300 12:29:54.294594 [Duty_Offset_Calibration]
2301 12:29:54.294679 B0:2 B1:0 CA:3
2302 12:29:54.294744
2303 12:29:54.298199 [DutyScan_Calibration_Flow] k_type=0
2304 12:29:54.307521
2305 12:29:54.307638 ==CLK 0==
2306 12:29:54.311020 Final CLK duty delay cell = 0
2307 12:29:54.314505 [0] MAX Duty = 5031%(X100), DQS PI = 12
2308 12:29:54.318099 [0] MIN Duty = 4906%(X100), DQS PI = 54
2309 12:29:54.318188 [0] AVG Duty = 4968%(X100)
2310 12:29:54.320999
2311 12:29:54.324534 CH0 CLK Duty spec in!! Max-Min= 125%
2312 12:29:54.328018 [DutyScan_Calibration_Flow] ====Done====
2313 12:29:54.328114
2314 12:29:54.330988 [DutyScan_Calibration_Flow] k_type=1
2315 12:29:54.346570
2316 12:29:54.346726 ==DQS 0 ==
2317 12:29:54.349598 Final DQS duty delay cell = 0
2318 12:29:54.353456 [0] MAX Duty = 5062%(X100), DQS PI = 12
2319 12:29:54.356220 [0] MIN Duty = 4907%(X100), DQS PI = 2
2320 12:29:54.359579 [0] AVG Duty = 4984%(X100)
2321 12:29:54.359677
2322 12:29:54.359744 ==DQS 1 ==
2323 12:29:54.362487 Final DQS duty delay cell = -4
2324 12:29:54.365922 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2325 12:29:54.369499 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2326 12:29:54.372517 [-4] AVG Duty = 4922%(X100)
2327 12:29:54.372600
2328 12:29:54.376224 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2329 12:29:54.376329
2330 12:29:54.379364 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2331 12:29:54.382294 [DutyScan_Calibration_Flow] ====Done====
2332 12:29:54.382370
2333 12:29:54.385870 [DutyScan_Calibration_Flow] k_type=3
2334 12:29:54.403822
2335 12:29:54.403961 ==DQM 0 ==
2336 12:29:54.406817 Final DQM duty delay cell = 0
2337 12:29:54.410507 [0] MAX Duty = 5124%(X100), DQS PI = 28
2338 12:29:54.413593 [0] MIN Duty = 4876%(X100), DQS PI = 0
2339 12:29:54.416614 [0] AVG Duty = 5000%(X100)
2340 12:29:54.416706
2341 12:29:54.416773 ==DQM 1 ==
2342 12:29:54.420172 Final DQM duty delay cell = 4
2343 12:29:54.423133 [4] MAX Duty = 5124%(X100), DQS PI = 50
2344 12:29:54.426985 [4] MIN Duty = 5031%(X100), DQS PI = 10
2345 12:29:54.429881 [4] AVG Duty = 5077%(X100)
2346 12:29:54.429982
2347 12:29:54.433302 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2348 12:29:54.433393
2349 12:29:54.436986 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2350 12:29:54.440070 [DutyScan_Calibration_Flow] ====Done====
2351 12:29:54.440168
2352 12:29:54.443173 [DutyScan_Calibration_Flow] k_type=2
2353 12:29:54.458660
2354 12:29:54.458850 ==DQ 0 ==
2355 12:29:54.461744 Final DQ duty delay cell = -4
2356 12:29:54.465337 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2357 12:29:54.468596 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2358 12:29:54.471469 [-4] AVG Duty = 4969%(X100)
2359 12:29:54.471566
2360 12:29:54.471634 ==DQ 1 ==
2361 12:29:54.474898 Final DQ duty delay cell = -4
2362 12:29:54.478270 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2363 12:29:54.481633 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2364 12:29:54.485193 [-4] AVG Duty = 4938%(X100)
2365 12:29:54.485315
2366 12:29:54.488440 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2367 12:29:54.488529
2368 12:29:54.491413 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2369 12:29:54.495110 [DutyScan_Calibration_Flow] ====Done====
2370 12:29:54.495202 ==
2371 12:29:54.498215 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 12:29:54.501323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 12:29:54.501415 ==
2374 12:29:54.505111 [Duty_Offset_Calibration]
2375 12:29:54.505199 B0:1 B1:-3 CA:0
2376 12:29:54.505268
2377 12:29:54.507990 [DutyScan_Calibration_Flow] k_type=0
2378 12:29:54.519311
2379 12:29:54.519442 ==CLK 0==
2380 12:29:54.522410 Final CLK duty delay cell = 0
2381 12:29:54.525396 [0] MAX Duty = 5031%(X100), DQS PI = 18
2382 12:29:54.529080 [0] MIN Duty = 4876%(X100), DQS PI = 2
2383 12:29:54.529181 [0] AVG Duty = 4953%(X100)
2384 12:29:54.532433
2385 12:29:54.535493 CH1 CLK Duty spec in!! Max-Min= 155%
2386 12:29:54.538761 [DutyScan_Calibration_Flow] ====Done====
2387 12:29:54.538896
2388 12:29:54.541856 [DutyScan_Calibration_Flow] k_type=1
2389 12:29:54.557680
2390 12:29:54.557817 ==DQS 0 ==
2391 12:29:54.560812 Final DQS duty delay cell = -4
2392 12:29:54.563932 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2393 12:29:54.567595 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2394 12:29:54.570595 [-4] AVG Duty = 4969%(X100)
2395 12:29:54.570691
2396 12:29:54.570764 ==DQS 1 ==
2397 12:29:54.574237 Final DQS duty delay cell = 0
2398 12:29:54.577219 [0] MAX Duty = 5094%(X100), DQS PI = 0
2399 12:29:54.580585 [0] MIN Duty = 4844%(X100), DQS PI = 26
2400 12:29:54.583991 [0] AVG Duty = 4969%(X100)
2401 12:29:54.584088
2402 12:29:54.587508 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2403 12:29:54.587599
2404 12:29:54.590681 CH1 DQS 1 Duty spec in!! Max-Min= 250%
2405 12:29:54.593800 [DutyScan_Calibration_Flow] ====Done====
2406 12:29:54.593890
2407 12:29:54.597502 [DutyScan_Calibration_Flow] k_type=3
2408 12:29:54.614689
2409 12:29:54.614854 ==DQM 0 ==
2410 12:29:54.618357 Final DQM duty delay cell = 4
2411 12:29:54.621563 [4] MAX Duty = 5156%(X100), DQS PI = 20
2412 12:29:54.625247 [4] MIN Duty = 4969%(X100), DQS PI = 56
2413 12:29:54.628384 [4] AVG Duty = 5062%(X100)
2414 12:29:54.628477
2415 12:29:54.628544 ==DQM 1 ==
2416 12:29:54.631401 Final DQM duty delay cell = 0
2417 12:29:54.634444 [0] MAX Duty = 5031%(X100), DQS PI = 36
2418 12:29:54.638018 [0] MIN Duty = 4875%(X100), DQS PI = 26
2419 12:29:54.641655 [0] AVG Duty = 4953%(X100)
2420 12:29:54.641774
2421 12:29:54.644571 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2422 12:29:54.644658
2423 12:29:54.648201 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2424 12:29:54.651637 [DutyScan_Calibration_Flow] ====Done====
2425 12:29:54.651755
2426 12:29:54.654609 [DutyScan_Calibration_Flow] k_type=2
2427 12:29:54.671826
2428 12:29:54.671966 ==DQ 0 ==
2429 12:29:54.674545 Final DQ duty delay cell = 0
2430 12:29:54.678096 [0] MAX Duty = 5093%(X100), DQS PI = 20
2431 12:29:54.681770 [0] MIN Duty = 4938%(X100), DQS PI = 54
2432 12:29:54.681863 [0] AVG Duty = 5015%(X100)
2433 12:29:54.684721
2434 12:29:54.684807 ==DQ 1 ==
2435 12:29:54.688135 Final DQ duty delay cell = 0
2436 12:29:54.691104 [0] MAX Duty = 5124%(X100), DQS PI = 36
2437 12:29:54.694776 [0] MIN Duty = 4938%(X100), DQS PI = 26
2438 12:29:54.697662 [0] AVG Duty = 5031%(X100)
2439 12:29:54.697750
2440 12:29:54.701486 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2441 12:29:54.701575
2442 12:29:54.704525 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2443 12:29:54.707635 [DutyScan_Calibration_Flow] ====Done====
2444 12:29:54.711421 nWR fixed to 30
2445 12:29:54.711510 [ModeRegInit_LP4] CH0 RK0
2446 12:29:54.714391 [ModeRegInit_LP4] CH0 RK1
2447 12:29:54.717873 [ModeRegInit_LP4] CH1 RK0
2448 12:29:54.720968 [ModeRegInit_LP4] CH1 RK1
2449 12:29:54.721058 match AC timing 7
2450 12:29:54.727397 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 12:29:54.731036 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 12:29:54.734128 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 12:29:54.740833 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 12:29:54.744329 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 12:29:54.744455 ==
2456 12:29:54.747331 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 12:29:54.750709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 12:29:54.750838 ==
2459 12:29:54.757290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 12:29:54.764051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2461 12:29:54.771541 [CA 0] Center 40 (10~71) winsize 62
2462 12:29:54.774644 [CA 1] Center 39 (9~70) winsize 62
2463 12:29:54.778682 [CA 2] Center 36 (6~66) winsize 61
2464 12:29:54.781459 [CA 3] Center 35 (5~66) winsize 62
2465 12:29:54.784477 [CA 4] Center 34 (4~65) winsize 62
2466 12:29:54.788366 [CA 5] Center 33 (3~64) winsize 62
2467 12:29:54.788484
2468 12:29:54.791077 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2469 12:29:54.791162
2470 12:29:54.797683 [CATrainingPosCal] consider 1 rank data
2471 12:29:54.797780 u2DelayCellTimex100 = 270/100 ps
2472 12:29:54.804489 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2473 12:29:54.807544 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2474 12:29:54.811250 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2475 12:29:54.814372 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 12:29:54.817501 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2477 12:29:54.821254 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2478 12:29:54.821377
2479 12:29:54.824131 CA PerBit enable=1, Macro0, CA PI delay=33
2480 12:29:54.824243
2481 12:29:54.827358 [CBTSetCACLKResult] CA Dly = 33
2482 12:29:54.831212 CS Dly: 7 (0~38)
2483 12:29:54.831306 ==
2484 12:29:54.834171 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 12:29:54.837401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 12:29:54.837506 ==
2487 12:29:54.843770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 12:29:54.847404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2489 12:29:54.857418 [CA 0] Center 40 (10~70) winsize 61
2490 12:29:54.860769 [CA 1] Center 40 (10~70) winsize 61
2491 12:29:54.864378 [CA 2] Center 35 (5~66) winsize 62
2492 12:29:54.867428 [CA 3] Center 35 (5~66) winsize 62
2493 12:29:54.870787 [CA 4] Center 34 (4~65) winsize 62
2494 12:29:54.874364 [CA 5] Center 33 (3~64) winsize 62
2495 12:29:54.874527
2496 12:29:54.877459 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 12:29:54.877600
2498 12:29:54.880463 [CATrainingPosCal] consider 2 rank data
2499 12:29:54.884164 u2DelayCellTimex100 = 270/100 ps
2500 12:29:54.887200 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2501 12:29:54.893988 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2502 12:29:54.897304 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2503 12:29:54.900809 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 12:29:54.903736 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2505 12:29:54.907422 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2506 12:29:54.907552
2507 12:29:54.910554 CA PerBit enable=1, Macro0, CA PI delay=33
2508 12:29:54.910688
2509 12:29:54.913662 [CBTSetCACLKResult] CA Dly = 33
2510 12:29:54.917363 CS Dly: 8 (0~40)
2511 12:29:54.917469
2512 12:29:54.920614 ----->DramcWriteLeveling(PI) begin...
2513 12:29:54.920703 ==
2514 12:29:54.924413 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 12:29:54.927049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 12:29:54.927166 ==
2517 12:29:54.930726 Write leveling (Byte 0): 34 => 34
2518 12:29:54.933715 Write leveling (Byte 1): 29 => 29
2519 12:29:54.937545 DramcWriteLeveling(PI) end<-----
2520 12:29:54.937658
2521 12:29:54.937739 ==
2522 12:29:54.940574 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 12:29:54.943843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 12:29:54.943935 ==
2525 12:29:54.946938 [Gating] SW mode calibration
2526 12:29:54.953757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 12:29:54.960886 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 12:29:54.963797 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 12:29:54.967044 0 15 4 | B1->B0 | 2626 3333 | 1 0 | (0 0) (0 0)
2530 12:29:54.973547 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 12:29:54.976986 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:29:54.980333 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 12:29:54.987351 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 12:29:54.990699 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 12:29:54.993529 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2536 12:29:55.000056 1 0 0 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
2537 12:29:55.003483 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2538 12:29:55.006980 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:29:55.013522 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:29:55.016802 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 12:29:55.019939 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 12:29:55.026726 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 12:29:55.029815 1 0 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2544 12:29:55.033434 1 1 0 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
2545 12:29:55.040030 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2546 12:29:55.043433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:29:55.046557 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:29:55.053376 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:29:55.056578 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 12:29:55.059769 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 12:29:55.063264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 12:29:55.069861 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2553 12:29:55.073223 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 12:29:55.076929 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:29:55.083228 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:29:55.086614 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:29:55.089536 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:29:55.096366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:29:55.099450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:29:55.102926 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:29:55.109308 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:29:55.112769 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:29:55.116261 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:29:55.122958 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:29:55.126097 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:29:55.129148 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:29:55.135923 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 12:29:55.138973 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2569 12:29:55.142604 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 12:29:55.145634 Total UI for P1: 0, mck2ui 16
2571 12:29:55.149490 best dqsien dly found for B0: ( 1, 3, 30)
2572 12:29:55.152551 Total UI for P1: 0, mck2ui 16
2573 12:29:55.155784 best dqsien dly found for B1: ( 1, 4, 0)
2574 12:29:55.159480 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2575 12:29:55.162611 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 12:29:55.162740
2577 12:29:55.168895 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2578 12:29:55.172568 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 12:29:55.172671 [Gating] SW calibration Done
2580 12:29:55.175577 ==
2581 12:29:55.179237 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 12:29:55.182516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 12:29:55.182635 ==
2584 12:29:55.182733 RX Vref Scan: 0
2585 12:29:55.182839
2586 12:29:55.185720 RX Vref 0 -> 0, step: 1
2587 12:29:55.185832
2588 12:29:55.188939 RX Delay -40 -> 252, step: 8
2589 12:29:55.192438 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2590 12:29:55.195961 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2591 12:29:55.201963 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2592 12:29:55.205643 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2593 12:29:55.208587 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2594 12:29:55.212400 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2595 12:29:55.215376 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2596 12:29:55.222179 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2597 12:29:55.225582 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2598 12:29:55.228622 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2599 12:29:55.231845 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2600 12:29:55.235575 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2601 12:29:55.241614 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2602 12:29:55.245551 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2603 12:29:55.248546 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2604 12:29:55.251824 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2605 12:29:55.251904 ==
2606 12:29:55.254819 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 12:29:55.261800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 12:29:55.261889 ==
2609 12:29:55.261960 DQS Delay:
2610 12:29:55.262051 DQS0 = 0, DQS1 = 0
2611 12:29:55.264908 DQM Delay:
2612 12:29:55.264981 DQM0 = 112, DQM1 = 102
2613 12:29:55.268115 DQ Delay:
2614 12:29:55.271830 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2615 12:29:55.274993 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2616 12:29:55.278413 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =95
2617 12:29:55.281567 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2618 12:29:55.281655
2619 12:29:55.281722
2620 12:29:55.281782 ==
2621 12:29:55.284636 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 12:29:55.288035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 12:29:55.288142 ==
2624 12:29:55.288209
2625 12:29:55.291570
2626 12:29:55.291658 TX Vref Scan disable
2627 12:29:55.294512 == TX Byte 0 ==
2628 12:29:55.298034 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2629 12:29:55.301507 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2630 12:29:55.304386 == TX Byte 1 ==
2631 12:29:55.307789 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2632 12:29:55.310898 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2633 12:29:55.310990 ==
2634 12:29:55.314723 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 12:29:55.321093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 12:29:55.321201 ==
2637 12:29:55.332297 TX Vref=22, minBit 5, minWin=25, winSum=418
2638 12:29:55.335730 TX Vref=24, minBit 0, minWin=26, winSum=420
2639 12:29:55.338766 TX Vref=26, minBit 1, minWin=26, winSum=428
2640 12:29:55.342353 TX Vref=28, minBit 2, minWin=26, winSum=431
2641 12:29:55.345327 TX Vref=30, minBit 10, minWin=26, winSum=431
2642 12:29:55.352332 TX Vref=32, minBit 1, minWin=26, winSum=428
2643 12:29:55.355272 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
2644 12:29:55.355380
2645 12:29:55.358516 Final TX Range 1 Vref 28
2646 12:29:55.358604
2647 12:29:55.358670 ==
2648 12:29:55.362264 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 12:29:55.365357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 12:29:55.368430 ==
2651 12:29:55.368522
2652 12:29:55.368589
2653 12:29:55.368649 TX Vref Scan disable
2654 12:29:55.372328 == TX Byte 0 ==
2655 12:29:55.375519 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2656 12:29:55.382052 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2657 12:29:55.382160 == TX Byte 1 ==
2658 12:29:55.385238 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2659 12:29:55.391865 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2660 12:29:55.391976
2661 12:29:55.392046 [DATLAT]
2662 12:29:55.392108 Freq=1200, CH0 RK0
2663 12:29:55.392166
2664 12:29:55.395682 DATLAT Default: 0xd
2665 12:29:55.395771 0, 0xFFFF, sum = 0
2666 12:29:55.398668 1, 0xFFFF, sum = 0
2667 12:29:55.402180 2, 0xFFFF, sum = 0
2668 12:29:55.402271 3, 0xFFFF, sum = 0
2669 12:29:55.405433 4, 0xFFFF, sum = 0
2670 12:29:55.405574 5, 0xFFFF, sum = 0
2671 12:29:55.408686 6, 0xFFFF, sum = 0
2672 12:29:55.408775 7, 0xFFFF, sum = 0
2673 12:29:55.412165 8, 0xFFFF, sum = 0
2674 12:29:55.412255 9, 0xFFFF, sum = 0
2675 12:29:55.414994 10, 0xFFFF, sum = 0
2676 12:29:55.415084 11, 0xFFFF, sum = 0
2677 12:29:55.418734 12, 0x0, sum = 1
2678 12:29:55.418884 13, 0x0, sum = 2
2679 12:29:55.422277 14, 0x0, sum = 3
2680 12:29:55.422365 15, 0x0, sum = 4
2681 12:29:55.425256 best_step = 13
2682 12:29:55.425404
2683 12:29:55.425481 ==
2684 12:29:55.428319 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 12:29:55.431873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 12:29:55.431990 ==
2687 12:29:55.432085 RX Vref Scan: 1
2688 12:29:55.434718
2689 12:29:55.434836 Set Vref Range= 32 -> 127
2690 12:29:55.434907
2691 12:29:55.438330 RX Vref 32 -> 127, step: 1
2692 12:29:55.438444
2693 12:29:55.441661 RX Delay -37 -> 252, step: 4
2694 12:29:55.441773
2695 12:29:55.444721 Set Vref, RX VrefLevel [Byte0]: 32
2696 12:29:55.448272 [Byte1]: 32
2697 12:29:55.448358
2698 12:29:55.451325 Set Vref, RX VrefLevel [Byte0]: 33
2699 12:29:55.454570 [Byte1]: 33
2700 12:29:55.458492
2701 12:29:55.458601 Set Vref, RX VrefLevel [Byte0]: 34
2702 12:29:55.462515 [Byte1]: 34
2703 12:29:55.466824
2704 12:29:55.466926 Set Vref, RX VrefLevel [Byte0]: 35
2705 12:29:55.469867 [Byte1]: 35
2706 12:29:55.474817
2707 12:29:55.474955 Set Vref, RX VrefLevel [Byte0]: 36
2708 12:29:55.477935 [Byte1]: 36
2709 12:29:55.482826
2710 12:29:55.482980 Set Vref, RX VrefLevel [Byte0]: 37
2711 12:29:55.485858 [Byte1]: 37
2712 12:29:55.490758
2713 12:29:55.490925 Set Vref, RX VrefLevel [Byte0]: 38
2714 12:29:55.494404 [Byte1]: 38
2715 12:29:55.498659
2716 12:29:55.498778 Set Vref, RX VrefLevel [Byte0]: 39
2717 12:29:55.501896 [Byte1]: 39
2718 12:29:55.506688
2719 12:29:55.506803 Set Vref, RX VrefLevel [Byte0]: 40
2720 12:29:55.510155 [Byte1]: 40
2721 12:29:55.514985
2722 12:29:55.515126 Set Vref, RX VrefLevel [Byte0]: 41
2723 12:29:55.518336 [Byte1]: 41
2724 12:29:55.522537
2725 12:29:55.522651 Set Vref, RX VrefLevel [Byte0]: 42
2726 12:29:55.525946 [Byte1]: 42
2727 12:29:55.530703
2728 12:29:55.530798 Set Vref, RX VrefLevel [Byte0]: 43
2729 12:29:55.534229 [Byte1]: 43
2730 12:29:55.538769
2731 12:29:55.538885 Set Vref, RX VrefLevel [Byte0]: 44
2732 12:29:55.542374 [Byte1]: 44
2733 12:29:55.546968
2734 12:29:55.547071 Set Vref, RX VrefLevel [Byte0]: 45
2735 12:29:55.550212 [Byte1]: 45
2736 12:29:55.554684
2737 12:29:55.554784 Set Vref, RX VrefLevel [Byte0]: 46
2738 12:29:55.557767 [Byte1]: 46
2739 12:29:55.562795
2740 12:29:55.562936 Set Vref, RX VrefLevel [Byte0]: 47
2741 12:29:55.566302 [Byte1]: 47
2742 12:29:55.570790
2743 12:29:55.570929 Set Vref, RX VrefLevel [Byte0]: 48
2744 12:29:55.574029 [Byte1]: 48
2745 12:29:55.578975
2746 12:29:55.579083 Set Vref, RX VrefLevel [Byte0]: 49
2747 12:29:55.582244 [Byte1]: 49
2748 12:29:55.587449
2749 12:29:55.587556 Set Vref, RX VrefLevel [Byte0]: 50
2750 12:29:55.590097 [Byte1]: 50
2751 12:29:55.594498
2752 12:29:55.594591 Set Vref, RX VrefLevel [Byte0]: 51
2753 12:29:55.598238 [Byte1]: 51
2754 12:29:55.603107
2755 12:29:55.603206 Set Vref, RX VrefLevel [Byte0]: 52
2756 12:29:55.606201 [Byte1]: 52
2757 12:29:55.610543
2758 12:29:55.610637 Set Vref, RX VrefLevel [Byte0]: 53
2759 12:29:55.614359 [Byte1]: 53
2760 12:29:55.618627
2761 12:29:55.618723 Set Vref, RX VrefLevel [Byte0]: 54
2762 12:29:55.622124 [Byte1]: 54
2763 12:29:55.626702
2764 12:29:55.626835 Set Vref, RX VrefLevel [Byte0]: 55
2765 12:29:55.630198 [Byte1]: 55
2766 12:29:55.634786
2767 12:29:55.634923 Set Vref, RX VrefLevel [Byte0]: 56
2768 12:29:55.638715 [Byte1]: 56
2769 12:29:55.642840
2770 12:29:55.642949 Set Vref, RX VrefLevel [Byte0]: 57
2771 12:29:55.645719 [Byte1]: 57
2772 12:29:55.651041
2773 12:29:55.651142 Set Vref, RX VrefLevel [Byte0]: 58
2774 12:29:55.653907 [Byte1]: 58
2775 12:29:55.659079
2776 12:29:55.659180 Set Vref, RX VrefLevel [Byte0]: 59
2777 12:29:55.661822 [Byte1]: 59
2778 12:29:55.666725
2779 12:29:55.666820 Set Vref, RX VrefLevel [Byte0]: 60
2780 12:29:55.669847 [Byte1]: 60
2781 12:29:55.674735
2782 12:29:55.674853 Set Vref, RX VrefLevel [Byte0]: 61
2783 12:29:55.677861 [Byte1]: 61
2784 12:29:55.682912
2785 12:29:55.683009 Set Vref, RX VrefLevel [Byte0]: 62
2786 12:29:55.685986 [Byte1]: 62
2787 12:29:55.690970
2788 12:29:55.691088 Set Vref, RX VrefLevel [Byte0]: 63
2789 12:29:55.693959 [Byte1]: 63
2790 12:29:55.698780
2791 12:29:55.698927 Set Vref, RX VrefLevel [Byte0]: 64
2792 12:29:55.701857 [Byte1]: 64
2793 12:29:55.706724
2794 12:29:55.706869 Set Vref, RX VrefLevel [Byte0]: 65
2795 12:29:55.709743 [Byte1]: 65
2796 12:29:55.714998
2797 12:29:55.715095 Set Vref, RX VrefLevel [Byte0]: 66
2798 12:29:55.718075 [Byte1]: 66
2799 12:29:55.722501
2800 12:29:55.722595 Set Vref, RX VrefLevel [Byte0]: 67
2801 12:29:55.726103 [Byte1]: 67
2802 12:29:55.730841
2803 12:29:55.730976 Set Vref, RX VrefLevel [Byte0]: 68
2804 12:29:55.733863 [Byte1]: 68
2805 12:29:55.738986
2806 12:29:55.739086 Set Vref, RX VrefLevel [Byte0]: 69
2807 12:29:55.741876 [Byte1]: 69
2808 12:29:55.746740
2809 12:29:55.746858 Set Vref, RX VrefLevel [Byte0]: 70
2810 12:29:55.750325 [Byte1]: 70
2811 12:29:55.754488
2812 12:29:55.754587 Set Vref, RX VrefLevel [Byte0]: 71
2813 12:29:55.758333 [Byte1]: 71
2814 12:29:55.762709
2815 12:29:55.762806 Set Vref, RX VrefLevel [Byte0]: 72
2816 12:29:55.766102 [Byte1]: 72
2817 12:29:55.770786
2818 12:29:55.770928 Set Vref, RX VrefLevel [Byte0]: 73
2819 12:29:55.773866 [Byte1]: 73
2820 12:29:55.778724
2821 12:29:55.778822 Set Vref, RX VrefLevel [Byte0]: 74
2822 12:29:55.781836 [Byte1]: 74
2823 12:29:55.786813
2824 12:29:55.786973 Final RX Vref Byte 0 = 63 to rank0
2825 12:29:55.790015 Final RX Vref Byte 1 = 58 to rank0
2826 12:29:55.793147 Final RX Vref Byte 0 = 63 to rank1
2827 12:29:55.796905 Final RX Vref Byte 1 = 58 to rank1==
2828 12:29:55.800122 Dram Type= 6, Freq= 0, CH_0, rank 0
2829 12:29:55.806518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 12:29:55.806626 ==
2831 12:29:55.806731 DQS Delay:
2832 12:29:55.809990 DQS0 = 0, DQS1 = 0
2833 12:29:55.810081 DQM Delay:
2834 12:29:55.810169 DQM0 = 112, DQM1 = 102
2835 12:29:55.813069 DQ Delay:
2836 12:29:55.816214 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =106
2837 12:29:55.819882 DQ4 =114, DQ5 =104, DQ6 =120, DQ7 =120
2838 12:29:55.822957 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2839 12:29:55.826251 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2840 12:29:55.826400
2841 12:29:55.826490
2842 12:29:55.836131 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2843 12:29:55.836249 CH0 RK0: MR19=303, MR18=F9F9
2844 12:29:55.842730 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2845 12:29:55.842850
2846 12:29:55.846276 ----->DramcWriteLeveling(PI) begin...
2847 12:29:55.846368 ==
2848 12:29:55.849122 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 12:29:55.855868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 12:29:55.855976 ==
2851 12:29:55.859343 Write leveling (Byte 0): 31 => 31
2852 12:29:55.862967 Write leveling (Byte 1): 31 => 31
2853 12:29:55.863080 DramcWriteLeveling(PI) end<-----
2854 12:29:55.865528
2855 12:29:55.865626 ==
2856 12:29:55.869054 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 12:29:55.872471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 12:29:55.872560 ==
2859 12:29:55.875886 [Gating] SW mode calibration
2860 12:29:55.882451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2861 12:29:55.886126 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2862 12:29:55.892301 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2863 12:29:55.895960 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:29:55.899037 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 12:29:55.905652 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 12:29:55.908700 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 12:29:55.912444 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 12:29:55.919253 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2869 12:29:55.922424 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
2870 12:29:55.925546 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2871 12:29:55.932432 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:29:55.935572 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 12:29:55.939002 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 12:29:55.945513 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 12:29:55.949001 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 12:29:55.951935 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2877 12:29:55.959233 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2878 12:29:55.962345 1 1 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2879 12:29:55.965433 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:29:55.971813 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:29:55.975253 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 12:29:55.978680 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 12:29:55.985030 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 12:29:55.988509 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 12:29:55.992115 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2886 12:29:55.998428 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2887 12:29:56.002040 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:29:56.005006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:29:56.012056 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:29:56.015019 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:29:56.018494 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:29:56.024997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:29:56.028834 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:29:56.031676 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:29:56.038346 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:29:56.041490 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:29:56.044644 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 12:29:56.048397 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 12:29:56.054990 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 12:29:56.058373 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2901 12:29:56.061274 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2902 12:29:56.068283 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2903 12:29:56.071300 Total UI for P1: 0, mck2ui 16
2904 12:29:56.074917 best dqsien dly found for B0: ( 1, 3, 26)
2905 12:29:56.077687 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 12:29:56.081461 Total UI for P1: 0, mck2ui 16
2907 12:29:56.084580 best dqsien dly found for B1: ( 1, 4, 0)
2908 12:29:56.087481 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2909 12:29:56.090916 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2910 12:29:56.091002
2911 12:29:56.094340 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2912 12:29:56.097853 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2913 12:29:56.100752 [Gating] SW calibration Done
2914 12:29:56.100837 ==
2915 12:29:56.104541 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 12:29:56.111233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 12:29:56.111338 ==
2918 12:29:56.111406 RX Vref Scan: 0
2919 12:29:56.111465
2920 12:29:56.114334 RX Vref 0 -> 0, step: 1
2921 12:29:56.114420
2922 12:29:56.117387 RX Delay -40 -> 252, step: 8
2923 12:29:56.121008 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2924 12:29:56.124139 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2925 12:29:56.127859 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2926 12:29:56.131041 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2927 12:29:56.137294 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2928 12:29:56.141113 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2929 12:29:56.144123 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2930 12:29:56.147330 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2931 12:29:56.151081 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2932 12:29:56.157415 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2933 12:29:56.161042 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2934 12:29:56.164226 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2935 12:29:56.167241 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2936 12:29:56.170674 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2937 12:29:56.177179 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2938 12:29:56.180775 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2939 12:29:56.180885 ==
2940 12:29:56.183969 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 12:29:56.187553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 12:29:56.187648 ==
2943 12:29:56.190621 DQS Delay:
2944 12:29:56.190710 DQS0 = 0, DQS1 = 0
2945 12:29:56.190774 DQM Delay:
2946 12:29:56.193815 DQM0 = 111, DQM1 = 102
2947 12:29:56.193902 DQ Delay:
2948 12:29:56.197145 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2949 12:29:56.200417 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2950 12:29:56.203804 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2951 12:29:56.210751 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2952 12:29:56.210924
2953 12:29:56.211002
2954 12:29:56.211072 ==
2955 12:29:56.213611 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 12:29:56.217222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 12:29:56.217315 ==
2958 12:29:56.217382
2959 12:29:56.217444
2960 12:29:56.220395 TX Vref Scan disable
2961 12:29:56.220481 == TX Byte 0 ==
2962 12:29:56.226917 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2963 12:29:56.230630 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2964 12:29:56.230760 == TX Byte 1 ==
2965 12:29:56.236801 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2966 12:29:56.240035 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2967 12:29:56.240135 ==
2968 12:29:56.243767 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 12:29:56.246856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 12:29:56.246964 ==
2971 12:29:56.259329 TX Vref=22, minBit 0, minWin=26, winSum=427
2972 12:29:56.263072 TX Vref=24, minBit 3, minWin=26, winSum=427
2973 12:29:56.266172 TX Vref=26, minBit 0, minWin=27, winSum=437
2974 12:29:56.269372 TX Vref=28, minBit 1, minWin=27, winSum=442
2975 12:29:56.273033 TX Vref=30, minBit 2, minWin=27, winSum=440
2976 12:29:56.279646 TX Vref=32, minBit 13, minWin=26, winSum=440
2977 12:29:56.282856 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
2978 12:29:56.282977
2979 12:29:56.285844 Final TX Range 1 Vref 28
2980 12:29:56.285931
2981 12:29:56.285996 ==
2982 12:29:56.289388 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 12:29:56.292527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 12:29:56.295711 ==
2985 12:29:56.295802
2986 12:29:56.295868
2987 12:29:56.295928 TX Vref Scan disable
2988 12:29:56.299193 == TX Byte 0 ==
2989 12:29:56.302707 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2990 12:29:56.306152 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2991 12:29:56.309536 == TX Byte 1 ==
2992 12:29:56.312297 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2993 12:29:56.319291 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2994 12:29:56.319404
2995 12:29:56.319506 [DATLAT]
2996 12:29:56.319568 Freq=1200, CH0 RK1
2997 12:29:56.319626
2998 12:29:56.322890 DATLAT Default: 0xd
2999 12:29:56.322992 0, 0xFFFF, sum = 0
3000 12:29:56.326060 1, 0xFFFF, sum = 0
3001 12:29:56.326151 2, 0xFFFF, sum = 0
3002 12:29:56.329059 3, 0xFFFF, sum = 0
3003 12:29:56.332470 4, 0xFFFF, sum = 0
3004 12:29:56.332564 5, 0xFFFF, sum = 0
3005 12:29:56.336128 6, 0xFFFF, sum = 0
3006 12:29:56.336217 7, 0xFFFF, sum = 0
3007 12:29:56.339388 8, 0xFFFF, sum = 0
3008 12:29:56.339477 9, 0xFFFF, sum = 0
3009 12:29:56.342521 10, 0xFFFF, sum = 0
3010 12:29:56.342609 11, 0xFFFF, sum = 0
3011 12:29:56.345613 12, 0x0, sum = 1
3012 12:29:56.345702 13, 0x0, sum = 2
3013 12:29:56.349510 14, 0x0, sum = 3
3014 12:29:56.349599 15, 0x0, sum = 4
3015 12:29:56.349666 best_step = 13
3016 12:29:56.352528
3017 12:29:56.352615 ==
3018 12:29:56.355668 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 12:29:56.358803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 12:29:56.358923 ==
3021 12:29:56.358991 RX Vref Scan: 0
3022 12:29:56.359054
3023 12:29:56.362534 RX Vref 0 -> 0, step: 1
3024 12:29:56.362622
3025 12:29:56.365480 RX Delay -29 -> 252, step: 4
3026 12:29:56.368720 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3027 12:29:56.375970 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3028 12:29:56.379288 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3029 12:29:56.382353 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3030 12:29:56.385813 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3031 12:29:56.389073 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3032 12:29:56.395557 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3033 12:29:56.398630 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3034 12:29:56.402224 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3035 12:29:56.405239 iDelay=195, Bit 9, Center 86 (15 ~ 158) 144
3036 12:29:56.408738 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3037 12:29:56.415619 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3038 12:29:56.418514 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3039 12:29:56.421911 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3040 12:29:56.425364 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3041 12:29:56.431543 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3042 12:29:56.431657 ==
3043 12:29:56.435098 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 12:29:56.438141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 12:29:56.438233 ==
3046 12:29:56.438297 DQS Delay:
3047 12:29:56.441947 DQS0 = 0, DQS1 = 0
3048 12:29:56.442025 DQM Delay:
3049 12:29:56.445042 DQM0 = 110, DQM1 = 102
3050 12:29:56.445115 DQ Delay:
3051 12:29:56.448310 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3052 12:29:56.451381 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3053 12:29:56.454956 DQ8 =90, DQ9 =86, DQ10 =102, DQ11 =94
3054 12:29:56.458092 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3055 12:29:56.458185
3056 12:29:56.458252
3057 12:29:56.468292 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3058 12:29:56.471472 CH0 RK1: MR19=403, MR18=11F9
3059 12:29:56.474697 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3060 12:29:56.477746 [RxdqsGatingPostProcess] freq 1200
3061 12:29:56.484700 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3062 12:29:56.487788 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 12:29:56.491302 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 12:29:56.494344 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 12:29:56.497704 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 12:29:56.501142 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 12:29:56.504485 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 12:29:56.507936 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 12:29:56.511127 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 12:29:56.514353 Pre-setting of DQS Precalculation
3071 12:29:56.517482 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3072 12:29:56.517579 ==
3073 12:29:56.520698 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 12:29:56.524538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 12:29:56.524637 ==
3076 12:29:56.530717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 12:29:56.537346 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3078 12:29:56.545420 [CA 0] Center 37 (7~67) winsize 61
3079 12:29:56.548535 [CA 1] Center 37 (7~68) winsize 62
3080 12:29:56.552260 [CA 2] Center 34 (4~64) winsize 61
3081 12:29:56.555372 [CA 3] Center 33 (3~64) winsize 62
3082 12:29:56.558436 [CA 4] Center 34 (4~64) winsize 61
3083 12:29:56.562205 [CA 5] Center 33 (3~63) winsize 61
3084 12:29:56.562305
3085 12:29:56.565275 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3086 12:29:56.565356
3087 12:29:56.568478 [CATrainingPosCal] consider 1 rank data
3088 12:29:56.571536 u2DelayCellTimex100 = 270/100 ps
3089 12:29:56.575320 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3090 12:29:56.581518 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 12:29:56.584961 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 12:29:56.588502 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3093 12:29:56.591605 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 12:29:56.594744 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3095 12:29:56.594898
3096 12:29:56.598484 CA PerBit enable=1, Macro0, CA PI delay=33
3097 12:29:56.598592
3098 12:29:56.601548 [CBTSetCACLKResult] CA Dly = 33
3099 12:29:56.604608 CS Dly: 6 (0~37)
3100 12:29:56.604689 ==
3101 12:29:56.608001 Dram Type= 6, Freq= 0, CH_1, rank 1
3102 12:29:56.611562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 12:29:56.611659 ==
3104 12:29:56.618125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 12:29:56.621517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3106 12:29:56.631313 [CA 0] Center 37 (8~67) winsize 60
3107 12:29:56.634292 [CA 1] Center 37 (7~68) winsize 62
3108 12:29:56.637806 [CA 2] Center 34 (4~65) winsize 62
3109 12:29:56.640676 [CA 3] Center 33 (3~64) winsize 62
3110 12:29:56.644075 [CA 4] Center 34 (4~65) winsize 62
3111 12:29:56.647302 [CA 5] Center 33 (3~63) winsize 61
3112 12:29:56.647422
3113 12:29:56.650755 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3114 12:29:56.650901
3115 12:29:56.654153 [CATrainingPosCal] consider 2 rank data
3116 12:29:56.657293 u2DelayCellTimex100 = 270/100 ps
3117 12:29:56.660959 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3118 12:29:56.667201 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 12:29:56.671017 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 12:29:56.674188 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3121 12:29:56.677275 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 12:29:56.680850 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3123 12:29:56.680964
3124 12:29:56.683935 CA PerBit enable=1, Macro0, CA PI delay=33
3125 12:29:56.684027
3126 12:29:56.687560 [CBTSetCACLKResult] CA Dly = 33
3127 12:29:56.687650 CS Dly: 7 (0~39)
3128 12:29:56.690658
3129 12:29:56.694233 ----->DramcWriteLeveling(PI) begin...
3130 12:29:56.694330 ==
3131 12:29:56.697350 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 12:29:56.700428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 12:29:56.700522 ==
3134 12:29:56.704097 Write leveling (Byte 0): 25 => 25
3135 12:29:56.707177 Write leveling (Byte 1): 31 => 31
3136 12:29:56.710279 DramcWriteLeveling(PI) end<-----
3137 12:29:56.710418
3138 12:29:56.710517 ==
3139 12:29:56.713840 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 12:29:56.717166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 12:29:56.717260 ==
3142 12:29:56.720729 [Gating] SW mode calibration
3143 12:29:56.727077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3144 12:29:56.733283 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3145 12:29:56.736895 0 15 0 | B1->B0 | 2d2d 2828 | 1 0 | (0 0) (0 0)
3146 12:29:56.740697 0 15 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
3147 12:29:56.746807 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 12:29:56.750399 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 12:29:56.753412 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 12:29:56.760075 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 12:29:56.763498 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 12:29:56.767182 0 15 28 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (0 1)
3153 12:29:56.773396 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3154 12:29:56.776460 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 12:29:56.780254 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 12:29:56.786588 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 12:29:56.790378 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 12:29:56.793388 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 12:29:56.800285 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3160 12:29:56.803464 1 0 28 | B1->B0 | 3838 3434 | 0 0 | (0 0) (0 0)
3161 12:29:56.806512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:29:56.810303 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:29:56.816373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 12:29:56.820056 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:29:56.823102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 12:29:56.830027 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 12:29:56.833004 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 12:29:56.836568 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 12:29:56.843317 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3170 12:29:56.846341 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:29:56.849791 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:29:56.856423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:29:56.859411 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:29:56.862880 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:29:56.869231 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:29:56.872617 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:29:56.876401 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:29:56.883065 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:29:56.886107 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:29:56.889804 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:29:56.895938 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 12:29:56.899668 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 12:29:56.902762 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 12:29:56.909060 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3185 12:29:56.912833 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 12:29:56.915963 Total UI for P1: 0, mck2ui 16
3187 12:29:56.919143 best dqsien dly found for B0: ( 1, 3, 28)
3188 12:29:56.922309 Total UI for P1: 0, mck2ui 16
3189 12:29:56.926079 best dqsien dly found for B1: ( 1, 3, 28)
3190 12:29:56.929270 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3191 12:29:56.932198 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3192 12:29:56.932299
3193 12:29:56.935674 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3194 12:29:56.939121 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3195 12:29:56.942448 [Gating] SW calibration Done
3196 12:29:56.942565 ==
3197 12:29:56.945906 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 12:29:56.952373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 12:29:56.952487 ==
3200 12:29:56.952556 RX Vref Scan: 0
3201 12:29:56.952619
3202 12:29:56.955441 RX Vref 0 -> 0, step: 1
3203 12:29:56.955531
3204 12:29:56.958558 RX Delay -40 -> 252, step: 8
3205 12:29:56.961849 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3206 12:29:56.965533 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3207 12:29:56.968602 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3208 12:29:56.972166 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3209 12:29:56.978577 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3210 12:29:56.982122 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3211 12:29:56.985273 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3212 12:29:56.988946 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3213 12:29:56.992000 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3214 12:29:56.998974 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3215 12:29:57.001972 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3216 12:29:57.005103 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3217 12:29:57.008801 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3218 12:29:57.011911 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3219 12:29:57.018713 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3220 12:29:57.021782 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3221 12:29:57.021878 ==
3222 12:29:57.025460 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 12:29:57.028601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 12:29:57.028781 ==
3225 12:29:57.031777 DQS Delay:
3226 12:29:57.031889 DQS0 = 0, DQS1 = 0
3227 12:29:57.031995 DQM Delay:
3228 12:29:57.035351 DQM0 = 114, DQM1 = 104
3229 12:29:57.035468 DQ Delay:
3230 12:29:57.038413 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =115
3231 12:29:57.041992 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3232 12:29:57.044968 DQ8 =91, DQ9 =99, DQ10 =103, DQ11 =99
3233 12:29:57.051811 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3234 12:29:57.051923
3235 12:29:57.051993
3236 12:29:57.052055 ==
3237 12:29:57.054638 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 12:29:57.058324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 12:29:57.058470 ==
3240 12:29:57.058540
3241 12:29:57.058606
3242 12:29:57.061943 TX Vref Scan disable
3243 12:29:57.062034 == TX Byte 0 ==
3244 12:29:57.068435 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3245 12:29:57.071320 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3246 12:29:57.071418 == TX Byte 1 ==
3247 12:29:57.077914 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3248 12:29:57.081386 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3249 12:29:57.081490 ==
3250 12:29:57.084772 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 12:29:57.088169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 12:29:57.088270 ==
3253 12:29:57.101220 TX Vref=22, minBit 8, minWin=25, winSum=418
3254 12:29:57.104273 TX Vref=24, minBit 8, minWin=25, winSum=420
3255 12:29:57.107993 TX Vref=26, minBit 1, minWin=26, winSum=429
3256 12:29:57.111087 TX Vref=28, minBit 1, minWin=26, winSum=430
3257 12:29:57.114205 TX Vref=30, minBit 8, minWin=26, winSum=433
3258 12:29:57.121075 TX Vref=32, minBit 0, minWin=26, winSum=432
3259 12:29:57.124789 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3260 12:29:57.124896
3261 12:29:57.127836 Final TX Range 1 Vref 30
3262 12:29:57.127926
3263 12:29:57.127992 ==
3264 12:29:57.130956 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 12:29:57.134697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 12:29:57.137742 ==
3267 12:29:57.137837
3268 12:29:57.137905
3269 12:29:57.137967 TX Vref Scan disable
3270 12:29:57.140891 == TX Byte 0 ==
3271 12:29:57.144439 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3272 12:29:57.148212 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3273 12:29:57.151135 == TX Byte 1 ==
3274 12:29:57.154520 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3275 12:29:57.157747 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3276 12:29:57.160689
3277 12:29:57.160787 [DATLAT]
3278 12:29:57.160857 Freq=1200, CH1 RK0
3279 12:29:57.160941
3280 12:29:57.164142 DATLAT Default: 0xd
3281 12:29:57.164238 0, 0xFFFF, sum = 0
3282 12:29:57.167500 1, 0xFFFF, sum = 0
3283 12:29:57.170987 2, 0xFFFF, sum = 0
3284 12:29:57.171122 3, 0xFFFF, sum = 0
3285 12:29:57.173968 4, 0xFFFF, sum = 0
3286 12:29:57.174091 5, 0xFFFF, sum = 0
3287 12:29:57.177418 6, 0xFFFF, sum = 0
3288 12:29:57.177614 7, 0xFFFF, sum = 0
3289 12:29:57.180775 8, 0xFFFF, sum = 0
3290 12:29:57.180864 9, 0xFFFF, sum = 0
3291 12:29:57.183822 10, 0xFFFF, sum = 0
3292 12:29:57.183944 11, 0xFFFF, sum = 0
3293 12:29:57.187091 12, 0x0, sum = 1
3294 12:29:57.187188 13, 0x0, sum = 2
3295 12:29:57.190639 14, 0x0, sum = 3
3296 12:29:57.190759 15, 0x0, sum = 4
3297 12:29:57.193612 best_step = 13
3298 12:29:57.193719
3299 12:29:57.193825 ==
3300 12:29:57.197496 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 12:29:57.200286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 12:29:57.200372 ==
3303 12:29:57.200444 RX Vref Scan: 1
3304 12:29:57.203987
3305 12:29:57.204070 Set Vref Range= 32 -> 127
3306 12:29:57.204147
3307 12:29:57.207049 RX Vref 32 -> 127, step: 1
3308 12:29:57.207139
3309 12:29:57.210743 RX Delay -21 -> 252, step: 4
3310 12:29:57.210886
3311 12:29:57.213852 Set Vref, RX VrefLevel [Byte0]: 32
3312 12:29:57.216967 [Byte1]: 32
3313 12:29:57.217082
3314 12:29:57.220129 Set Vref, RX VrefLevel [Byte0]: 33
3315 12:29:57.223853 [Byte1]: 33
3316 12:29:57.227408
3317 12:29:57.227497 Set Vref, RX VrefLevel [Byte0]: 34
3318 12:29:57.234258 [Byte1]: 34
3319 12:29:57.234375
3320 12:29:57.237342 Set Vref, RX VrefLevel [Byte0]: 35
3321 12:29:57.240467 [Byte1]: 35
3322 12:29:57.240554
3323 12:29:57.244202 Set Vref, RX VrefLevel [Byte0]: 36
3324 12:29:57.247255 [Byte1]: 36
3325 12:29:57.250969
3326 12:29:57.251084 Set Vref, RX VrefLevel [Byte0]: 37
3327 12:29:57.254734 [Byte1]: 37
3328 12:29:57.258840
3329 12:29:57.258947 Set Vref, RX VrefLevel [Byte0]: 38
3330 12:29:57.262369 [Byte1]: 38
3331 12:29:57.267076
3332 12:29:57.267186 Set Vref, RX VrefLevel [Byte0]: 39
3333 12:29:57.270617 [Byte1]: 39
3334 12:29:57.274705
3335 12:29:57.274876 Set Vref, RX VrefLevel [Byte0]: 40
3336 12:29:57.278036 [Byte1]: 40
3337 12:29:57.282647
3338 12:29:57.282789 Set Vref, RX VrefLevel [Byte0]: 41
3339 12:29:57.286016 [Byte1]: 41
3340 12:29:57.291068
3341 12:29:57.291166 Set Vref, RX VrefLevel [Byte0]: 42
3342 12:29:57.293982 [Byte1]: 42
3343 12:29:57.298837
3344 12:29:57.298931 Set Vref, RX VrefLevel [Byte0]: 43
3345 12:29:57.302432 [Byte1]: 43
3346 12:29:57.306964
3347 12:29:57.307056 Set Vref, RX VrefLevel [Byte0]: 44
3348 12:29:57.309769 [Byte1]: 44
3349 12:29:57.314734
3350 12:29:57.314841 Set Vref, RX VrefLevel [Byte0]: 45
3351 12:29:57.317864 [Byte1]: 45
3352 12:29:57.322249
3353 12:29:57.322347 Set Vref, RX VrefLevel [Byte0]: 46
3354 12:29:57.325975 [Byte1]: 46
3355 12:29:57.330273
3356 12:29:57.330376 Set Vref, RX VrefLevel [Byte0]: 47
3357 12:29:57.333933 [Byte1]: 47
3358 12:29:57.338361
3359 12:29:57.338477 Set Vref, RX VrefLevel [Byte0]: 48
3360 12:29:57.341471 [Byte1]: 48
3361 12:29:57.346394
3362 12:29:57.346497 Set Vref, RX VrefLevel [Byte0]: 49
3363 12:29:57.349489 [Byte1]: 49
3364 12:29:57.353957
3365 12:29:57.354047 Set Vref, RX VrefLevel [Byte0]: 50
3366 12:29:57.357734 [Byte1]: 50
3367 12:29:57.361962
3368 12:29:57.362055 Set Vref, RX VrefLevel [Byte0]: 51
3369 12:29:57.365570 [Byte1]: 51
3370 12:29:57.370277
3371 12:29:57.370377 Set Vref, RX VrefLevel [Byte0]: 52
3372 12:29:57.373182 [Byte1]: 52
3373 12:29:57.377944
3374 12:29:57.378051 Set Vref, RX VrefLevel [Byte0]: 53
3375 12:29:57.381430 [Byte1]: 53
3376 12:29:57.385907
3377 12:29:57.386007 Set Vref, RX VrefLevel [Byte0]: 54
3378 12:29:57.389460 [Byte1]: 54
3379 12:29:57.393710
3380 12:29:57.393799 Set Vref, RX VrefLevel [Byte0]: 55
3381 12:29:57.397339 [Byte1]: 55
3382 12:29:57.401771
3383 12:29:57.401874 Set Vref, RX VrefLevel [Byte0]: 56
3384 12:29:57.405318 [Byte1]: 56
3385 12:29:57.409534
3386 12:29:57.409635 Set Vref, RX VrefLevel [Byte0]: 57
3387 12:29:57.412621 [Byte1]: 57
3388 12:29:57.417732
3389 12:29:57.417844 Set Vref, RX VrefLevel [Byte0]: 58
3390 12:29:57.420813 [Byte1]: 58
3391 12:29:57.425671
3392 12:29:57.425809 Set Vref, RX VrefLevel [Byte0]: 59
3393 12:29:57.429089 [Byte1]: 59
3394 12:29:57.433452
3395 12:29:57.433561 Set Vref, RX VrefLevel [Byte0]: 60
3396 12:29:57.436476 [Byte1]: 60
3397 12:29:57.441576
3398 12:29:57.441681 Set Vref, RX VrefLevel [Byte0]: 61
3399 12:29:57.444666 [Byte1]: 61
3400 12:29:57.449089
3401 12:29:57.449189 Set Vref, RX VrefLevel [Byte0]: 62
3402 12:29:57.452735 [Byte1]: 62
3403 12:29:57.457096
3404 12:29:57.457200 Set Vref, RX VrefLevel [Byte0]: 63
3405 12:29:57.460249 [Byte1]: 63
3406 12:29:57.465116
3407 12:29:57.465219 Set Vref, RX VrefLevel [Byte0]: 64
3408 12:29:57.468660 [Byte1]: 64
3409 12:29:57.472989
3410 12:29:57.473090 Set Vref, RX VrefLevel [Byte0]: 65
3411 12:29:57.476002 [Byte1]: 65
3412 12:29:57.480697
3413 12:29:57.480800 Set Vref, RX VrefLevel [Byte0]: 66
3414 12:29:57.484080 [Byte1]: 66
3415 12:29:57.489055
3416 12:29:57.489164 Set Vref, RX VrefLevel [Byte0]: 67
3417 12:29:57.491940 [Byte1]: 67
3418 12:29:57.496456
3419 12:29:57.496562 Final RX Vref Byte 0 = 57 to rank0
3420 12:29:57.499855 Final RX Vref Byte 1 = 48 to rank0
3421 12:29:57.503322 Final RX Vref Byte 0 = 57 to rank1
3422 12:29:57.506720 Final RX Vref Byte 1 = 48 to rank1==
3423 12:29:57.509937 Dram Type= 6, Freq= 0, CH_1, rank 0
3424 12:29:57.516661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 12:29:57.516788 ==
3426 12:29:57.516863 DQS Delay:
3427 12:29:57.516925 DQS0 = 0, DQS1 = 0
3428 12:29:57.519881 DQM Delay:
3429 12:29:57.519969 DQM0 = 113, DQM1 = 104
3430 12:29:57.523342 DQ Delay:
3431 12:29:57.526820 DQ0 =118, DQ1 =108, DQ2 =102, DQ3 =112
3432 12:29:57.529921 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =112
3433 12:29:57.532903 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =98
3434 12:29:57.536740 DQ12 =114, DQ13 =110, DQ14 =112, DQ15 =110
3435 12:29:57.536860
3436 12:29:57.536959
3437 12:29:57.546169 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3438 12:29:57.546292 CH1 RK0: MR19=303, MR18=F1F8
3439 12:29:57.552939 CH1_RK0: MR19=0x303, MR18=0xF1F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3440 12:29:57.553056
3441 12:29:57.556065 ----->DramcWriteLeveling(PI) begin...
3442 12:29:57.556160 ==
3443 12:29:57.559690 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 12:29:57.565877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 12:29:57.565993 ==
3446 12:29:57.569497 Write leveling (Byte 0): 24 => 24
3447 12:29:57.572439 Write leveling (Byte 1): 27 => 27
3448 12:29:57.572553 DramcWriteLeveling(PI) end<-----
3449 12:29:57.572624
3450 12:29:57.576119 ==
3451 12:29:57.579232 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 12:29:57.582399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 12:29:57.582494 ==
3454 12:29:57.586020 [Gating] SW mode calibration
3455 12:29:57.592471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3456 12:29:57.595865 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3457 12:29:57.602308 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 12:29:57.605660 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 12:29:57.608636 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 12:29:57.615228 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 12:29:57.618836 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 12:29:57.622011 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3463 12:29:57.628770 0 15 24 | B1->B0 | 3434 2727 | 1 1 | (1 0) (1 0)
3464 12:29:57.632217 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3465 12:29:57.635741 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 12:29:57.642169 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 12:29:57.645266 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 12:29:57.648341 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 12:29:57.655035 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 12:29:57.658791 1 0 20 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
3471 12:29:57.661970 1 0 24 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
3472 12:29:57.668696 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3473 12:29:57.671793 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 12:29:57.674862 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 12:29:57.681477 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 12:29:57.684719 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 12:29:57.688333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 12:29:57.695068 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 12:29:57.698161 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3480 12:29:57.701515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:29:57.707854 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:29:57.711243 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:29:57.714502 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:29:57.721003 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:29:57.724561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:29:57.727690 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:29:57.734657 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:29:57.738069 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:29:57.741007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:29:57.747350 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:29:57.751123 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:29:57.754529 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:29:57.760525 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:29:57.763670 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:29:57.767408 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3496 12:29:57.774253 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3497 12:29:57.774398 Total UI for P1: 0, mck2ui 16
3498 12:29:57.780346 best dqsien dly found for B0: ( 1, 3, 24)
3499 12:29:57.783783 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 12:29:57.787428 Total UI for P1: 0, mck2ui 16
3501 12:29:57.790425 best dqsien dly found for B1: ( 1, 3, 28)
3502 12:29:57.793511 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3503 12:29:57.797245 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3504 12:29:57.797382
3505 12:29:57.800287 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3506 12:29:57.803370 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3507 12:29:57.806966 [Gating] SW calibration Done
3508 12:29:57.807051 ==
3509 12:29:57.810469 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 12:29:57.816828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 12:29:57.816942 ==
3512 12:29:57.817013 RX Vref Scan: 0
3513 12:29:57.817075
3514 12:29:57.819685 RX Vref 0 -> 0, step: 1
3515 12:29:57.819774
3516 12:29:57.823135 RX Delay -40 -> 252, step: 8
3517 12:29:57.826509 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3518 12:29:57.829982 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3519 12:29:57.832977 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3520 12:29:57.836641 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3521 12:29:57.842934 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3522 12:29:57.846279 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3523 12:29:57.849649 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3524 12:29:57.852976 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3525 12:29:57.855994 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3526 12:29:57.862922 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3527 12:29:57.866074 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3528 12:29:57.869170 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3529 12:29:57.872704 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3530 12:29:57.878936 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3531 12:29:57.882674 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3532 12:29:57.885521 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3533 12:29:57.885608 ==
3534 12:29:57.888768 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 12:29:57.892263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 12:29:57.892353 ==
3537 12:29:57.895662 DQS Delay:
3538 12:29:57.895749 DQS0 = 0, DQS1 = 0
3539 12:29:57.899114 DQM Delay:
3540 12:29:57.899200 DQM0 = 111, DQM1 = 106
3541 12:29:57.902177 DQ Delay:
3542 12:29:57.905258 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =111
3543 12:29:57.908930 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3544 12:29:57.912046 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3545 12:29:57.915186 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3546 12:29:57.915269
3547 12:29:57.915336
3548 12:29:57.915399 ==
3549 12:29:57.918722 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 12:29:57.922115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 12:29:57.922191 ==
3552 12:29:57.922258
3553 12:29:57.922340
3554 12:29:57.925485 TX Vref Scan disable
3555 12:29:57.928492 == TX Byte 0 ==
3556 12:29:57.931907 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3557 12:29:57.935394 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3558 12:29:57.938322 == TX Byte 1 ==
3559 12:29:57.941750 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 12:29:57.945353 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 12:29:57.945471 ==
3562 12:29:57.948403 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 12:29:57.955116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 12:29:57.955211 ==
3565 12:29:57.965544 TX Vref=22, minBit 3, minWin=25, winSum=416
3566 12:29:57.968669 TX Vref=24, minBit 9, minWin=25, winSum=426
3567 12:29:57.971741 TX Vref=26, minBit 3, minWin=26, winSum=429
3568 12:29:57.975446 TX Vref=28, minBit 3, minWin=26, winSum=431
3569 12:29:57.978501 TX Vref=30, minBit 0, minWin=27, winSum=437
3570 12:29:57.985337 TX Vref=32, minBit 8, minWin=26, winSum=435
3571 12:29:57.988404 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 30
3572 12:29:57.988482
3573 12:29:57.991993 Final TX Range 1 Vref 30
3574 12:29:57.992079
3575 12:29:57.992144 ==
3576 12:29:57.994925 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 12:29:57.998620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 12:29:58.001721 ==
3579 12:29:58.001804
3580 12:29:58.001870
3581 12:29:58.001973 TX Vref Scan disable
3582 12:29:58.004769 == TX Byte 0 ==
3583 12:29:58.008549 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3584 12:29:58.014748 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3585 12:29:58.014892 == TX Byte 1 ==
3586 12:29:58.018463 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3587 12:29:58.025172 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3588 12:29:58.025256
3589 12:29:58.025323 [DATLAT]
3590 12:29:58.025385 Freq=1200, CH1 RK1
3591 12:29:58.025445
3592 12:29:58.028032 DATLAT Default: 0xd
3593 12:29:58.031379 0, 0xFFFF, sum = 0
3594 12:29:58.031494 1, 0xFFFF, sum = 0
3595 12:29:58.034757 2, 0xFFFF, sum = 0
3596 12:29:58.034898 3, 0xFFFF, sum = 0
3597 12:29:58.037747 4, 0xFFFF, sum = 0
3598 12:29:58.037832 5, 0xFFFF, sum = 0
3599 12:29:58.041054 6, 0xFFFF, sum = 0
3600 12:29:58.041140 7, 0xFFFF, sum = 0
3601 12:29:58.044437 8, 0xFFFF, sum = 0
3602 12:29:58.044523 9, 0xFFFF, sum = 0
3603 12:29:58.047847 10, 0xFFFF, sum = 0
3604 12:29:58.047933 11, 0xFFFF, sum = 0
3605 12:29:58.051378 12, 0x0, sum = 1
3606 12:29:58.051463 13, 0x0, sum = 2
3607 12:29:58.054254 14, 0x0, sum = 3
3608 12:29:58.054338 15, 0x0, sum = 4
3609 12:29:58.057836 best_step = 13
3610 12:29:58.057945
3611 12:29:58.058038 ==
3612 12:29:58.061096 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 12:29:58.064299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 12:29:58.064384 ==
3615 12:29:58.067677 RX Vref Scan: 0
3616 12:29:58.067788
3617 12:29:58.067883 RX Vref 0 -> 0, step: 1
3618 12:29:58.067974
3619 12:29:58.070573 RX Delay -21 -> 252, step: 4
3620 12:29:58.077402 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3621 12:29:58.081068 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3622 12:29:58.084248 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3623 12:29:58.087409 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3624 12:29:58.090448 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3625 12:29:58.097433 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3626 12:29:58.100480 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3627 12:29:58.104113 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3628 12:29:58.107329 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3629 12:29:58.110424 iDelay=195, Bit 9, Center 102 (35 ~ 170) 136
3630 12:29:58.117244 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3631 12:29:58.120276 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3632 12:29:58.123875 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3633 12:29:58.127001 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3634 12:29:58.134224 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3635 12:29:58.136750 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3636 12:29:58.136836 ==
3637 12:29:58.140210 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 12:29:58.143554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 12:29:58.143639 ==
3640 12:29:58.146971 DQS Delay:
3641 12:29:58.147086 DQS0 = 0, DQS1 = 0
3642 12:29:58.147160 DQM Delay:
3643 12:29:58.149857 DQM0 = 111, DQM1 = 109
3644 12:29:58.149941 DQ Delay:
3645 12:29:58.153321 DQ0 =112, DQ1 =108, DQ2 =102, DQ3 =108
3646 12:29:58.156858 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =110
3647 12:29:58.160141 DQ8 =98, DQ9 =102, DQ10 =110, DQ11 =102
3648 12:29:58.166865 DQ12 =116, DQ13 =114, DQ14 =114, DQ15 =116
3649 12:29:58.166964
3650 12:29:58.167029
3651 12:29:58.172913 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3652 12:29:58.176527 CH1 RK1: MR19=304, MR18=FA0A
3653 12:29:58.182868 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3654 12:29:58.186519 [RxdqsGatingPostProcess] freq 1200
3655 12:29:58.189627 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3656 12:29:58.192796 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 12:29:58.195839 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 12:29:58.199434 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 12:29:58.203080 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 12:29:58.206253 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 12:29:58.209353 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 12:29:58.212404 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 12:29:58.216236 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 12:29:58.219299 Pre-setting of DQS Precalculation
3665 12:29:58.226029 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3666 12:29:58.232256 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3667 12:29:58.239049 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3668 12:29:58.239178
3669 12:29:58.239251
3670 12:29:58.242070 [Calibration Summary] 2400 Mbps
3671 12:29:58.242161 CH 0, Rank 0
3672 12:29:58.245547 SW Impedance : PASS
3673 12:29:58.248978 DUTY Scan : NO K
3674 12:29:58.249126 ZQ Calibration : PASS
3675 12:29:58.252816 Jitter Meter : NO K
3676 12:29:58.255439 CBT Training : PASS
3677 12:29:58.255527 Write leveling : PASS
3678 12:29:58.258919 RX DQS gating : PASS
3679 12:29:58.259005 RX DQ/DQS(RDDQC) : PASS
3680 12:29:58.262523 TX DQ/DQS : PASS
3681 12:29:58.265440 RX DATLAT : PASS
3682 12:29:58.265530 RX DQ/DQS(Engine): PASS
3683 12:29:58.268859 TX OE : NO K
3684 12:29:58.268949 All Pass.
3685 12:29:58.269017
3686 12:29:58.272119 CH 0, Rank 1
3687 12:29:58.272209 SW Impedance : PASS
3688 12:29:58.275601 DUTY Scan : NO K
3689 12:29:58.278704 ZQ Calibration : PASS
3690 12:29:58.278803 Jitter Meter : NO K
3691 12:29:58.282259 CBT Training : PASS
3692 12:29:58.285147 Write leveling : PASS
3693 12:29:58.285236 RX DQS gating : PASS
3694 12:29:58.288813 RX DQ/DQS(RDDQC) : PASS
3695 12:29:58.291695 TX DQ/DQS : PASS
3696 12:29:58.291786 RX DATLAT : PASS
3697 12:29:58.295170 RX DQ/DQS(Engine): PASS
3698 12:29:58.298291 TX OE : NO K
3699 12:29:58.298387 All Pass.
3700 12:29:58.298455
3701 12:29:58.298516 CH 1, Rank 0
3702 12:29:58.301399 SW Impedance : PASS
3703 12:29:58.304915 DUTY Scan : NO K
3704 12:29:58.305029 ZQ Calibration : PASS
3705 12:29:58.308235 Jitter Meter : NO K
3706 12:29:58.311688 CBT Training : PASS
3707 12:29:58.311777 Write leveling : PASS
3708 12:29:58.314774 RX DQS gating : PASS
3709 12:29:58.317806 RX DQ/DQS(RDDQC) : PASS
3710 12:29:58.317896 TX DQ/DQS : PASS
3711 12:29:58.321545 RX DATLAT : PASS
3712 12:29:58.324736 RX DQ/DQS(Engine): PASS
3713 12:29:58.324836 TX OE : NO K
3714 12:29:58.327798 All Pass.
3715 12:29:58.327892
3716 12:29:58.327960 CH 1, Rank 1
3717 12:29:58.331265 SW Impedance : PASS
3718 12:29:58.331368 DUTY Scan : NO K
3719 12:29:58.334614 ZQ Calibration : PASS
3720 12:29:58.337761 Jitter Meter : NO K
3721 12:29:58.337873 CBT Training : PASS
3722 12:29:58.340894 Write leveling : PASS
3723 12:29:58.344551 RX DQS gating : PASS
3724 12:29:58.344656 RX DQ/DQS(RDDQC) : PASS
3725 12:29:58.347672 TX DQ/DQS : PASS
3726 12:29:58.350768 RX DATLAT : PASS
3727 12:29:58.350952 RX DQ/DQS(Engine): PASS
3728 12:29:58.353730 TX OE : NO K
3729 12:29:58.353842 All Pass.
3730 12:29:58.353936
3731 12:29:58.357260 DramC Write-DBI off
3732 12:29:58.360679 PER_BANK_REFRESH: Hybrid Mode
3733 12:29:58.360831 TX_TRACKING: ON
3734 12:29:58.370478 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3735 12:29:58.374113 [FAST_K] Save calibration result to emmc
3736 12:29:58.377280 dramc_set_vcore_voltage set vcore to 650000
3737 12:29:58.380078 Read voltage for 600, 5
3738 12:29:58.380202 Vio18 = 0
3739 12:29:58.380298 Vcore = 650000
3740 12:29:58.383799 Vdram = 0
3741 12:29:58.383911 Vddq = 0
3742 12:29:58.384007 Vmddr = 0
3743 12:29:58.390446 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3744 12:29:58.393499 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3745 12:29:58.397184 MEM_TYPE=3, freq_sel=19
3746 12:29:58.400012 sv_algorithm_assistance_LP4_1600
3747 12:29:58.403681 ============ PULL DRAM RESETB DOWN ============
3748 12:29:58.406767 ========== PULL DRAM RESETB DOWN end =========
3749 12:29:58.413276 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3750 12:29:58.416613 ===================================
3751 12:29:58.420084 LPDDR4 DRAM CONFIGURATION
3752 12:29:58.423287 ===================================
3753 12:29:58.423410 EX_ROW_EN[0] = 0x0
3754 12:29:58.426458 EX_ROW_EN[1] = 0x0
3755 12:29:58.426563 LP4Y_EN = 0x0
3756 12:29:58.429619 WORK_FSP = 0x0
3757 12:29:58.429717 WL = 0x2
3758 12:29:58.432737 RL = 0x2
3759 12:29:58.432838 BL = 0x2
3760 12:29:58.436337 RPST = 0x0
3761 12:29:58.436440 RD_PRE = 0x0
3762 12:29:58.439524 WR_PRE = 0x1
3763 12:29:58.439623 WR_PST = 0x0
3764 12:29:58.443130 DBI_WR = 0x0
3765 12:29:58.446268 DBI_RD = 0x0
3766 12:29:58.446365 OTF = 0x1
3767 12:29:58.449408 ===================================
3768 12:29:58.452613 ===================================
3769 12:29:58.452713 ANA top config
3770 12:29:58.456303 ===================================
3771 12:29:58.459285 DLL_ASYNC_EN = 0
3772 12:29:58.462733 ALL_SLAVE_EN = 1
3773 12:29:58.465853 NEW_RANK_MODE = 1
3774 12:29:58.469323 DLL_IDLE_MODE = 1
3775 12:29:58.469431 LP45_APHY_COMB_EN = 1
3776 12:29:58.472264 TX_ODT_DIS = 1
3777 12:29:58.475663 NEW_8X_MODE = 1
3778 12:29:58.479162 ===================================
3779 12:29:58.482111 ===================================
3780 12:29:58.485496 data_rate = 1200
3781 12:29:58.488947 CKR = 1
3782 12:29:58.492428 DQ_P2S_RATIO = 8
3783 12:29:58.495463 ===================================
3784 12:29:58.495572 CA_P2S_RATIO = 8
3785 12:29:58.498651 DQ_CA_OPEN = 0
3786 12:29:58.502533 DQ_SEMI_OPEN = 0
3787 12:29:58.505389 CA_SEMI_OPEN = 0
3788 12:29:58.508926 CA_FULL_RATE = 0
3789 12:29:58.511737 DQ_CKDIV4_EN = 1
3790 12:29:58.511822 CA_CKDIV4_EN = 1
3791 12:29:58.515338 CA_PREDIV_EN = 0
3792 12:29:58.518481 PH8_DLY = 0
3793 12:29:58.522182 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3794 12:29:58.525303 DQ_AAMCK_DIV = 4
3795 12:29:58.528442 CA_AAMCK_DIV = 4
3796 12:29:58.528526 CA_ADMCK_DIV = 4
3797 12:29:58.532106 DQ_TRACK_CA_EN = 0
3798 12:29:58.535176 CA_PICK = 600
3799 12:29:58.538284 CA_MCKIO = 600
3800 12:29:58.542063 MCKIO_SEMI = 0
3801 12:29:58.545189 PLL_FREQ = 2288
3802 12:29:58.548338 DQ_UI_PI_RATIO = 32
3803 12:29:58.548421 CA_UI_PI_RATIO = 0
3804 12:29:58.551485 ===================================
3805 12:29:58.554642 ===================================
3806 12:29:58.558330 memory_type:LPDDR4
3807 12:29:58.561382 GP_NUM : 10
3808 12:29:58.561467 SRAM_EN : 1
3809 12:29:58.564997 MD32_EN : 0
3810 12:29:58.567925 ===================================
3811 12:29:58.571464 [ANA_INIT] >>>>>>>>>>>>>>
3812 12:29:58.574518 <<<<<< [CONFIGURE PHASE]: ANA_TX
3813 12:29:58.578202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3814 12:29:58.581105 ===================================
3815 12:29:58.581193 data_rate = 1200,PCW = 0X5800
3816 12:29:58.584557 ===================================
3817 12:29:58.590954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3818 12:29:58.594466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 12:29:58.600958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 12:29:58.604477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3821 12:29:58.607573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3822 12:29:58.610635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3823 12:29:58.614349 [ANA_INIT] flow start
3824 12:29:58.617545 [ANA_INIT] PLL >>>>>>>>
3825 12:29:58.617629 [ANA_INIT] PLL <<<<<<<<
3826 12:29:58.620878 [ANA_INIT] MIDPI >>>>>>>>
3827 12:29:58.623996 [ANA_INIT] MIDPI <<<<<<<<
3828 12:29:58.627145 [ANA_INIT] DLL >>>>>>>>
3829 12:29:58.627229 [ANA_INIT] flow end
3830 12:29:58.630739 ============ LP4 DIFF to SE enter ============
3831 12:29:58.636999 ============ LP4 DIFF to SE exit ============
3832 12:29:58.637088 [ANA_INIT] <<<<<<<<<<<<<
3833 12:29:58.640261 [Flow] Enable top DCM control >>>>>
3834 12:29:58.643849 [Flow] Enable top DCM control <<<<<
3835 12:29:58.646964 Enable DLL master slave shuffle
3836 12:29:58.653811 ==============================================================
3837 12:29:58.653895 Gating Mode config
3838 12:29:58.659899 ==============================================================
3839 12:29:58.663621 Config description:
3840 12:29:58.673382 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3841 12:29:58.679830 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3842 12:29:58.683518 SELPH_MODE 0: By rank 1: By Phase
3843 12:29:58.689808 ==============================================================
3844 12:29:58.693336 GAT_TRACK_EN = 1
3845 12:29:58.696162 RX_GATING_MODE = 2
3846 12:29:58.699718 RX_GATING_TRACK_MODE = 2
3847 12:29:58.699808 SELPH_MODE = 1
3848 12:29:58.702633 PICG_EARLY_EN = 1
3849 12:29:58.706083 VALID_LAT_VALUE = 1
3850 12:29:58.712637 ==============================================================
3851 12:29:58.716197 Enter into Gating configuration >>>>
3852 12:29:58.719679 Exit from Gating configuration <<<<
3853 12:29:58.722952 Enter into DVFS_PRE_config >>>>>
3854 12:29:58.732589 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3855 12:29:58.735764 Exit from DVFS_PRE_config <<<<<
3856 12:29:58.738826 Enter into PICG configuration >>>>
3857 12:29:58.742557 Exit from PICG configuration <<<<
3858 12:29:58.745934 [RX_INPUT] configuration >>>>>
3859 12:29:58.749206 [RX_INPUT] configuration <<<<<
3860 12:29:58.752190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3861 12:29:58.759194 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3862 12:29:58.765414 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 12:29:58.772342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 12:29:58.778720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 12:29:58.785146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 12:29:58.788279 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3867 12:29:58.791771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3868 12:29:58.795161 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3869 12:29:58.801770 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3870 12:29:58.805148 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3871 12:29:58.808555 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 12:29:58.811593 ===================================
3873 12:29:58.814656 LPDDR4 DRAM CONFIGURATION
3874 12:29:58.818223 ===================================
3875 12:29:58.818328 EX_ROW_EN[0] = 0x0
3876 12:29:58.821318 EX_ROW_EN[1] = 0x0
3877 12:29:58.824467 LP4Y_EN = 0x0
3878 12:29:58.824572 WORK_FSP = 0x0
3879 12:29:58.828033 WL = 0x2
3880 12:29:58.828139 RL = 0x2
3881 12:29:58.831507 BL = 0x2
3882 12:29:58.831610 RPST = 0x0
3883 12:29:58.834740 RD_PRE = 0x0
3884 12:29:58.834889 WR_PRE = 0x1
3885 12:29:58.838113 WR_PST = 0x0
3886 12:29:58.838216 DBI_WR = 0x0
3887 12:29:58.840910 DBI_RD = 0x0
3888 12:29:58.841009 OTF = 0x1
3889 12:29:58.844678 ===================================
3890 12:29:58.847755 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3891 12:29:58.854432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3892 12:29:58.857492 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3893 12:29:58.861207 ===================================
3894 12:29:58.864220 LPDDR4 DRAM CONFIGURATION
3895 12:29:58.867369 ===================================
3896 12:29:58.867444 EX_ROW_EN[0] = 0x10
3897 12:29:58.871181 EX_ROW_EN[1] = 0x0
3898 12:29:58.874263 LP4Y_EN = 0x0
3899 12:29:58.874367 WORK_FSP = 0x0
3900 12:29:58.877386 WL = 0x2
3901 12:29:58.877483 RL = 0x2
3902 12:29:58.880634 BL = 0x2
3903 12:29:58.880728 RPST = 0x0
3904 12:29:58.884226 RD_PRE = 0x0
3905 12:29:58.884303 WR_PRE = 0x1
3906 12:29:58.887669 WR_PST = 0x0
3907 12:29:58.887742 DBI_WR = 0x0
3908 12:29:58.890637 DBI_RD = 0x0
3909 12:29:58.890742 OTF = 0x1
3910 12:29:58.893711 ===================================
3911 12:29:58.900268 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3912 12:29:58.904887 nWR fixed to 30
3913 12:29:58.908439 [ModeRegInit_LP4] CH0 RK0
3914 12:29:58.908543 [ModeRegInit_LP4] CH0 RK1
3915 12:29:58.911332 [ModeRegInit_LP4] CH1 RK0
3916 12:29:58.915590 [ModeRegInit_LP4] CH1 RK1
3917 12:29:58.915667 match AC timing 17
3918 12:29:58.921628 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3919 12:29:58.924595 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3920 12:29:58.928333 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3921 12:29:58.934996 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3922 12:29:58.937969 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3923 12:29:58.938089 ==
3924 12:29:58.941137 Dram Type= 6, Freq= 0, CH_0, rank 0
3925 12:29:58.944903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3926 12:29:58.945020 ==
3927 12:29:58.951305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3928 12:29:58.958004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3929 12:29:58.961115 [CA 0] Center 37 (7~67) winsize 61
3930 12:29:58.964748 [CA 1] Center 37 (7~67) winsize 61
3931 12:29:58.967810 [CA 2] Center 35 (5~65) winsize 61
3932 12:29:58.970979 [CA 3] Center 35 (5~65) winsize 61
3933 12:29:58.974103 [CA 4] Center 34 (4~65) winsize 62
3934 12:29:58.977758 [CA 5] Center 33 (3~64) winsize 62
3935 12:29:58.977865
3936 12:29:58.980810 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3937 12:29:58.980884
3938 12:29:58.984614 [CATrainingPosCal] consider 1 rank data
3939 12:29:58.987666 u2DelayCellTimex100 = 270/100 ps
3940 12:29:58.990731 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3941 12:29:58.994210 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3942 12:29:58.997440 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3943 12:29:59.004389 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3944 12:29:59.007495 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3945 12:29:59.010398 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3946 12:29:59.010478
3947 12:29:59.014035 CA PerBit enable=1, Macro0, CA PI delay=33
3948 12:29:59.014112
3949 12:29:59.017358 [CBTSetCACLKResult] CA Dly = 33
3950 12:29:59.017445 CS Dly: 4 (0~35)
3951 12:29:59.017507 ==
3952 12:29:59.020255 Dram Type= 6, Freq= 0, CH_0, rank 1
3953 12:29:59.027139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 12:29:59.027239 ==
3955 12:29:59.030491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 12:29:59.036886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 12:29:59.040481 [CA 0] Center 37 (7~67) winsize 61
3958 12:29:59.043866 [CA 1] Center 37 (7~67) winsize 61
3959 12:29:59.046978 [CA 2] Center 35 (5~65) winsize 61
3960 12:29:59.050174 [CA 3] Center 35 (5~65) winsize 61
3961 12:29:59.053339 [CA 4] Center 33 (3~64) winsize 62
3962 12:29:59.056977 [CA 5] Center 33 (3~64) winsize 62
3963 12:29:59.057065
3964 12:29:59.060025 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 12:29:59.060112
3966 12:29:59.063644 [CATrainingPosCal] consider 2 rank data
3967 12:29:59.066652 u2DelayCellTimex100 = 270/100 ps
3968 12:29:59.070515 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3969 12:29:59.076454 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3970 12:29:59.080175 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3971 12:29:59.083270 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3972 12:29:59.086322 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3973 12:29:59.090084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 12:29:59.090172
3975 12:29:59.093136 CA PerBit enable=1, Macro0, CA PI delay=33
3976 12:29:59.093222
3977 12:29:59.096302 [CBTSetCACLKResult] CA Dly = 33
3978 12:29:59.099910 CS Dly: 5 (0~37)
3979 12:29:59.099997
3980 12:29:59.103283 ----->DramcWriteLeveling(PI) begin...
3981 12:29:59.103370 ==
3982 12:29:59.106472 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 12:29:59.109794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 12:29:59.109884 ==
3985 12:29:59.112925 Write leveling (Byte 0): 34 => 34
3986 12:29:59.115907 Write leveling (Byte 1): 30 => 30
3987 12:29:59.119281 DramcWriteLeveling(PI) end<-----
3988 12:29:59.119370
3989 12:29:59.119438 ==
3990 12:29:59.122724 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 12:29:59.126250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 12:29:59.126338 ==
3993 12:29:59.129132 [Gating] SW mode calibration
3994 12:29:59.136366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3995 12:29:59.143106 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3996 12:29:59.145668 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 12:29:59.152328 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 12:29:59.156111 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 12:29:59.159183 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (0 0)
4000 12:29:59.165878 0 9 16 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 0)
4001 12:29:59.168880 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4002 12:29:59.172691 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 12:29:59.179147 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 12:29:59.182048 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 12:29:59.185204 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 12:29:59.192379 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 12:29:59.195140 0 10 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
4008 12:29:59.198916 0 10 16 | B1->B0 | 3434 3a3a | 1 0 | (0 0) (0 0)
4009 12:29:59.205081 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 12:29:59.208706 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 12:29:59.211702 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 12:29:59.218271 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 12:29:59.221866 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 12:29:59.225253 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 12:29:59.228630 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 12:29:59.234824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:29:59.238473 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:29:59.241393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:29:59.248159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:29:59.251386 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:29:59.254616 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:29:59.261831 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:29:59.264848 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:29:59.268000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:29:59.274946 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:29:59.277998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:29:59.281092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:29:59.287964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:29:59.291067 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:29:59.294770 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:29:59.301113 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:29:59.304712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4033 12:29:59.307751 Total UI for P1: 0, mck2ui 16
4034 12:29:59.310732 best dqsien dly found for B0: ( 0, 13, 14)
4035 12:29:59.314331 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 12:29:59.317449 Total UI for P1: 0, mck2ui 16
4037 12:29:59.321003 best dqsien dly found for B1: ( 0, 13, 18)
4038 12:29:59.324454 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4039 12:29:59.330722 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4040 12:29:59.330824
4041 12:29:59.334275 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4042 12:29:59.337678 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4043 12:29:59.340968 [Gating] SW calibration Done
4044 12:29:59.341053 ==
4045 12:29:59.344395 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 12:29:59.347280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 12:29:59.347366 ==
4048 12:29:59.350926 RX Vref Scan: 0
4049 12:29:59.351009
4050 12:29:59.351074 RX Vref 0 -> 0, step: 1
4051 12:29:59.351134
4052 12:29:59.353958 RX Delay -230 -> 252, step: 16
4053 12:29:59.357495 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4054 12:29:59.363874 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4055 12:29:59.367437 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4056 12:29:59.370507 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4057 12:29:59.373575 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4058 12:29:59.380456 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4059 12:29:59.383575 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4060 12:29:59.386676 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4061 12:29:59.390408 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4062 12:29:59.393527 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4063 12:29:59.400362 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4064 12:29:59.403569 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4065 12:29:59.406682 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4066 12:29:59.410453 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4067 12:29:59.417107 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4068 12:29:59.420150 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4069 12:29:59.420235 ==
4070 12:29:59.423153 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 12:29:59.426760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 12:29:59.426864 ==
4073 12:29:59.429747 DQS Delay:
4074 12:29:59.429831 DQS0 = 0, DQS1 = 0
4075 12:29:59.433316 DQM Delay:
4076 12:29:59.433402 DQM0 = 37, DQM1 = 28
4077 12:29:59.433469 DQ Delay:
4078 12:29:59.436273 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4079 12:29:59.439883 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4080 12:29:59.442916 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =17
4081 12:29:59.446387 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4082 12:29:59.446473
4083 12:29:59.446545
4084 12:29:59.449712 ==
4085 12:29:59.449792 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 12:29:59.456353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 12:29:59.456450 ==
4088 12:29:59.456519
4089 12:29:59.456581
4090 12:29:59.459348 TX Vref Scan disable
4091 12:29:59.459436 == TX Byte 0 ==
4092 12:29:59.465910 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4093 12:29:59.469333 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4094 12:29:59.469428 == TX Byte 1 ==
4095 12:29:59.476382 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4096 12:29:59.479181 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4097 12:29:59.479271 ==
4098 12:29:59.482301 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 12:29:59.485995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 12:29:59.486089 ==
4101 12:29:59.486157
4102 12:29:59.486219
4103 12:29:59.489036 TX Vref Scan disable
4104 12:29:59.492168 == TX Byte 0 ==
4105 12:29:59.495947 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4106 12:29:59.498805 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4107 12:29:59.502019 == TX Byte 1 ==
4108 12:29:59.505795 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4109 12:29:59.512002 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4110 12:29:59.512094
4111 12:29:59.512161 [DATLAT]
4112 12:29:59.512224 Freq=600, CH0 RK0
4113 12:29:59.512283
4114 12:29:59.515720 DATLAT Default: 0x9
4115 12:29:59.515804 0, 0xFFFF, sum = 0
4116 12:29:59.518728 1, 0xFFFF, sum = 0
4117 12:29:59.521789 2, 0xFFFF, sum = 0
4118 12:29:59.521874 3, 0xFFFF, sum = 0
4119 12:29:59.525578 4, 0xFFFF, sum = 0
4120 12:29:59.525665 5, 0xFFFF, sum = 0
4121 12:29:59.528680 6, 0xFFFF, sum = 0
4122 12:29:59.528766 7, 0xFFFF, sum = 0
4123 12:29:59.531695 8, 0x0, sum = 1
4124 12:29:59.531781 9, 0x0, sum = 2
4125 12:29:59.531850 10, 0x0, sum = 3
4126 12:29:59.535301 11, 0x0, sum = 4
4127 12:29:59.535394 best_step = 9
4128 12:29:59.535461
4129 12:29:59.535522 ==
4130 12:29:59.538396 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 12:29:59.545280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 12:29:59.545378 ==
4133 12:29:59.545446 RX Vref Scan: 1
4134 12:29:59.545507
4135 12:29:59.548523 RX Vref 0 -> 0, step: 1
4136 12:29:59.548610
4137 12:29:59.551492 RX Delay -195 -> 252, step: 8
4138 12:29:59.551576
4139 12:29:59.555125 Set Vref, RX VrefLevel [Byte0]: 63
4140 12:29:59.558439 [Byte1]: 58
4141 12:29:59.558524
4142 12:29:59.561336 Final RX Vref Byte 0 = 63 to rank0
4143 12:29:59.564876 Final RX Vref Byte 1 = 58 to rank0
4144 12:29:59.568457 Final RX Vref Byte 0 = 63 to rank1
4145 12:29:59.571480 Final RX Vref Byte 1 = 58 to rank1==
4146 12:29:59.574677 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 12:29:59.578271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 12:29:59.581404 ==
4149 12:29:59.581535 DQS Delay:
4150 12:29:59.581633 DQS0 = 0, DQS1 = 0
4151 12:29:59.584769 DQM Delay:
4152 12:29:59.584894 DQM0 = 34, DQM1 = 28
4153 12:29:59.587812 DQ Delay:
4154 12:29:59.587927 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4155 12:29:59.591498 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4156 12:29:59.594607 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4157 12:29:59.597624 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4158 12:29:59.601387
4159 12:29:59.601501
4160 12:29:59.607670 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4161 12:29:59.610717 CH0 RK0: MR19=808, MR18=3A3A
4162 12:29:59.617555 CH0_RK0: MR19=0x808, MR18=0x3A3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4163 12:29:59.617698
4164 12:29:59.620747 ----->DramcWriteLeveling(PI) begin...
4165 12:29:59.620872 ==
4166 12:29:59.624422 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 12:29:59.627335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 12:29:59.627451 ==
4169 12:29:59.630482 Write leveling (Byte 0): 31 => 31
4170 12:29:59.634003 Write leveling (Byte 1): 32 => 32
4171 12:29:59.637051 DramcWriteLeveling(PI) end<-----
4172 12:29:59.637181
4173 12:29:59.637271 ==
4174 12:29:59.640844 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 12:29:59.643991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 12:29:59.644116 ==
4177 12:29:59.647096 [Gating] SW mode calibration
4178 12:29:59.653667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4179 12:29:59.660474 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4180 12:29:59.663716 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 12:29:59.670253 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 12:29:59.673598 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 12:29:59.677112 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4184 12:29:59.683847 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4185 12:29:59.686692 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 12:29:59.689813 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 12:29:59.696706 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 12:29:59.699864 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 12:29:59.703534 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 12:29:59.709867 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 12:29:59.713033 0 10 12 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4192 12:29:59.716717 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4193 12:29:59.722838 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 12:29:59.726496 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 12:29:59.729429 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 12:29:59.736288 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 12:29:59.739420 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 12:29:59.743008 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 12:29:59.749146 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 12:29:59.752859 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:29:59.756045 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:29:59.762194 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:29:59.765799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:29:59.769260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:29:59.775507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:29:59.778972 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:29:59.782345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:29:59.788717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:29:59.792165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:29:59.795782 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:29:59.802114 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:29:59.805593 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:29:59.809108 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:29:59.815186 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:29:59.818317 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4216 12:29:59.821945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4217 12:29:59.825162 Total UI for P1: 0, mck2ui 16
4218 12:29:59.828219 best dqsien dly found for B0: ( 0, 13, 12)
4219 12:29:59.834871 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 12:29:59.835002 Total UI for P1: 0, mck2ui 16
4221 12:29:59.841727 best dqsien dly found for B1: ( 0, 13, 16)
4222 12:29:59.845347 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4223 12:29:59.848532 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4224 12:29:59.848632
4225 12:29:59.851572 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4226 12:29:59.855325 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4227 12:29:59.858366 [Gating] SW calibration Done
4228 12:29:59.858455 ==
4229 12:29:59.861493 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 12:29:59.864469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 12:29:59.864555 ==
4232 12:29:59.868187 RX Vref Scan: 0
4233 12:29:59.868290
4234 12:29:59.868354 RX Vref 0 -> 0, step: 1
4235 12:29:59.868414
4236 12:29:59.871239 RX Delay -230 -> 252, step: 16
4237 12:29:59.877737 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4238 12:29:59.881056 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4239 12:29:59.884446 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4240 12:29:59.887907 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4241 12:29:59.894058 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4242 12:29:59.897476 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4243 12:29:59.901055 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4244 12:29:59.904560 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4245 12:29:59.907609 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4246 12:29:59.913936 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4247 12:29:59.917873 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4248 12:29:59.921136 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4249 12:29:59.924025 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4250 12:29:59.930937 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4251 12:29:59.933937 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4252 12:29:59.936891 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4253 12:29:59.937054 ==
4254 12:29:59.940595 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 12:29:59.947226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 12:29:59.947370 ==
4257 12:29:59.947479 DQS Delay:
4258 12:29:59.947580 DQS0 = 0, DQS1 = 0
4259 12:29:59.950637 DQM Delay:
4260 12:29:59.950756 DQM0 = 39, DQM1 = 27
4261 12:29:59.953354 DQ Delay:
4262 12:29:59.957178 DQ0 =41, DQ1 =33, DQ2 =41, DQ3 =33
4263 12:29:59.960200 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4264 12:29:59.963250 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4265 12:29:59.966839 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4266 12:29:59.966951
4267 12:29:59.967025
4268 12:29:59.967090 ==
4269 12:29:59.969888 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 12:29:59.973144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 12:29:59.973239 ==
4272 12:29:59.973307
4273 12:29:59.973377
4274 12:29:59.976719 TX Vref Scan disable
4275 12:29:59.979834 == TX Byte 0 ==
4276 12:29:59.982926 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4277 12:29:59.986560 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4278 12:29:59.990051 == TX Byte 1 ==
4279 12:29:59.992988 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4280 12:29:59.996226 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4281 12:29:59.996316 ==
4282 12:29:59.999597 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 12:30:00.003147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 12:30:00.006073 ==
4285 12:30:00.006162
4286 12:30:00.006230
4287 12:30:00.006301 TX Vref Scan disable
4288 12:30:00.010193 == TX Byte 0 ==
4289 12:30:00.013215 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4290 12:30:00.020155 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4291 12:30:00.020311 == TX Byte 1 ==
4292 12:30:00.023079 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4293 12:30:00.030160 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4294 12:30:00.030312
4295 12:30:00.030427 [DATLAT]
4296 12:30:00.030521 Freq=600, CH0 RK1
4297 12:30:00.030610
4298 12:30:00.032943 DATLAT Default: 0x9
4299 12:30:00.036651 0, 0xFFFF, sum = 0
4300 12:30:00.036749 1, 0xFFFF, sum = 0
4301 12:30:00.039477 2, 0xFFFF, sum = 0
4302 12:30:00.039565 3, 0xFFFF, sum = 0
4303 12:30:00.043159 4, 0xFFFF, sum = 0
4304 12:30:00.043286 5, 0xFFFF, sum = 0
4305 12:30:00.046194 6, 0xFFFF, sum = 0
4306 12:30:00.046282 7, 0xFFFF, sum = 0
4307 12:30:00.049273 8, 0x0, sum = 1
4308 12:30:00.049355 9, 0x0, sum = 2
4309 12:30:00.052915 10, 0x0, sum = 3
4310 12:30:00.053005 11, 0x0, sum = 4
4311 12:30:00.053077 best_step = 9
4312 12:30:00.053140
4313 12:30:00.055955 ==
4314 12:30:00.059096 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 12:30:00.062533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 12:30:00.062621 ==
4317 12:30:00.062690 RX Vref Scan: 0
4318 12:30:00.062753
4319 12:30:00.066006 RX Vref 0 -> 0, step: 1
4320 12:30:00.066090
4321 12:30:00.069020 RX Delay -195 -> 252, step: 8
4322 12:30:00.075674 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4323 12:30:00.078789 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4324 12:30:00.082373 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4325 12:30:00.085440 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4326 12:30:00.089018 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4327 12:30:00.095692 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4328 12:30:00.098763 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4329 12:30:00.102270 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4330 12:30:00.105665 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4331 12:30:00.112280 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4332 12:30:00.115202 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4333 12:30:00.118769 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4334 12:30:00.122516 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4335 12:30:00.128486 iDelay=205, Bit 13, Center 32 (-131 ~ 196) 328
4336 12:30:00.131704 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4337 12:30:00.135478 iDelay=205, Bit 15, Center 32 (-131 ~ 196) 328
4338 12:30:00.135589 ==
4339 12:30:00.138582 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 12:30:00.141729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 12:30:00.145158 ==
4342 12:30:00.145237 DQS Delay:
4343 12:30:00.145312 DQS0 = 0, DQS1 = 0
4344 12:30:00.148266 DQM Delay:
4345 12:30:00.148340 DQM0 = 33, DQM1 = 26
4346 12:30:00.151461 DQ Delay:
4347 12:30:00.155090 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4348 12:30:00.155182 DQ4 =28, DQ5 =20, DQ6 =44, DQ7 =44
4349 12:30:00.158451 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4350 12:30:00.161569 DQ12 =32, DQ13 =32, DQ14 =36, DQ15 =32
4351 12:30:00.164731
4352 12:30:00.164806
4353 12:30:00.171544 [DQSOSCAuto] RK1, (LSB)MR18= 0x6636, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4354 12:30:00.175164 CH0 RK1: MR19=808, MR18=6636
4355 12:30:00.181359 CH0_RK1: MR19=0x808, MR18=0x6636, DQSOSC=390, MR23=63, INC=172, DEC=114
4356 12:30:00.185027 [RxdqsGatingPostProcess] freq 600
4357 12:30:00.188141 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4358 12:30:00.191189 Pre-setting of DQS Precalculation
4359 12:30:00.198349 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4360 12:30:00.198478 ==
4361 12:30:00.201397 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 12:30:00.204518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 12:30:00.204630 ==
4364 12:30:00.210983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 12:30:00.214458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4366 12:30:00.218775 [CA 0] Center 36 (6~66) winsize 61
4367 12:30:00.222315 [CA 1] Center 35 (5~66) winsize 62
4368 12:30:00.225853 [CA 2] Center 34 (4~65) winsize 62
4369 12:30:00.229148 [CA 3] Center 34 (4~65) winsize 62
4370 12:30:00.232399 [CA 4] Center 34 (4~65) winsize 62
4371 12:30:00.235400 [CA 5] Center 33 (3~64) winsize 62
4372 12:30:00.235520
4373 12:30:00.238869 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4374 12:30:00.238981
4375 12:30:00.241919 [CATrainingPosCal] consider 1 rank data
4376 12:30:00.245911 u2DelayCellTimex100 = 270/100 ps
4377 12:30:00.248543 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4378 12:30:00.255382 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 12:30:00.258369 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 12:30:00.261921 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 12:30:00.265008 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 12:30:00.268714 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 12:30:00.268837
4384 12:30:00.271849 CA PerBit enable=1, Macro0, CA PI delay=33
4385 12:30:00.271933
4386 12:30:00.274992 [CBTSetCACLKResult] CA Dly = 33
4387 12:30:00.278169 CS Dly: 4 (0~35)
4388 12:30:00.278252 ==
4389 12:30:00.281835 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 12:30:00.284993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 12:30:00.285115 ==
4392 12:30:00.291658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 12:30:00.294821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4394 12:30:00.298857 [CA 0] Center 36 (6~66) winsize 61
4395 12:30:00.302515 [CA 1] Center 36 (6~67) winsize 62
4396 12:30:00.305611 [CA 2] Center 34 (4~65) winsize 62
4397 12:30:00.308635 [CA 3] Center 34 (4~65) winsize 62
4398 12:30:00.312235 [CA 4] Center 34 (4~65) winsize 62
4399 12:30:00.315258 [CA 5] Center 34 (3~65) winsize 63
4400 12:30:00.315351
4401 12:30:00.318813 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4402 12:30:00.318911
4403 12:30:00.322353 [CATrainingPosCal] consider 2 rank data
4404 12:30:00.325413 u2DelayCellTimex100 = 270/100 ps
4405 12:30:00.329164 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4406 12:30:00.335605 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 12:30:00.338812 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 12:30:00.341801 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 12:30:00.345254 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 12:30:00.348341 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 12:30:00.348435
4412 12:30:00.351808 CA PerBit enable=1, Macro0, CA PI delay=33
4413 12:30:00.351896
4414 12:30:00.354857 [CBTSetCACLKResult] CA Dly = 33
4415 12:30:00.358651 CS Dly: 5 (0~37)
4416 12:30:00.358747
4417 12:30:00.361694 ----->DramcWriteLeveling(PI) begin...
4418 12:30:00.361780 ==
4419 12:30:00.364695 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 12:30:00.368290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 12:30:00.368383 ==
4422 12:30:00.371531 Write leveling (Byte 0): 29 => 29
4423 12:30:00.374803 Write leveling (Byte 1): 33 => 33
4424 12:30:00.378234 DramcWriteLeveling(PI) end<-----
4425 12:30:00.378327
4426 12:30:00.378395 ==
4427 12:30:00.381301 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 12:30:00.384984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 12:30:00.385085 ==
4430 12:30:00.388099 [Gating] SW mode calibration
4431 12:30:00.394694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4432 12:30:00.400955 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4433 12:30:00.404521 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 12:30:00.407522 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 12:30:00.414272 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 12:30:00.417878 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (0 0)
4437 12:30:00.420866 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4438 12:30:00.427413 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 12:30:00.431213 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 12:30:00.434058 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 12:30:00.440591 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 12:30:00.443633 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 12:30:00.450561 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 12:30:00.454095 0 10 12 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (0 0)
4445 12:30:00.456997 0 10 16 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
4446 12:30:00.463700 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 12:30:00.466692 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 12:30:00.470399 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:30:00.476624 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:30:00.480300 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 12:30:00.483323 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 12:30:00.490049 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 12:30:00.493146 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:30:00.496740 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:30:00.503437 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:30:00.506431 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:30:00.509961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:30:00.516215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:30:00.519889 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:30:00.522807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:30:00.529838 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:30:00.533016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:30:00.535970 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:30:00.542928 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:30:00.546043 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:30:00.549179 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:30:00.555588 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:30:00.559018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4469 12:30:00.562635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 12:30:00.566075 Total UI for P1: 0, mck2ui 16
4471 12:30:00.569028 best dqsien dly found for B0: ( 0, 13, 12)
4472 12:30:00.572627 Total UI for P1: 0, mck2ui 16
4473 12:30:00.575630 best dqsien dly found for B1: ( 0, 13, 12)
4474 12:30:00.579298 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4475 12:30:00.582130 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4476 12:30:00.582224
4477 12:30:00.585886 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4478 12:30:00.592767 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4479 12:30:00.592905 [Gating] SW calibration Done
4480 12:30:00.595725 ==
4481 12:30:00.595810 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 12:30:00.602498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 12:30:00.602625 ==
4484 12:30:00.602731 RX Vref Scan: 0
4485 12:30:00.602837
4486 12:30:00.605680 RX Vref 0 -> 0, step: 1
4487 12:30:00.605796
4488 12:30:00.608961 RX Delay -230 -> 252, step: 16
4489 12:30:00.612019 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4490 12:30:00.615515 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4491 12:30:00.621796 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4492 12:30:00.625199 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4493 12:30:00.628878 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4494 12:30:00.631914 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4495 12:30:00.634940 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4496 12:30:00.641866 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4497 12:30:00.645018 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4498 12:30:00.648570 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4499 12:30:00.652047 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4500 12:30:00.658345 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4501 12:30:00.661836 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4502 12:30:00.664869 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4503 12:30:00.668376 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4504 12:30:00.674898 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4505 12:30:00.674997 ==
4506 12:30:00.678184 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 12:30:00.681242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 12:30:00.681324 ==
4509 12:30:00.681390 DQS Delay:
4510 12:30:00.685042 DQS0 = 0, DQS1 = 0
4511 12:30:00.685163 DQM Delay:
4512 12:30:00.688214 DQM0 = 38, DQM1 = 28
4513 12:30:00.688300 DQ Delay:
4514 12:30:00.691247 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4515 12:30:00.694897 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4516 12:30:00.697975 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4517 12:30:00.701110 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4518 12:30:00.701192
4519 12:30:00.701257
4520 12:30:00.701318 ==
4521 12:30:00.704760 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 12:30:00.707724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 12:30:00.711471 ==
4524 12:30:00.711562
4525 12:30:00.711629
4526 12:30:00.711690 TX Vref Scan disable
4527 12:30:00.714520 == TX Byte 0 ==
4528 12:30:00.717428 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 12:30:00.724194 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 12:30:00.724291 == TX Byte 1 ==
4531 12:30:00.727334 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4532 12:30:00.734523 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4533 12:30:00.734629 ==
4534 12:30:00.737595 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 12:30:00.740708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 12:30:00.740803 ==
4537 12:30:00.740891
4538 12:30:00.740972
4539 12:30:00.744402 TX Vref Scan disable
4540 12:30:00.747424 == TX Byte 0 ==
4541 12:30:00.750975 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 12:30:00.753921 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 12:30:00.757333 == TX Byte 1 ==
4544 12:30:00.760339 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4545 12:30:00.764058 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4546 12:30:00.764181
4547 12:30:00.767097 [DATLAT]
4548 12:30:00.767219 Freq=600, CH1 RK0
4549 12:30:00.767309
4550 12:30:00.770562 DATLAT Default: 0x9
4551 12:30:00.770652 0, 0xFFFF, sum = 0
4552 12:30:00.773773 1, 0xFFFF, sum = 0
4553 12:30:00.773891 2, 0xFFFF, sum = 0
4554 12:30:00.777113 3, 0xFFFF, sum = 0
4555 12:30:00.777202 4, 0xFFFF, sum = 0
4556 12:30:00.780523 5, 0xFFFF, sum = 0
4557 12:30:00.780612 6, 0xFFFF, sum = 0
4558 12:30:00.783468 7, 0xFFFF, sum = 0
4559 12:30:00.783557 8, 0x0, sum = 1
4560 12:30:00.786786 9, 0x0, sum = 2
4561 12:30:00.786898 10, 0x0, sum = 3
4562 12:30:00.790276 11, 0x0, sum = 4
4563 12:30:00.790364 best_step = 9
4564 12:30:00.790449
4565 12:30:00.790549 ==
4566 12:30:00.793405 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 12:30:00.797024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 12:30:00.800021 ==
4569 12:30:00.800117 RX Vref Scan: 1
4570 12:30:00.800197
4571 12:30:00.803116 RX Vref 0 -> 0, step: 1
4572 12:30:00.803237
4573 12:30:00.806766 RX Delay -195 -> 252, step: 8
4574 12:30:00.806862
4575 12:30:00.809881 Set Vref, RX VrefLevel [Byte0]: 57
4576 12:30:00.813349 [Byte1]: 48
4577 12:30:00.813460
4578 12:30:00.816553 Final RX Vref Byte 0 = 57 to rank0
4579 12:30:00.819501 Final RX Vref Byte 1 = 48 to rank0
4580 12:30:00.823063 Final RX Vref Byte 0 = 57 to rank1
4581 12:30:00.826672 Final RX Vref Byte 1 = 48 to rank1==
4582 12:30:00.829811 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 12:30:00.832754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 12:30:00.832860 ==
4585 12:30:00.836372 DQS Delay:
4586 12:30:00.836467 DQS0 = 0, DQS1 = 0
4587 12:30:00.836545 DQM Delay:
4588 12:30:00.839363 DQM0 = 39, DQM1 = 29
4589 12:30:00.839450 DQ Delay:
4590 12:30:00.843061 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4591 12:30:00.846159 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4592 12:30:00.849319 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4593 12:30:00.852370 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4594 12:30:00.852465
4595 12:30:00.852553
4596 12:30:00.862268 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d2a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4597 12:30:00.865718 CH1 RK0: MR19=808, MR18=1D2A
4598 12:30:00.869123 CH1_RK0: MR19=0x808, MR18=0x1D2A, DQSOSC=401, MR23=63, INC=163, DEC=108
4599 12:30:00.872617
4600 12:30:00.875899 ----->DramcWriteLeveling(PI) begin...
4601 12:30:00.875992 ==
4602 12:30:00.879096 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 12:30:00.882338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 12:30:00.882454 ==
4605 12:30:00.885438 Write leveling (Byte 0): 29 => 29
4606 12:30:00.889075 Write leveling (Byte 1): 29 => 29
4607 12:30:00.892149 DramcWriteLeveling(PI) end<-----
4608 12:30:00.892235
4609 12:30:00.892302 ==
4610 12:30:00.895722 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 12:30:00.898514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 12:30:00.898629 ==
4613 12:30:00.901939 [Gating] SW mode calibration
4614 12:30:00.908641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4615 12:30:00.915340 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4616 12:30:00.918319 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 12:30:00.922066 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 12:30:00.928711 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4619 12:30:00.931781 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (0 0)
4620 12:30:00.934960 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4621 12:30:00.941559 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 12:30:00.944683 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 12:30:00.948288 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 12:30:00.954516 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 12:30:00.958208 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 12:30:00.961231 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4627 12:30:00.967937 0 10 12 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
4628 12:30:00.970929 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 12:30:00.974445 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 12:30:00.981330 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 12:30:00.984675 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:30:00.987782 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 12:30:00.994189 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 12:30:00.997235 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 12:30:01.000736 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4636 12:30:01.007343 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4637 12:30:01.010817 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:30:01.013877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:30:01.020568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:30:01.023708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:30:01.027419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:30:01.034010 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:30:01.037064 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:30:01.040034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:30:01.046648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:30:01.050431 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:30:01.053590 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:30:01.060300 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:30:01.063463 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:30:01.066422 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:30:01.073263 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4652 12:30:01.076290 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 12:30:01.079945 Total UI for P1: 0, mck2ui 16
4654 12:30:01.082877 best dqsien dly found for B0: ( 0, 13, 12)
4655 12:30:01.086450 Total UI for P1: 0, mck2ui 16
4656 12:30:01.089800 best dqsien dly found for B1: ( 0, 13, 12)
4657 12:30:01.092706 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4658 12:30:01.096303 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4659 12:30:01.096410
4660 12:30:01.099677 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4661 12:30:01.106156 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4662 12:30:01.106279 [Gating] SW calibration Done
4663 12:30:01.106396 ==
4664 12:30:01.109196 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 12:30:01.115855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 12:30:01.115961 ==
4667 12:30:01.116077 RX Vref Scan: 0
4668 12:30:01.116189
4669 12:30:01.119434 RX Vref 0 -> 0, step: 1
4670 12:30:01.119509
4671 12:30:01.122508 RX Delay -230 -> 252, step: 16
4672 12:30:01.125962 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4673 12:30:01.129025 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4674 12:30:01.135774 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4675 12:30:01.138699 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4676 12:30:01.142516 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4677 12:30:01.145418 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4678 12:30:01.149128 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4679 12:30:01.155288 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4680 12:30:01.158475 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4681 12:30:01.162189 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4682 12:30:01.165316 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4683 12:30:01.172261 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4684 12:30:01.175340 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4685 12:30:01.178424 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4686 12:30:01.181729 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4687 12:30:01.188456 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4688 12:30:01.188609 ==
4689 12:30:01.191509 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 12:30:01.195077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 12:30:01.195173 ==
4692 12:30:01.195244 DQS Delay:
4693 12:30:01.198446 DQS0 = 0, DQS1 = 0
4694 12:30:01.198570 DQM Delay:
4695 12:30:01.201402 DQM0 = 35, DQM1 = 29
4696 12:30:01.201532 DQ Delay:
4697 12:30:01.204922 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4698 12:30:01.208332 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4699 12:30:01.211095 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4700 12:30:01.214528 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4701 12:30:01.214650
4702 12:30:01.214758
4703 12:30:01.214857 ==
4704 12:30:01.218055 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 12:30:01.224870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 12:30:01.224984 ==
4707 12:30:01.225055
4708 12:30:01.225118
4709 12:30:01.225177 TX Vref Scan disable
4710 12:30:01.227823 == TX Byte 0 ==
4711 12:30:01.231251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 12:30:01.237625 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 12:30:01.237747 == TX Byte 1 ==
4714 12:30:01.241118 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4715 12:30:01.247526 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4716 12:30:01.247637 ==
4717 12:30:01.250906 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 12:30:01.254162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 12:30:01.254252 ==
4720 12:30:01.254320
4721 12:30:01.254384
4722 12:30:01.257865 TX Vref Scan disable
4723 12:30:01.260981 == TX Byte 0 ==
4724 12:30:01.264053 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4725 12:30:01.267280 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4726 12:30:01.270950 == TX Byte 1 ==
4727 12:30:01.274024 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4728 12:30:01.277199 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4729 12:30:01.277290
4730 12:30:01.277358 [DATLAT]
4731 12:30:01.280977 Freq=600, CH1 RK1
4732 12:30:01.281066
4733 12:30:01.284026 DATLAT Default: 0x9
4734 12:30:01.284114 0, 0xFFFF, sum = 0
4735 12:30:01.287068 1, 0xFFFF, sum = 0
4736 12:30:01.287157 2, 0xFFFF, sum = 0
4737 12:30:01.290270 3, 0xFFFF, sum = 0
4738 12:30:01.290358 4, 0xFFFF, sum = 0
4739 12:30:01.293991 5, 0xFFFF, sum = 0
4740 12:30:01.294084 6, 0xFFFF, sum = 0
4741 12:30:01.297128 7, 0xFFFF, sum = 0
4742 12:30:01.297216 8, 0x0, sum = 1
4743 12:30:01.300804 9, 0x0, sum = 2
4744 12:30:01.300894 10, 0x0, sum = 3
4745 12:30:01.303459 11, 0x0, sum = 4
4746 12:30:01.303575 best_step = 9
4747 12:30:01.303672
4748 12:30:01.303763 ==
4749 12:30:01.306943 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 12:30:01.310315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 12:30:01.310403 ==
4752 12:30:01.313718 RX Vref Scan: 0
4753 12:30:01.313801
4754 12:30:01.317054 RX Vref 0 -> 0, step: 1
4755 12:30:01.317142
4756 12:30:01.317210 RX Delay -195 -> 252, step: 8
4757 12:30:01.325090 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4758 12:30:01.328163 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4759 12:30:01.331761 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4760 12:30:01.334910 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4761 12:30:01.341313 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4762 12:30:01.344788 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4763 12:30:01.348400 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4764 12:30:01.351435 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4765 12:30:01.358075 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4766 12:30:01.361185 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4767 12:30:01.365224 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4768 12:30:01.368019 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4769 12:30:01.374275 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4770 12:30:01.378248 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4771 12:30:01.381109 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4772 12:30:01.384212 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4773 12:30:01.384298 ==
4774 12:30:01.387319 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 12:30:01.393954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 12:30:01.394097 ==
4777 12:30:01.394200 DQS Delay:
4778 12:30:01.397735 DQS0 = 0, DQS1 = 0
4779 12:30:01.397823 DQM Delay:
4780 12:30:01.400818 DQM0 = 35, DQM1 = 30
4781 12:30:01.400902 DQ Delay:
4782 12:30:01.403776 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4783 12:30:01.407389 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =36
4784 12:30:01.410517 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4785 12:30:01.413962 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4786 12:30:01.414047
4787 12:30:01.414124
4788 12:30:01.420328 [DQSOSCAuto] RK1, (LSB)MR18= 0x3456, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4789 12:30:01.423866 CH1 RK1: MR19=808, MR18=3456
4790 12:30:01.430103 CH1_RK1: MR19=0x808, MR18=0x3456, DQSOSC=393, MR23=63, INC=169, DEC=113
4791 12:30:01.433543 [RxdqsGatingPostProcess] freq 600
4792 12:30:01.439996 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4793 12:30:01.440105 Pre-setting of DQS Precalculation
4794 12:30:01.446940 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4795 12:30:01.453284 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4796 12:30:01.459765 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4797 12:30:01.459874
4798 12:30:01.459942
4799 12:30:01.463471 [Calibration Summary] 1200 Mbps
4800 12:30:01.466540 CH 0, Rank 0
4801 12:30:01.466626 SW Impedance : PASS
4802 12:30:01.469770 DUTY Scan : NO K
4803 12:30:01.473282 ZQ Calibration : PASS
4804 12:30:01.473371 Jitter Meter : NO K
4805 12:30:01.476354 CBT Training : PASS
4806 12:30:01.479556 Write leveling : PASS
4807 12:30:01.479642 RX DQS gating : PASS
4808 12:30:01.483238 RX DQ/DQS(RDDQC) : PASS
4809 12:30:01.486363 TX DQ/DQS : PASS
4810 12:30:01.486495 RX DATLAT : PASS
4811 12:30:01.489491 RX DQ/DQS(Engine): PASS
4812 12:30:01.489594 TX OE : NO K
4813 12:30:01.493160 All Pass.
4814 12:30:01.493263
4815 12:30:01.493360 CH 0, Rank 1
4816 12:30:01.496231 SW Impedance : PASS
4817 12:30:01.499325 DUTY Scan : NO K
4818 12:30:01.499426 ZQ Calibration : PASS
4819 12:30:01.503012 Jitter Meter : NO K
4820 12:30:01.503100 CBT Training : PASS
4821 12:30:01.506165 Write leveling : PASS
4822 12:30:01.509741 RX DQS gating : PASS
4823 12:30:01.509830 RX DQ/DQS(RDDQC) : PASS
4824 12:30:01.512833 TX DQ/DQS : PASS
4825 12:30:01.515943 RX DATLAT : PASS
4826 12:30:01.516035 RX DQ/DQS(Engine): PASS
4827 12:30:01.520008 TX OE : NO K
4828 12:30:01.520112 All Pass.
4829 12:30:01.520179
4830 12:30:01.522560 CH 1, Rank 0
4831 12:30:01.522645 SW Impedance : PASS
4832 12:30:01.526033 DUTY Scan : NO K
4833 12:30:01.529069 ZQ Calibration : PASS
4834 12:30:01.529159 Jitter Meter : NO K
4835 12:30:01.532283 CBT Training : PASS
4836 12:30:01.536293 Write leveling : PASS
4837 12:30:01.536385 RX DQS gating : PASS
4838 12:30:01.539290 RX DQ/DQS(RDDQC) : PASS
4839 12:30:01.542280 TX DQ/DQS : PASS
4840 12:30:01.542365 RX DATLAT : PASS
4841 12:30:01.545818 RX DQ/DQS(Engine): PASS
4842 12:30:01.548770 TX OE : NO K
4843 12:30:01.548884 All Pass.
4844 12:30:01.548952
4845 12:30:01.549012 CH 1, Rank 1
4846 12:30:01.552306 SW Impedance : PASS
4847 12:30:01.555533 DUTY Scan : NO K
4848 12:30:01.555659 ZQ Calibration : PASS
4849 12:30:01.558833 Jitter Meter : NO K
4850 12:30:01.562427 CBT Training : PASS
4851 12:30:01.562515 Write leveling : PASS
4852 12:30:01.565501 RX DQS gating : PASS
4853 12:30:01.565616 RX DQ/DQS(RDDQC) : PASS
4854 12:30:01.568671 TX DQ/DQS : PASS
4855 12:30:01.572351 RX DATLAT : PASS
4856 12:30:01.572428 RX DQ/DQS(Engine): PASS
4857 12:30:01.575363 TX OE : NO K
4858 12:30:01.575440 All Pass.
4859 12:30:01.575508
4860 12:30:01.578498 DramC Write-DBI off
4861 12:30:01.582181 PER_BANK_REFRESH: Hybrid Mode
4862 12:30:01.582276 TX_TRACKING: ON
4863 12:30:01.592225 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4864 12:30:01.595152 [FAST_K] Save calibration result to emmc
4865 12:30:01.598751 dramc_set_vcore_voltage set vcore to 662500
4866 12:30:01.601833 Read voltage for 933, 3
4867 12:30:01.601915 Vio18 = 0
4868 12:30:01.604983 Vcore = 662500
4869 12:30:01.605060 Vdram = 0
4870 12:30:01.605120 Vddq = 0
4871 12:30:01.605178 Vmddr = 0
4872 12:30:01.611731 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4873 12:30:01.618401 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4874 12:30:01.618508 MEM_TYPE=3, freq_sel=17
4875 12:30:01.621614 sv_algorithm_assistance_LP4_1600
4876 12:30:01.625043 ============ PULL DRAM RESETB DOWN ============
4877 12:30:01.631265 ========== PULL DRAM RESETB DOWN end =========
4878 12:30:01.634859 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4879 12:30:01.638247 ===================================
4880 12:30:01.641473 LPDDR4 DRAM CONFIGURATION
4881 12:30:01.644533 ===================================
4882 12:30:01.644621 EX_ROW_EN[0] = 0x0
4883 12:30:01.648089 EX_ROW_EN[1] = 0x0
4884 12:30:01.648197 LP4Y_EN = 0x0
4885 12:30:01.651275 WORK_FSP = 0x0
4886 12:30:01.651378 WL = 0x3
4887 12:30:01.654477 RL = 0x3
4888 12:30:01.658057 BL = 0x2
4889 12:30:01.658172 RPST = 0x0
4890 12:30:01.660894 RD_PRE = 0x0
4891 12:30:01.660987 WR_PRE = 0x1
4892 12:30:01.664350 WR_PST = 0x0
4893 12:30:01.664459 DBI_WR = 0x0
4894 12:30:01.667721 DBI_RD = 0x0
4895 12:30:01.667827 OTF = 0x1
4896 12:30:01.671136 ===================================
4897 12:30:01.674158 ===================================
4898 12:30:01.677825 ANA top config
4899 12:30:01.680936 ===================================
4900 12:30:01.681038 DLL_ASYNC_EN = 0
4901 12:30:01.684025 ALL_SLAVE_EN = 1
4902 12:30:01.687801 NEW_RANK_MODE = 1
4903 12:30:01.690848 DLL_IDLE_MODE = 1
4904 12:30:01.693968 LP45_APHY_COMB_EN = 1
4905 12:30:01.694062 TX_ODT_DIS = 1
4906 12:30:01.697634 NEW_8X_MODE = 1
4907 12:30:01.700735 ===================================
4908 12:30:01.703698 ===================================
4909 12:30:01.707487 data_rate = 1866
4910 12:30:01.710644 CKR = 1
4911 12:30:01.713706 DQ_P2S_RATIO = 8
4912 12:30:01.717362 ===================================
4913 12:30:01.717482 CA_P2S_RATIO = 8
4914 12:30:01.720272 DQ_CA_OPEN = 0
4915 12:30:01.723987 DQ_SEMI_OPEN = 0
4916 12:30:01.727061 CA_SEMI_OPEN = 0
4917 12:30:01.730608 CA_FULL_RATE = 0
4918 12:30:01.733535 DQ_CKDIV4_EN = 1
4919 12:30:01.736637 CA_CKDIV4_EN = 1
4920 12:30:01.736721 CA_PREDIV_EN = 0
4921 12:30:01.740373 PH8_DLY = 0
4922 12:30:01.743288 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4923 12:30:01.746782 DQ_AAMCK_DIV = 4
4924 12:30:01.750372 CA_AAMCK_DIV = 4
4925 12:30:01.753418 CA_ADMCK_DIV = 4
4926 12:30:01.753505 DQ_TRACK_CA_EN = 0
4927 12:30:01.756424 CA_PICK = 933
4928 12:30:01.760344 CA_MCKIO = 933
4929 12:30:01.762944 MCKIO_SEMI = 0
4930 12:30:01.766429 PLL_FREQ = 3732
4931 12:30:01.769745 DQ_UI_PI_RATIO = 32
4932 12:30:01.773387 CA_UI_PI_RATIO = 0
4933 12:30:01.776601 ===================================
4934 12:30:01.779960 ===================================
4935 12:30:01.780048 memory_type:LPDDR4
4936 12:30:01.783103 GP_NUM : 10
4937 12:30:01.786199 SRAM_EN : 1
4938 12:30:01.786282 MD32_EN : 0
4939 12:30:01.789325 ===================================
4940 12:30:01.793177 [ANA_INIT] >>>>>>>>>>>>>>
4941 12:30:01.796003 <<<<<< [CONFIGURE PHASE]: ANA_TX
4942 12:30:01.799714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4943 12:30:01.802946 ===================================
4944 12:30:01.805953 data_rate = 1866,PCW = 0X8f00
4945 12:30:01.809028 ===================================
4946 12:30:01.812723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4947 12:30:01.815858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 12:30:01.822375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 12:30:01.825922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4950 12:30:01.831992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4951 12:30:01.835507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4952 12:30:01.835614 [ANA_INIT] flow start
4953 12:30:01.838561 [ANA_INIT] PLL >>>>>>>>
4954 12:30:01.842180 [ANA_INIT] PLL <<<<<<<<
4955 12:30:01.842268 [ANA_INIT] MIDPI >>>>>>>>
4956 12:30:01.845164 [ANA_INIT] MIDPI <<<<<<<<
4957 12:30:01.848819 [ANA_INIT] DLL >>>>>>>>
4958 12:30:01.848908 [ANA_INIT] flow end
4959 12:30:01.855080 ============ LP4 DIFF to SE enter ============
4960 12:30:01.858542 ============ LP4 DIFF to SE exit ============
4961 12:30:01.861612 [ANA_INIT] <<<<<<<<<<<<<
4962 12:30:01.865226 [Flow] Enable top DCM control >>>>>
4963 12:30:01.868504 [Flow] Enable top DCM control <<<<<
4964 12:30:01.868589 Enable DLL master slave shuffle
4965 12:30:01.874757 ==============================================================
4966 12:30:01.878311 Gating Mode config
4967 12:30:01.881923 ==============================================================
4968 12:30:01.884567 Config description:
4969 12:30:01.894807 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4970 12:30:01.901597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4971 12:30:01.904779 SELPH_MODE 0: By rank 1: By Phase
4972 12:30:01.911402 ==============================================================
4973 12:30:01.914464 GAT_TRACK_EN = 1
4974 12:30:01.918252 RX_GATING_MODE = 2
4975 12:30:01.921366 RX_GATING_TRACK_MODE = 2
4976 12:30:01.924347 SELPH_MODE = 1
4977 12:30:01.927838 PICG_EARLY_EN = 1
4978 12:30:01.927926 VALID_LAT_VALUE = 1
4979 12:30:01.934521 ==============================================================
4980 12:30:01.937470 Enter into Gating configuration >>>>
4981 12:30:01.941040 Exit from Gating configuration <<<<
4982 12:30:01.944149 Enter into DVFS_PRE_config >>>>>
4983 12:30:01.953954 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4984 12:30:01.957792 Exit from DVFS_PRE_config <<<<<
4985 12:30:01.960682 Enter into PICG configuration >>>>
4986 12:30:01.964149 Exit from PICG configuration <<<<
4987 12:30:01.967584 [RX_INPUT] configuration >>>>>
4988 12:30:01.970701 [RX_INPUT] configuration <<<<<
4989 12:30:01.977361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4990 12:30:01.980708 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4991 12:30:01.987302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 12:30:01.993968 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 12:30:02.000697 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 12:30:02.007260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 12:30:02.010433 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4996 12:30:02.013519 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4997 12:30:02.017110 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4998 12:30:02.023454 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4999 12:30:02.026510 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5000 12:30:02.030140 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 12:30:02.033199 ===================================
5002 12:30:02.036965 LPDDR4 DRAM CONFIGURATION
5003 12:30:02.039971 ===================================
5004 12:30:02.040064 EX_ROW_EN[0] = 0x0
5005 12:30:02.043529 EX_ROW_EN[1] = 0x0
5006 12:30:02.046543 LP4Y_EN = 0x0
5007 12:30:02.046648 WORK_FSP = 0x0
5008 12:30:02.049647 WL = 0x3
5009 12:30:02.049719 RL = 0x3
5010 12:30:02.053347 BL = 0x2
5011 12:30:02.053443 RPST = 0x0
5012 12:30:02.056800 RD_PRE = 0x0
5013 12:30:02.056877 WR_PRE = 0x1
5014 12:30:02.059915 WR_PST = 0x0
5015 12:30:02.060018 DBI_WR = 0x0
5016 12:30:02.063023 DBI_RD = 0x0
5017 12:30:02.063122 OTF = 0x1
5018 12:30:02.066679 ===================================
5019 12:30:02.069712 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5020 12:30:02.076629 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5021 12:30:02.079580 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 12:30:02.082644 ===================================
5023 12:30:02.086284 LPDDR4 DRAM CONFIGURATION
5024 12:30:02.089580 ===================================
5025 12:30:02.092747 EX_ROW_EN[0] = 0x10
5026 12:30:02.092826 EX_ROW_EN[1] = 0x0
5027 12:30:02.096427 LP4Y_EN = 0x0
5028 12:30:02.096511 WORK_FSP = 0x0
5029 12:30:02.099187 WL = 0x3
5030 12:30:02.099268 RL = 0x3
5031 12:30:02.102553 BL = 0x2
5032 12:30:02.102662 RPST = 0x0
5033 12:30:02.106157 RD_PRE = 0x0
5034 12:30:02.106260 WR_PRE = 0x1
5035 12:30:02.109460 WR_PST = 0x0
5036 12:30:02.109533 DBI_WR = 0x0
5037 12:30:02.112619 DBI_RD = 0x0
5038 12:30:02.112701 OTF = 0x1
5039 12:30:02.115667 ===================================
5040 12:30:02.122343 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5041 12:30:02.127102 nWR fixed to 30
5042 12:30:02.130470 [ModeRegInit_LP4] CH0 RK0
5043 12:30:02.130599 [ModeRegInit_LP4] CH0 RK1
5044 12:30:02.133530 [ModeRegInit_LP4] CH1 RK0
5045 12:30:02.137112 [ModeRegInit_LP4] CH1 RK1
5046 12:30:02.137195 match AC timing 9
5047 12:30:02.143399 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5048 12:30:02.146974 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5049 12:30:02.150002 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5050 12:30:02.156809 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5051 12:30:02.159783 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5052 12:30:02.159941 ==
5053 12:30:02.163418 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 12:30:02.166454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 12:30:02.166539 ==
5056 12:30:02.173267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 12:30:02.179942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5058 12:30:02.182860 [CA 0] Center 38 (7~69) winsize 63
5059 12:30:02.186442 [CA 1] Center 38 (8~69) winsize 62
5060 12:30:02.189501 [CA 2] Center 35 (5~66) winsize 62
5061 12:30:02.193109 [CA 3] Center 35 (5~65) winsize 61
5062 12:30:02.196146 [CA 4] Center 34 (4~65) winsize 62
5063 12:30:02.200015 [CA 5] Center 33 (3~64) winsize 62
5064 12:30:02.200106
5065 12:30:02.202723 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5066 12:30:02.202853
5067 12:30:02.205994 [CATrainingPosCal] consider 1 rank data
5068 12:30:02.209374 u2DelayCellTimex100 = 270/100 ps
5069 12:30:02.212818 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5070 12:30:02.216307 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5071 12:30:02.219031 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5072 12:30:02.225802 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5073 12:30:02.228853 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5074 12:30:02.232675 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5075 12:30:02.232763
5076 12:30:02.235787 CA PerBit enable=1, Macro0, CA PI delay=33
5077 12:30:02.235929
5078 12:30:02.238952 [CBTSetCACLKResult] CA Dly = 33
5079 12:30:02.239073 CS Dly: 6 (0~37)
5080 12:30:02.242291 ==
5081 12:30:02.242417 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 12:30:02.248525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 12:30:02.248640 ==
5084 12:30:02.252010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 12:30:02.258934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 12:30:02.262515 [CA 0] Center 38 (8~69) winsize 62
5087 12:30:02.265429 [CA 1] Center 38 (8~68) winsize 61
5088 12:30:02.269214 [CA 2] Center 35 (5~66) winsize 62
5089 12:30:02.272371 [CA 3] Center 35 (5~66) winsize 62
5090 12:30:02.275457 [CA 4] Center 34 (3~65) winsize 63
5091 12:30:02.278423 [CA 5] Center 33 (3~64) winsize 62
5092 12:30:02.278509
5093 12:30:02.282149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 12:30:02.282249
5095 12:30:02.285374 [CATrainingPosCal] consider 2 rank data
5096 12:30:02.288223 u2DelayCellTimex100 = 270/100 ps
5097 12:30:02.294807 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5098 12:30:02.298434 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5099 12:30:02.301553 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5100 12:30:02.304700 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5101 12:30:02.308172 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 12:30:02.312013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 12:30:02.312186
5104 12:30:02.314652 CA PerBit enable=1, Macro0, CA PI delay=33
5105 12:30:02.314777
5106 12:30:02.318067 [CBTSetCACLKResult] CA Dly = 33
5107 12:30:02.321378 CS Dly: 6 (0~38)
5108 12:30:02.321502
5109 12:30:02.324837 ----->DramcWriteLeveling(PI) begin...
5110 12:30:02.324920 ==
5111 12:30:02.327808 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 12:30:02.331399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 12:30:02.331492 ==
5114 12:30:02.334504 Write leveling (Byte 0): 32 => 32
5115 12:30:02.338376 Write leveling (Byte 1): 30 => 30
5116 12:30:02.341331 DramcWriteLeveling(PI) end<-----
5117 12:30:02.341432
5118 12:30:02.341510 ==
5119 12:30:02.344787 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 12:30:02.347827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 12:30:02.347938 ==
5122 12:30:02.350890 [Gating] SW mode calibration
5123 12:30:02.357530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5124 12:30:02.364397 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5125 12:30:02.367404 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5126 12:30:02.374099 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5127 12:30:02.377099 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 12:30:02.380805 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 12:30:02.386965 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 12:30:02.390654 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 12:30:02.393726 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 12:30:02.400319 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 12:30:02.403862 0 15 0 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 1)
5134 12:30:02.407016 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5135 12:30:02.413660 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 12:30:02.416776 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 12:30:02.420470 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 12:30:02.426528 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 12:30:02.429954 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 12:30:02.433300 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5141 12:30:02.439775 1 0 0 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (0 0)
5142 12:30:02.443560 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 12:30:02.446737 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 12:30:02.453201 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 12:30:02.456252 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 12:30:02.459816 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 12:30:02.465939 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 12:30:02.469768 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 12:30:02.472825 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5150 12:30:02.479480 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5151 12:30:02.482563 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:30:02.486277 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:30:02.492480 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:30:02.496256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:30:02.499237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:30:02.505701 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:30:02.509351 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:30:02.512365 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:30:02.518931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:30:02.521923 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:30:02.525625 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:30:02.532091 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:30:02.535504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:30:02.538469 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5165 12:30:02.545383 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5166 12:30:02.548514 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5167 12:30:02.552064 Total UI for P1: 0, mck2ui 16
5168 12:30:02.554937 best dqsien dly found for B0: ( 1, 2, 30)
5169 12:30:02.558168 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5170 12:30:02.564723 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 12:30:02.564807 Total UI for P1: 0, mck2ui 16
5172 12:30:02.571508 best dqsien dly found for B1: ( 1, 3, 6)
5173 12:30:02.574685 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5174 12:30:02.578274 best DQS1 dly(MCK, UI, PI) = (1, 3, 6)
5175 12:30:02.578359
5176 12:30:02.581419 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5177 12:30:02.584571 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 6)
5178 12:30:02.588247 [Gating] SW calibration Done
5179 12:30:02.588332 ==
5180 12:30:02.591388 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 12:30:02.594992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 12:30:02.595077 ==
5183 12:30:02.598072 RX Vref Scan: 0
5184 12:30:02.598157
5185 12:30:02.598225 RX Vref 0 -> 0, step: 1
5186 12:30:02.598287
5187 12:30:02.601145 RX Delay -80 -> 252, step: 8
5188 12:30:02.604295 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5189 12:30:02.611337 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5190 12:30:02.614220 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5191 12:30:02.617589 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5192 12:30:02.621206 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5193 12:30:02.624333 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5194 12:30:02.630586 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5195 12:30:02.634246 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5196 12:30:02.638110 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5197 12:30:02.640684 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5198 12:30:02.644308 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5199 12:30:02.650736 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5200 12:30:02.654282 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5201 12:30:02.657147 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5202 12:30:02.660551 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5203 12:30:02.663708 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5204 12:30:02.663793 ==
5205 12:30:02.667315 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 12:30:02.673991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 12:30:02.674077 ==
5208 12:30:02.674144 DQS Delay:
5209 12:30:02.677049 DQS0 = 0, DQS1 = 0
5210 12:30:02.677132 DQM Delay:
5211 12:30:02.680194 DQM0 = 94, DQM1 = 83
5212 12:30:02.680278 DQ Delay:
5213 12:30:02.683872 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5214 12:30:02.686847 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5215 12:30:02.690521 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5216 12:30:02.693579 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5217 12:30:02.693658
5218 12:30:02.693722
5219 12:30:02.693783 ==
5220 12:30:02.696692 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 12:30:02.700314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 12:30:02.700413 ==
5223 12:30:02.700523
5224 12:30:02.700582
5225 12:30:02.703522 TX Vref Scan disable
5226 12:30:02.707137 == TX Byte 0 ==
5227 12:30:02.710239 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5228 12:30:02.713237 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5229 12:30:02.716892 == TX Byte 1 ==
5230 12:30:02.719776 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5231 12:30:02.723330 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5232 12:30:02.723417 ==
5233 12:30:02.726747 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 12:30:02.733308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 12:30:02.733394 ==
5236 12:30:02.733526
5237 12:30:02.733647
5238 12:30:02.733774 TX Vref Scan disable
5239 12:30:02.736971 == TX Byte 0 ==
5240 12:30:02.740552 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5241 12:30:02.746727 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5242 12:30:02.746819 == TX Byte 1 ==
5243 12:30:02.750788 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5244 12:30:02.756797 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5245 12:30:02.756897
5246 12:30:02.756963 [DATLAT]
5247 12:30:02.757024 Freq=933, CH0 RK0
5248 12:30:02.757083
5249 12:30:02.760385 DATLAT Default: 0xd
5250 12:30:02.763252 0, 0xFFFF, sum = 0
5251 12:30:02.763336 1, 0xFFFF, sum = 0
5252 12:30:02.766686 2, 0xFFFF, sum = 0
5253 12:30:02.766812 3, 0xFFFF, sum = 0
5254 12:30:02.770107 4, 0xFFFF, sum = 0
5255 12:30:02.770192 5, 0xFFFF, sum = 0
5256 12:30:02.773025 6, 0xFFFF, sum = 0
5257 12:30:02.773110 7, 0xFFFF, sum = 0
5258 12:30:02.776734 8, 0xFFFF, sum = 0
5259 12:30:02.776819 9, 0xFFFF, sum = 0
5260 12:30:02.779788 10, 0x0, sum = 1
5261 12:30:02.779887 11, 0x0, sum = 2
5262 12:30:02.783063 12, 0x0, sum = 3
5263 12:30:02.783149 13, 0x0, sum = 4
5264 12:30:02.786329 best_step = 11
5265 12:30:02.786426
5266 12:30:02.786506 ==
5267 12:30:02.789326 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 12:30:02.792956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 12:30:02.793042 ==
5270 12:30:02.793126 RX Vref Scan: 1
5271 12:30:02.796094
5272 12:30:02.796169 RX Vref 0 -> 0, step: 1
5273 12:30:02.796248
5274 12:30:02.799260 RX Delay -69 -> 252, step: 4
5275 12:30:02.799344
5276 12:30:02.802898 Set Vref, RX VrefLevel [Byte0]: 63
5277 12:30:02.805959 [Byte1]: 58
5278 12:30:02.809742
5279 12:30:02.809846 Final RX Vref Byte 0 = 63 to rank0
5280 12:30:02.813094 Final RX Vref Byte 1 = 58 to rank0
5281 12:30:02.815985 Final RX Vref Byte 0 = 63 to rank1
5282 12:30:02.819751 Final RX Vref Byte 1 = 58 to rank1==
5283 12:30:02.822718 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 12:30:02.829314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:30:02.829408 ==
5286 12:30:02.829477 DQS Delay:
5287 12:30:02.832636 DQS0 = 0, DQS1 = 0
5288 12:30:02.832747 DQM Delay:
5289 12:30:02.832816 DQM0 = 96, DQM1 = 85
5290 12:30:02.836065 DQ Delay:
5291 12:30:02.839167 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5292 12:30:02.842682 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =108
5293 12:30:02.845633 DQ8 =80, DQ9 =72, DQ10 =84, DQ11 =80
5294 12:30:02.849204 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5295 12:30:02.849314
5296 12:30:02.849417
5297 12:30:02.856295 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5298 12:30:02.859123 CH0 RK0: MR19=505, MR18=1212
5299 12:30:02.865586 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5300 12:30:02.865699
5301 12:30:02.869220 ----->DramcWriteLeveling(PI) begin...
5302 12:30:02.869324 ==
5303 12:30:02.872215 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 12:30:02.875374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 12:30:02.875451 ==
5306 12:30:02.878752 Write leveling (Byte 0): 29 => 29
5307 12:30:02.882378 Write leveling (Byte 1): 27 => 27
5308 12:30:02.885357 DramcWriteLeveling(PI) end<-----
5309 12:30:02.885441
5310 12:30:02.885506 ==
5311 12:30:02.888955 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 12:30:02.895119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 12:30:02.895207 ==
5314 12:30:02.895289 [Gating] SW mode calibration
5315 12:30:02.905033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 12:30:02.908079 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 12:30:02.911777 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5318 12:30:02.918061 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 12:30:02.921826 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 12:30:02.924877 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 12:30:02.931723 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 12:30:02.934664 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 12:30:02.941559 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 12:30:02.944459 0 14 28 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (1 1)
5325 12:30:02.947845 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5326 12:30:02.951385 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 12:30:02.957604 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 12:30:02.961353 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 12:30:02.964360 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 12:30:02.970777 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 12:30:02.974498 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 12:30:02.980733 0 15 28 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (0 0)
5333 12:30:02.983973 1 0 0 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5334 12:30:02.987477 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 12:30:02.993675 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 12:30:02.997267 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 12:30:03.000345 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 12:30:03.007166 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 12:30:03.010164 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 12:30:03.013851 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5341 12:30:03.020121 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:30:03.023805 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:30:03.026916 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:30:03.033260 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:30:03.036861 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:30:03.040054 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 12:30:03.046588 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 12:30:03.049569 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:30:03.052931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:30:03.059966 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 12:30:03.063055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:30:03.066157 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:30:03.072834 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:30:03.076018 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:30:03.079708 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:30:03.086078 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 12:30:03.086193 Total UI for P1: 0, mck2ui 16
5358 12:30:03.092929 best dqsien dly found for B0: ( 1, 2, 26)
5359 12:30:03.095937 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 12:30:03.099357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 12:30:03.102678 Total UI for P1: 0, mck2ui 16
5362 12:30:03.106144 best dqsien dly found for B1: ( 1, 2, 30)
5363 12:30:03.109147 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5364 12:30:03.112439 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5365 12:30:03.112523
5366 12:30:03.118646 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5367 12:30:03.122254 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5368 12:30:03.122340 [Gating] SW calibration Done
5369 12:30:03.125313 ==
5370 12:30:03.129043 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 12:30:03.132090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 12:30:03.132173 ==
5373 12:30:03.132238 RX Vref Scan: 0
5374 12:30:03.132298
5375 12:30:03.135270 RX Vref 0 -> 0, step: 1
5376 12:30:03.135352
5377 12:30:03.138848 RX Delay -80 -> 252, step: 8
5378 12:30:03.141982 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5379 12:30:03.145161 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5380 12:30:03.148692 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5381 12:30:03.155277 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5382 12:30:03.158755 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5383 12:30:03.161561 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5384 12:30:03.165064 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5385 12:30:03.168283 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5386 12:30:03.174783 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5387 12:30:03.178409 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5388 12:30:03.181558 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5389 12:30:03.184713 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5390 12:30:03.191816 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5391 12:30:03.194979 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5392 12:30:03.197964 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5393 12:30:03.201600 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5394 12:30:03.201688 ==
5395 12:30:03.205034 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 12:30:03.207773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 12:30:03.211172 ==
5398 12:30:03.211276 DQS Delay:
5399 12:30:03.211367 DQS0 = 0, DQS1 = 0
5400 12:30:03.214665 DQM Delay:
5401 12:30:03.214748 DQM0 = 92, DQM1 = 82
5402 12:30:03.217658 DQ Delay:
5403 12:30:03.217742 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5404 12:30:03.221420 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =107
5405 12:30:03.224461 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5406 12:30:03.227615 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5407 12:30:03.231549
5408 12:30:03.231633
5409 12:30:03.231703 ==
5410 12:30:03.234633 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 12:30:03.237553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 12:30:03.237638 ==
5413 12:30:03.237704
5414 12:30:03.237765
5415 12:30:03.241310 TX Vref Scan disable
5416 12:30:03.241400 == TX Byte 0 ==
5417 12:30:03.247401 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5418 12:30:03.250620 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5419 12:30:03.250726 == TX Byte 1 ==
5420 12:30:03.257683 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5421 12:30:03.260682 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5422 12:30:03.260764 ==
5423 12:30:03.263666 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 12:30:03.267221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 12:30:03.267308 ==
5426 12:30:03.267393
5427 12:30:03.270484
5428 12:30:03.270569 TX Vref Scan disable
5429 12:30:03.273487 == TX Byte 0 ==
5430 12:30:03.277132 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5431 12:30:03.283881 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5432 12:30:03.283975 == TX Byte 1 ==
5433 12:30:03.286956 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5434 12:30:03.293812 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5435 12:30:03.293901
5436 12:30:03.293987 [DATLAT]
5437 12:30:03.294066 Freq=933, CH0 RK1
5438 12:30:03.294145
5439 12:30:03.296877 DATLAT Default: 0xb
5440 12:30:03.300011 0, 0xFFFF, sum = 0
5441 12:30:03.300098 1, 0xFFFF, sum = 0
5442 12:30:03.303496 2, 0xFFFF, sum = 0
5443 12:30:03.303595 3, 0xFFFF, sum = 0
5444 12:30:03.306745 4, 0xFFFF, sum = 0
5445 12:30:03.306888 5, 0xFFFF, sum = 0
5446 12:30:03.309725 6, 0xFFFF, sum = 0
5447 12:30:03.309828 7, 0xFFFF, sum = 0
5448 12:30:03.313263 8, 0xFFFF, sum = 0
5449 12:30:03.313349 9, 0xFFFF, sum = 0
5450 12:30:03.316763 10, 0x0, sum = 1
5451 12:30:03.316848 11, 0x0, sum = 2
5452 12:30:03.319714 12, 0x0, sum = 3
5453 12:30:03.319798 13, 0x0, sum = 4
5454 12:30:03.319865 best_step = 11
5455 12:30:03.323352
5456 12:30:03.323433 ==
5457 12:30:03.326422 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 12:30:03.329482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 12:30:03.329565 ==
5460 12:30:03.329629 RX Vref Scan: 0
5461 12:30:03.329689
5462 12:30:03.333287 RX Vref 0 -> 0, step: 1
5463 12:30:03.333368
5464 12:30:03.336459 RX Delay -77 -> 252, step: 4
5465 12:30:03.342668 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5466 12:30:03.346375 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5467 12:30:03.349495 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5468 12:30:03.352581 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5469 12:30:03.356226 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5470 12:30:03.359387 iDelay=199, Bit 5, Center 80 (-9 ~ 170) 180
5471 12:30:03.366175 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5472 12:30:03.369253 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5473 12:30:03.372798 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5474 12:30:03.375790 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5475 12:30:03.382754 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5476 12:30:03.385854 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5477 12:30:03.388995 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5478 12:30:03.392736 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5479 12:30:03.395864 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5480 12:30:03.402283 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5481 12:30:03.402364 ==
5482 12:30:03.405868 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 12:30:03.409185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 12:30:03.409264 ==
5485 12:30:03.409329 DQS Delay:
5486 12:30:03.411907 DQS0 = 0, DQS1 = 0
5487 12:30:03.411979 DQM Delay:
5488 12:30:03.415392 DQM0 = 92, DQM1 = 84
5489 12:30:03.415469 DQ Delay:
5490 12:30:03.418867 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5491 12:30:03.421883 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5492 12:30:03.425267 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5493 12:30:03.428538 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =92
5494 12:30:03.428623
5495 12:30:03.428688
5496 12:30:03.435068 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5497 12:30:03.438184 CH0 RK1: MR19=505, MR18=2F11
5498 12:30:03.444993 CH0_RK1: MR19=0x505, MR18=0x2F11, DQSOSC=407, MR23=63, INC=65, DEC=43
5499 12:30:03.448209 [RxdqsGatingPostProcess] freq 933
5500 12:30:03.455136 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 12:30:03.458169 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 12:30:03.461788 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 12:30:03.464932 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 12:30:03.468076 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 12:30:03.468162 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 12:30:03.471708 best DQS1 dly(2T, 0.5T) = (0, 10)
5507 12:30:03.475191 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 12:30:03.478230 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5509 12:30:03.481616 Pre-setting of DQS Precalculation
5510 12:30:03.487943 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 12:30:03.488031 ==
5512 12:30:03.491638 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 12:30:03.494761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 12:30:03.494873 ==
5515 12:30:03.500947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 12:30:03.507832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5517 12:30:03.510963 [CA 0] Center 37 (7~67) winsize 61
5518 12:30:03.514633 [CA 1] Center 37 (7~68) winsize 62
5519 12:30:03.517692 [CA 2] Center 34 (5~64) winsize 60
5520 12:30:03.521107 [CA 3] Center 34 (4~64) winsize 61
5521 12:30:03.524341 [CA 4] Center 34 (5~64) winsize 60
5522 12:30:03.527719 [CA 5] Center 34 (4~64) winsize 61
5523 12:30:03.527837
5524 12:30:03.531254 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5525 12:30:03.531339
5526 12:30:03.534240 [CATrainingPosCal] consider 1 rank data
5527 12:30:03.537684 u2DelayCellTimex100 = 270/100 ps
5528 12:30:03.540677 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5529 12:30:03.544428 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5530 12:30:03.547510 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5531 12:30:03.551184 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 12:30:03.554318 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5533 12:30:03.557406 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5534 12:30:03.557508
5535 12:30:03.564294 CA PerBit enable=1, Macro0, CA PI delay=34
5536 12:30:03.564403
5537 12:30:03.564466 [CBTSetCACLKResult] CA Dly = 34
5538 12:30:03.567359 CS Dly: 6 (0~37)
5539 12:30:03.567431 ==
5540 12:30:03.570553 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 12:30:03.573672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 12:30:03.573771 ==
5543 12:30:03.580286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 12:30:03.586940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5545 12:30:03.590380 [CA 0] Center 37 (7~68) winsize 62
5546 12:30:03.593704 [CA 1] Center 37 (7~68) winsize 62
5547 12:30:03.597016 [CA 2] Center 35 (5~65) winsize 61
5548 12:30:03.599878 [CA 3] Center 34 (4~64) winsize 61
5549 12:30:03.603595 [CA 4] Center 34 (4~65) winsize 62
5550 12:30:03.606772 [CA 5] Center 34 (4~64) winsize 61
5551 12:30:03.606894
5552 12:30:03.609827 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5553 12:30:03.609952
5554 12:30:03.613489 [CATrainingPosCal] consider 2 rank data
5555 12:30:03.616492 u2DelayCellTimex100 = 270/100 ps
5556 12:30:03.619576 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5557 12:30:03.623272 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5558 12:30:03.626534 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5559 12:30:03.633193 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5560 12:30:03.636254 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5561 12:30:03.639321 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5562 12:30:03.639397
5563 12:30:03.642680 CA PerBit enable=1, Macro0, CA PI delay=34
5564 12:30:03.642767
5565 12:30:03.646062 [CBTSetCACLKResult] CA Dly = 34
5566 12:30:03.646149 CS Dly: 7 (0~39)
5567 12:30:03.646217
5568 12:30:03.649780 ----->DramcWriteLeveling(PI) begin...
5569 12:30:03.649875 ==
5570 12:30:03.652832 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 12:30:03.659522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 12:30:03.659608 ==
5573 12:30:03.662495 Write leveling (Byte 0): 28 => 28
5574 12:30:03.665712 Write leveling (Byte 1): 29 => 29
5575 12:30:03.669439 DramcWriteLeveling(PI) end<-----
5576 12:30:03.669523
5577 12:30:03.669588 ==
5578 12:30:03.672612 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 12:30:03.675781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 12:30:03.675867 ==
5581 12:30:03.678931 [Gating] SW mode calibration
5582 12:30:03.685816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 12:30:03.692316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 12:30:03.695262 0 14 0 | B1->B0 | 3232 3232 | 0 1 | (0 0) (1 1)
5585 12:30:03.698672 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 12:30:03.705011 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 12:30:03.708480 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 12:30:03.712024 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 12:30:03.718855 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 12:30:03.721887 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5591 12:30:03.725452 0 14 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 1)
5592 12:30:03.731543 0 15 0 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
5593 12:30:03.734753 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 12:30:03.738242 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 12:30:03.744881 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 12:30:03.748256 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 12:30:03.751671 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 12:30:03.758112 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 12:30:03.761683 0 15 28 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
5600 12:30:03.764805 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5601 12:30:03.770941 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 12:30:03.774215 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 12:30:03.777886 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 12:30:03.784623 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 12:30:03.787746 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 12:30:03.790849 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 12:30:03.797561 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 12:30:03.801066 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 12:30:03.803974 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:30:03.811037 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:30:03.813986 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:30:03.817452 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 12:30:03.823981 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 12:30:03.827150 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 12:30:03.830726 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:30:03.836884 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:30:03.840566 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:30:03.843474 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:30:03.850521 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:30:03.853800 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:30:03.856760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:30:03.863178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5623 12:30:03.866685 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5624 12:30:03.870456 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5625 12:30:03.876521 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 12:30:03.876606 Total UI for P1: 0, mck2ui 16
5627 12:30:03.883255 best dqsien dly found for B0: ( 1, 2, 28)
5628 12:30:03.883339 Total UI for P1: 0, mck2ui 16
5629 12:30:03.889891 best dqsien dly found for B1: ( 1, 2, 28)
5630 12:30:03.892970 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5631 12:30:03.896687 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5632 12:30:03.896771
5633 12:30:03.899865 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5634 12:30:03.903031 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5635 12:30:03.906442 [Gating] SW calibration Done
5636 12:30:03.906526 ==
5637 12:30:03.909909 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 12:30:03.912702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 12:30:03.912786 ==
5640 12:30:03.916243 RX Vref Scan: 0
5641 12:30:03.916346
5642 12:30:03.916438 RX Vref 0 -> 0, step: 1
5643 12:30:03.916527
5644 12:30:03.919274 RX Delay -80 -> 252, step: 8
5645 12:30:03.922547 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5646 12:30:03.929076 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5647 12:30:03.932767 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5648 12:30:03.935852 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5649 12:30:03.938796 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5650 12:30:03.942661 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5651 12:30:03.949110 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5652 12:30:03.952235 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5653 12:30:03.955360 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5654 12:30:03.958791 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5655 12:30:03.962628 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5656 12:30:03.968663 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5657 12:30:03.972252 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5658 12:30:03.975210 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5659 12:30:03.978383 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5660 12:30:03.982127 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5661 12:30:03.982211 ==
5662 12:30:03.985259 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 12:30:03.991989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 12:30:03.992075 ==
5665 12:30:03.992145 DQS Delay:
5666 12:30:03.995167 DQS0 = 0, DQS1 = 0
5667 12:30:03.995253 DQM Delay:
5668 12:30:03.998209 DQM0 = 94, DQM1 = 86
5669 12:30:03.998291 DQ Delay:
5670 12:30:04.001880 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5671 12:30:04.005042 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5672 12:30:04.008178 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5673 12:30:04.011873 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5674 12:30:04.011956
5675 12:30:04.012022
5676 12:30:04.012083 ==
5677 12:30:04.014818 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 12:30:04.018513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 12:30:04.018597 ==
5680 12:30:04.018663
5681 12:30:04.018724
5682 12:30:04.021379 TX Vref Scan disable
5683 12:30:04.024854 == TX Byte 0 ==
5684 12:30:04.027815 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5685 12:30:04.031235 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5686 12:30:04.034748 == TX Byte 1 ==
5687 12:30:04.037833 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5688 12:30:04.041420 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5689 12:30:04.041540 ==
5690 12:30:04.044538 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 12:30:04.051201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 12:30:04.051288 ==
5693 12:30:04.051355
5694 12:30:04.051416
5695 12:30:04.051480 TX Vref Scan disable
5696 12:30:04.054941 == TX Byte 0 ==
5697 12:30:04.058137 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 12:30:04.064923 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 12:30:04.065006 == TX Byte 1 ==
5700 12:30:04.068408 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5701 12:30:04.075059 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5702 12:30:04.075147
5703 12:30:04.075212 [DATLAT]
5704 12:30:04.075274 Freq=933, CH1 RK0
5705 12:30:04.075334
5706 12:30:04.078259 DATLAT Default: 0xd
5707 12:30:04.081248 0, 0xFFFF, sum = 0
5708 12:30:04.081332 1, 0xFFFF, sum = 0
5709 12:30:04.084799 2, 0xFFFF, sum = 0
5710 12:30:04.084884 3, 0xFFFF, sum = 0
5711 12:30:04.087905 4, 0xFFFF, sum = 0
5712 12:30:04.087989 5, 0xFFFF, sum = 0
5713 12:30:04.091668 6, 0xFFFF, sum = 0
5714 12:30:04.091753 7, 0xFFFF, sum = 0
5715 12:30:04.094679 8, 0xFFFF, sum = 0
5716 12:30:04.094763 9, 0xFFFF, sum = 0
5717 12:30:04.097724 10, 0x0, sum = 1
5718 12:30:04.097823 11, 0x0, sum = 2
5719 12:30:04.101412 12, 0x0, sum = 3
5720 12:30:04.101498 13, 0x0, sum = 4
5721 12:30:04.104413 best_step = 11
5722 12:30:04.104495
5723 12:30:04.104561 ==
5724 12:30:04.107503 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 12:30:04.111225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 12:30:04.111312 ==
5727 12:30:04.111381 RX Vref Scan: 1
5728 12:30:04.111442
5729 12:30:04.114373 RX Vref 0 -> 0, step: 1
5730 12:30:04.114459
5731 12:30:04.117935 RX Delay -69 -> 252, step: 4
5732 12:30:04.118018
5733 12:30:04.120945 Set Vref, RX VrefLevel [Byte0]: 57
5734 12:30:04.124055 [Byte1]: 48
5735 12:30:04.127777
5736 12:30:04.127853 Final RX Vref Byte 0 = 57 to rank0
5737 12:30:04.130794 Final RX Vref Byte 1 = 48 to rank0
5738 12:30:04.134250 Final RX Vref Byte 0 = 57 to rank1
5739 12:30:04.137845 Final RX Vref Byte 1 = 48 to rank1==
5740 12:30:04.140774 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 12:30:04.147376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 12:30:04.147471 ==
5743 12:30:04.147539 DQS Delay:
5744 12:30:04.150427 DQS0 = 0, DQS1 = 0
5745 12:30:04.150522 DQM Delay:
5746 12:30:04.150589 DQM0 = 96, DQM1 = 88
5747 12:30:04.153929 DQ Delay:
5748 12:30:04.157635 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =92
5749 12:30:04.160791 DQ4 =94, DQ5 =104, DQ6 =108, DQ7 =94
5750 12:30:04.163970 DQ8 =74, DQ9 =78, DQ10 =90, DQ11 =80
5751 12:30:04.167034 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =94
5752 12:30:04.167118
5753 12:30:04.167184
5754 12:30:04.173654 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd06, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5755 12:30:04.177343 CH1 RK0: MR19=405, MR18=FD06
5756 12:30:04.183904 CH1_RK0: MR19=0x405, MR18=0xFD06, DQSOSC=420, MR23=63, INC=61, DEC=40
5757 12:30:04.183991
5758 12:30:04.187013 ----->DramcWriteLeveling(PI) begin...
5759 12:30:04.187097 ==
5760 12:30:04.190126 Dram Type= 6, Freq= 0, CH_1, rank 1
5761 12:30:04.193834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 12:30:04.193918 ==
5763 12:30:04.196892 Write leveling (Byte 0): 25 => 25
5764 12:30:04.200070 Write leveling (Byte 1): 29 => 29
5765 12:30:04.203874 DramcWriteLeveling(PI) end<-----
5766 12:30:04.203958
5767 12:30:04.204023 ==
5768 12:30:04.206814 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 12:30:04.210483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 12:30:04.213508 ==
5771 12:30:04.213583 [Gating] SW mode calibration
5772 12:30:04.223193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5773 12:30:04.226956 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5774 12:30:04.229975 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5775 12:30:04.236410 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 12:30:04.239590 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 12:30:04.243158 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 12:30:04.249786 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 12:30:04.252846 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 12:30:04.256569 0 14 24 | B1->B0 | 3434 302f | 1 1 | (1 1) (0 1)
5781 12:30:04.263273 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5782 12:30:04.265816 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 12:30:04.269546 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 12:30:04.276179 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 12:30:04.279209 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 12:30:04.282817 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 12:30:04.289255 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 12:30:04.292522 0 15 24 | B1->B0 | 2525 3333 | 1 0 | (0 0) (0 0)
5789 12:30:04.295694 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5790 12:30:04.301928 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 12:30:04.305731 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 12:30:04.311939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 12:30:04.315117 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 12:30:04.318767 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 12:30:04.325361 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 12:30:04.328496 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5797 12:30:04.331642 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5798 12:30:04.338502 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:30:04.341504 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:30:04.344902 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 12:30:04.351233 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:30:04.354747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 12:30:04.358298 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 12:30:04.364785 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:30:04.367808 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:30:04.370984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:30:04.377809 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:30:04.380860 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:30:04.383922 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:30:04.390768 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:30:04.393736 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:30:04.397162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5813 12:30:04.400604 Total UI for P1: 0, mck2ui 16
5814 12:30:04.403466 best dqsien dly found for B0: ( 1, 2, 22)
5815 12:30:04.410206 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5816 12:30:04.413896 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 12:30:04.416958 Total UI for P1: 0, mck2ui 16
5818 12:30:04.420106 best dqsien dly found for B1: ( 1, 2, 28)
5819 12:30:04.423651 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5820 12:30:04.426723 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5821 12:30:04.426794
5822 12:30:04.430130 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5823 12:30:04.433160 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5824 12:30:04.436891 [Gating] SW calibration Done
5825 12:30:04.436974 ==
5826 12:30:04.440014 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 12:30:04.446435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 12:30:04.446522 ==
5829 12:30:04.446587 RX Vref Scan: 0
5830 12:30:04.446649
5831 12:30:04.450106 RX Vref 0 -> 0, step: 1
5832 12:30:04.450189
5833 12:30:04.452988 RX Delay -80 -> 252, step: 8
5834 12:30:04.456606 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5835 12:30:04.460010 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5836 12:30:04.463038 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5837 12:30:04.466693 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5838 12:30:04.473052 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5839 12:30:04.476716 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5840 12:30:04.479769 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5841 12:30:04.482799 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5842 12:30:04.486374 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5843 12:30:04.492992 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5844 12:30:04.496191 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5845 12:30:04.499193 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5846 12:30:04.502581 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5847 12:30:04.506119 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5848 12:30:04.512538 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5849 12:30:04.515626 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5850 12:30:04.515737 ==
5851 12:30:04.519327 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 12:30:04.522371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 12:30:04.522454 ==
5854 12:30:04.522519 DQS Delay:
5855 12:30:04.525463 DQS0 = 0, DQS1 = 0
5856 12:30:04.525545 DQM Delay:
5857 12:30:04.528613 DQM0 = 93, DQM1 = 88
5858 12:30:04.528696 DQ Delay:
5859 12:30:04.532212 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5860 12:30:04.535737 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5861 12:30:04.538732 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5862 12:30:04.541825 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5863 12:30:04.541907
5864 12:30:04.541980
5865 12:30:04.542072 ==
5866 12:30:04.545629 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 12:30:04.551732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 12:30:04.551816 ==
5869 12:30:04.551881
5870 12:30:04.551941
5871 12:30:04.551998 TX Vref Scan disable
5872 12:30:04.555355 == TX Byte 0 ==
5873 12:30:04.559066 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5874 12:30:04.565329 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5875 12:30:04.565418 == TX Byte 1 ==
5876 12:30:04.568845 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5877 12:30:04.575475 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5878 12:30:04.575560 ==
5879 12:30:04.578884 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 12:30:04.582129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 12:30:04.582212 ==
5882 12:30:04.582278
5883 12:30:04.582338
5884 12:30:04.584935 TX Vref Scan disable
5885 12:30:04.588625 == TX Byte 0 ==
5886 12:30:04.591437 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5887 12:30:04.595207 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5888 12:30:04.598290 == TX Byte 1 ==
5889 12:30:04.601301 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5890 12:30:04.604892 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5891 12:30:04.605063
5892 12:30:04.605189 [DATLAT]
5893 12:30:04.607987 Freq=933, CH1 RK1
5894 12:30:04.608073
5895 12:30:04.611794 DATLAT Default: 0xb
5896 12:30:04.611878 0, 0xFFFF, sum = 0
5897 12:30:04.614788 1, 0xFFFF, sum = 0
5898 12:30:04.614921 2, 0xFFFF, sum = 0
5899 12:30:04.618201 3, 0xFFFF, sum = 0
5900 12:30:04.618286 4, 0xFFFF, sum = 0
5901 12:30:04.621248 5, 0xFFFF, sum = 0
5902 12:30:04.621334 6, 0xFFFF, sum = 0
5903 12:30:04.624840 7, 0xFFFF, sum = 0
5904 12:30:04.624930 8, 0xFFFF, sum = 0
5905 12:30:04.627960 9, 0xFFFF, sum = 0
5906 12:30:04.628054 10, 0x0, sum = 1
5907 12:30:04.631152 11, 0x0, sum = 2
5908 12:30:04.631235 12, 0x0, sum = 3
5909 12:30:04.634288 13, 0x0, sum = 4
5910 12:30:04.634387 best_step = 11
5911 12:30:04.634468
5912 12:30:04.634561 ==
5913 12:30:04.637872 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 12:30:04.640858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 12:30:04.644584 ==
5916 12:30:04.644747 RX Vref Scan: 0
5917 12:30:04.644880
5918 12:30:04.647748 RX Vref 0 -> 0, step: 1
5919 12:30:04.647845
5920 12:30:04.650946 RX Delay -69 -> 252, step: 4
5921 12:30:04.654586 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5922 12:30:04.657811 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5923 12:30:04.663973 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5924 12:30:04.667630 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5925 12:30:04.670840 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5926 12:30:04.673758 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5927 12:30:04.677316 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5928 12:30:04.680798 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5929 12:30:04.687439 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5930 12:30:04.690760 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5931 12:30:04.693814 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5932 12:30:04.696823 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5933 12:30:04.700511 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5934 12:30:04.706815 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5935 12:30:04.710464 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5936 12:30:04.713628 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5937 12:30:04.713738 ==
5938 12:30:04.716770 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 12:30:04.720586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 12:30:04.720671 ==
5941 12:30:04.723523 DQS Delay:
5942 12:30:04.723610 DQS0 = 0, DQS1 = 0
5943 12:30:04.726522 DQM Delay:
5944 12:30:04.726624 DQM0 = 91, DQM1 = 91
5945 12:30:04.730529 DQ Delay:
5946 12:30:04.730620 DQ0 =94, DQ1 =86, DQ2 =80, DQ3 =88
5947 12:30:04.733479 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
5948 12:30:04.736671 DQ8 =76, DQ9 =82, DQ10 =94, DQ11 =86
5949 12:30:04.743109 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =96
5950 12:30:04.743224
5951 12:30:04.743303
5952 12:30:04.749803 [DQSOSCAuto] RK1, (LSB)MR18= 0x1025, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5953 12:30:04.753557 CH1 RK1: MR19=505, MR18=1025
5954 12:30:04.759837 CH1_RK1: MR19=0x505, MR18=0x1025, DQSOSC=410, MR23=63, INC=64, DEC=42
5955 12:30:04.762941 [RxdqsGatingPostProcess] freq 933
5956 12:30:04.766605 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5957 12:30:04.770134 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 12:30:04.773251 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 12:30:04.776557 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 12:30:04.779604 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 12:30:04.783336 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 12:30:04.786436 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 12:30:04.790095 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 12:30:04.793141 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 12:30:04.796150 Pre-setting of DQS Precalculation
5966 12:30:04.799698 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5967 12:30:04.806354 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5968 12:30:04.816205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5969 12:30:04.816303
5970 12:30:04.816371
5971 12:30:04.819811 [Calibration Summary] 1866 Mbps
5972 12:30:04.819894 CH 0, Rank 0
5973 12:30:04.822940 SW Impedance : PASS
5974 12:30:04.823023 DUTY Scan : NO K
5975 12:30:04.825940 ZQ Calibration : PASS
5976 12:30:04.829707 Jitter Meter : NO K
5977 12:30:04.829790 CBT Training : PASS
5978 12:30:04.832782 Write leveling : PASS
5979 12:30:04.835760 RX DQS gating : PASS
5980 12:30:04.835842 RX DQ/DQS(RDDQC) : PASS
5981 12:30:04.839308 TX DQ/DQS : PASS
5982 12:30:04.842733 RX DATLAT : PASS
5983 12:30:04.842816 RX DQ/DQS(Engine): PASS
5984 12:30:04.845507 TX OE : NO K
5985 12:30:04.845591 All Pass.
5986 12:30:04.845656
5987 12:30:04.849129 CH 0, Rank 1
5988 12:30:04.849213 SW Impedance : PASS
5989 12:30:04.852322 DUTY Scan : NO K
5990 12:30:04.855996 ZQ Calibration : PASS
5991 12:30:04.856079 Jitter Meter : NO K
5992 12:30:04.859157 CBT Training : PASS
5993 12:30:04.859240 Write leveling : PASS
5994 12:30:04.862270 RX DQS gating : PASS
5995 12:30:04.865307 RX DQ/DQS(RDDQC) : PASS
5996 12:30:04.865390 TX DQ/DQS : PASS
5997 12:30:04.868971 RX DATLAT : PASS
5998 12:30:04.872127 RX DQ/DQS(Engine): PASS
5999 12:30:04.872210 TX OE : NO K
6000 12:30:04.875205 All Pass.
6001 12:30:04.875288
6002 12:30:04.875354 CH 1, Rank 0
6003 12:30:04.878779 SW Impedance : PASS
6004 12:30:04.878890 DUTY Scan : NO K
6005 12:30:04.882160 ZQ Calibration : PASS
6006 12:30:04.885683 Jitter Meter : NO K
6007 12:30:04.885767 CBT Training : PASS
6008 12:30:04.888734 Write leveling : PASS
6009 12:30:04.891655 RX DQS gating : PASS
6010 12:30:04.891766 RX DQ/DQS(RDDQC) : PASS
6011 12:30:04.895437 TX DQ/DQS : PASS
6012 12:30:04.898285 RX DATLAT : PASS
6013 12:30:04.898358 RX DQ/DQS(Engine): PASS
6014 12:30:04.901925 TX OE : NO K
6015 12:30:04.902024 All Pass.
6016 12:30:04.902113
6017 12:30:04.904880 CH 1, Rank 1
6018 12:30:04.904977 SW Impedance : PASS
6019 12:30:04.908680 DUTY Scan : NO K
6020 12:30:04.911831 ZQ Calibration : PASS
6021 12:30:04.911912 Jitter Meter : NO K
6022 12:30:04.914990 CBT Training : PASS
6023 12:30:04.918282 Write leveling : PASS
6024 12:30:04.918388 RX DQS gating : PASS
6025 12:30:04.921442 RX DQ/DQS(RDDQC) : PASS
6026 12:30:04.925133 TX DQ/DQS : PASS
6027 12:30:04.925205 RX DATLAT : PASS
6028 12:30:04.928318 RX DQ/DQS(Engine): PASS
6029 12:30:04.931280 TX OE : NO K
6030 12:30:04.931352 All Pass.
6031 12:30:04.931415
6032 12:30:04.931473 DramC Write-DBI off
6033 12:30:04.934974 PER_BANK_REFRESH: Hybrid Mode
6034 12:30:04.938005 TX_TRACKING: ON
6035 12:30:04.944681 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6036 12:30:04.947533 [FAST_K] Save calibration result to emmc
6037 12:30:04.954360 dramc_set_vcore_voltage set vcore to 650000
6038 12:30:04.954467 Read voltage for 400, 6
6039 12:30:04.957989 Vio18 = 0
6040 12:30:04.958093 Vcore = 650000
6041 12:30:04.958157 Vdram = 0
6042 12:30:04.961133 Vddq = 0
6043 12:30:04.961242 Vmddr = 0
6044 12:30:04.964345 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6045 12:30:04.971145 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6046 12:30:04.974234 MEM_TYPE=3, freq_sel=20
6047 12:30:04.977404 sv_algorithm_assistance_LP4_800
6048 12:30:04.980591 ============ PULL DRAM RESETB DOWN ============
6049 12:30:04.984128 ========== PULL DRAM RESETB DOWN end =========
6050 12:30:04.987903 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6051 12:30:04.990736 ===================================
6052 12:30:04.993719 LPDDR4 DRAM CONFIGURATION
6053 12:30:04.997482 ===================================
6054 12:30:05.000468 EX_ROW_EN[0] = 0x0
6055 12:30:05.000553 EX_ROW_EN[1] = 0x0
6056 12:30:05.003842 LP4Y_EN = 0x0
6057 12:30:05.003925 WORK_FSP = 0x0
6058 12:30:05.007474 WL = 0x2
6059 12:30:05.007551 RL = 0x2
6060 12:30:05.010452 BL = 0x2
6061 12:30:05.013576 RPST = 0x0
6062 12:30:05.013680 RD_PRE = 0x0
6063 12:30:05.017276 WR_PRE = 0x1
6064 12:30:05.017374 WR_PST = 0x0
6065 12:30:05.020405 DBI_WR = 0x0
6066 12:30:05.020477 DBI_RD = 0x0
6067 12:30:05.023755 OTF = 0x1
6068 12:30:05.026774 ===================================
6069 12:30:05.029951 ===================================
6070 12:30:05.030054 ANA top config
6071 12:30:05.033187 ===================================
6072 12:30:05.036774 DLL_ASYNC_EN = 0
6073 12:30:05.039782 ALL_SLAVE_EN = 1
6074 12:30:05.039864 NEW_RANK_MODE = 1
6075 12:30:05.043504 DLL_IDLE_MODE = 1
6076 12:30:05.046453 LP45_APHY_COMB_EN = 1
6077 12:30:05.050146 TX_ODT_DIS = 1
6078 12:30:05.053231 NEW_8X_MODE = 1
6079 12:30:05.056288 ===================================
6080 12:30:05.059698 ===================================
6081 12:30:05.059803 data_rate = 800
6082 12:30:05.062778 CKR = 1
6083 12:30:05.065941 DQ_P2S_RATIO = 4
6084 12:30:05.069351 ===================================
6085 12:30:05.073109 CA_P2S_RATIO = 4
6086 12:30:05.076141 DQ_CA_OPEN = 0
6087 12:30:05.079265 DQ_SEMI_OPEN = 1
6088 12:30:05.082288 CA_SEMI_OPEN = 1
6089 12:30:05.082388 CA_FULL_RATE = 0
6090 12:30:05.086006 DQ_CKDIV4_EN = 0
6091 12:30:05.089012 CA_CKDIV4_EN = 1
6092 12:30:05.092631 CA_PREDIV_EN = 0
6093 12:30:05.095977 PH8_DLY = 0
6094 12:30:05.098920 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6095 12:30:05.099037 DQ_AAMCK_DIV = 0
6096 12:30:05.102823 CA_AAMCK_DIV = 0
6097 12:30:05.105458 CA_ADMCK_DIV = 4
6098 12:30:05.109060 DQ_TRACK_CA_EN = 0
6099 12:30:05.112442 CA_PICK = 800
6100 12:30:05.115455 CA_MCKIO = 400
6101 12:30:05.118595 MCKIO_SEMI = 400
6102 12:30:05.122395 PLL_FREQ = 3016
6103 12:30:05.122507 DQ_UI_PI_RATIO = 32
6104 12:30:05.125409 CA_UI_PI_RATIO = 32
6105 12:30:05.128874 ===================================
6106 12:30:05.131990 ===================================
6107 12:30:05.135074 memory_type:LPDDR4
6108 12:30:05.138791 GP_NUM : 10
6109 12:30:05.138908 SRAM_EN : 1
6110 12:30:05.141817 MD32_EN : 0
6111 12:30:05.144917 ===================================
6112 12:30:05.148718 [ANA_INIT] >>>>>>>>>>>>>>
6113 12:30:05.148833 <<<<<< [CONFIGURE PHASE]: ANA_TX
6114 12:30:05.151782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6115 12:30:05.154776 ===================================
6116 12:30:05.158566 data_rate = 800,PCW = 0X7400
6117 12:30:05.161599 ===================================
6118 12:30:05.164705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6119 12:30:05.171256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 12:30:05.181286 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 12:30:05.188081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6122 12:30:05.191288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6123 12:30:05.194246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6124 12:30:05.197878 [ANA_INIT] flow start
6125 12:30:05.197965 [ANA_INIT] PLL >>>>>>>>
6126 12:30:05.201326 [ANA_INIT] PLL <<<<<<<<
6127 12:30:05.204273 [ANA_INIT] MIDPI >>>>>>>>
6128 12:30:05.204359 [ANA_INIT] MIDPI <<<<<<<<
6129 12:30:05.207922 [ANA_INIT] DLL >>>>>>>>
6130 12:30:05.210874 [ANA_INIT] flow end
6131 12:30:05.214530 ============ LP4 DIFF to SE enter ============
6132 12:30:05.217420 ============ LP4 DIFF to SE exit ============
6133 12:30:05.221083 [ANA_INIT] <<<<<<<<<<<<<
6134 12:30:05.224050 [Flow] Enable top DCM control >>>>>
6135 12:30:05.227257 [Flow] Enable top DCM control <<<<<
6136 12:30:05.230406 Enable DLL master slave shuffle
6137 12:30:05.234059 ==============================================================
6138 12:30:05.237155 Gating Mode config
6139 12:30:05.244048 ==============================================================
6140 12:30:05.244174 Config description:
6141 12:30:05.253932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6142 12:30:05.260489 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6143 12:30:05.266631 SELPH_MODE 0: By rank 1: By Phase
6144 12:30:05.270307 ==============================================================
6145 12:30:05.273441 GAT_TRACK_EN = 0
6146 12:30:05.276598 RX_GATING_MODE = 2
6147 12:30:05.280037 RX_GATING_TRACK_MODE = 2
6148 12:30:05.283466 SELPH_MODE = 1
6149 12:30:05.286375 PICG_EARLY_EN = 1
6150 12:30:05.290214 VALID_LAT_VALUE = 1
6151 12:30:05.296438 ==============================================================
6152 12:30:05.300102 Enter into Gating configuration >>>>
6153 12:30:05.303138 Exit from Gating configuration <<<<
6154 12:30:05.303225 Enter into DVFS_PRE_config >>>>>
6155 12:30:05.316502 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6156 12:30:05.319401 Exit from DVFS_PRE_config <<<<<
6157 12:30:05.323021 Enter into PICG configuration >>>>
6158 12:30:05.325829 Exit from PICG configuration <<<<
6159 12:30:05.329211 [RX_INPUT] configuration >>>>>
6160 12:30:05.329326 [RX_INPUT] configuration <<<<<
6161 12:30:05.335725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6162 12:30:05.342571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6163 12:30:05.345686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 12:30:05.352509 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 12:30:05.358666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 12:30:05.365376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 12:30:05.368465 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6168 12:30:05.372193 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6169 12:30:05.378383 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6170 12:30:05.382104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6171 12:30:05.385027 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6172 12:30:05.391679 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 12:30:05.394845 ===================================
6174 12:30:05.394945 LPDDR4 DRAM CONFIGURATION
6175 12:30:05.398517 ===================================
6176 12:30:05.401641 EX_ROW_EN[0] = 0x0
6177 12:30:05.405216 EX_ROW_EN[1] = 0x0
6178 12:30:05.405329 LP4Y_EN = 0x0
6179 12:30:05.408126 WORK_FSP = 0x0
6180 12:30:05.408234 WL = 0x2
6181 12:30:05.411659 RL = 0x2
6182 12:30:05.411769 BL = 0x2
6183 12:30:05.415183 RPST = 0x0
6184 12:30:05.415292 RD_PRE = 0x0
6185 12:30:05.418251 WR_PRE = 0x1
6186 12:30:05.418367 WR_PST = 0x0
6187 12:30:05.421310 DBI_WR = 0x0
6188 12:30:05.421420 DBI_RD = 0x0
6189 12:30:05.425086 OTF = 0x1
6190 12:30:05.428030 ===================================
6191 12:30:05.431568 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6192 12:30:05.434907 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6193 12:30:05.441472 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 12:30:05.444588 ===================================
6195 12:30:05.444711 LPDDR4 DRAM CONFIGURATION
6196 12:30:05.447615 ===================================
6197 12:30:05.451335 EX_ROW_EN[0] = 0x10
6198 12:30:05.454385 EX_ROW_EN[1] = 0x0
6199 12:30:05.454493 LP4Y_EN = 0x0
6200 12:30:05.457582 WORK_FSP = 0x0
6201 12:30:05.457666 WL = 0x2
6202 12:30:05.461314 RL = 0x2
6203 12:30:05.461391 BL = 0x2
6204 12:30:05.464370 RPST = 0x0
6205 12:30:05.464447 RD_PRE = 0x0
6206 12:30:05.467407 WR_PRE = 0x1
6207 12:30:05.467491 WR_PST = 0x0
6208 12:30:05.471013 DBI_WR = 0x0
6209 12:30:05.471097 DBI_RD = 0x0
6210 12:30:05.474030 OTF = 0x1
6211 12:30:05.477670 ===================================
6212 12:30:05.484388 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6213 12:30:05.487836 nWR fixed to 30
6214 12:30:05.490628 [ModeRegInit_LP4] CH0 RK0
6215 12:30:05.490738 [ModeRegInit_LP4] CH0 RK1
6216 12:30:05.494739 [ModeRegInit_LP4] CH1 RK0
6217 12:30:05.497149 [ModeRegInit_LP4] CH1 RK1
6218 12:30:05.497233 match AC timing 19
6219 12:30:05.503791 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6220 12:30:05.507352 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6221 12:30:05.510495 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6222 12:30:05.517118 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6223 12:30:05.520048 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6224 12:30:05.520131 ==
6225 12:30:05.523495 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 12:30:05.526927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 12:30:05.527017 ==
6228 12:30:05.533468 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 12:30:05.539829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 12:30:05.543197 [CA 0] Center 36 (8~64) winsize 57
6231 12:30:05.546682 [CA 1] Center 36 (8~64) winsize 57
6232 12:30:05.549741 [CA 2] Center 36 (8~64) winsize 57
6233 12:30:05.553387 [CA 3] Center 36 (8~64) winsize 57
6234 12:30:05.556645 [CA 4] Center 36 (8~64) winsize 57
6235 12:30:05.556728 [CA 5] Center 36 (8~64) winsize 57
6236 12:30:05.559619
6237 12:30:05.563264 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 12:30:05.563348
6239 12:30:05.566313 [CATrainingPosCal] consider 1 rank data
6240 12:30:05.569863 u2DelayCellTimex100 = 270/100 ps
6241 12:30:05.572855 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:30:05.576597 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:30:05.579715 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:30:05.582803 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:30:05.585943 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:30:05.589595 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:30:05.589678
6248 12:30:05.596151 CA PerBit enable=1, Macro0, CA PI delay=36
6249 12:30:05.596236
6250 12:30:05.596335 [CBTSetCACLKResult] CA Dly = 36
6251 12:30:05.599203 CS Dly: 1 (0~32)
6252 12:30:05.599286 ==
6253 12:30:05.602765 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 12:30:05.605879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 12:30:05.606011 ==
6256 12:30:05.612786 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 12:30:05.618812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 12:30:05.622533 [CA 0] Center 36 (8~64) winsize 57
6259 12:30:05.626101 [CA 1] Center 36 (8~64) winsize 57
6260 12:30:05.629040 [CA 2] Center 36 (8~64) winsize 57
6261 12:30:05.632771 [CA 3] Center 36 (8~64) winsize 57
6262 12:30:05.632855 [CA 4] Center 36 (8~64) winsize 57
6263 12:30:05.635922 [CA 5] Center 36 (8~64) winsize 57
6264 12:30:05.636006
6265 12:30:05.641974 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 12:30:05.642058
6267 12:30:05.645451 [CATrainingPosCal] consider 2 rank data
6268 12:30:05.648904 u2DelayCellTimex100 = 270/100 ps
6269 12:30:05.652287 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:30:05.655335 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 12:30:05.658993 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 12:30:05.662060 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 12:30:05.665301 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 12:30:05.668399 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 12:30:05.668482
6276 12:30:05.672425 CA PerBit enable=1, Macro0, CA PI delay=36
6277 12:30:05.672509
6278 12:30:05.675316 [CBTSetCACLKResult] CA Dly = 36
6279 12:30:05.678327 CS Dly: 1 (0~32)
6280 12:30:05.678436
6281 12:30:05.682016 ----->DramcWriteLeveling(PI) begin...
6282 12:30:05.682100 ==
6283 12:30:05.685184 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 12:30:05.688206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 12:30:05.688320 ==
6286 12:30:05.691387 Write leveling (Byte 0): 40 => 8
6287 12:30:05.695116 Write leveling (Byte 1): 40 => 8
6288 12:30:05.698174 DramcWriteLeveling(PI) end<-----
6289 12:30:05.698256
6290 12:30:05.698322 ==
6291 12:30:05.701268 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 12:30:05.705049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 12:30:05.705131 ==
6294 12:30:05.708380 [Gating] SW mode calibration
6295 12:30:05.714722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6296 12:30:05.721556 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6297 12:30:05.724561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 12:30:05.730849 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 12:30:05.734414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 12:30:05.737815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 12:30:05.744476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 12:30:05.747432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 12:30:05.750860 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 12:30:05.757506 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 12:30:05.760632 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 12:30:05.764388 Total UI for P1: 0, mck2ui 16
6307 12:30:05.767567 best dqsien dly found for B0: ( 0, 14, 24)
6308 12:30:05.770729 Total UI for P1: 0, mck2ui 16
6309 12:30:05.773799 best dqsien dly found for B1: ( 0, 14, 24)
6310 12:30:05.777531 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6311 12:30:05.780498 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6312 12:30:05.780577
6313 12:30:05.784206 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 12:30:05.787275 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 12:30:05.790317 [Gating] SW calibration Done
6316 12:30:05.790397 ==
6317 12:30:05.793873 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 12:30:05.800483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 12:30:05.800564 ==
6320 12:30:05.800627 RX Vref Scan: 0
6321 12:30:05.800686
6322 12:30:05.803406 RX Vref 0 -> 0, step: 1
6323 12:30:05.803486
6324 12:30:05.807090 RX Delay -410 -> 252, step: 16
6325 12:30:05.810239 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6326 12:30:05.813597 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6327 12:30:05.819993 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6328 12:30:05.823197 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6329 12:30:05.826974 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6330 12:30:05.830044 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6331 12:30:05.836700 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6332 12:30:05.840181 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6333 12:30:05.843211 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6334 12:30:05.846709 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6335 12:30:05.853212 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6336 12:30:05.855994 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6337 12:30:05.859501 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6338 12:30:05.862944 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6339 12:30:05.869361 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6340 12:30:05.873063 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6341 12:30:05.873143 ==
6342 12:30:05.876148 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 12:30:05.879238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 12:30:05.879319 ==
6345 12:30:05.882474 DQS Delay:
6346 12:30:05.882554 DQS0 = 59, DQS1 = 59
6347 12:30:05.886025 DQM Delay:
6348 12:30:05.886106 DQM0 = 18, DQM1 = 10
6349 12:30:05.889120 DQ Delay:
6350 12:30:05.889208 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6351 12:30:05.892328 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6352 12:30:05.895997 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6353 12:30:05.899099 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6354 12:30:05.899180
6355 12:30:05.899258
6356 12:30:05.902314 ==
6357 12:30:05.905945 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 12:30:05.908976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 12:30:05.909057 ==
6360 12:30:05.909120
6361 12:30:05.909177
6362 12:30:05.912020 TX Vref Scan disable
6363 12:30:05.912099 == TX Byte 0 ==
6364 12:30:05.915730 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 12:30:05.922059 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 12:30:05.922139 == TX Byte 1 ==
6367 12:30:05.925562 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 12:30:05.931862 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 12:30:05.931942 ==
6370 12:30:05.935576 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 12:30:05.938710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 12:30:05.938792 ==
6373 12:30:05.938896
6374 12:30:05.938956
6375 12:30:05.941821 TX Vref Scan disable
6376 12:30:05.941901 == TX Byte 0 ==
6377 12:30:05.945328 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 12:30:05.951767 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 12:30:05.951869 == TX Byte 1 ==
6380 12:30:05.955177 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 12:30:05.961801 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 12:30:05.961908
6383 12:30:05.961974 [DATLAT]
6384 12:30:05.962034 Freq=400, CH0 RK0
6385 12:30:05.965048
6386 12:30:05.965156 DATLAT Default: 0xf
6387 12:30:05.968510 0, 0xFFFF, sum = 0
6388 12:30:05.968591 1, 0xFFFF, sum = 0
6389 12:30:05.971331 2, 0xFFFF, sum = 0
6390 12:30:05.971412 3, 0xFFFF, sum = 0
6391 12:30:05.974718 4, 0xFFFF, sum = 0
6392 12:30:05.974799 5, 0xFFFF, sum = 0
6393 12:30:05.978269 6, 0xFFFF, sum = 0
6394 12:30:05.978351 7, 0xFFFF, sum = 0
6395 12:30:05.981261 8, 0xFFFF, sum = 0
6396 12:30:05.981342 9, 0xFFFF, sum = 0
6397 12:30:05.984413 10, 0xFFFF, sum = 0
6398 12:30:05.984498 11, 0xFFFF, sum = 0
6399 12:30:05.988226 12, 0xFFFF, sum = 0
6400 12:30:05.988307 13, 0x0, sum = 1
6401 12:30:05.991222 14, 0x0, sum = 2
6402 12:30:05.991324 15, 0x0, sum = 3
6403 12:30:05.994901 16, 0x0, sum = 4
6404 12:30:05.994985 best_step = 14
6405 12:30:05.995048
6406 12:30:05.995106 ==
6407 12:30:05.997928 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 12:30:06.004657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 12:30:06.004737 ==
6410 12:30:06.004799 RX Vref Scan: 1
6411 12:30:06.004858
6412 12:30:06.007945 RX Vref 0 -> 0, step: 1
6413 12:30:06.008025
6414 12:30:06.011210 RX Delay -359 -> 252, step: 8
6415 12:30:06.011291
6416 12:30:06.014266 Set Vref, RX VrefLevel [Byte0]: 63
6417 12:30:06.017453 [Byte1]: 58
6418 12:30:06.021191
6419 12:30:06.021286 Final RX Vref Byte 0 = 63 to rank0
6420 12:30:06.024332 Final RX Vref Byte 1 = 58 to rank0
6421 12:30:06.027957 Final RX Vref Byte 0 = 63 to rank1
6422 12:30:06.031157 Final RX Vref Byte 1 = 58 to rank1==
6423 12:30:06.034119 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 12:30:06.040895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 12:30:06.040976 ==
6426 12:30:06.041039 DQS Delay:
6427 12:30:06.044142 DQS0 = 60, DQS1 = 68
6428 12:30:06.044221 DQM Delay:
6429 12:30:06.047313 DQM0 = 14, DQM1 = 14
6430 12:30:06.047393 DQ Delay:
6431 12:30:06.050447 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6432 12:30:06.054007 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6433 12:30:06.056938 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6434 12:30:06.060638 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6435 12:30:06.060718
6436 12:30:06.060782
6437 12:30:06.066885 [DQSOSCAuto] RK0, (LSB)MR18= 0x8483, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6438 12:30:06.070306 CH0 RK0: MR19=C0C, MR18=8483
6439 12:30:06.077150 CH0_RK0: MR19=0xC0C, MR18=0x8483, DQSOSC=393, MR23=63, INC=382, DEC=254
6440 12:30:06.077242 ==
6441 12:30:06.079894 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 12:30:06.083281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 12:30:06.083382 ==
6444 12:30:06.086653 [Gating] SW mode calibration
6445 12:30:06.093162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6446 12:30:06.099886 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6447 12:30:06.103086 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 12:30:06.109810 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 12:30:06.112759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 12:30:06.116259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 12:30:06.122441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 12:30:06.126311 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 12:30:06.129447 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 12:30:06.135851 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 12:30:06.139072 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 12:30:06.142187 Total UI for P1: 0, mck2ui 16
6457 12:30:06.145365 best dqsien dly found for B0: ( 0, 14, 24)
6458 12:30:06.148507 Total UI for P1: 0, mck2ui 16
6459 12:30:06.152283 best dqsien dly found for B1: ( 0, 14, 24)
6460 12:30:06.155399 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6461 12:30:06.158615 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6462 12:30:06.158698
6463 12:30:06.162167 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 12:30:06.165140 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 12:30:06.168318 [Gating] SW calibration Done
6466 12:30:06.168402 ==
6467 12:30:06.172011 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 12:30:06.178434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 12:30:06.178518 ==
6470 12:30:06.178583 RX Vref Scan: 0
6471 12:30:06.178644
6472 12:30:06.181976 RX Vref 0 -> 0, step: 1
6473 12:30:06.182094
6474 12:30:06.185026 RX Delay -410 -> 252, step: 16
6475 12:30:06.188531 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6476 12:30:06.191428 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6477 12:30:06.198039 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6478 12:30:06.201414 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6479 12:30:06.204521 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6480 12:30:06.208251 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6481 12:30:06.214678 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6482 12:30:06.217744 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6483 12:30:06.221420 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6484 12:30:06.224451 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6485 12:30:06.231256 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6486 12:30:06.234445 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6487 12:30:06.237581 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6488 12:30:06.241451 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6489 12:30:06.247479 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6490 12:30:06.251153 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6491 12:30:06.251236 ==
6492 12:30:06.254206 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 12:30:06.257970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 12:30:06.258045 ==
6495 12:30:06.261080 DQS Delay:
6496 12:30:06.261156 DQS0 = 59, DQS1 = 59
6497 12:30:06.264143 DQM Delay:
6498 12:30:06.264233 DQM0 = 16, DQM1 = 10
6499 12:30:06.267262 DQ Delay:
6500 12:30:06.267369 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6501 12:30:06.270765 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6502 12:30:06.274211 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6503 12:30:06.277768 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6504 12:30:06.277879
6505 12:30:06.277976
6506 12:30:06.280617 ==
6507 12:30:06.280773 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 12:30:06.287625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 12:30:06.287742 ==
6510 12:30:06.287840
6511 12:30:06.287937
6512 12:30:06.290499 TX Vref Scan disable
6513 12:30:06.290610 == TX Byte 0 ==
6514 12:30:06.294009 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6515 12:30:06.300583 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6516 12:30:06.300703 == TX Byte 1 ==
6517 12:30:06.304140 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6518 12:30:06.310370 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6519 12:30:06.310485 ==
6520 12:30:06.313850 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 12:30:06.317004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 12:30:06.317118 ==
6523 12:30:06.317216
6524 12:30:06.317314
6525 12:30:06.320134 TX Vref Scan disable
6526 12:30:06.320245 == TX Byte 0 ==
6527 12:30:06.323730 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6528 12:30:06.330426 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6529 12:30:06.330541 == TX Byte 1 ==
6530 12:30:06.333660 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6531 12:30:06.340332 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6532 12:30:06.340462
6533 12:30:06.340560 [DATLAT]
6534 12:30:06.340657 Freq=400, CH0 RK1
6535 12:30:06.340756
6536 12:30:06.343428 DATLAT Default: 0xe
6537 12:30:06.346773 0, 0xFFFF, sum = 0
6538 12:30:06.346909 1, 0xFFFF, sum = 0
6539 12:30:06.350372 2, 0xFFFF, sum = 0
6540 12:30:06.350485 3, 0xFFFF, sum = 0
6541 12:30:06.353228 4, 0xFFFF, sum = 0
6542 12:30:06.353357 5, 0xFFFF, sum = 0
6543 12:30:06.356226 6, 0xFFFF, sum = 0
6544 12:30:06.356341 7, 0xFFFF, sum = 0
6545 12:30:06.359922 8, 0xFFFF, sum = 0
6546 12:30:06.360032 9, 0xFFFF, sum = 0
6547 12:30:06.362993 10, 0xFFFF, sum = 0
6548 12:30:06.363106 11, 0xFFFF, sum = 0
6549 12:30:06.366608 12, 0xFFFF, sum = 0
6550 12:30:06.366735 13, 0x0, sum = 1
6551 12:30:06.369605 14, 0x0, sum = 2
6552 12:30:06.369731 15, 0x0, sum = 3
6553 12:30:06.373289 16, 0x0, sum = 4
6554 12:30:06.373402 best_step = 14
6555 12:30:06.373502
6556 12:30:06.373599 ==
6557 12:30:06.376286 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 12:30:06.382676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 12:30:06.382793 ==
6560 12:30:06.382933 RX Vref Scan: 0
6561 12:30:06.383030
6562 12:30:06.386233 RX Vref 0 -> 0, step: 1
6563 12:30:06.386342
6564 12:30:06.389615 RX Delay -359 -> 252, step: 8
6565 12:30:06.396098 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6566 12:30:06.399599 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6567 12:30:06.402571 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6568 12:30:06.406101 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6569 12:30:06.412746 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6570 12:30:06.415801 iDelay=217, Bit 5, Center -56 (-303 ~ 192) 496
6571 12:30:06.418840 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6572 12:30:06.422598 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6573 12:30:06.429092 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6574 12:30:06.432204 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6575 12:30:06.435273 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6576 12:30:06.442057 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6577 12:30:06.445174 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6578 12:30:06.448879 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6579 12:30:06.451965 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6580 12:30:06.458930 iDelay=217, Bit 15, Center -44 (-295 ~ 208) 504
6581 12:30:06.459045 ==
6582 12:30:06.461747 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 12:30:06.464915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 12:30:06.465029 ==
6585 12:30:06.465128 DQS Delay:
6586 12:30:06.468685 DQS0 = 56, DQS1 = 68
6587 12:30:06.468797 DQM Delay:
6588 12:30:06.471856 DQM0 = 8, DQM1 = 14
6589 12:30:06.471967 DQ Delay:
6590 12:30:06.474948 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6591 12:30:06.478087 DQ4 =4, DQ5 =0, DQ6 =20, DQ7 =20
6592 12:30:06.481806 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6593 12:30:06.484801 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6594 12:30:06.484911
6595 12:30:06.485009
6596 12:30:06.491680 [DQSOSCAuto] RK1, (LSB)MR18= 0xc175, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6597 12:30:06.495027 CH0 RK1: MR19=C0C, MR18=C175
6598 12:30:06.501405 CH0_RK1: MR19=0xC0C, MR18=0xC175, DQSOSC=385, MR23=63, INC=398, DEC=265
6599 12:30:06.504867 [RxdqsGatingPostProcess] freq 400
6600 12:30:06.511195 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6601 12:30:06.514531 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 12:30:06.517925 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 12:30:06.520834 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 12:30:06.524647 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 12:30:06.527764 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 12:30:06.527875 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 12:30:06.530746 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 12:30:06.534388 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 12:30:06.537371 Pre-setting of DQS Precalculation
6610 12:30:06.544308 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6611 12:30:06.544422 ==
6612 12:30:06.547291 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 12:30:06.551139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 12:30:06.551253 ==
6615 12:30:06.557298 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 12:30:06.564331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6617 12:30:06.567652 [CA 0] Center 36 (8~64) winsize 57
6618 12:30:06.570730 [CA 1] Center 36 (8~64) winsize 57
6619 12:30:06.570866 [CA 2] Center 36 (8~64) winsize 57
6620 12:30:06.573808 [CA 3] Center 36 (8~64) winsize 57
6621 12:30:06.577473 [CA 4] Center 36 (8~64) winsize 57
6622 12:30:06.580583 [CA 5] Center 36 (8~64) winsize 57
6623 12:30:06.580692
6624 12:30:06.583622 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6625 12:30:06.586944
6626 12:30:06.590435 [CATrainingPosCal] consider 1 rank data
6627 12:30:06.593407 u2DelayCellTimex100 = 270/100 ps
6628 12:30:06.596927 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:30:06.600420 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:30:06.603404 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:30:06.606995 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:30:06.609880 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:30:06.613400 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:30:06.613510
6635 12:30:06.616845 CA PerBit enable=1, Macro0, CA PI delay=36
6636 12:30:06.616957
6637 12:30:06.620202 [CBTSetCACLKResult] CA Dly = 36
6638 12:30:06.623451 CS Dly: 1 (0~32)
6639 12:30:06.623564 ==
6640 12:30:06.626816 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 12:30:06.629722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 12:30:06.629834 ==
6643 12:30:06.636624 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 12:30:06.642792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6645 12:30:06.646467 [CA 0] Center 36 (8~64) winsize 57
6646 12:30:06.646597 [CA 1] Center 36 (8~64) winsize 57
6647 12:30:06.649513 [CA 2] Center 36 (8~64) winsize 57
6648 12:30:06.653170 [CA 3] Center 36 (8~64) winsize 57
6649 12:30:06.656320 [CA 4] Center 36 (8~64) winsize 57
6650 12:30:06.659393 [CA 5] Center 36 (8~64) winsize 57
6651 12:30:06.659512
6652 12:30:06.662582 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6653 12:30:06.662690
6654 12:30:06.669316 [CATrainingPosCal] consider 2 rank data
6655 12:30:06.669441 u2DelayCellTimex100 = 270/100 ps
6656 12:30:06.675939 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:30:06.679714 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 12:30:06.682728 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 12:30:06.685924 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 12:30:06.689052 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 12:30:06.692161 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 12:30:06.692279
6663 12:30:06.695852 CA PerBit enable=1, Macro0, CA PI delay=36
6664 12:30:06.695988
6665 12:30:06.698757 [CBTSetCACLKResult] CA Dly = 36
6666 12:30:06.702440 CS Dly: 1 (0~32)
6667 12:30:06.702547
6668 12:30:06.705488 ----->DramcWriteLeveling(PI) begin...
6669 12:30:06.705605 ==
6670 12:30:06.708949 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 12:30:06.712403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 12:30:06.712490 ==
6673 12:30:06.715480 Write leveling (Byte 0): 40 => 8
6674 12:30:06.718496 Write leveling (Byte 1): 40 => 8
6675 12:30:06.722025 DramcWriteLeveling(PI) end<-----
6676 12:30:06.722129
6677 12:30:06.722224 ==
6678 12:30:06.725039 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 12:30:06.728283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 12:30:06.728385 ==
6681 12:30:06.731731 [Gating] SW mode calibration
6682 12:30:06.738252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6683 12:30:06.744704 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6684 12:30:06.748388 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 12:30:06.751435 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 12:30:06.758181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 12:30:06.761297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 12:30:06.768204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 12:30:06.771315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 12:30:06.774381 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 12:30:06.777788 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 12:30:06.784650 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 12:30:06.787708 Total UI for P1: 0, mck2ui 16
6694 12:30:06.791429 best dqsien dly found for B0: ( 0, 14, 24)
6695 12:30:06.794573 Total UI for P1: 0, mck2ui 16
6696 12:30:06.797626 best dqsien dly found for B1: ( 0, 14, 24)
6697 12:30:06.801204 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6698 12:30:06.804264 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6699 12:30:06.804349
6700 12:30:06.807390 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 12:30:06.811034 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 12:30:06.814454 [Gating] SW calibration Done
6703 12:30:06.814539 ==
6704 12:30:06.817442 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 12:30:06.821178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 12:30:06.821264 ==
6707 12:30:06.824191 RX Vref Scan: 0
6708 12:30:06.824275
6709 12:30:06.827666 RX Vref 0 -> 0, step: 1
6710 12:30:06.827750
6711 12:30:06.830512 RX Delay -410 -> 252, step: 16
6712 12:30:06.833806 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6713 12:30:06.837177 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6714 12:30:06.840491 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6715 12:30:06.847456 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6716 12:30:06.850434 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6717 12:30:06.853816 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6718 12:30:06.856783 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6719 12:30:06.863478 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6720 12:30:06.867133 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6721 12:30:06.870200 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6722 12:30:06.873422 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6723 12:30:06.880100 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6724 12:30:06.883178 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6725 12:30:06.886715 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6726 12:30:06.892964 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6727 12:30:06.896717 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6728 12:30:06.896801 ==
6729 12:30:06.899798 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 12:30:06.902809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 12:30:06.902902 ==
6732 12:30:06.906326 DQS Delay:
6733 12:30:06.906410 DQS0 = 51, DQS1 = 67
6734 12:30:06.909359 DQM Delay:
6735 12:30:06.909442 DQM0 = 13, DQM1 = 20
6736 12:30:06.909508 DQ Delay:
6737 12:30:06.913045 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6738 12:30:06.916656 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6739 12:30:06.919672 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6740 12:30:06.922795 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6741 12:30:06.922907
6742 12:30:06.923000
6743 12:30:06.923099 ==
6744 12:30:06.926456 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 12:30:06.933054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 12:30:06.933133 ==
6747 12:30:06.933233
6748 12:30:06.933324
6749 12:30:06.933419 TX Vref Scan disable
6750 12:30:06.935986 == TX Byte 0 ==
6751 12:30:06.939474 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 12:30:06.942381 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 12:30:06.945800 == TX Byte 1 ==
6754 12:30:06.949221 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 12:30:06.952293 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 12:30:06.952378 ==
6757 12:30:06.955954 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 12:30:06.962274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 12:30:06.962359 ==
6760 12:30:06.962425
6761 12:30:06.962507
6762 12:30:06.965867 TX Vref Scan disable
6763 12:30:06.965950 == TX Byte 0 ==
6764 12:30:06.969005 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 12:30:06.975794 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 12:30:06.975877 == TX Byte 1 ==
6767 12:30:06.978872 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 12:30:06.985723 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 12:30:06.985807
6770 12:30:06.985873 [DATLAT]
6771 12:30:06.985932 Freq=400, CH1 RK0
6772 12:30:06.985991
6773 12:30:06.988413 DATLAT Default: 0xf
6774 12:30:06.988496 0, 0xFFFF, sum = 0
6775 12:30:06.991676 1, 0xFFFF, sum = 0
6776 12:30:06.995343 2, 0xFFFF, sum = 0
6777 12:30:06.995448 3, 0xFFFF, sum = 0
6778 12:30:06.998466 4, 0xFFFF, sum = 0
6779 12:30:06.998552 5, 0xFFFF, sum = 0
6780 12:30:07.001567 6, 0xFFFF, sum = 0
6781 12:30:07.001651 7, 0xFFFF, sum = 0
6782 12:30:07.005301 8, 0xFFFF, sum = 0
6783 12:30:07.005383 9, 0xFFFF, sum = 0
6784 12:30:07.008325 10, 0xFFFF, sum = 0
6785 12:30:07.008404 11, 0xFFFF, sum = 0
6786 12:30:07.011992 12, 0xFFFF, sum = 0
6787 12:30:07.012095 13, 0x0, sum = 1
6788 12:30:07.015111 14, 0x0, sum = 2
6789 12:30:07.015196 15, 0x0, sum = 3
6790 12:30:07.018235 16, 0x0, sum = 4
6791 12:30:07.018313 best_step = 14
6792 12:30:07.018381
6793 12:30:07.018439 ==
6794 12:30:07.021258 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 12:30:07.027987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 12:30:07.028115 ==
6797 12:30:07.028233 RX Vref Scan: 1
6798 12:30:07.028350
6799 12:30:07.031139 RX Vref 0 -> 0, step: 1
6800 12:30:07.031260
6801 12:30:07.034796 RX Delay -375 -> 252, step: 8
6802 12:30:07.034952
6803 12:30:07.037951 Set Vref, RX VrefLevel [Byte0]: 57
6804 12:30:07.041463 [Byte1]: 48
6805 12:30:07.041582
6806 12:30:07.044519 Final RX Vref Byte 0 = 57 to rank0
6807 12:30:07.047987 Final RX Vref Byte 1 = 48 to rank0
6808 12:30:07.050788 Final RX Vref Byte 0 = 57 to rank1
6809 12:30:07.054185 Final RX Vref Byte 1 = 48 to rank1==
6810 12:30:07.057538 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 12:30:07.064344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 12:30:07.064472 ==
6813 12:30:07.064580 DQS Delay:
6814 12:30:07.067889 DQS0 = 56, DQS1 = 68
6815 12:30:07.068008 DQM Delay:
6816 12:30:07.068114 DQM0 = 13, DQM1 = 14
6817 12:30:07.070702 DQ Delay:
6818 12:30:07.074256 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6819 12:30:07.074375 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6820 12:30:07.077367 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6821 12:30:07.080580 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6822 12:30:07.080699
6823 12:30:07.083719
6824 12:30:07.090389 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6825 12:30:07.093999 CH1 RK0: MR19=C0C, MR18=5C6F
6826 12:30:07.100646 CH1_RK0: MR19=0xC0C, MR18=0x5C6F, DQSOSC=395, MR23=63, INC=378, DEC=252
6827 12:30:07.100767 ==
6828 12:30:07.103763 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 12:30:07.106839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 12:30:07.106992 ==
6831 12:30:07.110242 [Gating] SW mode calibration
6832 12:30:07.116599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6833 12:30:07.123387 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6834 12:30:07.126387 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 12:30:07.130107 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 12:30:07.136387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 12:30:07.139408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 12:30:07.143062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 12:30:07.149633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 12:30:07.152653 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 12:30:07.155893 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 12:30:07.162430 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 12:30:07.165776 Total UI for P1: 0, mck2ui 16
6844 12:30:07.169267 best dqsien dly found for B0: ( 0, 14, 24)
6845 12:30:07.172206 Total UI for P1: 0, mck2ui 16
6846 12:30:07.175906 best dqsien dly found for B1: ( 0, 14, 24)
6847 12:30:07.178982 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6848 12:30:07.182250 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6849 12:30:07.182367
6850 12:30:07.185741 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 12:30:07.188922 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 12:30:07.192074 [Gating] SW calibration Done
6853 12:30:07.192191 ==
6854 12:30:07.195974 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 12:30:07.198862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 12:30:07.198996 ==
6857 12:30:07.202364 RX Vref Scan: 0
6858 12:30:07.202478
6859 12:30:07.205447 RX Vref 0 -> 0, step: 1
6860 12:30:07.205563
6861 12:30:07.208674 RX Delay -410 -> 252, step: 16
6862 12:30:07.211833 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6863 12:30:07.215484 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6864 12:30:07.218422 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6865 12:30:07.225270 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6866 12:30:07.228388 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6867 12:30:07.231830 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6868 12:30:07.234866 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6869 12:30:07.241852 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6870 12:30:07.245013 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6871 12:30:07.248144 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6872 12:30:07.251257 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6873 12:30:07.257876 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6874 12:30:07.261455 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6875 12:30:07.264341 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6876 12:30:07.271164 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6877 12:30:07.274454 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6878 12:30:07.274570 ==
6879 12:30:07.277992 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 12:30:07.281066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 12:30:07.281234 ==
6882 12:30:07.284676 DQS Delay:
6883 12:30:07.284837 DQS0 = 59, DQS1 = 59
6884 12:30:07.287526 DQM Delay:
6885 12:30:07.287665 DQM0 = 19, DQM1 = 12
6886 12:30:07.287777 DQ Delay:
6887 12:30:07.291011 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6888 12:30:07.294148 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6889 12:30:07.297886 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6890 12:30:07.300981 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6891 12:30:07.301102
6892 12:30:07.301204
6893 12:30:07.301308 ==
6894 12:30:07.304001 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 12:30:07.310671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 12:30:07.310791 ==
6897 12:30:07.310908
6898 12:30:07.311008
6899 12:30:07.311108 TX Vref Scan disable
6900 12:30:07.314356 == TX Byte 0 ==
6901 12:30:07.317403 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6902 12:30:07.320410 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6903 12:30:07.323964 == TX Byte 1 ==
6904 12:30:07.327237 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6905 12:30:07.330290 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6906 12:30:07.333826 ==
6907 12:30:07.333947 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 12:30:07.340341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 12:30:07.340458 ==
6910 12:30:07.340568
6911 12:30:07.340671
6912 12:30:07.343997 TX Vref Scan disable
6913 12:30:07.344108 == TX Byte 0 ==
6914 12:30:07.347086 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6915 12:30:07.353263 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6916 12:30:07.353381 == TX Byte 1 ==
6917 12:30:07.356900 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6918 12:30:07.363547 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6919 12:30:07.363630
6920 12:30:07.363696 [DATLAT]
6921 12:30:07.363795 Freq=400, CH1 RK1
6922 12:30:07.363855
6923 12:30:07.366674 DATLAT Default: 0xe
6924 12:30:07.366798 0, 0xFFFF, sum = 0
6925 12:30:07.370204 1, 0xFFFF, sum = 0
6926 12:30:07.370287 2, 0xFFFF, sum = 0
6927 12:30:07.373523 3, 0xFFFF, sum = 0
6928 12:30:07.376516 4, 0xFFFF, sum = 0
6929 12:30:07.376599 5, 0xFFFF, sum = 0
6930 12:30:07.379964 6, 0xFFFF, sum = 0
6931 12:30:07.380048 7, 0xFFFF, sum = 0
6932 12:30:07.383340 8, 0xFFFF, sum = 0
6933 12:30:07.383423 9, 0xFFFF, sum = 0
6934 12:30:07.387071 10, 0xFFFF, sum = 0
6935 12:30:07.387160 11, 0xFFFF, sum = 0
6936 12:30:07.389868 12, 0xFFFF, sum = 0
6937 12:30:07.389951 13, 0x0, sum = 1
6938 12:30:07.392912 14, 0x0, sum = 2
6939 12:30:07.392996 15, 0x0, sum = 3
6940 12:30:07.396324 16, 0x0, sum = 4
6941 12:30:07.396407 best_step = 14
6942 12:30:07.396472
6943 12:30:07.396532 ==
6944 12:30:07.400024 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 12:30:07.403184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 12:30:07.406145 ==
6947 12:30:07.406227 RX Vref Scan: 0
6948 12:30:07.406292
6949 12:30:07.409843 RX Vref 0 -> 0, step: 1
6950 12:30:07.409926
6951 12:30:07.412900 RX Delay -359 -> 252, step: 8
6952 12:30:07.419705 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6953 12:30:07.423088 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6954 12:30:07.426061 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6955 12:30:07.429690 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6956 12:30:07.435870 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6957 12:30:07.439475 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6958 12:30:07.442382 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6959 12:30:07.446076 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6960 12:30:07.452273 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6961 12:30:07.456015 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6962 12:30:07.459052 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6963 12:30:07.462198 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6964 12:30:07.468918 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6965 12:30:07.472012 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6966 12:30:07.475615 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6967 12:30:07.482169 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6968 12:30:07.482279 ==
6969 12:30:07.485641 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 12:30:07.488493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 12:30:07.488576 ==
6972 12:30:07.488642 DQS Delay:
6973 12:30:07.492187 DQS0 = 60, DQS1 = 64
6974 12:30:07.492270 DQM Delay:
6975 12:30:07.495291 DQM0 = 12, DQM1 = 10
6976 12:30:07.495373 DQ Delay:
6977 12:30:07.498815 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6978 12:30:07.501700 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6979 12:30:07.505408 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6980 12:30:07.508534 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6981 12:30:07.508616
6982 12:30:07.508682
6983 12:30:07.515292 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6984 12:30:07.518226 CH1 RK1: MR19=C0C, MR18=75A7
6985 12:30:07.524803 CH1_RK1: MR19=0xC0C, MR18=0x75A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6986 12:30:07.528459 [RxdqsGatingPostProcess] freq 400
6987 12:30:07.535008 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6988 12:30:07.538001 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 12:30:07.538072 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 12:30:07.541174 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 12:30:07.544833 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 12:30:07.547803 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 12:30:07.551646 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 12:30:07.554523 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 12:30:07.557724 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 12:30:07.561425 Pre-setting of DQS Precalculation
6997 12:30:07.567445 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6998 12:30:07.574297 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6999 12:30:07.580800 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7000 12:30:07.580881
7001 12:30:07.580947
7002 12:30:07.584440 [Calibration Summary] 800 Mbps
7003 12:30:07.584520 CH 0, Rank 0
7004 12:30:07.587462 SW Impedance : PASS
7005 12:30:07.591122 DUTY Scan : NO K
7006 12:30:07.591223 ZQ Calibration : PASS
7007 12:30:07.593903 Jitter Meter : NO K
7008 12:30:07.597249 CBT Training : PASS
7009 12:30:07.597384 Write leveling : PASS
7010 12:30:07.600455 RX DQS gating : PASS
7011 12:30:07.603945 RX DQ/DQS(RDDQC) : PASS
7012 12:30:07.604076 TX DQ/DQS : PASS
7013 12:30:07.607471 RX DATLAT : PASS
7014 12:30:07.610594 RX DQ/DQS(Engine): PASS
7015 12:30:07.610708 TX OE : NO K
7016 12:30:07.613612 All Pass.
7017 12:30:07.613714
7018 12:30:07.613809 CH 0, Rank 1
7019 12:30:07.617341 SW Impedance : PASS
7020 12:30:07.617448 DUTY Scan : NO K
7021 12:30:07.620513 ZQ Calibration : PASS
7022 12:30:07.623752 Jitter Meter : NO K
7023 12:30:07.623834 CBT Training : PASS
7024 12:30:07.627091 Write leveling : NO K
7025 12:30:07.630096 RX DQS gating : PASS
7026 12:30:07.630178 RX DQ/DQS(RDDQC) : PASS
7027 12:30:07.633653 TX DQ/DQS : PASS
7028 12:30:07.637119 RX DATLAT : PASS
7029 12:30:07.637201 RX DQ/DQS(Engine): PASS
7030 12:30:07.640162 TX OE : NO K
7031 12:30:07.640244 All Pass.
7032 12:30:07.640308
7033 12:30:07.643297 CH 1, Rank 0
7034 12:30:07.643379 SW Impedance : PASS
7035 12:30:07.646764 DUTY Scan : NO K
7036 12:30:07.646870 ZQ Calibration : PASS
7037 12:30:07.650370 Jitter Meter : NO K
7038 12:30:07.653539 CBT Training : PASS
7039 12:30:07.653621 Write leveling : PASS
7040 12:30:07.656711 RX DQS gating : PASS
7041 12:30:07.659797 RX DQ/DQS(RDDQC) : PASS
7042 12:30:07.659879 TX DQ/DQS : PASS
7043 12:30:07.663486 RX DATLAT : PASS
7044 12:30:07.666652 RX DQ/DQS(Engine): PASS
7045 12:30:07.666734 TX OE : NO K
7046 12:30:07.670274 All Pass.
7047 12:30:07.670357
7048 12:30:07.670422 CH 1, Rank 1
7049 12:30:07.673362 SW Impedance : PASS
7050 12:30:07.673443 DUTY Scan : NO K
7051 12:30:07.676649 ZQ Calibration : PASS
7052 12:30:07.679797 Jitter Meter : NO K
7053 12:30:07.679879 CBT Training : PASS
7054 12:30:07.683378 Write leveling : NO K
7055 12:30:07.686437 RX DQS gating : PASS
7056 12:30:07.686519 RX DQ/DQS(RDDQC) : PASS
7057 12:30:07.689775 TX DQ/DQS : PASS
7058 12:30:07.693248 RX DATLAT : PASS
7059 12:30:07.693330 RX DQ/DQS(Engine): PASS
7060 12:30:07.696769 TX OE : NO K
7061 12:30:07.696851 All Pass.
7062 12:30:07.696917
7063 12:30:07.699544 DramC Write-DBI off
7064 12:30:07.702981 PER_BANK_REFRESH: Hybrid Mode
7065 12:30:07.703063 TX_TRACKING: ON
7066 12:30:07.712922 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7067 12:30:07.716391 [FAST_K] Save calibration result to emmc
7068 12:30:07.719490 dramc_set_vcore_voltage set vcore to 725000
7069 12:30:07.722551 Read voltage for 1600, 0
7070 12:30:07.722660 Vio18 = 0
7071 12:30:07.722753 Vcore = 725000
7072 12:30:07.726347 Vdram = 0
7073 12:30:07.726428 Vddq = 0
7074 12:30:07.726494 Vmddr = 0
7075 12:30:07.732596 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7076 12:30:07.736141 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7077 12:30:07.739039 MEM_TYPE=3, freq_sel=13
7078 12:30:07.742686 sv_algorithm_assistance_LP4_3733
7079 12:30:07.745726 ============ PULL DRAM RESETB DOWN ============
7080 12:30:07.752437 ========== PULL DRAM RESETB DOWN end =========
7081 12:30:07.755469 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7082 12:30:07.758638 ===================================
7083 12:30:07.762353 LPDDR4 DRAM CONFIGURATION
7084 12:30:07.765384 ===================================
7085 12:30:07.765476 EX_ROW_EN[0] = 0x0
7086 12:30:07.768501 EX_ROW_EN[1] = 0x0
7087 12:30:07.768583 LP4Y_EN = 0x0
7088 12:30:07.772228 WORK_FSP = 0x1
7089 12:30:07.772311 WL = 0x5
7090 12:30:07.775329 RL = 0x5
7091 12:30:07.775415 BL = 0x2
7092 12:30:07.778470 RPST = 0x0
7093 12:30:07.778552 RD_PRE = 0x0
7094 12:30:07.782105 WR_PRE = 0x1
7095 12:30:07.785286 WR_PST = 0x1
7096 12:30:07.785388 DBI_WR = 0x0
7097 12:30:07.788279 DBI_RD = 0x0
7098 12:30:07.788399 OTF = 0x1
7099 12:30:07.792227 ===================================
7100 12:30:07.794974 ===================================
7101 12:30:07.798659 ANA top config
7102 12:30:07.801690 ===================================
7103 12:30:07.801784 DLL_ASYNC_EN = 0
7104 12:30:07.805249 ALL_SLAVE_EN = 0
7105 12:30:07.807980 NEW_RANK_MODE = 1
7106 12:30:07.811527 DLL_IDLE_MODE = 1
7107 12:30:07.811636 LP45_APHY_COMB_EN = 1
7108 12:30:07.814499 TX_ODT_DIS = 0
7109 12:30:07.817948 NEW_8X_MODE = 1
7110 12:30:07.821412 ===================================
7111 12:30:07.824866 ===================================
7112 12:30:07.827960 data_rate = 3200
7113 12:30:07.831213 CKR = 1
7114 12:30:07.834383 DQ_P2S_RATIO = 8
7115 12:30:07.838246 ===================================
7116 12:30:07.838328 CA_P2S_RATIO = 8
7117 12:30:07.840885 DQ_CA_OPEN = 0
7118 12:30:07.844445 DQ_SEMI_OPEN = 0
7119 12:30:07.847490 CA_SEMI_OPEN = 0
7120 12:30:07.851089 CA_FULL_RATE = 0
7121 12:30:07.854189 DQ_CKDIV4_EN = 0
7122 12:30:07.854272 CA_CKDIV4_EN = 0
7123 12:30:07.857792 CA_PREDIV_EN = 0
7124 12:30:07.860730 PH8_DLY = 12
7125 12:30:07.864348 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7126 12:30:07.867551 DQ_AAMCK_DIV = 4
7127 12:30:07.870746 CA_AAMCK_DIV = 4
7128 12:30:07.873903 CA_ADMCK_DIV = 4
7129 12:30:07.873986 DQ_TRACK_CA_EN = 0
7130 12:30:07.877489 CA_PICK = 1600
7131 12:30:07.880524 CA_MCKIO = 1600
7132 12:30:07.883699 MCKIO_SEMI = 0
7133 12:30:07.887400 PLL_FREQ = 3068
7134 12:30:07.890538 DQ_UI_PI_RATIO = 32
7135 12:30:07.893504 CA_UI_PI_RATIO = 0
7136 12:30:07.897482 ===================================
7137 12:30:07.900260 ===================================
7138 12:30:07.900343 memory_type:LPDDR4
7139 12:30:07.903823 GP_NUM : 10
7140 12:30:07.906805 SRAM_EN : 1
7141 12:30:07.906922 MD32_EN : 0
7142 12:30:07.910421 ===================================
7143 12:30:07.913288 [ANA_INIT] >>>>>>>>>>>>>>
7144 12:30:07.916716 <<<<<< [CONFIGURE PHASE]: ANA_TX
7145 12:30:07.920299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7146 12:30:07.923707 ===================================
7147 12:30:07.926374 data_rate = 3200,PCW = 0X7600
7148 12:30:07.929902 ===================================
7149 12:30:07.932965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7150 12:30:07.936531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 12:30:07.943398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 12:30:07.946420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7153 12:30:07.952747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7154 12:30:07.956338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7155 12:30:07.956423 [ANA_INIT] flow start
7156 12:30:07.959454 [ANA_INIT] PLL >>>>>>>>
7157 12:30:07.963079 [ANA_INIT] PLL <<<<<<<<
7158 12:30:07.963154 [ANA_INIT] MIDPI >>>>>>>>
7159 12:30:07.966251 [ANA_INIT] MIDPI <<<<<<<<
7160 12:30:07.969299 [ANA_INIT] DLL >>>>>>>>
7161 12:30:07.969371 [ANA_INIT] DLL <<<<<<<<
7162 12:30:07.972986 [ANA_INIT] flow end
7163 12:30:07.976199 ============ LP4 DIFF to SE enter ============
7164 12:30:07.979294 ============ LP4 DIFF to SE exit ============
7165 12:30:07.982912 [ANA_INIT] <<<<<<<<<<<<<
7166 12:30:07.986114 [Flow] Enable top DCM control >>>>>
7167 12:30:07.989206 [Flow] Enable top DCM control <<<<<
7168 12:30:07.992225 Enable DLL master slave shuffle
7169 12:30:07.998778 ==============================================================
7170 12:30:07.998889 Gating Mode config
7171 12:30:08.005519 ==============================================================
7172 12:30:08.009089 Config description:
7173 12:30:08.015663 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7174 12:30:08.021986 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7175 12:30:08.028724 SELPH_MODE 0: By rank 1: By Phase
7176 12:30:08.035656 ==============================================================
7177 12:30:08.035736 GAT_TRACK_EN = 1
7178 12:30:08.038520 RX_GATING_MODE = 2
7179 12:30:08.042222 RX_GATING_TRACK_MODE = 2
7180 12:30:08.045288 SELPH_MODE = 1
7181 12:30:08.048386 PICG_EARLY_EN = 1
7182 12:30:08.052035 VALID_LAT_VALUE = 1
7183 12:30:08.058378 ==============================================================
7184 12:30:08.061738 Enter into Gating configuration >>>>
7185 12:30:08.064753 Exit from Gating configuration <<<<
7186 12:30:08.068272 Enter into DVFS_PRE_config >>>>>
7187 12:30:08.078321 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7188 12:30:08.081263 Exit from DVFS_PRE_config <<<<<
7189 12:30:08.084979 Enter into PICG configuration >>>>
7190 12:30:08.088136 Exit from PICG configuration <<<<
7191 12:30:08.091341 [RX_INPUT] configuration >>>>>
7192 12:30:08.094976 [RX_INPUT] configuration <<<<<
7193 12:30:08.098165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7194 12:30:08.104790 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7195 12:30:08.111444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 12:30:08.118030 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 12:30:08.120979 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 12:30:08.127895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 12:30:08.134028 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7200 12:30:08.137808 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7201 12:30:08.140703 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7202 12:30:08.144290 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7203 12:30:08.147739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7204 12:30:08.154033 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 12:30:08.157210 ===================================
7206 12:30:08.160734 LPDDR4 DRAM CONFIGURATION
7207 12:30:08.163776 ===================================
7208 12:30:08.163858 EX_ROW_EN[0] = 0x0
7209 12:30:08.167242 EX_ROW_EN[1] = 0x0
7210 12:30:08.167327 LP4Y_EN = 0x0
7211 12:30:08.170606 WORK_FSP = 0x1
7212 12:30:08.170713 WL = 0x5
7213 12:30:08.173708 RL = 0x5
7214 12:30:08.173790 BL = 0x2
7215 12:30:08.177455 RPST = 0x0
7216 12:30:08.177536 RD_PRE = 0x0
7217 12:30:08.180527 WR_PRE = 0x1
7218 12:30:08.180608 WR_PST = 0x1
7219 12:30:08.183640 DBI_WR = 0x0
7220 12:30:08.186751 DBI_RD = 0x0
7221 12:30:08.186891 OTF = 0x1
7222 12:30:08.190397 ===================================
7223 12:30:08.193511 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7224 12:30:08.196686 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7225 12:30:08.203334 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 12:30:08.206946 ===================================
7227 12:30:08.209995 LPDDR4 DRAM CONFIGURATION
7228 12:30:08.213092 ===================================
7229 12:30:08.213175 EX_ROW_EN[0] = 0x10
7230 12:30:08.216762 EX_ROW_EN[1] = 0x0
7231 12:30:08.216845 LP4Y_EN = 0x0
7232 12:30:08.219755 WORK_FSP = 0x1
7233 12:30:08.219837 WL = 0x5
7234 12:30:08.223360 RL = 0x5
7235 12:30:08.223443 BL = 0x2
7236 12:30:08.226760 RPST = 0x0
7237 12:30:08.229993 RD_PRE = 0x0
7238 12:30:08.230081 WR_PRE = 0x1
7239 12:30:08.232753 WR_PST = 0x1
7240 12:30:08.232836 DBI_WR = 0x0
7241 12:30:08.236061 DBI_RD = 0x0
7242 12:30:08.236143 OTF = 0x1
7243 12:30:08.239796 ===================================
7244 12:30:08.246980 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7245 12:30:08.247064 ==
7246 12:30:08.249521 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 12:30:08.252961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7248 12:30:08.253048 ==
7249 12:30:08.256177 [Duty_Offset_Calibration]
7250 12:30:08.259731 B0:2 B1:0 CA:3
7251 12:30:08.259840
7252 12:30:08.262743 [DutyScan_Calibration_Flow] k_type=0
7253 12:30:08.271110
7254 12:30:08.271193 ==CLK 0==
7255 12:30:08.274158 Final CLK duty delay cell = 0
7256 12:30:08.277709 [0] MAX Duty = 5031%(X100), DQS PI = 12
7257 12:30:08.281092 [0] MIN Duty = 4907%(X100), DQS PI = 4
7258 12:30:08.281175 [0] AVG Duty = 4969%(X100)
7259 12:30:08.284093
7260 12:30:08.287875 CH0 CLK Duty spec in!! Max-Min= 124%
7261 12:30:08.291113 [DutyScan_Calibration_Flow] ====Done====
7262 12:30:08.291195
7263 12:30:08.294208 [DutyScan_Calibration_Flow] k_type=1
7264 12:30:08.310766
7265 12:30:08.310889 ==DQS 0 ==
7266 12:30:08.313892 Final DQS duty delay cell = 0
7267 12:30:08.317601 [0] MAX Duty = 5125%(X100), DQS PI = 30
7268 12:30:08.320766 [0] MIN Duty = 4875%(X100), DQS PI = 48
7269 12:30:08.323715 [0] AVG Duty = 5000%(X100)
7270 12:30:08.323798
7271 12:30:08.323862 ==DQS 1 ==
7272 12:30:08.327550 Final DQS duty delay cell = 0
7273 12:30:08.330746 [0] MAX Duty = 5156%(X100), DQS PI = 32
7274 12:30:08.333795 [0] MIN Duty = 5062%(X100), DQS PI = 8
7275 12:30:08.336766 [0] AVG Duty = 5109%(X100)
7276 12:30:08.336848
7277 12:30:08.340173 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7278 12:30:08.340255
7279 12:30:08.343740 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7280 12:30:08.347270 [DutyScan_Calibration_Flow] ====Done====
7281 12:30:08.347351
7282 12:30:08.350317 [DutyScan_Calibration_Flow] k_type=3
7283 12:30:08.368309
7284 12:30:08.368396 ==DQM 0 ==
7285 12:30:08.371884 Final DQM duty delay cell = 0
7286 12:30:08.374935 [0] MAX Duty = 5187%(X100), DQS PI = 32
7287 12:30:08.378653 [0] MIN Duty = 4875%(X100), DQS PI = 0
7288 12:30:08.381697 [0] AVG Duty = 5031%(X100)
7289 12:30:08.381783
7290 12:30:08.381850 ==DQM 1 ==
7291 12:30:08.385134 Final DQM duty delay cell = 4
7292 12:30:08.388151 [4] MAX Duty = 5187%(X100), DQS PI = 60
7293 12:30:08.391463 [4] MIN Duty = 5031%(X100), DQS PI = 12
7294 12:30:08.395223 [4] AVG Duty = 5109%(X100)
7295 12:30:08.395339
7296 12:30:08.398414 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7297 12:30:08.398559
7298 12:30:08.401577 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7299 12:30:08.404787 [DutyScan_Calibration_Flow] ====Done====
7300 12:30:08.404927
7301 12:30:08.408119 [DutyScan_Calibration_Flow] k_type=2
7302 12:30:08.424358
7303 12:30:08.424442 ==DQ 0 ==
7304 12:30:08.428167 Final DQ duty delay cell = -4
7305 12:30:08.431103 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7306 12:30:08.434318 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7307 12:30:08.437840 [-4] AVG Duty = 4938%(X100)
7308 12:30:08.437920
7309 12:30:08.437984 ==DQ 1 ==
7310 12:30:08.441508 Final DQ duty delay cell = 0
7311 12:30:08.444340 [0] MAX Duty = 5156%(X100), DQS PI = 58
7312 12:30:08.447826 [0] MIN Duty = 5000%(X100), DQS PI = 16
7313 12:30:08.451336 [0] AVG Duty = 5078%(X100)
7314 12:30:08.451449
7315 12:30:08.454353 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7316 12:30:08.454463
7317 12:30:08.457576 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7318 12:30:08.460695 [DutyScan_Calibration_Flow] ====Done====
7319 12:30:08.460803 ==
7320 12:30:08.464530 Dram Type= 6, Freq= 0, CH_1, rank 0
7321 12:30:08.467637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7322 12:30:08.467723 ==
7323 12:30:08.470733 [Duty_Offset_Calibration]
7324 12:30:08.470804 B0:1 B1:-2 CA:1
7325 12:30:08.470879
7326 12:30:08.473821 [DutyScan_Calibration_Flow] k_type=0
7327 12:30:08.485168
7328 12:30:08.485282 ==CLK 0==
7329 12:30:08.488285 Final CLK duty delay cell = 0
7330 12:30:08.491529 [0] MAX Duty = 5062%(X100), DQS PI = 20
7331 12:30:08.495228 [0] MIN Duty = 4844%(X100), DQS PI = 58
7332 12:30:08.498435 [0] AVG Duty = 4953%(X100)
7333 12:30:08.498511
7334 12:30:08.501717 CH1 CLK Duty spec in!! Max-Min= 218%
7335 12:30:08.504965 [DutyScan_Calibration_Flow] ====Done====
7336 12:30:08.505048
7337 12:30:08.508203 [DutyScan_Calibration_Flow] k_type=1
7338 12:30:08.524163
7339 12:30:08.524249 ==DQS 0 ==
7340 12:30:08.527366 Final DQS duty delay cell = -4
7341 12:30:08.530590 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7342 12:30:08.533883 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7343 12:30:08.536942 [-4] AVG Duty = 4906%(X100)
7344 12:30:08.537027
7345 12:30:08.537094 ==DQS 1 ==
7346 12:30:08.540100 Final DQS duty delay cell = 0
7347 12:30:08.543801 [0] MAX Duty = 5093%(X100), DQS PI = 60
7348 12:30:08.546704 [0] MIN Duty = 4844%(X100), DQS PI = 24
7349 12:30:08.550226 [0] AVG Duty = 4968%(X100)
7350 12:30:08.550312
7351 12:30:08.553756 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7352 12:30:08.553840
7353 12:30:08.556810 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7354 12:30:08.559914 [DutyScan_Calibration_Flow] ====Done====
7355 12:30:08.560002
7356 12:30:08.563105 [DutyScan_Calibration_Flow] k_type=3
7357 12:30:08.581287
7358 12:30:08.581372 ==DQM 0 ==
7359 12:30:08.584300 Final DQM duty delay cell = 0
7360 12:30:08.587907 [0] MAX Duty = 5031%(X100), DQS PI = 24
7361 12:30:08.590965 [0] MIN Duty = 4813%(X100), DQS PI = 54
7362 12:30:08.594115 [0] AVG Duty = 4922%(X100)
7363 12:30:08.594199
7364 12:30:08.594266 ==DQM 1 ==
7365 12:30:08.597811 Final DQM duty delay cell = 0
7366 12:30:08.600755 [0] MAX Duty = 5062%(X100), DQS PI = 34
7367 12:30:08.604595 [0] MIN Duty = 4875%(X100), DQS PI = 24
7368 12:30:08.607370 [0] AVG Duty = 4968%(X100)
7369 12:30:08.607454
7370 12:30:08.610413 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7371 12:30:08.610497
7372 12:30:08.614137 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7373 12:30:08.617532 [DutyScan_Calibration_Flow] ====Done====
7374 12:30:08.617616
7375 12:30:08.620272 [DutyScan_Calibration_Flow] k_type=2
7376 12:30:08.637769
7377 12:30:08.637856 ==DQ 0 ==
7378 12:30:08.641360 Final DQ duty delay cell = 0
7379 12:30:08.644334 [0] MAX Duty = 5124%(X100), DQS PI = 22
7380 12:30:08.647972 [0] MIN Duty = 4938%(X100), DQS PI = 0
7381 12:30:08.648083 [0] AVG Duty = 5031%(X100)
7382 12:30:08.651080
7383 12:30:08.651196 ==DQ 1 ==
7384 12:30:08.654667 Final DQ duty delay cell = 0
7385 12:30:08.657636 [0] MAX Duty = 5125%(X100), DQS PI = 34
7386 12:30:08.661128 [0] MIN Duty = 4938%(X100), DQS PI = 24
7387 12:30:08.661235 [0] AVG Duty = 5031%(X100)
7388 12:30:08.664075
7389 12:30:08.667854 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7390 12:30:08.667969
7391 12:30:08.671086 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7392 12:30:08.674014 [DutyScan_Calibration_Flow] ====Done====
7393 12:30:08.677519 nWR fixed to 30
7394 12:30:08.677627 [ModeRegInit_LP4] CH0 RK0
7395 12:30:08.680637 [ModeRegInit_LP4] CH0 RK1
7396 12:30:08.684264 [ModeRegInit_LP4] CH1 RK0
7397 12:30:08.687338 [ModeRegInit_LP4] CH1 RK1
7398 12:30:08.687449 match AC timing 5
7399 12:30:08.694203 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7400 12:30:08.697314 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7401 12:30:08.700440 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7402 12:30:08.707025 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7403 12:30:08.710763 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7404 12:30:08.710903 [MiockJmeterHQA]
7405 12:30:08.710976
7406 12:30:08.713663 [DramcMiockJmeter] u1RxGatingPI = 0
7407 12:30:08.716881 0 : 4255, 4029
7408 12:30:08.716967 4 : 4257, 4029
7409 12:30:08.720007 8 : 4257, 4029
7410 12:30:08.720088 12 : 4260, 4032
7411 12:30:08.723260 16 : 4255, 4030
7412 12:30:08.723339 20 : 4255, 4029
7413 12:30:08.723406 24 : 4257, 4029
7414 12:30:08.726918 28 : 4255, 4029
7415 12:30:08.727002 32 : 4255, 4029
7416 12:30:08.729878 36 : 4255, 4029
7417 12:30:08.729987 40 : 4366, 4139
7418 12:30:08.733103 44 : 4366, 4140
7419 12:30:08.733222 48 : 4252, 4029
7420 12:30:08.736911 52 : 4254, 4030
7421 12:30:08.737036 56 : 4255, 4029
7422 12:30:08.737138 60 : 4365, 4140
7423 12:30:08.740238 64 : 4254, 4029
7424 12:30:08.740348 68 : 4252, 4030
7425 12:30:08.743332 72 : 4255, 4029
7426 12:30:08.743447 76 : 4368, 4143
7427 12:30:08.746423 80 : 4252, 4030
7428 12:30:08.746526 84 : 4258, 4032
7429 12:30:08.750088 88 : 4255, 4029
7430 12:30:08.750199 92 : 4252, 4029
7431 12:30:08.750294 96 : 4258, 4032
7432 12:30:08.753145 100 : 4366, 4140
7433 12:30:08.753254 104 : 4252, 4009
7434 12:30:08.756103 108 : 4252, 30
7435 12:30:08.756207 112 : 4365, 0
7436 12:30:08.759879 116 : 4250, 0
7437 12:30:08.759954 120 : 4252, 0
7438 12:30:08.760033 124 : 4365, 0
7439 12:30:08.762894 128 : 4252, 0
7440 12:30:08.762968 132 : 4252, 0
7441 12:30:08.766223 136 : 4363, 0
7442 12:30:08.766324 140 : 4252, 0
7443 12:30:08.766423 144 : 4252, 0
7444 12:30:08.769674 148 : 4252, 0
7445 12:30:08.769784 152 : 4363, 0
7446 12:30:08.772730 156 : 4366, 0
7447 12:30:08.772842 160 : 4252, 0
7448 12:30:08.772938 164 : 4252, 0
7449 12:30:08.776283 168 : 4368, 0
7450 12:30:08.776374 172 : 4253, 0
7451 12:30:08.779300 176 : 4255, 0
7452 12:30:08.779376 180 : 4255, 0
7453 12:30:08.779449 184 : 4258, 0
7454 12:30:08.782886 188 : 4363, 0
7455 12:30:08.782994 192 : 4253, 0
7456 12:30:08.783062 196 : 4255, 0
7457 12:30:08.785768 200 : 4363, 0
7458 12:30:08.785868 204 : 4363, 0
7459 12:30:08.789422 208 : 4249, 0
7460 12:30:08.789529 212 : 4363, 0
7461 12:30:08.789624 216 : 4252, 0
7462 12:30:08.792629 220 : 4255, 0
7463 12:30:08.792733 224 : 4255, 0
7464 12:30:08.795707 228 : 4253, 0
7465 12:30:08.795779 232 : 4255, 0
7466 12:30:08.795841 236 : 4252, 331
7467 12:30:08.799418 240 : 4365, 4140
7468 12:30:08.799492 244 : 4365, 4139
7469 12:30:08.802468 248 : 4252, 4029
7470 12:30:08.802566 252 : 4255, 4029
7471 12:30:08.805627 256 : 4255, 4029
7472 12:30:08.805730 260 : 4254, 4030
7473 12:30:08.809268 264 : 4253, 4030
7474 12:30:08.809380 268 : 4258, 4032
7475 12:30:08.812326 272 : 4255, 4029
7476 12:30:08.812401 276 : 4252, 4030
7477 12:30:08.816032 280 : 4365, 4140
7478 12:30:08.816140 284 : 4255, 4029
7479 12:30:08.819042 288 : 4255, 4030
7480 12:30:08.819124 292 : 4250, 4027
7481 12:30:08.822013 296 : 4252, 4030
7482 12:30:08.822118 300 : 4255, 4029
7483 12:30:08.822185 304 : 4257, 4032
7484 12:30:08.825623 308 : 4255, 4029
7485 12:30:08.825725 312 : 4365, 4140
7486 12:30:08.828662 316 : 4252, 4029
7487 12:30:08.828772 320 : 4252, 4030
7488 12:30:08.832382 324 : 4252, 4029
7489 12:30:08.832457 328 : 4255, 4029
7490 12:30:08.835500 332 : 4255, 4029
7491 12:30:08.835579 336 : 4255, 4029
7492 12:30:08.838675 340 : 4258, 4032
7493 12:30:08.838782 344 : 4252, 4029
7494 12:30:08.841820 348 : 4249, 4027
7495 12:30:08.841925 352 : 4253, 4026
7496 12:30:08.845418 356 : 4257, 3197
7497 12:30:08.845517 360 : 4365, 0
7498 12:30:08.845617
7499 12:30:08.848536 MIOCK jitter meter ch=0
7500 12:30:08.848632
7501 12:30:08.852061 1T = (360-108) = 252 dly cells
7502 12:30:08.855039 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7503 12:30:08.855112 ==
7504 12:30:08.858756 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 12:30:08.865059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 12:30:08.865160 ==
7507 12:30:08.868161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 12:30:08.874960 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 12:30:08.878588 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 12:30:08.884967 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 12:30:08.892575 [CA 0] Center 44 (14~75) winsize 62
7512 12:30:08.896230 [CA 1] Center 43 (13~74) winsize 62
7513 12:30:08.899270 [CA 2] Center 40 (11~69) winsize 59
7514 12:30:08.902379 [CA 3] Center 39 (10~68) winsize 59
7515 12:30:08.906162 [CA 4] Center 37 (8~67) winsize 60
7516 12:30:08.909238 [CA 5] Center 37 (7~67) winsize 61
7517 12:30:08.909355
7518 12:30:08.912810 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 12:30:08.912904
7520 12:30:08.919099 [CATrainingPosCal] consider 1 rank data
7521 12:30:08.919187 u2DelayCellTimex100 = 258/100 ps
7522 12:30:08.925429 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7523 12:30:08.928850 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7524 12:30:08.931885 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7525 12:30:08.935692 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 12:30:08.938805 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7527 12:30:08.942106 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 12:30:08.942211
7529 12:30:08.945327 CA PerBit enable=1, Macro0, CA PI delay=37
7530 12:30:08.948568
7531 12:30:08.948699 [CBTSetCACLKResult] CA Dly = 37
7532 12:30:08.951730 CS Dly: 11 (0~42)
7533 12:30:08.955022 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 12:30:08.961768 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 12:30:08.961901 ==
7536 12:30:08.964963 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 12:30:08.968261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 12:30:08.968369 ==
7539 12:30:08.975166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 12:30:08.978008 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 12:30:08.981634 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 12:30:08.987703 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 12:30:08.996799 [CA 0] Center 44 (13~75) winsize 63
7544 12:30:08.999793 [CA 1] Center 43 (13~74) winsize 62
7545 12:30:09.003325 [CA 2] Center 39 (10~69) winsize 60
7546 12:30:09.006287 [CA 3] Center 39 (10~68) winsize 59
7547 12:30:09.010040 [CA 4] Center 37 (8~67) winsize 60
7548 12:30:09.013222 [CA 5] Center 36 (7~66) winsize 60
7549 12:30:09.013311
7550 12:30:09.016335 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 12:30:09.016448
7552 12:30:09.022653 [CATrainingPosCal] consider 2 rank data
7553 12:30:09.022790 u2DelayCellTimex100 = 258/100 ps
7554 12:30:09.030055 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7555 12:30:09.033132 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7556 12:30:09.036273 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7557 12:30:09.039480 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7558 12:30:09.042604 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7559 12:30:09.045778 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7560 12:30:09.045880
7561 12:30:09.049650 CA PerBit enable=1, Macro0, CA PI delay=36
7562 12:30:09.052840
7563 12:30:09.052950 [CBTSetCACLKResult] CA Dly = 36
7564 12:30:09.056115 CS Dly: 11 (0~43)
7565 12:30:09.059161 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 12:30:09.062299 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 12:30:09.062400
7568 12:30:09.068953 ----->DramcWriteLeveling(PI) begin...
7569 12:30:09.069069 ==
7570 12:30:09.072104 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 12:30:09.075526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 12:30:09.075627 ==
7573 12:30:09.078652 Write leveling (Byte 0): 37 => 37
7574 12:30:09.082471 Write leveling (Byte 1): 26 => 26
7575 12:30:09.085405 DramcWriteLeveling(PI) end<-----
7576 12:30:09.085502
7577 12:30:09.085570 ==
7578 12:30:09.088850 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 12:30:09.091898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 12:30:09.092005 ==
7581 12:30:09.095381 [Gating] SW mode calibration
7582 12:30:09.102048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 12:30:09.108800 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 12:30:09.111955 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 12:30:09.115343 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 12:30:09.121505 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 12:30:09.124960 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 12:30:09.128679 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
7589 12:30:09.134886 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7590 12:30:09.138506 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7591 12:30:09.141569 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 12:30:09.148262 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 12:30:09.151462 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 12:30:09.154637 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 12:30:09.161361 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7596 12:30:09.165116 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7597 12:30:09.168004 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7598 12:30:09.174734 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7599 12:30:09.177837 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 12:30:09.181557 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 12:30:09.188219 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 12:30:09.191241 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:30:09.194395 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:30:09.200740 1 6 16 | B1->B0 | 2323 3838 | 0 1 | (0 0) (1 1)
7605 12:30:09.204434 1 6 20 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
7606 12:30:09.207494 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7607 12:30:09.214202 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 12:30:09.217809 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 12:30:09.220835 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 12:30:09.227360 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:30:09.230986 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:30:09.234001 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 12:30:09.240824 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7614 12:30:09.243959 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 12:30:09.247574 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 12:30:09.254022 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 12:30:09.257166 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 12:30:09.260334 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:30:09.267039 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:30:09.270123 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:30:09.273545 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:30:09.280336 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:30:09.283405 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:30:09.287259 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:30:09.293448 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:30:09.296636 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:30:09.299801 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:30:09.306682 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 12:30:09.309719 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 12:30:09.312836 Total UI for P1: 0, mck2ui 16
7631 12:30:09.316447 best dqsien dly found for B0: ( 1, 9, 16)
7632 12:30:09.319530 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 12:30:09.325996 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 12:30:09.326111 Total UI for P1: 0, mck2ui 16
7635 12:30:09.332746 best dqsien dly found for B1: ( 1, 9, 22)
7636 12:30:09.335836 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7637 12:30:09.339552 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7638 12:30:09.339630
7639 12:30:09.342534 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7640 12:30:09.345703 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7641 12:30:09.349362 [Gating] SW calibration Done
7642 12:30:09.349438 ==
7643 12:30:09.352576 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:30:09.355867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:30:09.355983 ==
7646 12:30:09.358918 RX Vref Scan: 0
7647 12:30:09.359032
7648 12:30:09.362125 RX Vref 0 -> 0, step: 1
7649 12:30:09.362211
7650 12:30:09.362279 RX Delay 0 -> 252, step: 8
7651 12:30:09.369132 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7652 12:30:09.372172 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7653 12:30:09.375307 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7654 12:30:09.378742 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7655 12:30:09.381747 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7656 12:30:09.388602 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7657 12:30:09.392220 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7658 12:30:09.395113 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7659 12:30:09.398473 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7660 12:30:09.401551 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7661 12:30:09.408295 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7662 12:30:09.411406 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7663 12:30:09.415002 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7664 12:30:09.417986 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7665 12:30:09.425169 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 12:30:09.428293 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7667 12:30:09.428379 ==
7668 12:30:09.431685 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 12:30:09.434703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 12:30:09.434817 ==
7671 12:30:09.437867 DQS Delay:
7672 12:30:09.437952 DQS0 = 0, DQS1 = 0
7673 12:30:09.438020 DQM Delay:
7674 12:30:09.441733 DQM0 = 128, DQM1 = 123
7675 12:30:09.441817 DQ Delay:
7676 12:30:09.444766 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7677 12:30:09.447809 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =143
7678 12:30:09.451472 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7679 12:30:09.457717 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7680 12:30:09.457807
7681 12:30:09.457873
7682 12:30:09.457936 ==
7683 12:30:09.461346 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 12:30:09.464490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 12:30:09.464575 ==
7686 12:30:09.464641
7687 12:30:09.464702
7688 12:30:09.467672 TX Vref Scan disable
7689 12:30:09.467755 == TX Byte 0 ==
7690 12:30:09.474332 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7691 12:30:09.477341 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7692 12:30:09.481381 == TX Byte 1 ==
7693 12:30:09.484177 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7694 12:30:09.487756 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7695 12:30:09.487842 ==
7696 12:30:09.490778 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 12:30:09.493851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 12:30:09.497326 ==
7699 12:30:09.510772
7700 12:30:09.513873 TX Vref early break, caculate TX vref
7701 12:30:09.517522 TX Vref=16, minBit 8, minWin=21, winSum=368
7702 12:30:09.520479 TX Vref=18, minBit 11, minWin=21, winSum=376
7703 12:30:09.524266 TX Vref=20, minBit 8, minWin=23, winSum=387
7704 12:30:09.527294 TX Vref=22, minBit 8, minWin=23, winSum=395
7705 12:30:09.533465 TX Vref=24, minBit 8, minWin=23, winSum=400
7706 12:30:09.536982 TX Vref=26, minBit 8, minWin=24, winSum=409
7707 12:30:09.540230 TX Vref=28, minBit 8, minWin=23, winSum=409
7708 12:30:09.543472 TX Vref=30, minBit 8, minWin=23, winSum=405
7709 12:30:09.547244 TX Vref=32, minBit 8, minWin=22, winSum=392
7710 12:30:09.550415 TX Vref=34, minBit 8, minWin=22, winSum=389
7711 12:30:09.556749 TX Vref=36, minBit 9, minWin=20, winSum=376
7712 12:30:09.559926 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 26
7713 12:30:09.560014
7714 12:30:09.563507 Final TX Range 0 Vref 26
7715 12:30:09.563590
7716 12:30:09.563664 ==
7717 12:30:09.566706 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 12:30:09.569868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 12:30:09.573485 ==
7720 12:30:09.573565
7721 12:30:09.573628
7722 12:30:09.573689 TX Vref Scan disable
7723 12:30:09.580050 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7724 12:30:09.580246 == TX Byte 0 ==
7725 12:30:09.583223 u2DelayCellOfst[0]=11 cells (3 PI)
7726 12:30:09.587033 u2DelayCellOfst[1]=15 cells (4 PI)
7727 12:30:09.589913 u2DelayCellOfst[2]=7 cells (2 PI)
7728 12:30:09.593680 u2DelayCellOfst[3]=11 cells (3 PI)
7729 12:30:09.597047 u2DelayCellOfst[4]=7 cells (2 PI)
7730 12:30:09.600281 u2DelayCellOfst[5]=0 cells (0 PI)
7731 12:30:09.603539 u2DelayCellOfst[6]=15 cells (4 PI)
7732 12:30:09.606702 u2DelayCellOfst[7]=15 cells (4 PI)
7733 12:30:09.609751 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7734 12:30:09.613445 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7735 12:30:09.616583 == TX Byte 1 ==
7736 12:30:09.619690 u2DelayCellOfst[8]=0 cells (0 PI)
7737 12:30:09.622755 u2DelayCellOfst[9]=3 cells (1 PI)
7738 12:30:09.626421 u2DelayCellOfst[10]=11 cells (3 PI)
7739 12:30:09.629377 u2DelayCellOfst[11]=7 cells (2 PI)
7740 12:30:09.633116 u2DelayCellOfst[12]=15 cells (4 PI)
7741 12:30:09.636216 u2DelayCellOfst[13]=15 cells (4 PI)
7742 12:30:09.639431 u2DelayCellOfst[14]=18 cells (5 PI)
7743 12:30:09.643147 u2DelayCellOfst[15]=15 cells (4 PI)
7744 12:30:09.646327 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7745 12:30:09.649599 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7746 12:30:09.652852 DramC Write-DBI on
7747 12:30:09.652970 ==
7748 12:30:09.655944 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 12:30:09.659385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 12:30:09.659502 ==
7751 12:30:09.659572
7752 12:30:09.659633
7753 12:30:09.662554 TX Vref Scan disable
7754 12:30:09.665810 == TX Byte 0 ==
7755 12:30:09.668905 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7756 12:30:09.668990 == TX Byte 1 ==
7757 12:30:09.675973 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7758 12:30:09.676089 DramC Write-DBI off
7759 12:30:09.676158
7760 12:30:09.676221 [DATLAT]
7761 12:30:09.679159 Freq=1600, CH0 RK0
7762 12:30:09.679271
7763 12:30:09.682231 DATLAT Default: 0xf
7764 12:30:09.682334 0, 0xFFFF, sum = 0
7765 12:30:09.685841 1, 0xFFFF, sum = 0
7766 12:30:09.685944 2, 0xFFFF, sum = 0
7767 12:30:09.688853 3, 0xFFFF, sum = 0
7768 12:30:09.688964 4, 0xFFFF, sum = 0
7769 12:30:09.692001 5, 0xFFFF, sum = 0
7770 12:30:09.692116 6, 0xFFFF, sum = 0
7771 12:30:09.695833 7, 0xFFFF, sum = 0
7772 12:30:09.695955 8, 0xFFFF, sum = 0
7773 12:30:09.699119 9, 0xFFFF, sum = 0
7774 12:30:09.699235 10, 0xFFFF, sum = 0
7775 12:30:09.702181 11, 0xFFFF, sum = 0
7776 12:30:09.702294 12, 0xFFFF, sum = 0
7777 12:30:09.705222 13, 0xCFFF, sum = 0
7778 12:30:09.705304 14, 0x0, sum = 1
7779 12:30:09.709035 15, 0x0, sum = 2
7780 12:30:09.709122 16, 0x0, sum = 3
7781 12:30:09.712078 17, 0x0, sum = 4
7782 12:30:09.712163 best_step = 15
7783 12:30:09.712230
7784 12:30:09.712292 ==
7785 12:30:09.715692 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 12:30:09.721834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 12:30:09.721929 ==
7788 12:30:09.721997 RX Vref Scan: 1
7789 12:30:09.722059
7790 12:30:09.725329 Set Vref Range= 24 -> 127
7791 12:30:09.725477
7792 12:30:09.728444 RX Vref 24 -> 127, step: 1
7793 12:30:09.728603
7794 12:30:09.731482 RX Delay 11 -> 252, step: 4
7795 12:30:09.731569
7796 12:30:09.734949 Set Vref, RX VrefLevel [Byte0]: 24
7797 12:30:09.737978 [Byte1]: 24
7798 12:30:09.738081
7799 12:30:09.741728 Set Vref, RX VrefLevel [Byte0]: 25
7800 12:30:09.744720 [Byte1]: 25
7801 12:30:09.744839
7802 12:30:09.747846 Set Vref, RX VrefLevel [Byte0]: 26
7803 12:30:09.751092 [Byte1]: 26
7804 12:30:09.754769
7805 12:30:09.754894 Set Vref, RX VrefLevel [Byte0]: 27
7806 12:30:09.757871 [Byte1]: 27
7807 12:30:09.762346
7808 12:30:09.762432 Set Vref, RX VrefLevel [Byte0]: 28
7809 12:30:09.765611 [Byte1]: 28
7810 12:30:09.769903
7811 12:30:09.770001 Set Vref, RX VrefLevel [Byte0]: 29
7812 12:30:09.773103 [Byte1]: 29
7813 12:30:09.777681
7814 12:30:09.777761 Set Vref, RX VrefLevel [Byte0]: 30
7815 12:30:09.783886 [Byte1]: 30
7816 12:30:09.783976
7817 12:30:09.787156 Set Vref, RX VrefLevel [Byte0]: 31
7818 12:30:09.790727 [Byte1]: 31
7819 12:30:09.790817
7820 12:30:09.793950 Set Vref, RX VrefLevel [Byte0]: 32
7821 12:30:09.797260 [Byte1]: 32
7822 12:30:09.800549
7823 12:30:09.800640 Set Vref, RX VrefLevel [Byte0]: 33
7824 12:30:09.803672 [Byte1]: 33
7825 12:30:09.808136
7826 12:30:09.808226 Set Vref, RX VrefLevel [Byte0]: 34
7827 12:30:09.811186 [Byte1]: 34
7828 12:30:09.815705
7829 12:30:09.815791 Set Vref, RX VrefLevel [Byte0]: 35
7830 12:30:09.818660 [Byte1]: 35
7831 12:30:09.823274
7832 12:30:09.823395 Set Vref, RX VrefLevel [Byte0]: 36
7833 12:30:09.826274 [Byte1]: 36
7834 12:30:09.831211
7835 12:30:09.831313 Set Vref, RX VrefLevel [Byte0]: 37
7836 12:30:09.834312 [Byte1]: 37
7837 12:30:09.838518
7838 12:30:09.838603 Set Vref, RX VrefLevel [Byte0]: 38
7839 12:30:09.842003 [Byte1]: 38
7840 12:30:09.846131
7841 12:30:09.846232 Set Vref, RX VrefLevel [Byte0]: 39
7842 12:30:09.849145 [Byte1]: 39
7843 12:30:09.853947
7844 12:30:09.854091 Set Vref, RX VrefLevel [Byte0]: 40
7845 12:30:09.857277 [Byte1]: 40
7846 12:30:09.861222
7847 12:30:09.861331 Set Vref, RX VrefLevel [Byte0]: 41
7848 12:30:09.864531 [Byte1]: 41
7849 12:30:09.869019
7850 12:30:09.869123 Set Vref, RX VrefLevel [Byte0]: 42
7851 12:30:09.872268 [Byte1]: 42
7852 12:30:09.876714
7853 12:30:09.876811 Set Vref, RX VrefLevel [Byte0]: 43
7854 12:30:09.883235 [Byte1]: 43
7855 12:30:09.883363
7856 12:30:09.886374 Set Vref, RX VrefLevel [Byte0]: 44
7857 12:30:09.889596 [Byte1]: 44
7858 12:30:09.889699
7859 12:30:09.892960 Set Vref, RX VrefLevel [Byte0]: 45
7860 12:30:09.896367 [Byte1]: 45
7861 12:30:09.899265
7862 12:30:09.899357 Set Vref, RX VrefLevel [Byte0]: 46
7863 12:30:09.903386 [Byte1]: 46
7864 12:30:09.907091
7865 12:30:09.907198 Set Vref, RX VrefLevel [Byte0]: 47
7866 12:30:09.910342 [Byte1]: 47
7867 12:30:09.914417
7868 12:30:09.914504 Set Vref, RX VrefLevel [Byte0]: 48
7869 12:30:09.918175 [Byte1]: 48
7870 12:30:09.922529
7871 12:30:09.922631 Set Vref, RX VrefLevel [Byte0]: 49
7872 12:30:09.925671 [Byte1]: 49
7873 12:30:09.930069
7874 12:30:09.930163 Set Vref, RX VrefLevel [Byte0]: 50
7875 12:30:09.933289 [Byte1]: 50
7876 12:30:09.937589
7877 12:30:09.937684 Set Vref, RX VrefLevel [Byte0]: 51
7878 12:30:09.941199 [Byte1]: 51
7879 12:30:09.945274
7880 12:30:09.945390 Set Vref, RX VrefLevel [Byte0]: 52
7881 12:30:09.948519 [Byte1]: 52
7882 12:30:09.952738
7883 12:30:09.952866 Set Vref, RX VrefLevel [Byte0]: 53
7884 12:30:09.956246 [Byte1]: 53
7885 12:30:09.960541
7886 12:30:09.960624 Set Vref, RX VrefLevel [Byte0]: 54
7887 12:30:09.963728 [Byte1]: 54
7888 12:30:09.968090
7889 12:30:09.968172 Set Vref, RX VrefLevel [Byte0]: 55
7890 12:30:09.971223 [Byte1]: 55
7891 12:30:09.975526
7892 12:30:09.975608 Set Vref, RX VrefLevel [Byte0]: 56
7893 12:30:09.981724 [Byte1]: 56
7894 12:30:09.981808
7895 12:30:09.985492 Set Vref, RX VrefLevel [Byte0]: 57
7896 12:30:09.988575 [Byte1]: 57
7897 12:30:09.988658
7898 12:30:09.991774 Set Vref, RX VrefLevel [Byte0]: 58
7899 12:30:09.994886 [Byte1]: 58
7900 12:30:09.998617
7901 12:30:09.998701 Set Vref, RX VrefLevel [Byte0]: 59
7902 12:30:10.001745 [Byte1]: 59
7903 12:30:10.005844
7904 12:30:10.005928 Set Vref, RX VrefLevel [Byte0]: 60
7905 12:30:10.009346 [Byte1]: 60
7906 12:30:10.013473
7907 12:30:10.013556 Set Vref, RX VrefLevel [Byte0]: 61
7908 12:30:10.017029 [Byte1]: 61
7909 12:30:10.021031
7910 12:30:10.021116 Set Vref, RX VrefLevel [Byte0]: 62
7911 12:30:10.024502 [Byte1]: 62
7912 12:30:10.028752
7913 12:30:10.028839 Set Vref, RX VrefLevel [Byte0]: 63
7914 12:30:10.032486 [Byte1]: 63
7915 12:30:10.037075
7916 12:30:10.037167 Set Vref, RX VrefLevel [Byte0]: 64
7917 12:30:10.039793 [Byte1]: 64
7918 12:30:10.044103
7919 12:30:10.044191 Set Vref, RX VrefLevel [Byte0]: 65
7920 12:30:10.047148 [Byte1]: 65
7921 12:30:10.051783
7922 12:30:10.051870 Set Vref, RX VrefLevel [Byte0]: 66
7923 12:30:10.055316 [Byte1]: 66
7924 12:30:10.059283
7925 12:30:10.059402 Set Vref, RX VrefLevel [Byte0]: 67
7926 12:30:10.062738 [Byte1]: 67
7927 12:30:10.067030
7928 12:30:10.067117 Set Vref, RX VrefLevel [Byte0]: 68
7929 12:30:10.070066 [Byte1]: 68
7930 12:30:10.074441
7931 12:30:10.074529 Set Vref, RX VrefLevel [Byte0]: 69
7932 12:30:10.081237 [Byte1]: 69
7933 12:30:10.081348
7934 12:30:10.084360 Set Vref, RX VrefLevel [Byte0]: 70
7935 12:30:10.087418 [Byte1]: 70
7936 12:30:10.087510
7937 12:30:10.091045 Set Vref, RX VrefLevel [Byte0]: 71
7938 12:30:10.094109 [Byte1]: 71
7939 12:30:10.097239
7940 12:30:10.097331 Set Vref, RX VrefLevel [Byte0]: 72
7941 12:30:10.100929 [Byte1]: 72
7942 12:30:10.105283
7943 12:30:10.105383 Set Vref, RX VrefLevel [Byte0]: 73
7944 12:30:10.108376 [Byte1]: 73
7945 12:30:10.112730
7946 12:30:10.112829 Set Vref, RX VrefLevel [Byte0]: 74
7947 12:30:10.116480 [Byte1]: 74
7948 12:30:10.120325
7949 12:30:10.120422 Set Vref, RX VrefLevel [Byte0]: 75
7950 12:30:10.123387 [Byte1]: 75
7951 12:30:10.127637
7952 12:30:10.127736 Set Vref, RX VrefLevel [Byte0]: 76
7953 12:30:10.131157 [Byte1]: 76
7954 12:30:10.135311
7955 12:30:10.135397 Set Vref, RX VrefLevel [Byte0]: 77
7956 12:30:10.139072 [Byte1]: 77
7957 12:30:10.142759
7958 12:30:10.142868 Set Vref, RX VrefLevel [Byte0]: 78
7959 12:30:10.146497 [Byte1]: 78
7960 12:30:10.150749
7961 12:30:10.150860 Final RX Vref Byte 0 = 64 to rank0
7962 12:30:10.153739 Final RX Vref Byte 1 = 58 to rank0
7963 12:30:10.157270 Final RX Vref Byte 0 = 64 to rank1
7964 12:30:10.160749 Final RX Vref Byte 1 = 58 to rank1==
7965 12:30:10.163758 Dram Type= 6, Freq= 0, CH_0, rank 0
7966 12:30:10.170384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 12:30:10.170473 ==
7968 12:30:10.170539 DQS Delay:
7969 12:30:10.170600 DQS0 = 0, DQS1 = 0
7970 12:30:10.174026 DQM Delay:
7971 12:30:10.174108 DQM0 = 126, DQM1 = 120
7972 12:30:10.177247 DQ Delay:
7973 12:30:10.180361 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7974 12:30:10.183455 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7975 12:30:10.187234 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7976 12:30:10.190497 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
7977 12:30:10.190601
7978 12:30:10.190672
7979 12:30:10.190734
7980 12:30:10.193687 [DramC_TX_OE_Calibration] TA2
7981 12:30:10.196761 Original DQ_B0 (3 6) =30, OEN = 27
7982 12:30:10.200410 Original DQ_B1 (3 6) =30, OEN = 27
7983 12:30:10.203438 24, 0x0, End_B0=24 End_B1=24
7984 12:30:10.203564 25, 0x0, End_B0=25 End_B1=25
7985 12:30:10.206690 26, 0x0, End_B0=26 End_B1=26
7986 12:30:10.209791 27, 0x0, End_B0=27 End_B1=27
7987 12:30:10.213375 28, 0x0, End_B0=28 End_B1=28
7988 12:30:10.216337 29, 0x0, End_B0=29 End_B1=29
7989 12:30:10.216438 30, 0x0, End_B0=30 End_B1=30
7990 12:30:10.220212 31, 0x4141, End_B0=30 End_B1=30
7991 12:30:10.223243 Byte0 end_step=30 best_step=27
7992 12:30:10.226729 Byte1 end_step=30 best_step=27
7993 12:30:10.229539 Byte0 TX OE(2T, 0.5T) = (3, 3)
7994 12:30:10.233306 Byte1 TX OE(2T, 0.5T) = (3, 3)
7995 12:30:10.233389
7996 12:30:10.233492
7997 12:30:10.239586 [DQSOSCAuto] RK0, (LSB)MR18= 0x100f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
7998 12:30:10.243104 CH0 RK0: MR19=303, MR18=100F
7999 12:30:10.249291 CH0_RK0: MR19=0x303, MR18=0x100F, DQSOSC=401, MR23=63, INC=22, DEC=15
8000 12:30:10.249375
8001 12:30:10.252852 ----->DramcWriteLeveling(PI) begin...
8002 12:30:10.252971 ==
8003 12:30:10.255929 Dram Type= 6, Freq= 0, CH_0, rank 1
8004 12:30:10.259084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 12:30:10.259272 ==
8006 12:30:10.262182 Write leveling (Byte 0): 34 => 34
8007 12:30:10.265768 Write leveling (Byte 1): 28 => 28
8008 12:30:10.268855 DramcWriteLeveling(PI) end<-----
8009 12:30:10.268952
8010 12:30:10.269019 ==
8011 12:30:10.272681 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 12:30:10.279037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 12:30:10.279136 ==
8014 12:30:10.279206 [Gating] SW mode calibration
8015 12:30:10.288910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8016 12:30:10.292095 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8017 12:30:10.298965 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 12:30:10.302240 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 12:30:10.305490 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:30:10.312417 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8021 12:30:10.315451 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
8022 12:30:10.318577 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8023 12:30:10.324984 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 12:30:10.328298 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 12:30:10.331247 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 12:30:10.338333 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8027 12:30:10.341374 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8028 12:30:10.344519 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8029 12:30:10.351446 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8030 12:30:10.354778 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8031 12:30:10.358065 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 12:30:10.364230 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 12:30:10.367940 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:30:10.371065 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 12:30:10.377978 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 12:30:10.381100 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8037 12:30:10.384116 1 6 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8038 12:30:10.391095 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 12:30:10.394386 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 12:30:10.397686 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:30:10.404176 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 12:30:10.407344 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:30:10.410614 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8044 12:30:10.417551 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 12:30:10.420735 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8046 12:30:10.424045 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 12:30:10.430563 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:30:10.434001 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:30:10.437310 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:30:10.444319 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:30:10.447058 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:30:10.450924 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:30:10.457162 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:30:10.460279 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:30:10.463991 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:30:10.470072 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:30:10.473183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:30:10.476461 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:30:10.483273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8060 12:30:10.486444 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 12:30:10.489620 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8062 12:30:10.492919 Total UI for P1: 0, mck2ui 16
8063 12:30:10.496302 best dqsien dly found for B0: ( 1, 9, 10)
8064 12:30:10.503032 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 12:30:10.506318 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 12:30:10.509381 Total UI for P1: 0, mck2ui 16
8067 12:30:10.513108 best dqsien dly found for B1: ( 1, 9, 18)
8068 12:30:10.516291 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8069 12:30:10.519754 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8070 12:30:10.520199
8071 12:30:10.523039 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8072 12:30:10.526261 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8073 12:30:10.529409 [Gating] SW calibration Done
8074 12:30:10.529788 ==
8075 12:30:10.532634 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 12:30:10.536351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 12:30:10.539508 ==
8078 12:30:10.539847 RX Vref Scan: 0
8079 12:30:10.540083
8080 12:30:10.542880 RX Vref 0 -> 0, step: 1
8081 12:30:10.543151
8082 12:30:10.545861 RX Delay 0 -> 252, step: 8
8083 12:30:10.549355 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8084 12:30:10.552275 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8085 12:30:10.555876 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8086 12:30:10.558817 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8087 12:30:10.565852 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8088 12:30:10.568879 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8089 12:30:10.572557 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8090 12:30:10.575714 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8091 12:30:10.578728 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8092 12:30:10.585345 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8093 12:30:10.588472 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8094 12:30:10.591655 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8095 12:30:10.595334 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8096 12:30:10.598710 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8097 12:30:10.605130 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8098 12:30:10.608437 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8099 12:30:10.608525 ==
8100 12:30:10.611459 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 12:30:10.615205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 12:30:10.615289 ==
8103 12:30:10.618388 DQS Delay:
8104 12:30:10.618472 DQS0 = 0, DQS1 = 0
8105 12:30:10.621455 DQM Delay:
8106 12:30:10.621542 DQM0 = 127, DQM1 = 121
8107 12:30:10.621612 DQ Delay:
8108 12:30:10.625086 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8109 12:30:10.631438 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8110 12:30:10.634708 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8111 12:30:10.638264 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8112 12:30:10.638361
8113 12:30:10.638425
8114 12:30:10.638485 ==
8115 12:30:10.641592 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:30:10.644686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:30:10.644785 ==
8118 12:30:10.644861
8119 12:30:10.644930
8120 12:30:10.647746 TX Vref Scan disable
8121 12:30:10.651399 == TX Byte 0 ==
8122 12:30:10.655037 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8123 12:30:10.658187 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8124 12:30:10.661084 == TX Byte 1 ==
8125 12:30:10.664316 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8126 12:30:10.667708 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8127 12:30:10.667810 ==
8128 12:30:10.670880 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 12:30:10.677032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 12:30:10.677137 ==
8131 12:30:10.690752
8132 12:30:10.694166 TX Vref early break, caculate TX vref
8133 12:30:10.697217 TX Vref=16, minBit 0, minWin=22, winSum=368
8134 12:30:10.700799 TX Vref=18, minBit 9, minWin=22, winSum=373
8135 12:30:10.703732 TX Vref=20, minBit 8, minWin=22, winSum=376
8136 12:30:10.707390 TX Vref=22, minBit 1, minWin=23, winSum=387
8137 12:30:10.710512 TX Vref=24, minBit 8, minWin=23, winSum=398
8138 12:30:10.717294 TX Vref=26, minBit 1, minWin=25, winSum=407
8139 12:30:10.720489 TX Vref=28, minBit 8, minWin=24, winSum=410
8140 12:30:10.723818 TX Vref=30, minBit 8, minWin=23, winSum=405
8141 12:30:10.727050 TX Vref=32, minBit 8, minWin=24, winSum=398
8142 12:30:10.730278 TX Vref=34, minBit 8, minWin=22, winSum=389
8143 12:30:10.736806 TX Vref=36, minBit 8, minWin=22, winSum=379
8144 12:30:10.740008 [TxChooseVref] Worse bit 1, Min win 25, Win sum 407, Final Vref 26
8145 12:30:10.740212
8146 12:30:10.743249 Final TX Range 0 Vref 26
8147 12:30:10.743450
8148 12:30:10.743609 ==
8149 12:30:10.747265 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 12:30:10.750049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 12:30:10.753693 ==
8152 12:30:10.753855
8153 12:30:10.753922
8154 12:30:10.753985 TX Vref Scan disable
8155 12:30:10.760113 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8156 12:30:10.760226 == TX Byte 0 ==
8157 12:30:10.763557 u2DelayCellOfst[0]=15 cells (4 PI)
8158 12:30:10.766629 u2DelayCellOfst[1]=18 cells (5 PI)
8159 12:30:10.770134 u2DelayCellOfst[2]=15 cells (4 PI)
8160 12:30:10.773686 u2DelayCellOfst[3]=15 cells (4 PI)
8161 12:30:10.776778 u2DelayCellOfst[4]=11 cells (3 PI)
8162 12:30:10.779948 u2DelayCellOfst[5]=0 cells (0 PI)
8163 12:30:10.782988 u2DelayCellOfst[6]=22 cells (6 PI)
8164 12:30:10.786268 u2DelayCellOfst[7]=22 cells (6 PI)
8165 12:30:10.789842 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8166 12:30:10.792872 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8167 12:30:10.796489 == TX Byte 1 ==
8168 12:30:10.799426 u2DelayCellOfst[8]=0 cells (0 PI)
8169 12:30:10.803034 u2DelayCellOfst[9]=3 cells (1 PI)
8170 12:30:10.806400 u2DelayCellOfst[10]=11 cells (3 PI)
8171 12:30:10.809264 u2DelayCellOfst[11]=7 cells (2 PI)
8172 12:30:10.812787 u2DelayCellOfst[12]=15 cells (4 PI)
8173 12:30:10.815831 u2DelayCellOfst[13]=15 cells (4 PI)
8174 12:30:10.818977 u2DelayCellOfst[14]=15 cells (4 PI)
8175 12:30:10.822536 u2DelayCellOfst[15]=11 cells (3 PI)
8176 12:30:10.825635 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8177 12:30:10.829417 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8178 12:30:10.832666 DramC Write-DBI on
8179 12:30:10.833029 ==
8180 12:30:10.835963 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 12:30:10.839617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 12:30:10.840051 ==
8183 12:30:10.840367
8184 12:30:10.840660
8185 12:30:10.842652 TX Vref Scan disable
8186 12:30:10.846315 == TX Byte 0 ==
8187 12:30:10.849481 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8188 12:30:10.849873 == TX Byte 1 ==
8189 12:30:10.855605 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8190 12:30:10.855998 DramC Write-DBI off
8191 12:30:10.856381
8192 12:30:10.856750 [DATLAT]
8193 12:30:10.859034 Freq=1600, CH0 RK1
8194 12:30:10.859423
8195 12:30:10.862191 DATLAT Default: 0xf
8196 12:30:10.862579 0, 0xFFFF, sum = 0
8197 12:30:10.865484 1, 0xFFFF, sum = 0
8198 12:30:10.865945 2, 0xFFFF, sum = 0
8199 12:30:10.869049 3, 0xFFFF, sum = 0
8200 12:30:10.869706 4, 0xFFFF, sum = 0
8201 12:30:10.872572 5, 0xFFFF, sum = 0
8202 12:30:10.873074 6, 0xFFFF, sum = 0
8203 12:30:10.875511 7, 0xFFFF, sum = 0
8204 12:30:10.875908 8, 0xFFFF, sum = 0
8205 12:30:10.878568 9, 0xFFFF, sum = 0
8206 12:30:10.879013 10, 0xFFFF, sum = 0
8207 12:30:10.882367 11, 0xFFFF, sum = 0
8208 12:30:10.882934 12, 0xFFFF, sum = 0
8209 12:30:10.885206 13, 0xCFFF, sum = 0
8210 12:30:10.888598 14, 0x0, sum = 1
8211 12:30:10.889215 15, 0x0, sum = 2
8212 12:30:10.889777 16, 0x0, sum = 3
8213 12:30:10.891983 17, 0x0, sum = 4
8214 12:30:10.892506 best_step = 15
8215 12:30:10.893051
8216 12:30:10.893562 ==
8217 12:30:10.895471 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 12:30:10.902052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 12:30:10.902445 ==
8220 12:30:10.902761 RX Vref Scan: 0
8221 12:30:10.903259
8222 12:30:10.904922 RX Vref 0 -> 0, step: 1
8223 12:30:10.905200
8224 12:30:10.908318 RX Delay 3 -> 252, step: 4
8225 12:30:10.911821 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8226 12:30:10.914732 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8227 12:30:10.921434 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8228 12:30:10.924497 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8229 12:30:10.928360 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8230 12:30:10.931502 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8231 12:30:10.934499 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8232 12:30:10.941118 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8233 12:30:10.944363 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8234 12:30:10.947408 iDelay=191, Bit 9, Center 106 (51 ~ 162) 112
8235 12:30:10.951072 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8236 12:30:10.957176 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8237 12:30:10.960760 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8238 12:30:10.964359 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8239 12:30:10.967388 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8240 12:30:10.970511 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8241 12:30:10.974345 ==
8242 12:30:10.974429 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 12:30:10.980394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 12:30:10.980482 ==
8245 12:30:10.980551 DQS Delay:
8246 12:30:10.984019 DQS0 = 0, DQS1 = 0
8247 12:30:10.984104 DQM Delay:
8248 12:30:10.987181 DQM0 = 124, DQM1 = 118
8249 12:30:10.987269 DQ Delay:
8250 12:30:10.990706 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8251 12:30:10.993654 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8252 12:30:10.997264 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =112
8253 12:30:11.000121 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8254 12:30:11.000206
8255 12:30:11.000273
8256 12:30:11.000336
8257 12:30:11.003653 [DramC_TX_OE_Calibration] TA2
8258 12:30:11.007212 Original DQ_B0 (3 6) =30, OEN = 27
8259 12:30:11.010154 Original DQ_B1 (3 6) =30, OEN = 27
8260 12:30:11.013552 24, 0x0, End_B0=24 End_B1=24
8261 12:30:11.017058 25, 0x0, End_B0=25 End_B1=25
8262 12:30:11.017144 26, 0x0, End_B0=26 End_B1=26
8263 12:30:11.020072 27, 0x0, End_B0=27 End_B1=27
8264 12:30:11.023447 28, 0x0, End_B0=28 End_B1=28
8265 12:30:11.026914 29, 0x0, End_B0=29 End_B1=29
8266 12:30:11.029951 30, 0x0, End_B0=30 End_B1=30
8267 12:30:11.030038 31, 0x4141, End_B0=30 End_B1=30
8268 12:30:11.033479 Byte0 end_step=30 best_step=27
8269 12:30:11.036519 Byte1 end_step=30 best_step=27
8270 12:30:11.039857 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 12:30:11.043356 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 12:30:11.043439
8273 12:30:11.043505
8274 12:30:11.049635 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8275 12:30:11.053460 CH0 RK1: MR19=303, MR18=2210
8276 12:30:11.059581 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8277 12:30:11.063198 [RxdqsGatingPostProcess] freq 1600
8278 12:30:11.069780 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 12:30:11.072842 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 12:30:11.072982 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 12:30:11.075980 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 12:30:11.079877 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 12:30:11.082820 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 12:30:11.086016 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 12:30:11.089157 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 12:30:11.092870 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 12:30:11.095983 Pre-setting of DQS Precalculation
8288 12:30:11.102492 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 12:30:11.102845 ==
8290 12:30:11.105954 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 12:30:11.109790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 12:30:11.110303 ==
8293 12:30:11.116031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 12:30:11.119406 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 12:30:11.122255 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 12:30:11.128895 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 12:30:11.137836 [CA 0] Center 41 (13~70) winsize 58
8298 12:30:11.140758 [CA 1] Center 42 (12~72) winsize 61
8299 12:30:11.144114 [CA 2] Center 37 (9~66) winsize 58
8300 12:30:11.147180 [CA 3] Center 37 (8~66) winsize 59
8301 12:30:11.150960 [CA 4] Center 37 (8~67) winsize 60
8302 12:30:11.154270 [CA 5] Center 36 (7~66) winsize 60
8303 12:30:11.154684
8304 12:30:11.157779 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 12:30:11.158331
8306 12:30:11.164192 [CATrainingPosCal] consider 1 rank data
8307 12:30:11.164648 u2DelayCellTimex100 = 258/100 ps
8308 12:30:11.170938 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8309 12:30:11.173797 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8310 12:30:11.176965 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8311 12:30:11.180768 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 12:30:11.183895 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8313 12:30:11.186963 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 12:30:11.187204
8315 12:30:11.190073 CA PerBit enable=1, Macro0, CA PI delay=36
8316 12:30:11.190267
8317 12:30:11.193776 [CBTSetCACLKResult] CA Dly = 36
8318 12:30:11.196706 CS Dly: 9 (0~40)
8319 12:30:11.200136 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 12:30:11.203217 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 12:30:11.203322 ==
8322 12:30:11.206871 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 12:30:11.213538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 12:30:11.213631 ==
8325 12:30:11.216423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 12:30:11.223069 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 12:30:11.226626 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 12:30:11.233043 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 12:30:11.240831 [CA 0] Center 42 (13~72) winsize 60
8330 12:30:11.243940 [CA 1] Center 42 (12~72) winsize 61
8331 12:30:11.247407 [CA 2] Center 38 (9~67) winsize 59
8332 12:30:11.250390 [CA 3] Center 36 (7~66) winsize 60
8333 12:30:11.253405 [CA 4] Center 38 (8~68) winsize 61
8334 12:30:11.257114 [CA 5] Center 36 (7~66) winsize 60
8335 12:30:11.257196
8336 12:30:11.259979 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 12:30:11.260063
8338 12:30:11.266395 [CATrainingPosCal] consider 2 rank data
8339 12:30:11.266524 u2DelayCellTimex100 = 258/100 ps
8340 12:30:11.273326 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8341 12:30:11.276912 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8342 12:30:11.280001 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8343 12:30:11.283088 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8344 12:30:11.286492 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8345 12:30:11.289974 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8346 12:30:11.290055
8347 12:30:11.292972 CA PerBit enable=1, Macro0, CA PI delay=36
8348 12:30:11.293053
8349 12:30:11.296135 [CBTSetCACLKResult] CA Dly = 36
8350 12:30:11.299252 CS Dly: 11 (0~44)
8351 12:30:11.302760 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 12:30:11.305790 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 12:30:11.305902
8354 12:30:11.309598 ----->DramcWriteLeveling(PI) begin...
8355 12:30:11.312735 ==
8356 12:30:11.315779 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 12:30:11.319234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 12:30:11.319342 ==
8359 12:30:11.322479 Write leveling (Byte 0): 24 => 24
8360 12:30:11.325792 Write leveling (Byte 1): 27 => 27
8361 12:30:11.329317 DramcWriteLeveling(PI) end<-----
8362 12:30:11.329428
8363 12:30:11.329496 ==
8364 12:30:11.332455 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 12:30:11.336048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 12:30:11.336160 ==
8367 12:30:11.338823 [Gating] SW mode calibration
8368 12:30:11.345464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 12:30:11.352121 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 12:30:11.355768 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:30:11.358760 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:30:11.365560 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:30:11.368805 1 4 12 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
8374 12:30:11.372052 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 12:30:11.378273 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:30:11.381819 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:30:11.384936 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:30:11.391793 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:30:11.395028 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:30:11.398063 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:30:11.405044 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 12:30:11.408607 1 5 16 | B1->B0 | 2424 2727 | 0 1 | (0 0) (1 0)
8383 12:30:11.411724 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:30:11.418106 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:30:11.421098 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:30:11.424776 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:30:11.431113 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:30:11.434679 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:30:11.437730 1 6 12 | B1->B0 | 2d2d 2727 | 0 1 | (0 0) (0 0)
8390 12:30:11.444275 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8391 12:30:11.447829 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:30:11.451303 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:30:11.457794 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:30:11.460787 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:30:11.464247 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:30:11.470981 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:30:11.474130 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8398 12:30:11.477239 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 12:30:11.483943 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 12:30:11.487047 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:30:11.490775 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:30:11.497116 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:30:11.500665 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:30:11.503685 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:30:11.510324 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:30:11.513451 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:30:11.516597 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:30:11.523309 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:30:11.526464 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:30:11.530377 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:30:11.536808 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:30:11.539812 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:30:11.543544 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:30:11.549986 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 12:30:11.553446 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 12:30:11.556354 Total UI for P1: 0, mck2ui 16
8417 12:30:11.559961 best dqsien dly found for B0: ( 1, 9, 16)
8418 12:30:11.562963 Total UI for P1: 0, mck2ui 16
8419 12:30:11.566648 best dqsien dly found for B1: ( 1, 9, 16)
8420 12:30:11.569551 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8421 12:30:11.573202 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8422 12:30:11.573285
8423 12:30:11.576244 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8424 12:30:11.579333 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8425 12:30:11.583093 [Gating] SW calibration Done
8426 12:30:11.583176 ==
8427 12:30:11.586160 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 12:30:11.592824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 12:30:11.592908 ==
8430 12:30:11.592974 RX Vref Scan: 0
8431 12:30:11.593034
8432 12:30:11.595851 RX Vref 0 -> 0, step: 1
8433 12:30:11.595933
8434 12:30:11.599719 RX Delay 0 -> 252, step: 8
8435 12:30:11.602618 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8436 12:30:11.605781 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8437 12:30:11.609276 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8438 12:30:11.613041 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8439 12:30:11.619137 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8440 12:30:11.623092 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8441 12:30:11.626169 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8442 12:30:11.629408 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8443 12:30:11.632475 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8444 12:30:11.638864 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8445 12:30:11.642149 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8446 12:30:11.645564 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8447 12:30:11.649142 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8448 12:30:11.655480 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8449 12:30:11.658880 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8450 12:30:11.661912 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8451 12:30:11.662335 ==
8452 12:30:11.665420 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 12:30:11.669114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 12:30:11.669687 ==
8455 12:30:11.672151 DQS Delay:
8456 12:30:11.672784 DQS0 = 0, DQS1 = 0
8457 12:30:11.675448 DQM Delay:
8458 12:30:11.675747 DQM0 = 131, DQM1 = 126
8459 12:30:11.678295 DQ Delay:
8460 12:30:11.681828 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8461 12:30:11.685019 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8462 12:30:11.688452 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8463 12:30:11.691497 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8464 12:30:11.691579
8465 12:30:11.691644
8466 12:30:11.691705 ==
8467 12:30:11.694966 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 12:30:11.698004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 12:30:11.698086 ==
8470 12:30:11.698152
8471 12:30:11.698212
8472 12:30:11.701689 TX Vref Scan disable
8473 12:30:11.704846 == TX Byte 0 ==
8474 12:30:11.708346 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8475 12:30:11.711523 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8476 12:30:11.714453 == TX Byte 1 ==
8477 12:30:11.717700 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8478 12:30:11.720967 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8479 12:30:11.721050 ==
8480 12:30:11.724201 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 12:30:11.730757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 12:30:11.730849 ==
8483 12:30:11.744173
8484 12:30:11.747234 TX Vref early break, caculate TX vref
8485 12:30:11.750742 TX Vref=16, minBit 1, minWin=22, winSum=360
8486 12:30:11.753867 TX Vref=18, minBit 1, minWin=22, winSum=365
8487 12:30:11.757085 TX Vref=20, minBit 9, minWin=23, winSum=384
8488 12:30:11.760507 TX Vref=22, minBit 4, minWin=23, winSum=388
8489 12:30:11.763459 TX Vref=24, minBit 0, minWin=24, winSum=401
8490 12:30:11.770026 TX Vref=26, minBit 6, minWin=24, winSum=411
8491 12:30:11.773478 TX Vref=28, minBit 6, minWin=24, winSum=413
8492 12:30:11.777027 TX Vref=30, minBit 1, minWin=24, winSum=413
8493 12:30:11.780116 TX Vref=32, minBit 1, minWin=24, winSum=409
8494 12:30:11.783217 TX Vref=34, minBit 0, minWin=23, winSum=393
8495 12:30:11.789848 TX Vref=36, minBit 1, minWin=22, winSum=385
8496 12:30:11.793418 [TxChooseVref] Worse bit 6, Min win 24, Win sum 413, Final Vref 28
8497 12:30:11.793498
8498 12:30:11.796550 Final TX Range 0 Vref 28
8499 12:30:11.796636
8500 12:30:11.796721 ==
8501 12:30:11.800005 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 12:30:11.803083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 12:30:11.806161 ==
8504 12:30:11.806245
8505 12:30:11.806329
8506 12:30:11.806409 TX Vref Scan disable
8507 12:30:11.812978 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8508 12:30:11.813064 == TX Byte 0 ==
8509 12:30:11.816053 u2DelayCellOfst[0]=22 cells (6 PI)
8510 12:30:11.819847 u2DelayCellOfst[1]=15 cells (4 PI)
8511 12:30:11.822892 u2DelayCellOfst[2]=0 cells (0 PI)
8512 12:30:11.826581 u2DelayCellOfst[3]=11 cells (3 PI)
8513 12:30:11.829806 u2DelayCellOfst[4]=11 cells (3 PI)
8514 12:30:11.832991 u2DelayCellOfst[5]=22 cells (6 PI)
8515 12:30:11.836139 u2DelayCellOfst[6]=22 cells (6 PI)
8516 12:30:11.839299 u2DelayCellOfst[7]=11 cells (3 PI)
8517 12:30:11.842407 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8518 12:30:11.846244 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 12:30:11.849219 == TX Byte 1 ==
8520 12:30:11.852680 u2DelayCellOfst[8]=0 cells (0 PI)
8521 12:30:11.855644 u2DelayCellOfst[9]=7 cells (2 PI)
8522 12:30:11.858815 u2DelayCellOfst[10]=15 cells (4 PI)
8523 12:30:11.862213 u2DelayCellOfst[11]=11 cells (3 PI)
8524 12:30:11.865601 u2DelayCellOfst[12]=18 cells (5 PI)
8525 12:30:11.869124 u2DelayCellOfst[13]=22 cells (6 PI)
8526 12:30:11.872030 u2DelayCellOfst[14]=22 cells (6 PI)
8527 12:30:11.875372 u2DelayCellOfst[15]=22 cells (6 PI)
8528 12:30:11.878815 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8529 12:30:11.882399 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 12:30:11.885350 DramC Write-DBI on
8531 12:30:11.885435 ==
8532 12:30:11.888880 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 12:30:11.891880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 12:30:11.891966 ==
8535 12:30:11.892051
8536 12:30:11.892131
8537 12:30:11.895468 TX Vref Scan disable
8538 12:30:11.898441 == TX Byte 0 ==
8539 12:30:11.901923 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8540 12:30:11.902008 == TX Byte 1 ==
8541 12:30:11.908697 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8542 12:30:11.908782 DramC Write-DBI off
8543 12:30:11.908882
8544 12:30:11.908964 [DATLAT]
8545 12:30:11.911951 Freq=1600, CH1 RK0
8546 12:30:11.912033
8547 12:30:11.915099 DATLAT Default: 0xf
8548 12:30:11.915181 0, 0xFFFF, sum = 0
8549 12:30:11.918720 1, 0xFFFF, sum = 0
8550 12:30:11.918804 2, 0xFFFF, sum = 0
8551 12:30:11.921894 3, 0xFFFF, sum = 0
8552 12:30:11.921980 4, 0xFFFF, sum = 0
8553 12:30:11.924980 5, 0xFFFF, sum = 0
8554 12:30:11.925097 6, 0xFFFF, sum = 0
8555 12:30:11.928597 7, 0xFFFF, sum = 0
8556 12:30:11.928701 8, 0xFFFF, sum = 0
8557 12:30:11.931709 9, 0xFFFF, sum = 0
8558 12:30:11.931793 10, 0xFFFF, sum = 0
8559 12:30:11.934978 11, 0xFFFF, sum = 0
8560 12:30:11.935061 12, 0xFFFF, sum = 0
8561 12:30:11.938005 13, 0x8FFF, sum = 0
8562 12:30:11.938097 14, 0x0, sum = 1
8563 12:30:11.941626 15, 0x0, sum = 2
8564 12:30:11.941716 16, 0x0, sum = 3
8565 12:30:11.944764 17, 0x0, sum = 4
8566 12:30:11.944852 best_step = 15
8567 12:30:11.944918
8568 12:30:11.944978 ==
8569 12:30:11.947935 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 12:30:11.954724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 12:30:11.954807 ==
8572 12:30:11.954921 RX Vref Scan: 1
8573 12:30:11.954984
8574 12:30:11.958352 Set Vref Range= 24 -> 127
8575 12:30:11.958435
8576 12:30:11.961446 RX Vref 24 -> 127, step: 1
8577 12:30:11.961568
8578 12:30:11.964484 RX Delay 11 -> 252, step: 4
8579 12:30:11.964587
8580 12:30:11.967712 Set Vref, RX VrefLevel [Byte0]: 24
8581 12:30:11.970906 [Byte1]: 24
8582 12:30:11.970988
8583 12:30:11.974107 Set Vref, RX VrefLevel [Byte0]: 25
8584 12:30:11.977585 [Byte1]: 25
8585 12:30:11.977693
8586 12:30:11.981011 Set Vref, RX VrefLevel [Byte0]: 26
8587 12:30:11.984591 [Byte1]: 26
8588 12:30:11.987891
8589 12:30:11.987973 Set Vref, RX VrefLevel [Byte0]: 27
8590 12:30:11.990706 [Byte1]: 27
8591 12:30:11.995309
8592 12:30:11.995451 Set Vref, RX VrefLevel [Byte0]: 28
8593 12:30:11.998396 [Byte1]: 28
8594 12:30:12.003075
8595 12:30:12.003157 Set Vref, RX VrefLevel [Byte0]: 29
8596 12:30:12.005948 [Byte1]: 29
8597 12:30:12.010766
8598 12:30:12.010875 Set Vref, RX VrefLevel [Byte0]: 30
8599 12:30:12.013697 [Byte1]: 30
8600 12:30:12.018319
8601 12:30:12.018400 Set Vref, RX VrefLevel [Byte0]: 31
8602 12:30:12.021326 [Byte1]: 31
8603 12:30:12.025763
8604 12:30:12.028817 Set Vref, RX VrefLevel [Byte0]: 32
8605 12:30:12.032315 [Byte1]: 32
8606 12:30:12.032397
8607 12:30:12.035338 Set Vref, RX VrefLevel [Byte0]: 33
8608 12:30:12.038547 [Byte1]: 33
8609 12:30:12.038631
8610 12:30:12.042336 Set Vref, RX VrefLevel [Byte0]: 34
8611 12:30:12.045428 [Byte1]: 34
8612 12:30:12.048578
8613 12:30:12.048660 Set Vref, RX VrefLevel [Byte0]: 35
8614 12:30:12.051647 [Byte1]: 35
8615 12:30:12.055986
8616 12:30:12.056079 Set Vref, RX VrefLevel [Byte0]: 36
8617 12:30:12.063050 [Byte1]: 36
8618 12:30:12.063135
8619 12:30:12.065805 Set Vref, RX VrefLevel [Byte0]: 37
8620 12:30:12.069578 [Byte1]: 37
8621 12:30:12.069660
8622 12:30:12.072414 Set Vref, RX VrefLevel [Byte0]: 38
8623 12:30:12.076055 [Byte1]: 38
8624 12:30:12.076138
8625 12:30:12.079160 Set Vref, RX VrefLevel [Byte0]: 39
8626 12:30:12.082353 [Byte1]: 39
8627 12:30:12.086376
8628 12:30:12.086458 Set Vref, RX VrefLevel [Byte0]: 40
8629 12:30:12.089951 [Byte1]: 40
8630 12:30:12.094074
8631 12:30:12.094151 Set Vref, RX VrefLevel [Byte0]: 41
8632 12:30:12.097412 [Byte1]: 41
8633 12:30:12.101613
8634 12:30:12.101692 Set Vref, RX VrefLevel [Byte0]: 42
8635 12:30:12.105094 [Byte1]: 42
8636 12:30:12.109276
8637 12:30:12.109358 Set Vref, RX VrefLevel [Byte0]: 43
8638 12:30:12.112726 [Byte1]: 43
8639 12:30:12.117228
8640 12:30:12.117342 Set Vref, RX VrefLevel [Byte0]: 44
8641 12:30:12.120357 [Byte1]: 44
8642 12:30:12.125050
8643 12:30:12.125135 Set Vref, RX VrefLevel [Byte0]: 45
8644 12:30:12.127983 [Byte1]: 45
8645 12:30:12.132330
8646 12:30:12.132413 Set Vref, RX VrefLevel [Byte0]: 46
8647 12:30:12.135308 [Byte1]: 46
8648 12:30:12.140110
8649 12:30:12.140191 Set Vref, RX VrefLevel [Byte0]: 47
8650 12:30:12.143299 [Byte1]: 47
8651 12:30:12.147701
8652 12:30:12.147784 Set Vref, RX VrefLevel [Byte0]: 48
8653 12:30:12.150772 [Byte1]: 48
8654 12:30:12.155256
8655 12:30:12.155337 Set Vref, RX VrefLevel [Byte0]: 49
8656 12:30:12.158455 [Byte1]: 49
8657 12:30:12.162712
8658 12:30:12.162809 Set Vref, RX VrefLevel [Byte0]: 50
8659 12:30:12.165687 [Byte1]: 50
8660 12:30:12.170122
8661 12:30:12.170204 Set Vref, RX VrefLevel [Byte0]: 51
8662 12:30:12.173748 [Byte1]: 51
8663 12:30:12.178213
8664 12:30:12.178303 Set Vref, RX VrefLevel [Byte0]: 52
8665 12:30:12.181277 [Byte1]: 52
8666 12:30:12.185670
8667 12:30:12.185752 Set Vref, RX VrefLevel [Byte0]: 53
8668 12:30:12.189115 [Byte1]: 53
8669 12:30:12.192992
8670 12:30:12.193108 Set Vref, RX VrefLevel [Byte0]: 54
8671 12:30:12.196638 [Byte1]: 54
8672 12:30:12.200707
8673 12:30:12.200790 Set Vref, RX VrefLevel [Byte0]: 55
8674 12:30:12.204014 [Byte1]: 55
8675 12:30:12.208204
8676 12:30:12.208357 Set Vref, RX VrefLevel [Byte0]: 56
8677 12:30:12.211784 [Byte1]: 56
8678 12:30:12.215950
8679 12:30:12.216064 Set Vref, RX VrefLevel [Byte0]: 57
8680 12:30:12.219594 [Byte1]: 57
8681 12:30:12.223761
8682 12:30:12.223860 Set Vref, RX VrefLevel [Byte0]: 58
8683 12:30:12.226935 [Byte1]: 58
8684 12:30:12.231249
8685 12:30:12.231332 Set Vref, RX VrefLevel [Byte0]: 59
8686 12:30:12.234882 [Byte1]: 59
8687 12:30:12.239062
8688 12:30:12.239145 Set Vref, RX VrefLevel [Byte0]: 60
8689 12:30:12.242049 [Byte1]: 60
8690 12:30:12.246417
8691 12:30:12.246522 Set Vref, RX VrefLevel [Byte0]: 61
8692 12:30:12.249575 [Byte1]: 61
8693 12:30:12.253975
8694 12:30:12.254060 Set Vref, RX VrefLevel [Byte0]: 62
8695 12:30:12.260420 [Byte1]: 62
8696 12:30:12.260535
8697 12:30:12.263566 Set Vref, RX VrefLevel [Byte0]: 63
8698 12:30:12.267352 [Byte1]: 63
8699 12:30:12.267439
8700 12:30:12.270255 Set Vref, RX VrefLevel [Byte0]: 64
8701 12:30:12.273353 [Byte1]: 64
8702 12:30:12.277187
8703 12:30:12.277304 Set Vref, RX VrefLevel [Byte0]: 65
8704 12:30:12.280271 [Byte1]: 65
8705 12:30:12.284645
8706 12:30:12.284730 Set Vref, RX VrefLevel [Byte0]: 66
8707 12:30:12.287821 [Byte1]: 66
8708 12:30:12.292340
8709 12:30:12.292424 Set Vref, RX VrefLevel [Byte0]: 67
8710 12:30:12.295568 [Byte1]: 67
8711 12:30:12.299890
8712 12:30:12.299972 Set Vref, RX VrefLevel [Byte0]: 68
8713 12:30:12.303000 [Byte1]: 68
8714 12:30:12.307204
8715 12:30:12.307280 Set Vref, RX VrefLevel [Byte0]: 69
8716 12:30:12.310649 [Byte1]: 69
8717 12:30:12.314929
8718 12:30:12.315023 Set Vref, RX VrefLevel [Byte0]: 70
8719 12:30:12.318381 [Byte1]: 70
8720 12:30:12.322620
8721 12:30:12.322727 Set Vref, RX VrefLevel [Byte0]: 71
8722 12:30:12.325626 [Byte1]: 71
8723 12:30:12.330530
8724 12:30:12.330638 Final RX Vref Byte 0 = 58 to rank0
8725 12:30:12.333340 Final RX Vref Byte 1 = 56 to rank0
8726 12:30:12.336935 Final RX Vref Byte 0 = 58 to rank1
8727 12:30:12.340162 Final RX Vref Byte 1 = 56 to rank1==
8728 12:30:12.343123 Dram Type= 6, Freq= 0, CH_1, rank 0
8729 12:30:12.349946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 12:30:12.350058 ==
8731 12:30:12.350155 DQS Delay:
8732 12:30:12.353005 DQS0 = 0, DQS1 = 0
8733 12:30:12.353090 DQM Delay:
8734 12:30:12.353165 DQM0 = 131, DQM1 = 123
8735 12:30:12.356254 DQ Delay:
8736 12:30:12.359989 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8737 12:30:12.363454 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8738 12:30:12.366371 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8739 12:30:12.370112 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8740 12:30:12.370197
8741 12:30:12.370265
8742 12:30:12.370354
8743 12:30:12.373131 [DramC_TX_OE_Calibration] TA2
8744 12:30:12.376684 Original DQ_B0 (3 6) =30, OEN = 27
8745 12:30:12.379626 Original DQ_B1 (3 6) =30, OEN = 27
8746 12:30:12.382741 24, 0x0, End_B0=24 End_B1=24
8747 12:30:12.386610 25, 0x0, End_B0=25 End_B1=25
8748 12:30:12.386687 26, 0x0, End_B0=26 End_B1=26
8749 12:30:12.389677 27, 0x0, End_B0=27 End_B1=27
8750 12:30:12.392740 28, 0x0, End_B0=28 End_B1=28
8751 12:30:12.395844 29, 0x0, End_B0=29 End_B1=29
8752 12:30:12.395932 30, 0x0, End_B0=30 End_B1=30
8753 12:30:12.399054 31, 0x4545, End_B0=30 End_B1=30
8754 12:30:12.403027 Byte0 end_step=30 best_step=27
8755 12:30:12.406015 Byte1 end_step=30 best_step=27
8756 12:30:12.409078 Byte0 TX OE(2T, 0.5T) = (3, 3)
8757 12:30:12.412665 Byte1 TX OE(2T, 0.5T) = (3, 3)
8758 12:30:12.412741
8759 12:30:12.412804
8760 12:30:12.419035 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8761 12:30:12.422482 CH1 RK0: MR19=303, MR18=90E
8762 12:30:12.428544 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8763 12:30:12.428621
8764 12:30:12.432149 ----->DramcWriteLeveling(PI) begin...
8765 12:30:12.432235 ==
8766 12:30:12.435173 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 12:30:12.438629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 12:30:12.438704 ==
8769 12:30:12.442127 Write leveling (Byte 0): 24 => 24
8770 12:30:12.445276 Write leveling (Byte 1): 27 => 27
8771 12:30:12.448803 DramcWriteLeveling(PI) end<-----
8772 12:30:12.448886
8773 12:30:12.448999 ==
8774 12:30:12.451802 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 12:30:12.458619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 12:30:12.458747 ==
8777 12:30:12.458876 [Gating] SW mode calibration
8778 12:30:12.468553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8779 12:30:12.471702 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8780 12:30:12.474717 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 12:30:12.481579 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8782 12:30:12.484700 1 4 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8783 12:30:12.487809 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8784 12:30:12.494676 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 12:30:12.498249 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 12:30:12.501325 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 12:30:12.508106 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 12:30:12.511105 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 12:30:12.514553 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 12:30:12.521407 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8791 12:30:12.524277 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8792 12:30:12.527717 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 12:30:12.534261 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 12:30:12.537552 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 12:30:12.540958 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 12:30:12.547772 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 12:30:12.550711 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8798 12:30:12.554303 1 6 8 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
8799 12:30:12.560873 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8800 12:30:12.564244 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 12:30:12.567392 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 12:30:12.574261 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 12:30:12.577493 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 12:30:12.580620 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:30:12.587509 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 12:30:12.590686 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8807 12:30:12.593980 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8808 12:30:12.600422 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 12:30:12.603640 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:30:12.606700 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:30:12.613376 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:30:12.617142 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:30:12.620274 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:30:12.626792 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:30:12.630120 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:30:12.633549 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:30:12.639950 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:30:12.642972 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:30:12.646444 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:30:12.652897 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:30:12.656456 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:30:12.660060 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8823 12:30:12.666633 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 12:30:12.666720 Total UI for P1: 0, mck2ui 16
8825 12:30:12.672905 best dqsien dly found for B0: ( 1, 9, 8)
8826 12:30:12.676055 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 12:30:12.679763 Total UI for P1: 0, mck2ui 16
8828 12:30:12.682793 best dqsien dly found for B1: ( 1, 9, 10)
8829 12:30:12.686363 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8830 12:30:12.689458 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8831 12:30:12.689569
8832 12:30:12.692617 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8833 12:30:12.696255 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8834 12:30:12.699429 [Gating] SW calibration Done
8835 12:30:12.699515 ==
8836 12:30:12.702455 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 12:30:12.709412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 12:30:12.709534 ==
8839 12:30:12.709604 RX Vref Scan: 0
8840 12:30:12.709672
8841 12:30:12.712573 RX Vref 0 -> 0, step: 1
8842 12:30:12.712672
8843 12:30:12.715647 RX Delay 0 -> 252, step: 8
8844 12:30:12.718743 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8845 12:30:12.722449 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8846 12:30:12.725442 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8847 12:30:12.728749 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8848 12:30:12.735269 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8849 12:30:12.738683 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8850 12:30:12.741928 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8851 12:30:12.745399 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8852 12:30:12.748877 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8853 12:30:12.755332 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8854 12:30:12.758849 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8855 12:30:12.761798 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8856 12:30:12.765240 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8857 12:30:12.771842 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8858 12:30:12.774863 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8859 12:30:12.778563 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8860 12:30:12.778672 ==
8861 12:30:12.781633 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 12:30:12.785254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 12:30:12.785359 ==
8864 12:30:12.788176 DQS Delay:
8865 12:30:12.788278 DQS0 = 0, DQS1 = 0
8866 12:30:12.791889 DQM Delay:
8867 12:30:12.791993 DQM0 = 129, DQM1 = 127
8868 12:30:12.794909 DQ Delay:
8869 12:30:12.798019 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =131
8870 12:30:12.801695 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8871 12:30:12.804900 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8872 12:30:12.808151 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8873 12:30:12.808263
8874 12:30:12.808358
8875 12:30:12.808422 ==
8876 12:30:12.811320 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 12:30:12.814546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 12:30:12.814661 ==
8879 12:30:12.814757
8880 12:30:12.814854
8881 12:30:12.818247 TX Vref Scan disable
8882 12:30:12.821404 == TX Byte 0 ==
8883 12:30:12.824607 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8884 12:30:12.828247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8885 12:30:12.831480 == TX Byte 1 ==
8886 12:30:12.834550 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8887 12:30:12.837481 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 12:30:12.837565 ==
8889 12:30:12.841237 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 12:30:12.847403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 12:30:12.847489 ==
8892 12:30:12.859138
8893 12:30:12.862708 TX Vref early break, caculate TX vref
8894 12:30:12.866258 TX Vref=16, minBit 0, minWin=23, winSum=382
8895 12:30:12.869136 TX Vref=18, minBit 0, minWin=24, winSum=394
8896 12:30:12.872739 TX Vref=20, minBit 1, minWin=23, winSum=400
8897 12:30:12.876147 TX Vref=22, minBit 0, minWin=24, winSum=411
8898 12:30:12.879026 TX Vref=24, minBit 0, minWin=25, winSum=418
8899 12:30:12.885726 TX Vref=26, minBit 5, minWin=25, winSum=425
8900 12:30:12.888825 TX Vref=28, minBit 1, minWin=25, winSum=429
8901 12:30:12.892589 TX Vref=30, minBit 0, minWin=25, winSum=421
8902 12:30:12.895600 TX Vref=32, minBit 5, minWin=23, winSum=414
8903 12:30:12.898724 TX Vref=34, minBit 0, minWin=24, winSum=404
8904 12:30:12.905627 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 28
8905 12:30:12.905714
8906 12:30:12.908765 Final TX Range 0 Vref 28
8907 12:30:12.908874
8908 12:30:12.908968 ==
8909 12:30:12.911923 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 12:30:12.915133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 12:30:12.915242 ==
8912 12:30:12.915339
8913 12:30:12.915432
8914 12:30:12.918833 TX Vref Scan disable
8915 12:30:12.925016 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8916 12:30:12.925123 == TX Byte 0 ==
8917 12:30:12.928218 u2DelayCellOfst[0]=22 cells (6 PI)
8918 12:30:12.931947 u2DelayCellOfst[1]=15 cells (4 PI)
8919 12:30:12.935183 u2DelayCellOfst[2]=0 cells (0 PI)
8920 12:30:12.938202 u2DelayCellOfst[3]=7 cells (2 PI)
8921 12:30:12.941401 u2DelayCellOfst[4]=11 cells (3 PI)
8922 12:30:12.945151 u2DelayCellOfst[5]=22 cells (6 PI)
8923 12:30:12.948004 u2DelayCellOfst[6]=22 cells (6 PI)
8924 12:30:12.951640 u2DelayCellOfst[7]=7 cells (2 PI)
8925 12:30:12.954762 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8926 12:30:12.957935 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 12:30:12.961413 == TX Byte 1 ==
8928 12:30:12.964360 u2DelayCellOfst[8]=0 cells (0 PI)
8929 12:30:12.967984 u2DelayCellOfst[9]=7 cells (2 PI)
8930 12:30:12.970825 u2DelayCellOfst[10]=15 cells (4 PI)
8931 12:30:12.974496 u2DelayCellOfst[11]=7 cells (2 PI)
8932 12:30:12.977605 u2DelayCellOfst[12]=15 cells (4 PI)
8933 12:30:12.980925 u2DelayCellOfst[13]=18 cells (5 PI)
8934 12:30:12.981088 u2DelayCellOfst[14]=18 cells (5 PI)
8935 12:30:12.983947 u2DelayCellOfst[15]=18 cells (5 PI)
8936 12:30:12.991229 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8937 12:30:12.994025 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8938 12:30:12.997623 DramC Write-DBI on
8939 12:30:12.997706 ==
8940 12:30:13.000764 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 12:30:13.003830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 12:30:13.003914 ==
8943 12:30:13.003979
8944 12:30:13.004039
8945 12:30:13.007161 TX Vref Scan disable
8946 12:30:13.007243 == TX Byte 0 ==
8947 12:30:13.013938 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8948 12:30:13.014034 == TX Byte 1 ==
8949 12:30:13.017129 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8950 12:30:13.020761 DramC Write-DBI off
8951 12:30:13.020843
8952 12:30:13.020908 [DATLAT]
8953 12:30:13.024082 Freq=1600, CH1 RK1
8954 12:30:13.024165
8955 12:30:13.024231 DATLAT Default: 0xf
8956 12:30:13.027209 0, 0xFFFF, sum = 0
8957 12:30:13.027293 1, 0xFFFF, sum = 0
8958 12:30:13.030320 2, 0xFFFF, sum = 0
8959 12:30:13.033904 3, 0xFFFF, sum = 0
8960 12:30:13.034022 4, 0xFFFF, sum = 0
8961 12:30:13.036917 5, 0xFFFF, sum = 0
8962 12:30:13.037008 6, 0xFFFF, sum = 0
8963 12:30:13.040591 7, 0xFFFF, sum = 0
8964 12:30:13.040716 8, 0xFFFF, sum = 0
8965 12:30:13.043620 9, 0xFFFF, sum = 0
8966 12:30:13.043720 10, 0xFFFF, sum = 0
8967 12:30:13.046893 11, 0xFFFF, sum = 0
8968 12:30:13.046977 12, 0xFFFF, sum = 0
8969 12:30:13.050019 13, 0x8FFF, sum = 0
8970 12:30:13.050129 14, 0x0, sum = 1
8971 12:30:13.053690 15, 0x0, sum = 2
8972 12:30:13.053769 16, 0x0, sum = 3
8973 12:30:13.056648 17, 0x0, sum = 4
8974 12:30:13.056724 best_step = 15
8975 12:30:13.056800
8976 12:30:13.056866 ==
8977 12:30:13.060132 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 12:30:13.066272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 12:30:13.066383 ==
8980 12:30:13.066482 RX Vref Scan: 0
8981 12:30:13.066575
8982 12:30:13.070011 RX Vref 0 -> 0, step: 1
8983 12:30:13.070091
8984 12:30:13.072963 RX Delay 3 -> 252, step: 4
8985 12:30:13.076590 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8986 12:30:13.079617 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8987 12:30:13.086403 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8988 12:30:13.089570 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8989 12:30:13.092649 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8990 12:30:13.096082 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8991 12:30:13.099256 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8992 12:30:13.105682 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8993 12:30:13.108793 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8994 12:30:13.112521 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8995 12:30:13.115672 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8996 12:30:13.118937 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8997 12:30:13.125127 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8998 12:30:13.128941 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8999 12:30:13.132007 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
9000 12:30:13.135236 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9001 12:30:13.138305 ==
9002 12:30:13.138400 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 12:30:13.145108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 12:30:13.145193 ==
9005 12:30:13.145276 DQS Delay:
9006 12:30:13.148225 DQS0 = 0, DQS1 = 0
9007 12:30:13.148339 DQM Delay:
9008 12:30:13.151297 DQM0 = 127, DQM1 = 125
9009 12:30:13.151382 DQ Delay:
9010 12:30:13.155051 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9011 12:30:13.158254 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9012 12:30:13.161666 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
9013 12:30:13.164786 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =136
9014 12:30:13.164895
9015 12:30:13.164990
9016 12:30:13.165085
9017 12:30:13.168309 [DramC_TX_OE_Calibration] TA2
9018 12:30:13.171338 Original DQ_B0 (3 6) =30, OEN = 27
9019 12:30:13.175001 Original DQ_B1 (3 6) =30, OEN = 27
9020 12:30:13.177917 24, 0x0, End_B0=24 End_B1=24
9021 12:30:13.181427 25, 0x0, End_B0=25 End_B1=25
9022 12:30:13.181553 26, 0x0, End_B0=26 End_B1=26
9023 12:30:13.184531 27, 0x0, End_B0=27 End_B1=27
9024 12:30:13.188058 28, 0x0, End_B0=28 End_B1=28
9025 12:30:13.191018 29, 0x0, End_B0=29 End_B1=29
9026 12:30:13.194572 30, 0x0, End_B0=30 End_B1=30
9027 12:30:13.194689 31, 0x4141, End_B0=30 End_B1=30
9028 12:30:13.198107 Byte0 end_step=30 best_step=27
9029 12:30:13.200888 Byte1 end_step=30 best_step=27
9030 12:30:13.204351 Byte0 TX OE(2T, 0.5T) = (3, 3)
9031 12:30:13.207707 Byte1 TX OE(2T, 0.5T) = (3, 3)
9032 12:30:13.207819
9033 12:30:13.207903
9034 12:30:13.214209 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9035 12:30:13.217891 CH1 RK1: MR19=303, MR18=F1B
9036 12:30:13.223995 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9037 12:30:13.227246 [RxdqsGatingPostProcess] freq 1600
9038 12:30:13.234087 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9039 12:30:13.237212 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 12:30:13.237289 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 12:30:13.240811 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 12:30:13.243916 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 12:30:13.246974 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 12:30:13.250623 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 12:30:13.253789 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 12:30:13.256931 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 12:30:13.260638 Pre-setting of DQS Precalculation
9048 12:30:13.263790 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9049 12:30:13.273368 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9050 12:30:13.279866 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 12:30:13.279952
9052 12:30:13.280065
9053 12:30:13.283466 [Calibration Summary] 3200 Mbps
9054 12:30:13.283573 CH 0, Rank 0
9055 12:30:13.286487 SW Impedance : PASS
9056 12:30:13.289948 DUTY Scan : NO K
9057 12:30:13.290029 ZQ Calibration : PASS
9058 12:30:13.293693 Jitter Meter : NO K
9059 12:30:13.293797 CBT Training : PASS
9060 12:30:13.296714 Write leveling : PASS
9061 12:30:13.299787 RX DQS gating : PASS
9062 12:30:13.299861 RX DQ/DQS(RDDQC) : PASS
9063 12:30:13.303049 TX DQ/DQS : PASS
9064 12:30:13.306692 RX DATLAT : PASS
9065 12:30:13.306795 RX DQ/DQS(Engine): PASS
9066 12:30:13.309686 TX OE : PASS
9067 12:30:13.309793 All Pass.
9068 12:30:13.309886
9069 12:30:13.313403 CH 0, Rank 1
9070 12:30:13.313507 SW Impedance : PASS
9071 12:30:13.316378 DUTY Scan : NO K
9072 12:30:13.319885 ZQ Calibration : PASS
9073 12:30:13.319987 Jitter Meter : NO K
9074 12:30:13.322739 CBT Training : PASS
9075 12:30:13.326455 Write leveling : PASS
9076 12:30:13.326557 RX DQS gating : PASS
9077 12:30:13.329686 RX DQ/DQS(RDDQC) : PASS
9078 12:30:13.332762 TX DQ/DQS : PASS
9079 12:30:13.332861 RX DATLAT : PASS
9080 12:30:13.335849 RX DQ/DQS(Engine): PASS
9081 12:30:13.339667 TX OE : PASS
9082 12:30:13.339752 All Pass.
9083 12:30:13.339837
9084 12:30:13.339899 CH 1, Rank 0
9085 12:30:13.342719 SW Impedance : PASS
9086 12:30:13.345691 DUTY Scan : NO K
9087 12:30:13.345789 ZQ Calibration : PASS
9088 12:30:13.348877 Jitter Meter : NO K
9089 12:30:13.352597 CBT Training : PASS
9090 12:30:13.352702 Write leveling : PASS
9091 12:30:13.355707 RX DQS gating : PASS
9092 12:30:13.358858 RX DQ/DQS(RDDQC) : PASS
9093 12:30:13.358971 TX DQ/DQS : PASS
9094 12:30:13.362529 RX DATLAT : PASS
9095 12:30:13.365636 RX DQ/DQS(Engine): PASS
9096 12:30:13.365735 TX OE : PASS
9097 12:30:13.368770 All Pass.
9098 12:30:13.368869
9099 12:30:13.368958 CH 1, Rank 1
9100 12:30:13.372408 SW Impedance : PASS
9101 12:30:13.372481 DUTY Scan : NO K
9102 12:30:13.375390 ZQ Calibration : PASS
9103 12:30:13.378907 Jitter Meter : NO K
9104 12:30:13.379007 CBT Training : PASS
9105 12:30:13.382189 Write leveling : PASS
9106 12:30:13.385132 RX DQS gating : PASS
9107 12:30:13.385233 RX DQ/DQS(RDDQC) : PASS
9108 12:30:13.388653 TX DQ/DQS : PASS
9109 12:30:13.391688 RX DATLAT : PASS
9110 12:30:13.391794 RX DQ/DQS(Engine): PASS
9111 12:30:13.395049 TX OE : PASS
9112 12:30:13.395156 All Pass.
9113 12:30:13.395251
9114 12:30:13.398209 DramC Write-DBI on
9115 12:30:13.401760 PER_BANK_REFRESH: Hybrid Mode
9116 12:30:13.401863 TX_TRACKING: ON
9117 12:30:13.411715 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9118 12:30:13.418321 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9119 12:30:13.425074 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9120 12:30:13.428102 [FAST_K] Save calibration result to emmc
9121 12:30:13.431092 sync common calibartion params.
9122 12:30:13.434661 sync cbt_mode0:1, 1:1
9123 12:30:13.437796 dram_init: ddr_geometry: 2
9124 12:30:13.437912 dram_init: ddr_geometry: 2
9125 12:30:13.441043 dram_init: ddr_geometry: 2
9126 12:30:13.444814 0:dram_rank_size:100000000
9127 12:30:13.447972 1:dram_rank_size:100000000
9128 12:30:13.451184 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9129 12:30:13.454297 DFS_SHUFFLE_HW_MODE: ON
9130 12:30:13.457471 dramc_set_vcore_voltage set vcore to 725000
9131 12:30:13.460772 Read voltage for 1600, 0
9132 12:30:13.460878 Vio18 = 0
9133 12:30:13.460970 Vcore = 725000
9134 12:30:13.464346 Vdram = 0
9135 12:30:13.464445 Vddq = 0
9136 12:30:13.464550 Vmddr = 0
9137 12:30:13.467560 switch to 3200 Mbps bootup
9138 12:30:13.470568 [DramcRunTimeConfig]
9139 12:30:13.470663 PHYPLL
9140 12:30:13.470754 DPM_CONTROL_AFTERK: ON
9141 12:30:13.474274 PER_BANK_REFRESH: ON
9142 12:30:13.477428 REFRESH_OVERHEAD_REDUCTION: ON
9143 12:30:13.477523 CMD_PICG_NEW_MODE: OFF
9144 12:30:13.480568 XRTWTW_NEW_MODE: ON
9145 12:30:13.483642 XRTRTR_NEW_MODE: ON
9146 12:30:13.483728 TX_TRACKING: ON
9147 12:30:13.487143 RDSEL_TRACKING: OFF
9148 12:30:13.487214 DQS Precalculation for DVFS: ON
9149 12:30:13.490388 RX_TRACKING: OFF
9150 12:30:13.490458 HW_GATING DBG: ON
9151 12:30:13.493784 ZQCS_ENABLE_LP4: ON
9152 12:30:13.497328 RX_PICG_NEW_MODE: ON
9153 12:30:13.497406 TX_PICG_NEW_MODE: ON
9154 12:30:13.500139 ENABLE_RX_DCM_DPHY: ON
9155 12:30:13.503797 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9156 12:30:13.503883 DUMMY_READ_FOR_TRACKING: OFF
9157 12:30:13.507325 !!! SPM_CONTROL_AFTERK: OFF
9158 12:30:13.510177 !!! SPM could not control APHY
9159 12:30:13.513770 IMPEDANCE_TRACKING: ON
9160 12:30:13.513870 TEMP_SENSOR: ON
9161 12:30:13.517099 HW_SAVE_FOR_SR: OFF
9162 12:30:13.519984 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9163 12:30:13.523594 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9164 12:30:13.523680 Read ODT Tracking: ON
9165 12:30:13.526580 Refresh Rate DeBounce: ON
9166 12:30:13.530148 DFS_NO_QUEUE_FLUSH: ON
9167 12:30:13.533273 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9168 12:30:13.533373 ENABLE_DFS_RUNTIME_MRW: OFF
9169 12:30:13.536342 DDR_RESERVE_NEW_MODE: ON
9170 12:30:13.540081 MR_CBT_SWITCH_FREQ: ON
9171 12:30:13.540185 =========================
9172 12:30:13.559706 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9173 12:30:13.563438 dram_init: ddr_geometry: 2
9174 12:30:13.581526 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9175 12:30:13.584669 dram_init: dram init end (result: 0)
9176 12:30:13.591332 DRAM-K: Full calibration passed in 24617 msecs
9177 12:30:13.594414 MRC: failed to locate region type 0.
9178 12:30:13.594499 DRAM rank0 size:0x100000000,
9179 12:30:13.597620 DRAM rank1 size=0x100000000
9180 12:30:13.607891 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9181 12:30:13.617450 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9182 12:30:13.624398 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9183 12:30:13.630684 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9184 12:30:13.630812 DRAM rank0 size:0x100000000,
9185 12:30:13.633664 DRAM rank1 size=0x100000000
9186 12:30:13.633774 CBMEM:
9187 12:30:13.637477 IMD: root @ 0xfffff000 254 entries.
9188 12:30:13.640548 IMD: root @ 0xffffec00 62 entries.
9189 12:30:13.647378 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9190 12:30:13.650454 WARNING: RO_VPD is uninitialized or empty.
9191 12:30:13.653692 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9192 12:30:13.661400 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9193 12:30:13.674040 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9194 12:30:13.685844 BS: romstage times (exec / console): total (unknown) / 24076 ms
9195 12:30:13.685931
9196 12:30:13.685998
9197 12:30:13.695661 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9198 12:30:13.698860 ARM64: Exception handlers installed.
9199 12:30:13.701960 ARM64: Testing exception
9200 12:30:13.705560 ARM64: Done test exception
9201 12:30:13.705670 Enumerating buses...
9202 12:30:13.708947 Show all devs... Before device enumeration.
9203 12:30:13.712020 Root Device: enabled 1
9204 12:30:13.715641 CPU_CLUSTER: 0: enabled 1
9205 12:30:13.715724 CPU: 00: enabled 1
9206 12:30:13.718685 Compare with tree...
9207 12:30:13.718791 Root Device: enabled 1
9208 12:30:13.721722 CPU_CLUSTER: 0: enabled 1
9209 12:30:13.725225 CPU: 00: enabled 1
9210 12:30:13.725329 Root Device scanning...
9211 12:30:13.728760 scan_static_bus for Root Device
9212 12:30:13.731825 CPU_CLUSTER: 0 enabled
9213 12:30:13.735242 scan_static_bus for Root Device done
9214 12:30:13.738177 scan_bus: bus Root Device finished in 8 msecs
9215 12:30:13.738283 done
9216 12:30:13.745028 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9217 12:30:13.748144 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9218 12:30:13.755017 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9219 12:30:13.761197 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9220 12:30:13.761311 Allocating resources...
9221 12:30:13.764341 Reading resources...
9222 12:30:13.767963 Root Device read_resources bus 0 link: 0
9223 12:30:13.770975 DRAM rank0 size:0x100000000,
9224 12:30:13.771049 DRAM rank1 size=0x100000000
9225 12:30:13.777837 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9226 12:30:13.777914 CPU: 00 missing read_resources
9227 12:30:13.784488 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9228 12:30:13.787692 Root Device read_resources bus 0 link: 0 done
9229 12:30:13.790755 Done reading resources.
9230 12:30:13.794621 Show resources in subtree (Root Device)...After reading.
9231 12:30:13.797681 Root Device child on link 0 CPU_CLUSTER: 0
9232 12:30:13.800709 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 12:30:13.810501 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 12:30:13.810581 CPU: 00
9235 12:30:13.816893 Root Device assign_resources, bus 0 link: 0
9236 12:30:13.820494 CPU_CLUSTER: 0 missing set_resources
9237 12:30:13.823892 Root Device assign_resources, bus 0 link: 0 done
9238 12:30:13.827366 Done setting resources.
9239 12:30:13.830416 Show resources in subtree (Root Device)...After assigning values.
9240 12:30:13.836902 Root Device child on link 0 CPU_CLUSTER: 0
9241 12:30:13.840377 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 12:30:13.846647 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 12:30:13.850242 CPU: 00
9244 12:30:13.850327 Done allocating resources.
9245 12:30:13.856655 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9246 12:30:13.860276 Enabling resources...
9247 12:30:13.860360 done.
9248 12:30:13.863455 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9249 12:30:13.866657 Initializing devices...
9250 12:30:13.866742 Root Device init
9251 12:30:13.869732 init hardware done!
9252 12:30:13.873319 0x00000018: ctrlr->caps
9253 12:30:13.873406 52.000 MHz: ctrlr->f_max
9254 12:30:13.876385 0.400 MHz: ctrlr->f_min
9255 12:30:13.879417 0x40ff8080: ctrlr->voltages
9256 12:30:13.879502 sclk: 390625
9257 12:30:13.879569 Bus Width = 1
9258 12:30:13.883280 sclk: 390625
9259 12:30:13.883365 Bus Width = 1
9260 12:30:13.886401 Early init status = 3
9261 12:30:13.889418 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9262 12:30:13.893310 in-header: 03 fc 00 00 01 00 00 00
9263 12:30:13.896434 in-data: 00
9264 12:30:13.899576 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9265 12:30:13.904376 in-header: 03 fd 00 00 00 00 00 00
9266 12:30:13.907598 in-data:
9267 12:30:13.911135 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9268 12:30:13.914305 in-header: 03 fc 00 00 01 00 00 00
9269 12:30:13.918055 in-data: 00
9270 12:30:13.920947 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9271 12:30:13.926017 in-header: 03 fd 00 00 00 00 00 00
9272 12:30:13.928758 in-data:
9273 12:30:13.932084 [SSUSB] Setting up USB HOST controller...
9274 12:30:13.935704 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 12:30:13.938778 [SSUSB] phy power-on done.
9276 12:30:13.942338 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 12:30:13.949023 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 12:30:13.951998 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 12:30:13.958981 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 12:30:13.965208 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9281 12:30:13.972067 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 12:30:13.978259 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 12:30:13.985175 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9284 12:30:13.988261 SPM: binary array size = 0x9dc
9285 12:30:13.991296 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 12:30:13.998121 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 12:30:14.004927 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 12:30:14.011668 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 12:30:14.014856 configure_display: Starting display init
9290 12:30:14.049095 anx7625_power_on_init: Init interface.
9291 12:30:14.052232 anx7625_disable_pd_protocol: Disabled PD feature.
9292 12:30:14.055639 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 12:30:14.083352 anx7625_start_dp_work: Secure OCM version=00
9294 12:30:14.086387 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 12:30:14.101430 sp_tx_get_edid_block: EDID Block = 1
9296 12:30:14.204130 Extracted contents:
9297 12:30:14.207179 header: 00 ff ff ff ff ff ff 00
9298 12:30:14.210758 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 12:30:14.213847 version: 01 04
9300 12:30:14.217505 basic params: 95 1f 11 78 0a
9301 12:30:14.220684 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 12:30:14.223818 established: 00 00 00
9303 12:30:14.230492 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 12:30:14.233600 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 12:30:14.240220 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 12:30:14.246802 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 12:30:14.253927 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 12:30:14.256627 extensions: 00
9309 12:30:14.256706 checksum: fb
9310 12:30:14.256770
9311 12:30:14.263647 Manufacturer: IVO Model 57d Serial Number 0
9312 12:30:14.263745 Made week 0 of 2020
9313 12:30:14.266692 EDID version: 1.4
9314 12:30:14.266761 Digital display
9315 12:30:14.270137 6 bits per primary color channel
9316 12:30:14.270221 DisplayPort interface
9317 12:30:14.273151 Maximum image size: 31 cm x 17 cm
9318 12:30:14.276723 Gamma: 220%
9319 12:30:14.276804 Check DPMS levels
9320 12:30:14.283320 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 12:30:14.286387 First detailed timing is preferred timing
9322 12:30:14.286470 Established timings supported:
9323 12:30:14.290039 Standard timings supported:
9324 12:30:14.293080 Detailed timings
9325 12:30:14.296099 Hex of detail: 383680a07038204018303c0035ae10000019
9326 12:30:14.302840 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 12:30:14.305900 0780 0798 07c8 0820 hborder 0
9328 12:30:14.309723 0438 043b 0447 0458 vborder 0
9329 12:30:14.312889 -hsync -vsync
9330 12:30:14.312966 Did detailed timing
9331 12:30:14.319354 Hex of detail: 000000000000000000000000000000000000
9332 12:30:14.323043 Manufacturer-specified data, tag 0
9333 12:30:14.326145 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 12:30:14.329235 ASCII string: InfoVision
9335 12:30:14.332464 Hex of detail: 000000fe00523134304e574635205248200a
9336 12:30:14.336053 ASCII string: R140NWF5 RH
9337 12:30:14.336127 Checksum
9338 12:30:14.339029 Checksum: 0xfb (valid)
9339 12:30:14.342720 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 12:30:14.345897 DSI data_rate: 832800000 bps
9341 12:30:14.352558 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 12:30:14.355605 anx7625_parse_edid: pixelclock(138800).
9343 12:30:14.359715 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 12:30:14.362408 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 12:30:14.365551 anx7625_dsi_config: config dsi.
9346 12:30:14.372796 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 12:30:14.386173 anx7625_dsi_config: success to config DSI
9348 12:30:14.389591 anx7625_dp_start: MIPI phy setup OK.
9349 12:30:14.392606 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 12:30:14.395948 mtk_ddp_mode_set invalid vrefresh 60
9351 12:30:14.399040 main_disp_path_setup
9352 12:30:14.399155 ovl_layer_smi_id_en
9353 12:30:14.402606 ovl_layer_smi_id_en
9354 12:30:14.402748 ccorr_config
9355 12:30:14.402866 aal_config
9356 12:30:14.405653 gamma_config
9357 12:30:14.405750 postmask_config
9358 12:30:14.408865 dither_config
9359 12:30:14.412045 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 12:30:14.419066 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 12:30:14.422111 Root Device init finished in 551 msecs
9362 12:30:14.425229 CPU_CLUSTER: 0 init
9363 12:30:14.432071 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 12:30:14.438432 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 12:30:14.438516 APU_MBOX 0x190000b0 = 0x10001
9366 12:30:14.442050 APU_MBOX 0x190001b0 = 0x10001
9367 12:30:14.445167 APU_MBOX 0x190005b0 = 0x10001
9368 12:30:14.448243 APU_MBOX 0x190006b0 = 0x10001
9369 12:30:14.454993 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 12:30:14.465064 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9371 12:30:14.477649 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 12:30:14.484117 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 12:30:14.495717 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9374 12:30:14.504937 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 12:30:14.507909 CPU_CLUSTER: 0 init finished in 81 msecs
9376 12:30:14.511573 Devices initialized
9377 12:30:14.514595 Show all devs... After init.
9378 12:30:14.514705 Root Device: enabled 1
9379 12:30:14.518310 CPU_CLUSTER: 0: enabled 1
9380 12:30:14.521522 CPU: 00: enabled 1
9381 12:30:14.524675 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9382 12:30:14.527654 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 12:30:14.531373 ELOG: NV offset 0x57f000 size 0x1000
9384 12:30:14.538293 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9385 12:30:14.544319 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 12:30:14.548036 ELOG: Event(17) added with size 13 at 2023-06-06 12:30:14 UTC
9387 12:30:14.554700 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 12:30:14.557658 in-header: 03 2b 00 00 2c 00 00 00
9389 12:30:14.567694 in-data: 33 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 12:30:14.573957 ELOG: Event(A1) added with size 10 at 2023-06-06 12:30:14 UTC
9391 12:30:14.580684 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 12:30:14.587322 ELOG: Event(A0) added with size 9 at 2023-06-06 12:30:14 UTC
9393 12:30:14.590791 elog_add_boot_reason: Logged dev mode boot
9394 12:30:14.597328 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9395 12:30:14.597437 Finalize devices...
9396 12:30:14.600406 Devices finalized
9397 12:30:14.603860 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 12:30:14.606762 Writing coreboot table at 0xffe64000
9399 12:30:14.610491 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 12:30:14.616777 1. 0000000040000000-00000000400fffff: RAM
9401 12:30:14.620457 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 12:30:14.623528 3. 000000004032b000-00000000545fffff: RAM
9403 12:30:14.626629 4. 0000000054600000-000000005465ffff: BL31
9404 12:30:14.630231 5. 0000000054660000-00000000ffe63fff: RAM
9405 12:30:14.636474 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 12:30:14.640154 7. 0000000100000000-000000023fffffff: RAM
9407 12:30:14.643244 Passing 5 GPIOs to payload:
9408 12:30:14.646336 NAME | PORT | POLARITY | VALUE
9409 12:30:14.653109 EC in RW | 0x000000aa | low | undefined
9410 12:30:14.656779 EC interrupt | 0x00000005 | low | undefined
9411 12:30:14.659822 TPM interrupt | 0x000000ab | high | undefined
9412 12:30:14.666334 SD card detect | 0x00000011 | high | undefined
9413 12:30:14.670080 speaker enable | 0x00000093 | high | undefined
9414 12:30:14.673223 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 12:30:14.676486 in-header: 03 f9 00 00 02 00 00 00
9416 12:30:14.679656 in-data: 02 00
9417 12:30:14.683309 ADC[4]: Raw value=895930 ID=7
9418 12:30:14.686363 ADC[3]: Raw value=212330 ID=1
9419 12:30:14.686444 RAM Code: 0x71
9420 12:30:14.689453 ADC[6]: Raw value=74722 ID=0
9421 12:30:14.692884 ADC[5]: Raw value=212330 ID=1
9422 12:30:14.692970 SKU Code: 0x1
9423 12:30:14.699418 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9424 12:30:14.699505 coreboot table: 964 bytes.
9425 12:30:14.702449 IMD ROOT 0. 0xfffff000 0x00001000
9426 12:30:14.706078 IMD SMALL 1. 0xffffe000 0x00001000
9427 12:30:14.708966 RO MCACHE 2. 0xffffc000 0x00001104
9428 12:30:14.712423 CONSOLE 3. 0xfff7c000 0x00080000
9429 12:30:14.716305 FMAP 4. 0xfff7b000 0x00000452
9430 12:30:14.718922 TIME STAMP 5. 0xfff7a000 0x00000910
9431 12:30:14.722563 VBOOT WORK 6. 0xfff66000 0x00014000
9432 12:30:14.725570 RAMOOPS 7. 0xffe66000 0x00100000
9433 12:30:14.728726 COREBOOT 8. 0xffe64000 0x00002000
9434 12:30:14.732289 IMD small region:
9435 12:30:14.735276 IMD ROOT 0. 0xffffec00 0x00000400
9436 12:30:14.738903 VPD 1. 0xffffeba0 0x0000004c
9437 12:30:14.742016 MMC STATUS 2. 0xffffeb80 0x00000004
9438 12:30:14.748801 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 12:30:14.748875 Probing TPM: done!
9440 12:30:14.755431 Connected to device vid:did:rid of 1ae0:0028:00
9441 12:30:14.761694 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9442 12:30:14.765295 Initialized TPM device CR50 revision 0
9443 12:30:14.769302 Checking cr50 for pending updates
9444 12:30:14.774611 Reading cr50 TPM mode
9445 12:30:14.783305 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 12:30:14.789905 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 12:30:14.830066 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9448 12:30:14.833326 Checking segment from ROM address 0x40100000
9449 12:30:14.836540 Checking segment from ROM address 0x4010001c
9450 12:30:14.843097 Loading segment from ROM address 0x40100000
9451 12:30:14.843209 code (compression=0)
9452 12:30:14.853065 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 12:30:14.859487 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 12:30:14.859572 it's not compressed!
9455 12:30:14.866199 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 12:30:14.872879 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 12:30:14.890434 Loading segment from ROM address 0x4010001c
9458 12:30:14.890519 Entry Point 0x80000000
9459 12:30:14.893488 Loaded segments
9460 12:30:14.896663 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 12:30:14.903393 Jumping to boot code at 0x80000000(0xffe64000)
9462 12:30:14.909928 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 12:30:14.916524 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 12:30:14.924504 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9465 12:30:14.927669 Checking segment from ROM address 0x40100000
9466 12:30:14.931197 Checking segment from ROM address 0x4010001c
9467 12:30:14.937717 Loading segment from ROM address 0x40100000
9468 12:30:14.937826 code (compression=1)
9469 12:30:14.944633 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 12:30:14.954643 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 12:30:14.954726 using LZMA
9472 12:30:14.962833 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 12:30:14.969659 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 12:30:14.973214 Loading segment from ROM address 0x4010001c
9475 12:30:14.973297 Entry Point 0x54601000
9476 12:30:14.976255 Loaded segments
9477 12:30:14.979472 NOTICE: MT8192 bl31_setup
9478 12:30:14.986947 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 12:30:14.990094 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 12:30:14.993171 WARNING: region 0:
9481 12:30:14.996241 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 12:30:14.996325 WARNING: region 1:
9483 12:30:15.003163 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 12:30:15.006204 WARNING: region 2:
9485 12:30:15.009849 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 12:30:15.012894 WARNING: region 3:
9487 12:30:15.016314 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 12:30:15.019725 WARNING: region 4:
9489 12:30:15.026666 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 12:30:15.026766 WARNING: region 5:
9491 12:30:15.029498 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 12:30:15.033192 WARNING: region 6:
9493 12:30:15.036218 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 12:30:15.039863 WARNING: region 7:
9495 12:30:15.043031 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 12:30:15.049441 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 12:30:15.053097 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 12:30:15.056144 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 12:30:15.063023 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 12:30:15.066105 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 12:30:15.069534 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 12:30:15.076398 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 12:30:15.079516 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 12:30:15.086401 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 12:30:15.089433 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 12:30:15.093074 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 12:30:15.099358 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 12:30:15.102571 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 12:30:15.106235 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 12:30:15.112754 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 12:30:15.115791 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 12:30:15.122525 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 12:30:15.126048 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 12:30:15.129496 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 12:30:15.136009 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 12:30:15.139114 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 12:30:15.145829 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 12:30:15.148971 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 12:30:15.152605 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 12:30:15.159153 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 12:30:15.162215 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 12:30:15.169020 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 12:30:15.171906 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 12:30:15.175317 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 12:30:15.182230 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 12:30:15.185392 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 12:30:15.192140 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 12:30:15.195249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 12:30:15.198376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 12:30:15.202206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 12:30:15.208352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 12:30:15.212091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 12:30:15.215171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 12:30:15.219130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 12:30:15.224897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 12:30:15.228634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 12:30:15.231865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 12:30:15.235250 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 12:30:15.241656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 12:30:15.245217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 12:30:15.248339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 12:30:15.254959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 12:30:15.258647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 12:30:15.261721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 12:30:15.268293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 12:30:15.271365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 12:30:15.275060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 12:30:15.281811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 12:30:15.284932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 12:30:15.291628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 12:30:15.294674 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 12:30:15.301346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 12:30:15.304523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 12:30:15.311532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 12:30:15.314593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 12:30:15.317680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 12:30:15.324739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 12:30:15.328147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 12:30:15.334007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 12:30:15.337638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 12:30:15.343992 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 12:30:15.347536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 12:30:15.354152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 12:30:15.357875 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 12:30:15.360810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 12:30:15.367393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 12:30:15.370426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 12:30:15.377375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 12:30:15.381484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 12:30:15.387123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 12:30:15.390675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 12:30:15.397427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 12:30:15.400613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 12:30:15.404289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 12:30:15.410479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 12:30:15.414040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 12:30:15.420215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 12:30:15.423991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 12:30:15.430160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 12:30:15.433710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 12:30:15.437299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 12:30:15.443806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 12:30:15.447492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 12:30:15.453705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 12:30:15.457248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 12:30:15.463918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 12:30:15.466926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 12:30:15.473611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 12:30:15.476637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 12:30:15.480403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 12:30:15.487075 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 12:30:15.490288 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 12:30:15.493150 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 12:30:15.500106 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 12:30:15.503276 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 12:30:15.506909 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 12:30:15.513234 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 12:30:15.516920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 12:30:15.520080 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 12:30:15.526735 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 12:30:15.529831 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 12:30:15.536619 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 12:30:15.539718 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 12:30:15.546560 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 12:30:15.549540 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 12:30:15.553063 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 12:30:15.559469 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 12:30:15.562746 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 12:30:15.569804 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 12:30:15.572956 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 12:30:15.575983 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 12:30:15.579574 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 12:30:15.586241 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 12:30:15.589263 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 12:30:15.593012 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 12:30:15.599586 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 12:30:15.602688 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 12:30:15.605820 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 12:30:15.609484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 12:30:15.615812 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 12:30:15.618934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 12:30:15.625665 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 12:30:15.629285 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 12:30:15.635507 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 12:30:15.639374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 12:30:15.642420 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 12:30:15.649052 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 12:30:15.652232 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 12:30:15.655738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 12:30:15.662367 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 12:30:15.665264 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 12:30:15.672205 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 12:30:15.675271 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 12:30:15.678800 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 12:30:15.685471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 12:30:15.688980 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 12:30:15.695441 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 12:30:15.698709 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 12:30:15.702164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 12:30:15.708866 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 12:30:15.711959 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 12:30:15.718677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 12:30:15.721809 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 12:30:15.724898 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 12:30:15.731720 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 12:30:15.734785 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 12:30:15.741482 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 12:30:15.745026 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 12:30:15.748446 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 12:30:15.754787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 12:30:15.758433 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 12:30:15.764987 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 12:30:15.768478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 12:30:15.771478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 12:30:15.778261 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 12:30:15.781359 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 12:30:15.784985 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 12:30:15.791091 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 12:30:15.794625 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 12:30:15.800954 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 12:30:15.804484 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 12:30:15.808019 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 12:30:15.814450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 12:30:15.817755 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 12:30:15.823875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 12:30:15.827678 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 12:30:15.833870 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 12:30:15.837648 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 12:30:15.840770 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 12:30:15.846925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 12:30:15.850762 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 12:30:15.857005 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 12:30:15.860622 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 12:30:15.864036 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 12:30:15.870375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 12:30:15.873785 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 12:30:15.880305 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 12:30:15.883167 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 12:30:15.886786 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 12:30:15.893419 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 12:30:15.896503 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 12:30:15.903130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 12:30:15.906707 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 12:30:15.909849 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 12:30:15.916481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 12:30:15.919627 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 12:30:15.926439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 12:30:15.929703 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 12:30:15.936474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 12:30:15.939473 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 12:30:15.942616 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 12:30:15.949353 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 12:30:15.952509 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 12:30:15.959287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 12:30:15.962336 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 12:30:15.969247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 12:30:15.972214 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 12:30:15.975788 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 12:30:15.982520 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 12:30:15.985322 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 12:30:15.992145 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 12:30:15.995213 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 12:30:16.001855 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 12:30:16.005370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 12:30:16.008875 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 12:30:16.015368 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 12:30:16.018341 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 12:30:16.024973 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 12:30:16.028098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 12:30:16.035048 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 12:30:16.038182 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 12:30:16.041246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 12:30:16.048061 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 12:30:16.051210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 12:30:16.058086 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 12:30:16.061172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 12:30:16.064780 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 12:30:16.071012 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 12:30:16.074621 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 12:30:16.080960 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 12:30:16.084438 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 12:30:16.090927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 12:30:16.094294 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 12:30:16.097815 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 12:30:16.103989 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 12:30:16.107576 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 12:30:16.110612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 12:30:16.114204 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 12:30:16.120770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 12:30:16.124158 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 12:30:16.127191 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 12:30:16.134048 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 12:30:16.137490 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 12:30:16.144068 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 12:30:16.147201 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 12:30:16.150297 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 12:30:16.156622 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 12:30:16.160354 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 12:30:16.163597 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 12:30:16.170387 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 12:30:16.173589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 12:30:16.179930 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 12:30:16.183158 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 12:30:16.186644 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 12:30:16.192983 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 12:30:16.196451 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 12:30:16.202806 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 12:30:16.206155 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 12:30:16.209860 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 12:30:16.216071 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 12:30:16.219625 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 12:30:16.222533 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 12:30:16.229359 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 12:30:16.232744 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 12:30:16.235696 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 12:30:16.242607 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 12:30:16.246370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 12:30:16.252526 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 12:30:16.255700 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 12:30:16.259279 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 12:30:16.265996 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 12:30:16.269098 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 12:30:16.272837 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 12:30:16.279062 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 12:30:16.282174 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 12:30:16.286083 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 12:30:16.289208 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 12:30:16.296123 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 12:30:16.299077 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 12:30:16.302273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 12:30:16.305086 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 12:30:16.311597 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 12:30:16.315253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 12:30:16.318270 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 12:30:16.322023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 12:30:16.328154 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 12:30:16.331653 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 12:30:16.335088 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 12:30:16.341904 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 12:30:16.344977 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 12:30:16.351209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 12:30:16.355026 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 12:30:16.361271 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 12:30:16.364363 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 12:30:16.368063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 12:30:16.374310 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 12:30:16.378096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 12:30:16.384284 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 12:30:16.387417 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 12:30:16.394085 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 12:30:16.397774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 12:30:16.403996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 12:30:16.407403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 12:30:16.410833 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 12:30:16.417536 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 12:30:16.420288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 12:30:16.427119 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 12:30:16.430665 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 12:30:16.433647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 12:30:16.440464 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 12:30:16.443491 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 12:30:16.450230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 12:30:16.453205 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 12:30:16.456856 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 12:30:16.463128 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 12:30:16.466497 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 12:30:16.472923 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 12:30:16.476199 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 12:30:16.482717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 12:30:16.486435 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 12:30:16.489731 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 12:30:16.496377 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 12:30:16.499433 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 12:30:16.505653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 12:30:16.509281 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 12:30:16.515725 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 12:30:16.519404 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 12:30:16.522841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 12:30:16.528924 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 12:30:16.532462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 12:30:16.539164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 12:30:16.542152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 12:30:16.545726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 12:30:16.552265 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 12:30:16.555686 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 12:30:16.562327 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 12:30:16.565730 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 12:30:16.568857 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 12:30:16.575700 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 12:30:16.578685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 12:30:16.585402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 12:30:16.588581 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 12:30:16.592185 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 12:30:16.598458 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 12:30:16.601565 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 12:30:16.608424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 12:30:16.611546 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 12:30:16.618230 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 12:30:16.621497 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 12:30:16.628344 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 12:30:16.631246 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 12:30:16.634839 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 12:30:16.641370 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 12:30:16.644406 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 12:30:16.651268 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 12:30:16.654848 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 12:30:16.657757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 12:30:16.664298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 12:30:16.667737 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 12:30:16.674660 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 12:30:16.677688 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 12:30:16.684333 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 12:30:16.687466 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 12:30:16.694183 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 12:30:16.697264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 12:30:16.700882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 12:30:16.707132 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 12:30:16.710741 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 12:30:16.717045 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 12:30:16.720653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 12:30:16.726742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 12:30:16.730407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 12:30:16.737068 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 12:30:16.739946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 12:30:16.743409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 12:30:16.750098 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 12:30:16.753474 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 12:30:16.759986 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 12:30:16.762905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 12:30:16.769909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 12:30:16.773239 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 12:30:16.779329 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 12:30:16.782633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 12:30:16.786126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 12:30:16.792364 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 12:30:16.796066 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 12:30:16.802413 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 12:30:16.806122 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 12:30:16.812548 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 12:30:16.815676 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 12:30:16.822414 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 12:30:16.825438 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 12:30:16.828633 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 12:30:16.835513 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 12:30:16.838703 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 12:30:16.845445 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 12:30:16.848669 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 12:30:16.855403 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 12:30:16.858182 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 12:30:16.864989 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 12:30:16.868151 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 12:30:16.875020 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 12:30:16.877993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 12:30:16.881444 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 12:30:16.887939 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 12:30:16.891462 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 12:30:16.898018 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 12:30:16.901178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 12:30:16.904262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 12:30:16.911000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 12:30:16.914679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 12:30:16.920837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 12:30:16.924030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 12:30:16.930680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 12:30:16.934380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 12:30:16.940638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 12:30:16.943674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 12:30:16.950430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 12:30:16.953983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 12:30:16.960325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 12:30:16.963840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 12:30:16.970235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 12:30:16.973300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 12:30:16.980103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 12:30:16.983711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 12:30:16.990173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 12:30:16.993039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 12:30:17.000002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 12:30:17.002984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 12:30:17.010071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 12:30:17.013217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 12:30:17.019434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 12:30:17.023313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 12:30:17.029661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 12:30:17.032750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 12:30:17.039795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 12:30:17.043019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 12:30:17.049875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 12:30:17.053115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 12:30:17.059275 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 12:30:17.059389 INFO: [APUAPC] vio 0
9932 12:30:17.066391 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 12:30:17.069990 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 12:30:17.072874 INFO: [APUAPC] D0_APC_0: 0x400510
9935 12:30:17.076542 INFO: [APUAPC] D0_APC_1: 0x0
9936 12:30:17.079570 INFO: [APUAPC] D0_APC_2: 0x1540
9937 12:30:17.083195 INFO: [APUAPC] D0_APC_3: 0x0
9938 12:30:17.086295 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 12:30:17.089332 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 12:30:17.092880 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 12:30:17.096459 INFO: [APUAPC] D1_APC_3: 0x0
9942 12:30:17.099690 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 12:30:17.102937 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 12:30:17.105839 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 12:30:17.109276 INFO: [APUAPC] D2_APC_3: 0x0
9946 12:30:17.112812 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 12:30:17.115902 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 12:30:17.119741 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 12:30:17.122679 INFO: [APUAPC] D3_APC_3: 0x0
9950 12:30:17.125813 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 12:30:17.128992 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 12:30:17.132720 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 12:30:17.135716 INFO: [APUAPC] D4_APC_3: 0x0
9954 12:30:17.139229 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 12:30:17.142340 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 12:30:17.145423 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 12:30:17.149191 INFO: [APUAPC] D5_APC_3: 0x0
9958 12:30:17.152262 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 12:30:17.155447 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 12:30:17.158662 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 12:30:17.161774 INFO: [APUAPC] D6_APC_3: 0x0
9962 12:30:17.165387 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 12:30:17.168401 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 12:30:17.172031 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 12:30:17.172133 INFO: [APUAPC] D7_APC_3: 0x0
9966 12:30:17.178536 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 12:30:17.182013 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 12:30:17.184939 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 12:30:17.185015 INFO: [APUAPC] D8_APC_3: 0x0
9970 12:30:17.188640 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 12:30:17.195278 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 12:30:17.195355 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 12:30:17.198306 INFO: [APUAPC] D9_APC_3: 0x0
9974 12:30:17.201955 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 12:30:17.208466 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 12:30:17.211545 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 12:30:17.211628 INFO: [APUAPC] D10_APC_3: 0x0
9978 12:30:17.217895 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 12:30:17.221490 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 12:30:17.224426 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 12:30:17.224499 INFO: [APUAPC] D11_APC_3: 0x0
9982 12:30:17.231167 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 12:30:17.234317 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 12:30:17.238043 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 12:30:17.240892 INFO: [APUAPC] D12_APC_3: 0x0
9986 12:30:17.244599 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 12:30:17.247702 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 12:30:17.250810 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 12:30:17.254561 INFO: [APUAPC] D13_APC_3: 0x0
9990 12:30:17.257600 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 12:30:17.260858 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 12:30:17.263998 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 12:30:17.267751 INFO: [APUAPC] D14_APC_3: 0x0
9994 12:30:17.270789 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 12:30:17.273864 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 12:30:17.277573 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 12:30:17.280545 INFO: [APUAPC] D15_APC_3: 0x0
9998 12:30:17.284066 INFO: [APUAPC] APC_CON: 0x4
9999 12:30:17.284154 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 12:30:17.287143 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 12:30:17.290492 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 12:30:17.293393 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 12:30:17.296973 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 12:30:17.300613 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 12:30:17.303608 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 12:30:17.306727 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 12:30:17.310346 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 12:30:17.313231 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 12:30:17.316711 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 12:30:17.319705 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 12:30:17.319806 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 12:30:17.323109 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 12:30:17.326766 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 12:30:17.329815 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 12:30:17.332887 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 12:30:17.336640 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 12:30:17.339856 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 12:30:17.342938 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 12:30:17.346452 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 12:30:17.349573 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 12:30:17.353230 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 12:30:17.356279 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 12:30:17.359330 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 12:30:17.362973 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 12:30:17.363055 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 12:30:17.366032 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 12:30:17.369258 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 12:30:17.372996 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 12:30:17.376120 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 12:30:17.379137 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 12:30:17.382708 INFO: [NOCDAPC] APC_CON: 0x4
10032 12:30:17.385760 INFO: [APUAPC] set_apusys_apc done
10033 12:30:17.389297 INFO: [DEVAPC] devapc_init done
10034 12:30:17.392353 INFO: GICv3 without legacy support detected.
10035 12:30:17.395958 INFO: ARM GICv3 driver initialized in EL3
10036 12:30:17.402575 INFO: Maximum SPI INTID supported: 639
10037 12:30:17.405473 INFO: BL31: Initializing runtime services
10038 12:30:17.412194 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 12:30:17.412307 INFO: SPM: enable CPC mode
10040 12:30:17.418852 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 12:30:17.421903 INFO: BL31: Preparing for EL3 exit to normal world
10042 12:30:17.428450 INFO: Entry point address = 0x80000000
10043 12:30:17.428533 INFO: SPSR = 0x8
10044 12:30:17.435072
10045 12:30:17.435154
10046 12:30:17.435219
10047 12:30:17.438153 Starting depthcharge on Spherion...
10048 12:30:17.438236
10049 12:30:17.438300 Wipe memory regions:
10050 12:30:17.438362
10051 12:30:17.438997 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10052 12:30:17.439096 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 12:30:17.439177 Setting prompt string to ['asurada:']
10054 12:30:17.439287 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 12:30:17.441156 [0x00000040000000, 0x00000054600000)
10056 12:30:17.563697
10057 12:30:17.563826 [0x00000054660000, 0x00000080000000)
10058 12:30:17.823998
10059 12:30:17.824147 [0x000000821a7280, 0x000000ffe64000)
10060 12:30:18.569250
10061 12:30:18.569426 [0x00000100000000, 0x00000240000000)
10062 12:30:20.458998
10063 12:30:20.462144 Initializing XHCI USB controller at 0x11200000.
10064 12:30:21.500122
10065 12:30:21.503727 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 12:30:21.503821
10067 12:30:21.503889
10068 12:30:21.503952
10069 12:30:21.504229 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 12:30:21.604578 asurada: tftpboot 192.168.201.1 10605798/tftp-deploy-baj79x3r/kernel/image.itb 10605798/tftp-deploy-baj79x3r/kernel/cmdline
10072 12:30:21.604746 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 12:30:21.604838 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 12:30:21.609392 tftpboot 192.168.201.1 10605798/tftp-deploy-baj79x3r/kernel/image.ittp-deploy-baj79x3r/kernel/cmdline
10075 12:30:21.609531
10076 12:30:21.609603 Waiting for link
10077 12:30:21.769759
10078 12:30:21.769917 R8152: Initializing
10079 12:30:21.769996
10080 12:30:21.772858 Version 6 (ocp_data = 5c30)
10081 12:30:21.772967
10082 12:30:21.776558 R8152: Done initializing
10083 12:30:21.776700
10084 12:30:21.776800 Adding net device
10085 12:30:23.695693
10086 12:30:23.695830 done.
10087 12:30:23.695906
10088 12:30:23.695971 MAC: 00:24:32:30:78:ff
10089 12:30:23.696031
10090 12:30:23.698691 Sending DHCP discover... done.
10091 12:30:23.698793
10092 12:30:27.115991 Waiting for reply... done.
10093 12:30:27.116145
10094 12:30:27.116214 Sending DHCP request... done.
10095 12:30:27.118956
10096 12:30:27.119037 Waiting for reply... done.
10097 12:30:27.122251
10098 12:30:27.122331 My ip is 192.168.201.21
10099 12:30:27.122396
10100 12:30:27.125720 The DHCP server ip is 192.168.201.1
10101 12:30:27.125802
10102 12:30:27.128937 TFTP server IP predefined by user: 192.168.201.1
10103 12:30:27.129019
10104 12:30:27.135899 Bootfile predefined by user: 10605798/tftp-deploy-baj79x3r/kernel/image.itb
10105 12:30:27.135981
10106 12:30:27.139038 Sending tftp read request... done.
10107 12:30:27.139118
10108 12:30:27.145574 Waiting for the transfer...
10109 12:30:27.145660
10110 12:30:27.792756 00000000 ################################################################
10111 12:30:27.792905
10112 12:30:28.364343 00080000 ################################################################
10113 12:30:28.364492
10114 12:30:28.952650 00100000 ################################################################
10115 12:30:28.952785
10116 12:30:29.532039 00180000 ################################################################
10117 12:30:29.532205
10118 12:30:30.085232 00200000 ################################################################
10119 12:30:30.085368
10120 12:30:30.635802 00280000 ################################################################
10121 12:30:30.635962
10122 12:30:31.194132 00300000 ################################################################
10123 12:30:31.194303
10124 12:30:31.763251 00380000 ################################################################
10125 12:30:31.763411
10126 12:30:32.337141 00400000 ################################################################
10127 12:30:32.337323
10128 12:30:32.927649 00480000 ################################################################
10129 12:30:32.927824
10130 12:30:33.492952 00500000 ################################################################
10131 12:30:33.493130
10132 12:30:34.072434 00580000 ################################################################
10133 12:30:34.072587
10134 12:30:34.613732 00600000 ################################################################
10135 12:30:34.613885
10136 12:30:35.228725 00680000 ################################################################
10137 12:30:35.228874
10138 12:30:35.829357 00700000 ################################################################
10139 12:30:35.829507
10140 12:30:36.380564 00780000 ################################################################
10141 12:30:36.380720
10142 12:30:36.920146 00800000 ################################################################
10143 12:30:36.920324
10144 12:30:37.435935 00880000 ################################################################
10145 12:30:37.436110
10146 12:30:37.971133 00900000 ################################################################
10147 12:30:37.971299
10148 12:30:38.586759 00980000 ################################################################
10149 12:30:38.586995
10150 12:30:39.174961 00a00000 ################################################################
10151 12:30:39.175097
10152 12:30:39.762768 00a80000 ################################################################
10153 12:30:39.763282
10154 12:30:40.353469 00b00000 ################################################################
10155 12:30:40.353628
10156 12:30:40.931178 00b80000 ################################################################
10157 12:30:40.931316
10158 12:30:41.508526 00c00000 ################################################################
10159 12:30:41.508664
10160 12:30:42.097595 00c80000 ################################################################
10161 12:30:42.097734
10162 12:30:42.720362 00d00000 ################################################################
10163 12:30:42.720503
10164 12:30:43.350706 00d80000 ################################################################
10165 12:30:43.350898
10166 12:30:43.960331 00e00000 ################################################################
10167 12:30:43.960471
10168 12:30:44.574612 00e80000 ################################################################
10169 12:30:44.574765
10170 12:30:45.183068 00f00000 ################################################################
10171 12:30:45.183212
10172 12:30:45.752624 00f80000 ################################################################
10173 12:30:45.752779
10174 12:30:46.290601 01000000 ################################################################
10175 12:30:46.290737
10176 12:30:46.843095 01080000 ################################################################
10177 12:30:46.843255
10178 12:30:47.376960 01100000 ################################################################
10179 12:30:47.377099
10180 12:30:47.948486 01180000 ################################################################
10181 12:30:47.948626
10182 12:30:48.500319 01200000 ################################################################
10183 12:30:48.500481
10184 12:30:49.067319 01280000 ################################################################
10185 12:30:49.067496
10186 12:30:49.660840 01300000 ################################################################
10187 12:30:49.660998
10188 12:30:50.218128 01380000 ################################################################
10189 12:30:50.218277
10190 12:30:50.737861 01400000 ################################################################
10191 12:30:50.738066
10192 12:30:51.281583 01480000 ################################################################
10193 12:30:51.281740
10194 12:30:51.830999 01500000 ################################################################
10195 12:30:51.831162
10196 12:30:52.369885 01580000 ################################################################
10197 12:30:52.370061
10198 12:30:52.920619 01600000 ################################################################
10199 12:30:52.920767
10200 12:30:53.457544 01680000 ################################################################
10201 12:30:53.457711
10202 12:30:54.023602 01700000 ################################################################
10203 12:30:54.023738
10204 12:30:54.568545 01780000 ################################################################
10205 12:30:54.568688
10206 12:30:55.105218 01800000 ################################################################
10207 12:30:55.105356
10208 12:30:55.641213 01880000 ################################################################
10209 12:30:55.641355
10210 12:30:56.194263 01900000 ################################################################
10211 12:30:56.194435
10212 12:30:56.757215 01980000 ################################################################
10213 12:30:56.757356
10214 12:30:57.306594 01a00000 ################################################################
10215 12:30:57.306737
10216 12:30:57.892067 01a80000 ################################################################
10217 12:30:57.892247
10218 12:30:58.444904 01b00000 ################################################################
10219 12:30:58.445041
10220 12:30:59.044500 01b80000 ################################################################
10221 12:30:59.044668
10222 12:30:59.631135 01c00000 ################################################################
10223 12:30:59.631294
10224 12:31:00.196534 01c80000 ################################################################
10225 12:31:00.196673
10226 12:31:00.762448 01d00000 ################################################################
10227 12:31:00.762622
10228 12:31:01.334073 01d80000 ################################################################
10229 12:31:01.334231
10230 12:31:01.866986 01e00000 ################################################################
10231 12:31:01.867146
10232 12:31:02.393884 01e80000 ################################################################
10233 12:31:02.394074
10234 12:31:02.940494 01f00000 ################################################################
10235 12:31:02.940670
10236 12:31:03.535342 01f80000 ################################################################
10237 12:31:03.535513
10238 12:31:04.087569 02000000 ################################################################
10239 12:31:04.087722
10240 12:31:04.643180 02080000 ################################################################
10241 12:31:04.643330
10242 12:31:05.208498 02100000 ################################################################
10243 12:31:05.208635
10244 12:31:05.776789 02180000 ################################################################
10245 12:31:05.776963
10246 12:31:06.354403 02200000 ################################################################
10247 12:31:06.354553
10248 12:31:06.917185 02280000 ################################################################
10249 12:31:06.917338
10250 12:31:07.473684 02300000 ################################################################
10251 12:31:07.473835
10252 12:31:08.023289 02380000 ################################################################
10253 12:31:08.023438
10254 12:31:08.590606 02400000 ################################################################
10255 12:31:08.590753
10256 12:31:09.128680 02480000 ################################################################
10257 12:31:09.128817
10258 12:31:09.674286 02500000 ################################################################
10259 12:31:09.674442
10260 12:31:10.239525 02580000 ################################################################
10261 12:31:10.239682
10262 12:31:10.783706 02600000 ################################################################
10263 12:31:10.783893
10264 12:31:11.328027 02680000 ################################################################
10265 12:31:11.328200
10266 12:31:11.882965 02700000 ################################################################
10267 12:31:11.883127
10268 12:31:12.439567 02780000 ################################################################
10269 12:31:12.439739
10270 12:31:12.997010 02800000 ################################################################
10271 12:31:12.997155
10272 12:31:13.609654 02880000 ################################################################
10273 12:31:13.609834
10274 12:31:14.218094 02900000 ################################################################
10275 12:31:14.218231
10276 12:31:14.770761 02980000 ################################################################
10277 12:31:14.770953
10278 12:31:15.293774 02a00000 ################################################################
10279 12:31:15.293935
10280 12:31:15.836004 02a80000 ################################################################
10281 12:31:15.836182
10282 12:31:16.393602 02b00000 ################################################################
10283 12:31:16.393788
10284 12:31:16.946895 02b80000 ################################################################
10285 12:31:16.947071
10286 12:31:17.508994 02c00000 ################################################################
10287 12:31:17.509149
10288 12:31:18.159890 02c80000 ################################################################
10289 12:31:18.160442
10290 12:31:18.729787 02d00000 ################################################################
10291 12:31:18.729938
10292 12:31:19.314767 02d80000 ################################################################
10293 12:31:19.314970
10294 12:31:19.870276 02e00000 ################################################################
10295 12:31:19.870448
10296 12:31:20.422867 02e80000 ################################################################
10297 12:31:20.423001
10298 12:31:20.965351 02f00000 ################################################################
10299 12:31:20.965505
10300 12:31:21.511452 02f80000 ################################################################
10301 12:31:21.511599
10302 12:31:22.045280 03000000 ################################################################
10303 12:31:22.045428
10304 12:31:22.592406 03080000 ################################################################
10305 12:31:22.592558
10306 12:31:23.137413 03100000 ################################################################
10307 12:31:23.137597
10308 12:31:23.686090 03180000 ################################################################
10309 12:31:23.686254
10310 12:31:24.245950 03200000 ################################################################
10311 12:31:24.246089
10312 12:31:24.816652 03280000 ################################################################
10313 12:31:24.816803
10314 12:31:25.369108 03300000 ################################################################
10315 12:31:25.369260
10316 12:31:25.916102 03380000 ################################################################
10317 12:31:25.916249
10318 12:31:26.470280 03400000 ################################################################
10319 12:31:26.470457
10320 12:31:27.023495 03480000 ################################################################
10321 12:31:27.023660
10322 12:31:27.568289 03500000 ################################################################
10323 12:31:27.568458
10324 12:31:28.116580 03580000 ################################################################
10325 12:31:28.116719
10326 12:31:28.670536 03600000 ################################################################
10327 12:31:28.670687
10328 12:31:29.211371 03680000 ################################################################
10329 12:31:29.211527
10330 12:31:29.816706 03700000 ################################################################
10331 12:31:29.816890
10332 12:31:30.381027 03780000 ################################################################
10333 12:31:30.381173
10334 12:31:30.948849 03800000 ################################################################
10335 12:31:30.948998
10336 12:31:31.496288 03880000 ################################################################
10337 12:31:31.496432
10338 12:31:32.099401 03900000 ################################################################
10339 12:31:32.099588
10340 12:31:32.655975 03980000 ################################################################
10341 12:31:32.656154
10342 12:31:33.252460 03a00000 ################################################################
10343 12:31:33.252618
10344 12:31:33.837409 03a80000 ################################################################
10345 12:31:33.837558
10346 12:31:34.372413 03b00000 ################################################################
10347 12:31:34.372562
10348 12:31:35.006342 03b80000 ################################################################
10349 12:31:35.006504
10350 12:31:35.546339 03c00000 ################################################################
10351 12:31:35.546492
10352 12:31:36.102971 03c80000 ################################################################
10353 12:31:36.103131
10354 12:31:36.665599 03d00000 ################################################################
10355 12:31:36.665752
10356 12:31:37.203757 03d80000 ################################################################
10357 12:31:37.203938
10358 12:31:37.751453 03e00000 ################################################################
10359 12:31:37.751610
10360 12:31:38.280372 03e80000 ################################################################
10361 12:31:38.280509
10362 12:31:38.708709 03f00000 ##################################################### done.
10363 12:31:38.708845
10364 12:31:38.711878 The bootfile was 66487866 bytes long.
10365 12:31:38.711963
10366 12:31:38.715168 Sending tftp read request... done.
10367 12:31:38.715298
10368 12:31:38.718349 Waiting for the transfer...
10369 12:31:38.718475
10370 12:31:38.718584 00000000 # done.
10371 12:31:38.718686
10372 12:31:38.728276 Command line loaded dynamically from TFTP file: 10605798/tftp-deploy-baj79x3r/kernel/cmdline
10373 12:31:38.728363
10374 12:31:38.738272 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10375 12:31:38.738359
10376 12:31:38.741439 Loading FIT.
10377 12:31:38.741523
10378 12:31:38.744875 Image ramdisk-1 has 56352159 bytes.
10379 12:31:38.744960
10380 12:31:38.745026 Image fdt-1 has 46924 bytes.
10381 12:31:38.745111
10382 12:31:38.748473 Image kernel-1 has 10086749 bytes.
10383 12:31:38.748556
10384 12:31:38.757775 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10385 12:31:38.757860
10386 12:31:38.774881 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10387 12:31:38.774972
10388 12:31:38.781127 Choosing best match conf-1 for compat google,spherion-rev2.
10389 12:31:38.784891
10390 12:31:38.789282 Connected to device vid:did:rid of 1ae0:0028:00
10391 12:31:38.796386
10392 12:31:38.800139 tpm_get_response: command 0x17b, return code 0x0
10393 12:31:38.800226
10394 12:31:38.803147 ec_init: CrosEC protocol v3 supported (256, 248)
10395 12:31:38.806272
10396 12:31:38.809512 tpm_cleanup: add release locality here.
10397 12:31:38.809595
10398 12:31:38.813282 Shutting down all USB controllers.
10399 12:31:38.813365
10400 12:31:38.816265 Removing current net device
10401 12:31:38.816348
10402 12:31:38.819434 Exiting depthcharge with code 4 at timestamp: 110739168
10403 12:31:38.819518
10404 12:31:38.826381 LZMA decompressing kernel-1 to 0x821a6718
10405 12:31:38.826465
10406 12:31:38.829492 LZMA decompressing kernel-1 to 0x40000000
10407 12:31:40.094766
10408 12:31:40.094928 jumping to kernel
10409 12:31:40.095360 end: 2.2.4 bootloader-commands (duration 00:01:23) [common]
10410 12:31:40.095459 start: 2.2.5 auto-login-action (timeout 00:03:03) [common]
10411 12:31:40.095536 Setting prompt string to ['Linux version [0-9]']
10412 12:31:40.095605 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10413 12:31:40.095673 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10414 12:31:40.176608
10415 12:31:40.180261 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10416 12:31:40.183758 start: 2.2.5.1 login-action (timeout 00:03:02) [common]
10417 12:31:40.183900 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10418 12:31:40.184031 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10419 12:31:40.184143 Using line separator: #'\n'#
10420 12:31:40.184234 No login prompt set.
10421 12:31:40.184325 Parsing kernel messages
10422 12:31:40.184408 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10423 12:31:40.184558 [login-action] Waiting for messages, (timeout 00:03:02)
10424 12:31:40.203223 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10425 12:31:40.206371 [ 0.000000] random: crng init done
10426 12:31:40.212991 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10427 12:31:40.216054 [ 0.000000] efi: UEFI not found.
10428 12:31:40.223004 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10429 12:31:40.229656 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10430 12:31:40.239779 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10431 12:31:40.249568 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10432 12:31:40.255998 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10433 12:31:40.262409 [ 0.000000] printk: bootconsole [mtk8250] enabled
10434 12:31:40.268847 [ 0.000000] NUMA: No NUMA configuration found
10435 12:31:40.275601 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10436 12:31:40.278758 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10437 12:31:40.281922 [ 0.000000] Zone ranges:
10438 12:31:40.288898 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10439 12:31:40.292099 [ 0.000000] DMA32 empty
10440 12:31:40.298511 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10441 12:31:40.301817 [ 0.000000] Movable zone start for each node
10442 12:31:40.305075 [ 0.000000] Early memory node ranges
10443 12:31:40.311900 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10444 12:31:40.318579 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10445 12:31:40.324969 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10446 12:31:40.331751 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10447 12:31:40.337796 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10448 12:31:40.345090 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10449 12:31:40.400753 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10450 12:31:40.407775 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10451 12:31:40.414108 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10452 12:31:40.417246 [ 0.000000] psci: probing for conduit method from DT.
10453 12:31:40.423822 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10454 12:31:40.427060 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10455 12:31:40.433801 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10456 12:31:40.437442 [ 0.000000] psci: SMC Calling Convention v1.2
10457 12:31:40.443692 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10458 12:31:40.447406 [ 0.000000] Detected VIPT I-cache on CPU0
10459 12:31:40.453520 [ 0.000000] CPU features: detected: GIC system register CPU interface
10460 12:31:40.460213 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10461 12:31:40.466788 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10462 12:31:40.473427 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10463 12:31:40.483619 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10464 12:31:40.489692 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10465 12:31:40.493615 [ 0.000000] alternatives: applying boot alternatives
10466 12:31:40.500058 [ 0.000000] Fallback order for Node 0: 0
10467 12:31:40.506694 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10468 12:31:40.509813 [ 0.000000] Policy zone: Normal
10469 12:31:40.523143 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10470 12:31:40.532443 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10471 12:31:40.542901 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10472 12:31:40.552937 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10473 12:31:40.559734 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10474 12:31:40.562784 <6>[ 0.000000] software IO TLB: area num 8.
10475 12:31:40.618994 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10476 12:31:40.768981 <6>[ 0.000000] Memory: 7917908K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434860K reserved, 32768K cma-reserved)
10477 12:31:40.774812 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10478 12:31:40.781499 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10479 12:31:40.784960 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10480 12:31:40.791392 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10481 12:31:40.798055 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10482 12:31:40.801765 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10483 12:31:40.811416 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10484 12:31:40.818172 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10485 12:31:40.824479 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10486 12:31:40.831380 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10487 12:31:40.834607 <6>[ 0.000000] GICv3: 608 SPIs implemented
10488 12:31:40.837710 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10489 12:31:40.844115 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10490 12:31:40.847310 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10491 12:31:40.854058 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10492 12:31:40.867458 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10493 12:31:40.880605 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10494 12:31:40.886695 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10495 12:31:40.895000 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10496 12:31:40.907917 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10497 12:31:40.914609 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10498 12:31:40.921618 <6>[ 0.009225] Console: colour dummy device 80x25
10499 12:31:40.931174 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10500 12:31:40.938003 <6>[ 0.024459] pid_max: default: 32768 minimum: 301
10501 12:31:40.941072 <6>[ 0.029362] LSM: Security Framework initializing
10502 12:31:40.948052 <6>[ 0.034302] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10503 12:31:40.957649 <6>[ 0.042117] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10504 12:31:40.967761 <6>[ 0.051547] cblist_init_generic: Setting adjustable number of callback queues.
10505 12:31:40.974049 <6>[ 0.059001] cblist_init_generic: Setting shift to 3 and lim to 1.
10506 12:31:40.977068 <6>[ 0.065341] cblist_init_generic: Setting shift to 3 and lim to 1.
10507 12:31:40.984175 <6>[ 0.071748] rcu: Hierarchical SRCU implementation.
10508 12:31:40.990676 <6>[ 0.076761] rcu: Max phase no-delay instances is 1000.
10509 12:31:40.997105 <6>[ 0.083776] EFI services will not be available.
10510 12:31:41.000067 <6>[ 0.088752] smp: Bringing up secondary CPUs ...
10511 12:31:41.008158 <6>[ 0.093803] Detected VIPT I-cache on CPU1
10512 12:31:41.014819 <6>[ 0.093878] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10513 12:31:41.021491 <6>[ 0.093910] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10514 12:31:41.024615 <6>[ 0.094240] Detected VIPT I-cache on CPU2
10515 12:31:41.034841 <6>[ 0.094289] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10516 12:31:41.040909 <6>[ 0.094304] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10517 12:31:41.044584 <6>[ 0.094560] Detected VIPT I-cache on CPU3
10518 12:31:41.050832 <6>[ 0.094606] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10519 12:31:41.057716 <6>[ 0.094620] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10520 12:31:41.064420 <6>[ 0.094923] CPU features: detected: Spectre-v4
10521 12:31:41.067546 <6>[ 0.094929] CPU features: detected: Spectre-BHB
10522 12:31:41.070749 <6>[ 0.094935] Detected PIPT I-cache on CPU4
10523 12:31:41.077753 <6>[ 0.094993] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10524 12:31:41.087155 <6>[ 0.095009] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10525 12:31:41.090403 <6>[ 0.095303] Detected PIPT I-cache on CPU5
10526 12:31:41.096934 <6>[ 0.095367] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10527 12:31:41.104043 <6>[ 0.095383] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10528 12:31:41.106947 <6>[ 0.095664] Detected PIPT I-cache on CPU6
10529 12:31:41.117209 <6>[ 0.095727] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10530 12:31:41.123794 <6>[ 0.095744] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10531 12:31:41.126684 <6>[ 0.096042] Detected PIPT I-cache on CPU7
10532 12:31:41.133485 <6>[ 0.096108] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10533 12:31:41.139688 <6>[ 0.096124] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10534 12:31:41.143370 <6>[ 0.096171] smp: Brought up 1 node, 8 CPUs
10535 12:31:41.149598 <6>[ 0.237475] SMP: Total of 8 processors activated.
10536 12:31:41.156466 <6>[ 0.242396] CPU features: detected: 32-bit EL0 Support
10537 12:31:41.163196 <6>[ 0.247759] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10538 12:31:41.169356 <6>[ 0.256559] CPU features: detected: Common not Private translations
10539 12:31:41.176400 <6>[ 0.263075] CPU features: detected: CRC32 instructions
10540 12:31:41.182578 <6>[ 0.268459] CPU features: detected: RCpc load-acquire (LDAPR)
10541 12:31:41.186283 <6>[ 0.274420] CPU features: detected: LSE atomic instructions
10542 12:31:41.192340 <6>[ 0.280201] CPU features: detected: Privileged Access Never
10543 12:31:41.199226 <6>[ 0.285981] CPU features: detected: RAS Extension Support
10544 12:31:41.205726 <6>[ 0.291624] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10545 12:31:41.209331 <6>[ 0.298890] CPU: All CPU(s) started at EL2
10546 12:31:41.215323 <6>[ 0.303206] alternatives: applying system-wide alternatives
10547 12:31:41.226119 <6>[ 0.313925] devtmpfs: initialized
10548 12:31:41.241781 <6>[ 0.322877] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10549 12:31:41.248338 <6>[ 0.332834] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10550 12:31:41.254578 <6>[ 0.340514] pinctrl core: initialized pinctrl subsystem
10551 12:31:41.257816 <6>[ 0.347177] DMI not present or invalid.
10552 12:31:41.264835 <6>[ 0.351586] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10553 12:31:41.274373 <6>[ 0.358461] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10554 12:31:41.281075 <6>[ 0.366040] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10555 12:31:41.290948 <6>[ 0.374253] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10556 12:31:41.294181 <6>[ 0.382500] audit: initializing netlink subsys (disabled)
10557 12:31:41.304712 <5>[ 0.388194] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10558 12:31:41.310696 <6>[ 0.388903] thermal_sys: Registered thermal governor 'step_wise'
10559 12:31:41.317253 <6>[ 0.396159] thermal_sys: Registered thermal governor 'power_allocator'
10560 12:31:41.320766 <6>[ 0.402415] cpuidle: using governor menu
10561 12:31:41.327608 <6>[ 0.413380] NET: Registered PF_QIPCRTR protocol family
10562 12:31:41.333787 <6>[ 0.418859] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10563 12:31:41.336940 <6>[ 0.425961] ASID allocator initialised with 32768 entries
10564 12:31:41.344925 <6>[ 0.432549] Serial: AMBA PL011 UART driver
10565 12:31:41.353659 <4>[ 0.441255] Trying to register duplicate clock ID: 134
10566 12:31:41.409260 <6>[ 0.500547] KASLR enabled
10567 12:31:41.423631 <6>[ 0.508259] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10568 12:31:41.430063 <6>[ 0.515270] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10569 12:31:41.437006 <6>[ 0.521760] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10570 12:31:41.443600 <6>[ 0.528765] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10571 12:31:41.449892 <6>[ 0.535251] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10572 12:31:41.456845 <6>[ 0.542255] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10573 12:31:41.463582 <6>[ 0.548740] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10574 12:31:41.469735 <6>[ 0.555743] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10575 12:31:41.473008 <6>[ 0.563280] ACPI: Interpreter disabled.
10576 12:31:41.481600 <6>[ 0.569713] iommu: Default domain type: Translated
10577 12:31:41.488612 <6>[ 0.574828] iommu: DMA domain TLB invalidation policy: strict mode
10578 12:31:41.491727 <5>[ 0.581484] SCSI subsystem initialized
10579 12:31:41.498722 <6>[ 0.585651] usbcore: registered new interface driver usbfs
10580 12:31:41.505020 <6>[ 0.591383] usbcore: registered new interface driver hub
10581 12:31:41.508116 <6>[ 0.596932] usbcore: registered new device driver usb
10582 12:31:41.515136 <6>[ 0.603036] pps_core: LinuxPPS API ver. 1 registered
10583 12:31:41.525482 <6>[ 0.608232] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10584 12:31:41.528550 <6>[ 0.617576] PTP clock support registered
10585 12:31:41.531480 <6>[ 0.621819] EDAC MC: Ver: 3.0.0
10586 12:31:41.539217 <6>[ 0.626950] FPGA manager framework
10587 12:31:41.546180 <6>[ 0.630634] Advanced Linux Sound Architecture Driver Initialized.
10588 12:31:41.549275 <6>[ 0.637420] vgaarb: loaded
10589 12:31:41.555863 <6>[ 0.640588] clocksource: Switched to clocksource arch_sys_counter
10590 12:31:41.559084 <5>[ 0.647031] VFS: Disk quotas dquot_6.6.0
10591 12:31:41.565946 <6>[ 0.651213] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10592 12:31:41.569059 <6>[ 0.658400] pnp: PnP ACPI: disabled
10593 12:31:41.577811 <6>[ 0.665155] NET: Registered PF_INET protocol family
10594 12:31:41.587334 <6>[ 0.670737] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10595 12:31:41.598719 <6>[ 0.683020] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10596 12:31:41.608730 <6>[ 0.691835] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10597 12:31:41.615340 <6>[ 0.699804] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10598 12:31:41.625392 <6>[ 0.708505] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10599 12:31:41.631568 <6>[ 0.718249] TCP: Hash tables configured (established 65536 bind 65536)
10600 12:31:41.637726 <6>[ 0.725100] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10601 12:31:41.648109 <6>[ 0.732296] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10602 12:31:41.654523 <6>[ 0.739999] NET: Registered PF_UNIX/PF_LOCAL protocol family
10603 12:31:41.661022 <6>[ 0.746175] RPC: Registered named UNIX socket transport module.
10604 12:31:41.664554 <6>[ 0.752331] RPC: Registered udp transport module.
10605 12:31:41.670725 <6>[ 0.757262] RPC: Registered tcp transport module.
10606 12:31:41.677346 <6>[ 0.762194] RPC: Registered tcp NFSv4.1 backchannel transport module.
10607 12:31:41.681013 <6>[ 0.768862] PCI: CLS 0 bytes, default 64
10608 12:31:41.684171 <6>[ 0.773252] Unpacking initramfs...
10609 12:31:41.694092 <6>[ 0.777374] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10610 12:31:41.700535 <6>[ 0.786036] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10611 12:31:41.707236 <6>[ 0.794875] kvm [1]: IPA Size Limit: 40 bits
10612 12:31:41.710417 <6>[ 0.799406] kvm [1]: GICv3: no GICV resource entry
10613 12:31:41.717309 <6>[ 0.804426] kvm [1]: disabling GICv2 emulation
10614 12:31:41.723465 <6>[ 0.809114] kvm [1]: GIC system register CPU interface enabled
10615 12:31:41.727279 <6>[ 0.815276] kvm [1]: vgic interrupt IRQ18
10616 12:31:41.733326 <6>[ 0.819632] kvm [1]: VHE mode initialized successfully
10617 12:31:41.736535 <5>[ 0.826059] Initialise system trusted keyrings
10618 12:31:41.743450 <6>[ 0.830850] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10619 12:31:41.753138 <6>[ 0.840982] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10620 12:31:41.760031 <5>[ 0.847399] NFS: Registering the id_resolver key type
10621 12:31:41.762929 <5>[ 0.852718] Key type id_resolver registered
10622 12:31:41.769702 <5>[ 0.857135] Key type id_legacy registered
10623 12:31:41.776303 <6>[ 0.861416] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10624 12:31:41.783366 <6>[ 0.868339] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10625 12:31:41.789565 <6>[ 0.876062] 9p: Installing v9fs 9p2000 file system support
10626 12:31:41.825288 <5>[ 0.913090] Key type asymmetric registered
10627 12:31:41.829052 <5>[ 0.917423] Asymmetric key parser 'x509' registered
10628 12:31:41.838365 <6>[ 0.922597] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10629 12:31:41.842040 <6>[ 0.930211] io scheduler mq-deadline registered
10630 12:31:41.845226 <6>[ 0.934971] io scheduler kyber registered
10631 12:31:41.864161 <6>[ 0.951824] EINJ: ACPI disabled.
10632 12:31:41.896427 <4>[ 0.977611] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 12:31:41.906465 <4>[ 0.988241] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 12:31:41.921610 <6>[ 1.009258] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10635 12:31:41.929198 <6>[ 1.017339] printk: console [ttyS0] disabled
10636 12:31:41.957775 <6>[ 1.041982] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10637 12:31:41.964031 <6>[ 1.051455] printk: console [ttyS0] enabled
10638 12:31:41.967124 <6>[ 1.051455] printk: console [ttyS0] enabled
10639 12:31:41.973993 <6>[ 1.060348] printk: bootconsole [mtk8250] disabled
10640 12:31:41.976912 <6>[ 1.060348] printk: bootconsole [mtk8250] disabled
10641 12:31:41.984061 <6>[ 1.071629] SuperH (H)SCI(F) driver initialized
10642 12:31:41.987115 <6>[ 1.076914] msm_serial: driver initialized
10643 12:31:42.001361 <6>[ 1.085814] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10644 12:31:42.011021 <6>[ 1.094359] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10645 12:31:42.018080 <6>[ 1.102901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10646 12:31:42.027504 <6>[ 1.111529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10647 12:31:42.037549 <6>[ 1.120236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10648 12:31:42.044336 <6>[ 1.128956] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10649 12:31:42.053821 <6>[ 1.137499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10650 12:31:42.060731 <6>[ 1.146307] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10651 12:31:42.070038 <6>[ 1.154853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10652 12:31:42.082550 <6>[ 1.170394] loop: module loaded
10653 12:31:42.089044 <6>[ 1.176438] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10654 12:31:42.111936 <4>[ 1.199707] mtk-pmic-keys: Failed to locate of_node [id: -1]
10655 12:31:42.118600 <6>[ 1.206443] megasas: 07.719.03.00-rc1
10656 12:31:42.128221 <6>[ 1.215892] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10657 12:31:42.136386 <6>[ 1.223974] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10658 12:31:42.152958 <6>[ 1.240449] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10659 12:31:42.212801 <6>[ 1.293996] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10660 12:31:44.107668 <6>[ 3.195884] Freeing initrd memory: 55028K
10661 12:31:44.118355 <6>[ 3.206089] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10662 12:31:44.128835 <6>[ 3.217010] tun: Universal TUN/TAP device driver, 1.6
10663 12:31:44.132494 <6>[ 3.223055] thunder_xcv, ver 1.0
10664 12:31:44.135441 <6>[ 3.226566] thunder_bgx, ver 1.0
10665 12:31:44.138966 <6>[ 3.230060] nicpf, ver 1.0
10666 12:31:44.149549 <6>[ 3.234079] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10667 12:31:44.152556 <6>[ 3.241555] hns3: Copyright (c) 2017 Huawei Corporation.
10668 12:31:44.159409 <6>[ 3.247141] hclge is initializing
10669 12:31:44.162688 <6>[ 3.250723] e1000: Intel(R) PRO/1000 Network Driver
10670 12:31:44.169320 <6>[ 3.255852] e1000: Copyright (c) 1999-2006 Intel Corporation.
10671 12:31:44.172519 <6>[ 3.261865] e1000e: Intel(R) PRO/1000 Network Driver
10672 12:31:44.178958 <6>[ 3.267081] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10673 12:31:44.185894 <6>[ 3.273265] igb: Intel(R) Gigabit Ethernet Network Driver
10674 12:31:44.191981 <6>[ 3.278915] igb: Copyright (c) 2007-2014 Intel Corporation.
10675 12:31:44.198499 <6>[ 3.284754] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10676 12:31:44.205559 <6>[ 3.291273] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10677 12:31:44.208658 <6>[ 3.297728] sky2: driver version 1.30
10678 12:31:44.215455 <6>[ 3.302705] VFIO - User Level meta-driver version: 0.3
10679 12:31:44.223233 <6>[ 3.310890] usbcore: registered new interface driver usb-storage
10680 12:31:44.229584 <6>[ 3.317342] usbcore: registered new device driver onboard-usb-hub
10681 12:31:44.238594 <6>[ 3.326418] mt6397-rtc mt6359-rtc: registered as rtc0
10682 12:31:44.248667 <6>[ 3.331887] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:31:44 UTC (1686054704)
10683 12:31:44.252182 <6>[ 3.341446] i2c_dev: i2c /dev entries driver
10684 12:31:44.268421 <6>[ 3.353185] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10685 12:31:44.275571 <6>[ 3.363401] sdhci: Secure Digital Host Controller Interface driver
10686 12:31:44.281977 <6>[ 3.369840] sdhci: Copyright(c) Pierre Ossman
10687 12:31:44.289087 <6>[ 3.375233] Synopsys Designware Multimedia Card Interface Driver
10688 12:31:44.292116 <6>[ 3.381857] mmc0: CQHCI version 5.10
10689 12:31:44.298533 <6>[ 3.382416] sdhci-pltfm: SDHCI platform and OF driver helper
10690 12:31:44.305804 <6>[ 3.393722] ledtrig-cpu: registered to indicate activity on CPUs
10691 12:31:44.316417 <6>[ 3.401093] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10692 12:31:44.323515 <6>[ 3.408489] usbcore: registered new interface driver usbhid
10693 12:31:44.326541 <6>[ 3.414322] usbhid: USB HID core driver
10694 12:31:44.333204 <6>[ 3.418562] spi_master spi0: will run message pump with realtime priority
10695 12:31:44.380940 <6>[ 3.462344] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10696 12:31:44.401126 <6>[ 3.478577] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10697 12:31:44.404357 <6>[ 3.492161] mmc0: Command Queue Engine enabled
10698 12:31:44.410891 <6>[ 3.494725] cros-ec-spi spi0.0: Chrome EC device registered
10699 12:31:44.417866 <6>[ 3.496906] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10700 12:31:44.420805 <6>[ 3.509932] mmcblk0: mmc0:0001 DA4128 116 GiB
10701 12:31:44.436588 <6>[ 3.520976] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10702 12:31:44.442934 <6>[ 3.523804] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10703 12:31:44.449150 <6>[ 3.532461] NET: Registered PF_PACKET protocol family
10704 12:31:44.452842 <6>[ 3.537610] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10705 12:31:44.459302 <6>[ 3.541614] 9pnet: Installing 9P2000 support
10706 12:31:44.462823 <6>[ 3.547397] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10707 12:31:44.469076 <5>[ 3.551305] Key type dns_resolver registered
10708 12:31:44.475888 <6>[ 3.557202] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10709 12:31:44.479208 <6>[ 3.561614] registered taskstats version 1
10710 12:31:44.482238 <5>[ 3.571909] Loading compiled-in X.509 certificates
10711 12:31:44.518088 <4>[ 3.599360] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10712 12:31:44.527732 <4>[ 3.610090] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10713 12:31:44.538485 <3>[ 3.623046] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10714 12:31:44.550977 <6>[ 3.639115] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10715 12:31:44.557750 <6>[ 3.645934] xhci-mtk 11200000.usb: xHCI Host Controller
10716 12:31:44.564715 <6>[ 3.651446] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10717 12:31:44.574247 <6>[ 3.659392] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10718 12:31:44.581023 <6>[ 3.668839] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10719 12:31:44.587633 <6>[ 3.674944] xhci-mtk 11200000.usb: xHCI Host Controller
10720 12:31:44.594389 <6>[ 3.680427] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10721 12:31:44.600634 <6>[ 3.688078] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10722 12:31:44.607613 <6>[ 3.695789] hub 1-0:1.0: USB hub found
10723 12:31:44.610746 <6>[ 3.699814] hub 1-0:1.0: 1 port detected
10724 12:31:44.620679 <6>[ 3.704160] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10725 12:31:44.623759 <6>[ 3.712929] hub 2-0:1.0: USB hub found
10726 12:31:44.627388 <6>[ 3.716961] hub 2-0:1.0: 1 port detected
10727 12:31:44.635937 <6>[ 3.724374] mtk-msdc 11f70000.mmc: Got CD GPIO
10728 12:31:44.657406 <6>[ 3.742383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10729 12:31:44.664317 <6>[ 3.750440] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10730 12:31:44.673727 <4>[ 3.758421] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10731 12:31:44.683765 <6>[ 3.768082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10732 12:31:44.690392 <6>[ 3.776164] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10733 12:31:44.700506 <6>[ 3.784199] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10734 12:31:44.706720 <6>[ 3.792116] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10735 12:31:44.713614 <6>[ 3.799938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10736 12:31:44.723354 <6>[ 3.807760] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10737 12:31:44.733278 <6>[ 3.818420] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10738 12:31:44.743426 <6>[ 3.826802] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10739 12:31:44.749545 <6>[ 3.835155] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10740 12:31:44.759568 <6>[ 3.843499] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10741 12:31:44.766659 <6>[ 3.851842] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10742 12:31:44.776255 <6>[ 3.860185] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10743 12:31:44.782693 <6>[ 3.868529] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10744 12:31:44.792497 <6>[ 3.876875] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10745 12:31:44.799245 <6>[ 3.885218] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10746 12:31:44.809076 <6>[ 3.893561] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10747 12:31:44.815455 <6>[ 3.901905] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10748 12:31:44.825370 <6>[ 3.910249] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10749 12:31:44.832286 <6>[ 3.918594] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10750 12:31:44.842088 <6>[ 3.926937] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10751 12:31:44.851827 <6>[ 3.935283] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10752 12:31:44.858745 <6>[ 3.944197] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10753 12:31:44.865459 <6>[ 3.951673] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10754 12:31:44.871875 <6>[ 3.958773] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10755 12:31:44.878344 <6>[ 3.965930] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10756 12:31:44.888980 <6>[ 3.973269] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10757 12:31:44.895275 <6>[ 3.980211] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10758 12:31:44.904936 <6>[ 3.989355] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10759 12:31:44.914908 <6>[ 3.998484] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10760 12:31:44.925049 <6>[ 4.007789] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10761 12:31:44.934895 <6>[ 4.017264] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10762 12:31:44.941165 <6>[ 4.026739] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10763 12:31:44.951484 <6>[ 4.035869] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10764 12:31:44.961093 <6>[ 4.045343] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10765 12:31:44.971229 <6>[ 4.054469] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10766 12:31:44.980813 <6>[ 4.063771] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10767 12:31:44.990688 <6>[ 4.073937] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10768 12:31:45.001413 <6>[ 4.085822] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10769 12:31:45.040058 <6>[ 4.124869] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10770 12:31:45.194334 <6>[ 4.282174] hub 1-1:1.0: USB hub found
10771 12:31:45.197430 <6>[ 4.286667] hub 1-1:1.0: 4 ports detected
10772 12:31:45.320417 <6>[ 4.405048] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10773 12:31:45.344699 <6>[ 4.432441] hub 2-1:1.0: USB hub found
10774 12:31:45.347696 <6>[ 4.436819] hub 2-1:1.0: 3 ports detected
10775 12:31:45.519967 <6>[ 4.604859] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10776 12:31:45.652995 <6>[ 4.741155] hub 1-1.4:1.0: USB hub found
10777 12:31:45.655995 <6>[ 4.745837] hub 1-1.4:1.0: 2 ports detected
10778 12:31:45.732014 <6>[ 4.817093] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10779 12:31:45.956005 <6>[ 5.040859] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10780 12:31:46.147550 <6>[ 5.232860] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10781 12:31:57.276830 <6>[ 16.369411] ALSA device list:
10782 12:31:57.282894 <6>[ 16.372668] No soundcards found.
10783 12:31:57.295527 <6>[ 16.385092] Freeing unused kernel memory: 8384K
10784 12:31:57.298797 <6>[ 16.390022] Run /init as init process
10785 12:31:57.329418 <6>[ 16.418897] NET: Registered PF_INET6 protocol family
10786 12:31:57.336323 <6>[ 16.425381] Segment Routing with IPv6
10787 12:31:57.339114 <6>[ 16.429341] In-situ OAM (IOAM) with IPv6
10788 12:31:57.374227 <30>[ 16.444117] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10789 12:31:57.377419 <30>[ 16.468050] systemd[1]: Detected architecture arm64.
10790 12:31:57.380558
10791 12:31:57.384341 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10792 12:31:57.384515
10793 12:31:57.399631 <30>[ 16.489111] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10794 12:31:57.544907 <30>[ 16.631046] systemd[1]: Queued start job for default target Graphical Interface.
10795 12:31:57.592650 <30>[ 16.682238] systemd[1]: Created slice system-getty.slice.
10796 12:31:57.599647 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10797 12:31:57.616154 <30>[ 16.705451] systemd[1]: Created slice system-modprobe.slice.
10798 12:31:57.622364 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10799 12:31:57.640802 <30>[ 16.730011] systemd[1]: Created slice system-serial\x2dgetty.slice.
10800 12:31:57.650882 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10801 12:31:57.664243 <30>[ 16.753336] systemd[1]: Created slice User and Session Slice.
10802 12:31:57.670622 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10803 12:31:57.691071 <30>[ 16.777415] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10804 12:31:57.700921 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10805 12:31:57.719166 <30>[ 16.805040] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10806 12:31:57.725449 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10807 12:31:57.745924 <30>[ 16.828935] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10808 12:31:57.752249 <30>[ 16.840970] systemd[1]: Reached target Local Encrypted Volumes.
10809 12:31:57.759096 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10810 12:31:57.775658 <30>[ 16.865211] systemd[1]: Reached target Paths.
10811 12:31:57.778613 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10812 12:31:57.795417 <30>[ 16.884848] systemd[1]: Reached target Remote File Systems.
10813 12:31:57.801728 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10814 12:31:57.815372 <30>[ 16.904838] systemd[1]: Reached target Slices.
10815 12:31:57.818463 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10816 12:31:57.835328 <30>[ 16.924856] systemd[1]: Reached target Swap.
10817 12:31:57.839233 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10818 12:31:57.859401 <30>[ 16.945208] systemd[1]: Listening on initctl Compatibility Named Pipe.
10819 12:31:57.865678 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10820 12:31:57.872381 <30>[ 16.959902] systemd[1]: Listening on Journal Audit Socket.
10821 12:31:57.878691 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10822 12:31:57.891270 <30>[ 16.981096] systemd[1]: Listening on Journal Socket (/dev/log).
10823 12:31:57.897842 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10824 12:31:57.915616 <30>[ 17.005163] systemd[1]: Listening on Journal Socket.
10825 12:31:57.922381 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10826 12:31:57.935335 <30>[ 17.025110] systemd[1]: Listening on udev Control Socket.
10827 12:31:57.942205 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10828 12:31:57.955658 <30>[ 17.045045] systemd[1]: Listening on udev Kernel Socket.
10829 12:31:57.961966 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10830 12:31:57.991997 <30>[ 17.081115] systemd[1]: Mounting Huge Pages File System...
10831 12:31:57.997999 Mounting [0;1;39mHuge Pages File System[0m...
10832 12:31:58.013945 <30>[ 17.103051] systemd[1]: Mounting POSIX Message Queue File System...
10833 12:31:58.020831 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10834 12:31:58.037782 <30>[ 17.127002] systemd[1]: Mounting Kernel Debug File System...
10835 12:31:58.043720 Mounting [0;1;39mKernel Debug File System[0m...
10836 12:31:58.062767 <30>[ 17.149164] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10837 12:31:58.074423 <30>[ 17.160150] systemd[1]: Starting Create list of static device nodes for the current kernel...
10838 12:31:58.080705 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10839 12:31:58.097867 <30>[ 17.187359] systemd[1]: Starting Load Kernel Module configfs...
10840 12:31:58.104497 Starting [0;1;39mLoad Kernel Module configfs[0m...
10841 12:31:58.121993 <30>[ 17.211315] systemd[1]: Starting Load Kernel Module drm...
10842 12:31:58.128626 Starting [0;1;39mLoad Kernel Module drm[0m...
10843 12:31:58.147098 <30>[ 17.233130] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10844 12:31:58.183854 <30>[ 17.273506] systemd[1]: Starting Journal Service...
10845 12:31:58.186983 Starting [0;1;39mJournal Service[0m...
10846 12:31:58.206050 <30>[ 17.295654] systemd[1]: Starting Load Kernel Modules...
10847 12:31:58.212807 Starting [0;1;39mLoad Kernel Modules[0m...
10848 12:31:58.233797 <30>[ 17.319758] systemd[1]: Starting Remount Root and Kernel File Systems...
10849 12:31:58.240100 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10850 12:31:58.257670 <30>[ 17.347363] systemd[1]: Starting Coldplug All udev Devices...
10851 12:31:58.264441 Starting [0;1;39mColdplug All udev Devices[0m...
10852 12:31:58.282127 <30>[ 17.371664] systemd[1]: Mounted Huge Pages File System.
10853 12:31:58.288603 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10854 12:31:58.304241 <30>[ 17.393527] systemd[1]: Started Journal Service.
10855 12:31:58.310343 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10856 12:31:58.325110 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10857 12:31:58.339860 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10858 12:31:58.359886 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10859 12:31:58.376862 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10860 12:31:58.393124 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10861 12:31:58.409029 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10862 12:31:58.427956 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10863 12:31:58.443619 See 'systemctl status systemd-remount-fs.service' for details.
10864 12:31:58.479787 Mounting [0;1;39mKernel Configuration File System[0m...
10865 12:31:58.497785 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10866 12:31:58.514825 <46>[ 17.601382] systemd-journald[181]: Received client request to flush runtime journal.
10867 12:31:58.523496 Starting [0;1;39mLoad/Save Random Seed[0m...
10868 12:31:58.546167 Starting [0;1;39mApply Kernel Variables[0m...
10869 12:31:58.562631 Starting [0;1;39mCreate System Users[0m...
10870 12:31:58.583744 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10871 12:31:58.603657 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10872 12:31:58.616444 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10873 12:31:58.632317 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10874 12:31:58.652385 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10875 12:31:58.672086 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10876 12:31:58.699636 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10877 12:31:58.722481 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10878 12:31:58.735540 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10879 12:31:58.751016 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10880 12:31:58.795734 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10881 12:31:58.819380 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10882 12:31:58.839973 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10883 12:31:58.859410 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10884 12:31:58.900963 Starting [0;1;39mNetwork Time Synchronization[0m...
10885 12:31:58.920646 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10886 12:31:58.957786 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10887 12:31:59.008062 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10888 12:31:59.038003 <6>[ 18.124724] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10889 12:31:59.054342 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10890 12:31:59.057916 <6>[ 18.148474] remoteproc remoteproc0: scp is available
10891 12:31:59.067839 <4>[ 18.153987] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10892 12:31:59.078025 <3>[ 18.156351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 12:31:59.080910 <6>[ 18.163894] remoteproc remoteproc0: powering up scp
10894 12:31:59.090620 <4>[ 18.163927] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10895 12:31:59.097656 <3>[ 18.163932] remoteproc remoteproc0: request_firmware failed: -2
10896 12:31:59.107765 <3>[ 18.172045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 12:31:59.113982 <3>[ 18.201469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 12:31:59.123785 <6>[ 18.202992] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10899 12:31:59.126967 <6>[ 18.214906] usbcore: registered new interface driver r8152
10900 12:31:59.137189 [[0;32m OK [<3>[ 18.215877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 12:31:59.147084 0m] Reached targ<3>[ 18.215895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 12:31:59.156900 <3>[ 18.215903] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 12:31:59.163334 et [0;1;39mSyst<3>[ 18.215913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 12:31:59.173142 em Time Set[0m.<3>[ 18.215921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 12:31:59.173229
10906 12:31:59.183095 <3>[ 18.215959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 12:31:59.189658 <3>[ 18.216005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10908 12:31:59.199397 <3>[ 18.216013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 12:31:59.206361 <3>[ 18.216020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 12:31:59.215881 <3>[ 18.216061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 12:31:59.222637 <3>[ 18.216068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10912 12:31:59.232274 <3>[ 18.216075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 12:31:59.239348 <3>[ 18.216083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 12:31:59.248820 <3>[ 18.216090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 12:31:59.255716 <3>[ 18.216118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 12:31:59.265442 <6>[ 18.217416] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10917 12:31:59.268959 <6>[ 18.247218] mc: Linux media interface: v0.10
10918 12:31:59.278949 <6>[ 18.250074] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10919 12:31:59.282044 <6>[ 18.260876] Bluetooth: Core ver 2.22
10920 12:31:59.288600 <6>[ 18.261233] usbcore: registered new interface driver cdc_ether
10921 12:31:59.295035 <4>[ 18.278207] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10922 12:31:59.301627 <6>[ 18.285481] NET: Registered PF_BLUETOOTH protocol family
10923 12:31:59.305302 <6>[ 18.286344] videodev: Linux video capture interface: v2.00
10924 12:31:59.315305 <4>[ 18.294248] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10925 12:31:59.321660 <6>[ 18.301755] Bluetooth: HCI device and connection manager initialized
10926 12:31:59.325035 <6>[ 18.301798] Bluetooth: HCI socket layer initialized
10927 12:31:59.331421 <6>[ 18.301812] Bluetooth: L2CAP socket layer initialized
10928 12:31:59.335069 <6>[ 18.301840] Bluetooth: SCO socket layer initialized
10929 12:31:59.342099 <6>[ 18.318284] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10930 12:31:59.352096 <6>[ 18.327003] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10931 12:31:59.358466 <4>[ 18.372677] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10932 12:31:59.364894 <6>[ 18.394261] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10933 12:31:59.375309 <4>[ 18.395811] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10934 12:31:59.381871 <6>[ 18.401287] pci_bus 0000:00: root bus resource [bus 00-ff]
10935 12:31:59.388492 <4>[ 18.402671] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10936 12:31:59.395063 <4>[ 18.402671] Fallback method does not support PEC.
10937 12:31:59.405414 <6>[ 18.409721] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10938 12:31:59.411995 <6>[ 18.415141] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10939 12:31:59.421558 <6>[ 18.415147] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10940 12:31:59.428628 <6>[ 18.415210] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10941 12:31:59.434995 <3>[ 18.430105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 12:31:59.444938 <6>[ 18.431097] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10943 12:31:59.451932 <6>[ 18.434721] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10944 12:31:59.459520 <6>[ 18.456380] r8152 2-1.3:1.0 eth0: v1.12.13
10945 12:31:59.465857 <6>[ 18.460791] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10946 12:31:59.475562 <3>[ 18.460902] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:31:59.479353 <6>[ 18.461593] pci 0000:00:00.0: supports D1 D2
10948 12:31:59.489065 <3>[ 18.495685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 12:31:59.496141 <6>[ 18.499070] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10950 12:31:59.502423 <6>[ 18.499780] usbcore: registered new interface driver r8153_ecm
10951 12:31:59.509376 <6>[ 18.512973] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10952 12:31:59.515690 <6>[ 18.518108] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10953 12:31:59.522704 <6>[ 18.553728] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10954 12:31:59.529001 <6>[ 18.561544] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10955 12:31:59.535884 <6>[ 18.562197] usbcore: registered new interface driver btusb
10956 12:31:59.545354 <4>[ 18.563580] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10957 12:31:59.552414 <3>[ 18.563597] Bluetooth: hci0: Failed to load firmware file (-2)
10958 12:31:59.555594 <3>[ 18.563603] Bluetooth: hci0: Failed to set up firmware (-2)
10959 12:31:59.568954 <4>[ 18.563608] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10960 12:31:59.578527 <6>[ 18.571563] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10961 12:31:59.589113 <3>[ 18.573897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 12:31:59.595675 <6>[ 18.574697] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10963 12:31:59.602249 <6>[ 18.583711] usbcore: registered new interface driver uvcvideo
10964 12:31:59.612419 <3>[ 18.583778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10965 12:31:59.618964 <6>[ 18.584448] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10966 12:31:59.625837 <6>[ 18.590333] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10967 12:31:59.629054 <6>[ 18.590377] remoteproc remoteproc0: powering up scp
10968 12:31:59.639839 <4>[ 18.590446] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10969 12:31:59.646209 <3>[ 18.590455] remoteproc remoteproc0: request_firmware failed: -2
10970 12:31:59.652980 <3>[ 18.590459] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10971 12:31:59.662658 <3>[ 18.594354] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 12:31:59.670126 <3>[ 18.614441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 12:31:59.679635 <6>[ 18.617803] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10974 12:31:59.683323 <6>[ 18.617929] pci 0000:01:00.0: supports D1 D2
10975 12:31:59.694117 <3>[ 18.647378] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 12:31:59.699996 <6>[ 18.652238] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10977 12:31:59.707421 <6>[ 18.664637] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10978 12:31:59.714471 <3>[ 18.695955] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 12:31:59.724546 <6>[ 18.697457] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10980 12:31:59.731171 <3>[ 18.728556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 12:31:59.738439 <6>[ 18.735134] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10982 12:31:59.748613 <6>[ 18.735147] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10983 12:31:59.754761 <6>[ 18.842530] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10984 12:31:59.764763 <6>[ 18.842547] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10985 12:31:59.767748 <6>[ 18.842562] pci 0000:00:00.0: PCI bridge to [bus 01]
10986 12:31:59.778003 <6>[ 18.842570] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10987 12:31:59.784272 <6>[ 18.842745] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10988 12:31:59.790939 [[0;32m OK [<6>[ 18.879069] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10989 12:31:59.797195 0m] Reached targ<6>[ 18.886185] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10990 12:31:59.800454 et [0;1;39mSystem Time Synchronized[0m.
10991 12:31:59.817916 <5>[ 18.904468] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10992 12:31:59.837825 <5>[ 18.924168] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10993 12:31:59.844105 <4>[ 18.931120] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10994 12:31:59.851337 <6>[ 18.940183] cfg80211: failed to load regulatory.db
10995 12:31:59.867461 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10996 12:31:59.897737 [[0;32m OK [0m] Found device [0;1;39m/dev/t<6>[ 18.984987] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10997 12:31:59.898001 tyS0[0m.
10998 12:31:59.904006 <6>[ 18.992718] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10999 12:31:59.914953 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11000 12:31:59.930391 <6>[ 19.020287] mt7921e 0000:01:00.0: ASIC revision: 79610010
11001 12:32:00.036728 <4>[ 19.120250] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 12:32:00.095659 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11003 12:32:00.110765 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11004 12:32:00.130742 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11005 12:32:00.160255 [[0;32m OK [0m] Started [0;1;39mDaily Clean<4>[ 19.243522] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 12:32:00.163830 up of Temporary Directories[0m.
11007 12:32:00.169958 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11008 12:32:00.186903 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11009 12:32:00.198834 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11010 12:32:00.215243 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11011 12:32:00.234695 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11012 12:32:00.279653 [[0;32m OK [<4>[ 19.363333] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11013 12:32:00.286270 0m] Started [0;1;39mD-Bus System Message Bus[0m.
11014 12:32:00.311663 Starting [0;1;39mUser Login Management[0m...
11015 12:32:00.329895 Starting [0;1;39mPermit User Sessions[0m...
11016 12:32:00.347142 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11017 12:32:00.363553 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11018 12:32:00.380169 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11019 12:32:00.408355 <4>[ 19.488716] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11020 12:32:00.448279 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11021 12:32:00.466152 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11022 12:32:00.483584 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11023 12:32:00.518135 [[0;32m OK [0m] Started [0;<4>[ 19.599622] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11024 12:32:00.521234 1;39mUser Login Management[0m.
11025 12:32:00.538180 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11026 12:32:00.555036 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11027 12:32:00.610777 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11028 12:32:00.637716 <4>[ 19.720719] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11029 12:32:00.644052 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11030 12:32:00.661605
11031 12:32:00.661812
11032 12:32:00.665326 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11033 12:32:00.665509
11034 12:32:00.668345 debian-bullseye-arm64 login: root (automatic login)
11035 12:32:00.668561
11036 12:32:00.668709
11037 12:32:00.685470 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11038 12:32:00.685657
11039 12:32:00.691998 The programs included with the Debian GNU/Linux system are free software;
11040 12:32:00.698499 the exact distribution terms for each program are described in the
11041 12:32:00.701609 individual files in /usr/share/doc/*/copyright.
11042 12:32:00.701804
11043 12:32:00.708377 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11044 12:32:00.711384 permitted by applicable law.
11045 12:32:00.711943 Matched prompt #10: / #
11047 12:32:00.712384 Setting prompt string to ['/ #']
11048 12:32:00.712577 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11050 12:32:00.713004 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11051 12:32:00.713192 start: 2.2.6 expect-shell-connection (timeout 00:02:42) [common]
11052 12:32:00.713348 Setting prompt string to ['/ #']
11053 12:32:00.713482 Forcing a shell prompt, looking for ['/ #']
11055 12:32:00.763819 / #
11056 12:32:00.763969 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11057 12:32:00.764047 Waiting using forced prompt support (timeout 00:02:30)
11058 12:32:00.764149 <4>[ 19.839055] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11059 12:32:00.769606
11060 12:32:00.769873 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11061 12:32:00.769968 start: 2.2.7 export-device-env (timeout 00:02:42) [common]
11062 12:32:00.770060 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11063 12:32:00.770149 end: 2.2 depthcharge-retry (duration 00:02:18) [common]
11064 12:32:00.770231 end: 2 depthcharge-action (duration 00:02:18) [common]
11065 12:32:00.770315 start: 3 lava-test-retry (timeout 00:07:19) [common]
11066 12:32:00.770405 start: 3.1 lava-test-shell (timeout 00:07:19) [common]
11067 12:32:00.770477 Using namespace: common
11069 12:32:00.870781 / ##
11070 12:32:00.870985 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11071 12:32:00.915007 #<4>[ 19.959097] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11072 12:32:00.915107
11073 12:32:00.915362 Using /lava-10605798
11075 12:32:01.015702 / # export SHELL=/bin/sh
11076 12:32:01.015952 export SHELL=/bin/sh<4>[ 20.079138] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11077 12:32:01.020650
11079 12:32:01.121347 / # . /lava-10605798/environment
11080 12:32:01.121636 . /lava-10605798/environment<4>[ 20.199175] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11081 12:32:01.126487
11083 12:32:01.267696 / # /lava-10605798/bin/lava-test-runner /lava-10605798/0
11084 12:32:01.268226 Test shell timeout: 10s (minimum of the action and connection timeout)
11085 12:32:01.269569 /lava-1060579<3>[ 20.317161] mt7921e 0000:01:00.0: hardware init failed
11086 12:32:01.273781 8/bin/lava-test-runner /lava-10605
11087 12:32:01.283259 /lava-10605798/bin/lava-test-runner: 18: .: cannot open /lava-10605/../bin/lava-common-functions: No such file
11088 12:32:29.113206 / # <6>[ 48.208919] vpu: disabling
11089 12:32:29.116367 <6>[ 48.211998] vproc2: disabling
11090 12:32:29.119412 <6>[ 48.215290] vproc1: disabling
11091 12:32:29.122601 <6>[ 48.218553] vaud18: disabling
11092 12:32:29.129523 <6>[ 48.221956] vsram_others: disabling
11093 12:32:29.132647 <6>[ 48.225831] va09: disabling
11094 12:32:29.135462 <6>[ 48.228937] vsram_md: disabling
11095 12:32:29.138963 <6>[ 48.232422] Vgpu: disabling
11097 12:39:19.771680 end: 3.1 lava-test-shell (duration 00:07:19) [common]
11099 12:39:19.772820 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 439 seconds'
11101 12:39:19.773642 end: 3 lava-test-retry (duration 00:07:19) [common]
11103 12:39:19.774768 Cleaning after the job
11104 12:39:19.775312 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/ramdisk
11105 12:39:19.803496 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/kernel
11106 12:39:19.828054 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/dtb
11107 12:39:19.828324 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605798/tftp-deploy-baj79x3r/modules
11108 12:39:19.835273 start: 4.1 power-off (timeout 00:00:30) [common]
11109 12:39:19.835644 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11110 12:39:19.916861 >> Command sent successfully.
11111 12:39:19.928301 Returned 0 in 0 seconds
11112 12:39:20.029604 end: 4.1 power-off (duration 00:00:00) [common]
11114 12:39:20.031449 start: 4.2 read-feedback (timeout 00:10:00) [common]
11115 12:39:20.032769 Listened to connection for namespace 'common' for up to 1s
11116 12:39:21.033421 Finalising connection for namespace 'common'
11117 12:39:21.034171 Disconnecting from shell: Finalise
11118 12:39:21.135236 end: 4.2 read-feedback (duration 00:00:01) [common]
11119 12:39:21.135904 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605798
11120 12:39:21.265334 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605798
11121 12:39:21.265529 TestError: A test failed to run, look at the error message.