Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 12:28:59.443033 lava-dispatcher, installed at version: 2023.05.1
2 12:28:59.443251 start: 0 validate
3 12:28:59.443399 Start time: 2023-06-06 12:28:59.443391+00:00 (UTC)
4 12:28:59.443533 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:28:59.443675 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:28:59.737199 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:28:59.737381 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:29:00.024703 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:29:00.024917 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:29:00.312503 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:29:00.312691 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:29:00.599578 validate duration: 1.16
14 12:29:00.599949 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:29:00.600090 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:29:00.600209 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:29:00.600372 Not decompressing ramdisk as can be used compressed.
18 12:29:00.600491 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 12:29:00.600570 saving as /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/ramdisk/rootfs.cpio.gz
20 12:29:00.600635 total size: 43394293 (41MB)
21 12:29:00.602215 progress 0% (0MB)
22 12:29:00.613772 progress 5% (2MB)
23 12:29:00.625547 progress 10% (4MB)
24 12:29:00.637367 progress 15% (6MB)
25 12:29:00.648896 progress 20% (8MB)
26 12:29:00.660137 progress 25% (10MB)
27 12:29:00.671131 progress 30% (12MB)
28 12:29:00.682233 progress 35% (14MB)
29 12:29:00.693240 progress 40% (16MB)
30 12:29:00.704302 progress 45% (18MB)
31 12:29:00.715548 progress 50% (20MB)
32 12:29:00.726533 progress 55% (22MB)
33 12:29:00.737549 progress 60% (24MB)
34 12:29:00.748680 progress 65% (26MB)
35 12:29:00.759923 progress 70% (29MB)
36 12:29:00.770960 progress 75% (31MB)
37 12:29:00.782069 progress 80% (33MB)
38 12:29:00.793183 progress 85% (35MB)
39 12:29:00.804235 progress 90% (37MB)
40 12:29:00.815199 progress 95% (39MB)
41 12:29:00.826057 progress 100% (41MB)
42 12:29:00.826231 41MB downloaded in 0.23s (183.45MB/s)
43 12:29:00.826388 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:29:00.826640 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:29:00.826729 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:29:00.826814 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:29:00.826946 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:29:00.827021 saving as /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/kernel/Image
50 12:29:00.827084 total size: 45746688 (43MB)
51 12:29:00.827146 No compression specified
52 12:29:00.828255 progress 0% (0MB)
53 12:29:00.839882 progress 5% (2MB)
54 12:29:00.851458 progress 10% (4MB)
55 12:29:00.863117 progress 15% (6MB)
56 12:29:00.874763 progress 20% (8MB)
57 12:29:00.886362 progress 25% (10MB)
58 12:29:00.897741 progress 30% (13MB)
59 12:29:00.909349 progress 35% (15MB)
60 12:29:00.920934 progress 40% (17MB)
61 12:29:00.932472 progress 45% (19MB)
62 12:29:00.944095 progress 50% (21MB)
63 12:29:00.955756 progress 55% (24MB)
64 12:29:00.967398 progress 60% (26MB)
65 12:29:00.979023 progress 65% (28MB)
66 12:29:00.990698 progress 70% (30MB)
67 12:29:01.002366 progress 75% (32MB)
68 12:29:01.013909 progress 80% (34MB)
69 12:29:01.025708 progress 85% (37MB)
70 12:29:01.037845 progress 90% (39MB)
71 12:29:01.049906 progress 95% (41MB)
72 12:29:01.062248 progress 100% (43MB)
73 12:29:01.062452 43MB downloaded in 0.24s (185.36MB/s)
74 12:29:01.062617 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:29:01.062880 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:29:01.062970 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:29:01.063088 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:29:01.063220 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:29:01.063313 saving as /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/dtb/mt8192-asurada-spherion-r0.dtb
81 12:29:01.063398 total size: 46924 (0MB)
82 12:29:01.063459 No compression specified
83 12:29:01.064629 progress 69% (0MB)
84 12:29:01.064932 progress 100% (0MB)
85 12:29:01.065124 0MB downloaded in 0.00s (25.96MB/s)
86 12:29:01.065244 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:29:01.065466 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:29:01.065551 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:29:01.065633 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:29:01.065744 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:29:01.065811 saving as /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/modules/modules.tar
93 12:29:01.065872 total size: 8539116 (8MB)
94 12:29:01.065931 Using unxz to decompress xz
95 12:29:01.069496 progress 0% (0MB)
96 12:29:01.091714 progress 5% (0MB)
97 12:29:01.117942 progress 10% (0MB)
98 12:29:01.142368 progress 15% (1MB)
99 12:29:01.170772 progress 20% (1MB)
100 12:29:01.196704 progress 25% (2MB)
101 12:29:01.222300 progress 30% (2MB)
102 12:29:01.248089 progress 35% (2MB)
103 12:29:01.273005 progress 40% (3MB)
104 12:29:01.296828 progress 45% (3MB)
105 12:29:01.322244 progress 50% (4MB)
106 12:29:01.346952 progress 55% (4MB)
107 12:29:01.372428 progress 60% (4MB)
108 12:29:01.398269 progress 65% (5MB)
109 12:29:01.423668 progress 70% (5MB)
110 12:29:01.450281 progress 75% (6MB)
111 12:29:01.480840 progress 80% (6MB)
112 12:29:01.503687 progress 85% (6MB)
113 12:29:01.528072 progress 90% (7MB)
114 12:29:01.552722 progress 95% (7MB)
115 12:29:01.576791 progress 100% (8MB)
116 12:29:01.582508 8MB downloaded in 0.52s (15.76MB/s)
117 12:29:01.582808 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:29:01.583072 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:29:01.583166 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:29:01.583262 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:29:01.583357 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:29:01.583468 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:29:01.583734 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9
125 12:29:01.583867 makedir: /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin
126 12:29:01.583990 makedir: /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/tests
127 12:29:01.584142 makedir: /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/results
128 12:29:01.584308 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-add-keys
129 12:29:01.584501 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-add-sources
130 12:29:01.584676 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-background-process-start
131 12:29:01.584851 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-background-process-stop
132 12:29:01.585019 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-common-functions
133 12:29:01.585176 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-echo-ipv4
134 12:29:01.585343 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-install-packages
135 12:29:01.585508 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-installed-packages
136 12:29:01.585679 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-os-build
137 12:29:01.585842 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-probe-channel
138 12:29:01.586006 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-probe-ip
139 12:29:01.586169 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-target-ip
140 12:29:01.586325 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-target-mac
141 12:29:01.586488 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-target-storage
142 12:29:01.586655 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-case
143 12:29:01.586812 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-event
144 12:29:01.586975 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-feedback
145 12:29:01.587139 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-raise
146 12:29:01.587301 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-reference
147 12:29:01.587479 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-runner
148 12:29:01.587647 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-set
149 12:29:01.587777 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-test-shell
150 12:29:01.587923 Updating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-install-packages (oe)
151 12:29:01.627821 Updating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/bin/lava-installed-packages (oe)
152 12:29:01.627994 Creating /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/environment
153 12:29:01.628111 LAVA metadata
154 12:29:01.628189 - LAVA_JOB_ID=10605787
155 12:29:01.628260 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:29:01.628381 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:29:01.628451 skipped lava-vland-overlay
158 12:29:01.628528 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:29:01.628611 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:29:01.628674 skipped lava-multinode-overlay
161 12:29:01.628750 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:29:01.628832 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:29:01.628913 Loading test definitions
164 12:29:01.629009 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:29:01.629085 Using /lava-10605787 at stage 0
166 12:29:01.629389 uuid=10605787_1.5.2.3.1 testdef=None
167 12:29:01.629481 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:29:01.629570 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:29:01.630095 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:29:01.630333 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:29:01.655449 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:29:01.655714 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:29:01.660167 runner path: /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/0/tests/0_igt-kms-mediatek test_uuid 10605787_1.5.2.3.1
176 12:29:01.660349 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:29:01.660572 Creating lava-test-runner.conf files
179 12:29:01.660640 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605787/lava-overlay-90z2o9z9/lava-10605787/0 for stage 0
180 12:29:01.660731 - 0_igt-kms-mediatek
181 12:29:01.660830 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:29:01.660919 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:29:01.667594 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:29:01.667707 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:29:01.667797 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:29:01.667885 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:29:01.667978 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:29:03.050046 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:29:03.050471 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:29:03.050585 extracting modules file /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605787/extract-overlay-ramdisk-72dmfl6e/ramdisk
191 12:29:03.271121 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:29:03.271296 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:29:03.271404 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605787/compress-overlay-d1__ulll/overlay-1.5.2.4.tar.gz to ramdisk
194 12:29:03.271479 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605787/compress-overlay-d1__ulll/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605787/extract-overlay-ramdisk-72dmfl6e/ramdisk
195 12:29:03.277997 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:29:03.278125 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:29:03.278219 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:29:03.278310 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:29:03.278391 Building ramdisk /var/lib/lava/dispatcher/tmp/10605787/extract-overlay-ramdisk-72dmfl6e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605787/extract-overlay-ramdisk-72dmfl6e/ramdisk
200 12:29:05.191717 >> 369045 blocks
201 12:29:11.409282 rename /var/lib/lava/dispatcher/tmp/10605787/extract-overlay-ramdisk-72dmfl6e/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/ramdisk/ramdisk.cpio.gz
202 12:29:11.409711 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 12:29:11.409836 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 12:29:11.409937 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 12:29:11.410048 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/kernel/Image'
206 12:29:24.037817 Returned 0 in 12 seconds
207 12:29:24.138685 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/kernel/image.itb
208 12:29:24.956494 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:29:24.956838 output: Created: Tue Jun 6 13:29:24 2023
210 12:29:24.956914 output: Image 0 (kernel-1)
211 12:29:24.956982 output: Description:
212 12:29:24.957050 output: Created: Tue Jun 6 13:29:24 2023
213 12:29:24.957115 output: Type: Kernel Image
214 12:29:24.957176 output: Compression: lzma compressed
215 12:29:24.957240 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
216 12:29:24.957303 output: Architecture: AArch64
217 12:29:24.957363 output: OS: Linux
218 12:29:24.957422 output: Load Address: 0x00000000
219 12:29:24.957477 output: Entry Point: 0x00000000
220 12:29:24.957534 output: Hash algo: crc32
221 12:29:24.957588 output: Hash value: a26c3f91
222 12:29:24.957641 output: Image 1 (fdt-1)
223 12:29:24.957694 output: Description: mt8192-asurada-spherion-r0
224 12:29:24.957747 output: Created: Tue Jun 6 13:29:24 2023
225 12:29:24.957801 output: Type: Flat Device Tree
226 12:29:24.957855 output: Compression: uncompressed
227 12:29:24.957909 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:29:24.957964 output: Architecture: AArch64
229 12:29:24.958018 output: Hash algo: crc32
230 12:29:24.958072 output: Hash value: 1df858fa
231 12:29:24.958125 output: Image 2 (ramdisk-1)
232 12:29:24.958179 output: Description: unavailable
233 12:29:24.958232 output: Created: Tue Jun 6 13:29:24 2023
234 12:29:24.958286 output: Type: RAMDisk Image
235 12:29:24.958339 output: Compression: Unknown Compression
236 12:29:24.958393 output: Data Size: 56375568 Bytes = 55054.27 KiB = 53.76 MiB
237 12:29:24.958446 output: Architecture: AArch64
238 12:29:24.958500 output: OS: Linux
239 12:29:24.958553 output: Load Address: unavailable
240 12:29:24.958606 output: Entry Point: unavailable
241 12:29:24.958659 output: Hash algo: crc32
242 12:29:24.958712 output: Hash value: 4460587f
243 12:29:24.958765 output: Default Configuration: 'conf-1'
244 12:29:24.958818 output: Configuration 0 (conf-1)
245 12:29:24.958871 output: Description: mt8192-asurada-spherion-r0
246 12:29:24.958924 output: Kernel: kernel-1
247 12:29:24.958977 output: Init Ramdisk: ramdisk-1
248 12:29:24.959031 output: FDT: fdt-1
249 12:29:24.959084 output: Loadables: kernel-1
250 12:29:24.959137 output:
251 12:29:24.959333 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:29:24.959473 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:29:24.959578 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 12:29:24.959671 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 12:29:24.959748 No LXC device requested
256 12:29:24.959829 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:29:24.959916 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 12:29:24.959993 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:29:24.960064 Checking files for TFTP limit of 4294967296 bytes.
260 12:29:24.960560 end: 1 tftp-deploy (duration 00:00:24) [common]
261 12:29:24.960670 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:29:24.960761 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:29:24.960888 substitutions:
264 12:29:24.960955 - {DTB}: 10605787/tftp-deploy-0onrf3em/dtb/mt8192-asurada-spherion-r0.dtb
265 12:29:24.961021 - {INITRD}: 10605787/tftp-deploy-0onrf3em/ramdisk/ramdisk.cpio.gz
266 12:29:24.961081 - {KERNEL}: 10605787/tftp-deploy-0onrf3em/kernel/Image
267 12:29:24.961139 - {LAVA_MAC}: None
268 12:29:24.961196 - {PRESEED_CONFIG}: None
269 12:29:24.961253 - {PRESEED_LOCAL}: None
270 12:29:24.961309 - {RAMDISK}: 10605787/tftp-deploy-0onrf3em/ramdisk/ramdisk.cpio.gz
271 12:29:24.961365 - {ROOT_PART}: None
272 12:29:24.961420 - {ROOT}: None
273 12:29:24.961476 - {SERVER_IP}: 192.168.201.1
274 12:29:24.961531 - {TEE}: None
275 12:29:24.961585 Parsed boot commands:
276 12:29:24.961640 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:29:24.961806 Parsed boot commands: tftpboot 192.168.201.1 10605787/tftp-deploy-0onrf3em/kernel/image.itb 10605787/tftp-deploy-0onrf3em/kernel/cmdline
278 12:29:24.961895 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:29:24.961985 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:29:24.962076 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:29:24.962161 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:29:24.962236 Not connected, no need to disconnect.
283 12:29:24.962312 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:29:24.962393 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:29:24.962462 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 12:29:24.965766 Setting prompt string to ['lava-test: # ']
287 12:29:24.966107 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:29:24.966212 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:29:24.966316 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:29:24.966414 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:29:24.966611 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 12:29:30.114183 >> Command sent successfully.
293 12:29:30.124412 Returned 0 in 5 seconds
294 12:29:30.225802 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:29:30.229447 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:29:30.230249 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:29:30.230955 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:29:30.231589 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:29:30.232223 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:29:30.234027 [Enter `^Ec?' for help]
302 12:29:30.390697
303 12:29:30.391430
304 12:29:30.392035 F0: 102B 0000
305 12:29:30.392555
306 12:29:30.394452 F3: 1001 0000 [0200]
307 12:29:30.394911
308 12:29:30.395265 F3: 1001 0000
309 12:29:30.395642
310 12:29:30.395959 F7: 102D 0000
311 12:29:30.396275
312 12:29:30.397437 F1: 0000 0000
313 12:29:30.397984
314 12:29:30.398331 V0: 0000 0000 [0001]
315 12:29:30.398672
316 12:29:30.400745 00: 0007 8000
317 12:29:30.401328
318 12:29:30.401710 01: 0000 0000
319 12:29:30.402096
320 12:29:30.404108 BP: 0C00 0209 [0000]
321 12:29:30.404686
322 12:29:30.405177 G0: 1182 0000
323 12:29:30.405645
324 12:29:30.406100 EC: 0000 0021 [4000]
325 12:29:30.408031
326 12:29:30.408434 S7: 0000 0000 [0000]
327 12:29:30.408796
328 12:29:30.409135 CC: 0000 0000 [0001]
329 12:29:30.411361
330 12:29:30.411730 T0: 0000 0040 [010F]
331 12:29:30.412088
332 12:29:30.412478 Jump to BL
333 12:29:30.412786
334 12:29:30.438220
335 12:29:30.438747
336 12:29:30.439103
337 12:29:30.445105 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:29:30.449270 ARM64: Exception handlers installed.
339 12:29:30.452537 ARM64: Testing exception
340 12:29:30.455686 ARM64: Done test exception
341 12:29:30.462090 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:29:30.473059 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:29:30.479689 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:29:30.489649 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:29:30.496751 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:29:30.503179 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:29:30.515083 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:29:30.521309 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:29:30.540555 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:29:30.544052 WDT: Last reset was cold boot
351 12:29:30.546904 SPI1(PAD0) initialized at 2873684 Hz
352 12:29:30.550922 SPI5(PAD0) initialized at 992727 Hz
353 12:29:30.553713 VBOOT: Loading verstage.
354 12:29:30.560303 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:29:30.564078 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:29:30.567570 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:29:30.570979 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:29:30.578229 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:29:30.584925 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:29:30.595701 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:29:30.596281
362 12:29:30.596697
363 12:29:30.606173 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:29:30.609489 ARM64: Exception handlers installed.
365 12:29:30.613139 ARM64: Testing exception
366 12:29:30.613694 ARM64: Done test exception
367 12:29:30.619441 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:29:30.623273 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:29:30.636900 Probing TPM: . done!
370 12:29:30.637489 TPM ready after 0 ms
371 12:29:30.643849 Connected to device vid:did:rid of 1ae0:0028:00
372 12:29:30.651007 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 12:29:30.712132 Initialized TPM device CR50 revision 0
374 12:29:30.715394 tlcl_send_startup: Startup return code is 0
375 12:29:30.721709 TPM: setup succeeded
376 12:29:30.732887 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:29:30.742318 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:29:30.755381 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:29:30.762660 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:29:30.766834 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:29:30.770094 in-header: 03 07 00 00 08 00 00 00
382 12:29:30.774095 in-data: aa e4 47 04 13 02 00 00
383 12:29:30.777475 Chrome EC: UHEPI supported
384 12:29:30.780961 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:29:30.784806 in-header: 03 95 00 00 08 00 00 00
386 12:29:30.789002 in-data: 18 20 20 08 00 00 00 00
387 12:29:30.789467 Phase 1
388 12:29:30.792433 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:29:30.799778 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:29:30.807968 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:29:30.808560 Recovery requested (1009000e)
392 12:29:30.819385 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:29:30.823545 tlcl_extend: response is 0
394 12:29:30.832570 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:29:30.838113 tlcl_extend: response is 0
396 12:29:30.844948 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:29:30.864665 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:29:30.871428 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:29:30.871947
400 12:29:30.872311
401 12:29:30.881735 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:29:30.885317 ARM64: Exception handlers installed.
403 12:29:30.888465 ARM64: Testing exception
404 12:29:30.888931 ARM64: Done test exception
405 12:29:30.910415 pmic_efuse_setting: Set efuses in 11 msecs
406 12:29:30.913668 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:29:30.920186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:29:30.923988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:29:30.930669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:29:30.934600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:29:30.938509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:29:30.942315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:29:30.950072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:29:30.953425 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:29:30.957097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:29:30.960762 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:29:30.968541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:29:30.972557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:29:30.976695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:29:30.984200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:29:30.987595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:29:30.994823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:29:30.998907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:29:31.005644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:29:31.009745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:29:31.017161 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:29:31.020969 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:29:31.028865 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:29:31.032011 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:29:31.039781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:29:31.043917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:29:31.051142 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:29:31.055047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:29:31.058793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:29:31.065989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:29:31.069798 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:29:31.073595 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:29:31.080924 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:29:31.084228 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:29:31.088168 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:29:31.095539 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:29:31.098808 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:29:31.106370 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:29:31.110394 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:29:31.113770 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:29:31.117180 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:29:31.121193 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:29:31.128372 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:29:31.132092 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:29:31.135838 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:29:31.139751 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:29:31.143552 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:29:31.147611 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:29:31.154633 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:29:31.158510 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:29:31.161754 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:29:31.165529 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:29:31.173574 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:29:31.181006 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:29:31.188465 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:29:31.195523 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:29:31.202988 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:29:31.206342 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:29:31.210360 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:29:31.217945 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:29:31.224825 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 12:29:31.228822 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:29:31.232682 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:29:31.236458 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:29:31.248194 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 12:29:31.257104 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 12:29:31.267054 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 12:29:31.276214 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 12:29:31.285761 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 12:29:31.295442 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 12:29:31.305584 [RTC]rtc_get_frequency_meter,154: input=17, output=806
477 12:29:31.309043 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:29:31.312952 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:29:31.316545 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:29:31.324626 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:29:31.327970 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:29:31.332013 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:29:31.335276 ADC[4]: Raw value=906203 ID=7
484 12:29:31.335769 ADC[3]: Raw value=213441 ID=1
485 12:29:31.339104 RAM Code: 0x71
486 12:29:31.342369 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:29:31.346205 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:29:31.357775 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:29:31.361512 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:29:31.365321 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:29:31.369954 in-header: 03 07 00 00 08 00 00 00
492 12:29:31.373644 in-data: aa e4 47 04 13 02 00 00
493 12:29:31.376803 Chrome EC: UHEPI supported
494 12:29:31.384078 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:29:31.387668 in-header: 03 95 00 00 08 00 00 00
496 12:29:31.391629 in-data: 18 20 20 08 00 00 00 00
497 12:29:31.392092 MRC: failed to locate region type 0.
498 12:29:31.399301 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:29:31.403142 DRAM-K: Running full calibration
500 12:29:31.410791 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:29:31.411266 header.status = 0x0
502 12:29:31.414083 header.version = 0x6 (expected: 0x6)
503 12:29:31.417633 header.size = 0xd00 (expected: 0xd00)
504 12:29:31.418101 header.flags = 0x0
505 12:29:31.424303 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:29:31.443789 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 12:29:31.451037 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:29:31.454110 dram_init: ddr_geometry: 2
509 12:29:31.454433 [EMI] MDL number = 2
510 12:29:31.458087 [EMI] Get MDL freq = 0
511 12:29:31.458396 dram_init: ddr_type: 0
512 12:29:31.462131 is_discrete_lpddr4: 1
513 12:29:31.465972 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:29:31.466284
515 12:29:31.466530
516 12:29:31.466763 [Bian_co] ETT version 0.0.0.1
517 12:29:31.470328 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:29:31.470641
519 12:29:31.477358 dramc_set_vcore_voltage set vcore to 650000
520 12:29:31.477676 Read voltage for 800, 4
521 12:29:31.477926 Vio18 = 0
522 12:29:31.481114 Vcore = 650000
523 12:29:31.481577 Vdram = 0
524 12:29:31.481970 Vddq = 0
525 12:29:31.482327 Vmddr = 0
526 12:29:31.484758 dram_init: config_dvfs: 1
527 12:29:31.489184 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:29:31.496080 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:29:31.500321 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 12:29:31.503670 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 12:29:31.507369 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 12:29:31.511457 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 12:29:31.511656 MEM_TYPE=3, freq_sel=18
534 12:29:31.514914 sv_algorithm_assistance_LP4_1600
535 12:29:31.521655 ============ PULL DRAM RESETB DOWN ============
536 12:29:31.525019 ========== PULL DRAM RESETB DOWN end =========
537 12:29:31.528276 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:29:31.531624 ===================================
539 12:29:31.535629 LPDDR4 DRAM CONFIGURATION
540 12:29:31.538894 ===================================
541 12:29:31.539090 EX_ROW_EN[0] = 0x0
542 12:29:31.543054 EX_ROW_EN[1] = 0x0
543 12:29:31.543319 LP4Y_EN = 0x0
544 12:29:31.546513 WORK_FSP = 0x0
545 12:29:31.546792 WL = 0x2
546 12:29:31.549881 RL = 0x2
547 12:29:31.550082 BL = 0x2
548 12:29:31.553269 RPST = 0x0
549 12:29:31.553488 RD_PRE = 0x0
550 12:29:31.557224 WR_PRE = 0x1
551 12:29:31.557441 WR_PST = 0x0
552 12:29:31.560511 DBI_WR = 0x0
553 12:29:31.560715 DBI_RD = 0x0
554 12:29:31.563714 OTF = 0x1
555 12:29:31.567129 ===================================
556 12:29:31.570353 ===================================
557 12:29:31.570471 ANA top config
558 12:29:31.573665 ===================================
559 12:29:31.576794 DLL_ASYNC_EN = 0
560 12:29:31.580608 ALL_SLAVE_EN = 1
561 12:29:31.580802 NEW_RANK_MODE = 1
562 12:29:31.583771 DLL_IDLE_MODE = 1
563 12:29:31.586841 LP45_APHY_COMB_EN = 1
564 12:29:31.590600 TX_ODT_DIS = 1
565 12:29:31.590749 NEW_8X_MODE = 1
566 12:29:31.594381 ===================================
567 12:29:31.597697 ===================================
568 12:29:31.601334 data_rate = 1600
569 12:29:31.604524 CKR = 1
570 12:29:31.608123 DQ_P2S_RATIO = 8
571 12:29:31.611158 ===================================
572 12:29:31.611283 CA_P2S_RATIO = 8
573 12:29:31.614321 DQ_CA_OPEN = 0
574 12:29:31.617744 DQ_SEMI_OPEN = 0
575 12:29:31.621219 CA_SEMI_OPEN = 0
576 12:29:31.624656 CA_FULL_RATE = 0
577 12:29:31.627986 DQ_CKDIV4_EN = 1
578 12:29:31.628084 CA_CKDIV4_EN = 1
579 12:29:31.631201 CA_PREDIV_EN = 0
580 12:29:31.634713 PH8_DLY = 0
581 12:29:31.638212 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:29:31.641423 DQ_AAMCK_DIV = 4
583 12:29:31.644854 CA_AAMCK_DIV = 4
584 12:29:31.644997 CA_ADMCK_DIV = 4
585 12:29:31.648252 DQ_TRACK_CA_EN = 0
586 12:29:31.651509 CA_PICK = 800
587 12:29:31.654920 CA_MCKIO = 800
588 12:29:31.658298 MCKIO_SEMI = 0
589 12:29:31.662262 PLL_FREQ = 3068
590 12:29:31.662478 DQ_UI_PI_RATIO = 32
591 12:29:31.665953 CA_UI_PI_RATIO = 0
592 12:29:31.669737 ===================================
593 12:29:31.673945 ===================================
594 12:29:31.674205 memory_type:LPDDR4
595 12:29:31.677345 GP_NUM : 10
596 12:29:31.681324 SRAM_EN : 1
597 12:29:31.681579 MD32_EN : 0
598 12:29:31.685176 ===================================
599 12:29:31.688427 [ANA_INIT] >>>>>>>>>>>>>>
600 12:29:31.688694 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:29:31.692257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:29:31.696008 ===================================
603 12:29:31.699018 data_rate = 1600,PCW = 0X7600
604 12:29:31.702645 ===================================
605 12:29:31.705734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:29:31.711918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:29:31.715346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:29:31.722350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:29:31.725460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:29:31.728793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:29:31.728882 [ANA_INIT] flow start
612 12:29:31.732104 [ANA_INIT] PLL >>>>>>>>
613 12:29:31.735470 [ANA_INIT] PLL <<<<<<<<
614 12:29:31.735558 [ANA_INIT] MIDPI >>>>>>>>
615 12:29:31.738775 [ANA_INIT] MIDPI <<<<<<<<
616 12:29:31.742176 [ANA_INIT] DLL >>>>>>>>
617 12:29:31.742265 [ANA_INIT] flow end
618 12:29:31.748804 ============ LP4 DIFF to SE enter ============
619 12:29:31.752220 ============ LP4 DIFF to SE exit ============
620 12:29:31.755606 [ANA_INIT] <<<<<<<<<<<<<
621 12:29:31.759144 [Flow] Enable top DCM control >>>>>
622 12:29:31.762501 [Flow] Enable top DCM control <<<<<
623 12:29:31.762589 Enable DLL master slave shuffle
624 12:29:31.769008 ==============================================================
625 12:29:31.772270 Gating Mode config
626 12:29:31.775481 ==============================================================
627 12:29:31.778674 Config description:
628 12:29:31.788693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:29:31.795387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:29:31.799232 SELPH_MODE 0: By rank 1: By Phase
631 12:29:31.805594 ==============================================================
632 12:29:31.809334 GAT_TRACK_EN = 1
633 12:29:31.812441 RX_GATING_MODE = 2
634 12:29:31.815515 RX_GATING_TRACK_MODE = 2
635 12:29:31.815600 SELPH_MODE = 1
636 12:29:31.818773 PICG_EARLY_EN = 1
637 12:29:31.822389 VALID_LAT_VALUE = 1
638 12:29:31.829254 ==============================================================
639 12:29:31.832280 Enter into Gating configuration >>>>
640 12:29:31.835529 Exit from Gating configuration <<<<
641 12:29:31.838896 Enter into DVFS_PRE_config >>>>>
642 12:29:31.848870 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:29:31.852230 Exit from DVFS_PRE_config <<<<<
644 12:29:31.855514 Enter into PICG configuration >>>>
645 12:29:31.858815 Exit from PICG configuration <<<<
646 12:29:31.862184 [RX_INPUT] configuration >>>>>
647 12:29:31.865538 [RX_INPUT] configuration <<<<<
648 12:29:31.868894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:29:31.875597 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:29:31.882674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:29:31.886041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:29:31.892117 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:29:31.898778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:29:31.902605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:29:31.909055 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:29:31.912307 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:29:31.916051 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:29:31.919175 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:29:31.925737 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:29:31.928923 ===================================
661 12:29:31.929067 LPDDR4 DRAM CONFIGURATION
662 12:29:31.932748 ===================================
663 12:29:31.935849 EX_ROW_EN[0] = 0x0
664 12:29:31.935991 EX_ROW_EN[1] = 0x0
665 12:29:31.939589 LP4Y_EN = 0x0
666 12:29:31.942941 WORK_FSP = 0x0
667 12:29:31.943084 WL = 0x2
668 12:29:31.945570 RL = 0x2
669 12:29:31.945682 BL = 0x2
670 12:29:31.949502 RPST = 0x0
671 12:29:31.949605 RD_PRE = 0x0
672 12:29:31.952330 WR_PRE = 0x1
673 12:29:31.952438 WR_PST = 0x0
674 12:29:31.955841 DBI_WR = 0x0
675 12:29:31.956092 DBI_RD = 0x0
676 12:29:31.959141 OTF = 0x1
677 12:29:31.962287 ===================================
678 12:29:31.965718 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:29:31.969140 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:29:31.972642 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:29:31.975824 ===================================
682 12:29:31.979196 LPDDR4 DRAM CONFIGURATION
683 12:29:31.982318 ===================================
684 12:29:31.986024 EX_ROW_EN[0] = 0x10
685 12:29:31.986145 EX_ROW_EN[1] = 0x0
686 12:29:31.989305 LP4Y_EN = 0x0
687 12:29:31.989413 WORK_FSP = 0x0
688 12:29:31.992645 WL = 0x2
689 12:29:31.992739 RL = 0x2
690 12:29:31.995925 BL = 0x2
691 12:29:31.996012 RPST = 0x0
692 12:29:31.999244 RD_PRE = 0x0
693 12:29:31.999341 WR_PRE = 0x1
694 12:29:32.002620 WR_PST = 0x0
695 12:29:32.005926 DBI_WR = 0x0
696 12:29:32.006013 DBI_RD = 0x0
697 12:29:32.009256 OTF = 0x1
698 12:29:32.012435 ===================================
699 12:29:32.015540 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:29:32.021179 nWR fixed to 40
701 12:29:32.024285 [ModeRegInit_LP4] CH0 RK0
702 12:29:32.024397 [ModeRegInit_LP4] CH0 RK1
703 12:29:32.027921 [ModeRegInit_LP4] CH1 RK0
704 12:29:32.031078 [ModeRegInit_LP4] CH1 RK1
705 12:29:32.031204 match AC timing 13
706 12:29:32.037979 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:29:32.041231 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:29:32.044416 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:29:32.051337 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:29:32.054732 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:29:32.055033 [EMI DOE] emi_dcm 0
712 12:29:32.061403 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:29:32.061767 ==
714 12:29:32.064975 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:29:32.068287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:29:32.068659 ==
717 12:29:32.075011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:29:32.081091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:29:32.088459 [CA 0] Center 36 (6~67) winsize 62
720 12:29:32.092386 [CA 1] Center 36 (6~67) winsize 62
721 12:29:32.095441 [CA 2] Center 34 (4~65) winsize 62
722 12:29:32.099008 [CA 3] Center 34 (4~64) winsize 61
723 12:29:32.102148 [CA 4] Center 33 (2~64) winsize 63
724 12:29:32.105432 [CA 5] Center 32 (2~62) winsize 61
725 12:29:32.105870
726 12:29:32.109225 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:29:32.109667
728 12:29:32.112396 [CATrainingPosCal] consider 1 rank data
729 12:29:32.115825 u2DelayCellTimex100 = 270/100 ps
730 12:29:32.118992 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 12:29:32.122316 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 12:29:32.125966 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 12:29:32.132265 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 12:29:32.135807 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 12:29:32.138901 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 12:29:32.139508
737 12:29:32.142073 CA PerBit enable=1, Macro0, CA PI delay=32
738 12:29:32.142650
739 12:29:32.145538 [CBTSetCACLKResult] CA Dly = 32
740 12:29:32.146059 CS Dly: 5 (0~36)
741 12:29:32.146583 ==
742 12:29:32.148728 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:29:32.155437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:29:32.156013 ==
745 12:29:32.159011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:29:32.165567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:29:32.175132 [CA 0] Center 36 (6~67) winsize 62
748 12:29:32.178414 [CA 1] Center 36 (6~67) winsize 62
749 12:29:32.181827 [CA 2] Center 34 (4~65) winsize 62
750 12:29:32.185259 [CA 3] Center 33 (3~64) winsize 62
751 12:29:32.188570 [CA 4] Center 32 (2~63) winsize 62
752 12:29:32.191820 [CA 5] Center 32 (2~63) winsize 62
753 12:29:32.192330
754 12:29:32.195188 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 12:29:32.195981
756 12:29:32.198470 [CATrainingPosCal] consider 2 rank data
757 12:29:32.201746 u2DelayCellTimex100 = 270/100 ps
758 12:29:32.205572 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 12:29:32.208653 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 12:29:32.211652 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 12:29:32.218660 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 12:29:32.221984 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 12:29:32.225274 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 12:29:32.225542
765 12:29:32.228613 CA PerBit enable=1, Macro0, CA PI delay=32
766 12:29:32.228845
767 12:29:32.231906 [CBTSetCACLKResult] CA Dly = 32
768 12:29:32.232086 CS Dly: 5 (0~37)
769 12:29:32.232287
770 12:29:32.235072 ----->DramcWriteLeveling(PI) begin...
771 12:29:32.235241 ==
772 12:29:32.238778 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:29:32.242508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:29:32.246227 ==
775 12:29:32.246361 Write leveling (Byte 0): 33 => 33
776 12:29:32.249974 Write leveling (Byte 1): 29 => 29
777 12:29:32.253279 DramcWriteLeveling(PI) end<-----
778 12:29:32.253425
779 12:29:32.253545 ==
780 12:29:32.257075 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:29:32.260197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:29:32.260303 ==
783 12:29:32.263340 [Gating] SW mode calibration
784 12:29:32.270913 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:29:32.277736 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:29:32.281108 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:29:32.284391 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 12:29:32.291187 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 12:29:32.293854 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:29:32.297234 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:29:32.304474 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:29:32.307705 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:29:32.311028 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:29:32.314327 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:29:32.320681 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:29:32.324419 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:29:32.327763 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:29:32.334402 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:29:32.337733 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:29:32.341027 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:29:32.348057 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:29:32.351027 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:29:32.354175 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:29:32.361164 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 12:29:32.364335 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:29:32.368029 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:29:32.374171 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:29:32.378095 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:29:32.381545 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:29:32.384238 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:29:32.391651 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:29:32.394890 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
813 12:29:32.397612 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
814 12:29:32.404428 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:29:32.407934 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:29:32.411219 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:29:32.417816 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:29:32.421231 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:29:32.424523 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:29:32.431197 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
821 12:29:32.434658 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:29:32.437887 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:29:32.444794 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:29:32.448094 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:29:32.451151 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:29:32.458234 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:29:32.461476 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 12:29:32.464644 0 11 8 | B1->B0 | 2c2c 4040 | 1 1 | (0 0) (0 0)
829 12:29:32.468352 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
830 12:29:32.474617 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:29:32.477873 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:29:32.481453 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:29:32.488283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:29:32.491056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:29:32.494415 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:29:32.501224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 12:29:32.504440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:29:32.508431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:29:32.514536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:29:32.517881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:29:32.521961 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:29:32.528099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:29:32.531879 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:29:32.535080 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:29:32.541706 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:29:32.544870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:29:32.548415 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:29:32.551681 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:29:32.558351 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:29:32.562322 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:29:32.565565 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:29:32.572078 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:29:32.575193 Total UI for P1: 0, mck2ui 16
854 12:29:32.578678 best dqsien dly found for B0: ( 0, 14, 4)
855 12:29:32.582181 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:29:32.585243 Total UI for P1: 0, mck2ui 16
857 12:29:32.588940 best dqsien dly found for B1: ( 0, 14, 8)
858 12:29:32.592794 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 12:29:32.596170 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:29:32.596747
861 12:29:32.599698 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 12:29:32.603011 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:29:32.606321 [Gating] SW calibration Done
864 12:29:32.606766 ==
865 12:29:32.609899 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:29:32.612534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:29:32.613225 ==
868 12:29:32.616598 RX Vref Scan: 0
869 12:29:32.617214
870 12:29:32.617761 RX Vref 0 -> 0, step: 1
871 12:29:32.618328
872 12:29:32.619867 RX Delay -130 -> 252, step: 16
873 12:29:32.623031 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 12:29:32.629733 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 12:29:32.633074 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 12:29:32.636353 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 12:29:32.639869 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 12:29:32.642569 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 12:29:32.649747 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 12:29:32.652725 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 12:29:32.656407 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 12:29:32.659632 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 12:29:32.662768 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 12:29:32.669874 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 12:29:32.673091 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 12:29:32.676395 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 12:29:32.679538 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 12:29:32.683290 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 12:29:32.683653 ==
890 12:29:32.686643 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:29:32.692869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:29:32.693201 ==
893 12:29:32.693527 DQS Delay:
894 12:29:32.696106 DQS0 = 0, DQS1 = 0
895 12:29:32.696554 DQM Delay:
896 12:29:32.697083 DQM0 = 92, DQM1 = 86
897 12:29:32.699971 DQ Delay:
898 12:29:32.703283 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 12:29:32.706686 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 12:29:32.709980 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 12:29:32.713342 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 12:29:32.713658
903 12:29:32.713923
904 12:29:32.714155 ==
905 12:29:32.716710 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:29:32.719902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:29:32.720220 ==
908 12:29:32.720491
909 12:29:32.720741
910 12:29:32.723204 TX Vref Scan disable
911 12:29:32.723642 == TX Byte 0 ==
912 12:29:32.729814 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 12:29:32.733242 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 12:29:32.733580 == TX Byte 1 ==
915 12:29:32.739857 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 12:29:32.743195 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 12:29:32.743599 ==
918 12:29:32.746567 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:29:32.749869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:29:32.750275 ==
921 12:29:32.764138 TX Vref=22, minBit 10, minWin=27, winSum=449
922 12:29:32.767911 TX Vref=24, minBit 7, minWin=27, winSum=449
923 12:29:32.771017 TX Vref=26, minBit 3, minWin=28, winSum=453
924 12:29:32.774679 TX Vref=28, minBit 0, minWin=28, winSum=458
925 12:29:32.777749 TX Vref=30, minBit 5, minWin=28, winSum=456
926 12:29:32.781389 TX Vref=32, minBit 5, minWin=28, winSum=455
927 12:29:32.788087 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
928 12:29:32.788467
929 12:29:32.791137 Final TX Range 1 Vref 28
930 12:29:32.791544
931 12:29:32.791929 ==
932 12:29:32.794688 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:29:32.797744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:29:32.798148 ==
935 12:29:32.798527
936 12:29:32.798898
937 12:29:32.801198 TX Vref Scan disable
938 12:29:32.804917 == TX Byte 0 ==
939 12:29:32.809816 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 12:29:32.811388 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 12:29:32.814781 == TX Byte 1 ==
942 12:29:32.818065 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 12:29:32.821512 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 12:29:32.821902
945 12:29:32.824674 [DATLAT]
946 12:29:32.825057 Freq=800, CH0 RK0
947 12:29:32.825418
948 12:29:32.828052 DATLAT Default: 0xa
949 12:29:32.828437 0, 0xFFFF, sum = 0
950 12:29:32.831434 1, 0xFFFF, sum = 0
951 12:29:32.831765 2, 0xFFFF, sum = 0
952 12:29:32.834859 3, 0xFFFF, sum = 0
953 12:29:32.835141 4, 0xFFFF, sum = 0
954 12:29:32.838331 5, 0xFFFF, sum = 0
955 12:29:32.838652 6, 0xFFFF, sum = 0
956 12:29:32.841614 7, 0xFFFF, sum = 0
957 12:29:32.841930 8, 0xFFFF, sum = 0
958 12:29:32.844987 9, 0x0, sum = 1
959 12:29:32.845306 10, 0x0, sum = 2
960 12:29:32.848092 11, 0x0, sum = 3
961 12:29:32.848181 12, 0x0, sum = 4
962 12:29:32.851448 best_step = 10
963 12:29:32.851560
964 12:29:32.851658 ==
965 12:29:32.854823 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:29:32.858425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:29:32.858576 ==
968 12:29:32.861545 RX Vref Scan: 1
969 12:29:32.861676
970 12:29:32.861753 Set Vref Range= 32 -> 127
971 12:29:32.861820
972 12:29:32.864998 RX Vref 32 -> 127, step: 1
973 12:29:32.865155
974 12:29:32.868282 RX Delay -79 -> 252, step: 8
975 12:29:32.868372
976 12:29:32.871388 Set Vref, RX VrefLevel [Byte0]: 32
977 12:29:32.874717 [Byte1]: 32
978 12:29:32.874808
979 12:29:32.877790 Set Vref, RX VrefLevel [Byte0]: 33
980 12:29:32.881018 [Byte1]: 33
981 12:29:32.881112
982 12:29:32.884710 Set Vref, RX VrefLevel [Byte0]: 34
983 12:29:32.887839 [Byte1]: 34
984 12:29:32.891907
985 12:29:32.892004 Set Vref, RX VrefLevel [Byte0]: 35
986 12:29:32.895006 [Byte1]: 35
987 12:29:32.899532
988 12:29:32.899679 Set Vref, RX VrefLevel [Byte0]: 36
989 12:29:32.902661 [Byte1]: 36
990 12:29:32.907358
991 12:29:32.907504 Set Vref, RX VrefLevel [Byte0]: 37
992 12:29:32.910566 [Byte1]: 37
993 12:29:32.915342
994 12:29:32.915473 Set Vref, RX VrefLevel [Byte0]: 38
995 12:29:32.918141 [Byte1]: 38
996 12:29:32.922194
997 12:29:32.922456 Set Vref, RX VrefLevel [Byte0]: 39
998 12:29:32.925504 [Byte1]: 39
999 12:29:32.930382
1000 12:29:32.930593 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:29:32.933663 [Byte1]: 40
1002 12:29:32.937736
1003 12:29:32.937955 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:29:32.941172 [Byte1]: 41
1005 12:29:32.945222
1006 12:29:32.945637 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:29:32.948554 [Byte1]: 42
1008 12:29:32.952611
1009 12:29:32.953083 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:29:32.955942 [Byte1]: 43
1011 12:29:32.960490
1012 12:29:32.960928 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:29:32.963178 [Byte1]: 44
1014 12:29:32.967753
1015 12:29:32.968279 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:29:32.971061 [Byte1]: 45
1017 12:29:32.975618
1018 12:29:32.976332 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:29:32.978548 [Byte1]: 46
1020 12:29:32.982692
1021 12:29:32.983421 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:29:32.985791 [Byte1]: 47
1023 12:29:32.990224
1024 12:29:32.990795 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:29:32.993298 [Byte1]: 48
1026 12:29:32.998162
1027 12:29:32.998852 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:29:33.001340 [Byte1]: 49
1029 12:29:33.005128
1030 12:29:33.005778 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:29:33.008668 [Byte1]: 50
1032 12:29:33.012647
1033 12:29:33.013106 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:29:33.016145 [Byte1]: 51
1035 12:29:33.020391
1036 12:29:33.020785 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:29:33.023760 [Byte1]: 52
1038 12:29:33.027622
1039 12:29:33.027782 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:29:33.031030 [Byte1]: 53
1041 12:29:33.035102
1042 12:29:33.035262 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:29:33.038539 [Byte1]: 54
1044 12:29:33.043161
1045 12:29:33.043299 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:29:33.045922 [Byte1]: 55
1047 12:29:33.050475
1048 12:29:33.050602 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:29:33.053756 [Byte1]: 56
1050 12:29:33.057752
1051 12:29:33.057919 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:29:33.061040 [Byte1]: 57
1053 12:29:33.065790
1054 12:29:33.065927 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:29:33.072149 [Byte1]: 58
1056 12:29:33.072315
1057 12:29:33.075613 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:29:33.078780 [Byte1]: 59
1059 12:29:33.078881
1060 12:29:33.082023 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:29:33.085033 [Byte1]: 60
1062 12:29:33.085172
1063 12:29:33.088291 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:29:33.092270 [Byte1]: 61
1065 12:29:33.095921
1066 12:29:33.096007 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:29:33.099046 [Byte1]: 62
1068 12:29:33.103546
1069 12:29:33.103649 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:29:33.106774 [Byte1]: 63
1071 12:29:33.111112
1072 12:29:33.111244 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:29:33.114389 [Byte1]: 64
1074 12:29:33.118117
1075 12:29:33.118270 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:29:33.121883 [Byte1]: 65
1077 12:29:33.125675
1078 12:29:33.125764 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:29:33.129164 [Byte1]: 66
1080 12:29:33.133784
1081 12:29:33.133918 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:29:33.136531 [Byte1]: 67
1083 12:29:33.141130
1084 12:29:33.141235 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:29:33.144485 [Byte1]: 68
1086 12:29:33.148350
1087 12:29:33.148469 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:29:33.151766 [Byte1]: 69
1089 12:29:33.156469
1090 12:29:33.156683 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:29:33.159774 [Byte1]: 70
1092 12:29:33.163733
1093 12:29:33.163998 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:29:33.167056 [Byte1]: 71
1095 12:29:33.171720
1096 12:29:33.172065 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:29:33.174378 [Byte1]: 72
1098 12:29:33.179007
1099 12:29:33.179388 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:29:33.182540 [Byte1]: 73
1101 12:29:33.186397
1102 12:29:33.186699 Set Vref, RX VrefLevel [Byte0]: 74
1103 12:29:33.189581 [Byte1]: 74
1104 12:29:33.193975
1105 12:29:33.194334 Set Vref, RX VrefLevel [Byte0]: 75
1106 12:29:33.197204 [Byte1]: 75
1107 12:29:33.201741
1108 12:29:33.202023 Set Vref, RX VrefLevel [Byte0]: 76
1109 12:29:33.204980 [Byte1]: 76
1110 12:29:33.209259
1111 12:29:33.209446 Set Vref, RX VrefLevel [Byte0]: 77
1112 12:29:33.212293 [Byte1]: 77
1113 12:29:33.216315
1114 12:29:33.216591 Set Vref, RX VrefLevel [Byte0]: 78
1115 12:29:33.220021 [Byte1]: 78
1116 12:29:33.223916
1117 12:29:33.224132 Final RX Vref Byte 0 = 56 to rank0
1118 12:29:33.227806 Final RX Vref Byte 1 = 57 to rank0
1119 12:29:33.231098 Final RX Vref Byte 0 = 56 to rank1
1120 12:29:33.234209 Final RX Vref Byte 1 = 57 to rank1==
1121 12:29:33.237529 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 12:29:33.240958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 12:29:33.244371 ==
1124 12:29:33.244984 DQS Delay:
1125 12:29:33.245547 DQS0 = 0, DQS1 = 0
1126 12:29:33.247664 DQM Delay:
1127 12:29:33.248316 DQM0 = 92, DQM1 = 84
1128 12:29:33.250821 DQ Delay:
1129 12:29:33.254214 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1130 12:29:33.254769 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1131 12:29:33.257777 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1132 12:29:33.261143 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1133 12:29:33.264226
1134 12:29:33.264778
1135 12:29:33.271008 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1136 12:29:33.274348 CH0 RK0: MR19=606, MR18=4E45
1137 12:29:33.280961 CH0_RK0: MR19=0x606, MR18=0x4E45, DQSOSC=390, MR23=63, INC=97, DEC=64
1138 12:29:33.281545
1139 12:29:33.284656 ----->DramcWriteLeveling(PI) begin...
1140 12:29:33.285296 ==
1141 12:29:33.288149 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 12:29:33.291395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 12:29:33.291993 ==
1144 12:29:33.294764 Write leveling (Byte 0): 33 => 33
1145 12:29:33.297913 Write leveling (Byte 1): 31 => 31
1146 12:29:33.300929 DramcWriteLeveling(PI) end<-----
1147 12:29:33.301521
1148 12:29:33.302035 ==
1149 12:29:33.304723 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 12:29:33.307793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 12:29:33.308403 ==
1152 12:29:33.311588 [Gating] SW mode calibration
1153 12:29:33.356201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 12:29:33.357015 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 12:29:33.357589 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 12:29:33.358472 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 12:29:33.358947 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 12:29:33.359463 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:29:33.359937 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:29:33.360471 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:29:33.360721 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:29:33.370785 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:29:33.371538 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:29:33.371644 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:29:33.374929 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:29:33.377608 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:29:33.381069 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:29:33.384208 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:29:33.388199 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:29:33.394850 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:29:33.398113 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:29:33.401597 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:29:33.407972 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 12:29:33.411439 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:29:33.414661 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:29:33.421655 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:29:33.424816 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:29:33.427849 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:29:33.434870 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:29:33.438118 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:29:33.441182 0 9 8 | B1->B0 | 2e2e 2b2b | 1 0 | (1 1) (0 0)
1182 12:29:33.444891 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:29:33.451474 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:29:33.454650 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:29:33.457991 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:29:33.464889 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:29:33.468052 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:29:33.471352 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 12:29:33.478030 0 10 8 | B1->B0 | 2a2a 2a2a | 0 0 | (1 0) (0 1)
1190 12:29:33.481310 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:29:33.485258 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:29:33.489283 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:29:33.496663 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:29:33.500064 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:29:33.503295 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:29:33.506603 0 11 4 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
1197 12:29:33.514000 0 11 8 | B1->B0 | 4040 3838 | 0 0 | (0 0) (0 0)
1198 12:29:33.517299 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:29:33.520484 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:29:33.526931 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:29:33.530655 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:29:33.533759 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:29:33.537698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:29:33.544141 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 12:29:33.547255 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 12:29:33.550951 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:29:33.557392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:29:33.560722 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:29:33.564236 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:29:33.570941 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:29:33.574224 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:29:33.577421 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:29:33.583965 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:29:33.587304 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:29:33.590492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:29:33.597054 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:29:33.600375 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:29:33.603798 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:29:33.610524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:29:33.613907 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:29:33.617286 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 12:29:33.620530 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 12:29:33.623639 Total UI for P1: 0, mck2ui 16
1224 12:29:33.626884 best dqsien dly found for B0: ( 0, 14, 8)
1225 12:29:33.630037 Total UI for P1: 0, mck2ui 16
1226 12:29:33.633263 best dqsien dly found for B1: ( 0, 14, 8)
1227 12:29:33.637135 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 12:29:33.643314 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 12:29:33.643441
1230 12:29:33.647174 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 12:29:33.650397 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 12:29:33.653615 [Gating] SW calibration Done
1233 12:29:33.653697 ==
1234 12:29:33.656554 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 12:29:33.660382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 12:29:33.660507 ==
1237 12:29:33.660593 RX Vref Scan: 0
1238 12:29:33.660672
1239 12:29:33.663761 RX Vref 0 -> 0, step: 1
1240 12:29:33.663855
1241 12:29:33.667065 RX Delay -130 -> 252, step: 16
1242 12:29:33.670455 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 12:29:33.673806 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 12:29:33.680458 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 12:29:33.683727 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 12:29:33.687056 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 12:29:33.690462 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 12:29:33.693864 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 12:29:33.700370 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 12:29:33.703734 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 12:29:33.707198 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1252 12:29:33.710520 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 12:29:33.713764 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 12:29:33.717133 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1255 12:29:33.723781 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 12:29:33.727112 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 12:29:33.731021 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1258 12:29:33.731106 ==
1259 12:29:33.734218 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 12:29:33.737291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 12:29:33.737377 ==
1262 12:29:33.740413 DQS Delay:
1263 12:29:33.740497 DQS0 = 0, DQS1 = 0
1264 12:29:33.744299 DQM Delay:
1265 12:29:33.744383 DQM0 = 91, DQM1 = 83
1266 12:29:33.744449 DQ Delay:
1267 12:29:33.747336 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1268 12:29:33.750658 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 12:29:33.753804 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1270 12:29:33.757667 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1271 12:29:33.757751
1272 12:29:33.757816
1273 12:29:33.760775 ==
1274 12:29:33.764483 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:29:33.767913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 12:29:33.767997 ==
1277 12:29:33.768064
1278 12:29:33.768125
1279 12:29:33.771178 TX Vref Scan disable
1280 12:29:33.771262 == TX Byte 0 ==
1281 12:29:33.774370 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 12:29:33.781073 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 12:29:33.781158 == TX Byte 1 ==
1284 12:29:33.784434 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1285 12:29:33.791166 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1286 12:29:33.791250 ==
1287 12:29:33.794498 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:29:33.797198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 12:29:33.797281 ==
1290 12:29:33.811049 TX Vref=22, minBit 12, minWin=27, winSum=450
1291 12:29:33.814370 TX Vref=24, minBit 8, minWin=27, winSum=453
1292 12:29:33.817592 TX Vref=26, minBit 2, minWin=28, winSum=456
1293 12:29:33.820873 TX Vref=28, minBit 2, minWin=28, winSum=457
1294 12:29:33.824156 TX Vref=30, minBit 2, minWin=28, winSum=455
1295 12:29:33.827519 TX Vref=32, minBit 2, minWin=28, winSum=456
1296 12:29:33.834051 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
1297 12:29:33.834133
1298 12:29:33.837788 Final TX Range 1 Vref 28
1299 12:29:33.837863
1300 12:29:33.837924 ==
1301 12:29:33.841150 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:29:33.844243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:29:33.844328 ==
1304 12:29:33.844391
1305 12:29:33.847304
1306 12:29:33.847421 TX Vref Scan disable
1307 12:29:33.850959 == TX Byte 0 ==
1308 12:29:33.854052 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1309 12:29:33.857220 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1310 12:29:33.860988 == TX Byte 1 ==
1311 12:29:33.864075 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 12:29:33.867899 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 12:29:33.870842
1314 12:29:33.870911 [DATLAT]
1315 12:29:33.870970 Freq=800, CH0 RK1
1316 12:29:33.871035
1317 12:29:33.874173 DATLAT Default: 0xa
1318 12:29:33.874243 0, 0xFFFF, sum = 0
1319 12:29:33.877338 1, 0xFFFF, sum = 0
1320 12:29:33.877408 2, 0xFFFF, sum = 0
1321 12:29:33.880542 3, 0xFFFF, sum = 0
1322 12:29:33.880612 4, 0xFFFF, sum = 0
1323 12:29:33.884516 5, 0xFFFF, sum = 0
1324 12:29:33.884592 6, 0xFFFF, sum = 0
1325 12:29:33.887840 7, 0xFFFF, sum = 0
1326 12:29:33.887911 8, 0xFFFF, sum = 0
1327 12:29:33.891124 9, 0x0, sum = 1
1328 12:29:33.891203 10, 0x0, sum = 2
1329 12:29:33.894258 11, 0x0, sum = 3
1330 12:29:33.894331 12, 0x0, sum = 4
1331 12:29:33.897715 best_step = 10
1332 12:29:33.897785
1333 12:29:33.897854 ==
1334 12:29:33.901050 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 12:29:33.904497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 12:29:33.904568 ==
1337 12:29:33.907686 RX Vref Scan: 0
1338 12:29:33.907753
1339 12:29:33.907811 RX Vref 0 -> 0, step: 1
1340 12:29:33.907866
1341 12:29:33.910879 RX Delay -79 -> 252, step: 8
1342 12:29:33.917597 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 12:29:33.921036 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 12:29:33.924300 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 12:29:33.927543 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 12:29:33.930818 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 12:29:33.937686 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1348 12:29:33.941039 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 12:29:33.944239 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 12:29:33.947442 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1351 12:29:33.951191 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1352 12:29:33.957336 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 12:29:33.961127 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 12:29:33.964202 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1355 12:29:33.968087 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1356 12:29:33.971169 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 12:29:33.977902 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 12:29:33.977976 ==
1359 12:29:33.980993 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 12:29:33.984238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 12:29:33.984309 ==
1362 12:29:33.984376 DQS Delay:
1363 12:29:33.987522 DQS0 = 0, DQS1 = 0
1364 12:29:33.987600 DQM Delay:
1365 12:29:33.990863 DQM0 = 92, DQM1 = 84
1366 12:29:33.990963 DQ Delay:
1367 12:29:33.994219 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1368 12:29:33.997548 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1369 12:29:34.001334 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1370 12:29:34.004720 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1371 12:29:34.004819
1372 12:29:34.004921
1373 12:29:34.011422 [DQSOSCAuto] RK1, (LSB)MR18= 0x4414, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1374 12:29:34.014759 CH0 RK1: MR19=606, MR18=4414
1375 12:29:34.020800 CH0_RK1: MR19=0x606, MR18=0x4414, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 12:29:34.024287 [RxdqsGatingPostProcess] freq 800
1377 12:29:34.028168 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 12:29:34.031578 Pre-setting of DQS Precalculation
1379 12:29:34.038269 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 12:29:34.038351 ==
1381 12:29:34.041565 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 12:29:34.044838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 12:29:34.044906 ==
1384 12:29:34.051246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 12:29:34.057703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 12:29:34.065848 [CA 0] Center 36 (6~67) winsize 62
1387 12:29:34.068999 [CA 1] Center 36 (6~67) winsize 62
1388 12:29:34.072187 [CA 2] Center 34 (4~65) winsize 62
1389 12:29:34.076008 [CA 3] Center 34 (4~65) winsize 62
1390 12:29:34.079129 [CA 4] Center 34 (4~65) winsize 62
1391 12:29:34.082397 [CA 5] Center 33 (3~64) winsize 62
1392 12:29:34.082493
1393 12:29:34.086073 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 12:29:34.086144
1395 12:29:34.089020 [CATrainingPosCal] consider 1 rank data
1396 12:29:34.092282 u2DelayCellTimex100 = 270/100 ps
1397 12:29:34.096155 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1398 12:29:34.099335 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1399 12:29:34.102701 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 12:29:34.109523 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1401 12:29:34.112934 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 12:29:34.115534 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 12:29:34.115640
1404 12:29:34.118858 CA PerBit enable=1, Macro0, CA PI delay=33
1405 12:29:34.118959
1406 12:29:34.122277 [CBTSetCACLKResult] CA Dly = 33
1407 12:29:34.122400 CS Dly: 6 (0~37)
1408 12:29:34.122470 ==
1409 12:29:34.125686 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 12:29:34.132224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 12:29:34.132306 ==
1412 12:29:34.135553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 12:29:34.142402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 12:29:34.152344 [CA 0] Center 36 (6~67) winsize 62
1415 12:29:34.156349 [CA 1] Center 36 (6~67) winsize 62
1416 12:29:34.159463 [CA 2] Center 35 (4~66) winsize 63
1417 12:29:34.163808 [CA 3] Center 34 (4~65) winsize 62
1418 12:29:34.167732 [CA 4] Center 34 (4~65) winsize 62
1419 12:29:34.167904 [CA 5] Center 34 (4~65) winsize 62
1420 12:29:34.167982
1421 12:29:34.174713 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 12:29:34.174832
1423 12:29:34.178431 [CATrainingPosCal] consider 2 rank data
1424 12:29:34.178559 u2DelayCellTimex100 = 270/100 ps
1425 12:29:34.182402 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 12:29:34.185631 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 12:29:34.189269 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 12:29:34.195921 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 12:29:34.199053 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 12:29:34.202277 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 12:29:34.202813
1432 12:29:34.205541 CA PerBit enable=1, Macro0, CA PI delay=34
1433 12:29:34.205973
1434 12:29:34.209560 [CBTSetCACLKResult] CA Dly = 34
1435 12:29:34.210091 CS Dly: 6 (0~38)
1436 12:29:34.210437
1437 12:29:34.212515 ----->DramcWriteLeveling(PI) begin...
1438 12:29:34.212942 ==
1439 12:29:34.215964 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 12:29:34.222574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 12:29:34.223004 ==
1442 12:29:34.225859 Write leveling (Byte 0): 28 => 28
1443 12:29:34.229269 Write leveling (Byte 1): 28 => 28
1444 12:29:34.229695 DramcWriteLeveling(PI) end<-----
1445 12:29:34.230036
1446 12:29:34.233077 ==
1447 12:29:34.236049 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 12:29:34.239404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 12:29:34.239904 ==
1450 12:29:34.242835 [Gating] SW mode calibration
1451 12:29:34.249438 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 12:29:34.252048 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 12:29:34.258873 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 12:29:34.261967 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1455 12:29:34.265862 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:29:34.272271 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:29:34.275659 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:29:34.279415 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:29:34.286138 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:29:34.289197 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:29:34.292284 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:29:34.299137 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:29:34.302408 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:29:34.305839 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:29:34.308960 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:29:34.316062 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:29:34.319143 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:29:34.322139 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1469 12:29:34.329409 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 12:29:34.332789 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:29:34.335959 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:29:34.342660 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:29:34.346114 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:29:34.349284 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:29:34.356240 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:29:34.359608 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:29:34.362861 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:29:34.369640 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1479 12:29:34.372612 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1480 12:29:34.375833 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:29:34.379303 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:29:34.386053 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:29:34.389624 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:29:34.392887 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:29:34.399921 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:29:34.402620 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (0 1) (0 1)
1487 12:29:34.406552 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1488 12:29:34.412651 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:29:34.415923 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:29:34.419520 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:29:34.426527 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:29:34.429677 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:29:34.432796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:29:34.439203 0 11 4 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
1495 12:29:34.443233 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1496 12:29:34.446595 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:29:34.452796 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:29:34.456130 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:29:34.459570 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:29:34.462962 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:29:34.469834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:29:34.473084 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:29:34.476264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 12:29:34.483402 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:29:34.486721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:29:34.489928 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:29:34.496449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:29:34.499630 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:29:34.503294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:29:34.509520 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:29:34.513447 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:29:34.516651 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:29:34.523153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:29:34.526238 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:29:34.529862 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:29:34.536423 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:29:34.539480 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:29:34.543289 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1519 12:29:34.546548 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 12:29:34.549712 Total UI for P1: 0, mck2ui 16
1521 12:29:34.553216 best dqsien dly found for B0: ( 0, 14, 6)
1522 12:29:34.556627 Total UI for P1: 0, mck2ui 16
1523 12:29:34.559970 best dqsien dly found for B1: ( 0, 14, 4)
1524 12:29:34.563384 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 12:29:34.566689 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 12:29:34.569927
1527 12:29:34.573259 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 12:29:34.576608 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 12:29:34.577052 [Gating] SW calibration Done
1530 12:29:34.579899 ==
1531 12:29:34.583078 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 12:29:34.586283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 12:29:34.586807 ==
1534 12:29:34.587281 RX Vref Scan: 0
1535 12:29:34.587696
1536 12:29:34.589611 RX Vref 0 -> 0, step: 1
1537 12:29:34.590264
1538 12:29:34.593568 RX Delay -130 -> 252, step: 16
1539 12:29:34.596274 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 12:29:34.599528 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 12:29:34.606678 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 12:29:34.609831 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 12:29:34.612909 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 12:29:34.616265 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 12:29:34.620020 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1546 12:29:34.623098 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 12:29:34.629814 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 12:29:34.632978 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 12:29:34.636671 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 12:29:34.639962 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 12:29:34.643153 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 12:29:34.649772 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1553 12:29:34.652918 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 12:29:34.656861 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1555 12:29:34.657293 ==
1556 12:29:34.659523 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 12:29:34.662778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 12:29:34.666174 ==
1559 12:29:34.666606 DQS Delay:
1560 12:29:34.667006 DQS0 = 0, DQS1 = 0
1561 12:29:34.669626 DQM Delay:
1562 12:29:34.670058 DQM0 = 93, DQM1 = 89
1563 12:29:34.672962 DQ Delay:
1564 12:29:34.673394 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1565 12:29:34.676274 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1566 12:29:34.679623 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1567 12:29:34.686264 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1568 12:29:34.686715
1569 12:29:34.687061
1570 12:29:34.687451 ==
1571 12:29:34.689612 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 12:29:34.692882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 12:29:34.693318 ==
1574 12:29:34.693663
1575 12:29:34.693982
1576 12:29:34.696808 TX Vref Scan disable
1577 12:29:34.697239 == TX Byte 0 ==
1578 12:29:34.703457 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 12:29:34.706877 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 12:29:34.707308 == TX Byte 1 ==
1581 12:29:34.713547 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1582 12:29:34.716793 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1583 12:29:34.717228 ==
1584 12:29:34.719816 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:29:34.723085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:29:34.723656 ==
1587 12:29:34.736740 TX Vref=22, minBit 3, minWin=26, winSum=433
1588 12:29:34.739901 TX Vref=24, minBit 3, minWin=26, winSum=441
1589 12:29:34.743498 TX Vref=26, minBit 3, minWin=27, winSum=449
1590 12:29:34.746539 TX Vref=28, minBit 3, minWin=27, winSum=449
1591 12:29:34.750208 TX Vref=30, minBit 2, minWin=27, winSum=453
1592 12:29:34.753485 TX Vref=32, minBit 0, minWin=27, winSum=447
1593 12:29:34.759601 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
1594 12:29:34.759707
1595 12:29:34.762720 Final TX Range 1 Vref 30
1596 12:29:34.762804
1597 12:29:34.762871 ==
1598 12:29:34.766186 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 12:29:34.769712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 12:29:34.769802 ==
1601 12:29:34.769872
1602 12:29:34.772976
1603 12:29:34.773066 TX Vref Scan disable
1604 12:29:34.776241 == TX Byte 0 ==
1605 12:29:34.779631 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 12:29:34.782906 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 12:29:34.786239 == TX Byte 1 ==
1608 12:29:34.789393 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1609 12:29:34.793269 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1610 12:29:34.796591
1611 12:29:34.796674 [DATLAT]
1612 12:29:34.796741 Freq=800, CH1 RK0
1613 12:29:34.796803
1614 12:29:34.799903 DATLAT Default: 0xa
1615 12:29:34.799986 0, 0xFFFF, sum = 0
1616 12:29:34.802952 1, 0xFFFF, sum = 0
1617 12:29:34.803038 2, 0xFFFF, sum = 0
1618 12:29:34.806522 3, 0xFFFF, sum = 0
1619 12:29:34.806608 4, 0xFFFF, sum = 0
1620 12:29:34.809843 5, 0xFFFF, sum = 0
1621 12:29:34.809928 6, 0xFFFF, sum = 0
1622 12:29:34.813193 7, 0xFFFF, sum = 0
1623 12:29:34.813279 8, 0xFFFF, sum = 0
1624 12:29:34.816639 9, 0x0, sum = 1
1625 12:29:34.816727 10, 0x0, sum = 2
1626 12:29:34.819924 11, 0x0, sum = 3
1627 12:29:34.820009 12, 0x0, sum = 4
1628 12:29:34.823235 best_step = 10
1629 12:29:34.823368
1630 12:29:34.823437 ==
1631 12:29:34.826449 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 12:29:34.830047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 12:29:34.830153 ==
1634 12:29:34.833128 RX Vref Scan: 1
1635 12:29:34.833201
1636 12:29:34.833283 Set Vref Range= 32 -> 127
1637 12:29:34.833371
1638 12:29:34.836821 RX Vref 32 -> 127, step: 1
1639 12:29:34.836894
1640 12:29:34.840063 RX Delay -79 -> 252, step: 8
1641 12:29:34.840136
1642 12:29:34.843207 Set Vref, RX VrefLevel [Byte0]: 32
1643 12:29:34.846863 [Byte1]: 32
1644 12:29:34.846968
1645 12:29:34.849843 Set Vref, RX VrefLevel [Byte0]: 33
1646 12:29:34.853518 [Byte1]: 33
1647 12:29:34.853620
1648 12:29:34.856818 Set Vref, RX VrefLevel [Byte0]: 34
1649 12:29:34.860196 [Byte1]: 34
1650 12:29:34.864176
1651 12:29:34.864278 Set Vref, RX VrefLevel [Byte0]: 35
1652 12:29:34.867223 [Byte1]: 35
1653 12:29:34.871737
1654 12:29:34.871810 Set Vref, RX VrefLevel [Byte0]: 36
1655 12:29:34.874901 [Byte1]: 36
1656 12:29:34.878819
1657 12:29:34.878917 Set Vref, RX VrefLevel [Byte0]: 37
1658 12:29:34.882665 [Byte1]: 37
1659 12:29:34.886626
1660 12:29:34.886724 Set Vref, RX VrefLevel [Byte0]: 38
1661 12:29:34.889991 [Byte1]: 38
1662 12:29:34.894051
1663 12:29:34.894151 Set Vref, RX VrefLevel [Byte0]: 39
1664 12:29:34.897272 [Byte1]: 39
1665 12:29:34.901356
1666 12:29:34.901427 Set Vref, RX VrefLevel [Byte0]: 40
1667 12:29:34.905257 [Byte1]: 40
1668 12:29:34.909067
1669 12:29:34.909171 Set Vref, RX VrefLevel [Byte0]: 41
1670 12:29:34.912401 [Byte1]: 41
1671 12:29:34.917214
1672 12:29:34.917312 Set Vref, RX VrefLevel [Byte0]: 42
1673 12:29:34.919751 [Byte1]: 42
1674 12:29:34.924361
1675 12:29:34.924466 Set Vref, RX VrefLevel [Byte0]: 43
1676 12:29:34.927780 [Byte1]: 43
1677 12:29:34.931793
1678 12:29:34.931877 Set Vref, RX VrefLevel [Byte0]: 44
1679 12:29:34.935036 [Byte1]: 44
1680 12:29:34.939416
1681 12:29:34.939501 Set Vref, RX VrefLevel [Byte0]: 45
1682 12:29:34.943022 [Byte1]: 45
1683 12:29:34.947047
1684 12:29:34.947131 Set Vref, RX VrefLevel [Byte0]: 46
1685 12:29:34.950111 [Byte1]: 46
1686 12:29:34.954488
1687 12:29:34.954585 Set Vref, RX VrefLevel [Byte0]: 47
1688 12:29:34.957614 [Byte1]: 47
1689 12:29:34.962108
1690 12:29:34.962188 Set Vref, RX VrefLevel [Byte0]: 48
1691 12:29:34.965188 [Byte1]: 48
1692 12:29:34.969558
1693 12:29:34.969638 Set Vref, RX VrefLevel [Byte0]: 49
1694 12:29:34.972904 [Byte1]: 49
1695 12:29:34.977422
1696 12:29:34.977506 Set Vref, RX VrefLevel [Byte0]: 50
1697 12:29:34.980619 [Byte1]: 50
1698 12:29:34.984555
1699 12:29:34.984637 Set Vref, RX VrefLevel [Byte0]: 51
1700 12:29:34.988418 [Byte1]: 51
1701 12:29:34.992490
1702 12:29:34.992572 Set Vref, RX VrefLevel [Byte0]: 52
1703 12:29:34.995777 [Byte1]: 52
1704 12:29:34.999793
1705 12:29:34.999875 Set Vref, RX VrefLevel [Byte0]: 53
1706 12:29:35.003071 [Byte1]: 53
1707 12:29:35.007677
1708 12:29:35.007759 Set Vref, RX VrefLevel [Byte0]: 54
1709 12:29:35.011002 [Byte1]: 54
1710 12:29:35.014893
1711 12:29:35.014985 Set Vref, RX VrefLevel [Byte0]: 55
1712 12:29:35.018187 [Byte1]: 55
1713 12:29:35.022190
1714 12:29:35.022272 Set Vref, RX VrefLevel [Byte0]: 56
1715 12:29:35.025553 [Byte1]: 56
1716 12:29:35.030267
1717 12:29:35.030353 Set Vref, RX VrefLevel [Byte0]: 57
1718 12:29:35.033486 [Byte1]: 57
1719 12:29:35.037488
1720 12:29:35.037570 Set Vref, RX VrefLevel [Byte0]: 58
1721 12:29:35.040757 [Byte1]: 58
1722 12:29:35.045282
1723 12:29:35.045365 Set Vref, RX VrefLevel [Byte0]: 59
1724 12:29:35.048587 [Byte1]: 59
1725 12:29:35.052937
1726 12:29:35.053019 Set Vref, RX VrefLevel [Byte0]: 60
1727 12:29:35.055848 [Byte1]: 60
1728 12:29:35.060341
1729 12:29:35.060423 Set Vref, RX VrefLevel [Byte0]: 61
1730 12:29:35.063460 [Byte1]: 61
1731 12:29:35.067858
1732 12:29:35.067940 Set Vref, RX VrefLevel [Byte0]: 62
1733 12:29:35.070801 [Byte1]: 62
1734 12:29:35.075149
1735 12:29:35.075231 Set Vref, RX VrefLevel [Byte0]: 63
1736 12:29:35.078748 [Byte1]: 63
1737 12:29:35.082686
1738 12:29:35.082768 Set Vref, RX VrefLevel [Byte0]: 64
1739 12:29:35.085848 [Byte1]: 64
1740 12:29:35.090321
1741 12:29:35.090404 Set Vref, RX VrefLevel [Byte0]: 65
1742 12:29:35.093652 [Byte1]: 65
1743 12:29:35.097760
1744 12:29:35.097842 Set Vref, RX VrefLevel [Byte0]: 66
1745 12:29:35.101169 [Byte1]: 66
1746 12:29:35.105737
1747 12:29:35.105819 Set Vref, RX VrefLevel [Byte0]: 67
1748 12:29:35.109042 [Byte1]: 67
1749 12:29:35.113218
1750 12:29:35.113299 Set Vref, RX VrefLevel [Byte0]: 68
1751 12:29:35.116396 [Byte1]: 68
1752 12:29:35.120376
1753 12:29:35.120493 Set Vref, RX VrefLevel [Byte0]: 69
1754 12:29:35.123611 [Byte1]: 69
1755 12:29:35.128259
1756 12:29:35.128341 Set Vref, RX VrefLevel [Byte0]: 70
1757 12:29:35.131638 [Byte1]: 70
1758 12:29:35.135438
1759 12:29:35.135520 Set Vref, RX VrefLevel [Byte0]: 71
1760 12:29:35.138737 [Byte1]: 71
1761 12:29:35.143500
1762 12:29:35.143582 Set Vref, RX VrefLevel [Byte0]: 72
1763 12:29:35.146601 [Byte1]: 72
1764 12:29:35.151234
1765 12:29:35.151387 Final RX Vref Byte 0 = 58 to rank0
1766 12:29:35.153884 Final RX Vref Byte 1 = 56 to rank0
1767 12:29:35.157231 Final RX Vref Byte 0 = 58 to rank1
1768 12:29:35.161127 Final RX Vref Byte 1 = 56 to rank1==
1769 12:29:35.164254 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 12:29:35.171030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 12:29:35.171148 ==
1772 12:29:35.171253 DQS Delay:
1773 12:29:35.171394 DQS0 = 0, DQS1 = 0
1774 12:29:35.174134 DQM Delay:
1775 12:29:35.174237 DQM0 = 96, DQM1 = 91
1776 12:29:35.177249 DQ Delay:
1777 12:29:35.180763 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1778 12:29:35.184533 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1779 12:29:35.184653 DQ8 =76, DQ9 =84, DQ10 =92, DQ11 =84
1780 12:29:35.191067 DQ12 =96, DQ13 =100, DQ14 =100, DQ15 =96
1781 12:29:35.191173
1782 12:29:35.191286
1783 12:29:35.197598 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1784 12:29:35.200733 CH1 RK0: MR19=606, MR18=2B48
1785 12:29:35.207387 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1786 12:29:35.207480
1787 12:29:35.210674 ----->DramcWriteLeveling(PI) begin...
1788 12:29:35.210779 ==
1789 12:29:35.214119 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 12:29:35.217488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 12:29:35.217588 ==
1792 12:29:35.220841 Write leveling (Byte 0): 27 => 27
1793 12:29:35.224400 Write leveling (Byte 1): 28 => 28
1794 12:29:35.227558 DramcWriteLeveling(PI) end<-----
1795 12:29:35.227641
1796 12:29:35.227706 ==
1797 12:29:35.230794 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 12:29:35.234288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 12:29:35.234371 ==
1800 12:29:35.237645 [Gating] SW mode calibration
1801 12:29:35.244270 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 12:29:35.250935 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 12:29:35.254143 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1804 12:29:35.258153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1805 12:29:35.264263 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1806 12:29:35.267428 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:29:35.270914 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:29:35.277737 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:29:35.280850 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:29:35.284513 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:29:35.291120 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:29:35.294216 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:29:35.297507 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:29:35.304467 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:29:35.307601 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:29:35.310846 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:29:35.317478 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:29:35.320819 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:29:35.324151 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1820 12:29:35.327462 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1821 12:29:35.334247 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:29:35.337549 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:29:35.340900 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:29:35.347728 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:29:35.351033 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:29:35.354348 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:29:35.360642 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:29:35.364155 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1829 12:29:35.367568 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1830 12:29:35.374058 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 12:29:35.377948 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 12:29:35.381172 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 12:29:35.388016 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:29:35.391070 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:29:35.394254 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:29:35.400962 0 10 4 | B1->B0 | 2a2a 2f2f | 1 1 | (1 0) (1 0)
1837 12:29:35.404178 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1838 12:29:35.407980 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:29:35.411292 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:29:35.417742 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:29:35.421139 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:29:35.424457 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:29:35.431221 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1844 12:29:35.434552 0 11 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
1845 12:29:35.437867 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1846 12:29:35.444127 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 12:29:35.448050 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 12:29:35.451207 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 12:29:35.458042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:29:35.461387 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:29:35.464507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:29:35.471446 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1853 12:29:35.474630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:29:35.477862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:29:35.484548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:29:35.488416 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:29:35.491568 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:29:35.495131 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:29:35.501981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:29:35.505405 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:29:35.508703 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:29:35.515312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:29:35.518719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:29:35.521717 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:29:35.528847 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:29:35.531533 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:29:35.535010 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1868 12:29:35.541589 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1869 12:29:35.544927 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:29:35.548172 Total UI for P1: 0, mck2ui 16
1871 12:29:35.551970 best dqsien dly found for B0: ( 0, 14, 2)
1872 12:29:35.555309 Total UI for P1: 0, mck2ui 16
1873 12:29:35.558602 best dqsien dly found for B1: ( 0, 14, 2)
1874 12:29:35.561819 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1875 12:29:35.565173 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1876 12:29:35.565607
1877 12:29:35.568461 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1878 12:29:35.571824 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1879 12:29:35.575157 [Gating] SW calibration Done
1880 12:29:35.575632 ==
1881 12:29:35.578437 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 12:29:35.581616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 12:29:35.582055 ==
1884 12:29:35.585050 RX Vref Scan: 0
1885 12:29:35.585482
1886 12:29:35.585882 RX Vref 0 -> 0, step: 1
1887 12:29:35.588449
1888 12:29:35.588879 RX Delay -130 -> 252, step: 16
1889 12:29:35.595376 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1890 12:29:35.599099 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1891 12:29:35.601703 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1892 12:29:35.605451 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1893 12:29:35.608589 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1894 12:29:35.611674 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1895 12:29:35.618678 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1896 12:29:35.621984 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1897 12:29:35.625154 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1898 12:29:35.628931 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1899 12:29:35.632090 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1900 12:29:35.638749 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1901 12:29:35.642289 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1902 12:29:35.645567 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1903 12:29:35.648941 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1904 12:29:35.652430 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1905 12:29:35.655644 ==
1906 12:29:35.658677 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 12:29:35.661971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 12:29:35.662402 ==
1909 12:29:35.662742 DQS Delay:
1910 12:29:35.666005 DQS0 = 0, DQS1 = 0
1911 12:29:35.666431 DQM Delay:
1912 12:29:35.669301 DQM0 = 93, DQM1 = 90
1913 12:29:35.669733 DQ Delay:
1914 12:29:35.672290 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1915 12:29:35.675866 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1916 12:29:35.679174 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1917 12:29:35.682608 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1918 12:29:35.683138
1919 12:29:35.683686
1920 12:29:35.684025 ==
1921 12:29:35.685700 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 12:29:35.688948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 12:29:35.689384 ==
1924 12:29:35.689728
1925 12:29:35.690044
1926 12:29:35.692458 TX Vref Scan disable
1927 12:29:35.695920 == TX Byte 0 ==
1928 12:29:35.699183 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1929 12:29:35.702894 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1930 12:29:35.706065 == TX Byte 1 ==
1931 12:29:35.709172 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1932 12:29:35.712456 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1933 12:29:35.712882 ==
1934 12:29:35.716230 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 12:29:35.719422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 12:29:35.719849 ==
1937 12:29:35.733614 TX Vref=22, minBit 3, minWin=26, winSum=438
1938 12:29:35.737348 TX Vref=24, minBit 0, minWin=27, winSum=444
1939 12:29:35.740424 TX Vref=26, minBit 1, minWin=27, winSum=446
1940 12:29:35.743421 TX Vref=28, minBit 1, minWin=27, winSum=452
1941 12:29:35.747437 TX Vref=30, minBit 1, minWin=27, winSum=452
1942 12:29:35.750207 TX Vref=32, minBit 0, minWin=27, winSum=449
1943 12:29:35.756871 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 28
1944 12:29:35.757297
1945 12:29:35.760867 Final TX Range 1 Vref 28
1946 12:29:35.761308
1947 12:29:35.761646 ==
1948 12:29:35.764167 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 12:29:35.767546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 12:29:35.768006 ==
1951 12:29:35.768445
1952 12:29:35.768907
1953 12:29:35.770847 TX Vref Scan disable
1954 12:29:35.774242 == TX Byte 0 ==
1955 12:29:35.777392 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1956 12:29:35.780899 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1957 12:29:35.784430 == TX Byte 1 ==
1958 12:29:35.787585 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1959 12:29:35.790779 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1960 12:29:35.791307
1961 12:29:35.794181 [DATLAT]
1962 12:29:35.794605 Freq=800, CH1 RK1
1963 12:29:35.794946
1964 12:29:35.797564 DATLAT Default: 0xa
1965 12:29:35.797986 0, 0xFFFF, sum = 0
1966 12:29:35.800908 1, 0xFFFF, sum = 0
1967 12:29:35.801336 2, 0xFFFF, sum = 0
1968 12:29:35.804381 3, 0xFFFF, sum = 0
1969 12:29:35.804812 4, 0xFFFF, sum = 0
1970 12:29:35.807714 5, 0xFFFF, sum = 0
1971 12:29:35.808158 6, 0xFFFF, sum = 0
1972 12:29:35.810960 7, 0xFFFF, sum = 0
1973 12:29:35.811427 8, 0xFFFF, sum = 0
1974 12:29:35.814025 9, 0x0, sum = 1
1975 12:29:35.814459 10, 0x0, sum = 2
1976 12:29:35.817146 11, 0x0, sum = 3
1977 12:29:35.817657 12, 0x0, sum = 4
1978 12:29:35.820723 best_step = 10
1979 12:29:35.821149
1980 12:29:35.821491 ==
1981 12:29:35.823871 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 12:29:35.827032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 12:29:35.827588 ==
1984 12:29:35.831005 RX Vref Scan: 0
1985 12:29:35.831586
1986 12:29:35.831989 RX Vref 0 -> 0, step: 1
1987 12:29:35.832369
1988 12:29:35.834198 RX Delay -63 -> 252, step: 8
1989 12:29:35.837340 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1990 12:29:35.843828 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1991 12:29:35.847140 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1992 12:29:35.850886 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1993 12:29:35.854226 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1994 12:29:35.857696 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1995 12:29:35.864384 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1996 12:29:35.867061 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1997 12:29:35.870209 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1998 12:29:35.874074 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1999 12:29:35.877583 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2000 12:29:35.880798 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2001 12:29:35.887344 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2002 12:29:35.890693 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2003 12:29:35.894013 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2004 12:29:35.897237 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2005 12:29:35.897670 ==
2006 12:29:35.900906 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 12:29:35.907440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 12:29:35.907880 ==
2009 12:29:35.908224 DQS Delay:
2010 12:29:35.908548 DQS0 = 0, DQS1 = 0
2011 12:29:35.910843 DQM Delay:
2012 12:29:35.911271 DQM0 = 97, DQM1 = 90
2013 12:29:35.914353 DQ Delay:
2014 12:29:35.917326 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2015 12:29:35.920629 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2016 12:29:35.924389 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2017 12:29:35.927409 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2018 12:29:35.928010
2019 12:29:35.928502
2020 12:29:35.934002 [DQSOSCAuto] RK1, (LSB)MR18= 0x430d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2021 12:29:35.937633 CH1 RK1: MR19=606, MR18=430D
2022 12:29:35.944336 CH1_RK1: MR19=0x606, MR18=0x430D, DQSOSC=393, MR23=63, INC=95, DEC=63
2023 12:29:35.947631 [RxdqsGatingPostProcess] freq 800
2024 12:29:35.950797 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 12:29:35.954825 Pre-setting of DQS Precalculation
2026 12:29:35.960953 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 12:29:35.967628 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 12:29:35.974333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 12:29:35.974809
2030 12:29:35.975150
2031 12:29:35.977632 [Calibration Summary] 1600 Mbps
2032 12:29:35.978076 CH 0, Rank 0
2033 12:29:35.980888 SW Impedance : PASS
2034 12:29:35.984162 DUTY Scan : NO K
2035 12:29:35.984586 ZQ Calibration : PASS
2036 12:29:35.987513 Jitter Meter : NO K
2037 12:29:35.987951 CBT Training : PASS
2038 12:29:35.990736 Write leveling : PASS
2039 12:29:35.994610 RX DQS gating : PASS
2040 12:29:35.995100 RX DQ/DQS(RDDQC) : PASS
2041 12:29:35.997388 TX DQ/DQS : PASS
2042 12:29:36.001198 RX DATLAT : PASS
2043 12:29:36.001666 RX DQ/DQS(Engine): PASS
2044 12:29:36.004689 TX OE : NO K
2045 12:29:36.005115 All Pass.
2046 12:29:36.005452
2047 12:29:36.007969 CH 0, Rank 1
2048 12:29:36.008424 SW Impedance : PASS
2049 12:29:36.011314 DUTY Scan : NO K
2050 12:29:36.014592 ZQ Calibration : PASS
2051 12:29:36.015048 Jitter Meter : NO K
2052 12:29:36.017726 CBT Training : PASS
2053 12:29:36.020813 Write leveling : PASS
2054 12:29:36.020895 RX DQS gating : PASS
2055 12:29:36.024130 RX DQ/DQS(RDDQC) : PASS
2056 12:29:36.024261 TX DQ/DQS : PASS
2057 12:29:36.027609 RX DATLAT : PASS
2058 12:29:36.030834 RX DQ/DQS(Engine): PASS
2059 12:29:36.030942 TX OE : NO K
2060 12:29:36.034030 All Pass.
2061 12:29:36.034111
2062 12:29:36.034176 CH 1, Rank 0
2063 12:29:36.037613 SW Impedance : PASS
2064 12:29:36.037696 DUTY Scan : NO K
2065 12:29:36.040694 ZQ Calibration : PASS
2066 12:29:36.044396 Jitter Meter : NO K
2067 12:29:36.044484 CBT Training : PASS
2068 12:29:36.047680 Write leveling : PASS
2069 12:29:36.050787 RX DQS gating : PASS
2070 12:29:36.050889 RX DQ/DQS(RDDQC) : PASS
2071 12:29:36.054699 TX DQ/DQS : PASS
2072 12:29:36.057811 RX DATLAT : PASS
2073 12:29:36.057922 RX DQ/DQS(Engine): PASS
2074 12:29:36.060955 TX OE : NO K
2075 12:29:36.061079 All Pass.
2076 12:29:36.061176
2077 12:29:36.061267 CH 1, Rank 1
2078 12:29:36.064163 SW Impedance : PASS
2079 12:29:36.068139 DUTY Scan : NO K
2080 12:29:36.068274 ZQ Calibration : PASS
2081 12:29:36.071363 Jitter Meter : NO K
2082 12:29:36.074646 CBT Training : PASS
2083 12:29:36.074798 Write leveling : PASS
2084 12:29:36.078062 RX DQS gating : PASS
2085 12:29:36.081335 RX DQ/DQS(RDDQC) : PASS
2086 12:29:36.081536 TX DQ/DQS : PASS
2087 12:29:36.084143 RX DATLAT : PASS
2088 12:29:36.088029 RX DQ/DQS(Engine): PASS
2089 12:29:36.088270 TX OE : NO K
2090 12:29:36.091425 All Pass.
2091 12:29:36.091723
2092 12:29:36.091961 DramC Write-DBI off
2093 12:29:36.094653 PER_BANK_REFRESH: Hybrid Mode
2094 12:29:36.094952 TX_TRACKING: ON
2095 12:29:36.098020 [GetDramInforAfterCalByMRR] Vendor 6.
2096 12:29:36.104764 [GetDramInforAfterCalByMRR] Revision 606.
2097 12:29:36.108029 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 12:29:36.108454 MR0 0x3b3b
2099 12:29:36.108793 MR8 0x5151
2100 12:29:36.111096 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 12:29:36.111177
2102 12:29:36.114285 MR0 0x3b3b
2103 12:29:36.114367 MR8 0x5151
2104 12:29:36.117924 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 12:29:36.118007
2106 12:29:36.127560 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 12:29:36.131454 [FAST_K] Save calibration result to emmc
2108 12:29:36.134693 [FAST_K] Save calibration result to emmc
2109 12:29:36.138189 dram_init: config_dvfs: 1
2110 12:29:36.141457 dramc_set_vcore_voltage set vcore to 662500
2111 12:29:36.144592 Read voltage for 1200, 2
2112 12:29:36.144674 Vio18 = 0
2113 12:29:36.144740 Vcore = 662500
2114 12:29:36.147784 Vdram = 0
2115 12:29:36.147897 Vddq = 0
2116 12:29:36.147991 Vmddr = 0
2117 12:29:36.154433 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 12:29:36.157558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 12:29:36.161390 MEM_TYPE=3, freq_sel=15
2120 12:29:36.164600 sv_algorithm_assistance_LP4_1600
2121 12:29:36.167731 ============ PULL DRAM RESETB DOWN ============
2122 12:29:36.170803 ========== PULL DRAM RESETB DOWN end =========
2123 12:29:36.178033 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 12:29:36.181206 ===================================
2125 12:29:36.181295 LPDDR4 DRAM CONFIGURATION
2126 12:29:36.184494 ===================================
2127 12:29:36.187847 EX_ROW_EN[0] = 0x0
2128 12:29:36.187930 EX_ROW_EN[1] = 0x0
2129 12:29:36.191118 LP4Y_EN = 0x0
2130 12:29:36.191201 WORK_FSP = 0x0
2131 12:29:36.194908 WL = 0x4
2132 12:29:36.194991 RL = 0x4
2133 12:29:36.198066 BL = 0x2
2134 12:29:36.201492 RPST = 0x0
2135 12:29:36.201575 RD_PRE = 0x0
2136 12:29:36.204901 WR_PRE = 0x1
2137 12:29:36.204984 WR_PST = 0x0
2138 12:29:36.208269 DBI_WR = 0x0
2139 12:29:36.208353 DBI_RD = 0x0
2140 12:29:36.211595 OTF = 0x1
2141 12:29:36.214948 ===================================
2142 12:29:36.217730 ===================================
2143 12:29:36.217815 ANA top config
2144 12:29:36.221652 ===================================
2145 12:29:36.224826 DLL_ASYNC_EN = 0
2146 12:29:36.228176 ALL_SLAVE_EN = 0
2147 12:29:36.228266 NEW_RANK_MODE = 1
2148 12:29:36.231503 DLL_IDLE_MODE = 1
2149 12:29:36.234962 LP45_APHY_COMB_EN = 1
2150 12:29:36.238160 TX_ODT_DIS = 1
2151 12:29:36.238268 NEW_8X_MODE = 1
2152 12:29:36.241593 ===================================
2153 12:29:36.244819 ===================================
2154 12:29:36.248193 data_rate = 2400
2155 12:29:36.251396 CKR = 1
2156 12:29:36.254584 DQ_P2S_RATIO = 8
2157 12:29:36.258243 ===================================
2158 12:29:36.261408 CA_P2S_RATIO = 8
2159 12:29:36.264622 DQ_CA_OPEN = 0
2160 12:29:36.264800 DQ_SEMI_OPEN = 0
2161 12:29:36.267959 CA_SEMI_OPEN = 0
2162 12:29:36.271279 CA_FULL_RATE = 0
2163 12:29:36.274828 DQ_CKDIV4_EN = 0
2164 12:29:36.278016 CA_CKDIV4_EN = 0
2165 12:29:36.281587 CA_PREDIV_EN = 0
2166 12:29:36.282073 PH8_DLY = 17
2167 12:29:36.284811 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 12:29:36.288587 DQ_AAMCK_DIV = 4
2169 12:29:36.291819 CA_AAMCK_DIV = 4
2170 12:29:36.295208 CA_ADMCK_DIV = 4
2171 12:29:36.298525 DQ_TRACK_CA_EN = 0
2172 12:29:36.299079 CA_PICK = 1200
2173 12:29:36.301659 CA_MCKIO = 1200
2174 12:29:36.305343 MCKIO_SEMI = 0
2175 12:29:36.308597 PLL_FREQ = 2366
2176 12:29:36.312016 DQ_UI_PI_RATIO = 32
2177 12:29:36.315255 CA_UI_PI_RATIO = 0
2178 12:29:36.318726 ===================================
2179 12:29:36.322053 ===================================
2180 12:29:36.322617 memory_type:LPDDR4
2181 12:29:36.325356 GP_NUM : 10
2182 12:29:36.329030 SRAM_EN : 1
2183 12:29:36.329415 MD32_EN : 0
2184 12:29:36.331727 ===================================
2185 12:29:36.335141 [ANA_INIT] >>>>>>>>>>>>>>
2186 12:29:36.338438 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 12:29:36.341679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 12:29:36.345049 ===================================
2189 12:29:36.348352 data_rate = 2400,PCW = 0X5b00
2190 12:29:36.351686 ===================================
2191 12:29:36.355131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 12:29:36.358357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 12:29:36.365156 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 12:29:36.368880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 12:29:36.372163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 12:29:36.375492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 12:29:36.378688 [ANA_INIT] flow start
2198 12:29:36.381861 [ANA_INIT] PLL >>>>>>>>
2199 12:29:36.382310 [ANA_INIT] PLL <<<<<<<<
2200 12:29:36.385212 [ANA_INIT] MIDPI >>>>>>>>
2201 12:29:36.388881 [ANA_INIT] MIDPI <<<<<<<<
2202 12:29:36.389309 [ANA_INIT] DLL >>>>>>>>
2203 12:29:36.392170 [ANA_INIT] DLL <<<<<<<<
2204 12:29:36.395513 [ANA_INIT] flow end
2205 12:29:36.399011 ============ LP4 DIFF to SE enter ============
2206 12:29:36.402186 ============ LP4 DIFF to SE exit ============
2207 12:29:36.405127 [ANA_INIT] <<<<<<<<<<<<<
2208 12:29:36.408935 [Flow] Enable top DCM control >>>>>
2209 12:29:36.411842 [Flow] Enable top DCM control <<<<<
2210 12:29:36.415062 Enable DLL master slave shuffle
2211 12:29:36.419048 ==============================================================
2212 12:29:36.421792 Gating Mode config
2213 12:29:36.428586 ==============================================================
2214 12:29:36.429022 Config description:
2215 12:29:36.438664 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 12:29:36.445537 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 12:29:36.448551 SELPH_MODE 0: By rank 1: By Phase
2218 12:29:36.455283 ==============================================================
2219 12:29:36.458778 GAT_TRACK_EN = 1
2220 12:29:36.462105 RX_GATING_MODE = 2
2221 12:29:36.465312 RX_GATING_TRACK_MODE = 2
2222 12:29:36.468417 SELPH_MODE = 1
2223 12:29:36.472005 PICG_EARLY_EN = 1
2224 12:29:36.475034 VALID_LAT_VALUE = 1
2225 12:29:36.478760 ==============================================================
2226 12:29:36.481912 Enter into Gating configuration >>>>
2227 12:29:36.485732 Exit from Gating configuration <<<<
2228 12:29:36.489006 Enter into DVFS_PRE_config >>>>>
2229 12:29:36.498768 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 12:29:36.502105 Exit from DVFS_PRE_config <<<<<
2231 12:29:36.505213 Enter into PICG configuration >>>>
2232 12:29:36.508671 Exit from PICG configuration <<<<
2233 12:29:36.511992 [RX_INPUT] configuration >>>>>
2234 12:29:36.515190 [RX_INPUT] configuration <<<<<
2235 12:29:36.522237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 12:29:36.525176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 12:29:36.532119 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 12:29:36.538825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 12:29:36.545128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 12:29:36.552046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 12:29:36.555456 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 12:29:36.558991 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 12:29:36.562254 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 12:29:36.565561 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 12:29:36.572116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 12:29:36.575088 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 12:29:36.578811 ===================================
2248 12:29:36.582070 LPDDR4 DRAM CONFIGURATION
2249 12:29:36.585677 ===================================
2250 12:29:36.586327 EX_ROW_EN[0] = 0x0
2251 12:29:36.589103 EX_ROW_EN[1] = 0x0
2252 12:29:36.589560 LP4Y_EN = 0x0
2253 12:29:36.592241 WORK_FSP = 0x0
2254 12:29:36.592669 WL = 0x4
2255 12:29:36.595459 RL = 0x4
2256 12:29:36.595899 BL = 0x2
2257 12:29:36.598567 RPST = 0x0
2258 12:29:36.598994 RD_PRE = 0x0
2259 12:29:36.601846 WR_PRE = 0x1
2260 12:29:36.602273 WR_PST = 0x0
2261 12:29:36.605664 DBI_WR = 0x0
2262 12:29:36.608875 DBI_RD = 0x0
2263 12:29:36.609304 OTF = 0x1
2264 12:29:36.612151 ===================================
2265 12:29:36.615492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 12:29:36.618864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 12:29:36.625367 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 12:29:36.628651 ===================================
2269 12:29:36.631711 LPDDR4 DRAM CONFIGURATION
2270 12:29:36.632270 ===================================
2271 12:29:36.635628 EX_ROW_EN[0] = 0x10
2272 12:29:36.638850 EX_ROW_EN[1] = 0x0
2273 12:29:36.639444 LP4Y_EN = 0x0
2274 12:29:36.642342 WORK_FSP = 0x0
2275 12:29:36.642767 WL = 0x4
2276 12:29:36.645557 RL = 0x4
2277 12:29:36.645984 BL = 0x2
2278 12:29:36.648823 RPST = 0x0
2279 12:29:36.649252 RD_PRE = 0x0
2280 12:29:36.652171 WR_PRE = 0x1
2281 12:29:36.652598 WR_PST = 0x0
2282 12:29:36.655618 DBI_WR = 0x0
2283 12:29:36.656046 DBI_RD = 0x0
2284 12:29:36.658913 OTF = 0x1
2285 12:29:36.661968 ===================================
2286 12:29:36.668713 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 12:29:36.669171 ==
2288 12:29:36.672021 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 12:29:36.675320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 12:29:36.675838 ==
2291 12:29:36.678649 [Duty_Offset_Calibration]
2292 12:29:36.679078 B0:2 B1:1 CA:1
2293 12:29:36.679454
2294 12:29:36.682193 [DutyScan_Calibration_Flow] k_type=0
2295 12:29:36.692739
2296 12:29:36.693154 ==CLK 0==
2297 12:29:36.696083 Final CLK duty delay cell = 0
2298 12:29:36.699055 [0] MAX Duty = 5187%(X100), DQS PI = 24
2299 12:29:36.702347 [0] MIN Duty = 4875%(X100), DQS PI = 0
2300 12:29:36.702913 [0] AVG Duty = 5031%(X100)
2301 12:29:36.703436
2302 12:29:36.705539 CH0 CLK Duty spec in!! Max-Min= 312%
2303 12:29:36.712081 [DutyScan_Calibration_Flow] ====Done====
2304 12:29:36.712499
2305 12:29:36.715825 [DutyScan_Calibration_Flow] k_type=1
2306 12:29:36.730440
2307 12:29:36.730946 ==DQS 0 ==
2308 12:29:36.733715 Final DQS duty delay cell = -4
2309 12:29:36.737373 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2310 12:29:36.740227 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2311 12:29:36.743251 [-4] AVG Duty = 4969%(X100)
2312 12:29:36.743867
2313 12:29:36.744341 ==DQS 1 ==
2314 12:29:36.746504 Final DQS duty delay cell = -4
2315 12:29:36.749814 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2316 12:29:36.753664 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2317 12:29:36.756461 [-4] AVG Duty = 4906%(X100)
2318 12:29:36.757067
2319 12:29:36.759793 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2320 12:29:36.760340
2321 12:29:36.763777 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2322 12:29:36.767205 [DutyScan_Calibration_Flow] ====Done====
2323 12:29:36.767679
2324 12:29:36.770605 [DutyScan_Calibration_Flow] k_type=3
2325 12:29:36.786748
2326 12:29:36.787533 ==DQM 0 ==
2327 12:29:36.789730 Final DQM duty delay cell = 0
2328 12:29:36.793300 [0] MAX Duty = 5156%(X100), DQS PI = 30
2329 12:29:36.796294 [0] MIN Duty = 4906%(X100), DQS PI = 52
2330 12:29:36.796709 [0] AVG Duty = 5031%(X100)
2331 12:29:36.799979
2332 12:29:36.800388 ==DQM 1 ==
2333 12:29:36.803036 Final DQM duty delay cell = -4
2334 12:29:36.806191 [-4] MAX Duty = 4969%(X100), DQS PI = 58
2335 12:29:36.810083 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2336 12:29:36.813295 [-4] AVG Duty = 4922%(X100)
2337 12:29:36.813708
2338 12:29:36.816676 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2339 12:29:36.817095
2340 12:29:36.819953 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2341 12:29:36.823087 [DutyScan_Calibration_Flow] ====Done====
2342 12:29:36.823526
2343 12:29:36.826378 [DutyScan_Calibration_Flow] k_type=2
2344 12:29:36.843240
2345 12:29:36.843803 ==DQ 0 ==
2346 12:29:36.846371 Final DQ duty delay cell = 0
2347 12:29:36.850092 [0] MAX Duty = 5031%(X100), DQS PI = 24
2348 12:29:36.853252 [0] MIN Duty = 4906%(X100), DQS PI = 0
2349 12:29:36.853864 [0] AVG Duty = 4968%(X100)
2350 12:29:36.854384
2351 12:29:36.856404 ==DQ 1 ==
2352 12:29:36.859762 Final DQ duty delay cell = 0
2353 12:29:36.863102 [0] MAX Duty = 5093%(X100), DQS PI = 24
2354 12:29:36.866420 [0] MIN Duty = 4938%(X100), DQS PI = 36
2355 12:29:36.866849 [0] AVG Duty = 5015%(X100)
2356 12:29:36.867188
2357 12:29:36.870145 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2358 12:29:36.872902
2359 12:29:36.875819 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2360 12:29:36.879953 [DutyScan_Calibration_Flow] ====Done====
2361 12:29:36.880036 ==
2362 12:29:36.882591 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 12:29:36.886475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 12:29:36.886559 ==
2365 12:29:36.889741 [Duty_Offset_Calibration]
2366 12:29:36.889823 B0:1 B1:0 CA:0
2367 12:29:36.889888
2368 12:29:36.892914 [DutyScan_Calibration_Flow] k_type=0
2369 12:29:36.901892
2370 12:29:36.901975 ==CLK 0==
2371 12:29:36.905625 Final CLK duty delay cell = -4
2372 12:29:36.908819 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2373 12:29:36.912140 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2374 12:29:36.915366 [-4] AVG Duty = 4969%(X100)
2375 12:29:36.915475
2376 12:29:36.918622 CH1 CLK Duty spec in!! Max-Min= 124%
2377 12:29:36.922310 [DutyScan_Calibration_Flow] ====Done====
2378 12:29:36.922423
2379 12:29:36.925604 [DutyScan_Calibration_Flow] k_type=1
2380 12:29:36.942159
2381 12:29:36.942585 ==DQS 0 ==
2382 12:29:36.945530 Final DQS duty delay cell = 0
2383 12:29:36.948633 [0] MAX Duty = 5094%(X100), DQS PI = 24
2384 12:29:36.951851 [0] MIN Duty = 4875%(X100), DQS PI = 0
2385 12:29:36.951934 [0] AVG Duty = 4984%(X100)
2386 12:29:36.955053
2387 12:29:36.955135 ==DQS 1 ==
2388 12:29:36.958899 Final DQS duty delay cell = 0
2389 12:29:36.962171 [0] MAX Duty = 5187%(X100), DQS PI = 20
2390 12:29:36.965605 [0] MIN Duty = 4938%(X100), DQS PI = 12
2391 12:29:36.965694 [0] AVG Duty = 5062%(X100)
2392 12:29:36.968416
2393 12:29:36.971761 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2394 12:29:36.971857
2395 12:29:36.975629 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2396 12:29:36.978928 [DutyScan_Calibration_Flow] ====Done====
2397 12:29:36.979112
2398 12:29:36.982283 [DutyScan_Calibration_Flow] k_type=3
2399 12:29:36.998871
2400 12:29:36.999106 ==DQM 0 ==
2401 12:29:37.002139 Final DQM duty delay cell = 0
2402 12:29:37.005117 [0] MAX Duty = 5156%(X100), DQS PI = 6
2403 12:29:37.008136 [0] MIN Duty = 5031%(X100), DQS PI = 0
2404 12:29:37.008220 [0] AVG Duty = 5093%(X100)
2405 12:29:37.011850
2406 12:29:37.011933 ==DQM 1 ==
2407 12:29:37.015238 Final DQM duty delay cell = 0
2408 12:29:37.018182 [0] MAX Duty = 5031%(X100), DQS PI = 16
2409 12:29:37.022341 [0] MIN Duty = 4907%(X100), DQS PI = 36
2410 12:29:37.022430 [0] AVG Duty = 4969%(X100)
2411 12:29:37.022501
2412 12:29:37.025793 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2413 12:29:37.028897
2414 12:29:37.032233 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2415 12:29:37.035565 [DutyScan_Calibration_Flow] ====Done====
2416 12:29:37.035747
2417 12:29:37.038912 [DutyScan_Calibration_Flow] k_type=2
2418 12:29:37.054379
2419 12:29:37.054615 ==DQ 0 ==
2420 12:29:37.057898 Final DQ duty delay cell = -4
2421 12:29:37.061267 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2422 12:29:37.064150 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2423 12:29:37.067802 [-4] AVG Duty = 5000%(X100)
2424 12:29:37.068124
2425 12:29:37.068318 ==DQ 1 ==
2426 12:29:37.071164 Final DQ duty delay cell = 0
2427 12:29:37.074288 [0] MAX Duty = 5125%(X100), DQS PI = 20
2428 12:29:37.077988 [0] MIN Duty = 4969%(X100), DQS PI = 12
2429 12:29:37.081296 [0] AVG Duty = 5047%(X100)
2430 12:29:37.081685
2431 12:29:37.084002 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2432 12:29:37.084429
2433 12:29:37.087426 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2434 12:29:37.090785 [DutyScan_Calibration_Flow] ====Done====
2435 12:29:37.093799 nWR fixed to 30
2436 12:29:37.093883 [ModeRegInit_LP4] CH0 RK0
2437 12:29:37.097142 [ModeRegInit_LP4] CH0 RK1
2438 12:29:37.101035 [ModeRegInit_LP4] CH1 RK0
2439 12:29:37.103722 [ModeRegInit_LP4] CH1 RK1
2440 12:29:37.103804 match AC timing 7
2441 12:29:37.107270 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 12:29:37.114633 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 12:29:37.117284 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 12:29:37.121185 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 12:29:37.127564 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 12:29:37.127732 ==
2447 12:29:37.130723 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 12:29:37.133891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 12:29:37.134038 ==
2450 12:29:37.141034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 12:29:37.147557 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 12:29:37.154212 [CA 0] Center 39 (8~70) winsize 63
2453 12:29:37.157503 [CA 1] Center 39 (8~70) winsize 63
2454 12:29:37.160879 [CA 2] Center 35 (5~66) winsize 62
2455 12:29:37.164163 [CA 3] Center 34 (4~65) winsize 62
2456 12:29:37.167554 [CA 4] Center 33 (3~64) winsize 62
2457 12:29:37.170770 [CA 5] Center 32 (3~62) winsize 60
2458 12:29:37.170853
2459 12:29:37.174480 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2460 12:29:37.174563
2461 12:29:37.177618 [CATrainingPosCal] consider 1 rank data
2462 12:29:37.180852 u2DelayCellTimex100 = 270/100 ps
2463 12:29:37.184237 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 12:29:37.187607 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 12:29:37.194032 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2466 12:29:37.197529 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2467 12:29:37.200931 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2468 12:29:37.204103 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2469 12:29:37.204186
2470 12:29:37.207490 CA PerBit enable=1, Macro0, CA PI delay=32
2471 12:29:37.207573
2472 12:29:37.210787 [CBTSetCACLKResult] CA Dly = 32
2473 12:29:37.210871 CS Dly: 6 (0~37)
2474 12:29:37.210937 ==
2475 12:29:37.214340 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 12:29:37.221388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 12:29:37.221471 ==
2478 12:29:37.224305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 12:29:37.231075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2480 12:29:37.239861 [CA 0] Center 38 (8~69) winsize 62
2481 12:29:37.243603 [CA 1] Center 38 (8~69) winsize 62
2482 12:29:37.246884 [CA 2] Center 35 (4~66) winsize 63
2483 12:29:37.250086 [CA 3] Center 34 (4~65) winsize 62
2484 12:29:37.253278 [CA 4] Center 33 (3~64) winsize 62
2485 12:29:37.256586 [CA 5] Center 32 (2~62) winsize 61
2486 12:29:37.256669
2487 12:29:37.260031 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 12:29:37.260114
2489 12:29:37.264163 [CATrainingPosCal] consider 2 rank data
2490 12:29:37.267423 u2DelayCellTimex100 = 270/100 ps
2491 12:29:37.270693 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 12:29:37.273992 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 12:29:37.277151 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2494 12:29:37.284237 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 12:29:37.287582 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2496 12:29:37.290317 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2497 12:29:37.290762
2498 12:29:37.294265 CA PerBit enable=1, Macro0, CA PI delay=32
2499 12:29:37.294709
2500 12:29:37.297285 [CBTSetCACLKResult] CA Dly = 32
2501 12:29:37.297371 CS Dly: 6 (0~38)
2502 12:29:37.297457
2503 12:29:37.300602 ----->DramcWriteLeveling(PI) begin...
2504 12:29:37.300689 ==
2505 12:29:37.303743 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 12:29:37.310521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 12:29:37.310608 ==
2508 12:29:37.313818 Write leveling (Byte 0): 34 => 34
2509 12:29:37.317276 Write leveling (Byte 1): 29 => 29
2510 12:29:37.317362 DramcWriteLeveling(PI) end<-----
2511 12:29:37.317448
2512 12:29:37.320580 ==
2513 12:29:37.323842 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 12:29:37.327029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 12:29:37.327115 ==
2516 12:29:37.330620 [Gating] SW mode calibration
2517 12:29:37.336940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 12:29:37.340175 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 12:29:37.347156 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2520 12:29:37.350280 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2521 12:29:37.354212 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 12:29:37.360636 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 12:29:37.363809 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 12:29:37.367078 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:29:37.373795 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2526 12:29:37.377190 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2527 12:29:37.380406 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2528 12:29:37.383755 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 12:29:37.390947 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 12:29:37.394191 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 12:29:37.397326 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:29:37.403853 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:29:37.408110 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2534 12:29:37.411079 1 0 28 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
2535 12:29:37.417181 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2536 12:29:37.421018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 12:29:37.424103 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 12:29:37.430606 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 12:29:37.434437 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:29:37.437664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:29:37.444150 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:29:37.447816 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 12:29:37.451173 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2544 12:29:37.454371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:29:37.461149 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:29:37.464569 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:29:37.468330 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:29:37.474773 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:29:37.478014 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:29:37.481284 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:29:37.487857 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:29:37.491851 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:29:37.495182 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:29:37.502176 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:29:37.505285 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:29:37.508574 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:29:37.515283 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:29:37.518868 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 12:29:37.521868 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 12:29:37.524694 Total UI for P1: 0, mck2ui 16
2561 12:29:37.528075 best dqsien dly found for B0: ( 1, 3, 28)
2562 12:29:37.531618 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 12:29:37.538051 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 12:29:37.542022 Total UI for P1: 0, mck2ui 16
2565 12:29:37.545287 best dqsien dly found for B1: ( 1, 4, 2)
2566 12:29:37.548354 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2567 12:29:37.551652 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2568 12:29:37.552079
2569 12:29:37.554934 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2570 12:29:37.558461 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2571 12:29:37.561877 [Gating] SW calibration Done
2572 12:29:37.562548 ==
2573 12:29:37.564635 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 12:29:37.568071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 12:29:37.568498 ==
2576 12:29:37.571497 RX Vref Scan: 0
2577 12:29:37.571919
2578 12:29:37.572258 RX Vref 0 -> 0, step: 1
2579 12:29:37.572575
2580 12:29:37.574578 RX Delay -40 -> 252, step: 8
2581 12:29:37.578554 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2582 12:29:37.585320 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2583 12:29:37.588365 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2584 12:29:37.591632 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2585 12:29:37.595111 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2586 12:29:37.598504 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2587 12:29:37.605024 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2588 12:29:37.608503 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2589 12:29:37.611596 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2590 12:29:37.614645 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2591 12:29:37.617852 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2592 12:29:37.624648 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2593 12:29:37.628008 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2594 12:29:37.631374 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2595 12:29:37.634665 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2596 12:29:37.638040 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2597 12:29:37.641333 ==
2598 12:29:37.641778 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 12:29:37.648582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 12:29:37.649007 ==
2601 12:29:37.649340 DQS Delay:
2602 12:29:37.651219 DQS0 = 0, DQS1 = 0
2603 12:29:37.651700 DQM Delay:
2604 12:29:37.655126 DQM0 = 121, DQM1 = 113
2605 12:29:37.655631 DQ Delay:
2606 12:29:37.658413 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2607 12:29:37.661570 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2608 12:29:37.664786 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2609 12:29:37.668090 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2610 12:29:37.668623
2611 12:29:37.669097
2612 12:29:37.669558 ==
2613 12:29:37.671750 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 12:29:37.675280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 12:29:37.678508 ==
2616 12:29:37.678946
2617 12:29:37.679301
2618 12:29:37.679695 TX Vref Scan disable
2619 12:29:37.681782 == TX Byte 0 ==
2620 12:29:37.685045 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2621 12:29:37.688248 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2622 12:29:37.692008 == TX Byte 1 ==
2623 12:29:37.695144 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2624 12:29:37.698305 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2625 12:29:37.701900 ==
2626 12:29:37.702476 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 12:29:37.708413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 12:29:37.708893 ==
2629 12:29:37.719750 TX Vref=22, minBit 0, minWin=24, winSum=406
2630 12:29:37.723019 TX Vref=24, minBit 0, minWin=25, winSum=416
2631 12:29:37.726242 TX Vref=26, minBit 2, minWin=25, winSum=419
2632 12:29:37.729539 TX Vref=28, minBit 0, minWin=26, winSum=424
2633 12:29:37.732910 TX Vref=30, minBit 0, minWin=26, winSum=425
2634 12:29:37.736298 TX Vref=32, minBit 0, minWin=26, winSum=422
2635 12:29:37.743147 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2636 12:29:37.743615
2637 12:29:37.746508 Final TX Range 1 Vref 30
2638 12:29:37.746935
2639 12:29:37.747293 ==
2640 12:29:37.749572 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 12:29:37.753002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 12:29:37.753432 ==
2643 12:29:37.753802
2644 12:29:37.756673
2645 12:29:37.757202 TX Vref Scan disable
2646 12:29:37.759798 == TX Byte 0 ==
2647 12:29:37.762928 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2648 12:29:37.766101 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2649 12:29:37.769883 == TX Byte 1 ==
2650 12:29:37.773304 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2651 12:29:37.776223 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2652 12:29:37.776650
2653 12:29:37.779920 [DATLAT]
2654 12:29:37.780393 Freq=1200, CH0 RK0
2655 12:29:37.780808
2656 12:29:37.783287 DATLAT Default: 0xd
2657 12:29:37.783751 0, 0xFFFF, sum = 0
2658 12:29:37.786476 1, 0xFFFF, sum = 0
2659 12:29:37.786977 2, 0xFFFF, sum = 0
2660 12:29:37.789771 3, 0xFFFF, sum = 0
2661 12:29:37.790350 4, 0xFFFF, sum = 0
2662 12:29:37.793028 5, 0xFFFF, sum = 0
2663 12:29:37.793456 6, 0xFFFF, sum = 0
2664 12:29:37.796176 7, 0xFFFF, sum = 0
2665 12:29:37.796627 8, 0xFFFF, sum = 0
2666 12:29:37.799734 9, 0xFFFF, sum = 0
2667 12:29:37.799844 10, 0xFFFF, sum = 0
2668 12:29:37.802781 11, 0xFFFF, sum = 0
2669 12:29:37.802864 12, 0x0, sum = 1
2670 12:29:37.805915 13, 0x0, sum = 2
2671 12:29:37.805998 14, 0x0, sum = 3
2672 12:29:37.809307 15, 0x0, sum = 4
2673 12:29:37.809390 best_step = 13
2674 12:29:37.809456
2675 12:29:37.809516 ==
2676 12:29:37.813125 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 12:29:37.819109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 12:29:37.819219 ==
2679 12:29:37.819313 RX Vref Scan: 1
2680 12:29:37.819420
2681 12:29:37.823119 Set Vref Range= 32 -> 127
2682 12:29:37.823264
2683 12:29:37.826217 RX Vref 32 -> 127, step: 1
2684 12:29:37.826343
2685 12:29:37.829763 RX Delay -13 -> 252, step: 4
2686 12:29:37.829849
2687 12:29:37.832736 Set Vref, RX VrefLevel [Byte0]: 32
2688 12:29:37.836048 [Byte1]: 32
2689 12:29:37.836133
2690 12:29:37.839638 Set Vref, RX VrefLevel [Byte0]: 33
2691 12:29:37.842925 [Byte1]: 33
2692 12:29:37.843011
2693 12:29:37.846331 Set Vref, RX VrefLevel [Byte0]: 34
2694 12:29:37.849793 [Byte1]: 34
2695 12:29:37.853483
2696 12:29:37.853599 Set Vref, RX VrefLevel [Byte0]: 35
2697 12:29:37.856845 [Byte1]: 35
2698 12:29:37.861434
2699 12:29:37.861576 Set Vref, RX VrefLevel [Byte0]: 36
2700 12:29:37.864792 [Byte1]: 36
2701 12:29:37.869194
2702 12:29:37.869355 Set Vref, RX VrefLevel [Byte0]: 37
2703 12:29:37.872453 [Byte1]: 37
2704 12:29:37.877062
2705 12:29:37.877502 Set Vref, RX VrefLevel [Byte0]: 38
2706 12:29:37.880466 [Byte1]: 38
2707 12:29:37.885391
2708 12:29:37.885971 Set Vref, RX VrefLevel [Byte0]: 39
2709 12:29:37.888802 [Byte1]: 39
2710 12:29:37.893048
2711 12:29:37.893131 Set Vref, RX VrefLevel [Byte0]: 40
2712 12:29:37.896252 [Byte1]: 40
2713 12:29:37.900874
2714 12:29:37.900971 Set Vref, RX VrefLevel [Byte0]: 41
2715 12:29:37.904315 [Byte1]: 41
2716 12:29:37.908907
2717 12:29:37.909088 Set Vref, RX VrefLevel [Byte0]: 42
2718 12:29:37.912075 [Byte1]: 42
2719 12:29:37.916703
2720 12:29:37.916871 Set Vref, RX VrefLevel [Byte0]: 43
2721 12:29:37.919869 [Byte1]: 43
2722 12:29:37.924263
2723 12:29:37.924348 Set Vref, RX VrefLevel [Byte0]: 44
2724 12:29:37.927661 [Byte1]: 44
2725 12:29:37.932300
2726 12:29:37.932384 Set Vref, RX VrefLevel [Byte0]: 45
2727 12:29:37.935581 [Byte1]: 45
2728 12:29:37.940085
2729 12:29:37.940169 Set Vref, RX VrefLevel [Byte0]: 46
2730 12:29:37.943560 [Byte1]: 46
2731 12:29:37.948219
2732 12:29:37.948301 Set Vref, RX VrefLevel [Byte0]: 47
2733 12:29:37.951477 [Byte1]: 47
2734 12:29:37.956118
2735 12:29:37.956206 Set Vref, RX VrefLevel [Byte0]: 48
2736 12:29:37.959150 [Byte1]: 48
2737 12:29:37.963872
2738 12:29:37.963953 Set Vref, RX VrefLevel [Byte0]: 49
2739 12:29:37.967205 [Byte1]: 49
2740 12:29:37.971964
2741 12:29:37.972068 Set Vref, RX VrefLevel [Byte0]: 50
2742 12:29:37.974925 [Byte1]: 50
2743 12:29:37.979380
2744 12:29:37.979465 Set Vref, RX VrefLevel [Byte0]: 51
2745 12:29:37.982782 [Byte1]: 51
2746 12:29:37.987440
2747 12:29:37.987521 Set Vref, RX VrefLevel [Byte0]: 52
2748 12:29:37.990704 [Byte1]: 52
2749 12:29:37.994988
2750 12:29:37.995080 Set Vref, RX VrefLevel [Byte0]: 53
2751 12:29:37.998260 [Byte1]: 53
2752 12:29:38.002970
2753 12:29:38.003048 Set Vref, RX VrefLevel [Byte0]: 54
2754 12:29:38.006257 [Byte1]: 54
2755 12:29:38.011064
2756 12:29:38.011198 Set Vref, RX VrefLevel [Byte0]: 55
2757 12:29:38.014326 [Byte1]: 55
2758 12:29:38.018894
2759 12:29:38.019001 Set Vref, RX VrefLevel [Byte0]: 56
2760 12:29:38.021924 [Byte1]: 56
2761 12:29:38.026862
2762 12:29:38.026967 Set Vref, RX VrefLevel [Byte0]: 57
2763 12:29:38.030094 [Byte1]: 57
2764 12:29:38.034564
2765 12:29:38.034649 Set Vref, RX VrefLevel [Byte0]: 58
2766 12:29:38.037957 [Byte1]: 58
2767 12:29:38.042560
2768 12:29:38.042637 Set Vref, RX VrefLevel [Byte0]: 59
2769 12:29:38.045619 [Byte1]: 59
2770 12:29:38.050289
2771 12:29:38.050408 Set Vref, RX VrefLevel [Byte0]: 60
2772 12:29:38.053735 [Byte1]: 60
2773 12:29:38.058417
2774 12:29:38.058497 Set Vref, RX VrefLevel [Byte0]: 61
2775 12:29:38.061546 [Byte1]: 61
2776 12:29:38.066146
2777 12:29:38.066223 Set Vref, RX VrefLevel [Byte0]: 62
2778 12:29:38.069504 [Byte1]: 62
2779 12:29:38.074184
2780 12:29:38.074260 Set Vref, RX VrefLevel [Byte0]: 63
2781 12:29:38.077461 [Byte1]: 63
2782 12:29:38.082281
2783 12:29:38.082386 Set Vref, RX VrefLevel [Byte0]: 64
2784 12:29:38.085540 [Byte1]: 64
2785 12:29:38.089556
2786 12:29:38.089648 Set Vref, RX VrefLevel [Byte0]: 65
2787 12:29:38.093402 [Byte1]: 65
2788 12:29:38.097883
2789 12:29:38.097964 Set Vref, RX VrefLevel [Byte0]: 66
2790 12:29:38.100951 [Byte1]: 66
2791 12:29:38.105646
2792 12:29:38.105724 Set Vref, RX VrefLevel [Byte0]: 67
2793 12:29:38.109000 [Byte1]: 67
2794 12:29:38.113721
2795 12:29:38.113799 Set Vref, RX VrefLevel [Byte0]: 68
2796 12:29:38.117160 [Byte1]: 68
2797 12:29:38.121703
2798 12:29:38.121780 Set Vref, RX VrefLevel [Byte0]: 69
2799 12:29:38.125001 [Byte1]: 69
2800 12:29:38.129626
2801 12:29:38.129702 Final RX Vref Byte 0 = 54 to rank0
2802 12:29:38.132857 Final RX Vref Byte 1 = 48 to rank0
2803 12:29:38.135990 Final RX Vref Byte 0 = 54 to rank1
2804 12:29:38.139079 Final RX Vref Byte 1 = 48 to rank1==
2805 12:29:38.142989 Dram Type= 6, Freq= 0, CH_0, rank 0
2806 12:29:38.149627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2807 12:29:38.149709 ==
2808 12:29:38.149775 DQS Delay:
2809 12:29:38.149835 DQS0 = 0, DQS1 = 0
2810 12:29:38.152828 DQM Delay:
2811 12:29:38.152907 DQM0 = 120, DQM1 = 112
2812 12:29:38.156183 DQ Delay:
2813 12:29:38.159583 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2814 12:29:38.162841 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2815 12:29:38.166072 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2816 12:29:38.169436 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2817 12:29:38.169523
2818 12:29:38.169621
2819 12:29:38.176277 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2820 12:29:38.179578 CH0 RK0: MR19=404, MR18=140D
2821 12:29:38.186169 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2822 12:29:38.186256
2823 12:29:38.189302 ----->DramcWriteLeveling(PI) begin...
2824 12:29:38.189388 ==
2825 12:29:38.193068 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 12:29:38.196356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 12:29:38.199519 ==
2828 12:29:38.199624 Write leveling (Byte 0): 33 => 33
2829 12:29:38.202678 Write leveling (Byte 1): 30 => 30
2830 12:29:38.206332 DramcWriteLeveling(PI) end<-----
2831 12:29:38.206420
2832 12:29:38.206487 ==
2833 12:29:38.209567 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 12:29:38.216112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 12:29:38.216202 ==
2836 12:29:38.216271 [Gating] SW mode calibration
2837 12:29:38.226443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2838 12:29:38.229496 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2839 12:29:38.232848 0 15 0 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
2840 12:29:38.240108 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 12:29:38.243296 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 12:29:38.246450 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 12:29:38.253103 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 12:29:38.256194 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 12:29:38.259489 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 12:29:38.266203 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (1 0) (1 0)
2847 12:29:38.269918 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2848 12:29:38.273249 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 12:29:38.279390 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 12:29:38.282742 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 12:29:38.286148 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 12:29:38.292766 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 12:29:38.296506 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 12:29:38.299618 1 0 28 | B1->B0 | 3e3e 3f3f | 0 0 | (1 1) (0 0)
2855 12:29:38.302925 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 12:29:38.309932 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 12:29:38.313013 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 12:29:38.316616 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 12:29:38.323297 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 12:29:38.326303 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 12:29:38.330129 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 12:29:38.336618 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2863 12:29:38.339982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:29:38.343384 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:29:38.349747 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:29:38.352817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:29:38.356213 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:29:38.363216 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:29:38.366658 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:29:38.370057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:29:38.376614 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:29:38.379873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:29:38.383198 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:29:38.389880 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:29:38.393234 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:29:38.396619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:29:38.399700 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:29:38.406594 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2879 12:29:38.409810 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2880 12:29:38.413118 Total UI for P1: 0, mck2ui 16
2881 12:29:38.416329 best dqsien dly found for B1: ( 1, 3, 28)
2882 12:29:38.420169 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 12:29:38.423299 Total UI for P1: 0, mck2ui 16
2884 12:29:38.426685 best dqsien dly found for B0: ( 1, 3, 30)
2885 12:29:38.429670 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2886 12:29:38.433452 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2887 12:29:38.433570
2888 12:29:38.439955 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2889 12:29:38.443196 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2890 12:29:38.443298 [Gating] SW calibration Done
2891 12:29:38.446601 ==
2892 12:29:38.450003 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 12:29:38.453262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 12:29:38.453368 ==
2895 12:29:38.453469 RX Vref Scan: 0
2896 12:29:38.453568
2897 12:29:38.456432 RX Vref 0 -> 0, step: 1
2898 12:29:38.456534
2899 12:29:38.459682 RX Delay -40 -> 252, step: 8
2900 12:29:38.463026 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2901 12:29:38.466393 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2902 12:29:38.469590 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2903 12:29:38.476396 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2904 12:29:38.480183 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2905 12:29:38.483542 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2906 12:29:38.487071 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2907 12:29:38.489608 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2908 12:29:38.496418 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2909 12:29:38.499718 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2910 12:29:38.503581 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2911 12:29:38.507080 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2912 12:29:38.509694 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2913 12:29:38.516366 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2914 12:29:38.520090 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2915 12:29:38.523307 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2916 12:29:38.523430 ==
2917 12:29:38.526494 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 12:29:38.529531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 12:29:38.529633 ==
2920 12:29:38.533329 DQS Delay:
2921 12:29:38.533434 DQS0 = 0, DQS1 = 0
2922 12:29:38.536654 DQM Delay:
2923 12:29:38.536735 DQM0 = 122, DQM1 = 112
2924 12:29:38.540014 DQ Delay:
2925 12:29:38.543052 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2926 12:29:38.546319 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2927 12:29:38.549654 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2928 12:29:38.552992 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2929 12:29:38.553094
2930 12:29:38.553194
2931 12:29:38.553292 ==
2932 12:29:38.556326 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 12:29:38.559756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 12:29:38.559835 ==
2935 12:29:38.559919
2936 12:29:38.560018
2937 12:29:38.563011 TX Vref Scan disable
2938 12:29:38.566220 == TX Byte 0 ==
2939 12:29:38.569498 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2940 12:29:38.573309 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2941 12:29:38.576563 == TX Byte 1 ==
2942 12:29:38.579690 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2943 12:29:38.582934 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2944 12:29:38.583040 ==
2945 12:29:38.586255 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 12:29:38.589655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 12:29:38.593041 ==
2948 12:29:38.603084 TX Vref=22, minBit 1, minWin=25, winSum=419
2949 12:29:38.606467 TX Vref=24, minBit 0, minWin=26, winSum=424
2950 12:29:38.609843 TX Vref=26, minBit 0, minWin=26, winSum=425
2951 12:29:38.613194 TX Vref=28, minBit 1, minWin=26, winSum=427
2952 12:29:38.616596 TX Vref=30, minBit 0, minWin=26, winSum=430
2953 12:29:38.623005 TX Vref=32, minBit 0, minWin=26, winSum=423
2954 12:29:38.626929 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 30
2955 12:29:38.627030
2956 12:29:38.630206 Final TX Range 1 Vref 30
2957 12:29:38.630309
2958 12:29:38.630399 ==
2959 12:29:38.633441 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 12:29:38.636756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 12:29:38.636867 ==
2962 12:29:38.636962
2963 12:29:38.639960
2964 12:29:38.640062 TX Vref Scan disable
2965 12:29:38.643084 == TX Byte 0 ==
2966 12:29:38.646557 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2967 12:29:38.650317 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2968 12:29:38.653597 == TX Byte 1 ==
2969 12:29:38.656753 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2970 12:29:38.660175 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2971 12:29:38.660258
2972 12:29:38.663417 [DATLAT]
2973 12:29:38.663500 Freq=1200, CH0 RK1
2974 12:29:38.663566
2975 12:29:38.666688 DATLAT Default: 0xd
2976 12:29:38.666770 0, 0xFFFF, sum = 0
2977 12:29:38.669903 1, 0xFFFF, sum = 0
2978 12:29:38.669988 2, 0xFFFF, sum = 0
2979 12:29:38.673138 3, 0xFFFF, sum = 0
2980 12:29:38.673220 4, 0xFFFF, sum = 0
2981 12:29:38.676802 5, 0xFFFF, sum = 0
2982 12:29:38.676883 6, 0xFFFF, sum = 0
2983 12:29:38.680036 7, 0xFFFF, sum = 0
2984 12:29:38.680115 8, 0xFFFF, sum = 0
2985 12:29:38.683666 9, 0xFFFF, sum = 0
2986 12:29:38.686802 10, 0xFFFF, sum = 0
2987 12:29:38.686885 11, 0xFFFF, sum = 0
2988 12:29:38.690168 12, 0x0, sum = 1
2989 12:29:38.690245 13, 0x0, sum = 2
2990 12:29:38.690311 14, 0x0, sum = 3
2991 12:29:38.693557 15, 0x0, sum = 4
2992 12:29:38.693632 best_step = 13
2993 12:29:38.693696
2994 12:29:38.696929 ==
2995 12:29:38.697000 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 12:29:38.703729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 12:29:38.703815 ==
2998 12:29:38.703882 RX Vref Scan: 0
2999 12:29:38.703943
3000 12:29:38.707097 RX Vref 0 -> 0, step: 1
3001 12:29:38.707168
3002 12:29:38.710333 RX Delay -13 -> 252, step: 4
3003 12:29:38.713583 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3004 12:29:38.716945 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3005 12:29:38.723580 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3006 12:29:38.726875 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3007 12:29:38.730060 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3008 12:29:38.733285 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3009 12:29:38.737188 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3010 12:29:38.743546 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3011 12:29:38.746805 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3012 12:29:38.750468 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3013 12:29:38.753542 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3014 12:29:38.756702 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3015 12:29:38.763714 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3016 12:29:38.767095 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3017 12:29:38.770486 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3018 12:29:38.773805 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3019 12:29:38.773890 ==
3020 12:29:38.776996 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 12:29:38.780146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 12:29:38.783440 ==
3023 12:29:38.783545 DQS Delay:
3024 12:29:38.783610 DQS0 = 0, DQS1 = 0
3025 12:29:38.787195 DQM Delay:
3026 12:29:38.787263 DQM0 = 121, DQM1 = 110
3027 12:29:38.790229 DQ Delay:
3028 12:29:38.793807 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3029 12:29:38.796975 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3030 12:29:38.800162 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3031 12:29:38.803534 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3032 12:29:38.803676
3033 12:29:38.803784
3034 12:29:38.810183 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3035 12:29:38.813432 CH0 RK1: MR19=403, MR18=10F1
3036 12:29:38.820053 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3037 12:29:38.823553 [RxdqsGatingPostProcess] freq 1200
3038 12:29:38.830362 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3039 12:29:38.833773 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 12:29:38.833874 best DQS1 dly(2T, 0.5T) = (0, 12)
3041 12:29:38.836917 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 12:29:38.840818 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3043 12:29:38.844129 best DQS0 dly(2T, 0.5T) = (0, 11)
3044 12:29:38.847446 best DQS1 dly(2T, 0.5T) = (0, 11)
3045 12:29:38.850479 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3046 12:29:38.853659 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3047 12:29:38.857591 Pre-setting of DQS Precalculation
3048 12:29:38.864107 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3049 12:29:38.864804 ==
3050 12:29:38.867733 Dram Type= 6, Freq= 0, CH_1, rank 0
3051 12:29:38.871539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 12:29:38.872061 ==
3053 12:29:38.877678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3054 12:29:38.880666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3055 12:29:38.890342 [CA 0] Center 37 (7~68) winsize 62
3056 12:29:38.893235 [CA 1] Center 37 (7~68) winsize 62
3057 12:29:38.896953 [CA 2] Center 35 (5~65) winsize 61
3058 12:29:38.899922 [CA 3] Center 34 (4~64) winsize 61
3059 12:29:38.903405 [CA 4] Center 34 (5~64) winsize 60
3060 12:29:38.906600 [CA 5] Center 33 (3~63) winsize 61
3061 12:29:38.907025
3062 12:29:38.909917 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3063 12:29:38.910348
3064 12:29:38.913252 [CATrainingPosCal] consider 1 rank data
3065 12:29:38.916486 u2DelayCellTimex100 = 270/100 ps
3066 12:29:38.920325 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3067 12:29:38.923978 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3068 12:29:38.929941 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3069 12:29:38.933219 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3070 12:29:38.936595 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3071 12:29:38.939805 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3072 12:29:38.940234
3073 12:29:38.943740 CA PerBit enable=1, Macro0, CA PI delay=33
3074 12:29:38.944165
3075 12:29:38.946989 [CBTSetCACLKResult] CA Dly = 33
3076 12:29:38.947454 CS Dly: 8 (0~39)
3077 12:29:38.947801 ==
3078 12:29:38.949904 Dram Type= 6, Freq= 0, CH_1, rank 1
3079 12:29:38.957012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 12:29:38.957461 ==
3081 12:29:38.960052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3082 12:29:38.966883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3083 12:29:38.975879 [CA 0] Center 37 (7~68) winsize 62
3084 12:29:38.979259 [CA 1] Center 38 (8~68) winsize 61
3085 12:29:38.982738 [CA 2] Center 35 (5~65) winsize 61
3086 12:29:38.986041 [CA 3] Center 34 (4~65) winsize 62
3087 12:29:38.989353 [CA 4] Center 34 (4~65) winsize 62
3088 12:29:38.992598 [CA 5] Center 34 (4~64) winsize 61
3089 12:29:38.993048
3090 12:29:38.995835 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3091 12:29:38.996262
3092 12:29:38.999202 [CATrainingPosCal] consider 2 rank data
3093 12:29:39.002588 u2DelayCellTimex100 = 270/100 ps
3094 12:29:39.005807 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 12:29:39.009121 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3096 12:29:39.015682 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3097 12:29:39.018960 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 12:29:39.022352 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3099 12:29:39.026162 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3100 12:29:39.026797
3101 12:29:39.029429 CA PerBit enable=1, Macro0, CA PI delay=33
3102 12:29:39.030020
3103 12:29:39.032329 [CBTSetCACLKResult] CA Dly = 33
3104 12:29:39.033015 CS Dly: 8 (0~40)
3105 12:29:39.033390
3106 12:29:39.035641 ----->DramcWriteLeveling(PI) begin...
3107 12:29:39.039145 ==
3108 12:29:39.042452 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 12:29:39.045919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 12:29:39.046343 ==
3111 12:29:39.049212 Write leveling (Byte 0): 27 => 27
3112 12:29:39.052540 Write leveling (Byte 1): 27 => 27
3113 12:29:39.052970 DramcWriteLeveling(PI) end<-----
3114 12:29:39.055818
3115 12:29:39.056243 ==
3116 12:29:39.059008 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 12:29:39.062674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 12:29:39.063101 ==
3119 12:29:39.065749 [Gating] SW mode calibration
3120 12:29:39.072573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3121 12:29:39.075888 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3122 12:29:39.082850 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 12:29:39.086185 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 12:29:39.090045 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 12:29:39.096304 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 12:29:39.099463 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 12:29:39.102486 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 12:29:39.109583 0 15 24 | B1->B0 | 3333 2d2d | 0 1 | (0 1) (1 0)
3129 12:29:39.112754 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3130 12:29:39.115949 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 12:29:39.122936 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 12:29:39.126281 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 12:29:39.129606 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 12:29:39.135868 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 12:29:39.139211 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 12:29:39.142541 1 0 24 | B1->B0 | 2b2b 3737 | 1 0 | (0 0) (0 0)
3137 12:29:39.146082 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 12:29:39.152748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 12:29:39.156063 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 12:29:39.159312 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 12:29:39.165659 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 12:29:39.169362 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 12:29:39.172895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3144 12:29:39.179237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3145 12:29:39.183106 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3146 12:29:39.186387 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:29:39.192452 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:29:39.196414 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:29:39.199756 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:29:39.205934 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:29:39.209447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:29:39.212841 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:29:39.219648 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:29:39.223006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:29:39.225956 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:29:39.229165 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:29:39.236037 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:29:39.239319 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:29:39.242703 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:29:39.249608 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3161 12:29:39.253136 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3162 12:29:39.256542 Total UI for P1: 0, mck2ui 16
3163 12:29:39.259788 best dqsien dly found for B0: ( 1, 3, 24)
3164 12:29:39.262868 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:29:39.266288 Total UI for P1: 0, mck2ui 16
3166 12:29:39.269559 best dqsien dly found for B1: ( 1, 3, 26)
3167 12:29:39.272780 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3168 12:29:39.276500 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3169 12:29:39.276931
3170 12:29:39.279664 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3171 12:29:39.286606 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3172 12:29:39.287039 [Gating] SW calibration Done
3173 12:29:39.287443 ==
3174 12:29:39.289683 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 12:29:39.296129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 12:29:39.296580 ==
3177 12:29:39.297149 RX Vref Scan: 0
3178 12:29:39.297637
3179 12:29:39.300089 RX Vref 0 -> 0, step: 1
3180 12:29:39.300520
3181 12:29:39.303274 RX Delay -40 -> 252, step: 8
3182 12:29:39.306700 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3183 12:29:39.309543 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3184 12:29:39.312829 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3185 12:29:39.319550 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3186 12:29:39.323250 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3187 12:29:39.326317 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3188 12:29:39.329537 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3189 12:29:39.332766 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3190 12:29:39.339803 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3191 12:29:39.343062 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3192 12:29:39.346351 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3193 12:29:39.349541 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3194 12:29:39.353341 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3195 12:29:39.359872 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3196 12:29:39.363318 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3197 12:29:39.366760 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3198 12:29:39.367193 ==
3199 12:29:39.369483 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 12:29:39.373532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 12:29:39.374025 ==
3202 12:29:39.376841 DQS Delay:
3203 12:29:39.377291 DQS0 = 0, DQS1 = 0
3204 12:29:39.377696 DQM Delay:
3205 12:29:39.379575 DQM0 = 120, DQM1 = 116
3206 12:29:39.380005 DQ Delay:
3207 12:29:39.383367 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3208 12:29:39.386565 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3209 12:29:39.393486 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3210 12:29:39.396412 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3211 12:29:39.397003
3212 12:29:39.397520
3213 12:29:39.398047 ==
3214 12:29:39.399808 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 12:29:39.403471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 12:29:39.403968 ==
3217 12:29:39.404384
3218 12:29:39.404733
3219 12:29:39.406676 TX Vref Scan disable
3220 12:29:39.407162 == TX Byte 0 ==
3221 12:29:39.413450 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3222 12:29:39.416837 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3223 12:29:39.417237 == TX Byte 1 ==
3224 12:29:39.423550 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3225 12:29:39.426907 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3226 12:29:39.427498 ==
3227 12:29:39.430068 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 12:29:39.433829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 12:29:39.434425 ==
3230 12:29:39.445965 TX Vref=22, minBit 1, minWin=25, winSum=414
3231 12:29:39.449167 TX Vref=24, minBit 9, minWin=25, winSum=420
3232 12:29:39.452678 TX Vref=26, minBit 9, minWin=25, winSum=422
3233 12:29:39.455943 TX Vref=28, minBit 9, minWin=25, winSum=427
3234 12:29:39.459322 TX Vref=30, minBit 9, minWin=25, winSum=430
3235 12:29:39.462808 TX Vref=32, minBit 11, minWin=25, winSum=427
3236 12:29:39.469398 [TxChooseVref] Worse bit 9, Min win 25, Win sum 430, Final Vref 30
3237 12:29:39.469890
3238 12:29:39.472715 Final TX Range 1 Vref 30
3239 12:29:39.473138
3240 12:29:39.473468 ==
3241 12:29:39.476063 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 12:29:39.479401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 12:29:39.479828 ==
3244 12:29:39.480164
3245 12:29:39.480486
3246 12:29:39.482642 TX Vref Scan disable
3247 12:29:39.486047 == TX Byte 0 ==
3248 12:29:39.489281 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3249 12:29:39.492867 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3250 12:29:39.495945 == TX Byte 1 ==
3251 12:29:39.499737 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3252 12:29:39.502684 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3253 12:29:39.503301
3254 12:29:39.506354 [DATLAT]
3255 12:29:39.506787 Freq=1200, CH1 RK0
3256 12:29:39.507124
3257 12:29:39.509629 DATLAT Default: 0xd
3258 12:29:39.510051 0, 0xFFFF, sum = 0
3259 12:29:39.512562 1, 0xFFFF, sum = 0
3260 12:29:39.512651 2, 0xFFFF, sum = 0
3261 12:29:39.516027 3, 0xFFFF, sum = 0
3262 12:29:39.516112 4, 0xFFFF, sum = 0
3263 12:29:39.519243 5, 0xFFFF, sum = 0
3264 12:29:39.519333 6, 0xFFFF, sum = 0
3265 12:29:39.522697 7, 0xFFFF, sum = 0
3266 12:29:39.522781 8, 0xFFFF, sum = 0
3267 12:29:39.525939 9, 0xFFFF, sum = 0
3268 12:29:39.526022 10, 0xFFFF, sum = 0
3269 12:29:39.529313 11, 0xFFFF, sum = 0
3270 12:29:39.529397 12, 0x0, sum = 1
3271 12:29:39.532779 13, 0x0, sum = 2
3272 12:29:39.532863 14, 0x0, sum = 3
3273 12:29:39.535306 15, 0x0, sum = 4
3274 12:29:39.535428 best_step = 13
3275 12:29:39.535495
3276 12:29:39.535555 ==
3277 12:29:39.539208 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 12:29:39.545602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 12:29:39.545687 ==
3280 12:29:39.545753 RX Vref Scan: 1
3281 12:29:39.545814
3282 12:29:39.548772 Set Vref Range= 32 -> 127
3283 12:29:39.548855
3284 12:29:39.552390 RX Vref 32 -> 127, step: 1
3285 12:29:39.552473
3286 12:29:39.555502 RX Delay -5 -> 252, step: 4
3287 12:29:39.555585
3288 12:29:39.558803 Set Vref, RX VrefLevel [Byte0]: 32
3289 12:29:39.562100 [Byte1]: 32
3290 12:29:39.562183
3291 12:29:39.565547 Set Vref, RX VrefLevel [Byte0]: 33
3292 12:29:39.569070 [Byte1]: 33
3293 12:29:39.569151
3294 12:29:39.572183 Set Vref, RX VrefLevel [Byte0]: 34
3295 12:29:39.575552 [Byte1]: 34
3296 12:29:39.579566
3297 12:29:39.579647 Set Vref, RX VrefLevel [Byte0]: 35
3298 12:29:39.582867 [Byte1]: 35
3299 12:29:39.586875
3300 12:29:39.586956 Set Vref, RX VrefLevel [Byte0]: 36
3301 12:29:39.590289 [Byte1]: 36
3302 12:29:39.594902
3303 12:29:39.594983 Set Vref, RX VrefLevel [Byte0]: 37
3304 12:29:39.598280 [Byte1]: 37
3305 12:29:39.602795
3306 12:29:39.602876 Set Vref, RX VrefLevel [Byte0]: 38
3307 12:29:39.606078 [Byte1]: 38
3308 12:29:39.611035
3309 12:29:39.611116 Set Vref, RX VrefLevel [Byte0]: 39
3310 12:29:39.614167 [Byte1]: 39
3311 12:29:39.618567
3312 12:29:39.618647 Set Vref, RX VrefLevel [Byte0]: 40
3313 12:29:39.621686 [Byte1]: 40
3314 12:29:39.626676
3315 12:29:39.626757 Set Vref, RX VrefLevel [Byte0]: 41
3316 12:29:39.630025 [Byte1]: 41
3317 12:29:39.634118
3318 12:29:39.634199 Set Vref, RX VrefLevel [Byte0]: 42
3319 12:29:39.637483 [Byte1]: 42
3320 12:29:39.642122
3321 12:29:39.642203 Set Vref, RX VrefLevel [Byte0]: 43
3322 12:29:39.645217 [Byte1]: 43
3323 12:29:39.649896
3324 12:29:39.649977 Set Vref, RX VrefLevel [Byte0]: 44
3325 12:29:39.653083 [Byte1]: 44
3326 12:29:39.657707
3327 12:29:39.657787 Set Vref, RX VrefLevel [Byte0]: 45
3328 12:29:39.661021 [Byte1]: 45
3329 12:29:39.665892
3330 12:29:39.665972 Set Vref, RX VrefLevel [Byte0]: 46
3331 12:29:39.669191 [Byte1]: 46
3332 12:29:39.673308
3333 12:29:39.673389 Set Vref, RX VrefLevel [Byte0]: 47
3334 12:29:39.676548 [Byte1]: 47
3335 12:29:39.681168
3336 12:29:39.681248 Set Vref, RX VrefLevel [Byte0]: 48
3337 12:29:39.684537 [Byte1]: 48
3338 12:29:39.689143
3339 12:29:39.689227 Set Vref, RX VrefLevel [Byte0]: 49
3340 12:29:39.692526 [Byte1]: 49
3341 12:29:39.697118
3342 12:29:39.697198 Set Vref, RX VrefLevel [Byte0]: 50
3343 12:29:39.703648 [Byte1]: 50
3344 12:29:39.703729
3345 12:29:39.707047 Set Vref, RX VrefLevel [Byte0]: 51
3346 12:29:39.710309 [Byte1]: 51
3347 12:29:39.710390
3348 12:29:39.713389 Set Vref, RX VrefLevel [Byte0]: 52
3349 12:29:39.717068 [Byte1]: 52
3350 12:29:39.720916
3351 12:29:39.720996 Set Vref, RX VrefLevel [Byte0]: 53
3352 12:29:39.724082 [Byte1]: 53
3353 12:29:39.728396
3354 12:29:39.728477 Set Vref, RX VrefLevel [Byte0]: 54
3355 12:29:39.731606 [Byte1]: 54
3356 12:29:39.736686
3357 12:29:39.736767 Set Vref, RX VrefLevel [Byte0]: 55
3358 12:29:39.739365 [Byte1]: 55
3359 12:29:39.744043
3360 12:29:39.744124 Set Vref, RX VrefLevel [Byte0]: 56
3361 12:29:39.747281 [Byte1]: 56
3362 12:29:39.751899
3363 12:29:39.751981 Set Vref, RX VrefLevel [Byte0]: 57
3364 12:29:39.755184 [Byte1]: 57
3365 12:29:39.759703
3366 12:29:39.759785 Set Vref, RX VrefLevel [Byte0]: 58
3367 12:29:39.762935 [Byte1]: 58
3368 12:29:39.767602
3369 12:29:39.767683 Set Vref, RX VrefLevel [Byte0]: 59
3370 12:29:39.770765 [Byte1]: 59
3371 12:29:39.775712
3372 12:29:39.775792 Set Vref, RX VrefLevel [Byte0]: 60
3373 12:29:39.779011 [Byte1]: 60
3374 12:29:39.783206
3375 12:29:39.783303 Set Vref, RX VrefLevel [Byte0]: 61
3376 12:29:39.786547 [Byte1]: 61
3377 12:29:39.791117
3378 12:29:39.791198 Set Vref, RX VrefLevel [Byte0]: 62
3379 12:29:39.794559 [Byte1]: 62
3380 12:29:39.799229
3381 12:29:39.802531 Set Vref, RX VrefLevel [Byte0]: 63
3382 12:29:39.805724 [Byte1]: 63
3383 12:29:39.805806
3384 12:29:39.809163 Set Vref, RX VrefLevel [Byte0]: 64
3385 12:29:39.812406 [Byte1]: 64
3386 12:29:39.812488
3387 12:29:39.815774 Set Vref, RX VrefLevel [Byte0]: 65
3388 12:29:39.819012 [Byte1]: 65
3389 12:29:39.822662
3390 12:29:39.822743 Set Vref, RX VrefLevel [Byte0]: 66
3391 12:29:39.825867 [Byte1]: 66
3392 12:29:39.830333
3393 12:29:39.830414 Set Vref, RX VrefLevel [Byte0]: 67
3394 12:29:39.834062 [Byte1]: 67
3395 12:29:39.838617
3396 12:29:39.838705 Set Vref, RX VrefLevel [Byte0]: 68
3397 12:29:39.841693 [Byte1]: 68
3398 12:29:39.846410
3399 12:29:39.846494 Final RX Vref Byte 0 = 53 to rank0
3400 12:29:39.849481 Final RX Vref Byte 1 = 52 to rank0
3401 12:29:39.852645 Final RX Vref Byte 0 = 53 to rank1
3402 12:29:39.856034 Final RX Vref Byte 1 = 52 to rank1==
3403 12:29:39.859488 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 12:29:39.866112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 12:29:39.866197 ==
3406 12:29:39.866265 DQS Delay:
3407 12:29:39.866324 DQS0 = 0, DQS1 = 0
3408 12:29:39.869229 DQM Delay:
3409 12:29:39.869312 DQM0 = 119, DQM1 = 117
3410 12:29:39.872564 DQ Delay:
3411 12:29:39.876501 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =114
3412 12:29:39.879695 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3413 12:29:39.882966 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3414 12:29:39.886135 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3415 12:29:39.886219
3416 12:29:39.886285
3417 12:29:39.892641 [DQSOSCAuto] RK0, (LSB)MR18= 0x12, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3418 12:29:39.895886 CH1 RK0: MR19=404, MR18=12
3419 12:29:39.902563 CH1_RK0: MR19=0x404, MR18=0x12, DQSOSC=403, MR23=63, INC=40, DEC=26
3420 12:29:39.902648
3421 12:29:39.905987 ----->DramcWriteLeveling(PI) begin...
3422 12:29:39.906072 ==
3423 12:29:39.909381 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 12:29:39.912686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 12:29:39.912770 ==
3426 12:29:39.916043 Write leveling (Byte 0): 25 => 25
3427 12:29:39.919404 Write leveling (Byte 1): 27 => 27
3428 12:29:39.922765 DramcWriteLeveling(PI) end<-----
3429 12:29:39.922849
3430 12:29:39.922915 ==
3431 12:29:39.925906 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 12:29:39.929168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 12:29:39.933106 ==
3434 12:29:39.933189 [Gating] SW mode calibration
3435 12:29:39.942737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 12:29:39.946065 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 12:29:39.949879 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 12:29:39.956244 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 12:29:39.959593 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 12:29:39.962959 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 12:29:39.969513 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 12:29:39.972742 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3443 12:29:39.976018 0 15 24 | B1->B0 | 2f2f 3434 | 0 0 | (1 0) (0 1)
3444 12:29:39.983185 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 12:29:39.986405 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 12:29:39.989800 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 12:29:39.996139 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 12:29:39.999632 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 12:29:40.002996 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 12:29:40.006428 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
3451 12:29:40.013162 1 0 24 | B1->B0 | 3e3e 2525 | 1 0 | (0 0) (0 0)
3452 12:29:40.015886 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 12:29:40.019276 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 12:29:40.026036 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 12:29:40.029228 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 12:29:40.032696 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 12:29:40.039708 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 12:29:40.042901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3459 12:29:40.046165 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3460 12:29:40.052650 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3461 12:29:40.056486 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:29:40.059634 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:29:40.066382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:29:40.069701 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:29:40.072924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:29:40.079585 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:29:40.082827 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:29:40.086058 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:29:40.092539 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:29:40.095826 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:29:40.098984 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:29:40.106250 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:29:40.109508 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:29:40.112821 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3475 12:29:40.119253 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 12:29:40.122687 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3477 12:29:40.126152 Total UI for P1: 0, mck2ui 16
3478 12:29:40.128861 best dqsien dly found for B1: ( 1, 3, 22)
3479 12:29:40.132185 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 12:29:40.135557 Total UI for P1: 0, mck2ui 16
3481 12:29:40.138843 best dqsien dly found for B0: ( 1, 3, 26)
3482 12:29:40.142205 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 12:29:40.145930 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3484 12:29:40.146014
3485 12:29:40.149268 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 12:29:40.155589 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3487 12:29:40.155672 [Gating] SW calibration Done
3488 12:29:40.155738 ==
3489 12:29:40.159245 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 12:29:40.165567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 12:29:40.165651 ==
3492 12:29:40.165716 RX Vref Scan: 0
3493 12:29:40.165777
3494 12:29:40.169179 RX Vref 0 -> 0, step: 1
3495 12:29:40.169260
3496 12:29:40.172358 RX Delay -40 -> 252, step: 8
3497 12:29:40.175625 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3498 12:29:40.179047 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3499 12:29:40.182202 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3500 12:29:40.186197 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3501 12:29:40.192154 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3502 12:29:40.195566 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 12:29:40.198922 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3504 12:29:40.202376 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3505 12:29:40.205628 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3506 12:29:40.212423 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3507 12:29:40.215798 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3508 12:29:40.219201 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3509 12:29:40.222376 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3510 12:29:40.229082 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3511 12:29:40.232398 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3512 12:29:40.235713 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3513 12:29:40.235795 ==
3514 12:29:40.238938 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 12:29:40.242310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 12:29:40.242396 ==
3517 12:29:40.245679 DQS Delay:
3518 12:29:40.245763 DQS0 = 0, DQS1 = 0
3519 12:29:40.249073 DQM Delay:
3520 12:29:40.249170 DQM0 = 120, DQM1 = 118
3521 12:29:40.249236 DQ Delay:
3522 12:29:40.252231 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =115
3523 12:29:40.259005 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3524 12:29:40.262127 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3525 12:29:40.265414 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3526 12:29:40.265498
3527 12:29:40.265563
3528 12:29:40.265624 ==
3529 12:29:40.268611 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 12:29:40.271879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 12:29:40.271963 ==
3532 12:29:40.272029
3533 12:29:40.272089
3534 12:29:40.275550 TX Vref Scan disable
3535 12:29:40.278748 == TX Byte 0 ==
3536 12:29:40.282178 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3537 12:29:40.285414 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3538 12:29:40.288447 == TX Byte 1 ==
3539 12:29:40.292387 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3540 12:29:40.295543 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3541 12:29:40.295659 ==
3542 12:29:40.298735 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 12:29:40.302224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 12:29:40.304972 ==
3545 12:29:40.314915 TX Vref=22, minBit 9, minWin=25, winSum=420
3546 12:29:40.318238 TX Vref=24, minBit 2, minWin=26, winSum=424
3547 12:29:40.322173 TX Vref=26, minBit 2, minWin=26, winSum=427
3548 12:29:40.324893 TX Vref=28, minBit 10, minWin=25, winSum=433
3549 12:29:40.328165 TX Vref=30, minBit 9, minWin=26, winSum=435
3550 12:29:40.335079 TX Vref=32, minBit 9, minWin=26, winSum=433
3551 12:29:40.338392 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3552 12:29:40.338497
3553 12:29:40.341519 Final TX Range 1 Vref 30
3554 12:29:40.341633
3555 12:29:40.341722 ==
3556 12:29:40.345280 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 12:29:40.348591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 12:29:40.348767 ==
3559 12:29:40.351283
3560 12:29:40.351487
3561 12:29:40.351665 TX Vref Scan disable
3562 12:29:40.354675 == TX Byte 0 ==
3563 12:29:40.357848 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3564 12:29:40.364718 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3565 12:29:40.364949 == TX Byte 1 ==
3566 12:29:40.367871 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3567 12:29:40.374822 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3568 12:29:40.375193
3569 12:29:40.375480 [DATLAT]
3570 12:29:40.375667 Freq=1200, CH1 RK1
3571 12:29:40.375843
3572 12:29:40.378124 DATLAT Default: 0xd
3573 12:29:40.378423 0, 0xFFFF, sum = 0
3574 12:29:40.381150 1, 0xFFFF, sum = 0
3575 12:29:40.385080 2, 0xFFFF, sum = 0
3576 12:29:40.385532 3, 0xFFFF, sum = 0
3577 12:29:40.388370 4, 0xFFFF, sum = 0
3578 12:29:40.388798 5, 0xFFFF, sum = 0
3579 12:29:40.391580 6, 0xFFFF, sum = 0
3580 12:29:40.392013 7, 0xFFFF, sum = 0
3581 12:29:40.394898 8, 0xFFFF, sum = 0
3582 12:29:40.395363 9, 0xFFFF, sum = 0
3583 12:29:40.398030 10, 0xFFFF, sum = 0
3584 12:29:40.398458 11, 0xFFFF, sum = 0
3585 12:29:40.401196 12, 0x0, sum = 1
3586 12:29:40.401625 13, 0x0, sum = 2
3587 12:29:40.405175 14, 0x0, sum = 3
3588 12:29:40.405657 15, 0x0, sum = 4
3589 12:29:40.407991 best_step = 13
3590 12:29:40.408430
3591 12:29:40.408883 ==
3592 12:29:40.411256 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 12:29:40.414710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 12:29:40.415157 ==
3595 12:29:40.415634 RX Vref Scan: 0
3596 12:29:40.415960
3597 12:29:40.418086 RX Vref 0 -> 0, step: 1
3598 12:29:40.418520
3599 12:29:40.421197 RX Delay -5 -> 252, step: 4
3600 12:29:40.424398 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3601 12:29:40.431634 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3602 12:29:40.434893 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3603 12:29:40.437592 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3604 12:29:40.441042 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3605 12:29:40.444862 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3606 12:29:40.451319 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3607 12:29:40.454919 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3608 12:29:40.458175 iDelay=195, Bit 8, Center 108 (47 ~ 170) 124
3609 12:29:40.461484 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3610 12:29:40.464792 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3611 12:29:40.471057 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3612 12:29:40.474808 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3613 12:29:40.477837 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3614 12:29:40.480942 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3615 12:29:40.487788 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3616 12:29:40.488448 ==
3617 12:29:40.491533 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 12:29:40.494426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 12:29:40.494533 ==
3620 12:29:40.494632 DQS Delay:
3621 12:29:40.497663 DQS0 = 0, DQS1 = 0
3622 12:29:40.497766 DQM Delay:
3623 12:29:40.500911 DQM0 = 120, DQM1 = 118
3624 12:29:40.500997 DQ Delay:
3625 12:29:40.504148 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3626 12:29:40.507377 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3627 12:29:40.510774 DQ8 =108, DQ9 =108, DQ10 =118, DQ11 =112
3628 12:29:40.514183 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3629 12:29:40.514269
3630 12:29:40.514337
3631 12:29:40.523575 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3632 12:29:40.526976 CH1 RK1: MR19=403, MR18=12EF
3633 12:29:40.533942 CH1_RK1: MR19=0x403, MR18=0x12EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3634 12:29:40.534057 [RxdqsGatingPostProcess] freq 1200
3635 12:29:40.540452 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 12:29:40.543892 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 12:29:40.547310 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 12:29:40.550463 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 12:29:40.553587 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 12:29:40.556871 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 12:29:40.560261 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 12:29:40.563564 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 12:29:40.566966 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 12:29:40.570359 Pre-setting of DQS Precalculation
3645 12:29:40.573616 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 12:29:40.580494 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 12:29:40.587019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 12:29:40.587102
3649 12:29:40.590114
3650 12:29:40.590189 [Calibration Summary] 2400 Mbps
3651 12:29:40.593343 CH 0, Rank 0
3652 12:29:40.593422 SW Impedance : PASS
3653 12:29:40.597077 DUTY Scan : NO K
3654 12:29:40.600275 ZQ Calibration : PASS
3655 12:29:40.600351 Jitter Meter : NO K
3656 12:29:40.603552 CBT Training : PASS
3657 12:29:40.606813 Write leveling : PASS
3658 12:29:40.606895 RX DQS gating : PASS
3659 12:29:40.610559 RX DQ/DQS(RDDQC) : PASS
3660 12:29:40.613891 TX DQ/DQS : PASS
3661 12:29:40.613970 RX DATLAT : PASS
3662 12:29:40.616575 RX DQ/DQS(Engine): PASS
3663 12:29:40.619908 TX OE : NO K
3664 12:29:40.619984 All Pass.
3665 12:29:40.620046
3666 12:29:40.620108 CH 0, Rank 1
3667 12:29:40.623176 SW Impedance : PASS
3668 12:29:40.627088 DUTY Scan : NO K
3669 12:29:40.627168 ZQ Calibration : PASS
3670 12:29:40.630303 Jitter Meter : NO K
3671 12:29:40.630380 CBT Training : PASS
3672 12:29:40.633619 Write leveling : PASS
3673 12:29:40.636987 RX DQS gating : PASS
3674 12:29:40.637066 RX DQ/DQS(RDDQC) : PASS
3675 12:29:40.640143 TX DQ/DQS : PASS
3676 12:29:40.643238 RX DATLAT : PASS
3677 12:29:40.643316 RX DQ/DQS(Engine): PASS
3678 12:29:40.646540 TX OE : NO K
3679 12:29:40.646619 All Pass.
3680 12:29:40.646682
3681 12:29:40.649874 CH 1, Rank 0
3682 12:29:40.649949 SW Impedance : PASS
3683 12:29:40.653298 DUTY Scan : NO K
3684 12:29:40.656402 ZQ Calibration : PASS
3685 12:29:40.656487 Jitter Meter : NO K
3686 12:29:40.659747 CBT Training : PASS
3687 12:29:40.663103 Write leveling : PASS
3688 12:29:40.663184 RX DQS gating : PASS
3689 12:29:40.666581 RX DQ/DQS(RDDQC) : PASS
3690 12:29:40.669938 TX DQ/DQS : PASS
3691 12:29:40.670013 RX DATLAT : PASS
3692 12:29:40.673443 RX DQ/DQS(Engine): PASS
3693 12:29:40.676721 TX OE : NO K
3694 12:29:40.676795 All Pass.
3695 12:29:40.676860
3696 12:29:40.676920 CH 1, Rank 1
3697 12:29:40.679852 SW Impedance : PASS
3698 12:29:40.679929 DUTY Scan : NO K
3699 12:29:40.683505 ZQ Calibration : PASS
3700 12:29:40.686810 Jitter Meter : NO K
3701 12:29:40.686887 CBT Training : PASS
3702 12:29:40.690007 Write leveling : PASS
3703 12:29:40.693344 RX DQS gating : PASS
3704 12:29:40.693425 RX DQ/DQS(RDDQC) : PASS
3705 12:29:40.696517 TX DQ/DQS : PASS
3706 12:29:40.699759 RX DATLAT : PASS
3707 12:29:40.699847 RX DQ/DQS(Engine): PASS
3708 12:29:40.703591 TX OE : NO K
3709 12:29:40.703673 All Pass.
3710 12:29:40.703739
3711 12:29:40.706868 DramC Write-DBI off
3712 12:29:40.710156 PER_BANK_REFRESH: Hybrid Mode
3713 12:29:40.710231 TX_TRACKING: ON
3714 12:29:40.719845 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 12:29:40.723165 [FAST_K] Save calibration result to emmc
3716 12:29:40.726510 dramc_set_vcore_voltage set vcore to 650000
3717 12:29:40.729871 Read voltage for 600, 5
3718 12:29:40.729947 Vio18 = 0
3719 12:29:40.730011 Vcore = 650000
3720 12:29:40.732981 Vdram = 0
3721 12:29:40.733056 Vddq = 0
3722 12:29:40.733122 Vmddr = 0
3723 12:29:40.739903 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 12:29:40.743106 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 12:29:40.746283 MEM_TYPE=3, freq_sel=19
3726 12:29:40.749967 sv_algorithm_assistance_LP4_1600
3727 12:29:40.753094 ============ PULL DRAM RESETB DOWN ============
3728 12:29:40.756532 ========== PULL DRAM RESETB DOWN end =========
3729 12:29:40.763115 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 12:29:40.766447 ===================================
3731 12:29:40.769792 LPDDR4 DRAM CONFIGURATION
3732 12:29:40.773088 ===================================
3733 12:29:40.773164 EX_ROW_EN[0] = 0x0
3734 12:29:40.776499 EX_ROW_EN[1] = 0x0
3735 12:29:40.776573 LP4Y_EN = 0x0
3736 12:29:40.779909 WORK_FSP = 0x0
3737 12:29:40.779982 WL = 0x2
3738 12:29:40.783188 RL = 0x2
3739 12:29:40.783266 BL = 0x2
3740 12:29:40.786374 RPST = 0x0
3741 12:29:40.786450 RD_PRE = 0x0
3742 12:29:40.789455 WR_PRE = 0x1
3743 12:29:40.789531 WR_PST = 0x0
3744 12:29:40.793391 DBI_WR = 0x0
3745 12:29:40.793473 DBI_RD = 0x0
3746 12:29:40.796557 OTF = 0x1
3747 12:29:40.799744 ===================================
3748 12:29:40.802788 ===================================
3749 12:29:40.802876 ANA top config
3750 12:29:40.806113 ===================================
3751 12:29:40.809834 DLL_ASYNC_EN = 0
3752 12:29:40.812942 ALL_SLAVE_EN = 1
3753 12:29:40.816225 NEW_RANK_MODE = 1
3754 12:29:40.816318 DLL_IDLE_MODE = 1
3755 12:29:40.819465 LP45_APHY_COMB_EN = 1
3756 12:29:40.823104 TX_ODT_DIS = 1
3757 12:29:40.826545 NEW_8X_MODE = 1
3758 12:29:40.829784 ===================================
3759 12:29:40.833147 ===================================
3760 12:29:40.836466 data_rate = 1200
3761 12:29:40.836568 CKR = 1
3762 12:29:40.839714 DQ_P2S_RATIO = 8
3763 12:29:40.843078 ===================================
3764 12:29:40.846487 CA_P2S_RATIO = 8
3765 12:29:40.849965 DQ_CA_OPEN = 0
3766 12:29:40.853135 DQ_SEMI_OPEN = 0
3767 12:29:40.856370 CA_SEMI_OPEN = 0
3768 12:29:40.856484 CA_FULL_RATE = 0
3769 12:29:40.859602 DQ_CKDIV4_EN = 1
3770 12:29:40.862820 CA_CKDIV4_EN = 1
3771 12:29:40.866428 CA_PREDIV_EN = 0
3772 12:29:40.869647 PH8_DLY = 0
3773 12:29:40.873035 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 12:29:40.873139 DQ_AAMCK_DIV = 4
3775 12:29:40.876428 CA_AAMCK_DIV = 4
3776 12:29:40.879171 CA_ADMCK_DIV = 4
3777 12:29:40.882602 DQ_TRACK_CA_EN = 0
3778 12:29:40.885928 CA_PICK = 600
3779 12:29:40.889321 CA_MCKIO = 600
3780 12:29:40.889403 MCKIO_SEMI = 0
3781 12:29:40.892569 PLL_FREQ = 2288
3782 12:29:40.896294 DQ_UI_PI_RATIO = 32
3783 12:29:40.899539 CA_UI_PI_RATIO = 0
3784 12:29:40.902529 ===================================
3785 12:29:40.906179 ===================================
3786 12:29:40.909480 memory_type:LPDDR4
3787 12:29:40.909562 GP_NUM : 10
3788 12:29:40.912646 SRAM_EN : 1
3789 12:29:40.915834 MD32_EN : 0
3790 12:29:40.919701 ===================================
3791 12:29:40.919785 [ANA_INIT] >>>>>>>>>>>>>>
3792 12:29:40.923056 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 12:29:40.926179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 12:29:40.929343 ===================================
3795 12:29:40.932664 data_rate = 1200,PCW = 0X5800
3796 12:29:40.935943 ===================================
3797 12:29:40.939311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 12:29:40.945933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 12:29:40.949285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 12:29:40.956039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 12:29:40.959245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 12:29:40.962571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 12:29:40.962657 [ANA_INIT] flow start
3804 12:29:40.965662 [ANA_INIT] PLL >>>>>>>>
3805 12:29:40.968892 [ANA_INIT] PLL <<<<<<<<
3806 12:29:40.972554 [ANA_INIT] MIDPI >>>>>>>>
3807 12:29:40.972637 [ANA_INIT] MIDPI <<<<<<<<
3808 12:29:40.975779 [ANA_INIT] DLL >>>>>>>>
3809 12:29:40.975862 [ANA_INIT] flow end
3810 12:29:40.982459 ============ LP4 DIFF to SE enter ============
3811 12:29:40.985740 ============ LP4 DIFF to SE exit ============
3812 12:29:40.989200 [ANA_INIT] <<<<<<<<<<<<<
3813 12:29:40.992600 [Flow] Enable top DCM control >>>>>
3814 12:29:40.995874 [Flow] Enable top DCM control <<<<<
3815 12:29:40.999208 Enable DLL master slave shuffle
3816 12:29:41.002463 ==============================================================
3817 12:29:41.005451 Gating Mode config
3818 12:29:41.008592 ==============================================================
3819 12:29:41.012372 Config description:
3820 12:29:41.022278 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 12:29:41.028484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 12:29:41.032450 SELPH_MODE 0: By rank 1: By Phase
3823 12:29:41.038634 ==============================================================
3824 12:29:41.041866 GAT_TRACK_EN = 1
3825 12:29:41.045252 RX_GATING_MODE = 2
3826 12:29:41.048649 RX_GATING_TRACK_MODE = 2
3827 12:29:41.051947 SELPH_MODE = 1
3828 12:29:41.055795 PICG_EARLY_EN = 1
3829 12:29:41.055895 VALID_LAT_VALUE = 1
3830 12:29:41.062406 ==============================================================
3831 12:29:41.065070 Enter into Gating configuration >>>>
3832 12:29:41.068434 Exit from Gating configuration <<<<
3833 12:29:41.072314 Enter into DVFS_PRE_config >>>>>
3834 12:29:41.081986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 12:29:41.085496 Exit from DVFS_PRE_config <<<<<
3836 12:29:41.088778 Enter into PICG configuration >>>>
3837 12:29:41.092195 Exit from PICG configuration <<<<
3838 12:29:41.095337 [RX_INPUT] configuration >>>>>
3839 12:29:41.098754 [RX_INPUT] configuration <<<<<
3840 12:29:41.102163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 12:29:41.108811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 12:29:41.115127 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 12:29:41.122007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 12:29:41.128172 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 12:29:41.135119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 12:29:41.138197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 12:29:41.141988 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 12:29:41.145088 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 12:29:41.148311 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 12:29:41.154858 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 12:29:41.158246 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 12:29:41.161524 ===================================
3853 12:29:41.164707 LPDDR4 DRAM CONFIGURATION
3854 12:29:41.168552 ===================================
3855 12:29:41.168635 EX_ROW_EN[0] = 0x0
3856 12:29:41.171251 EX_ROW_EN[1] = 0x0
3857 12:29:41.171360 LP4Y_EN = 0x0
3858 12:29:41.174609 WORK_FSP = 0x0
3859 12:29:41.174693 WL = 0x2
3860 12:29:41.177978 RL = 0x2
3861 12:29:41.178062 BL = 0x2
3862 12:29:41.181209 RPST = 0x0
3863 12:29:41.184992 RD_PRE = 0x0
3864 12:29:41.185079 WR_PRE = 0x1
3865 12:29:41.188121 WR_PST = 0x0
3866 12:29:41.188229 DBI_WR = 0x0
3867 12:29:41.191432 DBI_RD = 0x0
3868 12:29:41.191533 OTF = 0x1
3869 12:29:41.194700 ===================================
3870 12:29:41.198079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 12:29:41.204892 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 12:29:41.208494 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 12:29:41.211200 ===================================
3874 12:29:41.214511 LPDDR4 DRAM CONFIGURATION
3875 12:29:41.217864 ===================================
3876 12:29:41.217974 EX_ROW_EN[0] = 0x10
3877 12:29:41.221195 EX_ROW_EN[1] = 0x0
3878 12:29:41.221307 LP4Y_EN = 0x0
3879 12:29:41.224935 WORK_FSP = 0x0
3880 12:29:41.225049 WL = 0x2
3881 12:29:41.228130 RL = 0x2
3882 12:29:41.228235 BL = 0x2
3883 12:29:41.231240 RPST = 0x0
3884 12:29:41.231383 RD_PRE = 0x0
3885 12:29:41.234426 WR_PRE = 0x1
3886 12:29:41.234499 WR_PST = 0x0
3887 12:29:41.238061 DBI_WR = 0x0
3888 12:29:41.241156 DBI_RD = 0x0
3889 12:29:41.241270 OTF = 0x1
3890 12:29:41.244194 ===================================
3891 12:29:41.251158 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 12:29:41.255067 nWR fixed to 30
3893 12:29:41.258234 [ModeRegInit_LP4] CH0 RK0
3894 12:29:41.258336 [ModeRegInit_LP4] CH0 RK1
3895 12:29:41.261474 [ModeRegInit_LP4] CH1 RK0
3896 12:29:41.264911 [ModeRegInit_LP4] CH1 RK1
3897 12:29:41.265019 match AC timing 17
3898 12:29:41.271502 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 12:29:41.274717 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 12:29:41.278095 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 12:29:41.284607 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 12:29:41.287829 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 12:29:41.287951 ==
3904 12:29:41.290977 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 12:29:41.294739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 12:29:41.294857 ==
3907 12:29:41.301509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 12:29:41.308265 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3909 12:29:41.311110 [CA 0] Center 35 (5~66) winsize 62
3910 12:29:41.314469 [CA 1] Center 35 (5~66) winsize 62
3911 12:29:41.317750 [CA 2] Center 33 (3~64) winsize 62
3912 12:29:41.321087 [CA 3] Center 33 (2~64) winsize 63
3913 12:29:41.324509 [CA 4] Center 33 (2~64) winsize 63
3914 12:29:41.327992 [CA 5] Center 32 (2~63) winsize 62
3915 12:29:41.328070
3916 12:29:41.331243 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3917 12:29:41.331380
3918 12:29:41.334503 [CATrainingPosCal] consider 1 rank data
3919 12:29:41.337703 u2DelayCellTimex100 = 270/100 ps
3920 12:29:41.340985 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3921 12:29:41.344255 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3922 12:29:41.347867 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3923 12:29:41.351595 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 12:29:41.354696 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 12:29:41.357956 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3926 12:29:41.358059
3927 12:29:41.364725 CA PerBit enable=1, Macro0, CA PI delay=32
3928 12:29:41.364811
3929 12:29:41.364908 [CBTSetCACLKResult] CA Dly = 32
3930 12:29:41.367829 CS Dly: 4 (0~35)
3931 12:29:41.367898 ==
3932 12:29:41.371226 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 12:29:41.374495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 12:29:41.374608 ==
3935 12:29:41.381258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 12:29:41.387965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 12:29:41.391294 [CA 0] Center 35 (5~66) winsize 62
3938 12:29:41.394568 [CA 1] Center 35 (5~66) winsize 62
3939 12:29:41.397854 [CA 2] Center 34 (3~65) winsize 63
3940 12:29:41.401117 [CA 3] Center 33 (3~64) winsize 62
3941 12:29:41.404443 [CA 4] Center 33 (2~64) winsize 63
3942 12:29:41.407824 [CA 5] Center 32 (2~63) winsize 62
3943 12:29:41.407909
3944 12:29:41.411173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 12:29:41.411258
3946 12:29:41.414438 [CATrainingPosCal] consider 2 rank data
3947 12:29:41.417773 u2DelayCellTimex100 = 270/100 ps
3948 12:29:41.421150 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 12:29:41.424535 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 12:29:41.427975 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 12:29:41.431237 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 12:29:41.434567 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3953 12:29:41.441175 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3954 12:29:41.441265
3955 12:29:41.444066 CA PerBit enable=1, Macro0, CA PI delay=32
3956 12:29:41.444155
3957 12:29:41.447344 [CBTSetCACLKResult] CA Dly = 32
3958 12:29:41.447433 CS Dly: 4 (0~36)
3959 12:29:41.447502
3960 12:29:41.451126 ----->DramcWriteLeveling(PI) begin...
3961 12:29:41.451246 ==
3962 12:29:41.454184 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 12:29:41.457335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 12:29:41.460568 ==
3965 12:29:41.460646 Write leveling (Byte 0): 33 => 33
3966 12:29:41.463981 Write leveling (Byte 1): 33 => 33
3967 12:29:41.467179 DramcWriteLeveling(PI) end<-----
3968 12:29:41.467286
3969 12:29:41.467376 ==
3970 12:29:41.471095 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 12:29:41.477405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 12:29:41.477486 ==
3973 12:29:41.480559 [Gating] SW mode calibration
3974 12:29:41.487309 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 12:29:41.490696 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 12:29:41.497388 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 12:29:41.500507 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 12:29:41.504199 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 12:29:41.507378 0 9 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
3980 12:29:41.514156 0 9 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3981 12:29:41.517596 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 12:29:41.520208 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 12:29:41.527059 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 12:29:41.530517 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:29:41.533940 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:29:41.540425 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 12:29:41.543746 0 10 12 | B1->B0 | 2727 3636 | 0 1 | (0 0) (0 0)
3988 12:29:41.547020 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3989 12:29:41.553599 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 12:29:41.556811 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:29:41.560533 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 12:29:41.566948 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:29:41.570012 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:29:41.573750 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 12:29:41.579886 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 12:29:41.583685 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3997 12:29:41.587048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:29:41.593427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:29:41.596814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:29:41.600322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:29:41.606999 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:29:41.610111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:29:41.613267 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:29:41.619936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:29:41.623304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:29:41.626594 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:29:41.633378 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:29:41.636837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:29:41.640201 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:29:41.643344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:29:41.650110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:29:41.653491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4013 12:29:41.656730 Total UI for P1: 0, mck2ui 16
4014 12:29:41.659934 best dqsien dly found for B0: ( 0, 13, 14)
4015 12:29:41.663682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 12:29:41.666956 Total UI for P1: 0, mck2ui 16
4017 12:29:41.669929 best dqsien dly found for B1: ( 0, 13, 16)
4018 12:29:41.673722 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4019 12:29:41.680036 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4020 12:29:41.680118
4021 12:29:41.683766 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4022 12:29:41.686920 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4023 12:29:41.690127 [Gating] SW calibration Done
4024 12:29:41.690211 ==
4025 12:29:41.693283 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 12:29:41.697074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 12:29:41.697157 ==
4028 12:29:41.697240 RX Vref Scan: 0
4029 12:29:41.700298
4030 12:29:41.700381 RX Vref 0 -> 0, step: 1
4031 12:29:41.700447
4032 12:29:41.703656 RX Delay -230 -> 252, step: 16
4033 12:29:41.706982 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4034 12:29:41.713590 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4035 12:29:41.716923 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4036 12:29:41.720072 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4037 12:29:41.723207 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4038 12:29:41.726971 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4039 12:29:41.733065 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4040 12:29:41.736463 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4041 12:29:41.739844 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4042 12:29:41.743275 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4043 12:29:41.746602 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4044 12:29:41.753313 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4045 12:29:41.756769 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4046 12:29:41.760115 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4047 12:29:41.763388 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4048 12:29:41.769889 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4049 12:29:41.769974 ==
4050 12:29:41.773024 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 12:29:41.776762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 12:29:41.776859 ==
4053 12:29:41.776929 DQS Delay:
4054 12:29:41.779784 DQS0 = 0, DQS1 = 0
4055 12:29:41.779860 DQM Delay:
4056 12:29:41.783484 DQM0 = 50, DQM1 = 46
4057 12:29:41.783578 DQ Delay:
4058 12:29:41.786658 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4059 12:29:41.789805 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4060 12:29:41.793592 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4061 12:29:41.796709 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4062 12:29:41.796794
4063 12:29:41.796861
4064 12:29:41.796922 ==
4065 12:29:41.799780 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 12:29:41.803041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 12:29:41.803151 ==
4068 12:29:41.806360
4069 12:29:41.806444
4070 12:29:41.806511 TX Vref Scan disable
4071 12:29:41.809715 == TX Byte 0 ==
4072 12:29:41.813143 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4073 12:29:41.816634 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4074 12:29:41.819972 == TX Byte 1 ==
4075 12:29:41.823104 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4076 12:29:41.826387 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4077 12:29:41.829671 ==
4078 12:29:41.829781 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 12:29:41.836435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 12:29:41.836541 ==
4081 12:29:41.836643
4082 12:29:41.836744
4083 12:29:41.839811 TX Vref Scan disable
4084 12:29:41.839920 == TX Byte 0 ==
4085 12:29:41.845793 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 12:29:41.849185 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 12:29:41.849289 == TX Byte 1 ==
4088 12:29:41.856067 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4089 12:29:41.859431 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4090 12:29:41.859522
4091 12:29:41.859632 [DATLAT]
4092 12:29:41.862722 Freq=600, CH0 RK0
4093 12:29:41.862832
4094 12:29:41.862928 DATLAT Default: 0x9
4095 12:29:41.866099 0, 0xFFFF, sum = 0
4096 12:29:41.866206 1, 0xFFFF, sum = 0
4097 12:29:41.869459 2, 0xFFFF, sum = 0
4098 12:29:41.869568 3, 0xFFFF, sum = 0
4099 12:29:41.872760 4, 0xFFFF, sum = 0
4100 12:29:41.876085 5, 0xFFFF, sum = 0
4101 12:29:41.876166 6, 0xFFFF, sum = 0
4102 12:29:41.879215 7, 0xFFFF, sum = 0
4103 12:29:41.879321 8, 0x0, sum = 1
4104 12:29:41.879425 9, 0x0, sum = 2
4105 12:29:41.882341 10, 0x0, sum = 3
4106 12:29:41.882430 11, 0x0, sum = 4
4107 12:29:41.885546 best_step = 9
4108 12:29:41.885654
4109 12:29:41.885760 ==
4110 12:29:41.889413 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 12:29:41.892623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 12:29:41.892748 ==
4113 12:29:41.895979 RX Vref Scan: 1
4114 12:29:41.896089
4115 12:29:41.896188 RX Vref 0 -> 0, step: 1
4116 12:29:41.896278
4117 12:29:41.899138 RX Delay -163 -> 252, step: 8
4118 12:29:41.899243
4119 12:29:41.902472 Set Vref, RX VrefLevel [Byte0]: 54
4120 12:29:41.905576 [Byte1]: 48
4121 12:29:41.909964
4122 12:29:41.910072 Final RX Vref Byte 0 = 54 to rank0
4123 12:29:41.913161 Final RX Vref Byte 1 = 48 to rank0
4124 12:29:41.916341 Final RX Vref Byte 0 = 54 to rank1
4125 12:29:41.919777 Final RX Vref Byte 1 = 48 to rank1==
4126 12:29:41.923250 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 12:29:41.929771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 12:29:41.929858 ==
4129 12:29:41.929927 DQS Delay:
4130 12:29:41.930035 DQS0 = 0, DQS1 = 0
4131 12:29:41.933039 DQM Delay:
4132 12:29:41.933113 DQM0 = 53, DQM1 = 46
4133 12:29:41.936204 DQ Delay:
4134 12:29:41.939377 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4135 12:29:41.942619 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4136 12:29:41.946145 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4137 12:29:41.949569 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4138 12:29:41.949672
4139 12:29:41.949863
4140 12:29:41.956107 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4141 12:29:41.959390 CH0 RK0: MR19=808, MR18=6E61
4142 12:29:41.966091 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4143 12:29:41.966205
4144 12:29:41.969463 ----->DramcWriteLeveling(PI) begin...
4145 12:29:41.969556 ==
4146 12:29:41.972673 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 12:29:41.976173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 12:29:41.976338 ==
4149 12:29:41.979517 Write leveling (Byte 0): 35 => 35
4150 12:29:41.982637 Write leveling (Byte 1): 32 => 32
4151 12:29:41.985809 DramcWriteLeveling(PI) end<-----
4152 12:29:41.985935
4153 12:29:41.986056 ==
4154 12:29:41.988973 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 12:29:41.992686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 12:29:41.992799 ==
4157 12:29:41.995858 [Gating] SW mode calibration
4158 12:29:42.002319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 12:29:42.009065 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 12:29:42.012129 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 12:29:42.018936 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 12:29:42.022085 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 12:29:42.026007 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4164 12:29:42.032664 0 9 16 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
4165 12:29:42.035837 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 12:29:42.039169 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 12:29:42.042435 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 12:29:42.048887 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 12:29:42.052056 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 12:29:42.055359 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 12:29:42.062479 0 10 12 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
4172 12:29:42.065188 0 10 16 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
4173 12:29:42.068507 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 12:29:42.075343 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 12:29:42.078686 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 12:29:42.082098 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 12:29:42.088528 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 12:29:42.091826 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 12:29:42.095554 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4180 12:29:42.101867 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4181 12:29:42.105594 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:29:42.108779 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:29:42.115354 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:29:42.118659 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:29:42.121873 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:29:42.128305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:29:42.132090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:29:42.135287 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:29:42.141805 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:29:42.145111 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:29:42.148888 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:29:42.155493 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:29:42.158773 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:29:42.162052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:29:42.165525 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4196 12:29:42.172284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4197 12:29:42.175596 Total UI for P1: 0, mck2ui 16
4198 12:29:42.178280 best dqsien dly found for B1: ( 0, 13, 12)
4199 12:29:42.182217 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 12:29:42.184970 Total UI for P1: 0, mck2ui 16
4201 12:29:42.188305 best dqsien dly found for B0: ( 0, 13, 14)
4202 12:29:42.191572 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4203 12:29:42.195154 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4204 12:29:42.195271
4205 12:29:42.198381 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 12:29:42.205381 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4207 12:29:42.205482 [Gating] SW calibration Done
4208 12:29:42.205578 ==
4209 12:29:42.208468 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 12:29:42.214848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 12:29:42.214967 ==
4212 12:29:42.215048 RX Vref Scan: 0
4213 12:29:42.215109
4214 12:29:42.218249 RX Vref 0 -> 0, step: 1
4215 12:29:42.218348
4216 12:29:42.221530 RX Delay -230 -> 252, step: 16
4217 12:29:42.224944 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4218 12:29:42.228094 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4219 12:29:42.235164 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4220 12:29:42.238449 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4221 12:29:42.241625 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4222 12:29:42.244732 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4223 12:29:42.248029 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4224 12:29:42.254643 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4225 12:29:42.258391 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4226 12:29:42.261155 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4227 12:29:42.264470 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4228 12:29:42.271095 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4229 12:29:42.274415 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4230 12:29:42.277794 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4231 12:29:42.281164 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4232 12:29:42.287757 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4233 12:29:42.287857 ==
4234 12:29:42.291056 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 12:29:42.293894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 12:29:42.293998 ==
4237 12:29:42.294093 DQS Delay:
4238 12:29:42.297199 DQS0 = 0, DQS1 = 0
4239 12:29:42.297281 DQM Delay:
4240 12:29:42.301084 DQM0 = 51, DQM1 = 44
4241 12:29:42.301188 DQ Delay:
4242 12:29:42.304268 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4243 12:29:42.307357 DQ4 =57, DQ5 =49, DQ6 =49, DQ7 =57
4244 12:29:42.310844 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4245 12:29:42.314085 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4246 12:29:42.314183
4247 12:29:42.314277
4248 12:29:42.314351 ==
4249 12:29:42.317785 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 12:29:42.320958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 12:29:42.321063 ==
4252 12:29:42.324386
4253 12:29:42.324482
4254 12:29:42.324577 TX Vref Scan disable
4255 12:29:42.327605 == TX Byte 0 ==
4256 12:29:42.330930 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4257 12:29:42.334229 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4258 12:29:42.337290 == TX Byte 1 ==
4259 12:29:42.340516 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4260 12:29:42.344346 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4261 12:29:42.347602 ==
4262 12:29:42.347684 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 12:29:42.354081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 12:29:42.354166 ==
4265 12:29:42.354273
4266 12:29:42.354364
4267 12:29:42.357404 TX Vref Scan disable
4268 12:29:42.357487 == TX Byte 0 ==
4269 12:29:42.364023 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4270 12:29:42.367318 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4271 12:29:42.367423 == TX Byte 1 ==
4272 12:29:42.373878 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4273 12:29:42.377222 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4274 12:29:42.377307
4275 12:29:42.377373 [DATLAT]
4276 12:29:42.380738 Freq=600, CH0 RK1
4277 12:29:42.380822
4278 12:29:42.380888 DATLAT Default: 0x9
4279 12:29:42.384083 0, 0xFFFF, sum = 0
4280 12:29:42.384196 1, 0xFFFF, sum = 0
4281 12:29:42.387394 2, 0xFFFF, sum = 0
4282 12:29:42.387481 3, 0xFFFF, sum = 0
4283 12:29:42.390700 4, 0xFFFF, sum = 0
4284 12:29:42.390787 5, 0xFFFF, sum = 0
4285 12:29:42.394064 6, 0xFFFF, sum = 0
4286 12:29:42.394149 7, 0xFFFF, sum = 0
4287 12:29:42.397402 8, 0x0, sum = 1
4288 12:29:42.397489 9, 0x0, sum = 2
4289 12:29:42.400860 10, 0x0, sum = 3
4290 12:29:42.400948 11, 0x0, sum = 4
4291 12:29:42.403585 best_step = 9
4292 12:29:42.403669
4293 12:29:42.403734 ==
4294 12:29:42.407333 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 12:29:42.410643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 12:29:42.410727 ==
4297 12:29:42.413854 RX Vref Scan: 0
4298 12:29:42.413937
4299 12:29:42.414002 RX Vref 0 -> 0, step: 1
4300 12:29:42.414062
4301 12:29:42.416972 RX Delay -163 -> 252, step: 8
4302 12:29:42.424149 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4303 12:29:42.427191 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4304 12:29:42.430429 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4305 12:29:42.433805 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4306 12:29:42.437251 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4307 12:29:42.444297 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4308 12:29:42.447644 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4309 12:29:42.450816 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4310 12:29:42.454348 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4311 12:29:42.457565 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4312 12:29:42.464180 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4313 12:29:42.467435 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4314 12:29:42.470597 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4315 12:29:42.473789 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4316 12:29:42.480527 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4317 12:29:42.483841 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4318 12:29:42.483923 ==
4319 12:29:42.487244 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 12:29:42.490654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 12:29:42.490736 ==
4322 12:29:42.493913 DQS Delay:
4323 12:29:42.493993 DQS0 = 0, DQS1 = 0
4324 12:29:42.494057 DQM Delay:
4325 12:29:42.497295 DQM0 = 53, DQM1 = 46
4326 12:29:42.497376 DQ Delay:
4327 12:29:42.500619 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4328 12:29:42.503961 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4329 12:29:42.507421 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4330 12:29:42.510711 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4331 12:29:42.510790
4332 12:29:42.510854
4333 12:29:42.520351 [DQSOSCAuto] RK1, (LSB)MR18= 0x6121, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4334 12:29:42.520434 CH0 RK1: MR19=808, MR18=6121
4335 12:29:42.527268 CH0_RK1: MR19=0x808, MR18=0x6121, DQSOSC=391, MR23=63, INC=171, DEC=114
4336 12:29:42.530407 [RxdqsGatingPostProcess] freq 600
4337 12:29:42.537316 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 12:29:42.540554 Pre-setting of DQS Precalculation
4339 12:29:42.544073 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 12:29:42.544156 ==
4341 12:29:42.547214 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 12:29:42.550518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 12:29:42.553775 ==
4344 12:29:42.557036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 12:29:42.564012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4346 12:29:42.567342 [CA 0] Center 36 (5~67) winsize 63
4347 12:29:42.570687 [CA 1] Center 36 (5~67) winsize 63
4348 12:29:42.573775 [CA 2] Center 34 (4~65) winsize 62
4349 12:29:42.577002 [CA 3] Center 34 (4~65) winsize 62
4350 12:29:42.580273 [CA 4] Center 34 (4~65) winsize 62
4351 12:29:42.583578 [CA 5] Center 34 (3~65) winsize 63
4352 12:29:42.583661
4353 12:29:42.587013 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4354 12:29:42.587112
4355 12:29:42.590373 [CATrainingPosCal] consider 1 rank data
4356 12:29:42.593747 u2DelayCellTimex100 = 270/100 ps
4357 12:29:42.597052 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4358 12:29:42.600498 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4359 12:29:42.603924 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 12:29:42.607270 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 12:29:42.613497 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 12:29:42.617294 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4363 12:29:42.617393
4364 12:29:42.620605 CA PerBit enable=1, Macro0, CA PI delay=34
4365 12:29:42.620687
4366 12:29:42.623666 [CBTSetCACLKResult] CA Dly = 34
4367 12:29:42.623771 CS Dly: 6 (0~37)
4368 12:29:42.623881 ==
4369 12:29:42.626959 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 12:29:42.633665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 12:29:42.633777 ==
4372 12:29:42.636951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 12:29:42.643737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 12:29:42.647160 [CA 0] Center 36 (5~67) winsize 63
4375 12:29:42.650510 [CA 1] Center 36 (5~67) winsize 63
4376 12:29:42.653693 [CA 2] Center 35 (4~66) winsize 63
4377 12:29:42.657002 [CA 3] Center 35 (4~66) winsize 63
4378 12:29:42.660265 [CA 4] Center 34 (4~65) winsize 62
4379 12:29:42.663312 [CA 5] Center 34 (4~65) winsize 62
4380 12:29:42.663416
4381 12:29:42.666511 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 12:29:42.666619
4383 12:29:42.670398 [CATrainingPosCal] consider 2 rank data
4384 12:29:42.673768 u2DelayCellTimex100 = 270/100 ps
4385 12:29:42.676483 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 12:29:42.680319 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4387 12:29:42.686750 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 12:29:42.690113 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 12:29:42.693412 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 12:29:42.696824 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 12:29:42.696907
4392 12:29:42.700149 CA PerBit enable=1, Macro0, CA PI delay=34
4393 12:29:42.700233
4394 12:29:42.703514 [CBTSetCACLKResult] CA Dly = 34
4395 12:29:42.703596 CS Dly: 6 (0~38)
4396 12:29:42.703661
4397 12:29:42.706930 ----->DramcWriteLeveling(PI) begin...
4398 12:29:42.707030 ==
4399 12:29:42.710348 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 12:29:42.716477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:29:42.716576 ==
4402 12:29:42.719831 Write leveling (Byte 0): 31 => 31
4403 12:29:42.723158 Write leveling (Byte 1): 31 => 31
4404 12:29:42.726874 DramcWriteLeveling(PI) end<-----
4405 12:29:42.726974
4406 12:29:42.727069 ==
4407 12:29:42.730032 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 12:29:42.733242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 12:29:42.733341 ==
4410 12:29:42.736816 [Gating] SW mode calibration
4411 12:29:42.743157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 12:29:42.746824 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 12:29:42.753534 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 12:29:42.756821 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 12:29:42.760017 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 12:29:42.766390 0 9 12 | B1->B0 | 2e2e 2e2e | 1 0 | (1 0) (0 0)
4417 12:29:42.769550 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 12:29:42.773458 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 12:29:42.779981 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 12:29:42.783267 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:29:42.786619 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 12:29:42.793030 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 12:29:42.796334 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4424 12:29:42.799709 0 10 12 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
4425 12:29:42.806305 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 12:29:42.809650 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 12:29:42.812983 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 12:29:42.819704 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:29:42.823172 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:29:42.825820 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 12:29:42.832983 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 12:29:42.836098 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4433 12:29:42.839165 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:29:42.846231 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:29:42.849404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:29:42.852583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:29:42.859503 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:29:42.862742 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:29:42.866088 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:29:42.872380 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:29:42.876462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:29:42.879636 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:29:42.882793 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:29:42.889404 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:29:42.892678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:29:42.896074 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:29:42.902735 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4448 12:29:42.905977 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:29:42.909192 Total UI for P1: 0, mck2ui 16
4450 12:29:42.912633 best dqsien dly found for B0: ( 0, 13, 8)
4451 12:29:42.916113 Total UI for P1: 0, mck2ui 16
4452 12:29:42.919381 best dqsien dly found for B1: ( 0, 13, 10)
4453 12:29:42.922697 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4454 12:29:42.926155 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4455 12:29:42.926240
4456 12:29:42.929441 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4457 12:29:42.932787 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4458 12:29:42.936185 [Gating] SW calibration Done
4459 12:29:42.936280 ==
4460 12:29:42.939435 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 12:29:42.945779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 12:29:42.945897 ==
4463 12:29:42.945994 RX Vref Scan: 0
4464 12:29:42.946084
4465 12:29:42.948854 RX Vref 0 -> 0, step: 1
4466 12:29:42.948931
4467 12:29:42.952615 RX Delay -230 -> 252, step: 16
4468 12:29:42.955793 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4469 12:29:42.958941 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4470 12:29:42.962465 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4471 12:29:42.969096 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4472 12:29:42.972233 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4473 12:29:42.975363 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4474 12:29:42.978653 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4475 12:29:42.982536 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4476 12:29:42.989170 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4477 12:29:42.991874 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4478 12:29:42.995731 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4479 12:29:42.998916 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4480 12:29:43.005279 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4481 12:29:43.009279 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4482 12:29:43.012011 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4483 12:29:43.015301 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4484 12:29:43.015438 ==
4485 12:29:43.018740 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 12:29:43.025505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 12:29:43.025590 ==
4488 12:29:43.025656 DQS Delay:
4489 12:29:43.028821 DQS0 = 0, DQS1 = 0
4490 12:29:43.028903 DQM Delay:
4491 12:29:43.032196 DQM0 = 50, DQM1 = 46
4492 12:29:43.032326 DQ Delay:
4493 12:29:43.035648 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4494 12:29:43.038388 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4495 12:29:43.041797 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4496 12:29:43.045647 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4497 12:29:43.045732
4498 12:29:43.045798
4499 12:29:43.045875 ==
4500 12:29:43.048894 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 12:29:43.052207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 12:29:43.052315 ==
4503 12:29:43.052410
4504 12:29:43.052502
4505 12:29:43.055209 TX Vref Scan disable
4506 12:29:43.058298 == TX Byte 0 ==
4507 12:29:43.061463 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4508 12:29:43.065202 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4509 12:29:43.068303 == TX Byte 1 ==
4510 12:29:43.071448 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4511 12:29:43.075270 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4512 12:29:43.075400 ==
4513 12:29:43.078491 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 12:29:43.085052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 12:29:43.085224 ==
4516 12:29:43.085344
4517 12:29:43.085454
4518 12:29:43.085544 TX Vref Scan disable
4519 12:29:43.088772 == TX Byte 0 ==
4520 12:29:43.092066 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4521 12:29:43.095788 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4522 12:29:43.099158 == TX Byte 1 ==
4523 12:29:43.102385 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4524 12:29:43.108901 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4525 12:29:43.109014
4526 12:29:43.109109 [DATLAT]
4527 12:29:43.109203 Freq=600, CH1 RK0
4528 12:29:43.109292
4529 12:29:43.112166 DATLAT Default: 0x9
4530 12:29:43.112240 0, 0xFFFF, sum = 0
4531 12:29:43.115440 1, 0xFFFF, sum = 0
4532 12:29:43.115519 2, 0xFFFF, sum = 0
4533 12:29:43.118814 3, 0xFFFF, sum = 0
4534 12:29:43.118921 4, 0xFFFF, sum = 0
4535 12:29:43.122083 5, 0xFFFF, sum = 0
4536 12:29:43.125439 6, 0xFFFF, sum = 0
4537 12:29:43.125541 7, 0xFFFF, sum = 0
4538 12:29:43.125638 8, 0x0, sum = 1
4539 12:29:43.128879 9, 0x0, sum = 2
4540 12:29:43.128984 10, 0x0, sum = 3
4541 12:29:43.132122 11, 0x0, sum = 4
4542 12:29:43.132226 best_step = 9
4543 12:29:43.132320
4544 12:29:43.132408 ==
4545 12:29:43.135528 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 12:29:43.142390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 12:29:43.142526 ==
4548 12:29:43.142644 RX Vref Scan: 1
4549 12:29:43.142803
4550 12:29:43.145743 RX Vref 0 -> 0, step: 1
4551 12:29:43.145870
4552 12:29:43.149075 RX Delay -163 -> 252, step: 8
4553 12:29:43.149227
4554 12:29:43.152392 Set Vref, RX VrefLevel [Byte0]: 53
4555 12:29:43.155108 [Byte1]: 52
4556 12:29:43.155212
4557 12:29:43.158443 Final RX Vref Byte 0 = 53 to rank0
4558 12:29:43.162305 Final RX Vref Byte 1 = 52 to rank0
4559 12:29:43.165384 Final RX Vref Byte 0 = 53 to rank1
4560 12:29:43.168560 Final RX Vref Byte 1 = 52 to rank1==
4561 12:29:43.172089 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 12:29:43.175160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 12:29:43.175260 ==
4564 12:29:43.178854 DQS Delay:
4565 12:29:43.178938 DQS0 = 0, DQS1 = 0
4566 12:29:43.179004 DQM Delay:
4567 12:29:43.181993 DQM0 = 48, DQM1 = 45
4568 12:29:43.182077 DQ Delay:
4569 12:29:43.185352 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4570 12:29:43.188606 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4571 12:29:43.191756 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4572 12:29:43.195571 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4573 12:29:43.195656
4574 12:29:43.195722
4575 12:29:43.205295 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4576 12:29:43.208578 CH1 RK0: MR19=808, MR18=496E
4577 12:29:43.211748 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4578 12:29:43.211833
4579 12:29:43.214908 ----->DramcWriteLeveling(PI) begin...
4580 12:29:43.218750 ==
4581 12:29:43.222025 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 12:29:43.225410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 12:29:43.225494 ==
4584 12:29:43.228843 Write leveling (Byte 0): 30 => 30
4585 12:29:43.231486 Write leveling (Byte 1): 30 => 30
4586 12:29:43.234972 DramcWriteLeveling(PI) end<-----
4587 12:29:43.235056
4588 12:29:43.235145 ==
4589 12:29:43.238248 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 12:29:43.241520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 12:29:43.241623 ==
4592 12:29:43.244901 [Gating] SW mode calibration
4593 12:29:43.251541 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 12:29:43.258142 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 12:29:43.261451 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 12:29:43.264820 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 12:29:43.268024 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4598 12:29:43.275104 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 0)
4599 12:29:43.278288 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 12:29:43.281462 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 12:29:43.288307 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 12:29:43.291514 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 12:29:43.294667 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 12:29:43.301697 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 12:29:43.304950 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 12:29:43.308172 0 10 12 | B1->B0 | 3838 3838 | 0 1 | (0 0) (0 0)
4607 12:29:43.314683 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 12:29:43.317808 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 12:29:43.321542 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 12:29:43.327966 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 12:29:43.331340 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 12:29:43.334820 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 12:29:43.341375 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4614 12:29:43.344767 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4615 12:29:43.348205 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:29:43.354817 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:29:43.358002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:29:43.361364 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:29:43.368120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:29:43.371492 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:29:43.374814 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:29:43.378176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:29:43.384971 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:29:43.388275 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:29:43.391577 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:29:43.398078 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:29:43.401299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:29:43.404474 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:29:43.411154 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:29:43.414441 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4631 12:29:43.418368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:29:43.421165 Total UI for P1: 0, mck2ui 16
4633 12:29:43.424379 best dqsien dly found for B0: ( 0, 13, 14)
4634 12:29:43.427629 Total UI for P1: 0, mck2ui 16
4635 12:29:43.431315 best dqsien dly found for B1: ( 0, 13, 12)
4636 12:29:43.434545 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4637 12:29:43.437762 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4638 12:29:43.441307
4639 12:29:43.444660 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4640 12:29:43.447976 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4641 12:29:43.451259 [Gating] SW calibration Done
4642 12:29:43.451365 ==
4643 12:29:43.454631 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 12:29:43.457801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 12:29:43.457917 ==
4646 12:29:43.458008 RX Vref Scan: 0
4647 12:29:43.461164
4648 12:29:43.461263 RX Vref 0 -> 0, step: 1
4649 12:29:43.461352
4650 12:29:43.464571 RX Delay -230 -> 252, step: 16
4651 12:29:43.467877 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4652 12:29:43.474434 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4653 12:29:43.477762 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4654 12:29:43.481215 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4655 12:29:43.484308 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 12:29:43.487317 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4657 12:29:43.494268 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4658 12:29:43.497448 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 12:29:43.501190 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4660 12:29:43.504327 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4661 12:29:43.510799 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4662 12:29:43.514173 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4663 12:29:43.517381 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 12:29:43.520617 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4665 12:29:43.524462 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4666 12:29:43.531129 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 12:29:43.531214 ==
4668 12:29:43.534508 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 12:29:43.537616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 12:29:43.537702 ==
4671 12:29:43.537769 DQS Delay:
4672 12:29:43.540650 DQS0 = 0, DQS1 = 0
4673 12:29:43.540734 DQM Delay:
4674 12:29:43.544316 DQM0 = 50, DQM1 = 48
4675 12:29:43.544401 DQ Delay:
4676 12:29:43.547681 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4677 12:29:43.551118 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4678 12:29:43.553737 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4679 12:29:43.557104 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4680 12:29:43.557186
4681 12:29:43.557261
4682 12:29:43.557326 ==
4683 12:29:43.560323 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 12:29:43.563702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 12:29:43.567534 ==
4686 12:29:43.567620
4687 12:29:43.567687
4688 12:29:43.567751 TX Vref Scan disable
4689 12:29:43.570326 == TX Byte 0 ==
4690 12:29:43.574326 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4691 12:29:43.577007 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4692 12:29:43.580797 == TX Byte 1 ==
4693 12:29:43.583962 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 12:29:43.587430 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 12:29:43.590660 ==
4696 12:29:43.593867 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:29:43.597536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:29:43.597621 ==
4699 12:29:43.597688
4700 12:29:43.597776
4701 12:29:43.600747 TX Vref Scan disable
4702 12:29:43.600830 == TX Byte 0 ==
4703 12:29:43.606817 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 12:29:43.610591 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 12:29:43.610676 == TX Byte 1 ==
4706 12:29:43.616911 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 12:29:43.620498 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 12:29:43.620596
4709 12:29:43.620663 [DATLAT]
4710 12:29:43.623790 Freq=600, CH1 RK1
4711 12:29:43.623874
4712 12:29:43.623983 DATLAT Default: 0x9
4713 12:29:43.626920 0, 0xFFFF, sum = 0
4714 12:29:43.627005 1, 0xFFFF, sum = 0
4715 12:29:43.629916 2, 0xFFFF, sum = 0
4716 12:29:43.633702 3, 0xFFFF, sum = 0
4717 12:29:43.633790 4, 0xFFFF, sum = 0
4718 12:29:43.637085 5, 0xFFFF, sum = 0
4719 12:29:43.637187 6, 0xFFFF, sum = 0
4720 12:29:43.640292 7, 0xFFFF, sum = 0
4721 12:29:43.640378 8, 0x0, sum = 1
4722 12:29:43.640446 9, 0x0, sum = 2
4723 12:29:43.643667 10, 0x0, sum = 3
4724 12:29:43.643780 11, 0x0, sum = 4
4725 12:29:43.647025 best_step = 9
4726 12:29:43.647126
4727 12:29:43.647218 ==
4728 12:29:43.650078 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 12:29:43.654030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 12:29:43.654136 ==
4731 12:29:43.656840 RX Vref Scan: 0
4732 12:29:43.656940
4733 12:29:43.657036 RX Vref 0 -> 0, step: 1
4734 12:29:43.657125
4735 12:29:43.660215 RX Delay -163 -> 252, step: 8
4736 12:29:43.667521 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4737 12:29:43.670684 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4738 12:29:43.674133 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4739 12:29:43.677439 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 12:29:43.680828 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4741 12:29:43.687401 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4742 12:29:43.690635 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4743 12:29:43.693939 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4744 12:29:43.697331 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 12:29:43.703754 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4746 12:29:43.706972 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4747 12:29:43.710846 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 12:29:43.714061 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4749 12:29:43.717123 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4750 12:29:43.724398 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4751 12:29:43.727388 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4752 12:29:43.727497 ==
4753 12:29:43.730648 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 12:29:43.733826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 12:29:43.733935 ==
4756 12:29:43.737061 DQS Delay:
4757 12:29:43.737163 DQS0 = 0, DQS1 = 0
4758 12:29:43.737256 DQM Delay:
4759 12:29:43.740786 DQM0 = 49, DQM1 = 46
4760 12:29:43.740892 DQ Delay:
4761 12:29:43.744038 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4762 12:29:43.747484 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4763 12:29:43.750751 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4764 12:29:43.754073 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4765 12:29:43.754194
4766 12:29:43.754313
4767 12:29:43.763643 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f26, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4768 12:29:43.763753 CH1 RK1: MR19=808, MR18=6F26
4769 12:29:43.770254 CH1_RK1: MR19=0x808, MR18=0x6F26, DQSOSC=389, MR23=63, INC=173, DEC=115
4770 12:29:43.773480 [RxdqsGatingPostProcess] freq 600
4771 12:29:43.780096 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 12:29:43.783517 Pre-setting of DQS Precalculation
4773 12:29:43.786796 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 12:29:43.793540 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 12:29:43.803789 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 12:29:43.803895
4777 12:29:43.803988
4778 12:29:43.807017 [Calibration Summary] 1200 Mbps
4779 12:29:43.807128 CH 0, Rank 0
4780 12:29:43.810234 SW Impedance : PASS
4781 12:29:43.810333 DUTY Scan : NO K
4782 12:29:43.813394 ZQ Calibration : PASS
4783 12:29:43.817093 Jitter Meter : NO K
4784 12:29:43.817193 CBT Training : PASS
4785 12:29:43.820203 Write leveling : PASS
4786 12:29:43.820278 RX DQS gating : PASS
4787 12:29:43.823384 RX DQ/DQS(RDDQC) : PASS
4788 12:29:43.826657 TX DQ/DQS : PASS
4789 12:29:43.826759 RX DATLAT : PASS
4790 12:29:43.829904 RX DQ/DQS(Engine): PASS
4791 12:29:43.833816 TX OE : NO K
4792 12:29:43.833930 All Pass.
4793 12:29:43.834037
4794 12:29:43.834132 CH 0, Rank 1
4795 12:29:43.836871 SW Impedance : PASS
4796 12:29:43.840100 DUTY Scan : NO K
4797 12:29:43.840204 ZQ Calibration : PASS
4798 12:29:43.843370 Jitter Meter : NO K
4799 12:29:43.846556 CBT Training : PASS
4800 12:29:43.846658 Write leveling : PASS
4801 12:29:43.850274 RX DQS gating : PASS
4802 12:29:43.853477 RX DQ/DQS(RDDQC) : PASS
4803 12:29:43.853582 TX DQ/DQS : PASS
4804 12:29:43.856847 RX DATLAT : PASS
4805 12:29:43.860134 RX DQ/DQS(Engine): PASS
4806 12:29:43.860231 TX OE : NO K
4807 12:29:43.860387 All Pass.
4808 12:29:43.860508
4809 12:29:43.863517 CH 1, Rank 0
4810 12:29:43.863629 SW Impedance : PASS
4811 12:29:43.866678 DUTY Scan : NO K
4812 12:29:43.869919 ZQ Calibration : PASS
4813 12:29:43.870027 Jitter Meter : NO K
4814 12:29:43.873219 CBT Training : PASS
4815 12:29:43.877153 Write leveling : PASS
4816 12:29:43.877255 RX DQS gating : PASS
4817 12:29:43.880509 RX DQ/DQS(RDDQC) : PASS
4818 12:29:43.883168 TX DQ/DQS : PASS
4819 12:29:43.883276 RX DATLAT : PASS
4820 12:29:43.886630 RX DQ/DQS(Engine): PASS
4821 12:29:43.889976 TX OE : NO K
4822 12:29:43.890108 All Pass.
4823 12:29:43.890175
4824 12:29:43.890283 CH 1, Rank 1
4825 12:29:43.893392 SW Impedance : PASS
4826 12:29:43.896945 DUTY Scan : NO K
4827 12:29:43.897020 ZQ Calibration : PASS
4828 12:29:43.900251 Jitter Meter : NO K
4829 12:29:43.902923 CBT Training : PASS
4830 12:29:43.903024 Write leveling : PASS
4831 12:29:43.906886 RX DQS gating : PASS
4832 12:29:43.910047 RX DQ/DQS(RDDQC) : PASS
4833 12:29:43.910148 TX DQ/DQS : PASS
4834 12:29:43.913361 RX DATLAT : PASS
4835 12:29:43.913435 RX DQ/DQS(Engine): PASS
4836 12:29:43.916597 TX OE : NO K
4837 12:29:43.916671 All Pass.
4838 12:29:43.916759
4839 12:29:43.919796 DramC Write-DBI off
4840 12:29:43.923001 PER_BANK_REFRESH: Hybrid Mode
4841 12:29:43.923094 TX_TRACKING: ON
4842 12:29:43.933127 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 12:29:43.936367 [FAST_K] Save calibration result to emmc
4844 12:29:43.939690 dramc_set_vcore_voltage set vcore to 662500
4845 12:29:43.943080 Read voltage for 933, 3
4846 12:29:43.943171 Vio18 = 0
4847 12:29:43.946042 Vcore = 662500
4848 12:29:43.946247 Vdram = 0
4849 12:29:43.946368 Vddq = 0
4850 12:29:43.946459 Vmddr = 0
4851 12:29:43.952655 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 12:29:43.959463 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 12:29:43.959555 MEM_TYPE=3, freq_sel=17
4854 12:29:43.962716 sv_algorithm_assistance_LP4_1600
4855 12:29:43.965986 ============ PULL DRAM RESETB DOWN ============
4856 12:29:43.973015 ========== PULL DRAM RESETB DOWN end =========
4857 12:29:43.976261 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 12:29:43.979570 ===================================
4859 12:29:43.982981 LPDDR4 DRAM CONFIGURATION
4860 12:29:43.986174 ===================================
4861 12:29:43.986273 EX_ROW_EN[0] = 0x0
4862 12:29:43.989402 EX_ROW_EN[1] = 0x0
4863 12:29:43.989476 LP4Y_EN = 0x0
4864 12:29:43.992908 WORK_FSP = 0x0
4865 12:29:43.993007 WL = 0x3
4866 12:29:43.995937 RL = 0x3
4867 12:29:43.996011 BL = 0x2
4868 12:29:43.999306 RPST = 0x0
4869 12:29:44.002601 RD_PRE = 0x0
4870 12:29:44.002752 WR_PRE = 0x1
4871 12:29:44.006081 WR_PST = 0x0
4872 12:29:44.006178 DBI_WR = 0x0
4873 12:29:44.009456 DBI_RD = 0x0
4874 12:29:44.009554 OTF = 0x1
4875 12:29:44.012705 ===================================
4876 12:29:44.015979 ===================================
4877 12:29:44.016050 ANA top config
4878 12:29:44.019262 ===================================
4879 12:29:44.022589 DLL_ASYNC_EN = 0
4880 12:29:44.025762 ALL_SLAVE_EN = 1
4881 12:29:44.029003 NEW_RANK_MODE = 1
4882 12:29:44.032832 DLL_IDLE_MODE = 1
4883 12:29:44.032933 LP45_APHY_COMB_EN = 1
4884 12:29:44.035880 TX_ODT_DIS = 1
4885 12:29:44.039129 NEW_8X_MODE = 1
4886 12:29:44.042333 ===================================
4887 12:29:44.045680 ===================================
4888 12:29:44.049052 data_rate = 1866
4889 12:29:44.052953 CKR = 1
4890 12:29:44.053036 DQ_P2S_RATIO = 8
4891 12:29:44.056015 ===================================
4892 12:29:44.059161 CA_P2S_RATIO = 8
4893 12:29:44.063072 DQ_CA_OPEN = 0
4894 12:29:44.066025 DQ_SEMI_OPEN = 0
4895 12:29:44.069609 CA_SEMI_OPEN = 0
4896 12:29:44.072838 CA_FULL_RATE = 0
4897 12:29:44.072920 DQ_CKDIV4_EN = 1
4898 12:29:44.076265 CA_CKDIV4_EN = 1
4899 12:29:44.079418 CA_PREDIV_EN = 0
4900 12:29:44.082710 PH8_DLY = 0
4901 12:29:44.086111 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 12:29:44.089366 DQ_AAMCK_DIV = 4
4903 12:29:44.089449 CA_AAMCK_DIV = 4
4904 12:29:44.092710 CA_ADMCK_DIV = 4
4905 12:29:44.096040 DQ_TRACK_CA_EN = 0
4906 12:29:44.099363 CA_PICK = 933
4907 12:29:44.102719 CA_MCKIO = 933
4908 12:29:44.106066 MCKIO_SEMI = 0
4909 12:29:44.106149 PLL_FREQ = 3732
4910 12:29:44.109488 DQ_UI_PI_RATIO = 32
4911 12:29:44.112772 CA_UI_PI_RATIO = 0
4912 12:29:44.116145 ===================================
4913 12:29:44.119566 ===================================
4914 12:29:44.122788 memory_type:LPDDR4
4915 12:29:44.125536 GP_NUM : 10
4916 12:29:44.125619 SRAM_EN : 1
4917 12:29:44.128933 MD32_EN : 0
4918 12:29:44.132712 ===================================
4919 12:29:44.132795 [ANA_INIT] >>>>>>>>>>>>>>
4920 12:29:44.135893 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 12:29:44.139133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 12:29:44.142696 ===================================
4923 12:29:44.145816 data_rate = 1866,PCW = 0X8f00
4924 12:29:44.149068 ===================================
4925 12:29:44.152432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 12:29:44.159134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 12:29:44.162242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 12:29:44.169128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 12:29:44.172450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 12:29:44.175565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 12:29:44.178659 [ANA_INIT] flow start
4932 12:29:44.178742 [ANA_INIT] PLL >>>>>>>>
4933 12:29:44.181844 [ANA_INIT] PLL <<<<<<<<
4934 12:29:44.185069 [ANA_INIT] MIDPI >>>>>>>>
4935 12:29:44.185151 [ANA_INIT] MIDPI <<<<<<<<
4936 12:29:44.188986 [ANA_INIT] DLL >>>>>>>>
4937 12:29:44.192224 [ANA_INIT] flow end
4938 12:29:44.195600 ============ LP4 DIFF to SE enter ============
4939 12:29:44.199028 ============ LP4 DIFF to SE exit ============
4940 12:29:44.202357 [ANA_INIT] <<<<<<<<<<<<<
4941 12:29:44.205651 [Flow] Enable top DCM control >>>>>
4942 12:29:44.208950 [Flow] Enable top DCM control <<<<<
4943 12:29:44.212182 Enable DLL master slave shuffle
4944 12:29:44.215605 ==============================================================
4945 12:29:44.218404 Gating Mode config
4946 12:29:44.225149 ==============================================================
4947 12:29:44.225263 Config description:
4948 12:29:44.234939 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 12:29:44.241638 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 12:29:44.248621 SELPH_MODE 0: By rank 1: By Phase
4951 12:29:44.251630 ==============================================================
4952 12:29:44.255024 GAT_TRACK_EN = 1
4953 12:29:44.258307 RX_GATING_MODE = 2
4954 12:29:44.261612 RX_GATING_TRACK_MODE = 2
4955 12:29:44.265102 SELPH_MODE = 1
4956 12:29:44.268468 PICG_EARLY_EN = 1
4957 12:29:44.271734 VALID_LAT_VALUE = 1
4958 12:29:44.274819 ==============================================================
4959 12:29:44.277932 Enter into Gating configuration >>>>
4960 12:29:44.281741 Exit from Gating configuration <<<<
4961 12:29:44.284915 Enter into DVFS_PRE_config >>>>>
4962 12:29:44.297899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 12:29:44.301159 Exit from DVFS_PRE_config <<<<<
4964 12:29:44.301244 Enter into PICG configuration >>>>
4965 12:29:44.304555 Exit from PICG configuration <<<<
4966 12:29:44.307806 [RX_INPUT] configuration >>>>>
4967 12:29:44.311240 [RX_INPUT] configuration <<<<<
4968 12:29:44.317916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 12:29:44.321405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 12:29:44.328063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 12:29:44.334734 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 12:29:44.341364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 12:29:44.348214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 12:29:44.351427 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 12:29:44.354439 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 12:29:44.358246 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 12:29:44.364614 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 12:29:44.367992 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 12:29:44.371264 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 12:29:44.374527 ===================================
4981 12:29:44.377849 LPDDR4 DRAM CONFIGURATION
4982 12:29:44.381179 ===================================
4983 12:29:44.384390 EX_ROW_EN[0] = 0x0
4984 12:29:44.384503 EX_ROW_EN[1] = 0x0
4985 12:29:44.388054 LP4Y_EN = 0x0
4986 12:29:44.388202 WORK_FSP = 0x0
4987 12:29:44.391187 WL = 0x3
4988 12:29:44.391304 RL = 0x3
4989 12:29:44.394394 BL = 0x2
4990 12:29:44.394469 RPST = 0x0
4991 12:29:44.397498 RD_PRE = 0x0
4992 12:29:44.397613 WR_PRE = 0x1
4993 12:29:44.401309 WR_PST = 0x0
4994 12:29:44.401395 DBI_WR = 0x0
4995 12:29:44.404542 DBI_RD = 0x0
4996 12:29:44.404641 OTF = 0x1
4997 12:29:44.407725 ===================================
4998 12:29:44.411032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 12:29:44.417634 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 12:29:44.421039 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 12:29:44.424480 ===================================
5002 12:29:44.427699 LPDDR4 DRAM CONFIGURATION
5003 12:29:44.430885 ===================================
5004 12:29:44.430980 EX_ROW_EN[0] = 0x10
5005 12:29:44.434329 EX_ROW_EN[1] = 0x0
5006 12:29:44.437731 LP4Y_EN = 0x0
5007 12:29:44.437844 WORK_FSP = 0x0
5008 12:29:44.441148 WL = 0x3
5009 12:29:44.441262 RL = 0x3
5010 12:29:44.443964 BL = 0x2
5011 12:29:44.444036 RPST = 0x0
5012 12:29:44.447301 RD_PRE = 0x0
5013 12:29:44.447421 WR_PRE = 0x1
5014 12:29:44.450623 WR_PST = 0x0
5015 12:29:44.450693 DBI_WR = 0x0
5016 12:29:44.454334 DBI_RD = 0x0
5017 12:29:44.454410 OTF = 0x1
5018 12:29:44.457665 ===================================
5019 12:29:44.463741 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 12:29:44.468238 nWR fixed to 30
5021 12:29:44.471471 [ModeRegInit_LP4] CH0 RK0
5022 12:29:44.471545 [ModeRegInit_LP4] CH0 RK1
5023 12:29:44.475317 [ModeRegInit_LP4] CH1 RK0
5024 12:29:44.478721 [ModeRegInit_LP4] CH1 RK1
5025 12:29:44.478810 match AC timing 9
5026 12:29:44.485117 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 12:29:44.488499 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 12:29:44.492075 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 12:29:44.498124 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 12:29:44.501834 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 12:29:44.501941 ==
5032 12:29:44.505053 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 12:29:44.508212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 12:29:44.508321 ==
5035 12:29:44.515166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 12:29:44.521716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 12:29:44.525196 [CA 0] Center 37 (7~68) winsize 62
5038 12:29:44.527909 [CA 1] Center 37 (7~68) winsize 62
5039 12:29:44.531223 [CA 2] Center 34 (4~65) winsize 62
5040 12:29:44.535108 [CA 3] Center 34 (3~65) winsize 63
5041 12:29:44.538516 [CA 4] Center 33 (3~64) winsize 62
5042 12:29:44.541275 [CA 5] Center 32 (2~62) winsize 61
5043 12:29:44.541378
5044 12:29:44.544484 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 12:29:44.544589
5046 12:29:44.547831 [CATrainingPosCal] consider 1 rank data
5047 12:29:44.551274 u2DelayCellTimex100 = 270/100 ps
5048 12:29:44.554394 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5049 12:29:44.558247 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5050 12:29:44.561633 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 12:29:44.564708 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5052 12:29:44.567911 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5053 12:29:44.574791 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5054 12:29:44.574899
5055 12:29:44.578049 CA PerBit enable=1, Macro0, CA PI delay=32
5056 12:29:44.578146
5057 12:29:44.581221 [CBTSetCACLKResult] CA Dly = 32
5058 12:29:44.581318 CS Dly: 5 (0~36)
5059 12:29:44.581435 ==
5060 12:29:44.584538 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 12:29:44.587936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 12:29:44.591125 ==
5063 12:29:44.594480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 12:29:44.600863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 12:29:44.604464 [CA 0] Center 37 (6~68) winsize 63
5066 12:29:44.607648 [CA 1] Center 37 (7~68) winsize 62
5067 12:29:44.611214 [CA 2] Center 34 (4~65) winsize 62
5068 12:29:44.614167 [CA 3] Center 34 (4~65) winsize 62
5069 12:29:44.617783 [CA 4] Center 32 (2~63) winsize 62
5070 12:29:44.621057 [CA 5] Center 32 (2~62) winsize 61
5071 12:29:44.621157
5072 12:29:44.624075 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 12:29:44.624170
5074 12:29:44.627815 [CATrainingPosCal] consider 2 rank data
5075 12:29:44.631179 u2DelayCellTimex100 = 270/100 ps
5076 12:29:44.633949 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5077 12:29:44.637245 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 12:29:44.641237 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 12:29:44.644571 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5080 12:29:44.650528 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5081 12:29:44.654009 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5082 12:29:44.654114
5083 12:29:44.657173 CA PerBit enable=1, Macro0, CA PI delay=32
5084 12:29:44.657275
5085 12:29:44.660934 [CBTSetCACLKResult] CA Dly = 32
5086 12:29:44.661038 CS Dly: 5 (0~37)
5087 12:29:44.661130
5088 12:29:44.664319 ----->DramcWriteLeveling(PI) begin...
5089 12:29:44.664392 ==
5090 12:29:44.667598 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 12:29:44.674034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 12:29:44.674121 ==
5093 12:29:44.677797 Write leveling (Byte 0): 32 => 32
5094 12:29:44.680962 Write leveling (Byte 1): 29 => 29
5095 12:29:44.681046 DramcWriteLeveling(PI) end<-----
5096 12:29:44.681113
5097 12:29:44.684216 ==
5098 12:29:44.687474 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 12:29:44.690956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 12:29:44.691055 ==
5101 12:29:44.694164 [Gating] SW mode calibration
5102 12:29:44.700775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 12:29:44.704207 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 12:29:44.711117 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5105 12:29:44.713989 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:29:44.717668 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 12:29:44.723924 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 12:29:44.727686 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 12:29:44.730940 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 12:29:44.737375 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5111 12:29:44.740704 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
5112 12:29:44.743950 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5113 12:29:44.750613 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:29:44.754129 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 12:29:44.757442 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 12:29:44.763890 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:29:44.767262 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 12:29:44.770602 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5119 12:29:44.773907 0 15 28 | B1->B0 | 2424 3b3b | 0 1 | (0 0) (0 0)
5120 12:29:44.780836 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5121 12:29:44.784043 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:29:44.787136 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:29:44.793987 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 12:29:44.797372 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:29:44.800734 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 12:29:44.807425 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5127 12:29:44.810249 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5128 12:29:44.813530 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5129 12:29:44.820636 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:29:44.823676 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:29:44.827230 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:29:44.833602 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:29:44.836677 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:29:44.840027 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:29:44.846980 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:29:44.850369 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:29:44.853719 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:29:44.860341 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:29:44.863041 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:29:44.866947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:29:44.873529 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:29:44.876867 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 12:29:44.880192 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5144 12:29:44.886552 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5145 12:29:44.886636 Total UI for P1: 0, mck2ui 16
5146 12:29:44.893034 best dqsien dly found for B0: ( 1, 2, 26)
5147 12:29:44.896242 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 12:29:44.900058 Total UI for P1: 0, mck2ui 16
5149 12:29:44.903097 best dqsien dly found for B1: ( 1, 3, 0)
5150 12:29:44.906353 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5151 12:29:44.909701 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5152 12:29:44.909819
5153 12:29:44.913101 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5154 12:29:44.916335 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5155 12:29:44.919546 [Gating] SW calibration Done
5156 12:29:44.919666 ==
5157 12:29:44.922913 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 12:29:44.926024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 12:29:44.926139 ==
5160 12:29:44.929781 RX Vref Scan: 0
5161 12:29:44.929888
5162 12:29:44.932986 RX Vref 0 -> 0, step: 1
5163 12:29:44.933111
5164 12:29:44.933204 RX Delay -80 -> 252, step: 8
5165 12:29:44.939863 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5166 12:29:44.943035 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5167 12:29:44.946210 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5168 12:29:44.950115 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5169 12:29:44.953316 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5170 12:29:44.956721 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5171 12:29:44.963365 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5172 12:29:44.966043 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5173 12:29:44.969392 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5174 12:29:44.973234 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5175 12:29:44.976636 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5176 12:29:44.980067 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5177 12:29:44.986676 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5178 12:29:44.989913 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5179 12:29:44.993064 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5180 12:29:44.996406 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5181 12:29:44.996521 ==
5182 12:29:44.999579 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 12:29:45.006005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 12:29:45.006117 ==
5185 12:29:45.006212 DQS Delay:
5186 12:29:45.009193 DQS0 = 0, DQS1 = 0
5187 12:29:45.009295 DQM Delay:
5188 12:29:45.009388 DQM0 = 105, DQM1 = 96
5189 12:29:45.013036 DQ Delay:
5190 12:29:45.016437 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5191 12:29:45.019811 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5192 12:29:45.023013 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =91
5193 12:29:45.026379 DQ12 =103, DQ13 =103, DQ14 =107, DQ15 =99
5194 12:29:45.026481
5195 12:29:45.026573
5196 12:29:45.026665 ==
5197 12:29:45.029738 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 12:29:45.032926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 12:29:45.032999 ==
5200 12:29:45.033092
5201 12:29:45.033182
5202 12:29:45.036206 TX Vref Scan disable
5203 12:29:45.039414 == TX Byte 0 ==
5204 12:29:45.042642 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5205 12:29:45.045717 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5206 12:29:45.049608 == TX Byte 1 ==
5207 12:29:45.052624 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 12:29:45.055769 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 12:29:45.055846 ==
5210 12:29:45.059025 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 12:29:45.065940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 12:29:45.066058 ==
5213 12:29:45.066155
5214 12:29:45.066264
5215 12:29:45.066372 TX Vref Scan disable
5216 12:29:45.069934 == TX Byte 0 ==
5217 12:29:45.073233 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5218 12:29:45.079724 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5219 12:29:45.079808 == TX Byte 1 ==
5220 12:29:45.083160 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5221 12:29:45.089861 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5222 12:29:45.089961
5223 12:29:45.090054 [DATLAT]
5224 12:29:45.090147 Freq=933, CH0 RK0
5225 12:29:45.090235
5226 12:29:45.093222 DATLAT Default: 0xd
5227 12:29:45.093318 0, 0xFFFF, sum = 0
5228 12:29:45.096266 1, 0xFFFF, sum = 0
5229 12:29:45.096365 2, 0xFFFF, sum = 0
5230 12:29:45.099603 3, 0xFFFF, sum = 0
5231 12:29:45.102838 4, 0xFFFF, sum = 0
5232 12:29:45.102940 5, 0xFFFF, sum = 0
5233 12:29:45.106523 6, 0xFFFF, sum = 0
5234 12:29:45.106626 7, 0xFFFF, sum = 0
5235 12:29:45.109657 8, 0xFFFF, sum = 0
5236 12:29:45.109775 9, 0xFFFF, sum = 0
5237 12:29:45.112906 10, 0x0, sum = 1
5238 12:29:45.113008 11, 0x0, sum = 2
5239 12:29:45.116030 12, 0x0, sum = 3
5240 12:29:45.116136 13, 0x0, sum = 4
5241 12:29:45.116234 best_step = 11
5242 12:29:45.116323
5243 12:29:45.119882 ==
5244 12:29:45.123181 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 12:29:45.126538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 12:29:45.126655 ==
5247 12:29:45.126751 RX Vref Scan: 1
5248 12:29:45.126856
5249 12:29:45.129966 RX Vref 0 -> 0, step: 1
5250 12:29:45.130112
5251 12:29:45.132554 RX Delay -45 -> 252, step: 4
5252 12:29:45.132671
5253 12:29:45.135783 Set Vref, RX VrefLevel [Byte0]: 54
5254 12:29:45.139638 [Byte1]: 48
5255 12:29:45.139738
5256 12:29:45.142381 Final RX Vref Byte 0 = 54 to rank0
5257 12:29:45.145765 Final RX Vref Byte 1 = 48 to rank0
5258 12:29:45.149022 Final RX Vref Byte 0 = 54 to rank1
5259 12:29:45.152947 Final RX Vref Byte 1 = 48 to rank1==
5260 12:29:45.155903 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 12:29:45.159023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 12:29:45.162687 ==
5263 12:29:45.162791 DQS Delay:
5264 12:29:45.162884 DQS0 = 0, DQS1 = 0
5265 12:29:45.165875 DQM Delay:
5266 12:29:45.165991 DQM0 = 104, DQM1 = 96
5267 12:29:45.169052 DQ Delay:
5268 12:29:45.172767 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =104
5269 12:29:45.175932 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5270 12:29:45.179137 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5271 12:29:45.182320 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =102
5272 12:29:45.182438
5273 12:29:45.182532
5274 12:29:45.188977 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5275 12:29:45.192390 CH0 RK0: MR19=505, MR18=2E26
5276 12:29:45.199072 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5277 12:29:45.199186
5278 12:29:45.202368 ----->DramcWriteLeveling(PI) begin...
5279 12:29:45.202473 ==
5280 12:29:45.205664 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 12:29:45.208982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 12:29:45.209083 ==
5283 12:29:45.212175 Write leveling (Byte 0): 34 => 34
5284 12:29:45.215785 Write leveling (Byte 1): 29 => 29
5285 12:29:45.218858 DramcWriteLeveling(PI) end<-----
5286 12:29:45.218962
5287 12:29:45.219059 ==
5288 12:29:45.222031 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 12:29:45.225866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:29:45.229073 ==
5291 12:29:45.229187 [Gating] SW mode calibration
5292 12:29:45.235763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 12:29:45.242379 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 12:29:45.245592 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5295 12:29:45.252227 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 12:29:45.255549 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 12:29:45.258998 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 12:29:45.265942 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 12:29:45.269081 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 12:29:45.272210 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5301 12:29:45.278716 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 0)
5302 12:29:45.281958 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:29:45.285613 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 12:29:45.292196 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 12:29:45.295608 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 12:29:45.298910 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 12:29:45.305425 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 12:29:45.308646 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 12:29:45.312100 0 15 28 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
5310 12:29:45.318750 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:29:45.321995 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:29:45.325092 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 12:29:45.332062 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 12:29:45.335255 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 12:29:45.338436 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 12:29:45.341856 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 12:29:45.348368 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5318 12:29:45.351742 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5319 12:29:45.354971 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:29:45.362337 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:29:45.365674 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:29:45.368877 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:29:45.375079 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:29:45.378876 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:29:45.382017 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:29:45.388398 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:29:45.392080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:29:45.395233 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:29:45.401904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:29:45.405340 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:29:45.408637 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:29:45.415329 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:29:45.418128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5334 12:29:45.421407 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 12:29:45.425306 Total UI for P1: 0, mck2ui 16
5336 12:29:45.428638 best dqsien dly found for B0: ( 1, 2, 28)
5337 12:29:45.431809 Total UI for P1: 0, mck2ui 16
5338 12:29:45.434985 best dqsien dly found for B1: ( 1, 2, 28)
5339 12:29:45.438163 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5340 12:29:45.441967 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5341 12:29:45.442071
5342 12:29:45.445181 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 12:29:45.451374 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5344 12:29:45.451488 [Gating] SW calibration Done
5345 12:29:45.451586 ==
5346 12:29:45.454881 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 12:29:45.461404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 12:29:45.461511 ==
5349 12:29:45.461611 RX Vref Scan: 0
5350 12:29:45.461703
5351 12:29:45.464669 RX Vref 0 -> 0, step: 1
5352 12:29:45.464767
5353 12:29:45.468108 RX Delay -80 -> 252, step: 8
5354 12:29:45.471458 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5355 12:29:45.474696 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5356 12:29:45.478499 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5357 12:29:45.484796 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5358 12:29:45.488002 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5359 12:29:45.491632 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5360 12:29:45.494874 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5361 12:29:45.498020 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5362 12:29:45.501587 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5363 12:29:45.508007 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5364 12:29:45.510887 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5365 12:29:45.514779 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5366 12:29:45.517568 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5367 12:29:45.521025 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5368 12:29:45.524435 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5369 12:29:45.531027 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5370 12:29:45.531174 ==
5371 12:29:45.534273 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 12:29:45.537600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 12:29:45.537710 ==
5374 12:29:45.537816 DQS Delay:
5375 12:29:45.541407 DQS0 = 0, DQS1 = 0
5376 12:29:45.541508 DQM Delay:
5377 12:29:45.544572 DQM0 = 104, DQM1 = 92
5378 12:29:45.544656 DQ Delay:
5379 12:29:45.547782 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5380 12:29:45.550940 DQ4 =103, DQ5 =99, DQ6 =107, DQ7 =115
5381 12:29:45.554654 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5382 12:29:45.557785 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5383 12:29:45.557867
5384 12:29:45.557932
5385 12:29:45.558009 ==
5386 12:29:45.561207 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 12:29:45.564310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 12:29:45.564411 ==
5389 12:29:45.567603
5390 12:29:45.567685
5391 12:29:45.567750 TX Vref Scan disable
5392 12:29:45.570927 == TX Byte 0 ==
5393 12:29:45.574321 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5394 12:29:45.577566 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5395 12:29:45.581438 == TX Byte 1 ==
5396 12:29:45.584771 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5397 12:29:45.588098 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5398 12:29:45.588181 ==
5399 12:29:45.591214 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 12:29:45.598063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 12:29:45.598151 ==
5402 12:29:45.598217
5403 12:29:45.598277
5404 12:29:45.601063 TX Vref Scan disable
5405 12:29:45.601150 == TX Byte 0 ==
5406 12:29:45.607905 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5407 12:29:45.610681 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5408 12:29:45.610756 == TX Byte 1 ==
5409 12:29:45.617636 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5410 12:29:45.621089 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5411 12:29:45.621189
5412 12:29:45.621284 [DATLAT]
5413 12:29:45.623847 Freq=933, CH0 RK1
5414 12:29:45.623929
5415 12:29:45.623994 DATLAT Default: 0xb
5416 12:29:45.627229 0, 0xFFFF, sum = 0
5417 12:29:45.627337 1, 0xFFFF, sum = 0
5418 12:29:45.630643 2, 0xFFFF, sum = 0
5419 12:29:45.630726 3, 0xFFFF, sum = 0
5420 12:29:45.634465 4, 0xFFFF, sum = 0
5421 12:29:45.634549 5, 0xFFFF, sum = 0
5422 12:29:45.637734 6, 0xFFFF, sum = 0
5423 12:29:45.637818 7, 0xFFFF, sum = 0
5424 12:29:45.641015 8, 0xFFFF, sum = 0
5425 12:29:45.644466 9, 0xFFFF, sum = 0
5426 12:29:45.644549 10, 0x0, sum = 1
5427 12:29:45.644615 11, 0x0, sum = 2
5428 12:29:45.647666 12, 0x0, sum = 3
5429 12:29:45.647750 13, 0x0, sum = 4
5430 12:29:45.650792 best_step = 11
5431 12:29:45.650874
5432 12:29:45.650939 ==
5433 12:29:45.653970 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 12:29:45.657144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 12:29:45.657234 ==
5436 12:29:45.660994 RX Vref Scan: 0
5437 12:29:45.661075
5438 12:29:45.661140 RX Vref 0 -> 0, step: 1
5439 12:29:45.661199
5440 12:29:45.663969 RX Delay -53 -> 252, step: 4
5441 12:29:45.670974 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5442 12:29:45.674306 iDelay=195, Bit 1, Center 108 (23 ~ 194) 172
5443 12:29:45.677610 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5444 12:29:45.680937 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5445 12:29:45.684738 iDelay=195, Bit 4, Center 104 (15 ~ 194) 180
5446 12:29:45.691437 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5447 12:29:45.694865 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5448 12:29:45.698067 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5449 12:29:45.701217 iDelay=195, Bit 8, Center 84 (-1 ~ 170) 172
5450 12:29:45.704366 iDelay=195, Bit 9, Center 86 (3 ~ 170) 168
5451 12:29:45.708071 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5452 12:29:45.714521 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5453 12:29:45.717630 iDelay=195, Bit 12, Center 98 (15 ~ 182) 168
5454 12:29:45.720942 iDelay=195, Bit 13, Center 98 (15 ~ 182) 168
5455 12:29:45.724561 iDelay=195, Bit 14, Center 104 (23 ~ 186) 164
5456 12:29:45.727815 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5457 12:29:45.730966 ==
5458 12:29:45.734318 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 12:29:45.737575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 12:29:45.737698 ==
5461 12:29:45.737819 DQS Delay:
5462 12:29:45.740980 DQS0 = 0, DQS1 = 0
5463 12:29:45.741106 DQM Delay:
5464 12:29:45.744303 DQM0 = 104, DQM1 = 94
5465 12:29:45.744423 DQ Delay:
5466 12:29:45.747697 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5467 12:29:45.750973 DQ4 =104, DQ5 =98, DQ6 =108, DQ7 =110
5468 12:29:45.754310 DQ8 =84, DQ9 =86, DQ10 =94, DQ11 =88
5469 12:29:45.757540 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =102
5470 12:29:45.757623
5471 12:29:45.757689
5472 12:29:45.767579 [DQSOSCAuto] RK1, (LSB)MR18= 0x2800, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5473 12:29:45.767684 CH0 RK1: MR19=505, MR18=2800
5474 12:29:45.773991 CH0_RK1: MR19=0x505, MR18=0x2800, DQSOSC=409, MR23=63, INC=64, DEC=43
5475 12:29:45.777720 [RxdqsGatingPostProcess] freq 933
5476 12:29:45.784359 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5477 12:29:45.787647 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 12:29:45.790817 best DQS1 dly(2T, 0.5T) = (0, 11)
5479 12:29:45.794255 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 12:29:45.797053 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5481 12:29:45.800405 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 12:29:45.800504 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 12:29:45.803736 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 12:29:45.806904 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 12:29:45.810723 Pre-setting of DQS Precalculation
5486 12:29:45.817469 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5487 12:29:45.817600 ==
5488 12:29:45.820568 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 12:29:45.823684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 12:29:45.823835 ==
5491 12:29:45.830634 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5492 12:29:45.837079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5493 12:29:45.840434 [CA 0] Center 36 (6~67) winsize 62
5494 12:29:45.843839 [CA 1] Center 37 (6~68) winsize 63
5495 12:29:45.847227 [CA 2] Center 34 (4~65) winsize 62
5496 12:29:45.850693 [CA 3] Center 34 (4~65) winsize 62
5497 12:29:45.853960 [CA 4] Center 34 (4~65) winsize 62
5498 12:29:45.857374 [CA 5] Center 33 (3~64) winsize 62
5499 12:29:45.857452
5500 12:29:45.860021 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5501 12:29:45.860095
5502 12:29:45.864079 [CATrainingPosCal] consider 1 rank data
5503 12:29:45.867163 u2DelayCellTimex100 = 270/100 ps
5504 12:29:45.870343 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5505 12:29:45.873516 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5506 12:29:45.876752 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 12:29:45.880590 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 12:29:45.883617 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 12:29:45.886643 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5510 12:29:45.886724
5511 12:29:45.890386 CA PerBit enable=1, Macro0, CA PI delay=33
5512 12:29:45.893733
5513 12:29:45.893810 [CBTSetCACLKResult] CA Dly = 33
5514 12:29:45.897079 CS Dly: 6 (0~37)
5515 12:29:45.897165 ==
5516 12:29:45.900324 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 12:29:45.903614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 12:29:45.903695 ==
5519 12:29:45.910465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 12:29:45.917061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 12:29:45.920201 [CA 0] Center 36 (6~67) winsize 62
5522 12:29:45.923457 [CA 1] Center 37 (6~68) winsize 63
5523 12:29:45.926789 [CA 2] Center 35 (4~66) winsize 63
5524 12:29:45.930381 [CA 3] Center 34 (4~65) winsize 62
5525 12:29:45.933625 [CA 4] Center 34 (4~65) winsize 62
5526 12:29:45.936789 [CA 5] Center 34 (4~64) winsize 61
5527 12:29:45.936876
5528 12:29:45.940115 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 12:29:45.940201
5530 12:29:45.943231 [CATrainingPosCal] consider 2 rank data
5531 12:29:45.946479 u2DelayCellTimex100 = 270/100 ps
5532 12:29:45.949925 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5533 12:29:45.953216 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5534 12:29:45.956530 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5535 12:29:45.959954 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5536 12:29:45.963311 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5537 12:29:45.966711 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5538 12:29:45.966798
5539 12:29:45.973410 CA PerBit enable=1, Macro0, CA PI delay=34
5540 12:29:45.973504
5541 12:29:45.976558 [CBTSetCACLKResult] CA Dly = 34
5542 12:29:45.976646 CS Dly: 7 (0~40)
5543 12:29:45.976715
5544 12:29:45.979794 ----->DramcWriteLeveling(PI) begin...
5545 12:29:45.979923 ==
5546 12:29:45.982866 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 12:29:45.986637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 12:29:45.986723 ==
5549 12:29:45.989626 Write leveling (Byte 0): 26 => 26
5550 12:29:45.993332 Write leveling (Byte 1): 28 => 28
5551 12:29:45.996472 DramcWriteLeveling(PI) end<-----
5552 12:29:45.996566
5553 12:29:45.996633 ==
5554 12:29:45.999726 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 12:29:46.006454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 12:29:46.006548 ==
5557 12:29:46.006617 [Gating] SW mode calibration
5558 12:29:46.016416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5559 12:29:46.019669 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5560 12:29:46.022922 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:29:46.029287 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:29:46.033176 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 12:29:46.036159 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:29:46.043243 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 12:29:46.046450 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5566 12:29:46.049545 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5567 12:29:46.056071 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5568 12:29:46.059441 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:29:46.062741 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:29:46.069529 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 12:29:46.072723 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 12:29:46.076035 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 12:29:46.083226 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 12:29:46.086480 0 15 24 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0)
5575 12:29:46.089655 0 15 28 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
5576 12:29:46.095984 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:29:46.099607 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:29:46.102682 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 12:29:46.109909 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:29:46.112645 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 12:29:46.116052 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 12:29:46.119390 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5583 12:29:46.126047 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5584 12:29:46.129369 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:29:46.133091 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:29:46.139380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:29:46.142433 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:29:46.146176 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:29:46.152575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:29:46.156204 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:29:46.159473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:29:46.166204 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:29:46.169569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:29:46.172920 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:29:46.179023 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:29:46.182318 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:29:46.185588 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:29:46.192172 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5599 12:29:46.195472 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 12:29:46.199276 Total UI for P1: 0, mck2ui 16
5601 12:29:46.202499 best dqsien dly found for B0: ( 1, 2, 24)
5602 12:29:46.205659 Total UI for P1: 0, mck2ui 16
5603 12:29:46.208867 best dqsien dly found for B1: ( 1, 2, 24)
5604 12:29:46.212620 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5605 12:29:46.215913 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5606 12:29:46.216013
5607 12:29:46.219286 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5608 12:29:46.222045 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 12:29:46.225454 [Gating] SW calibration Done
5610 12:29:46.225539 ==
5611 12:29:46.228862 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 12:29:46.232358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:29:46.235642 ==
5614 12:29:46.235728 RX Vref Scan: 0
5615 12:29:46.235795
5616 12:29:46.238977 RX Vref 0 -> 0, step: 1
5617 12:29:46.239062
5618 12:29:46.239130 RX Delay -80 -> 252, step: 8
5619 12:29:46.246039 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5620 12:29:46.249037 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5621 12:29:46.252654 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5622 12:29:46.255819 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5623 12:29:46.259089 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5624 12:29:46.262140 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5625 12:29:46.269224 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5626 12:29:46.272637 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5627 12:29:46.275959 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5628 12:29:46.279196 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5629 12:29:46.282624 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 12:29:46.286004 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5631 12:29:46.292530 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5632 12:29:46.295663 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5633 12:29:46.298919 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5634 12:29:46.302133 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5635 12:29:46.302240 ==
5636 12:29:46.305453 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 12:29:46.312404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 12:29:46.312518 ==
5639 12:29:46.312628 DQS Delay:
5640 12:29:46.315642 DQS0 = 0, DQS1 = 0
5641 12:29:46.315759 DQM Delay:
5642 12:29:46.315858 DQM0 = 102, DQM1 = 98
5643 12:29:46.318914 DQ Delay:
5644 12:29:46.322183 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5645 12:29:46.325582 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5646 12:29:46.328950 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5647 12:29:46.332230 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5648 12:29:46.332350
5649 12:29:46.332445
5650 12:29:46.332545 ==
5651 12:29:46.335577 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 12:29:46.338902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 12:29:46.339021 ==
5654 12:29:46.339120
5655 12:29:46.339213
5656 12:29:46.342250 TX Vref Scan disable
5657 12:29:46.345489 == TX Byte 0 ==
5658 12:29:46.349347 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5659 12:29:46.352524 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5660 12:29:46.355526 == TX Byte 1 ==
5661 12:29:46.359201 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5662 12:29:46.362320 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5663 12:29:46.362420 ==
5664 12:29:46.365432 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 12:29:46.369206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 12:29:46.372406 ==
5667 12:29:46.372506
5668 12:29:46.372597
5669 12:29:46.372686 TX Vref Scan disable
5670 12:29:46.375757 == TX Byte 0 ==
5671 12:29:46.379208 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 12:29:46.382499 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 12:29:46.385959 == TX Byte 1 ==
5674 12:29:46.389277 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5675 12:29:46.392617 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5676 12:29:46.395995
5677 12:29:46.396096 [DATLAT]
5678 12:29:46.396186 Freq=933, CH1 RK0
5679 12:29:46.396272
5680 12:29:46.399285 DATLAT Default: 0xd
5681 12:29:46.399403 0, 0xFFFF, sum = 0
5682 12:29:46.402325 1, 0xFFFF, sum = 0
5683 12:29:46.402423 2, 0xFFFF, sum = 0
5684 12:29:46.406209 3, 0xFFFF, sum = 0
5685 12:29:46.406309 4, 0xFFFF, sum = 0
5686 12:29:46.408912 5, 0xFFFF, sum = 0
5687 12:29:46.412706 6, 0xFFFF, sum = 0
5688 12:29:46.412807 7, 0xFFFF, sum = 0
5689 12:29:46.415960 8, 0xFFFF, sum = 0
5690 12:29:46.416057 9, 0xFFFF, sum = 0
5691 12:29:46.419176 10, 0x0, sum = 1
5692 12:29:46.419264 11, 0x0, sum = 2
5693 12:29:46.419372 12, 0x0, sum = 3
5694 12:29:46.422410 13, 0x0, sum = 4
5695 12:29:46.422525 best_step = 11
5696 12:29:46.422632
5697 12:29:46.426012 ==
5698 12:29:46.426124 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 12:29:46.432659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 12:29:46.432771 ==
5701 12:29:46.432888 RX Vref Scan: 1
5702 12:29:46.433020
5703 12:29:46.436018 RX Vref 0 -> 0, step: 1
5704 12:29:46.436134
5705 12:29:46.439428 RX Delay -45 -> 252, step: 4
5706 12:29:46.439521
5707 12:29:46.442729 Set Vref, RX VrefLevel [Byte0]: 53
5708 12:29:46.446034 [Byte1]: 52
5709 12:29:46.446105
5710 12:29:46.449378 Final RX Vref Byte 0 = 53 to rank0
5711 12:29:46.452529 Final RX Vref Byte 1 = 52 to rank0
5712 12:29:46.455853 Final RX Vref Byte 0 = 53 to rank1
5713 12:29:46.459070 Final RX Vref Byte 1 = 52 to rank1==
5714 12:29:46.462283 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 12:29:46.465484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 12:29:46.465570 ==
5717 12:29:46.469155 DQS Delay:
5718 12:29:46.469236 DQS0 = 0, DQS1 = 0
5719 12:29:46.472256 DQM Delay:
5720 12:29:46.472327 DQM0 = 103, DQM1 = 100
5721 12:29:46.472391 DQ Delay:
5722 12:29:46.475603 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =100
5723 12:29:46.478825 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5724 12:29:46.485514 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5725 12:29:46.488845 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5726 12:29:46.488920
5727 12:29:46.488983
5728 12:29:46.495598 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5729 12:29:46.498988 CH1 RK0: MR19=505, MR18=1830
5730 12:29:46.505579 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5731 12:29:46.505656
5732 12:29:46.508801 ----->DramcWriteLeveling(PI) begin...
5733 12:29:46.508881 ==
5734 12:29:46.512607 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 12:29:46.515856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:29:46.515938 ==
5737 12:29:46.518489 Write leveling (Byte 0): 28 => 28
5738 12:29:46.522325 Write leveling (Byte 1): 29 => 29
5739 12:29:46.525410 DramcWriteLeveling(PI) end<-----
5740 12:29:46.525485
5741 12:29:46.525597 ==
5742 12:29:46.528521 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 12:29:46.532299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 12:29:46.532372 ==
5745 12:29:46.535616 [Gating] SW mode calibration
5746 12:29:46.542364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 12:29:46.548953 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 12:29:46.552332 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 12:29:46.558843 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:29:46.562060 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 12:29:46.565148 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 12:29:46.572010 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 12:29:46.575540 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 12:29:46.578604 0 14 24 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (1 1)
5755 12:29:46.581890 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5756 12:29:46.589131 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 12:29:46.591861 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:29:46.595154 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 12:29:46.602085 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 12:29:46.605452 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 12:29:46.608832 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 12:29:46.615291 0 15 24 | B1->B0 | 3434 2a2a | 0 1 | (0 0) (0 0)
5763 12:29:46.618524 0 15 28 | B1->B0 | 4646 3b3b | 0 1 | (0 0) (1 1)
5764 12:29:46.622184 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 12:29:46.628472 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:29:46.632118 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:29:46.635320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 12:29:46.642246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 12:29:46.645401 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 12:29:46.648848 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5771 12:29:46.655426 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:29:46.658678 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5773 12:29:46.662063 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:29:46.668670 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:29:46.671883 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:29:46.674941 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:29:46.681830 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:29:46.684927 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:29:46.688536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:29:46.694985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:29:46.698351 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:29:46.701709 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:29:46.708462 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:29:46.711801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:29:46.715207 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5786 12:29:46.718506 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5787 12:29:46.724936 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 12:29:46.728196 Total UI for P1: 0, mck2ui 16
5789 12:29:46.731899 best dqsien dly found for B0: ( 1, 2, 24)
5790 12:29:46.735038 Total UI for P1: 0, mck2ui 16
5791 12:29:46.738187 best dqsien dly found for B1: ( 1, 2, 22)
5792 12:29:46.741338 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5793 12:29:46.745138 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5794 12:29:46.745238
5795 12:29:46.748266 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5796 12:29:46.751437 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5797 12:29:46.754597 [Gating] SW calibration Done
5798 12:29:46.754676 ==
5799 12:29:46.757978 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 12:29:46.761308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 12:29:46.761408 ==
5802 12:29:46.765319 RX Vref Scan: 0
5803 12:29:46.765393
5804 12:29:46.765455 RX Vref 0 -> 0, step: 1
5805 12:29:46.765514
5806 12:29:46.768699 RX Delay -80 -> 252, step: 8
5807 12:29:46.775270 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5808 12:29:46.778509 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5809 12:29:46.781795 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5810 12:29:46.784823 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5811 12:29:46.788415 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5812 12:29:46.791570 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5813 12:29:46.794744 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5814 12:29:46.801567 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5815 12:29:46.804917 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5816 12:29:46.808358 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5817 12:29:46.811094 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5818 12:29:46.814444 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5819 12:29:46.817862 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5820 12:29:46.824581 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5821 12:29:46.827981 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5822 12:29:46.831160 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5823 12:29:46.831261 ==
5824 12:29:46.834572 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 12:29:46.837895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 12:29:46.841045 ==
5827 12:29:46.841128 DQS Delay:
5828 12:29:46.841194 DQS0 = 0, DQS1 = 0
5829 12:29:46.844624 DQM Delay:
5830 12:29:46.844710 DQM0 = 101, DQM1 = 98
5831 12:29:46.847823 DQ Delay:
5832 12:29:46.850974 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =95
5833 12:29:46.854717 DQ4 =95, DQ5 =119, DQ6 =107, DQ7 =99
5834 12:29:46.857875 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5835 12:29:46.861159 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5836 12:29:46.861251
5837 12:29:46.861374
5838 12:29:46.861463 ==
5839 12:29:46.864526 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 12:29:46.867753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 12:29:46.867825 ==
5842 12:29:46.867902
5843 12:29:46.867993
5844 12:29:46.871060 TX Vref Scan disable
5845 12:29:46.871127 == TX Byte 0 ==
5846 12:29:46.877840 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5847 12:29:46.881136 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5848 12:29:46.881220 == TX Byte 1 ==
5849 12:29:46.888504 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5850 12:29:46.891585 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5851 12:29:46.891699 ==
5852 12:29:46.894590 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 12:29:46.897692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 12:29:46.897776 ==
5855 12:29:46.897857
5856 12:29:46.897918
5857 12:29:46.901552 TX Vref Scan disable
5858 12:29:46.904481 == TX Byte 0 ==
5859 12:29:46.907705 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5860 12:29:46.911498 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5861 12:29:46.914913 == TX Byte 1 ==
5862 12:29:46.917641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5863 12:29:46.921104 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5864 12:29:46.921187
5865 12:29:46.924335 [DATLAT]
5866 12:29:46.924418 Freq=933, CH1 RK1
5867 12:29:46.924485
5868 12:29:46.927600 DATLAT Default: 0xb
5869 12:29:46.927686 0, 0xFFFF, sum = 0
5870 12:29:46.931021 1, 0xFFFF, sum = 0
5871 12:29:46.931105 2, 0xFFFF, sum = 0
5872 12:29:46.934178 3, 0xFFFF, sum = 0
5873 12:29:46.934262 4, 0xFFFF, sum = 0
5874 12:29:46.937583 5, 0xFFFF, sum = 0
5875 12:29:46.937668 6, 0xFFFF, sum = 0
5876 12:29:46.941027 7, 0xFFFF, sum = 0
5877 12:29:46.941111 8, 0xFFFF, sum = 0
5878 12:29:46.944175 9, 0xFFFF, sum = 0
5879 12:29:46.944280 10, 0x0, sum = 1
5880 12:29:46.947973 11, 0x0, sum = 2
5881 12:29:46.948062 12, 0x0, sum = 3
5882 12:29:46.951223 13, 0x0, sum = 4
5883 12:29:46.951308 best_step = 11
5884 12:29:46.951414
5885 12:29:46.951477 ==
5886 12:29:46.954280 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 12:29:46.960723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 12:29:46.960808 ==
5889 12:29:46.960875 RX Vref Scan: 0
5890 12:29:46.960937
5891 12:29:46.964311 RX Vref 0 -> 0, step: 1
5892 12:29:46.964394
5893 12:29:46.967296 RX Delay -45 -> 252, step: 4
5894 12:29:46.970601 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5895 12:29:46.977416 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5896 12:29:46.980744 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5897 12:29:46.984132 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5898 12:29:46.987367 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5899 12:29:46.990783 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5900 12:29:46.994149 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5901 12:29:47.000578 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5902 12:29:47.004272 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5903 12:29:47.007548 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5904 12:29:47.010712 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5905 12:29:47.013864 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5906 12:29:47.020303 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5907 12:29:47.023707 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5908 12:29:47.027095 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5909 12:29:47.030521 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5910 12:29:47.030625 ==
5911 12:29:47.033726 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 12:29:47.040287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 12:29:47.040402 ==
5914 12:29:47.040500 DQS Delay:
5915 12:29:47.043729 DQS0 = 0, DQS1 = 0
5916 12:29:47.043835 DQM Delay:
5917 12:29:47.046879 DQM0 = 104, DQM1 = 100
5918 12:29:47.046982 DQ Delay:
5919 12:29:47.050175 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5920 12:29:47.053480 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5921 12:29:47.056646 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5922 12:29:47.060433 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5923 12:29:47.060541
5924 12:29:47.060635
5925 12:29:47.069957 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5926 12:29:47.070067 CH1 RK1: MR19=505, MR18=2F02
5927 12:29:47.076697 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5928 12:29:47.079892 [RxdqsGatingPostProcess] freq 933
5929 12:29:47.086696 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 12:29:47.089952 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 12:29:47.093227 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 12:29:47.096606 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 12:29:47.099901 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 12:29:47.100007 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 12:29:47.103106 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 12:29:47.106399 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 12:29:47.110197 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 12:29:47.113547 Pre-setting of DQS Precalculation
5939 12:29:47.119850 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 12:29:47.127007 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 12:29:47.133115 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 12:29:47.133200
5943 12:29:47.133266
5944 12:29:47.136374 [Calibration Summary] 1866 Mbps
5945 12:29:47.136484 CH 0, Rank 0
5946 12:29:47.139694 SW Impedance : PASS
5947 12:29:47.143127 DUTY Scan : NO K
5948 12:29:47.143211 ZQ Calibration : PASS
5949 12:29:47.146485 Jitter Meter : NO K
5950 12:29:47.149827 CBT Training : PASS
5951 12:29:47.149911 Write leveling : PASS
5952 12:29:47.153105 RX DQS gating : PASS
5953 12:29:47.156497 RX DQ/DQS(RDDQC) : PASS
5954 12:29:47.156581 TX DQ/DQS : PASS
5955 12:29:47.159847 RX DATLAT : PASS
5956 12:29:47.163095 RX DQ/DQS(Engine): PASS
5957 12:29:47.163179 TX OE : NO K
5958 12:29:47.163247 All Pass.
5959 12:29:47.163310
5960 12:29:47.166384 CH 0, Rank 1
5961 12:29:47.170237 SW Impedance : PASS
5962 12:29:47.170336 DUTY Scan : NO K
5963 12:29:47.173552 ZQ Calibration : PASS
5964 12:29:47.173636 Jitter Meter : NO K
5965 12:29:47.176698 CBT Training : PASS
5966 12:29:47.179999 Write leveling : PASS
5967 12:29:47.180113 RX DQS gating : PASS
5968 12:29:47.183118 RX DQ/DQS(RDDQC) : PASS
5969 12:29:47.186285 TX DQ/DQS : PASS
5970 12:29:47.186390 RX DATLAT : PASS
5971 12:29:47.189648 RX DQ/DQS(Engine): PASS
5972 12:29:47.192944 TX OE : NO K
5973 12:29:47.193047 All Pass.
5974 12:29:47.193155
5975 12:29:47.193246 CH 1, Rank 0
5976 12:29:47.196713 SW Impedance : PASS
5977 12:29:47.200253 DUTY Scan : NO K
5978 12:29:47.200355 ZQ Calibration : PASS
5979 12:29:47.203658 Jitter Meter : NO K
5980 12:29:47.206651 CBT Training : PASS
5981 12:29:47.206756 Write leveling : PASS
5982 12:29:47.210014 RX DQS gating : PASS
5983 12:29:47.210098 RX DQ/DQS(RDDQC) : PASS
5984 12:29:47.213407 TX DQ/DQS : PASS
5985 12:29:47.216540 RX DATLAT : PASS
5986 12:29:47.216624 RX DQ/DQS(Engine): PASS
5987 12:29:47.219775 TX OE : NO K
5988 12:29:47.219859 All Pass.
5989 12:29:47.219926
5990 12:29:47.223376 CH 1, Rank 1
5991 12:29:47.223488 SW Impedance : PASS
5992 12:29:47.226534 DUTY Scan : NO K
5993 12:29:47.229871 ZQ Calibration : PASS
5994 12:29:47.229956 Jitter Meter : NO K
5995 12:29:47.233048 CBT Training : PASS
5996 12:29:47.236285 Write leveling : PASS
5997 12:29:47.236384 RX DQS gating : PASS
5998 12:29:47.239660 RX DQ/DQS(RDDQC) : PASS
5999 12:29:47.242983 TX DQ/DQS : PASS
6000 12:29:47.243067 RX DATLAT : PASS
6001 12:29:47.246197 RX DQ/DQS(Engine): PASS
6002 12:29:47.249535 TX OE : NO K
6003 12:29:47.249620 All Pass.
6004 12:29:47.249686
6005 12:29:47.249747 DramC Write-DBI off
6006 12:29:47.252928 PER_BANK_REFRESH: Hybrid Mode
6007 12:29:47.256179 TX_TRACKING: ON
6008 12:29:47.262805 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 12:29:47.266074 [FAST_K] Save calibration result to emmc
6010 12:29:47.272760 dramc_set_vcore_voltage set vcore to 650000
6011 12:29:47.272845 Read voltage for 400, 6
6012 12:29:47.276000 Vio18 = 0
6013 12:29:47.276085 Vcore = 650000
6014 12:29:47.276152 Vdram = 0
6015 12:29:47.279776 Vddq = 0
6016 12:29:47.279860 Vmddr = 0
6017 12:29:47.282923 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 12:29:47.289548 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 12:29:47.292801 MEM_TYPE=3, freq_sel=20
6020 12:29:47.296211 sv_algorithm_assistance_LP4_800
6021 12:29:47.299536 ============ PULL DRAM RESETB DOWN ============
6022 12:29:47.302730 ========== PULL DRAM RESETB DOWN end =========
6023 12:29:47.306044 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 12:29:47.309278 ===================================
6025 12:29:47.312430 LPDDR4 DRAM CONFIGURATION
6026 12:29:47.315850 ===================================
6027 12:29:47.319177 EX_ROW_EN[0] = 0x0
6028 12:29:47.319293 EX_ROW_EN[1] = 0x0
6029 12:29:47.322248 LP4Y_EN = 0x0
6030 12:29:47.322369 WORK_FSP = 0x0
6031 12:29:47.325969 WL = 0x2
6032 12:29:47.326078 RL = 0x2
6033 12:29:47.329086 BL = 0x2
6034 12:29:47.332211 RPST = 0x0
6035 12:29:47.332329 RD_PRE = 0x0
6036 12:29:47.335533 WR_PRE = 0x1
6037 12:29:47.335641 WR_PST = 0x0
6038 12:29:47.338766 DBI_WR = 0x0
6039 12:29:47.338881 DBI_RD = 0x0
6040 12:29:47.342161 OTF = 0x1
6041 12:29:47.345546 ===================================
6042 12:29:47.349499 ===================================
6043 12:29:47.349609 ANA top config
6044 12:29:47.352806 ===================================
6045 12:29:47.356011 DLL_ASYNC_EN = 0
6046 12:29:47.356119 ALL_SLAVE_EN = 1
6047 12:29:47.359244 NEW_RANK_MODE = 1
6048 12:29:47.362567 DLL_IDLE_MODE = 1
6049 12:29:47.366006 LP45_APHY_COMB_EN = 1
6050 12:29:47.369265 TX_ODT_DIS = 1
6051 12:29:47.369353 NEW_8X_MODE = 1
6052 12:29:47.372489 ===================================
6053 12:29:47.375900 ===================================
6054 12:29:47.379182 data_rate = 800
6055 12:29:47.382365 CKR = 1
6056 12:29:47.385475 DQ_P2S_RATIO = 4
6057 12:29:47.388692 ===================================
6058 12:29:47.392525 CA_P2S_RATIO = 4
6059 12:29:47.395632 DQ_CA_OPEN = 0
6060 12:29:47.395757 DQ_SEMI_OPEN = 1
6061 12:29:47.398836 CA_SEMI_OPEN = 1
6062 12:29:47.402121 CA_FULL_RATE = 0
6063 12:29:47.405491 DQ_CKDIV4_EN = 0
6064 12:29:47.408790 CA_CKDIV4_EN = 1
6065 12:29:47.412196 CA_PREDIV_EN = 0
6066 12:29:47.412282 PH8_DLY = 0
6067 12:29:47.415439 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 12:29:47.418878 DQ_AAMCK_DIV = 0
6069 12:29:47.422216 CA_AAMCK_DIV = 0
6070 12:29:47.425556 CA_ADMCK_DIV = 4
6071 12:29:47.428613 DQ_TRACK_CA_EN = 0
6072 12:29:47.428699 CA_PICK = 800
6073 12:29:47.431937 CA_MCKIO = 400
6074 12:29:47.435077 MCKIO_SEMI = 400
6075 12:29:47.438260 PLL_FREQ = 3016
6076 12:29:47.441608 DQ_UI_PI_RATIO = 32
6077 12:29:47.445495 CA_UI_PI_RATIO = 32
6078 12:29:47.448292 ===================================
6079 12:29:47.451593 ===================================
6080 12:29:47.455005 memory_type:LPDDR4
6081 12:29:47.455091 GP_NUM : 10
6082 12:29:47.458321 SRAM_EN : 1
6083 12:29:47.458406 MD32_EN : 0
6084 12:29:47.461867 ===================================
6085 12:29:47.465135 [ANA_INIT] >>>>>>>>>>>>>>
6086 12:29:47.468114 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 12:29:47.471465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 12:29:47.474894 ===================================
6089 12:29:47.478081 data_rate = 800,PCW = 0X7400
6090 12:29:47.482057 ===================================
6091 12:29:47.484693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 12:29:47.491726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 12:29:47.501721 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 12:29:47.504865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 12:29:47.508575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 12:29:47.511895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 12:29:47.515213 [ANA_INIT] flow start
6098 12:29:47.518328 [ANA_INIT] PLL >>>>>>>>
6099 12:29:47.518455 [ANA_INIT] PLL <<<<<<<<
6100 12:29:47.521660 [ANA_INIT] MIDPI >>>>>>>>
6101 12:29:47.525142 [ANA_INIT] MIDPI <<<<<<<<
6102 12:29:47.525229 [ANA_INIT] DLL >>>>>>>>
6103 12:29:47.528556 [ANA_INIT] flow end
6104 12:29:47.531285 ============ LP4 DIFF to SE enter ============
6105 12:29:47.538411 ============ LP4 DIFF to SE exit ============
6106 12:29:47.538494 [ANA_INIT] <<<<<<<<<<<<<
6107 12:29:47.541547 [Flow] Enable top DCM control >>>>>
6108 12:29:47.544655 [Flow] Enable top DCM control <<<<<
6109 12:29:47.547945 Enable DLL master slave shuffle
6110 12:29:47.555087 ==============================================================
6111 12:29:47.555213 Gating Mode config
6112 12:29:47.561611 ==============================================================
6113 12:29:47.564463 Config description:
6114 12:29:47.571189 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 12:29:47.578437 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 12:29:47.584957 SELPH_MODE 0: By rank 1: By Phase
6117 12:29:47.591017 ==============================================================
6118 12:29:47.591133 GAT_TRACK_EN = 0
6119 12:29:47.594416 RX_GATING_MODE = 2
6120 12:29:47.597634 RX_GATING_TRACK_MODE = 2
6121 12:29:47.601313 SELPH_MODE = 1
6122 12:29:47.604482 PICG_EARLY_EN = 1
6123 12:29:47.607588 VALID_LAT_VALUE = 1
6124 12:29:47.614308 ==============================================================
6125 12:29:47.618177 Enter into Gating configuration >>>>
6126 12:29:47.621212 Exit from Gating configuration <<<<
6127 12:29:47.624349 Enter into DVFS_PRE_config >>>>>
6128 12:29:47.634309 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 12:29:47.637709 Exit from DVFS_PRE_config <<<<<
6130 12:29:47.641500 Enter into PICG configuration >>>>
6131 12:29:47.644730 Exit from PICG configuration <<<<
6132 12:29:47.647732 [RX_INPUT] configuration >>>>>
6133 12:29:47.647825 [RX_INPUT] configuration <<<<<
6134 12:29:47.654880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 12:29:47.660898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 12:29:47.664116 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 12:29:47.671315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 12:29:47.677914 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 12:29:47.684541 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 12:29:47.687863 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 12:29:47.691177 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 12:29:47.697290 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 12:29:47.700736 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 12:29:47.703947 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 12:29:47.711199 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 12:29:47.714233 ===================================
6147 12:29:47.714316 LPDDR4 DRAM CONFIGURATION
6148 12:29:47.717317 ===================================
6149 12:29:47.720543 EX_ROW_EN[0] = 0x0
6150 12:29:47.720623 EX_ROW_EN[1] = 0x0
6151 12:29:47.724352 LP4Y_EN = 0x0
6152 12:29:47.724430 WORK_FSP = 0x0
6153 12:29:47.727538 WL = 0x2
6154 12:29:47.730666 RL = 0x2
6155 12:29:47.730754 BL = 0x2
6156 12:29:47.734002 RPST = 0x0
6157 12:29:47.734087 RD_PRE = 0x0
6158 12:29:47.737314 WR_PRE = 0x1
6159 12:29:47.737390 WR_PST = 0x0
6160 12:29:47.740654 DBI_WR = 0x0
6161 12:29:47.740744 DBI_RD = 0x0
6162 12:29:47.743950 OTF = 0x1
6163 12:29:47.747165 ===================================
6164 12:29:47.750513 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 12:29:47.754339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 12:29:47.757462 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 12:29:47.760721 ===================================
6168 12:29:47.764056 LPDDR4 DRAM CONFIGURATION
6169 12:29:47.767274 ===================================
6170 12:29:47.770817 EX_ROW_EN[0] = 0x10
6171 12:29:47.770903 EX_ROW_EN[1] = 0x0
6172 12:29:47.774149 LP4Y_EN = 0x0
6173 12:29:47.774235 WORK_FSP = 0x0
6174 12:29:47.777363 WL = 0x2
6175 12:29:47.777448 RL = 0x2
6176 12:29:47.780723 BL = 0x2
6177 12:29:47.780808 RPST = 0x0
6178 12:29:47.784097 RD_PRE = 0x0
6179 12:29:47.784182 WR_PRE = 0x1
6180 12:29:47.787446 WR_PST = 0x0
6181 12:29:47.787531 DBI_WR = 0x0
6182 12:29:47.790774 DBI_RD = 0x0
6183 12:29:47.794118 OTF = 0x1
6184 12:29:47.797560 ===================================
6185 12:29:47.800858 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 12:29:47.806198 nWR fixed to 30
6187 12:29:47.809441 [ModeRegInit_LP4] CH0 RK0
6188 12:29:47.809526 [ModeRegInit_LP4] CH0 RK1
6189 12:29:47.812743 [ModeRegInit_LP4] CH1 RK0
6190 12:29:47.816079 [ModeRegInit_LP4] CH1 RK1
6191 12:29:47.816185 match AC timing 19
6192 12:29:47.822311 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 12:29:47.825448 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 12:29:47.829176 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 12:29:47.835445 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 12:29:47.839333 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 12:29:47.839438 ==
6198 12:29:47.842634 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 12:29:47.845976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 12:29:47.846067 ==
6201 12:29:47.852442 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 12:29:47.858907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6203 12:29:47.862629 [CA 0] Center 36 (8~64) winsize 57
6204 12:29:47.865779 [CA 1] Center 36 (8~64) winsize 57
6205 12:29:47.868981 [CA 2] Center 36 (8~64) winsize 57
6206 12:29:47.869093 [CA 3] Center 36 (8~64) winsize 57
6207 12:29:47.872186 [CA 4] Center 36 (8~64) winsize 57
6208 12:29:47.875608 [CA 5] Center 36 (8~64) winsize 57
6209 12:29:47.875687
6210 12:29:47.878953 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6211 12:29:47.879055
6212 12:29:47.885612 [CATrainingPosCal] consider 1 rank data
6213 12:29:47.885717 u2DelayCellTimex100 = 270/100 ps
6214 12:29:47.892192 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 12:29:47.895537 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 12:29:47.899451 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:29:47.902731 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 12:29:47.906091 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:29:47.909267 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 12:29:47.909376
6221 12:29:47.912419 CA PerBit enable=1, Macro0, CA PI delay=36
6222 12:29:47.912526
6223 12:29:47.915696 [CBTSetCACLKResult] CA Dly = 36
6224 12:29:47.919037 CS Dly: 1 (0~32)
6225 12:29:47.919148 ==
6226 12:29:47.922449 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 12:29:47.925694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 12:29:47.925802 ==
6229 12:29:47.932177 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 12:29:47.935780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 12:29:47.938906 [CA 0] Center 36 (8~64) winsize 57
6232 12:29:47.942476 [CA 1] Center 36 (8~64) winsize 57
6233 12:29:47.945449 [CA 2] Center 36 (8~64) winsize 57
6234 12:29:47.948828 [CA 3] Center 36 (8~64) winsize 57
6235 12:29:47.952046 [CA 4] Center 36 (8~64) winsize 57
6236 12:29:47.955461 [CA 5] Center 36 (8~64) winsize 57
6237 12:29:47.955571
6238 12:29:47.959212 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 12:29:47.959313
6240 12:29:47.962383 [CATrainingPosCal] consider 2 rank data
6241 12:29:47.965503 u2DelayCellTimex100 = 270/100 ps
6242 12:29:47.968720 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:29:47.971938 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:29:47.975101 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:29:47.982091 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:29:47.985413 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:29:47.988548 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:29:47.988651
6249 12:29:47.991948 CA PerBit enable=1, Macro0, CA PI delay=36
6250 12:29:47.992060
6251 12:29:47.995242 [CBTSetCACLKResult] CA Dly = 36
6252 12:29:47.995401 CS Dly: 1 (0~32)
6253 12:29:47.995475
6254 12:29:47.998498 ----->DramcWriteLeveling(PI) begin...
6255 12:29:47.998598 ==
6256 12:29:48.001873 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 12:29:48.008742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 12:29:48.008848 ==
6259 12:29:48.012064 Write leveling (Byte 0): 40 => 8
6260 12:29:48.015240 Write leveling (Byte 1): 40 => 8
6261 12:29:48.015387 DramcWriteLeveling(PI) end<-----
6262 12:29:48.015452
6263 12:29:48.018642 ==
6264 12:29:48.021916 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 12:29:48.025331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 12:29:48.025446 ==
6267 12:29:48.028604 [Gating] SW mode calibration
6268 12:29:48.035113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 12:29:48.038251 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 12:29:48.045326 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 12:29:48.048394 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 12:29:48.051992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 12:29:48.058612 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 12:29:48.062085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 12:29:48.065213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 12:29:48.071741 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 12:29:48.074927 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 12:29:48.078099 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 12:29:48.081442 Total UI for P1: 0, mck2ui 16
6280 12:29:48.085185 best dqsien dly found for B0: ( 0, 14, 24)
6281 12:29:48.088373 Total UI for P1: 0, mck2ui 16
6282 12:29:48.091635 best dqsien dly found for B1: ( 0, 14, 24)
6283 12:29:48.095017 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 12:29:48.098275 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 12:29:48.098349
6286 12:29:48.104966 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 12:29:48.108372 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 12:29:48.108471 [Gating] SW calibration Done
6289 12:29:48.111787 ==
6290 12:29:48.111870 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 12:29:48.118595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 12:29:48.118678 ==
6293 12:29:48.118742 RX Vref Scan: 0
6294 12:29:48.118801
6295 12:29:48.121800 RX Vref 0 -> 0, step: 1
6296 12:29:48.121880
6297 12:29:48.125159 RX Delay -410 -> 252, step: 16
6298 12:29:48.128451 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6299 12:29:48.131781 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6300 12:29:48.138254 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6301 12:29:48.141338 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6302 12:29:48.144535 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6303 12:29:48.147844 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6304 12:29:48.154769 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6305 12:29:48.157844 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6306 12:29:48.161063 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6307 12:29:48.164510 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6308 12:29:48.171228 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6309 12:29:48.174953 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6310 12:29:48.178135 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6311 12:29:48.181209 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6312 12:29:48.187940 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6313 12:29:48.191310 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6314 12:29:48.191413 ==
6315 12:29:48.194531 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 12:29:48.198323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 12:29:48.198404 ==
6318 12:29:48.201411 DQS Delay:
6319 12:29:48.201514 DQS0 = 27, DQS1 = 35
6320 12:29:48.204567 DQM Delay:
6321 12:29:48.204647 DQM0 = 11, DQM1 = 11
6322 12:29:48.204711 DQ Delay:
6323 12:29:48.207888 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6324 12:29:48.211253 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6325 12:29:48.214750 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6326 12:29:48.218193 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6327 12:29:48.218293
6328 12:29:48.218383
6329 12:29:48.218469 ==
6330 12:29:48.220949 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 12:29:48.227571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 12:29:48.227652 ==
6333 12:29:48.227747
6334 12:29:48.227807
6335 12:29:48.227863 TX Vref Scan disable
6336 12:29:48.230903 == TX Byte 0 ==
6337 12:29:48.234359 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 12:29:48.237691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 12:29:48.240913 == TX Byte 1 ==
6340 12:29:48.244291 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 12:29:48.247459 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 12:29:48.247557 ==
6343 12:29:48.250922 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 12:29:48.258232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 12:29:48.258650 ==
6346 12:29:48.258981
6347 12:29:48.259282
6348 12:29:48.259607 TX Vref Scan disable
6349 12:29:48.261493 == TX Byte 0 ==
6350 12:29:48.264463 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 12:29:48.268331 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 12:29:48.271688 == TX Byte 1 ==
6353 12:29:48.274995 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 12:29:48.278418 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 12:29:48.278843
6356 12:29:48.281415 [DATLAT]
6357 12:29:48.281837 Freq=400, CH0 RK0
6358 12:29:48.282175
6359 12:29:48.284692 DATLAT Default: 0xf
6360 12:29:48.285238 0, 0xFFFF, sum = 0
6361 12:29:48.288237 1, 0xFFFF, sum = 0
6362 12:29:48.288665 2, 0xFFFF, sum = 0
6363 12:29:48.291663 3, 0xFFFF, sum = 0
6364 12:29:48.292098 4, 0xFFFF, sum = 0
6365 12:29:48.294938 5, 0xFFFF, sum = 0
6366 12:29:48.295416 6, 0xFFFF, sum = 0
6367 12:29:48.298124 7, 0xFFFF, sum = 0
6368 12:29:48.298556 8, 0xFFFF, sum = 0
6369 12:29:48.301632 9, 0xFFFF, sum = 0
6370 12:29:48.304811 10, 0xFFFF, sum = 0
6371 12:29:48.305460 11, 0xFFFF, sum = 0
6372 12:29:48.307929 12, 0xFFFF, sum = 0
6373 12:29:48.308392 13, 0x0, sum = 1
6374 12:29:48.310981 14, 0x0, sum = 2
6375 12:29:48.311520 15, 0x0, sum = 3
6376 12:29:48.312160 16, 0x0, sum = 4
6377 12:29:48.314598 best_step = 14
6378 12:29:48.315067
6379 12:29:48.315796 ==
6380 12:29:48.317943 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:29:48.321355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:29:48.321902 ==
6383 12:29:48.324639 RX Vref Scan: 1
6384 12:29:48.325077
6385 12:29:48.327996 RX Vref 0 -> 0, step: 1
6386 12:29:48.328440
6387 12:29:48.328891 RX Delay -311 -> 252, step: 8
6388 12:29:48.329325
6389 12:29:48.331124 Set Vref, RX VrefLevel [Byte0]: 54
6390 12:29:48.334371 [Byte1]: 48
6391 12:29:48.339859
6392 12:29:48.340344 Final RX Vref Byte 0 = 54 to rank0
6393 12:29:48.342596 Final RX Vref Byte 1 = 48 to rank0
6394 12:29:48.346466 Final RX Vref Byte 0 = 54 to rank1
6395 12:29:48.349870 Final RX Vref Byte 1 = 48 to rank1==
6396 12:29:48.353018 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 12:29:48.359452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 12:29:48.359982 ==
6399 12:29:48.360486 DQS Delay:
6400 12:29:48.363125 DQS0 = 24, DQS1 = 36
6401 12:29:48.363646 DQM Delay:
6402 12:29:48.363991 DQM0 = 7, DQM1 = 13
6403 12:29:48.366412 DQ Delay:
6404 12:29:48.369568 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6405 12:29:48.369994 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6406 12:29:48.372637 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6407 12:29:48.375972 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6408 12:29:48.376445
6409 12:29:48.376788
6410 12:29:48.385947 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6411 12:29:48.389796 CH0 RK0: MR19=C0C, MR18=CBB8
6412 12:29:48.396099 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6413 12:29:48.396575 ==
6414 12:29:48.399419 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 12:29:48.402694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 12:29:48.403076 ==
6417 12:29:48.406336 [Gating] SW mode calibration
6418 12:29:48.412924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 12:29:48.416146 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 12:29:48.422460 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 12:29:48.426354 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 12:29:48.429577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 12:29:48.435984 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 12:29:48.439284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 12:29:48.442736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 12:29:48.449420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 12:29:48.452744 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 12:29:48.456050 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 12:29:48.459472 Total UI for P1: 0, mck2ui 16
6430 12:29:48.462639 best dqsien dly found for B0: ( 0, 14, 24)
6431 12:29:48.465811 Total UI for P1: 0, mck2ui 16
6432 12:29:48.469083 best dqsien dly found for B1: ( 0, 14, 24)
6433 12:29:48.472784 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 12:29:48.475923 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 12:29:48.476355
6436 12:29:48.482386 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 12:29:48.485724 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 12:29:48.489143 [Gating] SW calibration Done
6439 12:29:48.489573 ==
6440 12:29:48.492376 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 12:29:48.495620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 12:29:48.496367 ==
6443 12:29:48.497027 RX Vref Scan: 0
6444 12:29:48.497664
6445 12:29:48.499545 RX Vref 0 -> 0, step: 1
6446 12:29:48.500202
6447 12:29:48.502600 RX Delay -410 -> 252, step: 16
6448 12:29:48.505798 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6449 12:29:48.509126 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6450 12:29:48.515505 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6451 12:29:48.518805 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6452 12:29:48.522131 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6453 12:29:48.525383 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6454 12:29:48.532222 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6455 12:29:48.535518 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6456 12:29:48.538673 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6457 12:29:48.542013 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6458 12:29:48.548787 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6459 12:29:48.552090 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6460 12:29:48.555606 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6461 12:29:48.562185 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6462 12:29:48.565249 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6463 12:29:48.568431 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6464 12:29:48.568532 ==
6465 12:29:48.571654 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 12:29:48.575414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 12:29:48.575498 ==
6468 12:29:48.578582 DQS Delay:
6469 12:29:48.578682 DQS0 = 19, DQS1 = 35
6470 12:29:48.581770 DQM Delay:
6471 12:29:48.581869 DQM0 = 5, DQM1 = 12
6472 12:29:48.581964 DQ Delay:
6473 12:29:48.585011 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6474 12:29:48.588390 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6475 12:29:48.591671 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6476 12:29:48.595094 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6477 12:29:48.595196
6478 12:29:48.595288
6479 12:29:48.595413 ==
6480 12:29:48.598299 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 12:29:48.605284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 12:29:48.605368 ==
6483 12:29:48.605438
6484 12:29:48.605528
6485 12:29:48.605616 TX Vref Scan disable
6486 12:29:48.608608 == TX Byte 0 ==
6487 12:29:48.611635 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 12:29:48.615035 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 12:29:48.618358 == TX Byte 1 ==
6490 12:29:48.621567 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6491 12:29:48.624893 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6492 12:29:48.625002 ==
6493 12:29:48.628295 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 12:29:48.634949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 12:29:48.635057 ==
6496 12:29:48.635152
6497 12:29:48.635243
6498 12:29:48.635357 TX Vref Scan disable
6499 12:29:48.638613 == TX Byte 0 ==
6500 12:29:48.641749 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6501 12:29:48.645055 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6502 12:29:48.648436 == TX Byte 1 ==
6503 12:29:48.651706 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6504 12:29:48.655123 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6505 12:29:48.655230
6506 12:29:48.658516 [DATLAT]
6507 12:29:48.658598 Freq=400, CH0 RK1
6508 12:29:48.658698
6509 12:29:48.661705 DATLAT Default: 0xe
6510 12:29:48.661805 0, 0xFFFF, sum = 0
6511 12:29:48.665151 1, 0xFFFF, sum = 0
6512 12:29:48.665253 2, 0xFFFF, sum = 0
6513 12:29:48.668494 3, 0xFFFF, sum = 0
6514 12:29:48.668599 4, 0xFFFF, sum = 0
6515 12:29:48.671695 5, 0xFFFF, sum = 0
6516 12:29:48.671799 6, 0xFFFF, sum = 0
6517 12:29:48.674748 7, 0xFFFF, sum = 0
6518 12:29:48.674855 8, 0xFFFF, sum = 0
6519 12:29:48.678488 9, 0xFFFF, sum = 0
6520 12:29:48.678597 10, 0xFFFF, sum = 0
6521 12:29:48.681647 11, 0xFFFF, sum = 0
6522 12:29:48.684799 12, 0xFFFF, sum = 0
6523 12:29:48.684912 13, 0x0, sum = 1
6524 12:29:48.685011 14, 0x0, sum = 2
6525 12:29:48.687982 15, 0x0, sum = 3
6526 12:29:48.688090 16, 0x0, sum = 4
6527 12:29:48.691603 best_step = 14
6528 12:29:48.691715
6529 12:29:48.691814 ==
6530 12:29:48.695089 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:29:48.698455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:29:48.698561 ==
6533 12:29:48.701726 RX Vref Scan: 0
6534 12:29:48.701832
6535 12:29:48.701930 RX Vref 0 -> 0, step: 1
6536 12:29:48.702026
6537 12:29:48.704417 RX Delay -311 -> 252, step: 8
6538 12:29:48.712787 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6539 12:29:48.716066 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6540 12:29:48.719472 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6541 12:29:48.723224 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6542 12:29:48.729848 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6543 12:29:48.733149 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6544 12:29:48.736557 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6545 12:29:48.739732 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6546 12:29:48.746168 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6547 12:29:48.749972 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6548 12:29:48.752921 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6549 12:29:48.756102 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6550 12:29:48.762840 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6551 12:29:48.766271 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6552 12:29:48.769573 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6553 12:29:48.776435 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6554 12:29:48.776552 ==
6555 12:29:48.779729 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 12:29:48.782796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 12:29:48.782905 ==
6558 12:29:48.783000 DQS Delay:
6559 12:29:48.785932 DQS0 = 24, DQS1 = 32
6560 12:29:48.786039 DQM Delay:
6561 12:29:48.789015 DQM0 = 9, DQM1 = 9
6562 12:29:48.789114 DQ Delay:
6563 12:29:48.792968 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6564 12:29:48.795914 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6565 12:29:48.799004 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6566 12:29:48.802353 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6567 12:29:48.802461
6568 12:29:48.802556
6569 12:29:48.809103 [DQSOSCAuto] RK1, (LSB)MR18= 0xb958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6570 12:29:48.812247 CH0 RK1: MR19=C0C, MR18=B958
6571 12:29:48.819225 CH0_RK1: MR19=0xC0C, MR18=0xB958, DQSOSC=386, MR23=63, INC=396, DEC=264
6572 12:29:48.822277 [RxdqsGatingPostProcess] freq 400
6573 12:29:48.825650 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 12:29:48.828942 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 12:29:48.832134 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 12:29:48.835540 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 12:29:48.838989 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 12:29:48.842283 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 12:29:48.845546 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 12:29:48.848736 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 12:29:48.852044 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 12:29:48.855886 Pre-setting of DQS Precalculation
6583 12:29:48.859024 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 12:29:48.862523 ==
6585 12:29:48.862601 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 12:29:48.869181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 12:29:48.869285 ==
6588 12:29:48.872617 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 12:29:48.879270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6590 12:29:48.882658 [CA 0] Center 36 (8~64) winsize 57
6591 12:29:48.885451 [CA 1] Center 36 (8~64) winsize 57
6592 12:29:48.888658 [CA 2] Center 36 (8~64) winsize 57
6593 12:29:48.892488 [CA 3] Center 36 (8~64) winsize 57
6594 12:29:48.895708 [CA 4] Center 36 (8~64) winsize 57
6595 12:29:48.898885 [CA 5] Center 36 (8~64) winsize 57
6596 12:29:48.898963
6597 12:29:48.902671 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6598 12:29:48.902746
6599 12:29:48.905663 [CATrainingPosCal] consider 1 rank data
6600 12:29:48.909312 u2DelayCellTimex100 = 270/100 ps
6601 12:29:48.912658 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 12:29:48.915614 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 12:29:48.918868 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:29:48.922133 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 12:29:48.925732 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:29:48.928861 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 12:29:48.932048
6608 12:29:48.935365 CA PerBit enable=1, Macro0, CA PI delay=36
6609 12:29:48.935443
6610 12:29:48.938632 [CBTSetCACLKResult] CA Dly = 36
6611 12:29:48.938735 CS Dly: 1 (0~32)
6612 12:29:48.938832 ==
6613 12:29:48.942066 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 12:29:48.945320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 12:29:48.945435 ==
6616 12:29:48.952298 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 12:29:48.959121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 12:29:48.962227 [CA 0] Center 36 (8~64) winsize 57
6619 12:29:48.965521 [CA 1] Center 36 (8~64) winsize 57
6620 12:29:48.968686 [CA 2] Center 36 (8~64) winsize 57
6621 12:29:48.972005 [CA 3] Center 36 (8~64) winsize 57
6622 12:29:48.975307 [CA 4] Center 36 (8~64) winsize 57
6623 12:29:48.975426 [CA 5] Center 36 (8~64) winsize 57
6624 12:29:48.978607
6625 12:29:48.982030 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 12:29:48.982131
6627 12:29:48.985381 [CATrainingPosCal] consider 2 rank data
6628 12:29:48.988691 u2DelayCellTimex100 = 270/100 ps
6629 12:29:48.992060 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:29:48.995406 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:29:48.998633 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:29:49.001914 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:29:49.005617 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:29:49.008822 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:29:49.008926
6636 12:29:49.011983 CA PerBit enable=1, Macro0, CA PI delay=36
6637 12:29:49.012059
6638 12:29:49.015148 [CBTSetCACLKResult] CA Dly = 36
6639 12:29:49.018442 CS Dly: 1 (0~32)
6640 12:29:49.018516
6641 12:29:49.021702 ----->DramcWriteLeveling(PI) begin...
6642 12:29:49.021803 ==
6643 12:29:49.025567 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 12:29:49.028783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 12:29:49.028894 ==
6646 12:29:49.031919 Write leveling (Byte 0): 40 => 8
6647 12:29:49.034946 Write leveling (Byte 1): 40 => 8
6648 12:29:49.038263 DramcWriteLeveling(PI) end<-----
6649 12:29:49.038367
6650 12:29:49.038460 ==
6651 12:29:49.042050 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 12:29:49.045386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 12:29:49.045494 ==
6654 12:29:49.048741 [Gating] SW mode calibration
6655 12:29:49.055166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 12:29:49.061703 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 12:29:49.064964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 12:29:49.068781 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 12:29:49.075174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 12:29:49.078406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 12:29:49.081887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 12:29:49.088684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 12:29:49.092056 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 12:29:49.095253 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 12:29:49.101864 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 12:29:49.105268 Total UI for P1: 0, mck2ui 16
6667 12:29:49.108318 best dqsien dly found for B0: ( 0, 14, 24)
6668 12:29:49.108407 Total UI for P1: 0, mck2ui 16
6669 12:29:49.114895 best dqsien dly found for B1: ( 0, 14, 24)
6670 12:29:49.118667 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 12:29:49.121845 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 12:29:49.121989
6673 12:29:49.125180 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 12:29:49.128478 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 12:29:49.131684 [Gating] SW calibration Done
6676 12:29:49.131793 ==
6677 12:29:49.135486 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 12:29:49.138530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 12:29:49.138666 ==
6680 12:29:49.141711 RX Vref Scan: 0
6681 12:29:49.141814
6682 12:29:49.141912 RX Vref 0 -> 0, step: 1
6683 12:29:49.142019
6684 12:29:49.145013 RX Delay -410 -> 252, step: 16
6685 12:29:49.151566 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6686 12:29:49.154722 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6687 12:29:49.158010 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6688 12:29:49.161366 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6689 12:29:49.167911 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6690 12:29:49.171129 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6691 12:29:49.175033 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6692 12:29:49.178355 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6693 12:29:49.184909 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6694 12:29:49.188255 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6695 12:29:49.191565 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6696 12:29:49.194942 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6697 12:29:49.201629 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6698 12:29:49.204909 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6699 12:29:49.208280 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6700 12:29:49.211637 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6701 12:29:49.214723 ==
6702 12:29:49.217861 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 12:29:49.221315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 12:29:49.221417 ==
6705 12:29:49.221513 DQS Delay:
6706 12:29:49.224411 DQS0 = 35, DQS1 = 35
6707 12:29:49.224511 DQM Delay:
6708 12:29:49.228094 DQM0 = 18, DQM1 = 13
6709 12:29:49.228193 DQ Delay:
6710 12:29:49.231312 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6711 12:29:49.234674 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6712 12:29:49.237881 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6713 12:29:49.241797 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6714 12:29:49.241899
6715 12:29:49.241990
6716 12:29:49.242082 ==
6717 12:29:49.244936 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 12:29:49.248040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 12:29:49.248137 ==
6720 12:29:49.248202
6721 12:29:49.248262
6722 12:29:49.251371 TX Vref Scan disable
6723 12:29:49.251444 == TX Byte 0 ==
6724 12:29:49.257784 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 12:29:49.261039 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 12:29:49.261146 == TX Byte 1 ==
6727 12:29:49.268223 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 12:29:49.271516 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 12:29:49.271629 ==
6730 12:29:49.274919 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 12:29:49.278200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 12:29:49.278322 ==
6733 12:29:49.278419
6734 12:29:49.278490
6735 12:29:49.281533 TX Vref Scan disable
6736 12:29:49.281654 == TX Byte 0 ==
6737 12:29:49.288049 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 12:29:49.291322 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 12:29:49.291451 == TX Byte 1 ==
6740 12:29:49.297999 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 12:29:49.301169 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 12:29:49.301281
6743 12:29:49.301376 [DATLAT]
6744 12:29:49.304560 Freq=400, CH1 RK0
6745 12:29:49.304673
6746 12:29:49.304770 DATLAT Default: 0xf
6747 12:29:49.307933 0, 0xFFFF, sum = 0
6748 12:29:49.308050 1, 0xFFFF, sum = 0
6749 12:29:49.311215 2, 0xFFFF, sum = 0
6750 12:29:49.311317 3, 0xFFFF, sum = 0
6751 12:29:49.314623 4, 0xFFFF, sum = 0
6752 12:29:49.314721 5, 0xFFFF, sum = 0
6753 12:29:49.318118 6, 0xFFFF, sum = 0
6754 12:29:49.318218 7, 0xFFFF, sum = 0
6755 12:29:49.321270 8, 0xFFFF, sum = 0
6756 12:29:49.321370 9, 0xFFFF, sum = 0
6757 12:29:49.324305 10, 0xFFFF, sum = 0
6758 12:29:49.327598 11, 0xFFFF, sum = 0
6759 12:29:49.327689 12, 0xFFFF, sum = 0
6760 12:29:49.331178 13, 0x0, sum = 1
6761 12:29:49.331291 14, 0x0, sum = 2
6762 12:29:49.331398 15, 0x0, sum = 3
6763 12:29:49.334291 16, 0x0, sum = 4
6764 12:29:49.334391 best_step = 14
6765 12:29:49.334480
6766 12:29:49.338106 ==
6767 12:29:49.338204 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:29:49.344714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:29:49.344817 ==
6770 12:29:49.344909 RX Vref Scan: 1
6771 12:29:49.345000
6772 12:29:49.347973 RX Vref 0 -> 0, step: 1
6773 12:29:49.348069
6774 12:29:49.351025 RX Delay -311 -> 252, step: 8
6775 12:29:49.351121
6776 12:29:49.354084 Set Vref, RX VrefLevel [Byte0]: 53
6777 12:29:49.357372 [Byte1]: 52
6778 12:29:49.361094
6779 12:29:49.361177 Final RX Vref Byte 0 = 53 to rank0
6780 12:29:49.364403 Final RX Vref Byte 1 = 52 to rank0
6781 12:29:49.367618 Final RX Vref Byte 0 = 53 to rank1
6782 12:29:49.370965 Final RX Vref Byte 1 = 52 to rank1==
6783 12:29:49.374239 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 12:29:49.380621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 12:29:49.380704 ==
6786 12:29:49.380769 DQS Delay:
6787 12:29:49.384058 DQS0 = 32, DQS1 = 32
6788 12:29:49.384140 DQM Delay:
6789 12:29:49.384206 DQM0 = 13, DQM1 = 10
6790 12:29:49.387377 DQ Delay:
6791 12:29:49.390775 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6792 12:29:49.394423 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6793 12:29:49.394506 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6794 12:29:49.397609 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6795 12:29:49.401071
6796 12:29:49.401152
6797 12:29:49.407777 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6798 12:29:49.411095 CH1 RK0: MR19=C0C, MR18=8EC6
6799 12:29:49.417166 CH1_RK0: MR19=0xC0C, MR18=0x8EC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6800 12:29:49.417250 ==
6801 12:29:49.420556 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 12:29:49.423846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 12:29:49.423929 ==
6804 12:29:49.427192 [Gating] SW mode calibration
6805 12:29:49.434230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 12:29:49.440563 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 12:29:49.444357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 12:29:49.447593 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 12:29:49.454145 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 12:29:49.457367 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 12:29:49.460492 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 12:29:49.463739 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 12:29:49.470938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 12:29:49.474036 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 12:29:49.477361 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 12:29:49.480798 Total UI for P1: 0, mck2ui 16
6817 12:29:49.483951 best dqsien dly found for B0: ( 0, 14, 24)
6818 12:29:49.487199 Total UI for P1: 0, mck2ui 16
6819 12:29:49.490665 best dqsien dly found for B1: ( 0, 14, 24)
6820 12:29:49.494091 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 12:29:49.497442 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 12:29:49.500680
6823 12:29:49.504059 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 12:29:49.507507 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 12:29:49.510829 [Gating] SW calibration Done
6826 12:29:49.510912 ==
6827 12:29:49.514248 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 12:29:49.517422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 12:29:49.517507 ==
6830 12:29:49.517572 RX Vref Scan: 0
6831 12:29:49.520742
6832 12:29:49.520824 RX Vref 0 -> 0, step: 1
6833 12:29:49.520890
6834 12:29:49.523464 RX Delay -410 -> 252, step: 16
6835 12:29:49.526787 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6836 12:29:49.533403 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6837 12:29:49.537304 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6838 12:29:49.540633 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6839 12:29:49.543662 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6840 12:29:49.550415 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6841 12:29:49.553615 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6842 12:29:49.556888 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6843 12:29:49.560160 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6844 12:29:49.566487 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6845 12:29:49.570301 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6846 12:29:49.572976 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6847 12:29:49.579951 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6848 12:29:49.583131 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6849 12:29:49.586427 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6850 12:29:49.589549 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6851 12:29:49.589655 ==
6852 12:29:49.592846 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 12:29:49.599601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 12:29:49.599685 ==
6855 12:29:49.599751 DQS Delay:
6856 12:29:49.602751 DQS0 = 35, DQS1 = 35
6857 12:29:49.602834 DQM Delay:
6858 12:29:49.605983 DQM0 = 17, DQM1 = 13
6859 12:29:49.606084 DQ Delay:
6860 12:29:49.609260 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6861 12:29:49.612638 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6862 12:29:49.615934 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6863 12:29:49.619214 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6864 12:29:49.619296
6865 12:29:49.619403
6866 12:29:49.619466 ==
6867 12:29:49.622454 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 12:29:49.625762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 12:29:49.625846 ==
6870 12:29:49.625912
6871 12:29:49.625973
6872 12:29:49.629192 TX Vref Scan disable
6873 12:29:49.629275 == TX Byte 0 ==
6874 12:29:49.635859 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 12:29:49.639069 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 12:29:49.639152 == TX Byte 1 ==
6877 12:29:49.646337 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6878 12:29:49.649634 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6879 12:29:49.649718 ==
6880 12:29:49.652763 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 12:29:49.655792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 12:29:49.655877 ==
6883 12:29:49.655944
6884 12:29:49.656007
6885 12:29:49.658958 TX Vref Scan disable
6886 12:29:49.659042 == TX Byte 0 ==
6887 12:29:49.666037 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 12:29:49.669360 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 12:29:49.669444 == TX Byte 1 ==
6890 12:29:49.676158 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6891 12:29:49.679198 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6892 12:29:49.679282
6893 12:29:49.679387 [DATLAT]
6894 12:29:49.682366 Freq=400, CH1 RK1
6895 12:29:49.682450
6896 12:29:49.682515 DATLAT Default: 0xe
6897 12:29:49.685595 0, 0xFFFF, sum = 0
6898 12:29:49.685680 1, 0xFFFF, sum = 0
6899 12:29:49.688704 2, 0xFFFF, sum = 0
6900 12:29:49.688789 3, 0xFFFF, sum = 0
6901 12:29:49.692503 4, 0xFFFF, sum = 0
6902 12:29:49.692620 5, 0xFFFF, sum = 0
6903 12:29:49.695714 6, 0xFFFF, sum = 0
6904 12:29:49.695798 7, 0xFFFF, sum = 0
6905 12:29:49.699029 8, 0xFFFF, sum = 0
6906 12:29:49.699116 9, 0xFFFF, sum = 0
6907 12:29:49.702391 10, 0xFFFF, sum = 0
6908 12:29:49.705645 11, 0xFFFF, sum = 0
6909 12:29:49.705758 12, 0xFFFF, sum = 0
6910 12:29:49.708911 13, 0x0, sum = 1
6911 12:29:49.708995 14, 0x0, sum = 2
6912 12:29:49.712183 15, 0x0, sum = 3
6913 12:29:49.712269 16, 0x0, sum = 4
6914 12:29:49.712338 best_step = 14
6915 12:29:49.712401
6916 12:29:49.715310 ==
6917 12:29:49.718670 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:29:49.721960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:29:49.722062 ==
6920 12:29:49.722160 RX Vref Scan: 0
6921 12:29:49.722252
6922 12:29:49.725303 RX Vref 0 -> 0, step: 1
6923 12:29:49.725403
6924 12:29:49.728663 RX Delay -311 -> 252, step: 8
6925 12:29:49.735530 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6926 12:29:49.738744 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6927 12:29:49.741996 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6928 12:29:49.745357 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6929 12:29:49.752098 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6930 12:29:49.755319 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6931 12:29:49.759238 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6932 12:29:49.762477 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6933 12:29:49.768723 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6934 12:29:49.772115 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6935 12:29:49.775242 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6936 12:29:49.778894 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6937 12:29:49.785645 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6938 12:29:49.788915 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6939 12:29:49.792329 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6940 12:29:49.795470 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6941 12:29:49.798537 ==
6942 12:29:49.802444 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 12:29:49.805675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 12:29:49.805776 ==
6945 12:29:49.805858 DQS Delay:
6946 12:29:49.809076 DQS0 = 28, DQS1 = 36
6947 12:29:49.809161 DQM Delay:
6948 12:29:49.812465 DQM0 = 10, DQM1 = 14
6949 12:29:49.812548 DQ Delay:
6950 12:29:49.815156 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6951 12:29:49.819008 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6952 12:29:49.822172 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6953 12:29:49.825656 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6954 12:29:49.825755
6955 12:29:49.825845
6956 12:29:49.832373 [DQSOSCAuto] RK1, (LSB)MR18= 0xc454, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6957 12:29:49.835627 CH1 RK1: MR19=C0C, MR18=C454
6958 12:29:49.842285 CH1_RK1: MR19=0xC0C, MR18=0xC454, DQSOSC=385, MR23=63, INC=398, DEC=265
6959 12:29:49.845563 [RxdqsGatingPostProcess] freq 400
6960 12:29:49.848811 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 12:29:49.852234 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 12:29:49.855425 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 12:29:49.858974 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 12:29:49.861653 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 12:29:49.864914 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 12:29:49.868588 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 12:29:49.871708 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 12:29:49.875334 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 12:29:49.878649 Pre-setting of DQS Precalculation
6970 12:29:49.881888 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 12:29:49.891936 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 12:29:49.898641 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 12:29:49.898723
6974 12:29:49.898789
6975 12:29:49.902046 [Calibration Summary] 800 Mbps
6976 12:29:49.902148 CH 0, Rank 0
6977 12:29:49.905028 SW Impedance : PASS
6978 12:29:49.905114 DUTY Scan : NO K
6979 12:29:49.908128 ZQ Calibration : PASS
6980 12:29:49.911922 Jitter Meter : NO K
6981 12:29:49.912015 CBT Training : PASS
6982 12:29:49.915288 Write leveling : PASS
6983 12:29:49.918694 RX DQS gating : PASS
6984 12:29:49.918771 RX DQ/DQS(RDDQC) : PASS
6985 12:29:49.921970 TX DQ/DQS : PASS
6986 12:29:49.925206 RX DATLAT : PASS
6987 12:29:49.925316 RX DQ/DQS(Engine): PASS
6988 12:29:49.928449 TX OE : NO K
6989 12:29:49.928525 All Pass.
6990 12:29:49.928590
6991 12:29:49.931782 CH 0, Rank 1
6992 12:29:49.931871 SW Impedance : PASS
6993 12:29:49.935034 DUTY Scan : NO K
6994 12:29:49.935130 ZQ Calibration : PASS
6995 12:29:49.938341 Jitter Meter : NO K
6996 12:29:49.941658 CBT Training : PASS
6997 12:29:49.941741 Write leveling : NO K
6998 12:29:49.945091 RX DQS gating : PASS
6999 12:29:49.948346 RX DQ/DQS(RDDQC) : PASS
7000 12:29:49.948434 TX DQ/DQS : PASS
7001 12:29:49.951590 RX DATLAT : PASS
7002 12:29:49.954992 RX DQ/DQS(Engine): PASS
7003 12:29:49.955075 TX OE : NO K
7004 12:29:49.958357 All Pass.
7005 12:29:49.958470
7006 12:29:49.958535 CH 1, Rank 0
7007 12:29:49.961649 SW Impedance : PASS
7008 12:29:49.961731 DUTY Scan : NO K
7009 12:29:49.964990 ZQ Calibration : PASS
7010 12:29:49.968150 Jitter Meter : NO K
7011 12:29:49.968232 CBT Training : PASS
7012 12:29:49.971479 Write leveling : PASS
7013 12:29:49.974715 RX DQS gating : PASS
7014 12:29:49.974797 RX DQ/DQS(RDDQC) : PASS
7015 12:29:49.978536 TX DQ/DQS : PASS
7016 12:29:49.978619 RX DATLAT : PASS
7017 12:29:49.981552 RX DQ/DQS(Engine): PASS
7018 12:29:49.985280 TX OE : NO K
7019 12:29:49.985363 All Pass.
7020 12:29:49.985462
7021 12:29:49.985522 CH 1, Rank 1
7022 12:29:49.988232 SW Impedance : PASS
7023 12:29:49.991682 DUTY Scan : NO K
7024 12:29:49.991765 ZQ Calibration : PASS
7025 12:29:49.995286 Jitter Meter : NO K
7026 12:29:49.998339 CBT Training : PASS
7027 12:29:49.998421 Write leveling : NO K
7028 12:29:50.001573 RX DQS gating : PASS
7029 12:29:50.004785 RX DQ/DQS(RDDQC) : PASS
7030 12:29:50.004884 TX DQ/DQS : PASS
7031 12:29:50.008507 RX DATLAT : PASS
7032 12:29:50.011693 RX DQ/DQS(Engine): PASS
7033 12:29:50.011775 TX OE : NO K
7034 12:29:50.011841 All Pass.
7035 12:29:50.014939
7036 12:29:50.015021 DramC Write-DBI off
7037 12:29:50.018711 PER_BANK_REFRESH: Hybrid Mode
7038 12:29:50.018795 TX_TRACKING: ON
7039 12:29:50.028391 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 12:29:50.031616 [FAST_K] Save calibration result to emmc
7041 12:29:50.034829 dramc_set_vcore_voltage set vcore to 725000
7042 12:29:50.038708 Read voltage for 1600, 0
7043 12:29:50.038786 Vio18 = 0
7044 12:29:50.042107 Vcore = 725000
7045 12:29:50.042236 Vdram = 0
7046 12:29:50.042327 Vddq = 0
7047 12:29:50.042414 Vmddr = 0
7048 12:29:50.048127 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 12:29:50.054725 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 12:29:50.054810 MEM_TYPE=3, freq_sel=13
7051 12:29:50.057927 sv_algorithm_assistance_LP4_3733
7052 12:29:50.061383 ============ PULL DRAM RESETB DOWN ============
7053 12:29:50.068123 ========== PULL DRAM RESETB DOWN end =========
7054 12:29:50.071429 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 12:29:50.074686 ===================================
7056 12:29:50.078022 LPDDR4 DRAM CONFIGURATION
7057 12:29:50.081342 ===================================
7058 12:29:50.081428 EX_ROW_EN[0] = 0x0
7059 12:29:50.084671 EX_ROW_EN[1] = 0x0
7060 12:29:50.084755 LP4Y_EN = 0x0
7061 12:29:50.087705 WORK_FSP = 0x1
7062 12:29:50.087790 WL = 0x5
7063 12:29:50.091251 RL = 0x5
7064 12:29:50.094241 BL = 0x2
7065 12:29:50.094326 RPST = 0x0
7066 12:29:50.098230 RD_PRE = 0x0
7067 12:29:50.098348 WR_PRE = 0x1
7068 12:29:50.101547 WR_PST = 0x1
7069 12:29:50.101660 DBI_WR = 0x0
7070 12:29:50.104538 DBI_RD = 0x0
7071 12:29:50.104657 OTF = 0x1
7072 12:29:50.107621 ===================================
7073 12:29:50.111506 ===================================
7074 12:29:50.114508 ANA top config
7075 12:29:50.117688 ===================================
7076 12:29:50.117804 DLL_ASYNC_EN = 0
7077 12:29:50.120995 ALL_SLAVE_EN = 0
7078 12:29:50.124916 NEW_RANK_MODE = 1
7079 12:29:50.128214 DLL_IDLE_MODE = 1
7080 12:29:50.128340 LP45_APHY_COMB_EN = 1
7081 12:29:50.131573 TX_ODT_DIS = 0
7082 12:29:50.134830 NEW_8X_MODE = 1
7083 12:29:50.138019 ===================================
7084 12:29:50.141164 ===================================
7085 12:29:50.144272 data_rate = 3200
7086 12:29:50.147680 CKR = 1
7087 12:29:50.151071 DQ_P2S_RATIO = 8
7088 12:29:50.154501 ===================================
7089 12:29:50.154618 CA_P2S_RATIO = 8
7090 12:29:50.157867 DQ_CA_OPEN = 0
7091 12:29:50.161120 DQ_SEMI_OPEN = 0
7092 12:29:50.164464 CA_SEMI_OPEN = 0
7093 12:29:50.167713 CA_FULL_RATE = 0
7094 12:29:50.167828 DQ_CKDIV4_EN = 0
7095 12:29:50.171096 CA_CKDIV4_EN = 0
7096 12:29:50.174449 CA_PREDIV_EN = 0
7097 12:29:50.177675 PH8_DLY = 12
7098 12:29:50.181166 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 12:29:50.184483 DQ_AAMCK_DIV = 4
7100 12:29:50.187155 CA_AAMCK_DIV = 4
7101 12:29:50.187277 CA_ADMCK_DIV = 4
7102 12:29:50.190515 DQ_TRACK_CA_EN = 0
7103 12:29:50.194215 CA_PICK = 1600
7104 12:29:50.197383 CA_MCKIO = 1600
7105 12:29:50.200574 MCKIO_SEMI = 0
7106 12:29:50.204416 PLL_FREQ = 3068
7107 12:29:50.207814 DQ_UI_PI_RATIO = 32
7108 12:29:50.207933 CA_UI_PI_RATIO = 0
7109 12:29:50.210979 ===================================
7110 12:29:50.214161 ===================================
7111 12:29:50.217226 memory_type:LPDDR4
7112 12:29:50.221133 GP_NUM : 10
7113 12:29:50.221245 SRAM_EN : 1
7114 12:29:50.224315 MD32_EN : 0
7115 12:29:50.227553 ===================================
7116 12:29:50.230657 [ANA_INIT] >>>>>>>>>>>>>>
7117 12:29:50.234343 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 12:29:50.237444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 12:29:50.240817 ===================================
7120 12:29:50.240933 data_rate = 3200,PCW = 0X7600
7121 12:29:50.244085 ===================================
7122 12:29:50.247139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 12:29:50.254142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 12:29:50.260818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 12:29:50.264008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 12:29:50.267289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 12:29:50.270745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 12:29:50.274154 [ANA_INIT] flow start
7129 12:29:50.274262 [ANA_INIT] PLL >>>>>>>>
7130 12:29:50.277341 [ANA_INIT] PLL <<<<<<<<
7131 12:29:50.280598 [ANA_INIT] MIDPI >>>>>>>>
7132 12:29:50.283998 [ANA_INIT] MIDPI <<<<<<<<
7133 12:29:50.284077 [ANA_INIT] DLL >>>>>>>>
7134 12:29:50.287360 [ANA_INIT] DLL <<<<<<<<
7135 12:29:50.290670 [ANA_INIT] flow end
7136 12:29:50.294068 ============ LP4 DIFF to SE enter ============
7137 12:29:50.297085 ============ LP4 DIFF to SE exit ============
7138 12:29:50.300549 [ANA_INIT] <<<<<<<<<<<<<
7139 12:29:50.303950 [Flow] Enable top DCM control >>>>>
7140 12:29:50.307014 [Flow] Enable top DCM control <<<<<
7141 12:29:50.310151 Enable DLL master slave shuffle
7142 12:29:50.313966 ==============================================================
7143 12:29:50.317290 Gating Mode config
7144 12:29:50.320433 ==============================================================
7145 12:29:50.323627 Config description:
7146 12:29:50.333745 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 12:29:50.340179 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 12:29:50.343821 SELPH_MODE 0: By rank 1: By Phase
7149 12:29:50.350407 ==============================================================
7150 12:29:50.353712 GAT_TRACK_EN = 1
7151 12:29:50.357007 RX_GATING_MODE = 2
7152 12:29:50.360139 RX_GATING_TRACK_MODE = 2
7153 12:29:50.363578 SELPH_MODE = 1
7154 12:29:50.366908 PICG_EARLY_EN = 1
7155 12:29:50.366986 VALID_LAT_VALUE = 1
7156 12:29:50.373377 ==============================================================
7157 12:29:50.376740 Enter into Gating configuration >>>>
7158 12:29:50.380023 Exit from Gating configuration <<<<
7159 12:29:50.383260 Enter into DVFS_PRE_config >>>>>
7160 12:29:50.393331 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 12:29:50.396759 Exit from DVFS_PRE_config <<<<<
7162 12:29:50.400004 Enter into PICG configuration >>>>
7163 12:29:50.403164 Exit from PICG configuration <<<<
7164 12:29:50.407092 [RX_INPUT] configuration >>>>>
7165 12:29:50.410454 [RX_INPUT] configuration <<<<<
7166 12:29:50.413682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 12:29:50.420159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 12:29:50.426659 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 12:29:50.433646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 12:29:50.439903 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 12:29:50.446913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 12:29:50.450061 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 12:29:50.453244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 12:29:50.456326 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 12:29:50.459648 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 12:29:50.466759 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 12:29:50.469951 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 12:29:50.473288 ===================================
7179 12:29:50.476499 LPDDR4 DRAM CONFIGURATION
7180 12:29:50.479915 ===================================
7181 12:29:50.479993 EX_ROW_EN[0] = 0x0
7182 12:29:50.483250 EX_ROW_EN[1] = 0x0
7183 12:29:50.483382 LP4Y_EN = 0x0
7184 12:29:50.486566 WORK_FSP = 0x1
7185 12:29:50.486648 WL = 0x5
7186 12:29:50.489818 RL = 0x5
7187 12:29:50.493174 BL = 0x2
7188 12:29:50.493277 RPST = 0x0
7189 12:29:50.496629 RD_PRE = 0x0
7190 12:29:50.496703 WR_PRE = 0x1
7191 12:29:50.499897 WR_PST = 0x1
7192 12:29:50.499970 DBI_WR = 0x0
7193 12:29:50.503181 DBI_RD = 0x0
7194 12:29:50.503278 OTF = 0x1
7195 12:29:50.506356 ===================================
7196 12:29:50.509695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 12:29:50.516373 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 12:29:50.519600 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 12:29:50.523017 ===================================
7200 12:29:50.526127 LPDDR4 DRAM CONFIGURATION
7201 12:29:50.529293 ===================================
7202 12:29:50.529367 EX_ROW_EN[0] = 0x10
7203 12:29:50.532672 EX_ROW_EN[1] = 0x0
7204 12:29:50.532743 LP4Y_EN = 0x0
7205 12:29:50.536142 WORK_FSP = 0x1
7206 12:29:50.536215 WL = 0x5
7207 12:29:50.539288 RL = 0x5
7208 12:29:50.539423 BL = 0x2
7209 12:29:50.542996 RPST = 0x0
7210 12:29:50.543096 RD_PRE = 0x0
7211 12:29:50.546240 WR_PRE = 0x1
7212 12:29:50.549430 WR_PST = 0x1
7213 12:29:50.549515 DBI_WR = 0x0
7214 12:29:50.552698 DBI_RD = 0x0
7215 12:29:50.552798 OTF = 0x1
7216 12:29:50.555910 ===================================
7217 12:29:50.562679 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 12:29:50.562766 ==
7219 12:29:50.565985 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 12:29:50.569305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 12:29:50.569390 ==
7222 12:29:50.572658 [Duty_Offset_Calibration]
7223 12:29:50.572770 B0:2 B1:1 CA:1
7224 12:29:50.576276
7225 12:29:50.578931 [DutyScan_Calibration_Flow] k_type=0
7226 12:29:50.587690
7227 12:29:50.587796 ==CLK 0==
7228 12:29:50.590415 Final CLK duty delay cell = 0
7229 12:29:50.594287 [0] MAX Duty = 5156%(X100), DQS PI = 22
7230 12:29:50.597627 [0] MIN Duty = 4876%(X100), DQS PI = 48
7231 12:29:50.597736 [0] AVG Duty = 5016%(X100)
7232 12:29:50.601113
7233 12:29:50.603811 CH0 CLK Duty spec in!! Max-Min= 280%
7234 12:29:50.607051 [DutyScan_Calibration_Flow] ====Done====
7235 12:29:50.607153
7236 12:29:50.610266 [DutyScan_Calibration_Flow] k_type=1
7237 12:29:50.626833
7238 12:29:50.626963 ==DQS 0 ==
7239 12:29:50.629962 Final DQS duty delay cell = -4
7240 12:29:50.633092 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7241 12:29:50.636177 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7242 12:29:50.639505 [-4] AVG Duty = 4906%(X100)
7243 12:29:50.639613
7244 12:29:50.639706 ==DQS 1 ==
7245 12:29:50.642815 Final DQS duty delay cell = 0
7246 12:29:50.646256 [0] MAX Duty = 5187%(X100), DQS PI = 20
7247 12:29:50.650012 [0] MIN Duty = 5062%(X100), DQS PI = 34
7248 12:29:50.653047 [0] AVG Duty = 5124%(X100)
7249 12:29:50.653213
7250 12:29:50.656409 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7251 12:29:50.656519
7252 12:29:50.659694 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7253 12:29:50.662867 [DutyScan_Calibration_Flow] ====Done====
7254 12:29:50.662972
7255 12:29:50.666068 [DutyScan_Calibration_Flow] k_type=3
7256 12:29:50.683116
7257 12:29:50.683225 ==DQM 0 ==
7258 12:29:50.686910 Final DQM duty delay cell = 0
7259 12:29:50.689577 [0] MAX Duty = 5187%(X100), DQS PI = 26
7260 12:29:50.692986 [0] MIN Duty = 4907%(X100), DQS PI = 56
7261 12:29:50.696295 [0] AVG Duty = 5047%(X100)
7262 12:29:50.696404
7263 12:29:50.696498 ==DQM 1 ==
7264 12:29:50.699625 Final DQM duty delay cell = -4
7265 12:29:50.702927 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7266 12:29:50.706935 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7267 12:29:50.709575 [-4] AVG Duty = 4922%(X100)
7268 12:29:50.709695
7269 12:29:50.713415 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7270 12:29:50.713535
7271 12:29:50.716781 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7272 12:29:50.720055 [DutyScan_Calibration_Flow] ====Done====
7273 12:29:50.720171
7274 12:29:50.723460 [DutyScan_Calibration_Flow] k_type=2
7275 12:29:50.741113
7276 12:29:50.741199 ==DQ 0 ==
7277 12:29:50.744295 Final DQ duty delay cell = 0
7278 12:29:50.747669 [0] MAX Duty = 5062%(X100), DQS PI = 26
7279 12:29:50.751025 [0] MIN Duty = 4907%(X100), DQS PI = 0
7280 12:29:50.751127 [0] AVG Duty = 4984%(X100)
7281 12:29:50.754399
7282 12:29:50.754500 ==DQ 1 ==
7283 12:29:50.757535 Final DQ duty delay cell = 0
7284 12:29:50.760747 [0] MAX Duty = 5156%(X100), DQS PI = 22
7285 12:29:50.763704 [0] MIN Duty = 4938%(X100), DQS PI = 34
7286 12:29:50.763833 [0] AVG Duty = 5047%(X100)
7287 12:29:50.763978
7288 12:29:50.767589 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7289 12:29:50.770620
7290 12:29:50.773917 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7291 12:29:50.776979 [DutyScan_Calibration_Flow] ====Done====
7292 12:29:50.777091 ==
7293 12:29:50.780479 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 12:29:50.783631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 12:29:50.783735 ==
7296 12:29:50.786902 [Duty_Offset_Calibration]
7297 12:29:50.787012 B0:1 B1:0 CA:0
7298 12:29:50.787114
7299 12:29:50.790103 [DutyScan_Calibration_Flow] k_type=0
7300 12:29:50.800295
7301 12:29:50.800401 ==CLK 0==
7302 12:29:50.803583 Final CLK duty delay cell = -4
7303 12:29:50.806917 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7304 12:29:50.810167 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7305 12:29:50.813679 [-4] AVG Duty = 4922%(X100)
7306 12:29:50.813774
7307 12:29:50.816957 CH1 CLK Duty spec in!! Max-Min= 156%
7308 12:29:50.820215 [DutyScan_Calibration_Flow] ====Done====
7309 12:29:50.820315
7310 12:29:50.823648 [DutyScan_Calibration_Flow] k_type=1
7311 12:29:50.840398
7312 12:29:50.840501 ==DQS 0 ==
7313 12:29:50.843791 Final DQS duty delay cell = 0
7314 12:29:50.846974 [0] MAX Duty = 5094%(X100), DQS PI = 48
7315 12:29:50.850085 [0] MIN Duty = 4844%(X100), DQS PI = 14
7316 12:29:50.850219 [0] AVG Duty = 4969%(X100)
7317 12:29:50.853251
7318 12:29:50.853348 ==DQS 1 ==
7319 12:29:50.857215 Final DQS duty delay cell = 0
7320 12:29:50.859942 [0] MAX Duty = 5249%(X100), DQS PI = 48
7321 12:29:50.863557 [0] MIN Duty = 4907%(X100), DQS PI = 40
7322 12:29:50.866847 [0] AVG Duty = 5078%(X100)
7323 12:29:50.866950
7324 12:29:50.870155 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7325 12:29:50.870262
7326 12:29:50.873290 CH1 DQS 1 Duty spec in!! Max-Min= 342%
7327 12:29:50.876365 [DutyScan_Calibration_Flow] ====Done====
7328 12:29:50.876470
7329 12:29:50.880056 [DutyScan_Calibration_Flow] k_type=3
7330 12:29:50.896817
7331 12:29:50.896923 ==DQM 0 ==
7332 12:29:50.900626 Final DQM duty delay cell = 0
7333 12:29:50.903759 [0] MAX Duty = 5187%(X100), DQS PI = 40
7334 12:29:50.907067 [0] MIN Duty = 5000%(X100), DQS PI = 16
7335 12:29:50.910444 [0] AVG Duty = 5093%(X100)
7336 12:29:50.910542
7337 12:29:50.910633 ==DQM 1 ==
7338 12:29:50.913861 Final DQM duty delay cell = 0
7339 12:29:50.917172 [0] MAX Duty = 5125%(X100), DQS PI = 10
7340 12:29:50.920385 [0] MIN Duty = 4938%(X100), DQS PI = 0
7341 12:29:50.923594 [0] AVG Duty = 5031%(X100)
7342 12:29:50.923695
7343 12:29:50.926969 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7344 12:29:50.927069
7345 12:29:50.930428 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7346 12:29:50.933557 [DutyScan_Calibration_Flow] ====Done====
7347 12:29:50.933695
7348 12:29:50.936935 [DutyScan_Calibration_Flow] k_type=2
7349 12:29:50.952848
7350 12:29:50.952955 ==DQ 0 ==
7351 12:29:50.956811 Final DQ duty delay cell = -4
7352 12:29:50.959946 [-4] MAX Duty = 5062%(X100), DQS PI = 26
7353 12:29:50.963205 [-4] MIN Duty = 4875%(X100), DQS PI = 14
7354 12:29:50.966449 [-4] AVG Duty = 4968%(X100)
7355 12:29:50.966533
7356 12:29:50.966632 ==DQ 1 ==
7357 12:29:50.969812 Final DQ duty delay cell = 0
7358 12:29:50.973274 [0] MAX Duty = 5125%(X100), DQS PI = 8
7359 12:29:50.976476 [0] MIN Duty = 4938%(X100), DQS PI = 0
7360 12:29:50.976552 [0] AVG Duty = 5031%(X100)
7361 12:29:50.979565
7362 12:29:50.983234 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7363 12:29:50.983344
7364 12:29:50.986436 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7365 12:29:50.989652 [DutyScan_Calibration_Flow] ====Done====
7366 12:29:50.993319 nWR fixed to 30
7367 12:29:50.993438 [ModeRegInit_LP4] CH0 RK0
7368 12:29:50.996434 [ModeRegInit_LP4] CH0 RK1
7369 12:29:50.999433 [ModeRegInit_LP4] CH1 RK0
7370 12:29:51.002698 [ModeRegInit_LP4] CH1 RK1
7371 12:29:51.002806 match AC timing 5
7372 12:29:51.009216 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 12:29:51.012842 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 12:29:51.016057 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 12:29:51.022980 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 12:29:51.026209 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 12:29:51.026329 [MiockJmeterHQA]
7378 12:29:51.026419
7379 12:29:51.029472 [DramcMiockJmeter] u1RxGatingPI = 0
7380 12:29:51.033042 0 : 4366, 4139
7381 12:29:51.033133 4 : 4252, 4026
7382 12:29:51.036441 8 : 4363, 4137
7383 12:29:51.036527 12 : 4255, 4030
7384 12:29:51.036595 16 : 4252, 4027
7385 12:29:51.039692 20 : 4363, 4137
7386 12:29:51.039782 24 : 4252, 4027
7387 12:29:51.043081 28 : 4252, 4027
7388 12:29:51.043201 32 : 4253, 4026
7389 12:29:51.046542 36 : 4255, 4030
7390 12:29:51.046673 40 : 4363, 4137
7391 12:29:51.046754 44 : 4253, 4027
7392 12:29:51.049877 48 : 4363, 4137
7393 12:29:51.050021 52 : 4253, 4026
7394 12:29:51.053093 56 : 4253, 4027
7395 12:29:51.053202 60 : 4250, 4026
7396 12:29:51.056286 64 : 4363, 4137
7397 12:29:51.056400 68 : 4253, 4029
7398 12:29:51.059586 72 : 4360, 4137
7399 12:29:51.059672 76 : 4253, 4029
7400 12:29:51.059740 80 : 4250, 4026
7401 12:29:51.062992 84 : 4250, 4026
7402 12:29:51.063106 88 : 4252, 152
7403 12:29:51.066043 92 : 4250, 0
7404 12:29:51.066150 96 : 4252, 0
7405 12:29:51.066246 100 : 4252, 0
7406 12:29:51.069284 104 : 4252, 0
7407 12:29:51.069369 108 : 4250, 0
7408 12:29:51.072573 112 : 4250, 0
7409 12:29:51.072686 116 : 4252, 0
7410 12:29:51.072784 120 : 4361, 0
7411 12:29:51.075951 124 : 4249, 0
7412 12:29:51.076034 128 : 4250, 0
7413 12:29:51.079282 132 : 4250, 0
7414 12:29:51.079398 136 : 4360, 0
7415 12:29:51.079466 140 : 4250, 0
7416 12:29:51.082667 144 : 4250, 0
7417 12:29:51.082776 148 : 4360, 0
7418 12:29:51.086114 152 : 4360, 0
7419 12:29:51.086190 156 : 4250, 0
7420 12:29:51.086258 160 : 4250, 0
7421 12:29:51.089585 164 : 4250, 0
7422 12:29:51.089685 168 : 4250, 0
7423 12:29:51.089776 172 : 4361, 0
7424 12:29:51.092814 176 : 4249, 0
7425 12:29:51.092898 180 : 4250, 0
7426 12:29:51.095995 184 : 4250, 0
7427 12:29:51.096080 188 : 4360, 0
7428 12:29:51.096144 192 : 4250, 0
7429 12:29:51.099147 196 : 4250, 0
7430 12:29:51.099244 200 : 4360, 0
7431 12:29:51.102218 204 : 4250, 1425
7432 12:29:51.102332 208 : 4360, 4121
7433 12:29:51.105886 212 : 4363, 4140
7434 12:29:51.106004 216 : 4250, 4027
7435 12:29:51.109012 220 : 4361, 4138
7436 12:29:51.109110 224 : 4250, 4027
7437 12:29:51.109241 228 : 4250, 4026
7438 12:29:51.112214 232 : 4250, 4027
7439 12:29:51.112316 236 : 4250, 4027
7440 12:29:51.116095 240 : 4250, 4027
7441 12:29:51.116182 244 : 4250, 4026
7442 12:29:51.119209 248 : 4253, 4029
7443 12:29:51.119312 252 : 4250, 4027
7444 12:29:51.122347 256 : 4250, 4027
7445 12:29:51.122448 260 : 4360, 4137
7446 12:29:51.125693 264 : 4361, 4137
7447 12:29:51.125764 268 : 4250, 4027
7448 12:29:51.128949 272 : 4360, 4138
7449 12:29:51.129048 276 : 4361, 4137
7450 12:29:51.132086 280 : 4250, 4026
7451 12:29:51.132157 284 : 4250, 4027
7452 12:29:51.132221 288 : 4250, 4027
7453 12:29:51.136013 292 : 4250, 4027
7454 12:29:51.136089 296 : 4252, 4029
7455 12:29:51.139263 300 : 4253, 4029
7456 12:29:51.139393 304 : 4250, 4027
7457 12:29:51.142515 308 : 4250, 3980
7458 12:29:51.142586 312 : 4361, 1890
7459 12:29:51.142647
7460 12:29:51.145875 MIOCK jitter meter ch=0
7461 12:29:51.145967
7462 12:29:51.149255 1T = (312-88) = 224 dly cells
7463 12:29:51.155268 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7464 12:29:51.155416 ==
7465 12:29:51.158525 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 12:29:51.162227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7467 12:29:51.162311 ==
7468 12:29:51.168785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7469 12:29:51.172001 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7470 12:29:51.175149 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7471 12:29:51.181807 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7472 12:29:51.190479 [CA 0] Center 42 (12~73) winsize 62
7473 12:29:51.194329 [CA 1] Center 42 (12~73) winsize 62
7474 12:29:51.197490 [CA 2] Center 38 (8~68) winsize 61
7475 12:29:51.200601 [CA 3] Center 37 (7~67) winsize 61
7476 12:29:51.203811 [CA 4] Center 36 (6~66) winsize 61
7477 12:29:51.207073 [CA 5] Center 35 (6~64) winsize 59
7478 12:29:51.207155
7479 12:29:51.210254 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7480 12:29:51.210378
7481 12:29:51.214165 [CATrainingPosCal] consider 1 rank data
7482 12:29:51.217231 u2DelayCellTimex100 = 290/100 ps
7483 12:29:51.220336 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7484 12:29:51.227244 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7485 12:29:51.230378 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7486 12:29:51.234128 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7487 12:29:51.237423 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7488 12:29:51.240825 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7489 12:29:51.240909
7490 12:29:51.244275 CA PerBit enable=1, Macro0, CA PI delay=35
7491 12:29:51.244358
7492 12:29:51.247477 [CBTSetCACLKResult] CA Dly = 35
7493 12:29:51.250904 CS Dly: 9 (0~40)
7494 12:29:51.254144 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7495 12:29:51.257583 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7496 12:29:51.257696 ==
7497 12:29:51.260409 Dram Type= 6, Freq= 0, CH_0, rank 1
7498 12:29:51.264240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 12:29:51.264324 ==
7500 12:29:51.270841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 12:29:51.273653 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 12:29:51.280549 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 12:29:51.283705 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 12:29:51.294214 [CA 0] Center 42 (12~73) winsize 62
7505 12:29:51.297606 [CA 1] Center 42 (12~73) winsize 62
7506 12:29:51.300751 [CA 2] Center 38 (8~68) winsize 61
7507 12:29:51.303885 [CA 3] Center 38 (8~68) winsize 61
7508 12:29:51.307665 [CA 4] Center 35 (6~65) winsize 60
7509 12:29:51.310871 [CA 5] Center 35 (5~65) winsize 61
7510 12:29:51.310956
7511 12:29:51.313959 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7512 12:29:51.314049
7513 12:29:51.317200 [CATrainingPosCal] consider 2 rank data
7514 12:29:51.320774 u2DelayCellTimex100 = 290/100 ps
7515 12:29:51.323967 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7516 12:29:51.330773 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7517 12:29:51.333909 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7518 12:29:51.337051 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7519 12:29:51.340753 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7520 12:29:51.343783 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7521 12:29:51.343868
7522 12:29:51.347251 CA PerBit enable=1, Macro0, CA PI delay=35
7523 12:29:51.347360
7524 12:29:51.350545 [CBTSetCACLKResult] CA Dly = 35
7525 12:29:51.353989 CS Dly: 10 (0~42)
7526 12:29:51.357325 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 12:29:51.360671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 12:29:51.360756
7529 12:29:51.364066 ----->DramcWriteLeveling(PI) begin...
7530 12:29:51.364151 ==
7531 12:29:51.367288 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 12:29:51.370391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 12:29:51.373783 ==
7534 12:29:51.373859 Write leveling (Byte 0): 36 => 36
7535 12:29:51.377154 Write leveling (Byte 1): 28 => 28
7536 12:29:51.380522 DramcWriteLeveling(PI) end<-----
7537 12:29:51.380606
7538 12:29:51.380673 ==
7539 12:29:51.383821 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 12:29:51.390727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 12:29:51.390842 ==
7542 12:29:51.390908 [Gating] SW mode calibration
7543 12:29:51.400637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7544 12:29:51.404145 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7545 12:29:51.410107 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7546 12:29:51.413919 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 12:29:51.417148 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7548 12:29:51.420356 1 4 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (1 1)
7549 12:29:51.426688 1 4 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7550 12:29:51.430629 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7551 12:29:51.433644 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7552 12:29:51.440088 1 4 28 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7553 12:29:51.443413 1 5 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 1)
7554 12:29:51.447128 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7555 12:29:51.453359 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 12:29:51.456711 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7557 12:29:51.460024 1 5 16 | B1->B0 | 3434 2625 | 1 1 | (1 1) (0 0)
7558 12:29:51.466684 1 5 20 | B1->B0 | 2525 2626 | 0 0 | (1 0) (0 0)
7559 12:29:51.470018 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7560 12:29:51.473240 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7561 12:29:51.479897 1 6 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7562 12:29:51.483306 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7563 12:29:51.486557 1 6 8 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7564 12:29:51.493597 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7565 12:29:51.496772 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7566 12:29:51.500002 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 12:29:51.506645 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7568 12:29:51.510049 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 12:29:51.513348 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 12:29:51.520075 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 12:29:51.523265 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 12:29:51.526570 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 12:29:51.533386 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 12:29:51.536514 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7575 12:29:51.539763 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 12:29:51.546738 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:29:51.550187 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:29:51.553284 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:29:51.556390 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:29:51.563212 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:29:51.566690 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:29:51.570077 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:29:51.576637 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:29:51.579959 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:29:51.583297 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:29:51.590156 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:29:51.592843 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 12:29:51.596752 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 12:29:51.603465 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7590 12:29:51.603574 Total UI for P1: 0, mck2ui 16
7591 12:29:51.609933 best dqsien dly found for B0: ( 1, 9, 10)
7592 12:29:51.613286 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 12:29:51.616677 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 12:29:51.619973 Total UI for P1: 0, mck2ui 16
7595 12:29:51.623288 best dqsien dly found for B1: ( 1, 9, 20)
7596 12:29:51.626527 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7597 12:29:51.629778 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7598 12:29:51.629880
7599 12:29:51.636277 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7600 12:29:51.639417 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7601 12:29:51.642643 [Gating] SW calibration Done
7602 12:29:51.642744 ==
7603 12:29:51.646479 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 12:29:51.649626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 12:29:51.649727 ==
7606 12:29:51.649829 RX Vref Scan: 0
7607 12:29:51.649927
7608 12:29:51.652776 RX Vref 0 -> 0, step: 1
7609 12:29:51.652878
7610 12:29:51.656142 RX Delay 0 -> 252, step: 8
7611 12:29:51.659307 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7612 12:29:51.662708 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7613 12:29:51.669188 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7614 12:29:51.673017 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7615 12:29:51.676178 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7616 12:29:51.679614 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7617 12:29:51.682950 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7618 12:29:51.686208 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7619 12:29:51.692370 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7620 12:29:51.695682 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7621 12:29:51.699074 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7622 12:29:51.702189 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7623 12:29:51.708933 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7624 12:29:51.712264 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7625 12:29:51.715988 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7626 12:29:51.719366 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7627 12:29:51.719449 ==
7628 12:29:51.722787 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 12:29:51.725601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 12:29:51.729037 ==
7631 12:29:51.729118 DQS Delay:
7632 12:29:51.729184 DQS0 = 0, DQS1 = 0
7633 12:29:51.732793 DQM Delay:
7634 12:29:51.732891 DQM0 = 137, DQM1 = 129
7635 12:29:51.735525 DQ Delay:
7636 12:29:51.739151 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7637 12:29:51.742539 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7638 12:29:51.745502 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7639 12:29:51.749391 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7640 12:29:51.749477
7641 12:29:51.749542
7642 12:29:51.749608 ==
7643 12:29:51.752530 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:29:51.755661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:29:51.755771 ==
7646 12:29:51.758966
7647 12:29:51.759099
7648 12:29:51.759215 TX Vref Scan disable
7649 12:29:51.762091 == TX Byte 0 ==
7650 12:29:51.765331 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7651 12:29:51.768630 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7652 12:29:51.772570 == TX Byte 1 ==
7653 12:29:51.775651 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7654 12:29:51.778841 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7655 12:29:51.778926 ==
7656 12:29:51.781918 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 12:29:51.789102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 12:29:51.789188 ==
7659 12:29:51.801146
7660 12:29:51.804467 TX Vref early break, caculate TX vref
7661 12:29:51.808234 TX Vref=16, minBit 7, minWin=22, winSum=378
7662 12:29:51.811003 TX Vref=18, minBit 7, minWin=22, winSum=381
7663 12:29:51.814363 TX Vref=20, minBit 0, minWin=24, winSum=398
7664 12:29:51.818261 TX Vref=22, minBit 3, minWin=24, winSum=408
7665 12:29:51.821463 TX Vref=24, minBit 3, minWin=25, winSum=415
7666 12:29:51.828187 TX Vref=26, minBit 4, minWin=25, winSum=425
7667 12:29:51.831569 TX Vref=28, minBit 2, minWin=25, winSum=425
7668 12:29:51.834935 TX Vref=30, minBit 1, minWin=25, winSum=413
7669 12:29:51.838162 TX Vref=32, minBit 0, minWin=24, winSum=403
7670 12:29:51.841505 TX Vref=34, minBit 0, minWin=23, winSum=392
7671 12:29:51.848007 [TxChooseVref] Worse bit 4, Min win 25, Win sum 425, Final Vref 26
7672 12:29:51.848108
7673 12:29:51.851245 Final TX Range 0 Vref 26
7674 12:29:51.851359
7675 12:29:51.851428 ==
7676 12:29:51.854423 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 12:29:51.857811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 12:29:51.857896 ==
7679 12:29:51.857964
7680 12:29:51.858026
7681 12:29:51.861458 TX Vref Scan disable
7682 12:29:51.867599 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7683 12:29:51.867684 == TX Byte 0 ==
7684 12:29:51.871302 u2DelayCellOfst[0]=10 cells (3 PI)
7685 12:29:51.874766 u2DelayCellOfst[1]=13 cells (4 PI)
7686 12:29:51.878243 u2DelayCellOfst[2]=10 cells (3 PI)
7687 12:29:51.881542 u2DelayCellOfst[3]=6 cells (2 PI)
7688 12:29:51.884758 u2DelayCellOfst[4]=3 cells (1 PI)
7689 12:29:51.887993 u2DelayCellOfst[5]=0 cells (0 PI)
7690 12:29:51.891136 u2DelayCellOfst[6]=13 cells (4 PI)
7691 12:29:51.891238 u2DelayCellOfst[7]=13 cells (4 PI)
7692 12:29:51.897554 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7693 12:29:51.900965 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7694 12:29:51.901087 == TX Byte 1 ==
7695 12:29:51.904460 u2DelayCellOfst[8]=0 cells (0 PI)
7696 12:29:51.907857 u2DelayCellOfst[9]=0 cells (0 PI)
7697 12:29:51.911060 u2DelayCellOfst[10]=6 cells (2 PI)
7698 12:29:51.914260 u2DelayCellOfst[11]=3 cells (1 PI)
7699 12:29:51.917681 u2DelayCellOfst[12]=10 cells (3 PI)
7700 12:29:51.921622 u2DelayCellOfst[13]=13 cells (4 PI)
7701 12:29:51.924851 u2DelayCellOfst[14]=13 cells (4 PI)
7702 12:29:51.928052 u2DelayCellOfst[15]=10 cells (3 PI)
7703 12:29:51.931577 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7704 12:29:51.934876 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7705 12:29:51.938341 DramC Write-DBI on
7706 12:29:51.938761 ==
7707 12:29:51.941646 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 12:29:51.944862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 12:29:51.945368 ==
7710 12:29:51.945793
7711 12:29:51.947987
7712 12:29:51.948549 TX Vref Scan disable
7713 12:29:51.951322 == TX Byte 0 ==
7714 12:29:51.954686 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7715 12:29:51.957935 == TX Byte 1 ==
7716 12:29:51.961536 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7717 12:29:51.961990 DramC Write-DBI off
7718 12:29:51.962335
7719 12:29:51.964904 [DATLAT]
7720 12:29:51.965334 Freq=1600, CH0 RK0
7721 12:29:51.965679
7722 12:29:51.968046 DATLAT Default: 0xf
7723 12:29:51.968482 0, 0xFFFF, sum = 0
7724 12:29:51.971027 1, 0xFFFF, sum = 0
7725 12:29:51.971504 2, 0xFFFF, sum = 0
7726 12:29:51.974798 3, 0xFFFF, sum = 0
7727 12:29:51.975230 4, 0xFFFF, sum = 0
7728 12:29:51.978049 5, 0xFFFF, sum = 0
7729 12:29:51.978481 6, 0xFFFF, sum = 0
7730 12:29:51.981424 7, 0xFFFF, sum = 0
7731 12:29:51.984807 8, 0xFFFF, sum = 0
7732 12:29:51.985239 9, 0xFFFF, sum = 0
7733 12:29:51.988118 10, 0xFFFF, sum = 0
7734 12:29:51.988552 11, 0xFFFF, sum = 0
7735 12:29:51.991438 12, 0xFFFF, sum = 0
7736 12:29:51.991889 13, 0xFFFF, sum = 0
7737 12:29:51.994812 14, 0x0, sum = 1
7738 12:29:51.995243 15, 0x0, sum = 2
7739 12:29:51.997942 16, 0x0, sum = 3
7740 12:29:51.998372 17, 0x0, sum = 4
7741 12:29:51.998715 best_step = 15
7742 12:29:52.001528
7743 12:29:52.001956 ==
7744 12:29:52.004888 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 12:29:52.007864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 12:29:52.007947 ==
7747 12:29:52.008013 RX Vref Scan: 1
7748 12:29:52.008075
7749 12:29:52.011205 Set Vref Range= 24 -> 127
7750 12:29:52.011288
7751 12:29:52.014422 RX Vref 24 -> 127, step: 1
7752 12:29:52.014504
7753 12:29:52.017789 RX Delay 19 -> 252, step: 4
7754 12:29:52.017872
7755 12:29:52.021181 Set Vref, RX VrefLevel [Byte0]: 24
7756 12:29:52.024457 [Byte1]: 24
7757 12:29:52.024540
7758 12:29:52.027779 Set Vref, RX VrefLevel [Byte0]: 25
7759 12:29:52.031100 [Byte1]: 25
7760 12:29:52.031183
7761 12:29:52.034502 Set Vref, RX VrefLevel [Byte0]: 26
7762 12:29:52.037754 [Byte1]: 26
7763 12:29:52.041198
7764 12:29:52.041280 Set Vref, RX VrefLevel [Byte0]: 27
7765 12:29:52.044591 [Byte1]: 27
7766 12:29:52.048518
7767 12:29:52.048600 Set Vref, RX VrefLevel [Byte0]: 28
7768 12:29:52.051675 [Byte1]: 28
7769 12:29:52.056266
7770 12:29:52.056348 Set Vref, RX VrefLevel [Byte0]: 29
7771 12:29:52.059313 [Byte1]: 29
7772 12:29:52.063820
7773 12:29:52.063903 Set Vref, RX VrefLevel [Byte0]: 30
7774 12:29:52.067050 [Byte1]: 30
7775 12:29:52.071658
7776 12:29:52.071739 Set Vref, RX VrefLevel [Byte0]: 31
7777 12:29:52.074835 [Byte1]: 31
7778 12:29:52.079270
7779 12:29:52.079393 Set Vref, RX VrefLevel [Byte0]: 32
7780 12:29:52.082290 [Byte1]: 32
7781 12:29:52.086850
7782 12:29:52.086932 Set Vref, RX VrefLevel [Byte0]: 33
7783 12:29:52.090242 [Byte1]: 33
7784 12:29:52.094231
7785 12:29:52.094313 Set Vref, RX VrefLevel [Byte0]: 34
7786 12:29:52.097535 [Byte1]: 34
7787 12:29:52.101515
7788 12:29:52.101621 Set Vref, RX VrefLevel [Byte0]: 35
7789 12:29:52.104756 [Byte1]: 35
7790 12:29:52.109292
7791 12:29:52.109374 Set Vref, RX VrefLevel [Byte0]: 36
7792 12:29:52.112513 [Byte1]: 36
7793 12:29:52.117160
7794 12:29:52.117242 Set Vref, RX VrefLevel [Byte0]: 37
7795 12:29:52.120391 [Byte1]: 37
7796 12:29:52.124349
7797 12:29:52.124431 Set Vref, RX VrefLevel [Byte0]: 38
7798 12:29:52.127779 [Byte1]: 38
7799 12:29:52.131846
7800 12:29:52.131929 Set Vref, RX VrefLevel [Byte0]: 39
7801 12:29:52.135106 [Byte1]: 39
7802 12:29:52.139666
7803 12:29:52.139749 Set Vref, RX VrefLevel [Byte0]: 40
7804 12:29:52.143053 [Byte1]: 40
7805 12:29:52.147077
7806 12:29:52.147162 Set Vref, RX VrefLevel [Byte0]: 41
7807 12:29:52.150491 [Byte1]: 41
7808 12:29:52.154878
7809 12:29:52.154961 Set Vref, RX VrefLevel [Byte0]: 42
7810 12:29:52.158170 [Byte1]: 42
7811 12:29:52.162126
7812 12:29:52.162208 Set Vref, RX VrefLevel [Byte0]: 43
7813 12:29:52.165374 [Byte1]: 43
7814 12:29:52.169969
7815 12:29:52.170051 Set Vref, RX VrefLevel [Byte0]: 44
7816 12:29:52.173226 [Byte1]: 44
7817 12:29:52.177091
7818 12:29:52.177174 Set Vref, RX VrefLevel [Byte0]: 45
7819 12:29:52.180801 [Byte1]: 45
7820 12:29:52.184655
7821 12:29:52.184737 Set Vref, RX VrefLevel [Byte0]: 46
7822 12:29:52.188370 [Byte1]: 46
7823 12:29:52.192856
7824 12:29:52.192938 Set Vref, RX VrefLevel [Byte0]: 47
7825 12:29:52.196190 [Byte1]: 47
7826 12:29:52.200096
7827 12:29:52.200179 Set Vref, RX VrefLevel [Byte0]: 48
7828 12:29:52.203442 [Byte1]: 48
7829 12:29:52.207412
7830 12:29:52.207520 Set Vref, RX VrefLevel [Byte0]: 49
7831 12:29:52.211250 [Byte1]: 49
7832 12:29:52.215200
7833 12:29:52.215282 Set Vref, RX VrefLevel [Byte0]: 50
7834 12:29:52.218379 [Byte1]: 50
7835 12:29:52.222923
7836 12:29:52.223005 Set Vref, RX VrefLevel [Byte0]: 51
7837 12:29:52.226314 [Byte1]: 51
7838 12:29:52.230182
7839 12:29:52.230265 Set Vref, RX VrefLevel [Byte0]: 52
7840 12:29:52.233562 [Byte1]: 52
7841 12:29:52.238229
7842 12:29:52.238311 Set Vref, RX VrefLevel [Byte0]: 53
7843 12:29:52.241482 [Byte1]: 53
7844 12:29:52.245412
7845 12:29:52.245495 Set Vref, RX VrefLevel [Byte0]: 54
7846 12:29:52.248854 [Byte1]: 54
7847 12:29:52.253398
7848 12:29:52.253481 Set Vref, RX VrefLevel [Byte0]: 55
7849 12:29:52.256096 [Byte1]: 55
7850 12:29:52.260688
7851 12:29:52.260771 Set Vref, RX VrefLevel [Byte0]: 56
7852 12:29:52.263941 [Byte1]: 56
7853 12:29:52.268369
7854 12:29:52.268452 Set Vref, RX VrefLevel [Byte0]: 57
7855 12:29:52.271719 [Byte1]: 57
7856 12:29:52.276130
7857 12:29:52.276213 Set Vref, RX VrefLevel [Byte0]: 58
7858 12:29:52.279303 [Byte1]: 58
7859 12:29:52.283219
7860 12:29:52.283302 Set Vref, RX VrefLevel [Byte0]: 59
7861 12:29:52.287015 [Byte1]: 59
7862 12:29:52.290792
7863 12:29:52.290874 Set Vref, RX VrefLevel [Byte0]: 60
7864 12:29:52.294172 [Byte1]: 60
7865 12:29:52.298503
7866 12:29:52.298586 Set Vref, RX VrefLevel [Byte0]: 61
7867 12:29:52.301801 [Byte1]: 61
7868 12:29:52.305911
7869 12:29:52.305996 Set Vref, RX VrefLevel [Byte0]: 62
7870 12:29:52.309276 [Byte1]: 62
7871 12:29:52.313801
7872 12:29:52.313883 Set Vref, RX VrefLevel [Byte0]: 63
7873 12:29:52.316832 [Byte1]: 63
7874 12:29:52.321425
7875 12:29:52.321507 Set Vref, RX VrefLevel [Byte0]: 64
7876 12:29:52.324589 [Byte1]: 64
7877 12:29:52.329158
7878 12:29:52.329241 Set Vref, RX VrefLevel [Byte0]: 65
7879 12:29:52.332576 [Byte1]: 65
7880 12:29:52.336539
7881 12:29:52.336622 Set Vref, RX VrefLevel [Byte0]: 66
7882 12:29:52.339953 [Byte1]: 66
7883 12:29:52.344035
7884 12:29:52.344117 Set Vref, RX VrefLevel [Byte0]: 67
7885 12:29:52.347428 [Byte1]: 67
7886 12:29:52.351305
7887 12:29:52.351422 Set Vref, RX VrefLevel [Byte0]: 68
7888 12:29:52.354735 [Byte1]: 68
7889 12:29:52.359262
7890 12:29:52.359381 Set Vref, RX VrefLevel [Byte0]: 69
7891 12:29:52.362701 [Byte1]: 69
7892 12:29:52.366792
7893 12:29:52.366874 Set Vref, RX VrefLevel [Byte0]: 70
7894 12:29:52.370024 [Byte1]: 70
7895 12:29:52.374361
7896 12:29:52.374443 Set Vref, RX VrefLevel [Byte0]: 71
7897 12:29:52.377512 [Byte1]: 71
7898 12:29:52.382046
7899 12:29:52.382166 Set Vref, RX VrefLevel [Byte0]: 72
7900 12:29:52.385080 [Byte1]: 72
7901 12:29:52.389619
7902 12:29:52.389701 Set Vref, RX VrefLevel [Byte0]: 73
7903 12:29:52.392892 [Byte1]: 73
7904 12:29:52.396653
7905 12:29:52.396735 Set Vref, RX VrefLevel [Byte0]: 74
7906 12:29:52.400478 [Byte1]: 74
7907 12:29:52.404264
7908 12:29:52.404347 Set Vref, RX VrefLevel [Byte0]: 75
7909 12:29:52.407922 [Byte1]: 75
7910 12:29:52.411942
7911 12:29:52.412025 Final RX Vref Byte 0 = 56 to rank0
7912 12:29:52.415225 Final RX Vref Byte 1 = 60 to rank0
7913 12:29:52.419202 Final RX Vref Byte 0 = 56 to rank1
7914 12:29:52.422331 Final RX Vref Byte 1 = 60 to rank1==
7915 12:29:52.425663 Dram Type= 6, Freq= 0, CH_0, rank 0
7916 12:29:52.432153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7917 12:29:52.432240 ==
7918 12:29:52.432326 DQS Delay:
7919 12:29:52.432406 DQS0 = 0, DQS1 = 0
7920 12:29:52.435439 DQM Delay:
7921 12:29:52.435524 DQM0 = 134, DQM1 = 127
7922 12:29:52.438791 DQ Delay:
7923 12:29:52.442108 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7924 12:29:52.445491 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7925 12:29:52.448854 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7926 12:29:52.452186 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7927 12:29:52.452269
7928 12:29:52.452334
7929 12:29:52.452396
7930 12:29:52.455196 [DramC_TX_OE_Calibration] TA2
7931 12:29:52.458390 Original DQ_B0 (3 6) =30, OEN = 27
7932 12:29:52.461805 Original DQ_B1 (3 6) =30, OEN = 27
7933 12:29:52.465120 24, 0x0, End_B0=24 End_B1=24
7934 12:29:52.465205 25, 0x0, End_B0=25 End_B1=25
7935 12:29:52.468551 26, 0x0, End_B0=26 End_B1=26
7936 12:29:52.471871 27, 0x0, End_B0=27 End_B1=27
7937 12:29:52.475096 28, 0x0, End_B0=28 End_B1=28
7938 12:29:52.475181 29, 0x0, End_B0=29 End_B1=29
7939 12:29:52.478366 30, 0x0, End_B0=30 End_B1=30
7940 12:29:52.481608 31, 0x4545, End_B0=30 End_B1=30
7941 12:29:52.485454 Byte0 end_step=30 best_step=27
7942 12:29:52.488617 Byte1 end_step=30 best_step=27
7943 12:29:52.491605 Byte0 TX OE(2T, 0.5T) = (3, 3)
7944 12:29:52.491688 Byte1 TX OE(2T, 0.5T) = (3, 3)
7945 12:29:52.495387
7946 12:29:52.495469
7947 12:29:52.501761 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7948 12:29:52.505474 CH0 RK0: MR19=303, MR18=2420
7949 12:29:52.511598 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7950 12:29:52.511693
7951 12:29:52.515131 ----->DramcWriteLeveling(PI) begin...
7952 12:29:52.515215 ==
7953 12:29:52.518394 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 12:29:52.521617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 12:29:52.521701 ==
7956 12:29:52.524999 Write leveling (Byte 0): 37 => 37
7957 12:29:52.528354 Write leveling (Byte 1): 28 => 28
7958 12:29:52.531655 DramcWriteLeveling(PI) end<-----
7959 12:29:52.531739
7960 12:29:52.531805 ==
7961 12:29:52.535146 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 12:29:52.538114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 12:29:52.538198 ==
7964 12:29:52.541283 [Gating] SW mode calibration
7965 12:29:52.547876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7966 12:29:52.555272 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7967 12:29:52.557979 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 12:29:52.561266 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 12:29:52.567943 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 12:29:52.571239 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 12:29:52.574658 1 4 16 | B1->B0 | 2e2e 3535 | 1 0 | (1 1) (0 0)
7972 12:29:52.581382 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 12:29:52.584647 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 12:29:52.588004 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7975 12:29:52.594416 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 12:29:52.598331 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7977 12:29:52.601311 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
7978 12:29:52.607764 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
7979 12:29:52.611659 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
7980 12:29:52.614809 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 12:29:52.621513 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 12:29:52.624605 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7983 12:29:52.627754 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 12:29:52.634969 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7985 12:29:52.637680 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 12:29:52.641102 1 6 12 | B1->B0 | 2525 3a39 | 0 1 | (0 0) (1 1)
7987 12:29:52.647966 1 6 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
7988 12:29:52.651222 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 12:29:52.653916 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 12:29:52.660692 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 12:29:52.663986 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 12:29:52.667317 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 12:29:52.674482 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 12:29:52.677993 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7995 12:29:52.680620 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7996 12:29:52.687577 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 12:29:52.690840 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 12:29:52.694198 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 12:29:52.700560 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 12:29:52.703724 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 12:29:52.707492 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 12:29:52.713916 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 12:29:52.717234 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 12:29:52.720354 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:29:52.727123 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:29:52.730824 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:29:52.733995 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:29:52.737256 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:29:52.744200 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:29:52.747530 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8011 12:29:52.750645 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 12:29:52.753853 Total UI for P1: 0, mck2ui 16
8013 12:29:52.757135 best dqsien dly found for B0: ( 1, 9, 12)
8014 12:29:52.760261 Total UI for P1: 0, mck2ui 16
8015 12:29:52.763647 best dqsien dly found for B1: ( 1, 9, 12)
8016 12:29:52.767120 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8017 12:29:52.770473 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8018 12:29:52.773716
8019 12:29:52.776956 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8020 12:29:52.780320 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8021 12:29:52.783660 [Gating] SW calibration Done
8022 12:29:52.783743 ==
8023 12:29:52.787043 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 12:29:52.790322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 12:29:52.790406 ==
8026 12:29:52.790473 RX Vref Scan: 0
8027 12:29:52.790533
8028 12:29:52.793788 RX Vref 0 -> 0, step: 1
8029 12:29:52.793872
8030 12:29:52.797072 RX Delay 0 -> 252, step: 8
8031 12:29:52.800598 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8032 12:29:52.803743 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8033 12:29:52.806902 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8034 12:29:52.813845 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8035 12:29:52.816893 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8036 12:29:52.820537 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8037 12:29:52.823856 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8038 12:29:52.826968 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8039 12:29:52.833934 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8040 12:29:52.837030 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8041 12:29:52.840138 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8042 12:29:52.843888 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8043 12:29:52.847143 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8044 12:29:52.853869 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8045 12:29:52.857159 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8046 12:29:52.860461 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8047 12:29:52.860544 ==
8048 12:29:52.863556 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 12:29:52.866947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 12:29:52.870263 ==
8051 12:29:52.870343 DQS Delay:
8052 12:29:52.870408 DQS0 = 0, DQS1 = 0
8053 12:29:52.873508 DQM Delay:
8054 12:29:52.873592 DQM0 = 136, DQM1 = 128
8055 12:29:52.877045 DQ Delay:
8056 12:29:52.880080 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8057 12:29:52.883951 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8058 12:29:52.886661 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8059 12:29:52.890144 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8060 12:29:52.890230
8061 12:29:52.890296
8062 12:29:52.890358 ==
8063 12:29:52.893422 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 12:29:52.896799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 12:29:52.896883 ==
8066 12:29:52.896950
8067 12:29:52.900212
8068 12:29:52.900295 TX Vref Scan disable
8069 12:29:52.903339 == TX Byte 0 ==
8070 12:29:52.906729 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8071 12:29:52.910042 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8072 12:29:52.913962 == TX Byte 1 ==
8073 12:29:52.917082 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8074 12:29:52.920416 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8075 12:29:52.920497 ==
8076 12:29:52.923721 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 12:29:52.929928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 12:29:52.930016 ==
8079 12:29:52.942462
8080 12:29:52.946069 TX Vref early break, caculate TX vref
8081 12:29:52.949099 TX Vref=16, minBit 3, minWin=22, winSum=387
8082 12:29:52.952423 TX Vref=18, minBit 0, minWin=23, winSum=393
8083 12:29:52.955749 TX Vref=20, minBit 2, minWin=24, winSum=404
8084 12:29:52.959007 TX Vref=22, minBit 3, minWin=24, winSum=411
8085 12:29:52.962883 TX Vref=24, minBit 1, minWin=25, winSum=420
8086 12:29:52.969282 TX Vref=26, minBit 3, minWin=25, winSum=428
8087 12:29:52.972673 TX Vref=28, minBit 3, minWin=25, winSum=423
8088 12:29:52.976176 TX Vref=30, minBit 3, minWin=25, winSum=418
8089 12:29:52.979359 TX Vref=32, minBit 4, minWin=24, winSum=410
8090 12:29:52.982768 TX Vref=34, minBit 0, minWin=24, winSum=401
8091 12:29:52.989072 [TxChooseVref] Worse bit 3, Min win 25, Win sum 428, Final Vref 26
8092 12:29:52.989189
8093 12:29:52.992407 Final TX Range 0 Vref 26
8094 12:29:52.992482
8095 12:29:52.992548 ==
8096 12:29:52.995761 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 12:29:52.999167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 12:29:52.999240 ==
8099 12:29:52.999322
8100 12:29:52.999437
8101 12:29:53.002588 TX Vref Scan disable
8102 12:29:53.009237 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8103 12:29:53.009314 == TX Byte 0 ==
8104 12:29:53.012675 u2DelayCellOfst[0]=10 cells (3 PI)
8105 12:29:53.016025 u2DelayCellOfst[1]=13 cells (4 PI)
8106 12:29:53.019176 u2DelayCellOfst[2]=6 cells (2 PI)
8107 12:29:53.022275 u2DelayCellOfst[3]=6 cells (2 PI)
8108 12:29:53.026123 u2DelayCellOfst[4]=6 cells (2 PI)
8109 12:29:53.029271 u2DelayCellOfst[5]=0 cells (0 PI)
8110 12:29:53.029374 u2DelayCellOfst[6]=13 cells (4 PI)
8111 12:29:53.032467 u2DelayCellOfst[7]=13 cells (4 PI)
8112 12:29:53.038877 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8113 12:29:53.042590 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8114 12:29:53.042682 == TX Byte 1 ==
8115 12:29:53.045674 u2DelayCellOfst[8]=3 cells (1 PI)
8116 12:29:53.048791 u2DelayCellOfst[9]=0 cells (0 PI)
8117 12:29:53.052655 u2DelayCellOfst[10]=6 cells (2 PI)
8118 12:29:53.055839 u2DelayCellOfst[11]=6 cells (2 PI)
8119 12:29:53.059259 u2DelayCellOfst[12]=10 cells (3 PI)
8120 12:29:53.062641 u2DelayCellOfst[13]=10 cells (3 PI)
8121 12:29:53.065668 u2DelayCellOfst[14]=13 cells (4 PI)
8122 12:29:53.069094 u2DelayCellOfst[15]=10 cells (3 PI)
8123 12:29:53.072378 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8124 12:29:53.078914 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8125 12:29:53.078998 DramC Write-DBI on
8126 12:29:53.079066 ==
8127 12:29:53.082266 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 12:29:53.085545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 12:29:53.085636 ==
8130 12:29:53.085730
8131 12:29:53.088841
8132 12:29:53.088913 TX Vref Scan disable
8133 12:29:53.092666 == TX Byte 0 ==
8134 12:29:53.095905 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8135 12:29:53.099228 == TX Byte 1 ==
8136 12:29:53.102573 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8137 12:29:53.102707 DramC Write-DBI off
8138 12:29:53.102775
8139 12:29:53.106047 [DATLAT]
8140 12:29:53.106122 Freq=1600, CH0 RK1
8141 12:29:53.106185
8142 12:29:53.109319 DATLAT Default: 0xf
8143 12:29:53.109393 0, 0xFFFF, sum = 0
8144 12:29:53.111987 1, 0xFFFF, sum = 0
8145 12:29:53.112061 2, 0xFFFF, sum = 0
8146 12:29:53.115457 3, 0xFFFF, sum = 0
8147 12:29:53.115537 4, 0xFFFF, sum = 0
8148 12:29:53.118761 5, 0xFFFF, sum = 0
8149 12:29:53.118837 6, 0xFFFF, sum = 0
8150 12:29:53.121986 7, 0xFFFF, sum = 0
8151 12:29:53.125299 8, 0xFFFF, sum = 0
8152 12:29:53.125380 9, 0xFFFF, sum = 0
8153 12:29:53.128836 10, 0xFFFF, sum = 0
8154 12:29:53.128910 11, 0xFFFF, sum = 0
8155 12:29:53.131997 12, 0xFFFF, sum = 0
8156 12:29:53.132074 13, 0xFFFF, sum = 0
8157 12:29:53.135242 14, 0x0, sum = 1
8158 12:29:53.135317 15, 0x0, sum = 2
8159 12:29:53.139109 16, 0x0, sum = 3
8160 12:29:53.139182 17, 0x0, sum = 4
8161 12:29:53.142420 best_step = 15
8162 12:29:53.142490
8163 12:29:53.142549 ==
8164 12:29:53.145686 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 12:29:53.149027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 12:29:53.149112 ==
8167 12:29:53.149178 RX Vref Scan: 0
8168 12:29:53.151924
8169 12:29:53.152008 RX Vref 0 -> 0, step: 1
8170 12:29:53.152074
8171 12:29:53.155551 RX Delay 19 -> 252, step: 4
8172 12:29:53.158805 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8173 12:29:53.165342 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8174 12:29:53.168525 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8175 12:29:53.171847 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8176 12:29:53.175149 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8177 12:29:53.178455 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8178 12:29:53.184978 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8179 12:29:53.188321 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8180 12:29:53.191683 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8181 12:29:53.195111 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8182 12:29:53.198345 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8183 12:29:53.204903 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8184 12:29:53.208252 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8185 12:29:53.211468 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8186 12:29:53.215405 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8187 12:29:53.218231 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8188 12:29:53.221505 ==
8189 12:29:53.221591 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 12:29:53.228444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 12:29:53.228531 ==
8192 12:29:53.228600 DQS Delay:
8193 12:29:53.231648 DQS0 = 0, DQS1 = 0
8194 12:29:53.231733 DQM Delay:
8195 12:29:53.234735 DQM0 = 134, DQM1 = 127
8196 12:29:53.234821 DQ Delay:
8197 12:29:53.238017 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8198 12:29:53.241511 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8199 12:29:53.244674 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8200 12:29:53.248413 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8201 12:29:53.248498
8202 12:29:53.248566
8203 12:29:53.248630
8204 12:29:53.251672 [DramC_TX_OE_Calibration] TA2
8205 12:29:53.254687 Original DQ_B0 (3 6) =30, OEN = 27
8206 12:29:53.258444 Original DQ_B1 (3 6) =30, OEN = 27
8207 12:29:53.261385 24, 0x0, End_B0=24 End_B1=24
8208 12:29:53.264700 25, 0x0, End_B0=25 End_B1=25
8209 12:29:53.264787 26, 0x0, End_B0=26 End_B1=26
8210 12:29:53.268508 27, 0x0, End_B0=27 End_B1=27
8211 12:29:53.271719 28, 0x0, End_B0=28 End_B1=28
8212 12:29:53.274994 29, 0x0, End_B0=29 End_B1=29
8213 12:29:53.278283 30, 0x0, End_B0=30 End_B1=30
8214 12:29:53.278369 31, 0x4545, End_B0=30 End_B1=30
8215 12:29:53.281653 Byte0 end_step=30 best_step=27
8216 12:29:53.284961 Byte1 end_step=30 best_step=27
8217 12:29:53.288126 Byte0 TX OE(2T, 0.5T) = (3, 3)
8218 12:29:53.291265 Byte1 TX OE(2T, 0.5T) = (3, 3)
8219 12:29:53.291392
8220 12:29:53.291461
8221 12:29:53.298169 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8222 12:29:53.301522 CH0 RK1: MR19=303, MR18=1F07
8223 12:29:53.308195 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8224 12:29:53.311366 [RxdqsGatingPostProcess] freq 1600
8225 12:29:53.314631 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8226 12:29:53.318018 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 12:29:53.321272 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 12:29:53.324612 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 12:29:53.328032 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 12:29:53.331441 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 12:29:53.334738 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 12:29:53.338101 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 12:29:53.341346 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 12:29:53.344560 Pre-setting of DQS Precalculation
8235 12:29:53.347644 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8236 12:29:53.347729 ==
8237 12:29:53.351237 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 12:29:53.358173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 12:29:53.358283 ==
8240 12:29:53.361413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8241 12:29:53.364446 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8242 12:29:53.371221 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8243 12:29:53.377995 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8244 12:29:53.385127 [CA 0] Center 41 (11~71) winsize 61
8245 12:29:53.388542 [CA 1] Center 41 (12~71) winsize 60
8246 12:29:53.391825 [CA 2] Center 38 (9~68) winsize 60
8247 12:29:53.395113 [CA 3] Center 37 (8~66) winsize 59
8248 12:29:53.398366 [CA 4] Center 37 (8~67) winsize 60
8249 12:29:53.401737 [CA 5] Center 36 (7~66) winsize 60
8250 12:29:53.401820
8251 12:29:53.405011 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8252 12:29:53.405116
8253 12:29:53.408494 [CATrainingPosCal] consider 1 rank data
8254 12:29:53.412263 u2DelayCellTimex100 = 290/100 ps
8255 12:29:53.415296 CA0 delay=41 (11~71),Diff = 5 PI (16 cell)
8256 12:29:53.422170 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8257 12:29:53.425381 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8258 12:29:53.428681 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8259 12:29:53.432183 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8260 12:29:53.434973 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8261 12:29:53.435091
8262 12:29:53.438381 CA PerBit enable=1, Macro0, CA PI delay=36
8263 12:29:53.438465
8264 12:29:53.441711 [CBTSetCACLKResult] CA Dly = 36
8265 12:29:53.445009 CS Dly: 11 (0~42)
8266 12:29:53.448202 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8267 12:29:53.451588 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8268 12:29:53.451740 ==
8269 12:29:53.454669 Dram Type= 6, Freq= 0, CH_1, rank 1
8270 12:29:53.458421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 12:29:53.461514 ==
8272 12:29:53.464695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8273 12:29:53.468448 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8274 12:29:53.474788 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8275 12:29:53.481123 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8276 12:29:53.488533 [CA 0] Center 41 (12~71) winsize 60
8277 12:29:53.491748 [CA 1] Center 41 (12~71) winsize 60
8278 12:29:53.495226 [CA 2] Center 38 (9~68) winsize 60
8279 12:29:53.498561 [CA 3] Center 37 (8~67) winsize 60
8280 12:29:53.501766 [CA 4] Center 38 (8~68) winsize 61
8281 12:29:53.505314 [CA 5] Center 37 (7~67) winsize 61
8282 12:29:53.505426
8283 12:29:53.507989 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8284 12:29:53.508114
8285 12:29:53.511340 [CATrainingPosCal] consider 2 rank data
8286 12:29:53.514889 u2DelayCellTimex100 = 290/100 ps
8287 12:29:53.518292 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8288 12:29:53.525287 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8289 12:29:53.528016 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8290 12:29:53.531766 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8291 12:29:53.535217 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8292 12:29:53.537797 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8293 12:29:53.537905
8294 12:29:53.541346 CA PerBit enable=1, Macro0, CA PI delay=36
8295 12:29:53.541452
8296 12:29:53.544795 [CBTSetCACLKResult] CA Dly = 36
8297 12:29:53.548036 CS Dly: 12 (0~45)
8298 12:29:53.551248 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8299 12:29:53.554459 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8300 12:29:53.554563
8301 12:29:53.557756 ----->DramcWriteLeveling(PI) begin...
8302 12:29:53.557848 ==
8303 12:29:53.560995 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 12:29:53.565014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 12:29:53.568120 ==
8306 12:29:53.568216 Write leveling (Byte 0): 26 => 26
8307 12:29:53.571617 Write leveling (Byte 1): 27 => 27
8308 12:29:53.574680 DramcWriteLeveling(PI) end<-----
8309 12:29:53.574760
8310 12:29:53.574824 ==
8311 12:29:53.577933 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 12:29:53.584731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 12:29:53.584814 ==
8314 12:29:53.587781 [Gating] SW mode calibration
8315 12:29:53.594445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8316 12:29:53.598353 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8317 12:29:53.605024 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 12:29:53.608182 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 12:29:53.611608 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8320 12:29:53.615022 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8321 12:29:53.621594 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 12:29:53.624808 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 12:29:53.628029 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 12:29:53.634307 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 12:29:53.637968 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 12:29:53.641372 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8327 12:29:53.648010 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8328 12:29:53.651493 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8329 12:29:53.654534 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 12:29:53.661334 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 12:29:53.664648 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 12:29:53.668196 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 12:29:53.674595 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 12:29:53.678241 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8335 12:29:53.681414 1 6 8 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
8336 12:29:53.688174 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8337 12:29:53.691217 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 12:29:53.694308 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 12:29:53.701139 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 12:29:53.704781 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 12:29:53.708093 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 12:29:53.714505 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 12:29:53.717852 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 12:29:53.721181 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 12:29:53.727796 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 12:29:53.731043 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 12:29:53.734383 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 12:29:53.737736 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 12:29:53.744161 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 12:29:53.747855 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 12:29:53.751250 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 12:29:53.757937 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 12:29:53.761244 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 12:29:53.764542 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:29:53.771058 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:29:53.774567 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:29:53.777842 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:29:53.784288 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:29:53.787298 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 12:29:53.791128 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 12:29:53.797362 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 12:29:53.797447 Total UI for P1: 0, mck2ui 16
8363 12:29:53.803948 best dqsien dly found for B0: ( 1, 9, 10)
8364 12:29:53.804033 Total UI for P1: 0, mck2ui 16
8365 12:29:53.810689 best dqsien dly found for B1: ( 1, 9, 10)
8366 12:29:53.814070 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8367 12:29:53.817374 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8368 12:29:53.817457
8369 12:29:53.820547 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 12:29:53.823958 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8371 12:29:53.827279 [Gating] SW calibration Done
8372 12:29:53.827384 ==
8373 12:29:53.830652 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 12:29:53.833815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 12:29:53.833899 ==
8376 12:29:53.837709 RX Vref Scan: 0
8377 12:29:53.837792
8378 12:29:53.837857 RX Vref 0 -> 0, step: 1
8379 12:29:53.837918
8380 12:29:53.840527 RX Delay 0 -> 252, step: 8
8381 12:29:53.843802 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8382 12:29:53.850969 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8383 12:29:53.854079 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8384 12:29:53.857467 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8385 12:29:53.860752 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8386 12:29:53.864026 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8387 12:29:53.870703 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8388 12:29:53.873993 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8389 12:29:53.877442 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8390 12:29:53.880747 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8391 12:29:53.884141 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8392 12:29:53.887533 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8393 12:29:53.893869 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8394 12:29:53.897475 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8395 12:29:53.900694 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8396 12:29:53.903962 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8397 12:29:53.904046 ==
8398 12:29:53.907142 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 12:29:53.913890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 12:29:53.913975 ==
8401 12:29:53.914042 DQS Delay:
8402 12:29:53.917613 DQS0 = 0, DQS1 = 0
8403 12:29:53.917697 DQM Delay:
8404 12:29:53.917765 DQM0 = 136, DQM1 = 132
8405 12:29:53.920710 DQ Delay:
8406 12:29:53.924016 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8407 12:29:53.927130 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8408 12:29:53.930453 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8409 12:29:53.933825 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8410 12:29:53.933910
8411 12:29:53.933976
8412 12:29:53.934037 ==
8413 12:29:53.937220 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 12:29:53.940493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 12:29:53.943763 ==
8416 12:29:53.943840
8417 12:29:53.943908
8418 12:29:53.943971 TX Vref Scan disable
8419 12:29:53.947220 == TX Byte 0 ==
8420 12:29:53.950517 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8421 12:29:53.953944 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8422 12:29:53.957106 == TX Byte 1 ==
8423 12:29:53.961015 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8424 12:29:53.964350 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8425 12:29:53.967451 ==
8426 12:29:53.967533 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 12:29:53.974007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 12:29:53.974090 ==
8429 12:29:53.985241
8430 12:29:53.989184 TX Vref early break, caculate TX vref
8431 12:29:53.992448 TX Vref=16, minBit 1, minWin=22, winSum=381
8432 12:29:53.995860 TX Vref=18, minBit 1, minWin=22, winSum=383
8433 12:29:53.999112 TX Vref=20, minBit 1, minWin=23, winSum=396
8434 12:29:54.002457 TX Vref=22, minBit 6, minWin=24, winSum=405
8435 12:29:54.005542 TX Vref=24, minBit 1, minWin=24, winSum=418
8436 12:29:54.011926 TX Vref=26, minBit 0, minWin=25, winSum=425
8437 12:29:54.015415 TX Vref=28, minBit 1, minWin=25, winSum=426
8438 12:29:54.018555 TX Vref=30, minBit 0, minWin=25, winSum=422
8439 12:29:54.022324 TX Vref=32, minBit 2, minWin=23, winSum=413
8440 12:29:54.025319 TX Vref=34, minBit 2, minWin=23, winSum=401
8441 12:29:54.032570 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8442 12:29:54.032652
8443 12:29:54.035579 Final TX Range 0 Vref 28
8444 12:29:54.035661
8445 12:29:54.035726 ==
8446 12:29:54.038930 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 12:29:54.042316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 12:29:54.042403 ==
8449 12:29:54.042468
8450 12:29:54.042528
8451 12:29:54.045449 TX Vref Scan disable
8452 12:29:54.052172 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8453 12:29:54.052255 == TX Byte 0 ==
8454 12:29:54.055522 u2DelayCellOfst[0]=16 cells (5 PI)
8455 12:29:54.058659 u2DelayCellOfst[1]=10 cells (3 PI)
8456 12:29:54.062021 u2DelayCellOfst[2]=0 cells (0 PI)
8457 12:29:54.065237 u2DelayCellOfst[3]=6 cells (2 PI)
8458 12:29:54.068389 u2DelayCellOfst[4]=6 cells (2 PI)
8459 12:29:54.071724 u2DelayCellOfst[5]=20 cells (6 PI)
8460 12:29:54.074901 u2DelayCellOfst[6]=20 cells (6 PI)
8461 12:29:54.074983 u2DelayCellOfst[7]=6 cells (2 PI)
8462 12:29:54.082775 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8463 12:29:54.085373 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8464 12:29:54.085456 == TX Byte 1 ==
8465 12:29:54.088644 u2DelayCellOfst[8]=0 cells (0 PI)
8466 12:29:54.091749 u2DelayCellOfst[9]=3 cells (1 PI)
8467 12:29:54.095237 u2DelayCellOfst[10]=10 cells (3 PI)
8468 12:29:54.098708 u2DelayCellOfst[11]=3 cells (1 PI)
8469 12:29:54.101879 u2DelayCellOfst[12]=13 cells (4 PI)
8470 12:29:54.105123 u2DelayCellOfst[13]=16 cells (5 PI)
8471 12:29:54.108522 u2DelayCellOfst[14]=16 cells (5 PI)
8472 12:29:54.111880 u2DelayCellOfst[15]=16 cells (5 PI)
8473 12:29:54.115044 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8474 12:29:54.121894 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8475 12:29:54.121977 DramC Write-DBI on
8476 12:29:54.122043 ==
8477 12:29:54.125066 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 12:29:54.128686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 12:29:54.128769 ==
8480 12:29:54.128834
8481 12:29:54.131765
8482 12:29:54.131847 TX Vref Scan disable
8483 12:29:54.134913 == TX Byte 0 ==
8484 12:29:54.138699 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8485 12:29:54.141942 == TX Byte 1 ==
8486 12:29:54.145201 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8487 12:29:54.145283 DramC Write-DBI off
8488 12:29:54.145349
8489 12:29:54.148399 [DATLAT]
8490 12:29:54.148480 Freq=1600, CH1 RK0
8491 12:29:54.148546
8492 12:29:54.152299 DATLAT Default: 0xf
8493 12:29:54.152382 0, 0xFFFF, sum = 0
8494 12:29:54.154866 1, 0xFFFF, sum = 0
8495 12:29:54.154965 2, 0xFFFF, sum = 0
8496 12:29:54.159013 3, 0xFFFF, sum = 0
8497 12:29:54.159113 4, 0xFFFF, sum = 0
8498 12:29:54.161639 5, 0xFFFF, sum = 0
8499 12:29:54.161739 6, 0xFFFF, sum = 0
8500 12:29:54.165531 7, 0xFFFF, sum = 0
8501 12:29:54.165656 8, 0xFFFF, sum = 0
8502 12:29:54.168792 9, 0xFFFF, sum = 0
8503 12:29:54.172010 10, 0xFFFF, sum = 0
8504 12:29:54.172133 11, 0xFFFF, sum = 0
8505 12:29:54.175148 12, 0xFFFF, sum = 0
8506 12:29:54.175260 13, 0xFFFF, sum = 0
8507 12:29:54.178336 14, 0x0, sum = 1
8508 12:29:54.178420 15, 0x0, sum = 2
8509 12:29:54.181644 16, 0x0, sum = 3
8510 12:29:54.181768 17, 0x0, sum = 4
8511 12:29:54.181865 best_step = 15
8512 12:29:54.184954
8513 12:29:54.185071 ==
8514 12:29:54.188378 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 12:29:54.191810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 12:29:54.191897 ==
8517 12:29:54.191967 RX Vref Scan: 1
8518 12:29:54.192057
8519 12:29:54.195033 Set Vref Range= 24 -> 127
8520 12:29:54.195141
8521 12:29:54.198344 RX Vref 24 -> 127, step: 1
8522 12:29:54.198447
8523 12:29:54.201730 RX Delay 27 -> 252, step: 4
8524 12:29:54.201819
8525 12:29:54.205150 Set Vref, RX VrefLevel [Byte0]: 24
8526 12:29:54.208368 [Byte1]: 24
8527 12:29:54.208476
8528 12:29:54.211680 Set Vref, RX VrefLevel [Byte0]: 25
8529 12:29:54.215100 [Byte1]: 25
8530 12:29:54.215207
8531 12:29:54.218315 Set Vref, RX VrefLevel [Byte0]: 26
8532 12:29:54.221663 [Byte1]: 26
8533 12:29:54.224771
8534 12:29:54.224854 Set Vref, RX VrefLevel [Byte0]: 27
8535 12:29:54.228531 [Byte1]: 27
8536 12:29:54.232308
8537 12:29:54.232390 Set Vref, RX VrefLevel [Byte0]: 28
8538 12:29:54.236000 [Byte1]: 28
8539 12:29:54.239685
8540 12:29:54.239768 Set Vref, RX VrefLevel [Byte0]: 29
8541 12:29:54.243453 [Byte1]: 29
8542 12:29:54.247314
8543 12:29:54.247448 Set Vref, RX VrefLevel [Byte0]: 30
8544 12:29:54.250628 [Byte1]: 30
8545 12:29:54.254943
8546 12:29:54.255027 Set Vref, RX VrefLevel [Byte0]: 31
8547 12:29:54.258110 [Byte1]: 31
8548 12:29:54.262696
8549 12:29:54.262805 Set Vref, RX VrefLevel [Byte0]: 32
8550 12:29:54.269244 [Byte1]: 32
8551 12:29:54.269331
8552 12:29:54.272608 Set Vref, RX VrefLevel [Byte0]: 33
8553 12:29:54.275967 [Byte1]: 33
8554 12:29:54.276050
8555 12:29:54.279091 Set Vref, RX VrefLevel [Byte0]: 34
8556 12:29:54.282159 [Byte1]: 34
8557 12:29:54.282242
8558 12:29:54.285608 Set Vref, RX VrefLevel [Byte0]: 35
8559 12:29:54.288809 [Byte1]: 35
8560 12:29:54.292899
8561 12:29:54.293006 Set Vref, RX VrefLevel [Byte0]: 36
8562 12:29:54.295649 [Byte1]: 36
8563 12:29:54.300133
8564 12:29:54.300239 Set Vref, RX VrefLevel [Byte0]: 37
8565 12:29:54.303396 [Byte1]: 37
8566 12:29:54.307449
8567 12:29:54.307523 Set Vref, RX VrefLevel [Byte0]: 38
8568 12:29:54.310743 [Byte1]: 38
8569 12:29:54.315380
8570 12:29:54.315485 Set Vref, RX VrefLevel [Byte0]: 39
8571 12:29:54.318765 [Byte1]: 39
8572 12:29:54.322897
8573 12:29:54.323000 Set Vref, RX VrefLevel [Byte0]: 40
8574 12:29:54.326216 [Byte1]: 40
8575 12:29:54.330162
8576 12:29:54.330265 Set Vref, RX VrefLevel [Byte0]: 41
8577 12:29:54.333706 [Byte1]: 41
8578 12:29:54.338039
8579 12:29:54.338150 Set Vref, RX VrefLevel [Byte0]: 42
8580 12:29:54.341258 [Byte1]: 42
8581 12:29:54.345661
8582 12:29:54.345745 Set Vref, RX VrefLevel [Byte0]: 43
8583 12:29:54.348836 [Byte1]: 43
8584 12:29:54.353187
8585 12:29:54.353269 Set Vref, RX VrefLevel [Byte0]: 44
8586 12:29:54.356350 [Byte1]: 44
8587 12:29:54.360307
8588 12:29:54.360394 Set Vref, RX VrefLevel [Byte0]: 45
8589 12:29:54.363468 [Byte1]: 45
8590 12:29:54.367861
8591 12:29:54.367989 Set Vref, RX VrefLevel [Byte0]: 46
8592 12:29:54.371047 [Byte1]: 46
8593 12:29:54.375929
8594 12:29:54.376010 Set Vref, RX VrefLevel [Byte0]: 47
8595 12:29:54.379187 [Byte1]: 47
8596 12:29:54.383152
8597 12:29:54.383234 Set Vref, RX VrefLevel [Byte0]: 48
8598 12:29:54.386246 [Byte1]: 48
8599 12:29:54.390601
8600 12:29:54.390682 Set Vref, RX VrefLevel [Byte0]: 49
8601 12:29:54.394081 [Byte1]: 49
8602 12:29:54.397931
8603 12:29:54.398013 Set Vref, RX VrefLevel [Byte0]: 50
8604 12:29:54.401310 [Byte1]: 50
8605 12:29:54.405860
8606 12:29:54.405942 Set Vref, RX VrefLevel [Byte0]: 51
8607 12:29:54.409330 [Byte1]: 51
8608 12:29:54.413256
8609 12:29:54.413338 Set Vref, RX VrefLevel [Byte0]: 52
8610 12:29:54.416545 [Byte1]: 52
8611 12:29:54.420572
8612 12:29:54.420668 Set Vref, RX VrefLevel [Byte0]: 53
8613 12:29:54.423962 [Byte1]: 53
8614 12:29:54.428092
8615 12:29:54.428188 Set Vref, RX VrefLevel [Byte0]: 54
8616 12:29:54.431466 [Byte1]: 54
8617 12:29:54.435969
8618 12:29:54.436052 Set Vref, RX VrefLevel [Byte0]: 55
8619 12:29:54.439196 [Byte1]: 55
8620 12:29:54.443529
8621 12:29:54.443611 Set Vref, RX VrefLevel [Byte0]: 56
8622 12:29:54.446502 [Byte1]: 56
8623 12:29:54.451011
8624 12:29:54.451093 Set Vref, RX VrefLevel [Byte0]: 57
8625 12:29:54.454007 [Byte1]: 57
8626 12:29:54.458443
8627 12:29:54.458526 Set Vref, RX VrefLevel [Byte0]: 58
8628 12:29:54.461446 [Byte1]: 58
8629 12:29:54.465857
8630 12:29:54.465941 Set Vref, RX VrefLevel [Byte0]: 59
8631 12:29:54.469163 [Byte1]: 59
8632 12:29:54.473670
8633 12:29:54.473753 Set Vref, RX VrefLevel [Byte0]: 60
8634 12:29:54.476796 [Byte1]: 60
8635 12:29:54.480712
8636 12:29:54.480817 Set Vref, RX VrefLevel [Byte0]: 61
8637 12:29:54.483967 [Byte1]: 61
8638 12:29:54.488613
8639 12:29:54.488697 Set Vref, RX VrefLevel [Byte0]: 62
8640 12:29:54.491978 [Byte1]: 62
8641 12:29:54.496251
8642 12:29:54.496335 Set Vref, RX VrefLevel [Byte0]: 63
8643 12:29:54.499494 [Byte1]: 63
8644 12:29:54.503491
8645 12:29:54.503574 Set Vref, RX VrefLevel [Byte0]: 64
8646 12:29:54.506784 [Byte1]: 64
8647 12:29:54.511513
8648 12:29:54.511595 Set Vref, RX VrefLevel [Byte0]: 65
8649 12:29:54.514119 [Byte1]: 65
8650 12:29:54.518713
8651 12:29:54.518798 Set Vref, RX VrefLevel [Byte0]: 66
8652 12:29:54.521979 [Byte1]: 66
8653 12:29:54.526106
8654 12:29:54.526189 Set Vref, RX VrefLevel [Byte0]: 67
8655 12:29:54.532691 [Byte1]: 67
8656 12:29:54.532775
8657 12:29:54.536077 Set Vref, RX VrefLevel [Byte0]: 68
8658 12:29:54.539544 [Byte1]: 68
8659 12:29:54.539628
8660 12:29:54.542949 Set Vref, RX VrefLevel [Byte0]: 69
8661 12:29:54.546076 [Byte1]: 69
8662 12:29:54.546181
8663 12:29:54.549229 Set Vref, RX VrefLevel [Byte0]: 70
8664 12:29:54.552396 [Byte1]: 70
8665 12:29:54.556085
8666 12:29:54.556192 Set Vref, RX VrefLevel [Byte0]: 71
8667 12:29:54.559720 [Byte1]: 71
8668 12:29:54.564021
8669 12:29:54.564130 Set Vref, RX VrefLevel [Byte0]: 72
8670 12:29:54.567063 [Byte1]: 72
8671 12:29:54.571301
8672 12:29:54.571450 Set Vref, RX VrefLevel [Byte0]: 73
8673 12:29:54.574546 [Byte1]: 73
8674 12:29:54.579164
8675 12:29:54.579267 Set Vref, RX VrefLevel [Byte0]: 74
8676 12:29:54.581841 [Byte1]: 74
8677 12:29:54.586242
8678 12:29:54.586343 Set Vref, RX VrefLevel [Byte0]: 75
8679 12:29:54.589504 [Byte1]: 75
8680 12:29:54.594187
8681 12:29:54.594287 Set Vref, RX VrefLevel [Byte0]: 76
8682 12:29:54.596931 [Byte1]: 76
8683 12:29:54.601277
8684 12:29:54.601380 Final RX Vref Byte 0 = 56 to rank0
8685 12:29:54.604612 Final RX Vref Byte 1 = 56 to rank0
8686 12:29:54.607946 Final RX Vref Byte 0 = 56 to rank1
8687 12:29:54.611210 Final RX Vref Byte 1 = 56 to rank1==
8688 12:29:54.614343 Dram Type= 6, Freq= 0, CH_1, rank 0
8689 12:29:54.621268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8690 12:29:54.621354 ==
8691 12:29:54.621421 DQS Delay:
8692 12:29:54.621487 DQS0 = 0, DQS1 = 0
8693 12:29:54.624533 DQM Delay:
8694 12:29:54.624611 DQM0 = 134, DQM1 = 131
8695 12:29:54.627936 DQ Delay:
8696 12:29:54.631232 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8697 12:29:54.634573 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8698 12:29:54.637971 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8699 12:29:54.641196 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8700 12:29:54.641299
8701 12:29:54.641396
8702 12:29:54.641485
8703 12:29:54.644604 [DramC_TX_OE_Calibration] TA2
8704 12:29:54.648110 Original DQ_B0 (3 6) =30, OEN = 27
8705 12:29:54.651365 Original DQ_B1 (3 6) =30, OEN = 27
8706 12:29:54.654489 24, 0x0, End_B0=24 End_B1=24
8707 12:29:54.654565 25, 0x0, End_B0=25 End_B1=25
8708 12:29:54.658132 26, 0x0, End_B0=26 End_B1=26
8709 12:29:54.661291 27, 0x0, End_B0=27 End_B1=27
8710 12:29:54.664373 28, 0x0, End_B0=28 End_B1=28
8711 12:29:54.668069 29, 0x0, End_B0=29 End_B1=29
8712 12:29:54.668177 30, 0x0, End_B0=30 End_B1=30
8713 12:29:54.671213 31, 0x4141, End_B0=30 End_B1=30
8714 12:29:54.674413 Byte0 end_step=30 best_step=27
8715 12:29:54.677573 Byte1 end_step=30 best_step=27
8716 12:29:54.681326 Byte0 TX OE(2T, 0.5T) = (3, 3)
8717 12:29:54.681430 Byte1 TX OE(2T, 0.5T) = (3, 3)
8718 12:29:54.684396
8719 12:29:54.684504
8720 12:29:54.690972 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8721 12:29:54.694798 CH1 RK0: MR19=303, MR18=1623
8722 12:29:54.701448 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8723 12:29:54.701555
8724 12:29:54.704711 ----->DramcWriteLeveling(PI) begin...
8725 12:29:54.704797 ==
8726 12:29:54.707746 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 12:29:54.711038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 12:29:54.711143 ==
8729 12:29:54.714337 Write leveling (Byte 0): 26 => 26
8730 12:29:54.717676 Write leveling (Byte 1): 28 => 28
8731 12:29:54.721098 DramcWriteLeveling(PI) end<-----
8732 12:29:54.721202
8733 12:29:54.721303 ==
8734 12:29:54.724439 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 12:29:54.727682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 12:29:54.727758 ==
8737 12:29:54.730993 [Gating] SW mode calibration
8738 12:29:54.737775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8739 12:29:54.744608 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8740 12:29:54.747970 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 12:29:54.751241 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 12:29:54.757946 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8743 12:29:54.761231 1 4 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
8744 12:29:54.764405 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 12:29:54.771087 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 12:29:54.774085 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 12:29:54.777765 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 12:29:54.784491 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 12:29:54.787602 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8750 12:29:54.790631 1 5 8 | B1->B0 | 2929 3434 | 0 0 | (1 0) (0 0)
8751 12:29:54.797736 1 5 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 0)
8752 12:29:54.800909 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 12:29:54.804152 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 12:29:54.811050 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 12:29:54.814214 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 12:29:54.817511 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 12:29:54.824096 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 12:29:54.827518 1 6 8 | B1->B0 | 4646 2626 | 0 0 | (0 0) (0 0)
8759 12:29:54.830955 1 6 12 | B1->B0 | 4646 3d3c | 0 1 | (0 0) (0 0)
8760 12:29:54.834172 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 12:29:54.840776 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 12:29:54.844176 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 12:29:54.847598 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 12:29:54.854275 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 12:29:54.857619 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 12:29:54.860842 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8767 12:29:54.867635 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8768 12:29:54.870743 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:29:54.874423 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:29:54.880555 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:29:54.884230 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 12:29:54.887387 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 12:29:54.894062 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 12:29:54.897170 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 12:29:54.901034 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:29:54.907382 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:29:54.910461 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:29:54.913800 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:29:54.920812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:29:54.923785 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:29:54.927584 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 12:29:54.934105 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8783 12:29:54.937391 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8784 12:29:54.940735 Total UI for P1: 0, mck2ui 16
8785 12:29:54.943970 best dqsien dly found for B1: ( 1, 9, 6)
8786 12:29:54.947284 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 12:29:54.950618 Total UI for P1: 0, mck2ui 16
8788 12:29:54.954040 best dqsien dly found for B0: ( 1, 9, 12)
8789 12:29:54.957230 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8790 12:29:54.960528 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8791 12:29:54.960612
8792 12:29:54.963817 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8793 12:29:54.970579 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8794 12:29:54.970664 [Gating] SW calibration Done
8795 12:29:54.970732 ==
8796 12:29:54.973957 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 12:29:54.980344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 12:29:54.980463 ==
8799 12:29:54.980560 RX Vref Scan: 0
8800 12:29:54.980653
8801 12:29:54.983485 RX Vref 0 -> 0, step: 1
8802 12:29:54.983567
8803 12:29:54.987146 RX Delay 0 -> 252, step: 8
8804 12:29:54.990271 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8805 12:29:54.993778 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8806 12:29:54.996741 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8807 12:29:55.003425 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8808 12:29:55.006697 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8809 12:29:55.010212 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8810 12:29:55.013288 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8811 12:29:55.016482 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8812 12:29:55.023438 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8813 12:29:55.026619 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8814 12:29:55.029748 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8815 12:29:55.033323 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8816 12:29:55.036499 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8817 12:29:55.043222 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8818 12:29:55.046517 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8819 12:29:55.049957 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8820 12:29:55.050033 ==
8821 12:29:55.053344 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 12:29:55.056755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 12:29:55.056829 ==
8824 12:29:55.060195 DQS Delay:
8825 12:29:55.060267 DQS0 = 0, DQS1 = 0
8826 12:29:55.063524 DQM Delay:
8827 12:29:55.063598 DQM0 = 136, DQM1 = 133
8828 12:29:55.066951 DQ Delay:
8829 12:29:55.069569 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8830 12:29:55.073047 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8831 12:29:55.076418 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8832 12:29:55.079745 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8833 12:29:55.079819
8834 12:29:55.079883
8835 12:29:55.079942 ==
8836 12:29:55.083058 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 12:29:55.086391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 12:29:55.086466 ==
8839 12:29:55.086527
8840 12:29:55.086585
8841 12:29:55.089626 TX Vref Scan disable
8842 12:29:55.092789 == TX Byte 0 ==
8843 12:29:55.096483 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8844 12:29:55.099768 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8845 12:29:55.102915 == TX Byte 1 ==
8846 12:29:55.106620 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8847 12:29:55.109563 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8848 12:29:55.109631 ==
8849 12:29:55.113293 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 12:29:55.119590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 12:29:55.119674 ==
8852 12:29:55.131798
8853 12:29:55.135100 TX Vref early break, caculate TX vref
8854 12:29:55.138315 TX Vref=16, minBit 0, minWin=22, winSum=381
8855 12:29:55.141989 TX Vref=18, minBit 0, minWin=23, winSum=389
8856 12:29:55.145182 TX Vref=20, minBit 0, minWin=24, winSum=403
8857 12:29:55.148281 TX Vref=22, minBit 2, minWin=23, winSum=409
8858 12:29:55.151670 TX Vref=24, minBit 0, minWin=25, winSum=417
8859 12:29:55.158382 TX Vref=26, minBit 1, minWin=25, winSum=425
8860 12:29:55.161679 TX Vref=28, minBit 0, minWin=25, winSum=425
8861 12:29:55.165094 TX Vref=30, minBit 0, minWin=25, winSum=420
8862 12:29:55.168436 TX Vref=32, minBit 6, minWin=24, winSum=413
8863 12:29:55.171724 TX Vref=34, minBit 1, minWin=24, winSum=406
8864 12:29:55.175147 TX Vref=36, minBit 1, minWin=23, winSum=399
8865 12:29:55.181228 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8866 12:29:55.181299
8867 12:29:55.184518 Final TX Range 0 Vref 26
8868 12:29:55.184589
8869 12:29:55.184647 ==
8870 12:29:55.188435 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 12:29:55.191738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 12:29:55.191810 ==
8873 12:29:55.191874
8874 12:29:55.194444
8875 12:29:55.194508 TX Vref Scan disable
8876 12:29:55.201536 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8877 12:29:55.201611 == TX Byte 0 ==
8878 12:29:55.204589 u2DelayCellOfst[0]=16 cells (5 PI)
8879 12:29:55.207677 u2DelayCellOfst[1]=13 cells (4 PI)
8880 12:29:55.211429 u2DelayCellOfst[2]=0 cells (0 PI)
8881 12:29:55.214403 u2DelayCellOfst[3]=6 cells (2 PI)
8882 12:29:55.218100 u2DelayCellOfst[4]=10 cells (3 PI)
8883 12:29:55.221130 u2DelayCellOfst[5]=16 cells (5 PI)
8884 12:29:55.224871 u2DelayCellOfst[6]=16 cells (5 PI)
8885 12:29:55.227923 u2DelayCellOfst[7]=6 cells (2 PI)
8886 12:29:55.231166 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8887 12:29:55.234246 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8888 12:29:55.238015 == TX Byte 1 ==
8889 12:29:55.240936 u2DelayCellOfst[8]=0 cells (0 PI)
8890 12:29:55.244672 u2DelayCellOfst[9]=0 cells (0 PI)
8891 12:29:55.244746 u2DelayCellOfst[10]=10 cells (3 PI)
8892 12:29:55.247887 u2DelayCellOfst[11]=6 cells (2 PI)
8893 12:29:55.251035 u2DelayCellOfst[12]=13 cells (4 PI)
8894 12:29:55.254712 u2DelayCellOfst[13]=13 cells (4 PI)
8895 12:29:55.258085 u2DelayCellOfst[14]=13 cells (4 PI)
8896 12:29:55.261437 u2DelayCellOfst[15]=13 cells (4 PI)
8897 12:29:55.264825 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8898 12:29:55.271032 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8899 12:29:55.271113 DramC Write-DBI on
8900 12:29:55.271182 ==
8901 12:29:55.274322 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 12:29:55.281032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 12:29:55.281109 ==
8904 12:29:55.281174
8905 12:29:55.281234
8906 12:29:55.281290 TX Vref Scan disable
8907 12:29:55.285052 == TX Byte 0 ==
8908 12:29:55.288396 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8909 12:29:55.291766 == TX Byte 1 ==
8910 12:29:55.295133 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8911 12:29:55.298423 DramC Write-DBI off
8912 12:29:55.298501
8913 12:29:55.298565 [DATLAT]
8914 12:29:55.298623 Freq=1600, CH1 RK1
8915 12:29:55.298681
8916 12:29:55.301803 DATLAT Default: 0xf
8917 12:29:55.301877 0, 0xFFFF, sum = 0
8918 12:29:55.305120 1, 0xFFFF, sum = 0
8919 12:29:55.308298 2, 0xFFFF, sum = 0
8920 12:29:55.308374 3, 0xFFFF, sum = 0
8921 12:29:55.311636 4, 0xFFFF, sum = 0
8922 12:29:55.311709 5, 0xFFFF, sum = 0
8923 12:29:55.314620 6, 0xFFFF, sum = 0
8924 12:29:55.314696 7, 0xFFFF, sum = 0
8925 12:29:55.317884 8, 0xFFFF, sum = 0
8926 12:29:55.317960 9, 0xFFFF, sum = 0
8927 12:29:55.321704 10, 0xFFFF, sum = 0
8928 12:29:55.321779 11, 0xFFFF, sum = 0
8929 12:29:55.324920 12, 0xFFFF, sum = 0
8930 12:29:55.324991 13, 0xFFFF, sum = 0
8931 12:29:55.327978 14, 0x0, sum = 1
8932 12:29:55.328050 15, 0x0, sum = 2
8933 12:29:55.331609 16, 0x0, sum = 3
8934 12:29:55.331681 17, 0x0, sum = 4
8935 12:29:55.334764 best_step = 15
8936 12:29:55.334839
8937 12:29:55.334901 ==
8938 12:29:55.337967 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 12:29:55.341141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 12:29:55.341219 ==
8941 12:29:55.344431 RX Vref Scan: 0
8942 12:29:55.344506
8943 12:29:55.344567 RX Vref 0 -> 0, step: 1
8944 12:29:55.344625
8945 12:29:55.348240 RX Delay 19 -> 252, step: 4
8946 12:29:55.351320 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8947 12:29:55.357896 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8948 12:29:55.360995 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8949 12:29:55.364176 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8950 12:29:55.367493 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8951 12:29:55.370863 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8952 12:29:55.377662 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8953 12:29:55.381136 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8954 12:29:55.384502 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8955 12:29:55.387814 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8956 12:29:55.391220 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8957 12:29:55.397832 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8958 12:29:55.401185 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8959 12:29:55.404484 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8960 12:29:55.407738 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8961 12:29:55.410903 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8962 12:29:55.414373 ==
8963 12:29:55.417149 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 12:29:55.420838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 12:29:55.420919 ==
8966 12:29:55.420983 DQS Delay:
8967 12:29:55.424075 DQS0 = 0, DQS1 = 0
8968 12:29:55.424148 DQM Delay:
8969 12:29:55.427274 DQM0 = 134, DQM1 = 130
8970 12:29:55.427413 DQ Delay:
8971 12:29:55.430525 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8972 12:29:55.434224 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8973 12:29:55.437247 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8974 12:29:55.440430 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8975 12:29:55.440506
8976 12:29:55.440569
8977 12:29:55.440627
8978 12:29:55.444365 [DramC_TX_OE_Calibration] TA2
8979 12:29:55.447464 Original DQ_B0 (3 6) =30, OEN = 27
8980 12:29:55.450618 Original DQ_B1 (3 6) =30, OEN = 27
8981 12:29:55.453949 24, 0x0, End_B0=24 End_B1=24
8982 12:29:55.457132 25, 0x0, End_B0=25 End_B1=25
8983 12:29:55.457239 26, 0x0, End_B0=26 End_B1=26
8984 12:29:55.460744 27, 0x0, End_B0=27 End_B1=27
8985 12:29:55.464156 28, 0x0, End_B0=28 End_B1=28
8986 12:29:55.467414 29, 0x0, End_B0=29 End_B1=29
8987 12:29:55.467495 30, 0x0, End_B0=30 End_B1=30
8988 12:29:55.470650 31, 0x4141, End_B0=30 End_B1=30
8989 12:29:55.473891 Byte0 end_step=30 best_step=27
8990 12:29:55.477308 Byte1 end_step=30 best_step=27
8991 12:29:55.480736 Byte0 TX OE(2T, 0.5T) = (3, 3)
8992 12:29:55.484131 Byte1 TX OE(2T, 0.5T) = (3, 3)
8993 12:29:55.484207
8994 12:29:55.484270
8995 12:29:55.490671 [DQSOSCAuto] RK1, (LSB)MR18= 0x2006, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8996 12:29:55.494013 CH1 RK1: MR19=303, MR18=2006
8997 12:29:55.500770 CH1_RK1: MR19=0x303, MR18=0x2006, DQSOSC=393, MR23=63, INC=23, DEC=15
8998 12:29:55.504227 [RxdqsGatingPostProcess] freq 1600
8999 12:29:55.507455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9000 12:29:55.510964 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 12:29:55.514217 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 12:29:55.517548 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 12:29:55.520821 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 12:29:55.524120 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 12:29:55.527225 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 12:29:55.530371 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 12:29:55.534177 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 12:29:55.537229 Pre-setting of DQS Precalculation
9009 12:29:55.540888 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9010 12:29:55.547382 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9011 12:29:55.556995 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9012 12:29:55.557075
9013 12:29:55.557140
9014 12:29:55.560359 [Calibration Summary] 3200 Mbps
9015 12:29:55.560432 CH 0, Rank 0
9016 12:29:55.563516 SW Impedance : PASS
9017 12:29:55.563587 DUTY Scan : NO K
9018 12:29:55.567234 ZQ Calibration : PASS
9019 12:29:55.567317 Jitter Meter : NO K
9020 12:29:55.570256 CBT Training : PASS
9021 12:29:55.574134 Write leveling : PASS
9022 12:29:55.574212 RX DQS gating : PASS
9023 12:29:55.577344 RX DQ/DQS(RDDQC) : PASS
9024 12:29:55.580503 TX DQ/DQS : PASS
9025 12:29:55.580581 RX DATLAT : PASS
9026 12:29:55.583976 RX DQ/DQS(Engine): PASS
9027 12:29:55.587281 TX OE : PASS
9028 12:29:55.587372 All Pass.
9029 12:29:55.587449
9030 12:29:55.587510 CH 0, Rank 1
9031 12:29:55.590648 SW Impedance : PASS
9032 12:29:55.593903 DUTY Scan : NO K
9033 12:29:55.593976 ZQ Calibration : PASS
9034 12:29:55.597255 Jitter Meter : NO K
9035 12:29:55.600559 CBT Training : PASS
9036 12:29:55.600632 Write leveling : PASS
9037 12:29:55.603352 RX DQS gating : PASS
9038 12:29:55.606661 RX DQ/DQS(RDDQC) : PASS
9039 12:29:55.606732 TX DQ/DQS : PASS
9040 12:29:55.610093 RX DATLAT : PASS
9041 12:29:55.613360 RX DQ/DQS(Engine): PASS
9042 12:29:55.613437 TX OE : PASS
9043 12:29:55.613500 All Pass.
9044 12:29:55.616742
9045 12:29:55.616812 CH 1, Rank 0
9046 12:29:55.620144 SW Impedance : PASS
9047 12:29:55.620222 DUTY Scan : NO K
9048 12:29:55.623311 ZQ Calibration : PASS
9049 12:29:55.623421 Jitter Meter : NO K
9050 12:29:55.626645 CBT Training : PASS
9051 12:29:55.629967 Write leveling : PASS
9052 12:29:55.630038 RX DQS gating : PASS
9053 12:29:55.633223 RX DQ/DQS(RDDQC) : PASS
9054 12:29:55.637069 TX DQ/DQS : PASS
9055 12:29:55.637144 RX DATLAT : PASS
9056 12:29:55.640354 RX DQ/DQS(Engine): PASS
9057 12:29:55.643551 TX OE : PASS
9058 12:29:55.643626 All Pass.
9059 12:29:55.643688
9060 12:29:55.643749 CH 1, Rank 1
9061 12:29:55.646664 SW Impedance : PASS
9062 12:29:55.649866 DUTY Scan : NO K
9063 12:29:55.649936 ZQ Calibration : PASS
9064 12:29:55.653042 Jitter Meter : NO K
9065 12:29:55.656636 CBT Training : PASS
9066 12:29:55.656753 Write leveling : PASS
9067 12:29:55.659912 RX DQS gating : PASS
9068 12:29:55.663236 RX DQ/DQS(RDDQC) : PASS
9069 12:29:55.663373 TX DQ/DQS : PASS
9070 12:29:55.666560 RX DATLAT : PASS
9071 12:29:55.669799 RX DQ/DQS(Engine): PASS
9072 12:29:55.669882 TX OE : PASS
9073 12:29:55.669985 All Pass.
9074 12:29:55.673126
9075 12:29:55.673208 DramC Write-DBI on
9076 12:29:55.676218 PER_BANK_REFRESH: Hybrid Mode
9077 12:29:55.676291 TX_TRACKING: ON
9078 12:29:55.686399 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9079 12:29:55.692998 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9080 12:29:55.702994 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 12:29:55.706341 [FAST_K] Save calibration result to emmc
9082 12:29:55.709751 sync common calibartion params.
9083 12:29:55.709833 sync cbt_mode0:1, 1:1
9084 12:29:55.713092 dram_init: ddr_geometry: 2
9085 12:29:55.716494 dram_init: ddr_geometry: 2
9086 12:29:55.716576 dram_init: ddr_geometry: 2
9087 12:29:55.719784 0:dram_rank_size:100000000
9088 12:29:55.722959 1:dram_rank_size:100000000
9089 12:29:55.726195 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9090 12:29:55.729495 DFS_SHUFFLE_HW_MODE: ON
9091 12:29:55.732790 dramc_set_vcore_voltage set vcore to 725000
9092 12:29:55.736258 Read voltage for 1600, 0
9093 12:29:55.736340 Vio18 = 0
9094 12:29:55.739534 Vcore = 725000
9095 12:29:55.739616 Vdram = 0
9096 12:29:55.739681 Vddq = 0
9097 12:29:55.739740 Vmddr = 0
9098 12:29:55.742645 switch to 3200 Mbps bootup
9099 12:29:55.746426 [DramcRunTimeConfig]
9100 12:29:55.746507 PHYPLL
9101 12:29:55.749598 DPM_CONTROL_AFTERK: ON
9102 12:29:55.749689 PER_BANK_REFRESH: ON
9103 12:29:55.752747 REFRESH_OVERHEAD_REDUCTION: ON
9104 12:29:55.755969 CMD_PICG_NEW_MODE: OFF
9105 12:29:55.756052 XRTWTW_NEW_MODE: ON
9106 12:29:55.759197 XRTRTR_NEW_MODE: ON
9107 12:29:55.759295 TX_TRACKING: ON
9108 12:29:55.763033 RDSEL_TRACKING: OFF
9109 12:29:55.766177 DQS Precalculation for DVFS: ON
9110 12:29:55.766267 RX_TRACKING: OFF
9111 12:29:55.769381 HW_GATING DBG: ON
9112 12:29:55.769464 ZQCS_ENABLE_LP4: ON
9113 12:29:55.772664 RX_PICG_NEW_MODE: ON
9114 12:29:55.772746 TX_PICG_NEW_MODE: ON
9115 12:29:55.775999 ENABLE_RX_DCM_DPHY: ON
9116 12:29:55.779344 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9117 12:29:55.782727 DUMMY_READ_FOR_TRACKING: OFF
9118 12:29:55.782851 !!! SPM_CONTROL_AFTERK: OFF
9119 12:29:55.785824 !!! SPM could not control APHY
9120 12:29:55.789521 IMPEDANCE_TRACKING: ON
9121 12:29:55.789604 TEMP_SENSOR: ON
9122 12:29:55.792800 HW_SAVE_FOR_SR: OFF
9123 12:29:55.795982 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9124 12:29:55.799145 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9125 12:29:55.799228 Read ODT Tracking: ON
9126 12:29:55.802371 Refresh Rate DeBounce: ON
9127 12:29:55.806378 DFS_NO_QUEUE_FLUSH: ON
9128 12:29:55.809056 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9129 12:29:55.809139 ENABLE_DFS_RUNTIME_MRW: OFF
9130 12:29:55.812484 DDR_RESERVE_NEW_MODE: ON
9131 12:29:55.815850 MR_CBT_SWITCH_FREQ: ON
9132 12:29:55.815932 =========================
9133 12:29:55.835955 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9134 12:29:55.839301 dram_init: ddr_geometry: 2
9135 12:29:55.857285 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9136 12:29:55.860912 dram_init: dram init end (result: 0)
9137 12:29:55.867322 DRAM-K: Full calibration passed in 24453 msecs
9138 12:29:55.871085 MRC: failed to locate region type 0.
9139 12:29:55.871169 DRAM rank0 size:0x100000000,
9140 12:29:55.874299 DRAM rank1 size=0x100000000
9141 12:29:55.884074 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9142 12:29:55.890748 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9143 12:29:55.897176 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9144 12:29:55.904387 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9145 12:29:55.907500 DRAM rank0 size:0x100000000,
9146 12:29:55.910832 DRAM rank1 size=0x100000000
9147 12:29:55.910916 CBMEM:
9148 12:29:55.914318 IMD: root @ 0xfffff000 254 entries.
9149 12:29:55.920174 IMD: root @ 0xffffec00 62 entries.
9150 12:29:55.920468 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9151 12:29:55.923990 WARNING: RO_VPD is uninitialized or empty.
9152 12:29:55.930749 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9153 12:29:55.937911 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9154 12:29:55.950510 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9155 12:29:55.961933 BS: romstage times (exec / console): total (unknown) / 23987 ms
9156 12:29:55.962060
9157 12:29:55.962171
9158 12:29:55.971788 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9159 12:29:55.974952 ARM64: Exception handlers installed.
9160 12:29:55.978448 ARM64: Testing exception
9161 12:29:55.982073 ARM64: Done test exception
9162 12:29:55.982178 Enumerating buses...
9163 12:29:55.985203 Show all devs... Before device enumeration.
9164 12:29:55.988261 Root Device: enabled 1
9165 12:29:55.992130 CPU_CLUSTER: 0: enabled 1
9166 12:29:55.992240 CPU: 00: enabled 1
9167 12:29:55.995191 Compare with tree...
9168 12:29:55.995293 Root Device: enabled 1
9169 12:29:55.998566 CPU_CLUSTER: 0: enabled 1
9170 12:29:56.001899 CPU: 00: enabled 1
9171 12:29:56.002008 Root Device scanning...
9172 12:29:56.004948 scan_static_bus for Root Device
9173 12:29:56.008296 CPU_CLUSTER: 0 enabled
9174 12:29:56.011614 scan_static_bus for Root Device done
9175 12:29:56.015195 scan_bus: bus Root Device finished in 8 msecs
9176 12:29:56.015297 done
9177 12:29:56.021181 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9178 12:29:56.024645 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9179 12:29:56.031858 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9180 12:29:56.034571 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9181 12:29:56.038457 Allocating resources...
9182 12:29:56.041621 Reading resources...
9183 12:29:56.045041 Root Device read_resources bus 0 link: 0
9184 12:29:56.045143 DRAM rank0 size:0x100000000,
9185 12:29:56.048213 DRAM rank1 size=0x100000000
9186 12:29:56.051595 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9187 12:29:56.054982 CPU: 00 missing read_resources
9188 12:29:56.058253 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9189 12:29:56.064811 Root Device read_resources bus 0 link: 0 done
9190 12:29:56.064952 Done reading resources.
9191 12:29:56.071664 Show resources in subtree (Root Device)...After reading.
9192 12:29:56.074746 Root Device child on link 0 CPU_CLUSTER: 0
9193 12:29:56.078319 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 12:29:56.088205 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 12:29:56.088321 CPU: 00
9196 12:29:56.091318 Root Device assign_resources, bus 0 link: 0
9197 12:29:56.094970 CPU_CLUSTER: 0 missing set_resources
9198 12:29:56.098007 Root Device assign_resources, bus 0 link: 0 done
9199 12:29:56.101296 Done setting resources.
9200 12:29:56.107936 Show resources in subtree (Root Device)...After assigning values.
9201 12:29:56.111645 Root Device child on link 0 CPU_CLUSTER: 0
9202 12:29:56.114811 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 12:29:56.124591 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 12:29:56.124711 CPU: 00
9205 12:29:56.127986 Done allocating resources.
9206 12:29:56.131273 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9207 12:29:56.134723 Enabling resources...
9208 12:29:56.134826 done.
9209 12:29:56.141184 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9210 12:29:56.141298 Initializing devices...
9211 12:29:56.144966 Root Device init
9212 12:29:56.145051 init hardware done!
9213 12:29:56.147670 0x00000018: ctrlr->caps
9214 12:29:56.151041 52.000 MHz: ctrlr->f_max
9215 12:29:56.151127 0.400 MHz: ctrlr->f_min
9216 12:29:56.154399 0x40ff8080: ctrlr->voltages
9217 12:29:56.154484 sclk: 390625
9218 12:29:56.157616 Bus Width = 1
9219 12:29:56.157700 sclk: 390625
9220 12:29:56.157767 Bus Width = 1
9221 12:29:56.161601 Early init status = 3
9222 12:29:56.168140 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9223 12:29:56.171341 in-header: 03 fc 00 00 01 00 00 00
9224 12:29:56.171435 in-data: 00
9225 12:29:56.177714 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9226 12:29:56.181476 in-header: 03 fd 00 00 00 00 00 00
9227 12:29:56.181588 in-data:
9228 12:29:56.188112 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9229 12:29:56.191122 in-header: 03 fc 00 00 01 00 00 00
9230 12:29:56.194364 in-data: 00
9231 12:29:56.198067 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9232 12:29:56.201749 in-header: 03 fd 00 00 00 00 00 00
9233 12:29:56.204769 in-data:
9234 12:29:56.207986 [SSUSB] Setting up USB HOST controller...
9235 12:29:56.211685 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9236 12:29:56.214970 [SSUSB] phy power-on done.
9237 12:29:56.218136 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9238 12:29:56.225149 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9239 12:29:56.228385 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9240 12:29:56.234920 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9241 12:29:56.241571 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9242 12:29:56.247969 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9243 12:29:56.254716 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9244 12:29:56.261380 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9245 12:29:56.264817 SPM: binary array size = 0x9dc
9246 12:29:56.268177 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9247 12:29:56.274751 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9248 12:29:56.281335 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9249 12:29:56.285055 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9250 12:29:56.288110 configure_display: Starting display init
9251 12:29:56.324805 anx7625_power_on_init: Init interface.
9252 12:29:56.328001 anx7625_disable_pd_protocol: Disabled PD feature.
9253 12:29:56.331183 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9254 12:29:56.359142 anx7625_start_dp_work: Secure OCM version=00
9255 12:29:56.362871 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9256 12:29:56.377144 sp_tx_get_edid_block: EDID Block = 1
9257 12:29:56.480277 Extracted contents:
9258 12:29:56.483366 header: 00 ff ff ff ff ff ff 00
9259 12:29:56.486626 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9260 12:29:56.489939 version: 01 04
9261 12:29:56.493296 basic params: 95 1f 11 78 0a
9262 12:29:56.496408 chroma info: 76 90 94 55 54 90 27 21 50 54
9263 12:29:56.500024 established: 00 00 00
9264 12:29:56.506694 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9265 12:29:56.509800 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9266 12:29:56.516675 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9267 12:29:56.522998 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9268 12:29:56.529590 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9269 12:29:56.532780 extensions: 00
9270 12:29:56.532865 checksum: fb
9271 12:29:56.532931
9272 12:29:56.536671 Manufacturer: IVO Model 57d Serial Number 0
9273 12:29:56.539832 Made week 0 of 2020
9274 12:29:56.539957 EDID version: 1.4
9275 12:29:56.542861 Digital display
9276 12:29:56.546016 6 bits per primary color channel
9277 12:29:56.546104 DisplayPort interface
9278 12:29:56.549839 Maximum image size: 31 cm x 17 cm
9279 12:29:56.553344 Gamma: 220%
9280 12:29:56.553429 Check DPMS levels
9281 12:29:56.556052 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9282 12:29:56.560057 First detailed timing is preferred timing
9283 12:29:56.563233 Established timings supported:
9284 12:29:56.566045 Standard timings supported:
9285 12:29:56.569239 Detailed timings
9286 12:29:56.572676 Hex of detail: 383680a07038204018303c0035ae10000019
9287 12:29:56.576037 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9288 12:29:56.582682 0780 0798 07c8 0820 hborder 0
9289 12:29:56.585933 0438 043b 0447 0458 vborder 0
9290 12:29:56.589101 -hsync -vsync
9291 12:29:56.589187 Did detailed timing
9292 12:29:56.595704 Hex of detail: 000000000000000000000000000000000000
9293 12:29:56.595792 Manufacturer-specified data, tag 0
9294 12:29:56.602882 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9295 12:29:56.606022 ASCII string: InfoVision
9296 12:29:56.609283 Hex of detail: 000000fe00523134304e574635205248200a
9297 12:29:56.613076 ASCII string: R140NWF5 RH
9298 12:29:56.613161 Checksum
9299 12:29:56.613228 Checksum: 0xfb (valid)
9300 12:29:56.619278 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9301 12:29:56.623051 DSI data_rate: 832800000 bps
9302 12:29:56.626245 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9303 12:29:56.632532 anx7625_parse_edid: pixelclock(138800).
9304 12:29:56.636142 hactive(1920), hsync(48), hfp(24), hbp(88)
9305 12:29:56.639458 vactive(1080), vsync(12), vfp(3), vbp(17)
9306 12:29:56.642563 anx7625_dsi_config: config dsi.
9307 12:29:56.649432 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9308 12:29:56.662216 anx7625_dsi_config: success to config DSI
9309 12:29:56.665433 anx7625_dp_start: MIPI phy setup OK.
9310 12:29:56.668854 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9311 12:29:56.672206 mtk_ddp_mode_set invalid vrefresh 60
9312 12:29:56.675591 main_disp_path_setup
9313 12:29:56.675683 ovl_layer_smi_id_en
9314 12:29:56.678955 ovl_layer_smi_id_en
9315 12:29:56.679030 ccorr_config
9316 12:29:56.679093 aal_config
9317 12:29:56.681681 gamma_config
9318 12:29:56.681768 postmask_config
9319 12:29:56.685006 dither_config
9320 12:29:56.688332 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9321 12:29:56.694890 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9322 12:29:56.698948 Root Device init finished in 551 msecs
9323 12:29:56.702116 CPU_CLUSTER: 0 init
9324 12:29:56.708348 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9325 12:29:56.712387 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9326 12:29:56.714914 APU_MBOX 0x190000b0 = 0x10001
9327 12:29:56.718730 APU_MBOX 0x190001b0 = 0x10001
9328 12:29:56.721794 APU_MBOX 0x190005b0 = 0x10001
9329 12:29:56.725146 APU_MBOX 0x190006b0 = 0x10001
9330 12:29:56.728632 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9331 12:29:56.741097 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9332 12:29:56.753500 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9333 12:29:56.759822 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9334 12:29:56.771562 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9335 12:29:56.780697 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9336 12:29:56.784032 CPU_CLUSTER: 0 init finished in 81 msecs
9337 12:29:56.787434 Devices initialized
9338 12:29:56.790604 Show all devs... After init.
9339 12:29:56.790704 Root Device: enabled 1
9340 12:29:56.793895 CPU_CLUSTER: 0: enabled 1
9341 12:29:56.797226 CPU: 00: enabled 1
9342 12:29:56.800438 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9343 12:29:56.803868 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9344 12:29:56.807244 ELOG: NV offset 0x57f000 size 0x1000
9345 12:29:56.813841 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9346 12:29:56.820680 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9347 12:29:56.823857 ELOG: Event(17) added with size 13 at 2023-06-06 12:29:45 UTC
9348 12:29:56.827603 out: cmd=0x121: 03 db 21 01 00 00 00 00
9349 12:29:56.831395 in-header: 03 df 00 00 2c 00 00 00
9350 12:29:56.844303 in-data: 80 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 12:29:56.851179 ELOG: Event(A1) added with size 10 at 2023-06-06 12:29:45 UTC
9352 12:29:56.857841 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9353 12:29:56.864102 ELOG: Event(A0) added with size 9 at 2023-06-06 12:29:45 UTC
9354 12:29:56.867865 elog_add_boot_reason: Logged dev mode boot
9355 12:29:56.870964 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9356 12:29:56.874123 Finalize devices...
9357 12:29:56.874234 Devices finalized
9358 12:29:56.881007 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9359 12:29:56.884314 Writing coreboot table at 0xffe64000
9360 12:29:56.887520 0. 000000000010a000-0000000000113fff: RAMSTAGE
9361 12:29:56.890921 1. 0000000040000000-00000000400fffff: RAM
9362 12:29:56.894231 2. 0000000040100000-000000004032afff: RAMSTAGE
9363 12:29:56.900794 3. 000000004032b000-00000000545fffff: RAM
9364 12:29:56.904198 4. 0000000054600000-000000005465ffff: BL31
9365 12:29:56.907540 5. 0000000054660000-00000000ffe63fff: RAM
9366 12:29:56.914136 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9367 12:29:56.917361 7. 0000000100000000-000000023fffffff: RAM
9368 12:29:56.917446 Passing 5 GPIOs to payload:
9369 12:29:56.924057 NAME | PORT | POLARITY | VALUE
9370 12:29:56.927406 EC in RW | 0x000000aa | low | undefined
9371 12:29:56.933810 EC interrupt | 0x00000005 | low | undefined
9372 12:29:56.936863 TPM interrupt | 0x000000ab | high | undefined
9373 12:29:56.940652 SD card detect | 0x00000011 | high | undefined
9374 12:29:56.946964 speaker enable | 0x00000093 | high | undefined
9375 12:29:56.950265 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9376 12:29:56.954045 in-header: 03 f9 00 00 02 00 00 00
9377 12:29:56.954130 in-data: 02 00
9378 12:29:56.957051 ADC[4]: Raw value=905096 ID=7
9379 12:29:56.960731 ADC[3]: Raw value=213441 ID=1
9380 12:29:56.960842 RAM Code: 0x71
9381 12:29:56.963767 ADC[6]: Raw value=75701 ID=0
9382 12:29:56.967006 ADC[5]: Raw value=212703 ID=1
9383 12:29:56.967125 SKU Code: 0x1
9384 12:29:56.973483 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9385 12:29:56.976691 coreboot table: 964 bytes.
9386 12:29:56.980519 IMD ROOT 0. 0xfffff000 0x00001000
9387 12:29:56.983505 IMD SMALL 1. 0xffffe000 0x00001000
9388 12:29:56.987137 RO MCACHE 2. 0xffffc000 0x00001104
9389 12:29:56.989873 CONSOLE 3. 0xfff7c000 0x00080000
9390 12:29:56.993201 FMAP 4. 0xfff7b000 0x00000452
9391 12:29:56.997149 TIME STAMP 5. 0xfff7a000 0x00000910
9392 12:29:56.999929 VBOOT WORK 6. 0xfff66000 0x00014000
9393 12:29:57.003170 RAMOOPS 7. 0xffe66000 0x00100000
9394 12:29:57.006392 COREBOOT 8. 0xffe64000 0x00002000
9395 12:29:57.006504 IMD small region:
9396 12:29:57.009718 IMD ROOT 0. 0xffffec00 0x00000400
9397 12:29:57.013109 VPD 1. 0xffffeba0 0x0000004c
9398 12:29:57.016462 MMC STATUS 2. 0xffffeb80 0x00000004
9399 12:29:57.023296 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9400 12:29:57.026504 Probing TPM: done!
9401 12:29:57.029751 Connected to device vid:did:rid of 1ae0:0028:00
9402 12:29:57.039613 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9403 12:29:57.043334 Initialized TPM device CR50 revision 0
9404 12:29:57.046604 Checking cr50 for pending updates
9405 12:29:57.050246 Reading cr50 TPM mode
9406 12:29:57.059065 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9407 12:29:57.065414 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9408 12:29:57.105737 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9409 12:29:57.109001 Checking segment from ROM address 0x40100000
9410 12:29:57.112385 Checking segment from ROM address 0x4010001c
9411 12:29:57.119042 Loading segment from ROM address 0x40100000
9412 12:29:57.119126 code (compression=0)
9413 12:29:57.129316 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9414 12:29:57.135953 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9415 12:29:57.136037 it's not compressed!
9416 12:29:57.142512 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9417 12:29:57.145750 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9418 12:29:57.165952 Loading segment from ROM address 0x4010001c
9419 12:29:57.166060 Entry Point 0x80000000
9420 12:29:57.169756 Loaded segments
9421 12:29:57.172803 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9422 12:29:57.179982 Jumping to boot code at 0x80000000(0xffe64000)
9423 12:29:57.186427 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9424 12:29:57.192858 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9425 12:29:57.200900 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9426 12:29:57.204224 Checking segment from ROM address 0x40100000
9427 12:29:57.207589 Checking segment from ROM address 0x4010001c
9428 12:29:57.214076 Loading segment from ROM address 0x40100000
9429 12:29:57.214163 code (compression=1)
9430 12:29:57.220630 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9431 12:29:57.231064 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9432 12:29:57.231149 using LZMA
9433 12:29:57.239185 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9434 12:29:57.245667 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9435 12:29:57.249113 Loading segment from ROM address 0x4010001c
9436 12:29:57.249198 Entry Point 0x54601000
9437 12:29:57.252415 Loaded segments
9438 12:29:57.255621 NOTICE: MT8192 bl31_setup
9439 12:29:57.262448 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9440 12:29:57.266040 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9441 12:29:57.269178 WARNING: region 0:
9442 12:29:57.272880 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 12:29:57.272959 WARNING: region 1:
9444 12:29:57.279063 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9445 12:29:57.282709 WARNING: region 2:
9446 12:29:57.285709 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9447 12:29:57.289002 WARNING: region 3:
9448 12:29:57.292980 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 12:29:57.296070 WARNING: region 4:
9450 12:29:57.302565 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9451 12:29:57.302652 WARNING: region 5:
9452 12:29:57.305675 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 12:29:57.309639 WARNING: region 6:
9454 12:29:57.313070 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 12:29:57.313147 WARNING: region 7:
9456 12:29:57.319668 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 12:29:57.326285 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9458 12:29:57.329592 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9459 12:29:57.332775 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9460 12:29:57.339240 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9461 12:29:57.342492 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9462 12:29:57.345826 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9463 12:29:57.352875 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9464 12:29:57.356092 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9465 12:29:57.359453 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9466 12:29:57.366381 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9467 12:29:57.369491 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9468 12:29:57.376327 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9469 12:29:57.379531 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9470 12:29:57.382763 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9471 12:29:57.389680 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9472 12:29:57.392701 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9473 12:29:57.396095 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9474 12:29:57.403092 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9475 12:29:57.406289 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9476 12:29:57.409503 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9477 12:29:57.416474 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9478 12:29:57.419729 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9479 12:29:57.426234 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9480 12:29:57.429516 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9481 12:29:57.432942 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9482 12:29:57.439792 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9483 12:29:57.443064 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9484 12:29:57.449673 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9485 12:29:57.452899 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9486 12:29:57.456200 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9487 12:29:57.463409 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9488 12:29:57.466729 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9489 12:29:57.469940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9490 12:29:57.476212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9491 12:29:57.479913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9492 12:29:57.483134 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9493 12:29:57.486263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9494 12:29:57.493053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9495 12:29:57.496246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9496 12:29:57.500031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9497 12:29:57.503237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9498 12:29:57.509561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9499 12:29:57.513399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9500 12:29:57.516540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9501 12:29:57.519705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9502 12:29:57.526423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9503 12:29:57.529744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9504 12:29:57.532987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9505 12:29:57.539644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9506 12:29:57.543519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9507 12:29:57.546767 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9508 12:29:57.552911 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9509 12:29:57.556690 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9510 12:29:57.563216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9511 12:29:57.566479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9512 12:29:57.573138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9513 12:29:57.576302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9514 12:29:57.580117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9515 12:29:57.586602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9516 12:29:57.589661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9517 12:29:57.596675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9518 12:29:57.599891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9519 12:29:57.606813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9520 12:29:57.610108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9521 12:29:57.613354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9522 12:29:57.620436 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9523 12:29:57.623271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9524 12:29:57.629807 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9525 12:29:57.633247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9526 12:29:57.639970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9527 12:29:57.643093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9528 12:29:57.646663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9529 12:29:57.653381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9530 12:29:57.656777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9531 12:29:57.663296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9532 12:29:57.666635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9533 12:29:57.673328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9534 12:29:57.676675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9535 12:29:57.680006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9536 12:29:57.686337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9537 12:29:57.690052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9538 12:29:57.696950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9539 12:29:57.700159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9540 12:29:57.706622 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9541 12:29:57.710342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9542 12:29:57.713572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9543 12:29:57.720230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9544 12:29:57.723362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9545 12:29:57.730212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9546 12:29:57.733276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9547 12:29:57.740104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9548 12:29:57.743416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9549 12:29:57.746580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9550 12:29:57.753587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9551 12:29:57.757047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9552 12:29:57.763566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9553 12:29:57.766729 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9554 12:29:57.770031 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9555 12:29:57.773289 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9556 12:29:57.779987 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9557 12:29:57.783352 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9558 12:29:57.787143 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9559 12:29:57.793969 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9560 12:29:57.797074 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9561 12:29:57.804045 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9562 12:29:57.807167 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9563 12:29:57.810226 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9564 12:29:57.817281 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9565 12:29:57.820609 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9566 12:29:57.827116 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9567 12:29:57.830475 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9568 12:29:57.833672 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9569 12:29:57.840048 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9570 12:29:57.843791 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9571 12:29:57.850269 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9572 12:29:57.853956 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9573 12:29:57.857138 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9574 12:29:57.860404 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9575 12:29:57.867059 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9576 12:29:57.870122 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9577 12:29:57.873518 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9578 12:29:57.876975 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9579 12:29:57.883507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9580 12:29:57.886683 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9581 12:29:57.889996 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9582 12:29:57.896991 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9583 12:29:57.900063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9584 12:29:57.906712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9585 12:29:57.909961 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9586 12:29:57.913693 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9587 12:29:57.919987 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9588 12:29:57.923633 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9589 12:29:57.926727 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9590 12:29:57.933801 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9591 12:29:57.937172 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9592 12:29:57.943509 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9593 12:29:57.946893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9594 12:29:57.949966 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9595 12:29:57.956901 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9596 12:29:57.960033 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9597 12:29:57.967364 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9598 12:29:57.970622 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9599 12:29:57.973791 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9600 12:29:57.980390 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9601 12:29:57.983744 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9602 12:29:57.987126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9603 12:29:57.993806 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9604 12:29:57.997134 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9605 12:29:58.003601 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9606 12:29:58.007285 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9607 12:29:58.010427 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9608 12:29:58.017443 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9609 12:29:58.020609 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9610 12:29:58.026909 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9611 12:29:58.030516 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9612 12:29:58.033593 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9613 12:29:58.040224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9614 12:29:58.043461 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9615 12:29:58.047340 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9616 12:29:58.053725 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9617 12:29:58.056971 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9618 12:29:58.063716 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9619 12:29:58.067258 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9620 12:29:58.070577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9621 12:29:58.077027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9622 12:29:58.080196 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9623 12:29:58.084120 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9624 12:29:58.090653 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9625 12:29:58.093923 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9626 12:29:58.099937 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9627 12:29:58.103276 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9628 12:29:58.107203 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9629 12:29:58.113517 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9630 12:29:58.117192 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9631 12:29:58.123541 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9632 12:29:58.126610 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9633 12:29:58.130538 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9634 12:29:58.137038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9635 12:29:58.140128 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9636 12:29:58.147232 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9637 12:29:58.150537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9638 12:29:58.153751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9639 12:29:58.160273 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9640 12:29:58.163509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9641 12:29:58.169891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9642 12:29:58.173437 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9643 12:29:58.176738 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9644 12:29:58.183624 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9645 12:29:58.186959 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9646 12:29:58.193589 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9647 12:29:58.196721 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9648 12:29:58.199977 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9649 12:29:58.206664 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9650 12:29:58.209943 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9651 12:29:58.216562 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9652 12:29:58.220207 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9653 12:29:58.223409 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9654 12:29:58.229881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9655 12:29:58.233716 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9656 12:29:58.240115 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9657 12:29:58.243166 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9658 12:29:58.246931 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9659 12:29:58.253022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9660 12:29:58.256333 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9661 12:29:58.263506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9662 12:29:58.266756 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9663 12:29:58.273335 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9664 12:29:58.276409 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9665 12:29:58.279977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9666 12:29:58.286055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9667 12:29:58.289732 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9668 12:29:58.296468 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9669 12:29:58.299669 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9670 12:29:58.306166 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9671 12:29:58.309462 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9672 12:29:58.312795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9673 12:29:58.319322 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9674 12:29:58.322598 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9675 12:29:58.329291 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9676 12:29:58.332979 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9677 12:29:58.336008 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9678 12:29:58.343097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9679 12:29:58.346239 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9680 12:29:58.353083 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9681 12:29:58.355771 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9682 12:29:58.359774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9683 12:29:58.366203 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9684 12:29:58.369428 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9685 12:29:58.376142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9686 12:29:58.379507 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9687 12:29:58.382701 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9688 12:29:58.386204 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9689 12:29:58.392724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9690 12:29:58.395794 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9691 12:29:58.399609 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9692 12:29:58.406027 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9693 12:29:58.409357 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9694 12:29:58.412579 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9695 12:29:58.419120 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9696 12:29:58.422982 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9697 12:29:58.425749 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9698 12:29:58.432646 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9699 12:29:58.435883 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9700 12:29:58.439588 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9701 12:29:58.445979 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9702 12:29:58.449204 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9703 12:29:58.455938 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9704 12:29:58.459080 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9705 12:29:58.462451 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9706 12:29:58.469458 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9707 12:29:58.472600 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9708 12:29:58.475733 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9709 12:29:58.482271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9710 12:29:58.485557 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9711 12:29:58.488793 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9712 12:29:58.495680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9713 12:29:58.499057 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9714 12:29:58.505800 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9715 12:29:58.508997 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9716 12:29:58.512241 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9717 12:29:58.519013 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9718 12:29:58.522351 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9719 12:29:58.525632 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9720 12:29:58.532273 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9721 12:29:58.536085 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9722 12:29:58.539233 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9723 12:29:58.545631 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9724 12:29:58.549372 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9725 12:29:58.552628 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9726 12:29:58.558940 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9727 12:29:58.562629 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9728 12:29:58.565806 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9729 12:29:58.569034 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9730 12:29:58.572260 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9731 12:29:58.578800 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9732 12:29:58.582518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9733 12:29:58.585625 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9734 12:29:58.592236 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9735 12:29:58.595891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9736 12:29:58.599106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9737 12:29:58.602301 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9738 12:29:58.608796 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9739 12:29:58.612288 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9740 12:29:58.615921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9741 12:29:58.622375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9742 12:29:58.625601 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9743 12:29:58.632254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9744 12:29:58.635595 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9745 12:29:58.642183 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9746 12:29:58.645285 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9747 12:29:58.649061 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9748 12:29:58.655269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9749 12:29:58.658625 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9750 12:29:58.665700 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9751 12:29:58.668927 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9752 12:29:58.672008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9753 12:29:58.678766 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9754 12:29:58.682045 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9755 12:29:58.689051 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9756 12:29:58.691954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9757 12:29:58.695094 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9758 12:29:58.702012 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9759 12:29:58.705246 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9760 12:29:58.711969 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9761 12:29:58.715275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9762 12:29:58.718375 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9763 12:29:58.725065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9764 12:29:58.728408 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9765 12:29:58.735060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9766 12:29:58.738334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9767 12:29:58.745120 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9768 12:29:58.748329 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9769 12:29:58.752072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9770 12:29:58.758799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9771 12:29:58.761910 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9772 12:29:58.768328 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9773 12:29:58.772221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9774 12:29:58.775269 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9775 12:29:58.782328 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9776 12:29:58.785716 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9777 12:29:58.792290 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9778 12:29:58.795568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9779 12:29:58.798813 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9780 12:29:58.805463 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9781 12:29:58.808479 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9782 12:29:58.815174 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9783 12:29:58.818459 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9784 12:29:58.821765 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9785 12:29:58.828305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9786 12:29:58.831948 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9787 12:29:58.838411 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9788 12:29:58.841740 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9789 12:29:58.845009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9790 12:29:58.851587 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9791 12:29:58.855140 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9792 12:29:58.861545 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9793 12:29:58.865194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9794 12:29:58.868173 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9795 12:29:58.875145 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9796 12:29:58.878368 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9797 12:29:58.885324 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9798 12:29:58.888664 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9799 12:29:58.892093 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9800 12:29:58.898431 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9801 12:29:58.901797 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9802 12:29:58.908109 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9803 12:29:58.911541 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9804 12:29:58.915139 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9805 12:29:58.921621 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9806 12:29:58.924928 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9807 12:29:58.931551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9808 12:29:58.935047 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9809 12:29:58.941495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9810 12:29:58.944808 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9811 12:29:58.947954 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9812 12:29:58.954465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9813 12:29:58.958425 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9814 12:29:58.964529 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9815 12:29:58.967791 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9816 12:29:58.974601 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9817 12:29:58.977729 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9818 12:29:58.981394 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9819 12:29:58.987779 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9820 12:29:58.991064 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9821 12:29:58.997713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9822 12:29:59.001081 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9823 12:29:59.007663 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9824 12:29:59.010972 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9825 12:29:59.014324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9826 12:29:59.020933 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9827 12:29:59.024380 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9828 12:29:59.030990 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9829 12:29:59.034255 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9830 12:29:59.041143 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9831 12:29:59.044368 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9832 12:29:59.047573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9833 12:29:59.054278 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9834 12:29:59.057606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9835 12:29:59.064026 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9836 12:29:59.067808 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9837 12:29:59.074128 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9838 12:29:59.077332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9839 12:29:59.084114 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9840 12:29:59.087765 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9841 12:29:59.090968 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9842 12:29:59.097265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9843 12:29:59.100558 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9844 12:29:59.107178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9845 12:29:59.111084 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9846 12:29:59.117133 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9847 12:29:59.121036 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9848 12:29:59.124105 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9849 12:29:59.130777 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9850 12:29:59.133842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9851 12:29:59.140177 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9852 12:29:59.144014 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9853 12:29:59.150360 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9854 12:29:59.153721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9855 12:29:59.160472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9856 12:29:59.163739 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9857 12:29:59.167012 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9858 12:29:59.173991 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9859 12:29:59.177063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9860 12:29:59.180337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9861 12:29:59.187190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9862 12:29:59.190268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9863 12:29:59.197181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9864 12:29:59.200241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9865 12:29:59.207318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9866 12:29:59.210522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9867 12:29:59.216865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9868 12:29:59.220392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9869 12:29:59.226835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9870 12:29:59.230199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9871 12:29:59.236939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9872 12:29:59.239987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9873 12:29:59.246935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9874 12:29:59.250280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9875 12:29:59.256718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9876 12:29:59.259910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9877 12:29:59.266603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9878 12:29:59.269982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9879 12:29:59.276553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9880 12:29:59.279779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9881 12:29:59.286563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9882 12:29:59.290275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9883 12:29:59.296587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9884 12:29:59.300245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9885 12:29:59.306582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9886 12:29:59.309735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9887 12:29:59.316879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9888 12:29:59.320123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9889 12:29:59.326542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9890 12:29:59.329776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9891 12:29:59.333138 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9892 12:29:59.337060 INFO: [APUAPC] vio 0
9893 12:29:59.343315 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9894 12:29:59.346580 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9895 12:29:59.349681 INFO: [APUAPC] D0_APC_0: 0x400510
9896 12:29:59.353413 INFO: [APUAPC] D0_APC_1: 0x0
9897 12:29:59.356782 INFO: [APUAPC] D0_APC_2: 0x1540
9898 12:29:59.359976 INFO: [APUAPC] D0_APC_3: 0x0
9899 12:29:59.363077 INFO: [APUAPC] D1_APC_0: 0xffffffff
9900 12:29:59.366377 INFO: [APUAPC] D1_APC_1: 0xffffffff
9901 12:29:59.369734 INFO: [APUAPC] D1_APC_2: 0x3fffff
9902 12:29:59.369839 INFO: [APUAPC] D1_APC_3: 0x0
9903 12:29:59.376331 INFO: [APUAPC] D2_APC_0: 0xffffffff
9904 12:29:59.379648 INFO: [APUAPC] D2_APC_1: 0xffffffff
9905 12:29:59.382818 INFO: [APUAPC] D2_APC_2: 0x3fffff
9906 12:29:59.382922 INFO: [APUAPC] D2_APC_3: 0x0
9907 12:29:59.386121 INFO: [APUAPC] D3_APC_0: 0xffffffff
9908 12:29:59.389468 INFO: [APUAPC] D3_APC_1: 0xffffffff
9909 12:29:59.393205 INFO: [APUAPC] D3_APC_2: 0x3fffff
9910 12:29:59.396236 INFO: [APUAPC] D3_APC_3: 0x0
9911 12:29:59.399318 INFO: [APUAPC] D4_APC_0: 0xffffffff
9912 12:29:59.403046 INFO: [APUAPC] D4_APC_1: 0xffffffff
9913 12:29:59.406128 INFO: [APUAPC] D4_APC_2: 0x3fffff
9914 12:29:59.409802 INFO: [APUAPC] D4_APC_3: 0x0
9915 12:29:59.412846 INFO: [APUAPC] D5_APC_0: 0xffffffff
9916 12:29:59.416512 INFO: [APUAPC] D5_APC_1: 0xffffffff
9917 12:29:59.419605 INFO: [APUAPC] D5_APC_2: 0x3fffff
9918 12:29:59.422815 INFO: [APUAPC] D5_APC_3: 0x0
9919 12:29:59.426075 INFO: [APUAPC] D6_APC_0: 0xffffffff
9920 12:29:59.429278 INFO: [APUAPC] D6_APC_1: 0xffffffff
9921 12:29:59.432580 INFO: [APUAPC] D6_APC_2: 0x3fffff
9922 12:29:59.436502 INFO: [APUAPC] D6_APC_3: 0x0
9923 12:29:59.439645 INFO: [APUAPC] D7_APC_0: 0xffffffff
9924 12:29:59.442705 INFO: [APUAPC] D7_APC_1: 0xffffffff
9925 12:29:59.445960 INFO: [APUAPC] D7_APC_2: 0x3fffff
9926 12:29:59.449886 INFO: [APUAPC] D7_APC_3: 0x0
9927 12:29:59.453157 INFO: [APUAPC] D8_APC_0: 0xffffffff
9928 12:29:59.456253 INFO: [APUAPC] D8_APC_1: 0xffffffff
9929 12:29:59.459295 INFO: [APUAPC] D8_APC_2: 0x3fffff
9930 12:29:59.462624 INFO: [APUAPC] D8_APC_3: 0x0
9931 12:29:59.465930 INFO: [APUAPC] D9_APC_0: 0xffffffff
9932 12:29:59.469662 INFO: [APUAPC] D9_APC_1: 0xffffffff
9933 12:29:59.472937 INFO: [APUAPC] D9_APC_2: 0x3fffff
9934 12:29:59.476428 INFO: [APUAPC] D9_APC_3: 0x0
9935 12:29:59.479736 INFO: [APUAPC] D10_APC_0: 0xffffffff
9936 12:29:59.482468 INFO: [APUAPC] D10_APC_1: 0xffffffff
9937 12:29:59.486405 INFO: [APUAPC] D10_APC_2: 0x3fffff
9938 12:29:59.489681 INFO: [APUAPC] D10_APC_3: 0x0
9939 12:29:59.493116 INFO: [APUAPC] D11_APC_0: 0xffffffff
9940 12:29:59.496623 INFO: [APUAPC] D11_APC_1: 0xffffffff
9941 12:29:59.499800 INFO: [APUAPC] D11_APC_2: 0x3fffff
9942 12:29:59.502762 INFO: [APUAPC] D11_APC_3: 0x0
9943 12:29:59.506542 INFO: [APUAPC] D12_APC_0: 0xffffffff
9944 12:29:59.509690 INFO: [APUAPC] D12_APC_1: 0xffffffff
9945 12:29:59.512930 INFO: [APUAPC] D12_APC_2: 0x3fffff
9946 12:29:59.516035 INFO: [APUAPC] D12_APC_3: 0x0
9947 12:29:59.519804 INFO: [APUAPC] D13_APC_0: 0xffffffff
9948 12:29:59.522989 INFO: [APUAPC] D13_APC_1: 0xffffffff
9949 12:29:59.526131 INFO: [APUAPC] D13_APC_2: 0x3fffff
9950 12:29:59.529804 INFO: [APUAPC] D13_APC_3: 0x0
9951 12:29:59.532918 INFO: [APUAPC] D14_APC_0: 0xffffffff
9952 12:29:59.536124 INFO: [APUAPC] D14_APC_1: 0xffffffff
9953 12:29:59.539666 INFO: [APUAPC] D14_APC_2: 0x3fffff
9954 12:29:59.542910 INFO: [APUAPC] D14_APC_3: 0x0
9955 12:29:59.546100 INFO: [APUAPC] D15_APC_0: 0xffffffff
9956 12:29:59.549253 INFO: [APUAPC] D15_APC_1: 0xffffffff
9957 12:29:59.553179 INFO: [APUAPC] D15_APC_2: 0x3fffff
9958 12:29:59.555840 INFO: [APUAPC] D15_APC_3: 0x0
9959 12:29:59.558887 INFO: [APUAPC] APC_CON: 0x4
9960 12:29:59.562203 INFO: [NOCDAPC] D0_APC_0: 0x0
9961 12:29:59.565428 INFO: [NOCDAPC] D0_APC_1: 0x0
9962 12:29:59.565512 INFO: [NOCDAPC] D1_APC_0: 0x0
9963 12:29:59.569186 INFO: [NOCDAPC] D1_APC_1: 0xfff
9964 12:29:59.572325 INFO: [NOCDAPC] D2_APC_0: 0x0
9965 12:29:59.575447 INFO: [NOCDAPC] D2_APC_1: 0xfff
9966 12:29:59.578667 INFO: [NOCDAPC] D3_APC_0: 0x0
9967 12:29:59.582048 INFO: [NOCDAPC] D3_APC_1: 0xfff
9968 12:29:59.585430 INFO: [NOCDAPC] D4_APC_0: 0x0
9969 12:29:59.588652 INFO: [NOCDAPC] D4_APC_1: 0xfff
9970 12:29:59.591965 INFO: [NOCDAPC] D5_APC_0: 0x0
9971 12:29:59.595123 INFO: [NOCDAPC] D5_APC_1: 0xfff
9972 12:29:59.599099 INFO: [NOCDAPC] D6_APC_0: 0x0
9973 12:29:59.599189 INFO: [NOCDAPC] D6_APC_1: 0xfff
9974 12:29:59.602359 INFO: [NOCDAPC] D7_APC_0: 0x0
9975 12:29:59.605639 INFO: [NOCDAPC] D7_APC_1: 0xfff
9976 12:29:59.608761 INFO: [NOCDAPC] D8_APC_0: 0x0
9977 12:29:59.611977 INFO: [NOCDAPC] D8_APC_1: 0xfff
9978 12:29:59.615046 INFO: [NOCDAPC] D9_APC_0: 0x0
9979 12:29:59.618908 INFO: [NOCDAPC] D9_APC_1: 0xfff
9980 12:29:59.622079 INFO: [NOCDAPC] D10_APC_0: 0x0
9981 12:29:59.625091 INFO: [NOCDAPC] D10_APC_1: 0xfff
9982 12:29:59.628273 INFO: [NOCDAPC] D11_APC_0: 0x0
9983 12:29:59.632175 INFO: [NOCDAPC] D11_APC_1: 0xfff
9984 12:29:59.635161 INFO: [NOCDAPC] D12_APC_0: 0x0
9985 12:29:59.638825 INFO: [NOCDAPC] D12_APC_1: 0xfff
9986 12:29:59.638908 INFO: [NOCDAPC] D13_APC_0: 0x0
9987 12:29:59.642048 INFO: [NOCDAPC] D13_APC_1: 0xfff
9988 12:29:59.645346 INFO: [NOCDAPC] D14_APC_0: 0x0
9989 12:29:59.648461 INFO: [NOCDAPC] D14_APC_1: 0xfff
9990 12:29:59.651491 INFO: [NOCDAPC] D15_APC_0: 0x0
9991 12:29:59.655431 INFO: [NOCDAPC] D15_APC_1: 0xfff
9992 12:29:59.658574 INFO: [NOCDAPC] APC_CON: 0x4
9993 12:29:59.661920 INFO: [APUAPC] set_apusys_apc done
9994 12:29:59.665225 INFO: [DEVAPC] devapc_init done
9995 12:29:59.668230 INFO: GICv3 without legacy support detected.
9996 12:29:59.672057 INFO: ARM GICv3 driver initialized in EL3
9997 12:29:59.678648 INFO: Maximum SPI INTID supported: 639
9998 12:29:59.681719 INFO: BL31: Initializing runtime services
9999 12:29:59.684964 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10000 12:29:59.688236 INFO: SPM: enable CPC mode
10001 12:29:59.694961 INFO: mcdi ready for mcusys-off-idle and system suspend
10002 12:29:59.698704 INFO: BL31: Preparing for EL3 exit to normal world
10003 12:29:59.702136 INFO: Entry point address = 0x80000000
10004 12:29:59.704819 INFO: SPSR = 0x8
10005 12:29:59.710689
10006 12:29:59.710771
10007 12:29:59.710836
10008 12:29:59.713973 Starting depthcharge on Spherion...
10009 12:29:59.714056
10010 12:29:59.714121 Wipe memory regions:
10011 12:29:59.714181
10012 12:29:59.714793 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10013 12:29:59.714892 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10014 12:29:59.714973 Setting prompt string to ['asurada:']
10015 12:29:59.715048 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10016 12:29:59.716951 [0x00000040000000, 0x00000054600000)
10017 12:29:59.839251
10018 12:29:59.839411 [0x00000054660000, 0x00000080000000)
10019 12:30:00.100020
10020 12:30:00.100203 [0x000000821a7280, 0x000000ffe64000)
10021 12:30:00.845002
10022 12:30:00.845188 [0x00000100000000, 0x00000240000000)
10023 12:30:02.734879
10024 12:30:02.738394 Initializing XHCI USB controller at 0x11200000.
10025 12:30:03.775844
10026 12:30:03.779086 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10027 12:30:03.779209
10028 12:30:03.779304
10029 12:30:03.779445
10030 12:30:03.779766 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 12:30:03.880082 asurada: tftpboot 192.168.201.1 10605787/tftp-deploy-0onrf3em/kernel/image.itb 10605787/tftp-deploy-0onrf3em/kernel/cmdline
10033 12:30:03.880287 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10034 12:30:03.880416 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10035 12:30:03.884511 tftpboot 192.168.201.1 10605787/tftp-deploy-0onrf3em/kernel/image.itp-deploy-0onrf3em/kernel/cmdline
10036 12:30:03.884626
10037 12:30:03.884727 Waiting for link
10038 12:30:04.044700
10039 12:30:04.044864 R8152: Initializing
10040 12:30:04.044942
10041 12:30:04.048012 Version 9 (ocp_data = 6010)
10042 12:30:04.048103
10043 12:30:04.051298 R8152: Done initializing
10044 12:30:04.051405
10045 12:30:04.051483 Adding net device
10046 12:30:05.924404
10047 12:30:05.924563 done.
10048 12:30:05.924635
10049 12:30:05.924697 MAC: 00:e0:4c:78:7a:aa
10050 12:30:05.924757
10051 12:30:05.927906 Sending DHCP discover... done.
10052 12:30:05.927992
10053 12:30:15.900982 Waiting for reply... R8152: Bulk read error 0xffffffbf
10054 12:30:15.901513
10055 12:30:15.904088 Receive failed.
10056 12:30:15.904614
10057 12:30:15.905111 done.
10058 12:30:15.905681
10059 12:30:15.907731 Sending DHCP request... done.
10060 12:30:15.908260
10061 12:30:15.915463 Waiting for reply... done.
10062 12:30:15.915893
10063 12:30:15.916229 My ip is 192.168.201.12
10064 12:30:15.916549
10065 12:30:15.918924 The DHCP server ip is 192.168.201.1
10066 12:30:15.919520
10067 12:30:15.925207 TFTP server IP predefined by user: 192.168.201.1
10068 12:30:15.925858
10069 12:30:15.931539 Bootfile predefined by user: 10605787/tftp-deploy-0onrf3em/kernel/image.itb
10070 12:30:15.931936
10071 12:30:15.934908 Sending tftp read request... done.
10072 12:30:15.935367
10073 12:30:15.941048 Waiting for the transfer...
10074 12:30:15.941524
10075 12:30:16.274214 00000000 ################################################################
10076 12:30:16.274737
10077 12:30:16.616238 00080000 ################################################################
10078 12:30:16.616840
10079 12:30:16.869129 00100000 ################################################################
10080 12:30:16.869294
10081 12:30:17.121537 00180000 ################################################################
10082 12:30:17.121691
10083 12:30:17.378758 00200000 ################################################################
10084 12:30:17.378912
10085 12:30:17.634753 00280000 ################################################################
10086 12:30:17.634897
10087 12:30:17.888046 00300000 ################################################################
10088 12:30:17.888191
10089 12:30:18.135746 00380000 ################################################################
10090 12:30:18.135897
10091 12:30:18.383433 00400000 ################################################################
10092 12:30:18.383579
10093 12:30:18.625859 00480000 ################################################################
10094 12:30:18.626016
10095 12:30:18.882835 00500000 ################################################################
10096 12:30:18.883380
10097 12:30:19.161865 00580000 ################################################################
10098 12:30:19.162004
10099 12:30:19.419005 00600000 ################################################################
10100 12:30:19.419181
10101 12:30:19.672556 00680000 ################################################################
10102 12:30:19.672700
10103 12:30:19.924189 00700000 ################################################################
10104 12:30:19.924346
10105 12:30:20.169471 00780000 ################################################################
10106 12:30:20.169625
10107 12:30:20.419477 00800000 ################################################################
10108 12:30:20.419671
10109 12:30:20.668560 00880000 ################################################################
10110 12:30:20.668710
10111 12:30:20.917110 00900000 ################################################################
10112 12:30:20.917299
10113 12:30:21.159313 00980000 ################################################################
10114 12:30:21.159529
10115 12:30:21.407835 00a00000 ################################################################
10116 12:30:21.407987
10117 12:30:21.661579 00a80000 ################################################################
10118 12:30:21.661824
10119 12:30:21.904872 00b00000 ################################################################
10120 12:30:21.905027
10121 12:30:22.156307 00b80000 ################################################################
10122 12:30:22.156487
10123 12:30:22.419163 00c00000 ################################################################
10124 12:30:22.419374
10125 12:30:22.699548 00c80000 ################################################################
10126 12:30:22.699704
10127 12:30:22.947200 00d00000 ################################################################
10128 12:30:22.947419
10129 12:30:23.193329 00d80000 ################################################################
10130 12:30:23.193473
10131 12:30:23.431995 00e00000 ################################################################
10132 12:30:23.432161
10133 12:30:23.688504 00e80000 ################################################################
10134 12:30:23.688669
10135 12:30:23.926942 00f00000 ################################################################
10136 12:30:23.927115
10137 12:30:24.177233 00f80000 ################################################################
10138 12:30:24.177411
10139 12:30:24.427831 01000000 ################################################################
10140 12:30:24.427977
10141 12:30:24.685741 01080000 ################################################################
10142 12:30:24.685895
10143 12:30:24.934873 01100000 ################################################################
10144 12:30:24.935021
10145 12:30:25.177162 01180000 ################################################################
10146 12:30:25.177315
10147 12:30:25.425105 01200000 ################################################################
10148 12:30:25.425258
10149 12:30:25.676955 01280000 ################################################################
10150 12:30:25.677110
10151 12:30:25.931242 01300000 ################################################################
10152 12:30:25.931457
10153 12:30:26.187336 01380000 ################################################################
10154 12:30:26.187513
10155 12:30:26.433395 01400000 ################################################################
10156 12:30:26.433573
10157 12:30:26.684123 01480000 ################################################################
10158 12:30:26.684302
10159 12:30:26.937350 01500000 ################################################################
10160 12:30:26.937527
10161 12:30:27.185240 01580000 ################################################################
10162 12:30:27.185445
10163 12:30:27.432546 01600000 ################################################################
10164 12:30:27.432720
10165 12:30:27.683290 01680000 ################################################################
10166 12:30:27.683500
10167 12:30:27.927553 01700000 ################################################################
10168 12:30:27.927757
10169 12:30:28.172950 01780000 ################################################################
10170 12:30:28.173103
10171 12:30:28.420797 01800000 ################################################################
10172 12:30:28.420955
10173 12:30:28.658569 01880000 ################################################################
10174 12:30:28.658753
10175 12:30:28.935863 01900000 ################################################################
10176 12:30:28.936556
10177 12:30:29.266375 01980000 ################################################################
10178 12:30:29.267148
10179 12:30:29.589407 01a00000 ################################################################
10180 12:30:29.589996
10181 12:30:29.923952 01a80000 ################################################################
10182 12:30:29.924105
10183 12:30:30.180459 01b00000 ################################################################
10184 12:30:30.180638
10185 12:30:30.424286 01b80000 ################################################################
10186 12:30:30.424467
10187 12:30:30.670170 01c00000 ################################################################
10188 12:30:30.670345
10189 12:30:30.914111 01c80000 ################################################################
10190 12:30:30.914281
10191 12:30:31.158979 01d00000 ################################################################
10192 12:30:31.159129
10193 12:30:31.404898 01d80000 ################################################################
10194 12:30:31.405051
10195 12:30:31.661537 01e00000 ################################################################
10196 12:30:31.661690
10197 12:30:31.915860 01e80000 ################################################################
10198 12:30:31.916014
10199 12:30:32.171281 01f00000 ################################################################
10200 12:30:32.171454
10201 12:30:32.411953 01f80000 ################################################################
10202 12:30:32.412109
10203 12:30:32.658616 02000000 ################################################################
10204 12:30:32.658792
10205 12:30:32.903859 02080000 ################################################################
10206 12:30:32.904009
10207 12:30:33.147056 02100000 ################################################################
10208 12:30:33.147229
10209 12:30:33.395140 02180000 ################################################################
10210 12:30:33.395350
10211 12:30:33.639867 02200000 ################################################################
10212 12:30:33.640121
10213 12:30:33.898124 02280000 ################################################################
10214 12:30:33.898381
10215 12:30:34.145406 02300000 ################################################################
10216 12:30:34.145580
10217 12:30:34.395478 02380000 ################################################################
10218 12:30:34.395628
10219 12:30:34.639540 02400000 ################################################################
10220 12:30:34.639725
10221 12:30:34.880474 02480000 ################################################################
10222 12:30:34.880668
10223 12:30:35.120890 02500000 ################################################################
10224 12:30:35.121041
10225 12:30:35.361423 02580000 ################################################################
10226 12:30:35.361573
10227 12:30:35.607464 02600000 ################################################################
10228 12:30:35.607605
10229 12:30:35.852398 02680000 ################################################################
10230 12:30:35.852556
10231 12:30:36.098230 02700000 ################################################################
10232 12:30:36.098378
10233 12:30:36.355191 02780000 ################################################################
10234 12:30:36.355393
10235 12:30:36.614332 02800000 ################################################################
10236 12:30:36.614480
10237 12:30:36.886444 02880000 ################################################################
10238 12:30:36.886620
10239 12:30:37.136108 02900000 ################################################################
10240 12:30:37.136263
10241 12:30:37.377440 02980000 ################################################################
10242 12:30:37.377592
10243 12:30:37.621264 02a00000 ################################################################
10244 12:30:37.621442
10245 12:30:37.881406 02a80000 ################################################################
10246 12:30:37.881592
10247 12:30:38.136896 02b00000 ################################################################
10248 12:30:38.137043
10249 12:30:38.390594 02b80000 ################################################################
10250 12:30:38.390750
10251 12:30:38.638992 02c00000 ################################################################
10252 12:30:38.639137
10253 12:30:38.896645 02c80000 ################################################################
10254 12:30:38.896831
10255 12:30:39.150982 02d00000 ################################################################
10256 12:30:39.151141
10257 12:30:39.394963 02d80000 ################################################################
10258 12:30:39.395144
10259 12:30:39.636895 02e00000 ################################################################
10260 12:30:39.637052
10261 12:30:39.878837 02e80000 ################################################################
10262 12:30:39.879018
10263 12:30:40.131102 02f00000 ################################################################
10264 12:30:40.131313
10265 12:30:40.377069 02f80000 ################################################################
10266 12:30:40.377221
10267 12:30:40.629462 03000000 ################################################################
10268 12:30:40.629646
10269 12:30:40.874953 03080000 ################################################################
10270 12:30:40.875145
10271 12:30:41.123822 03100000 ################################################################
10272 12:30:41.124003
10273 12:30:41.378124 03180000 ################################################################
10274 12:30:41.378303
10275 12:30:41.624681 03200000 ################################################################
10276 12:30:41.624896
10277 12:30:41.891835 03280000 ################################################################
10278 12:30:41.892048
10279 12:30:42.139638 03300000 ################################################################
10280 12:30:42.139822
10281 12:30:42.386992 03380000 ################################################################
10282 12:30:42.387177
10283 12:30:42.642368 03400000 ################################################################
10284 12:30:42.642526
10285 12:30:42.904506 03480000 ################################################################
10286 12:30:42.904690
10287 12:30:43.167947 03500000 ################################################################
10288 12:30:43.168104
10289 12:30:43.415523 03580000 ################################################################
10290 12:30:43.415675
10291 12:30:43.668245 03600000 ################################################################
10292 12:30:43.668430
10293 12:30:43.911691 03680000 ################################################################
10294 12:30:43.911851
10295 12:30:44.158064 03700000 ################################################################
10296 12:30:44.158243
10297 12:30:44.424553 03780000 ################################################################
10298 12:30:44.424744
10299 12:30:44.668144 03800000 ################################################################
10300 12:30:44.668338
10301 12:30:44.918438 03880000 ################################################################
10302 12:30:44.918625
10303 12:30:45.162128 03900000 ################################################################
10304 12:30:45.162318
10305 12:30:45.407077 03980000 ################################################################
10306 12:30:45.407231
10307 12:30:45.652749 03a00000 ################################################################
10308 12:30:45.652955
10309 12:30:45.900373 03a80000 ################################################################
10310 12:30:45.900537
10311 12:30:46.144040 03b00000 ################################################################
10312 12:30:46.144192
10313 12:30:46.388516 03b80000 ################################################################
10314 12:30:46.388671
10315 12:30:46.637333 03c00000 ################################################################
10316 12:30:46.637522
10317 12:30:46.878179 03c80000 ################################################################
10318 12:30:46.878365
10319 12:30:47.116486 03d00000 ################################################################
10320 12:30:47.116652
10321 12:30:47.364265 03d80000 ################################################################
10322 12:30:47.364417
10323 12:30:47.632716 03e00000 ################################################################
10324 12:30:47.632869
10325 12:30:47.876422 03e80000 ################################################################
10326 12:30:47.876577
10327 12:30:48.084032 03f00000 ######################################################## done.
10328 12:30:48.084198
10329 12:30:48.087357 The bootfile was 66511274 bytes long.
10330 12:30:48.087439
10331 12:30:48.090598 Sending tftp read request... done.
10332 12:30:48.090684
10333 12:30:48.090752 Waiting for the transfer...
10334 12:30:48.090827
10335 12:30:48.093984 00000000 # done.
10336 12:30:48.094072
10337 12:30:48.100539 Command line loaded dynamically from TFTP file: 10605787/tftp-deploy-0onrf3em/kernel/cmdline
10338 12:30:48.100628
10339 12:30:48.114036 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10340 12:30:48.114124
10341 12:30:48.114192 Loading FIT.
10342 12:30:48.114255
10343 12:30:48.117172 Image ramdisk-1 has 56375568 bytes.
10344 12:30:48.117258
10345 12:30:48.120463 Image fdt-1 has 46924 bytes.
10346 12:30:48.120549
10347 12:30:48.124059 Image kernel-1 has 10086749 bytes.
10348 12:30:48.124146
10349 12:30:48.130861 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10350 12:30:48.130948
10351 12:30:48.150986 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10352 12:30:48.151079
10353 12:30:48.153698 Choosing best match conf-1 for compat google,spherion-rev2.
10354 12:30:48.158959
10355 12:30:48.197755 Connected to device vid:did:rid of 1ae0:0028:00
10356 12:30:48.207743
10357 12:30:48.210993 tpm_get_response: command 0x17b, return code 0x0
10358 12:30:48.211121
10359 12:30:48.214305 ec_init: CrosEC protocol v3 supported (256, 248)
10360 12:30:48.218870
10361 12:30:48.222741 tpm_cleanup: add release locality here.
10362 12:30:48.222836
10363 12:30:48.222937 Shutting down all USB controllers.
10364 12:30:48.225996
10365 12:30:48.226123 Removing current net device
10366 12:30:48.226210
10367 12:30:48.232539 Exiting depthcharge with code 4 at timestamp: 77791245
10368 12:30:48.232652
10369 12:30:48.235635 LZMA decompressing kernel-1 to 0x821a6718
10370 12:30:48.235739
10371 12:30:48.238846 LZMA decompressing kernel-1 to 0x40000000
10372 12:30:49.505761
10373 12:30:49.505936 jumping to kernel
10374 12:30:49.506679 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10375 12:30:49.506821 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10376 12:30:49.506927 Setting prompt string to ['Linux version [0-9]']
10377 12:30:49.507027 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 12:30:49.507127 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10379 12:30:49.588187
10380 12:30:49.591577 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10381 12:30:49.594981 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10382 12:30:49.595077 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10383 12:30:49.595207 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10384 12:30:49.595289 Using line separator: #'\n'#
10385 12:30:49.595390 No login prompt set.
10386 12:30:49.595454 Parsing kernel messages
10387 12:30:49.595510 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10388 12:30:49.595614 [login-action] Waiting for messages, (timeout 00:03:35)
10389 12:30:49.614897 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10390 12:30:49.618216 [ 0.000000] random: crng init done
10391 12:30:49.621359 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10392 12:30:49.624510 [ 0.000000] efi: UEFI not found.
10393 12:30:49.634663 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10394 12:30:49.640778 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10395 12:30:49.650862 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10396 12:30:49.660956 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10397 12:30:49.667458 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10398 12:30:49.670823 [ 0.000000] printk: bootconsole [mtk8250] enabled
10399 12:30:49.679429 [ 0.000000] NUMA: No NUMA configuration found
10400 12:30:49.686039 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10401 12:30:49.692414 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10402 12:30:49.692513 [ 0.000000] Zone ranges:
10403 12:30:49.699054 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10404 12:30:49.702351 [ 0.000000] DMA32 empty
10405 12:30:49.709431 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10406 12:30:49.712799 [ 0.000000] Movable zone start for each node
10407 12:30:49.715843 [ 0.000000] Early memory node ranges
10408 12:30:49.722454 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10409 12:30:49.728773 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10410 12:30:49.736042 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10411 12:30:49.742253 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10412 12:30:49.748712 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10413 12:30:49.755859 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10414 12:30:49.812001 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10415 12:30:49.818378 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10416 12:30:49.825453 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10417 12:30:49.828697 [ 0.000000] psci: probing for conduit method from DT.
10418 12:30:49.835042 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10419 12:30:49.838272 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10420 12:30:49.845297 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10421 12:30:49.848537 [ 0.000000] psci: SMC Calling Convention v1.2
10422 12:30:49.855122 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10423 12:30:49.858555 [ 0.000000] Detected VIPT I-cache on CPU0
10424 12:30:49.865123 [ 0.000000] CPU features: detected: GIC system register CPU interface
10425 12:30:49.871484 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10426 12:30:49.877894 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10427 12:30:49.884807 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10428 12:30:49.891294 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10429 12:30:49.901602 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10430 12:30:49.904765 [ 0.000000] alternatives: applying boot alternatives
10431 12:30:49.911237 [ 0.000000] Fallback order for Node 0: 0
10432 12:30:49.918013 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10433 12:30:49.921363 [ 0.000000] Policy zone: Normal
10434 12:30:49.931623 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10435 12:30:49.941279 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10436 12:30:49.952640 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10437 12:30:49.962692 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10438 12:30:49.969810 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10439 12:30:49.973051 <6>[ 0.000000] software IO TLB: area num 8.
10440 12:30:50.029216 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10441 12:30:50.178399 <6>[ 0.000000] Memory: 7917888K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434880K reserved, 32768K cma-reserved)
10442 12:30:50.185117 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10443 12:30:50.192021 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10444 12:30:50.195193 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10445 12:30:50.201550 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10446 12:30:50.208208 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10447 12:30:50.212039 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10448 12:30:50.221945 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10449 12:30:50.228554 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10450 12:30:50.231829 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10451 12:30:50.239899 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10452 12:30:50.243005 <6>[ 0.000000] GICv3: 608 SPIs implemented
10453 12:30:50.249849 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10454 12:30:50.252848 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10455 12:30:50.255995 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10456 12:30:50.266362 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10457 12:30:50.276209 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10458 12:30:50.289862 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10459 12:30:50.296225 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10460 12:30:50.305055 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10461 12:30:50.318139 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10462 12:30:50.324672 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10463 12:30:50.331760 <6>[ 0.009173] Console: colour dummy device 80x25
10464 12:30:50.341539 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10465 12:30:50.348208 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10466 12:30:50.351223 <6>[ 0.029216] LSM: Security Framework initializing
10467 12:30:50.358075 <6>[ 0.034153] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10468 12:30:50.368172 <6>[ 0.041966] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 12:30:50.374334 <6>[ 0.051386] cblist_init_generic: Setting adjustable number of callback queues.
10470 12:30:50.381555 <6>[ 0.058839] cblist_init_generic: Setting shift to 3 and lim to 1.
10471 12:30:50.387587 <6>[ 0.065178] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 12:30:50.394818 <6>[ 0.071626] rcu: Hierarchical SRCU implementation.
10473 12:30:50.397935 <6>[ 0.076641] rcu: Max phase no-delay instances is 1000.
10474 12:30:50.406328 <6>[ 0.083660] EFI services will not be available.
10475 12:30:50.409607 <6>[ 0.088657] smp: Bringing up secondary CPUs ...
10476 12:30:50.418525 <6>[ 0.093711] Detected VIPT I-cache on CPU1
10477 12:30:50.425091 <6>[ 0.093785] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10478 12:30:50.431480 <6>[ 0.093817] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10479 12:30:50.434758 <6>[ 0.094150] Detected VIPT I-cache on CPU2
10480 12:30:50.444789 <6>[ 0.094200] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10481 12:30:50.451290 <6>[ 0.094214] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10482 12:30:50.454513 <6>[ 0.094473] Detected VIPT I-cache on CPU3
10483 12:30:50.461172 <6>[ 0.094521] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10484 12:30:50.467908 <6>[ 0.094535] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10485 12:30:50.471599 <6>[ 0.094824] CPU features: detected: Spectre-v4
10486 12:30:50.477889 <6>[ 0.094830] CPU features: detected: Spectre-BHB
10487 12:30:50.481114 <6>[ 0.094835] Detected PIPT I-cache on CPU4
10488 12:30:50.487730 <6>[ 0.094885] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10489 12:30:50.494273 <6>[ 0.094900] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10490 12:30:50.501356 <6>[ 0.095185] Detected PIPT I-cache on CPU5
10491 12:30:50.507372 <6>[ 0.095247] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10492 12:30:50.514625 <6>[ 0.095264] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10493 12:30:50.517858 <6>[ 0.095552] Detected PIPT I-cache on CPU6
10494 12:30:50.523990 <6>[ 0.095618] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10495 12:30:50.530995 <6>[ 0.095634] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10496 12:30:50.537749 <6>[ 0.095932] Detected PIPT I-cache on CPU7
10497 12:30:50.544361 <6>[ 0.095999] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10498 12:30:50.550890 <6>[ 0.096015] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10499 12:30:50.554181 <6>[ 0.096062] smp: Brought up 1 node, 8 CPUs
10500 12:30:50.560368 <6>[ 0.237359] SMP: Total of 8 processors activated.
10501 12:30:50.563721 <6>[ 0.242310] CPU features: detected: 32-bit EL0 Support
10502 12:30:50.573825 <6>[ 0.247674] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10503 12:30:50.580836 <6>[ 0.256474] CPU features: detected: Common not Private translations
10504 12:30:50.584023 <6>[ 0.262949] CPU features: detected: CRC32 instructions
10505 12:30:50.590914 <6>[ 0.268301] CPU features: detected: RCpc load-acquire (LDAPR)
10506 12:30:50.597438 <6>[ 0.274261] CPU features: detected: LSE atomic instructions
10507 12:30:50.603850 <6>[ 0.280042] CPU features: detected: Privileged Access Never
10508 12:30:50.607596 <6>[ 0.285858] CPU features: detected: RAS Extension Support
10509 12:30:50.617555 <6>[ 0.291466] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10510 12:30:50.620817 <6>[ 0.298685] CPU: All CPU(s) started at EL2
10511 12:30:50.626948 <6>[ 0.303001] alternatives: applying system-wide alternatives
10512 12:30:50.636021 <6>[ 0.313721] devtmpfs: initialized
10513 12:30:50.651656 <6>[ 0.322662] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10514 12:30:50.658289 <6>[ 0.332627] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10515 12:30:50.664818 <6>[ 0.340847] pinctrl core: initialized pinctrl subsystem
10516 12:30:50.667973 <6>[ 0.347505] DMI not present or invalid.
10517 12:30:50.674771 <6>[ 0.351916] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10518 12:30:50.684903 <6>[ 0.358793] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10519 12:30:50.691028 <6>[ 0.366374] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10520 12:30:50.701385 <6>[ 0.374600] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10521 12:30:50.704706 <6>[ 0.382845] audit: initializing netlink subsys (disabled)
10522 12:30:50.714509 <5>[ 0.388541] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10523 12:30:50.721132 <6>[ 0.389250] thermal_sys: Registered thermal governor 'step_wise'
10524 12:30:50.727721 <6>[ 0.396508] thermal_sys: Registered thermal governor 'power_allocator'
10525 12:30:50.731008 <6>[ 0.402762] cpuidle: using governor menu
10526 12:30:50.737507 <6>[ 0.413727] NET: Registered PF_QIPCRTR protocol family
10527 12:30:50.744153 <6>[ 0.419206] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10528 12:30:50.750577 <6>[ 0.426309] ASID allocator initialised with 32768 entries
10529 12:30:50.753916 <6>[ 0.432884] Serial: AMBA PL011 UART driver
10530 12:30:50.763823 <4>[ 0.441537] Trying to register duplicate clock ID: 134
10531 12:30:50.819964 <6>[ 0.500701] KASLR enabled
10532 12:30:50.834016 <6>[ 0.508434] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10533 12:30:50.841059 <6>[ 0.515448] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10534 12:30:50.847243 <6>[ 0.521937] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10535 12:30:50.853767 <6>[ 0.528943] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10536 12:30:50.860723 <6>[ 0.535431] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10537 12:30:50.867460 <6>[ 0.542437] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10538 12:30:50.874013 <6>[ 0.548925] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10539 12:30:50.880751 <6>[ 0.555933] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10540 12:30:50.883912 <6>[ 0.563426] ACPI: Interpreter disabled.
10541 12:30:50.892098 <6>[ 0.569823] iommu: Default domain type: Translated
10542 12:30:50.898889 <6>[ 0.574987] iommu: DMA domain TLB invalidation policy: strict mode
10543 12:30:50.902114 <5>[ 0.581645] SCSI subsystem initialized
10544 12:30:50.908783 <6>[ 0.585884] usbcore: registered new interface driver usbfs
10545 12:30:50.915243 <6>[ 0.591616] usbcore: registered new interface driver hub
10546 12:30:50.918372 <6>[ 0.597169] usbcore: registered new device driver usb
10547 12:30:50.925399 <6>[ 0.603277] pps_core: LinuxPPS API ver. 1 registered
10548 12:30:50.935512 <6>[ 0.608474] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10549 12:30:50.938912 <6>[ 0.617818] PTP clock support registered
10550 12:30:50.942150 <6>[ 0.622058] EDAC MC: Ver: 3.0.0
10551 12:30:50.949237 <6>[ 0.627242] FPGA manager framework
10552 12:30:50.956233 <6>[ 0.630917] Advanced Linux Sound Architecture Driver Initialized.
10553 12:30:50.959439 <6>[ 0.637698] vgaarb: loaded
10554 12:30:50.966399 <6>[ 0.640852] clocksource: Switched to clocksource arch_sys_counter
10555 12:30:50.969587 <5>[ 0.647303] VFS: Disk quotas dquot_6.6.0
10556 12:30:50.976267 <6>[ 0.651489] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10557 12:30:50.979442 <6>[ 0.658683] pnp: PnP ACPI: disabled
10558 12:30:50.987617 <6>[ 0.665490] NET: Registered PF_INET protocol family
10559 12:30:50.997487 <6>[ 0.671088] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10560 12:30:51.009016 <6>[ 0.683395] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10561 12:30:51.018811 <6>[ 0.692209] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10562 12:30:51.025475 <6>[ 0.700183] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10563 12:30:51.035132 <6>[ 0.708891] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10564 12:30:51.041996 <6>[ 0.718640] TCP: Hash tables configured (established 65536 bind 65536)
10565 12:30:51.048357 <6>[ 0.725498] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10566 12:30:51.058399 <6>[ 0.732698] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10567 12:30:51.065173 <6>[ 0.740394] NET: Registered PF_UNIX/PF_LOCAL protocol family
10568 12:30:51.068246 <6>[ 0.746471] RPC: Registered named UNIX socket transport module.
10569 12:30:51.075150 <6>[ 0.752621] RPC: Registered udp transport module.
10570 12:30:51.078274 <6>[ 0.757552] RPC: Registered tcp transport module.
10571 12:30:51.088217 <6>[ 0.762488] RPC: Registered tcp NFSv4.1 backchannel transport module.
10572 12:30:51.091463 <6>[ 0.769151] PCI: CLS 0 bytes, default 64
10573 12:30:51.094825 <6>[ 0.773570] Unpacking initramfs...
10574 12:30:51.101192 <6>[ 0.777277] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10575 12:30:51.111263 <6>[ 0.785941] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10576 12:30:51.118100 <6>[ 0.794776] kvm [1]: IPA Size Limit: 40 bits
10577 12:30:51.121260 <6>[ 0.799300] kvm [1]: GICv3: no GICV resource entry
10578 12:30:51.124844 <6>[ 0.804322] kvm [1]: disabling GICv2 emulation
10579 12:30:51.131442 <6>[ 0.809012] kvm [1]: GIC system register CPU interface enabled
10580 12:30:51.138230 <6>[ 0.815182] kvm [1]: vgic interrupt IRQ18
10581 12:30:51.140874 <6>[ 0.819545] kvm [1]: VHE mode initialized successfully
10582 12:30:51.148109 <5>[ 0.825958] Initialise system trusted keyrings
10583 12:30:51.154577 <6>[ 0.830759] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10584 12:30:51.163167 <6>[ 0.840803] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10585 12:30:51.169432 <5>[ 0.847193] NFS: Registering the id_resolver key type
10586 12:30:51.172681 <5>[ 0.852505] Key type id_resolver registered
10587 12:30:51.179408 <5>[ 0.856920] Key type id_legacy registered
10588 12:30:51.186562 <6>[ 0.861198] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10589 12:30:51.193251 <6>[ 0.868120] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10590 12:30:51.199865 <6>[ 0.875839] 9p: Installing v9fs 9p2000 file system support
10591 12:30:51.235277 <5>[ 0.913243] Key type asymmetric registered
10592 12:30:51.238984 <5>[ 0.917577] Asymmetric key parser 'x509' registered
10593 12:30:51.248802 <6>[ 0.922721] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10594 12:30:51.252084 <6>[ 0.930338] io scheduler mq-deadline registered
10595 12:30:51.255282 <6>[ 0.935101] io scheduler kyber registered
10596 12:30:51.274074 <6>[ 0.951944] EINJ: ACPI disabled.
10597 12:30:51.306567 <4>[ 0.977338] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 12:30:51.316121 <4>[ 0.987974] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 12:30:51.330389 <6>[ 1.008348] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10600 12:30:51.338253 <6>[ 1.016248] printk: console [ttyS0] disabled
10601 12:30:51.366847 <6>[ 1.040917] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10602 12:30:51.373365 <6>[ 1.050402] printk: console [ttyS0] enabled
10603 12:30:51.376690 <6>[ 1.050402] printk: console [ttyS0] enabled
10604 12:30:51.383019 <6>[ 1.059321] printk: bootconsole [mtk8250] disabled
10605 12:30:51.386348 <6>[ 1.059321] printk: bootconsole [mtk8250] disabled
10606 12:30:51.393313 <6>[ 1.070372] SuperH (H)SCI(F) driver initialized
10607 12:30:51.396552 <6>[ 1.075642] msm_serial: driver initialized
10608 12:30:51.409923 <6>[ 1.084456] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10609 12:30:51.420183 <6>[ 1.093000] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10610 12:30:51.426998 <6>[ 1.101542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10611 12:30:51.436858 <6>[ 1.110170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10612 12:30:51.443587 <6>[ 1.118874] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10613 12:30:51.453379 <6>[ 1.127591] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10614 12:30:51.463103 <6>[ 1.136130] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10615 12:30:51.469491 <6>[ 1.144929] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10616 12:30:51.479280 <6>[ 1.153474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10617 12:30:51.491000 <6>[ 1.168695] loop: module loaded
10618 12:30:51.497394 <6>[ 1.174566] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10619 12:30:51.519714 <4>[ 1.197620] mtk-pmic-keys: Failed to locate of_node [id: -1]
10620 12:30:51.526055 <6>[ 1.204248] megasas: 07.719.03.00-rc1
10621 12:30:51.535984 <6>[ 1.213860] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10622 12:30:51.542967 <6>[ 1.220236] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10623 12:30:51.558746 <6>[ 1.236409] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10624 12:30:51.614815 <6>[ 1.286142] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10625 12:30:53.483546 <6>[ 3.161394] Freeing initrd memory: 55048K
10626 12:30:53.493578 <6>[ 3.171710] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10627 12:30:53.504486 <6>[ 3.182627] tun: Universal TUN/TAP device driver, 1.6
10628 12:30:53.507839 <6>[ 3.188690] thunder_xcv, ver 1.0
10629 12:30:53.511146 <6>[ 3.192194] thunder_bgx, ver 1.0
10630 12:30:53.514889 <6>[ 3.195689] nicpf, ver 1.0
10631 12:30:53.524716 <6>[ 3.199703] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10632 12:30:53.528476 <6>[ 3.207178] hns3: Copyright (c) 2017 Huawei Corporation.
10633 12:30:53.534844 <6>[ 3.212765] hclge is initializing
10634 12:30:53.538086 <6>[ 3.216340] e1000: Intel(R) PRO/1000 Network Driver
10635 12:30:53.544714 <6>[ 3.221469] e1000: Copyright (c) 1999-2006 Intel Corporation.
10636 12:30:53.548102 <6>[ 3.227483] e1000e: Intel(R) PRO/1000 Network Driver
10637 12:30:53.554694 <6>[ 3.232699] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10638 12:30:53.561231 <6>[ 3.238888] igb: Intel(R) Gigabit Ethernet Network Driver
10639 12:30:53.567952 <6>[ 3.244539] igb: Copyright (c) 2007-2014 Intel Corporation.
10640 12:30:53.574457 <6>[ 3.250375] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10641 12:30:53.581164 <6>[ 3.256893] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10642 12:30:53.584936 <6>[ 3.263350] sky2: driver version 1.30
10643 12:30:53.591000 <6>[ 3.268331] VFIO - User Level meta-driver version: 0.3
10644 12:30:53.598406 <6>[ 3.276515] usbcore: registered new interface driver usb-storage
10645 12:30:53.605380 <6>[ 3.282969] usbcore: registered new device driver onboard-usb-hub
10646 12:30:53.614036 <6>[ 3.292086] mt6397-rtc mt6359-rtc: registered as rtc0
10647 12:30:53.623729 <6>[ 3.297565] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:30:41 UTC (1686054641)
10648 12:30:53.626975 <6>[ 3.307143] i2c_dev: i2c /dev entries driver
10649 12:30:53.644017 <6>[ 3.318722] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10650 12:30:53.651151 <6>[ 3.328940] sdhci: Secure Digital Host Controller Interface driver
10651 12:30:53.657790 <6>[ 3.335375] sdhci: Copyright(c) Pierre Ossman
10652 12:30:53.663912 <6>[ 3.340776] Synopsys Designware Multimedia Card Interface Driver
10653 12:30:53.667242 <6>[ 3.347380] mmc0: CQHCI version 5.10
10654 12:30:53.673834 <6>[ 3.347931] sdhci-pltfm: SDHCI platform and OF driver helper
10655 12:30:53.681439 <6>[ 3.359535] ledtrig-cpu: registered to indicate activity on CPUs
10656 12:30:53.692170 <6>[ 3.366964] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10657 12:30:53.695807 <6>[ 3.374365] usbcore: registered new interface driver usbhid
10658 12:30:53.701926 <6>[ 3.380200] usbhid: USB HID core driver
10659 12:30:53.708817 <6>[ 3.384455] spi_master spi0: will run message pump with realtime priority
10660 12:30:53.755063 <6>[ 3.426154] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10661 12:30:53.773885 <6>[ 3.441553] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10662 12:30:53.777242 <6>[ 3.455162] mmc0: Command Queue Engine enabled
10663 12:30:53.784332 <6>[ 3.456739] cros-ec-spi spi0.0: Chrome EC device registered
10664 12:30:53.790948 <6>[ 3.459904] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10665 12:30:53.794106 <6>[ 3.472988] mmcblk0: mmc0:0001 DA4128 116 GiB
10666 12:30:53.809229 <6>[ 3.483997] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10667 12:30:53.816208 <6>[ 3.487305] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10668 12:30:53.822223 <6>[ 3.495481] NET: Registered PF_PACKET protocol family
10669 12:30:53.826105 <6>[ 3.500647] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10670 12:30:53.832717 <6>[ 3.504723] 9pnet: Installing 9P2000 support
10671 12:30:53.835923 <6>[ 3.510478] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10672 12:30:53.842553 <5>[ 3.514382] Key type dns_resolver registered
10673 12:30:53.849277 <6>[ 3.520249] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10674 12:30:53.852471 <6>[ 3.524657] registered taskstats version 1
10675 12:30:53.855553 <5>[ 3.535002] Loading compiled-in X.509 certificates
10676 12:30:53.890613 <4>[ 3.562013] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 12:30:53.900245 <4>[ 3.572713] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10678 12:30:53.910559 <3>[ 3.585530] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10679 12:30:53.923023 <6>[ 3.601054] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 12:30:53.929925 <6>[ 3.607884] xhci-mtk 11200000.usb: xHCI Host Controller
10681 12:30:53.936503 <6>[ 3.613399] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 12:30:53.946815 <6>[ 3.621251] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 12:30:53.952936 <6>[ 3.630678] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 12:30:53.959932 <6>[ 3.636899] xhci-mtk 11200000.usb: xHCI Host Controller
10685 12:30:53.966369 <6>[ 3.642392] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 12:30:53.972879 <6>[ 3.650051] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 12:30:53.979964 <6>[ 3.657933] hub 1-0:1.0: USB hub found
10688 12:30:53.983208 <6>[ 3.661982] hub 1-0:1.0: 1 port detected
10689 12:30:53.992946 <6>[ 3.666339] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 12:30:53.996237 <6>[ 3.675147] hub 2-0:1.0: USB hub found
10691 12:30:53.999633 <6>[ 3.679186] hub 2-0:1.0: 1 port detected
10692 12:30:54.008049 <6>[ 3.686335] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 12:30:54.025473 <6>[ 3.700346] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10694 12:30:54.032421 <6>[ 3.708380] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10695 12:30:54.042270 <4>[ 3.716355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10696 12:30:54.051920 <6>[ 3.726031] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10697 12:30:54.058490 <6>[ 3.734114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10698 12:30:54.065086 <6>[ 3.742153] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10699 12:30:54.075615 <6>[ 3.750079] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10700 12:30:54.081721 <6>[ 3.757907] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10701 12:30:54.092174 <6>[ 3.765736] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10702 12:30:54.101844 <6>[ 3.776441] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10703 12:30:54.108523 <6>[ 3.784838] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10704 12:30:54.118284 <6>[ 3.793210] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10705 12:30:54.128610 <6>[ 3.801554] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10706 12:30:54.134681 <6>[ 3.809897] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10707 12:30:54.144811 <6>[ 3.818240] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10708 12:30:54.151360 <6>[ 3.826583] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10709 12:30:54.161752 <6>[ 3.834926] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10710 12:30:54.168130 <6>[ 3.843268] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10711 12:30:54.177852 <6>[ 3.851610] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10712 12:30:54.185028 <6>[ 3.859954] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10713 12:30:54.194773 <6>[ 3.868296] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10714 12:30:54.201244 <6>[ 3.876639] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10715 12:30:54.211165 <6>[ 3.884983] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10716 12:30:54.217767 <6>[ 3.893331] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10717 12:30:54.224262 <6>[ 3.902254] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10718 12:30:54.231510 <6>[ 3.909707] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10719 12:30:54.238287 <6>[ 3.916749] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10720 12:30:54.245653 <6>[ 3.923850] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10721 12:30:54.256122 <6>[ 3.931140] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10722 12:30:54.263137 <6>[ 3.938150] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10723 12:30:54.272990 <6>[ 3.947316] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10724 12:30:54.282532 <6>[ 3.956444] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10725 12:30:54.292727 <6>[ 3.965745] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10726 12:30:54.302550 <6>[ 3.975220] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10727 12:30:54.309537 <6>[ 3.984694] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10728 12:30:54.319644 <6>[ 3.993828] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10729 12:30:54.329441 <6>[ 4.003302] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10730 12:30:54.339056 <6>[ 4.012450] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10731 12:30:54.349563 <6>[ 4.021753] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10732 12:30:54.359680 <6>[ 4.031920] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10733 12:30:54.369206 <6>[ 4.043922] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10734 12:30:54.390291 <6>[ 4.065119] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10735 12:30:54.419457 <6>[ 4.097312] hub 2-1:1.0: USB hub found
10736 12:30:54.422184 <6>[ 4.101805] hub 2-1:1.0: 3 ports detected
10737 12:30:54.539334 <6>[ 4.217098] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10738 12:30:54.695211 <6>[ 4.373388] hub 1-1:1.0: USB hub found
10739 12:30:54.698429 <6>[ 4.377809] hub 1-1:1.0: 4 ports detected
10740 12:30:54.774439 <6>[ 4.449380] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10741 12:30:55.017929 <6>[ 4.693125] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10742 12:30:55.151230 <6>[ 4.829378] hub 1-1.4:1.0: USB hub found
10743 12:30:55.154402 <6>[ 4.834064] hub 1-1.4:1.0: 2 ports detected
10744 12:30:55.450063 <6>[ 5.125122] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10745 12:30:55.642584 <6>[ 5.317122] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10746 12:31:06.654966 <6>[ 16.337691] ALSA device list:
10747 12:31:06.661490 <6>[ 16.340946] No soundcards found.
10748 12:31:06.674363 <6>[ 16.353372] Freeing unused kernel memory: 8384K
10749 12:31:06.677635 <6>[ 16.358307] Run /init as init process
10750 12:31:06.707563 <6>[ 16.387127] NET: Registered PF_INET6 protocol family
10751 12:31:06.714346 <6>[ 16.393546] Segment Routing with IPv6
10752 12:31:06.717801 <6>[ 16.397511] In-situ OAM (IOAM) with IPv6
10753 12:31:06.749180 <30>[ 16.411722] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10754 12:31:06.756537 <30>[ 16.435564] systemd[1]: Detected architecture arm64.
10755 12:31:06.756984
10756 12:31:06.762976 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10757 12:31:06.763607
10758 12:31:06.777681 <30>[ 16.457227] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10759 12:31:06.920023 <30>[ 16.595671] systemd[1]: Queued start job for default target Graphical Interface.
10760 12:31:06.963437 <30>[ 16.642300] systemd[1]: Created slice system-getty.slice.
10761 12:31:06.969665 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10762 12:31:06.986122 <30>[ 16.665705] systemd[1]: Created slice system-modprobe.slice.
10763 12:31:06.992812 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10764 12:31:07.011451 <30>[ 16.690246] systemd[1]: Created slice system-serial\x2dgetty.slice.
10765 12:31:07.020949 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10766 12:31:07.034528 <30>[ 16.713632] systemd[1]: Created slice User and Session Slice.
10767 12:31:07.040770 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10768 12:31:07.061980 <30>[ 16.737680] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10769 12:31:07.071815 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10770 12:31:07.089254 <30>[ 16.765286] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10771 12:31:07.096082 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10772 12:31:07.116815 <30>[ 16.789187] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10773 12:31:07.123080 <30>[ 16.801214] systemd[1]: Reached target Local Encrypted Volumes.
10774 12:31:07.129339 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10775 12:31:07.145639 <30>[ 16.825184] systemd[1]: Reached target Paths.
10776 12:31:07.149446 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10777 12:31:07.165618 <30>[ 16.845147] systemd[1]: Reached target Remote File Systems.
10778 12:31:07.172609 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10779 12:31:07.190224 <30>[ 16.869402] systemd[1]: Reached target Slices.
10780 12:31:07.196345 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10781 12:31:07.209506 <30>[ 16.889171] systemd[1]: Reached target Swap.
10782 12:31:07.213110 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10783 12:31:07.233247 <30>[ 16.909459] systemd[1]: Listening on initctl Compatibility Named Pipe.
10784 12:31:07.240209 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10785 12:31:07.246680 <30>[ 16.924201] systemd[1]: Listening on Journal Audit Socket.
10786 12:31:07.252832 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10787 12:31:07.266213 <30>[ 16.945421] systemd[1]: Listening on Journal Socket (/dev/log).
10788 12:31:07.272367 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10789 12:31:07.290324 <30>[ 16.969441] systemd[1]: Listening on Journal Socket.
10790 12:31:07.296312 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10791 12:31:07.309802 <30>[ 16.989432] systemd[1]: Listening on udev Control Socket.
10792 12:31:07.316657 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10793 12:31:07.334727 <30>[ 17.013783] systemd[1]: Listening on udev Kernel Socket.
10794 12:31:07.341351 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10795 12:31:07.374347 <30>[ 17.053374] systemd[1]: Mounting Huge Pages File System...
10796 12:31:07.380606 Mounting [0;1;39mHuge Pages File System[0m...
10797 12:31:07.396511 <30>[ 17.075348] systemd[1]: Mounting POSIX Message Queue File System...
10798 12:31:07.403053 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10799 12:31:07.420086 <30>[ 17.099287] systemd[1]: Mounting Kernel Debug File System...
10800 12:31:07.426712 Mounting [0;1;39mKernel Debug File System[0m...
10801 12:31:07.445771 <30>[ 17.121447] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10802 12:31:07.489459 <30>[ 17.165586] systemd[1]: Starting Create list of static device nodes for the current kernel...
10803 12:31:07.496332 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10804 12:31:07.516265 <30>[ 17.195558] systemd[1]: Starting Load Kernel Module configfs...
10805 12:31:07.522821 Starting [0;1;39mLoad Kernel Module configfs[0m...
10806 12:31:07.540013 <30>[ 17.219502] systemd[1]: Starting Load Kernel Module drm...
10807 12:31:07.546823 Starting [0;1;39mLoad Kernel Module drm[0m...
10808 12:31:07.565257 <30>[ 17.241339] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10809 12:31:07.602082 <30>[ 17.281676] systemd[1]: Starting Journal Service...
10810 12:31:07.605369 Starting [0;1;39mJournal Service[0m...
10811 12:31:07.624562 <30>[ 17.303967] systemd[1]: Starting Load Kernel Modules...
10812 12:31:07.630973 Starting [0;1;39mLoad Kernel Modules[0m...
10813 12:31:07.652085 <30>[ 17.327861] systemd[1]: Starting Remount Root and Kernel File Systems...
10814 12:31:07.658258 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10815 12:31:07.676283 <30>[ 17.355632] systemd[1]: Starting Coldplug All udev Devices...
10816 12:31:07.682929 Starting [0;1;39mColdplug All udev Devices[0m...
10817 12:31:07.700953 <30>[ 17.379865] systemd[1]: Mounted Huge Pages File System.
10818 12:31:07.706872 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10819 12:31:07.722212 <30>[ 17.402032] systemd[1]: Started Journal Service.
10820 12:31:07.728712 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10821 12:31:07.743164 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10822 12:31:07.758020 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10823 12:31:07.778180 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10824 12:31:07.796031 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10825 12:31:07.819285 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10826 12:31:07.839295 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10827 12:31:07.863297 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10828 12:31:07.877871 See 'systemctl status systemd-remount-fs.service' for details.
10829 12:31:07.934713 Mounting [0;1;39mKernel Configuration File System[0m...
10830 12:31:07.952586 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10831 12:31:07.970339 <46>[ 17.646356] systemd-journald[174]: Received client request to flush runtime journal.
10832 12:31:07.978854 Starting [0;1;39mLoad/Save Random Seed[0m...
10833 12:31:07.996980 Starting [0;1;39mApply Kernel Variables[0m...
10834 12:31:08.017210 Starting [0;1;39mCreate System Users[0m...
10835 12:31:08.038096 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10836 12:31:08.058246 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10837 12:31:08.070970 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10838 12:31:08.086943 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10839 12:31:08.102842 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10840 12:31:08.119584 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10841 12:31:08.151249 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10842 12:31:08.173267 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10843 12:31:08.190366 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10844 12:31:08.206098 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10845 12:31:08.254268 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10846 12:31:08.281800 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10847 12:31:08.302665 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10848 12:31:08.321996 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10849 12:31:08.343219 Starting [0;1;39mNetwork Time Synchronization[0m...
10850 12:31:08.361095 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10851 12:31:08.402429 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10852 12:31:08.466272 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10853 12:31:08.484585 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10854 12:31:08.505933 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10855 12:31:08.518245 <6>[ 18.194593] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10856 12:31:08.525015 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10857 12:31:08.541502 [[0;32m OK [0m] Reached targ<6>[ 18.220069] remoteproc remoteproc0: scp is available
10858 12:31:08.551426 et [0;1;39mSyst<4>[ 18.226112] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10859 12:31:08.561240 em Time Synchron<6>[ 18.229633] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10860 12:31:08.567994 <6>[ 18.237055] remoteproc remoteproc0: powering up scp
10861 12:31:08.568619 ized[0m.
10862 12:31:08.574846 <6>[ 18.246288] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10863 12:31:08.584591 <4>[ 18.251238] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10864 12:31:08.594512 <3>[ 18.253564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 12:31:08.601292 <3>[ 18.253584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 12:31:08.611448 <3>[ 18.253593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 12:31:08.617795 <6>[ 18.260744] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10868 12:31:08.624085 <3>[ 18.270560] remoteproc remoteproc0: request_firmware failed: -2
10869 12:31:08.634475 <3>[ 18.282465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 12:31:08.640871 <3>[ 18.318001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 12:31:08.651002 [[0;32m OK [<3>[ 18.326687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 12:31:08.657878 <6>[ 18.329001] usbcore: registered new interface driver r8152
10873 12:31:08.667472 0m] Started [0;<3>[ 18.336088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 12:31:08.677546 1;39mDiscard unu<3>[ 18.351058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 12:31:08.678117 sed blocks once a week[0m.
10876 12:31:08.683952 <4>[ 18.362289] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10877 12:31:08.694001 <3>[ 18.369989] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 12:31:08.701952 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10879 12:31:08.708860 <4>[ 18.386995] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10880 12:31:08.718918 <3>[ 18.392838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 12:31:08.725138 <3>[ 18.402614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 12:31:08.731537 <6>[ 18.405587] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10883 12:31:08.741998 <3>[ 18.410790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 12:31:08.748331 <6>[ 18.417631] pci_bus 0000:00: root bus resource [bus 00-ff]
10885 12:31:08.751517 <6>[ 18.427796] mc: Linux media interface: v0.10
10886 12:31:08.757839 <3>[ 18.431266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 12:31:08.767963 <3>[ 18.431319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 12:31:08.774835 <3>[ 18.431333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 12:31:08.784301 <3>[ 18.431348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 12:31:08.791318 <3>[ 18.431367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 12:31:08.798080 <6>[ 18.431599] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10892 12:31:08.807829 <3>[ 18.438226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 12:31:08.814690 <6>[ 18.438297] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10894 12:31:08.824536 <6>[ 18.444204] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10895 12:31:08.831278 <6>[ 18.444274] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10896 12:31:08.841715 <6>[ 18.465788] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10897 12:31:08.849198 <6>[ 18.468485] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10898 12:31:08.855792 <6>[ 18.473128] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10899 12:31:08.866326 <4>[ 18.474793] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10900 12:31:08.869476 <4>[ 18.474793] Fallback method does not support PEC.
10901 12:31:08.879511 <6>[ 18.477221] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10902 12:31:08.885620 <6>[ 18.477939] videodev: Linux video capture interface: v2.00
10903 12:31:08.888975 <6>[ 18.483769] pci 0000:00:00.0: supports D1 D2
10904 12:31:08.898814 <4>[ 18.496154] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10905 12:31:08.905479 <3>[ 18.496313] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:31:08.912181 <6>[ 18.499427] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10907 12:31:08.922433 <6>[ 18.504774] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10908 12:31:08.932356 <4>[ 18.510760] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10909 12:31:08.939026 <6>[ 18.518139] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10910 12:31:08.945601 <6>[ 18.533656] usbcore: registered new interface driver cdc_ether
10911 12:31:08.955848 <3>[ 18.534028] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 12:31:08.962207 <3>[ 18.534861] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10913 12:31:08.969925 <6>[ 18.542041] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10914 12:31:08.976493 <6>[ 18.569388] usbcore: registered new interface driver r8153_ecm
10915 12:31:08.980363 <6>[ 18.571884] Bluetooth: Core ver 2.22
10916 12:31:08.984186 <6>[ 18.571965] NET: Registered PF_BLUETOOTH protocol family
10917 12:31:08.990495 <6>[ 18.571968] Bluetooth: HCI device and connection manager initialized
10918 12:31:08.996867 <6>[ 18.571985] Bluetooth: HCI socket layer initialized
10919 12:31:09.000948 <6>[ 18.571993] Bluetooth: L2CAP socket layer initialized
10920 12:31:09.006945 <6>[ 18.572007] Bluetooth: SCO socket layer initialized
10921 12:31:09.013829 <6>[ 18.573675] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10922 12:31:09.020455 <6>[ 18.615767] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10923 12:31:09.028114 <6>[ 18.624145] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10924 12:31:09.034505 <6>[ 18.624674] r8152 2-1.3:1.0 eth0: v1.12.13
10925 12:31:09.037590 <6>[ 18.631743] usbcore: registered new interface driver btusb
10926 12:31:09.051234 <4>[ 18.632245] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10927 12:31:09.055098 <3>[ 18.632258] Bluetooth: hci0: Failed to load firmware file (-2)
10928 12:31:09.062175 <3>[ 18.632262] Bluetooth: hci0: Failed to set up firmware (-2)
10929 12:31:09.071768 <4>[ 18.632268] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10930 12:31:09.085379 <6>[ 18.632364] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10931 12:31:09.092511 <6>[ 18.632539] usbcore: registered new interface driver uvcvideo
10932 12:31:09.098827 <6>[ 18.638940] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10933 12:31:09.105553 <6>[ 18.642668] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10934 12:31:09.112183 <6>[ 18.648922] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10935 12:31:09.115659 <6>[ 18.654256] pci 0000:01:00.0: supports D1 D2
10936 12:31:09.125550 <3>[ 18.659612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 12:31:09.132330 <3>[ 18.660208] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10938 12:31:09.138846 <6>[ 18.663976] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10939 12:31:09.145696 <6>[ 18.664870] remoteproc remoteproc0: powering up scp
10940 12:31:09.152315 <6>[ 18.677184] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10941 12:31:09.159924 <4>[ 18.681866] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10942 12:31:09.170263 <6>[ 18.686676] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10943 12:31:09.176935 <3>[ 18.691803] remoteproc remoteproc0: request_firmware failed: -2
10944 12:31:09.184133 <6>[ 18.699245] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10945 12:31:09.190856 <3>[ 18.706397] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10946 12:31:09.201053 <3>[ 18.712564] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:31:09.207436 <3>[ 18.713416] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10948 12:31:09.217396 <6>[ 18.713776] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10949 12:31:09.224943 <6>[ 18.713793] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10950 12:31:09.231454 <3>[ 18.741923] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 12:31:09.240807 <6>[ 18.746288] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10952 12:31:09.250921 <3>[ 18.777121] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 12:31:09.254307 <6>[ 18.782596] pci 0000:00:00.0: PCI bridge to [bus 01]
10954 12:31:09.264001 <3>[ 18.810962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 12:31:09.271032 <6>[ 18.816740] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10956 12:31:09.281220 [[0;32m OK [<6>[ 18.956386] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10957 12:31:09.287438 0m] Listening on<6>[ 18.965114] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10958 12:31:09.293974 [0;1;39mD-Bus <6>[ 18.971960] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10959 12:31:09.297265 System Message Bus Socket[0m.
10960 12:31:09.313762 [[0;32m OK [<5>[ 18.990104] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10961 12:31:09.316821 0m] Reached target [0;1;39mSockets[0m.
10962 12:31:09.334838 <5>[ 19.010948] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10963 12:31:09.341002 <4>[ 19.018009] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10964 12:31:09.348093 <6>[ 19.026920] cfg80211: failed to load regulatory.db
10965 12:31:09.354823 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10966 12:31:09.394588 <6>[ 19.071123] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10967 12:31:09.401364 <6>[ 19.078638] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10968 12:31:09.414333 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10969 12:31:09.425267 <6>[ 19.105075] mt7921e 0000:01:00.0: ASIC revision: 79610010
10970 12:31:09.442387 Starting [0;1;39mUser Login Management[0m...
10971 12:31:09.460116 Starting [0;1;39mPermit User Sessions[0m...
10972 12:31:09.479507 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10973 12:31:09.507119 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10974 12:31:09.540288 <4>[ 19.212624] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 12:31:09.650594 <4>[ 19.323476] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10976 12:31:09.692999 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10977 12:31:09.715025 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10978 12:31:09.730335 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10979 12:31:09.749355 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10980 12:31:09.770918 <4>[ 19.443608] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10981 12:31:09.811048 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10982 12:31:09.829357 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10983 12:31:09.835995 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10984 12:31:09.849986 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10985 12:31:09.866223 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10986 12:31:09.890628 <4>[ 19.563726] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10987 12:31:09.912228 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10988 12:31:09.932509 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10989 12:31:09.952417 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10990 12:31:09.974323 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10991 12:31:09.994996 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10992 12:31:10.011405 <4>[ 19.684413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 12:31:10.036124 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10994 12:31:10.082417
10995 12:31:10.083031
10996 12:31:10.085613 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10997 12:31:10.085722
10998 12:31:10.088874 debian-bullseye-arm64 login: root (automatic login)
10999 12:31:10.088976
11000 12:31:10.089067
11001 12:31:10.105678 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11002 12:31:10.105796
11003 12:31:10.112720 The programs included with the Debian GNU/Linux system are free software;
11004 12:31:10.119433 the exact distribution terms for each program are described in the
11005 12:31:10.122608 individual files in /usr/share/doc/*/copyright.
11006 12:31:10.123175
11007 12:31:10.135592 Debian GNU/Linux com<4>[ 19.807791] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 12:31:10.138702 es with ABSOLUTELY NO WARRANTY, to the extent
11009 12:31:10.141930 permitted by applicable law.
11010 12:31:10.143725 Matched prompt #10: / #
11012 12:31:10.145377 Setting prompt string to ['/ #']
11013 12:31:10.146003 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11015 12:31:10.147727 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11016 12:31:10.148398 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11017 12:31:10.148809 Setting prompt string to ['/ #']
11018 12:31:10.149153 Forcing a shell prompt, looking for ['/ #']
11020 12:31:10.199905 / #
11021 12:31:10.200559 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11022 12:31:10.201112 Waiting using forced prompt support (timeout 00:02:30)
11023 12:31:10.205490
11024 12:31:10.206351 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 12:31:10.206983 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11026 12:31:10.207660 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11027 12:31:10.208259 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11028 12:31:10.208839 end: 2 depthcharge-action (duration 00:01:45) [common]
11029 12:31:10.209420 start: 3 lava-test-retry (timeout 00:07:50) [common]
11030 12:31:10.210013 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11031 12:31:10.210545 Using namespace: common
11033 12:31:10.311773 / # #
11034 12:31:10.311925 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11035 12:31:10.312077 <4>[ 19.927073] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 12:31:10.316953 #
11037 12:31:10.317244 Using /lava-10605787
11039 12:31:10.417590 / # export SHELL=/bin/sh
11040 12:31:10.417781 <4>[ 20.047213] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11041 12:31:10.422618 export SHELL=/bin/sh
11043 12:31:10.523249 / # . /lava-10605787/environment
11044 12:31:10.524182 . /lava-10605787/environment<4>[ 20.167036] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11045 12:31:10.528979
11047 12:31:10.630696 / # /lava-10605787/bin/lava-test-runner /lava-10605787/0
11048 12:31:10.631460 Test shell timeout: 10s (minimum of the action and connection timeout)
11049 12:31:10.634270 /lava-10605787/bin/lava-test-runner /lava-10605787/0<4>[ 20.286824] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11050 12:31:10.636283
11051 12:31:10.683665 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.341849] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 10605787_1.5.2.3.1>
11052 12:31:10.684227 diatek
11053 12:31:10.684987 Received signal: <STARTRUN> 0_igt-kms-mediatek 10605787_1.5.2.3.1
11054 12:31:10.685482 Starting test lava.0_igt-kms-mediatek (10605787_1.5.2.3.1)
11055 12:31:10.686048 Skipping test definition patterns.
11056 12:31:10.686820 + cd /lava-10605787/0/tests/0_igt-kms-mediatek
11057 12:31:10.687433 + cat uuid
11058 12:31:10.688026 + UUID=10605787_1.5.2.3.1
11059 12:31:10.688580 + set +x
11060 12:31:10.693208 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic km<8>[ 20.372810] <LAVA_SIGNAL_TESTSET START core_auth>
11061 12:31:10.693998 Received signal: <TESTSET> START core_auth
11062 12:31:10.694523 Starting test_set core_auth
11063 12:31:10.699946 s_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11064 12:31:10.723041 <14>[ 20.402595] [IGT] core_auth: executing
11065 12:31:10.726178 <3>[ 20.406068] mt7921e 0000:01:00.0: hardware init failed
11066 12:31:10.736259 IGT-Version: 1.2<14>[ 20.413302] [IGT] core_auth: starting subtest getclient-simple
11067 12:31:10.742911 7.1-g766edf9 (aa<14>[ 20.420832] [IGT] core_auth: exiting, ret=0
11068 12:31:10.743422 rch64) (Linux: 6.1.31 aarch64)
11069 12:31:10.746196 Starting subtest: getclient-simple
11070 12:31:10.756818 Opened devic<8>[ 20.432790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11071 12:31:10.757200 e: /dev/dri/card0
11072 12:31:10.757770 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11074 12:31:10.762750 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11075 12:31:10.779230 <14>[ 20.459210] [IGT] core_auth: executing
11076 12:31:10.786043 IGT-Version: 1.2<14>[ 20.463823] [IGT] core_auth: starting subtest getclient-master-drop
11077 12:31:10.792475 7.1-g766edf9 (aa<14>[ 20.472006] [IGT] core_auth: exiting, ret=0
11078 12:31:10.795612 rch64) (Linux: 6.1.31 aarch64)
11079 12:31:10.798803 Starting subtest: getclient-master-drop
11080 12:31:10.806059 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11082 12:31:10.809042 Opened <8>[ 20.483305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11083 12:31:10.809153 device: /dev/dri/card0
11084 12:31:10.815802 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11085 12:31:10.830552 <14>[ 20.510459] [IGT] core_auth: executing
11086 12:31:10.837688 IGT-Version: 1.2<14>[ 20.514947] [IGT] core_auth: starting subtest basic-auth
11087 12:31:10.844148 7.1-g766edf9 (aa<14>[ 20.522244] [IGT] core_auth: exiting, ret=0
11088 12:31:10.847421 rch64) (Linux: 6.1.31 aarch64)
11089 12:31:10.847797 Opened device: /dev/dri/card0
11090 12:31:10.857349 Starting subtest:<8>[ 20.533300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11091 12:31:10.857738 basic-auth
11092 12:31:10.858433 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11094 12:31:10.860520 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11095 12:31:10.879819 <14>[ 20.559182] [IGT] core_auth: executing
11096 12:31:10.886378 IGT-Version: 1.2<14>[ 20.563692] [IGT] core_auth: starting subtest many-magics
11097 12:31:10.889643 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11098 12:31:10.892427 Opened device: /dev/dri/card0
11099 12:31:10.896394 Starting subtest: many-magics
11100 12:31:10.899676 Reopening device failed after 1020 opens
11101 12:31:10.902948 <14>[ 20.583953] [IGT] core_auth: exiting, ret=0
11102 12:31:10.909112 [1mSubtest many-magics: SUCCESS (0.013s)[0m
11103 12:31:10.915407 <8>[ 20.594861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11104 12:31:10.916237 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11106 12:31:10.923462 <8>[ 20.603228] <LAVA_SIGNAL_TESTSET STOP>
11107 12:31:10.924275 Received signal: <TESTSET> STOP
11108 12:31:10.924775 Closing test_set core_auth
11109 12:31:10.964027 <14>[ 20.643570] [IGT] core_getclient: executing
11110 12:31:10.970506 IGT-Version: 1.2<14>[ 20.648572] [IGT] core_getclient: exiting, ret=0
11111 12:31:10.973753 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11112 12:31:10.977224 Opened device: /dev/dri/card0
11113 12:31:10.984000 S<8>[ 20.660632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11114 12:31:10.984680 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11116 12:31:10.987094 UCCESS (0.006s)
11117 12:31:11.025531 <14>[ 20.705403] [IGT] core_getstats: executing
11118 12:31:11.032301 IGT-Version: 1.2<14>[ 20.710417] [IGT] core_getstats: exiting, ret=0
11119 12:31:11.035612 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11120 12:31:11.038971 Opened device: /dev/dri/card0
11121 12:31:11.045379 S<8>[ 20.722221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11122 12:31:11.046163 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11124 12:31:11.048491 UCCESS (0.006s)
11125 12:31:11.088279 <14>[ 20.767735] [IGT] core_getversion: executing
11126 12:31:11.094291 IGT-Version: 1.2<14>[ 20.772965] [IGT] core_getversion: exiting, ret=0
11127 12:31:11.097589 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11128 12:31:11.100957 Opened device: /dev/dri/card0
11129 12:31:11.107558 S<8>[ 20.784648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11130 12:31:11.108232 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11132 12:31:11.110945 UCCESS (0.006s)
11133 12:31:11.150276 <14>[ 20.830194] [IGT] core_setmaster_vs_auth: executing
11134 12:31:11.157462 IGT-Version: 1.2<14>[ 20.836079] [IGT] core_setmaster_vs_auth: exiting, ret=0
11135 12:31:11.163974 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11136 12:31:11.164409 Opened device: /dev/dri/card0
11137 12:31:11.173597 S<8>[ 20.848472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11138 12:31:11.174177 UCCESS (0.007s)
11139 12:31:11.174773 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11141 12:31:11.197611 <8>[ 20.877690] <LAVA_SIGNAL_TESTSET START drm_read>
11142 12:31:11.198281 Received signal: <TESTSET> START drm_read
11143 12:31:11.198635 Starting test_set drm_read
11144 12:31:11.220339 <14>[ 20.900233] [IGT] drm_read: executing
11145 12:31:11.226859 IGT-Version: 1.2<14>[ 20.904890] [IGT] drm_read: exiting, ret=77
11146 12:31:11.230164 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11147 12:31:11.233485 Opened device: /dev/dri/card0
11148 12:31:11.240428 N<8>[ 20.916192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11149 12:31:11.241109 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11151 12:31:11.243618 o KMS driver or no outputs, pipes: 8, outputs: 0
11152 12:31:11.246793 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11153 12:31:11.261634 <14>[ 20.941540] [IGT] drm_read: executing
11154 12:31:11.268154 IGT-Version: 1.2<14>[ 20.946121] [IGT] drm_read: exiting, ret=77
11155 12:31:11.272042 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11156 12:31:11.275037 Opened device: /dev/dri/card0
11157 12:31:11.281695 N<8>[ 20.957315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11158 12:31:11.282406 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11160 12:31:11.285413 o KMS driver or no outputs, pipes: 8, outputs: 0
11161 12:31:11.288612 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11162 12:31:11.302651 <14>[ 20.982682] [IGT] drm_read: executing
11163 12:31:11.309546 IGT-Version: 1.2<14>[ 20.987276] [IGT] drm_read: exiting, ret=77
11164 12:31:11.312813 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11165 12:31:11.316121 Opened device: /dev/dri/card0
11166 12:31:11.322698 N<8>[ 20.998555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11167 12:31:11.323428 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11169 12:31:11.326006 o KMS driver or no outputs, pipes: 8, outputs: 0
11170 12:31:11.329286 [1mSubtest empty-block: SKIP (0.000s)[0m
11171 12:31:11.343643 <14>[ 21.023718] [IGT] drm_read: executing
11172 12:31:11.350336 IGT-Version: 1.2<14>[ 21.028292] [IGT] drm_read: exiting, ret=77
11173 12:31:11.354039 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11174 12:31:11.357150 Opened device: /dev/dri/card0
11175 12:31:11.363798 N<8>[ 21.039458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11176 12:31:11.364668 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11178 12:31:11.367104 o KMS driver or no outputs, pipes: 8, outputs: 0
11179 12:31:11.370330 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11180 12:31:11.385432 <14>[ 21.065042] [IGT] drm_read: executing
11181 12:31:11.391848 IGT-Version: 1.2<14>[ 21.069605] [IGT] drm_read: exiting, ret=77
11182 12:31:11.395514 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11183 12:31:11.398615 Opened device: /dev/dri/card0
11184 12:31:11.405195 N<8>[ 21.080718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11185 12:31:11.405736 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11187 12:31:11.408632 o KMS driver or no outputs, pipes: 8, outputs: 0
11188 12:31:11.415218 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11189 12:31:11.426492 <14>[ 21.106653] [IGT] drm_read: executing
11190 12:31:11.433059 IGT-Version: 1.2<14>[ 21.111225] [IGT] drm_read: exiting, ret=77
11191 12:31:11.436357 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11192 12:31:11.439748 Opened device: /dev/dri/card0
11193 12:31:11.446371 N<8>[ 21.122530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11194 12:31:11.446634 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11196 12:31:11.449596 o KMS driver or no outputs, pipes: 8, outputs: 0
11197 12:31:11.455948 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11198 12:31:11.469096 <14>[ 21.149432] [IGT] drm_read: executing
11199 12:31:11.476263 IGT-Version: 1.2<14>[ 21.154162] [IGT] drm_read: exiting, ret=77
11200 12:31:11.479396 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11201 12:31:11.482698 Opened device: /dev/dri/card0
11202 12:31:11.489390 N<8>[ 21.165655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11203 12:31:11.489680 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11205 12:31:11.496173 o KMS driver or no outputs, pipe<8>[ 21.175826] <LAVA_SIGNAL_TESTSET STOP>
11206 12:31:11.496286 s: 8, outputs: 0
11207 12:31:11.496554 Received signal: <TESTSET> STOP
11208 12:31:11.496657 Closing test_set drm_read
11209 12:31:11.502522 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11210 12:31:11.522663 <8>[ 21.202620] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11211 12:31:11.523008 Received signal: <TESTSET> START kms_addfb_basic
11212 12:31:11.523126 Starting test_set kms_addfb_basic
11213 12:31:11.545982 <14>[ 21.225808] [IGT] kms_addfb_basic: executing
11214 12:31:11.552056 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11215 12:31:11.558866 <14>[ 21.235572] [IGT] kms_addfb_basic: starting subtest unused-handle
11216 12:31:11.559008 Opened device: /dev/dri/card0
11217 12:31:11.562218 Starting subtest: unused-handle
11218 12:31:11.568661 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11219 12:31:11.572355 Test requiremen<14>[ 21.252726] [IGT] kms_addfb_basic: exiting, ret=0
11220 12:31:11.579028 t not met in function igt_require_i915, file ../lib/drmtest.c:721:
11221 12:31:11.589044 Test require<8>[ 21.265312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11222 12:31:11.589198 ment: is_i915_device(fd)
11223 12:31:11.589482 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11225 12:31:11.598917 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11226 12:31:11.602208 Test requirement: is_i915_device(fd)
11227 12:31:11.605646 No KMS driver or no outputs, pipes: 8, outputs: 0
11228 12:31:11.612090 <14>[ 21.291379] [IGT] kms_addfb_basic: executing
11229 12:31:11.615619 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11230 12:31:11.622312 <14>[ 21.301050] [IGT] kms_addfb_basic: starting subtest unused-pitches
11231 12:31:11.625565 Opened device: /dev/dri/card0
11232 12:31:11.628953 Starting subtest: unused-pitches
11233 12:31:11.632367 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11234 12:31:11.638979 Test requirement<14>[ 21.318646] [IGT] kms_addfb_basic: exiting, ret=0
11235 12:31:11.645596 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11236 12:31:11.651948 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11238 12:31:11.655126 Test requirem<8>[ 21.330937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11239 12:31:11.655246 ent: is_i915_device(fd)
11240 12:31:11.662155 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11241 12:31:11.665225 Test requirement: is_i915_device(fd)
11242 12:31:11.671594 No KMS driver or no outputs, pipes: 8, outputs: 0
11243 12:31:11.675330 <14>[ 21.357259] [IGT] kms_addfb_basic: executing
11244 12:31:11.682324 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11245 12:31:11.688387 <14>[ 21.366922] [IGT] kms_addfb_basic: starting subtest unused-offsets
11246 12:31:11.692253 Opened device: /dev/dri/card0
11247 12:31:11.695308 Starting subtest: unused-offsets
11248 12:31:11.698619 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11249 12:31:11.705421 Test requirem<14>[ 21.384270] [IGT] kms_addfb_basic: exiting, ret=0
11250 12:31:11.712051 ent not met in function igt_require_i915, file ../lib/drmtest.c:721:
11251 12:31:11.718570 Test requi<8>[ 21.396660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11252 12:31:11.718865 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11254 12:31:11.721625 rement: is_i915_device(fd)
11255 12:31:11.728692 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11256 12:31:11.731928 Test requirement: is_i915_device(fd)
11257 12:31:11.738632 No KMS driver or no outputs, pipes: 8, outputs: 0
11258 12:31:11.741908 <14>[ 21.422201] [IGT] kms_addfb_basic: executing
11259 12:31:11.748252 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11260 12:31:11.755026 <14>[ 21.431541] [IGT] kms_addfb_basic: starting subtest unused-modifier
11261 12:31:11.758466 Opened device: /dev/dri/card0
11262 12:31:11.758592 Starting subtest: unused-modifier
11263 12:31:11.765149 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11264 12:31:11.771704 Test requir<14>[ 21.449312] [IGT] kms_addfb_basic: exiting, ret=0
11265 12:31:11.774795 ement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11266 12:31:11.784890 Test req<8>[ 21.461262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11267 12:31:11.785216 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11269 12:31:11.787985 uirement: is_i915_device(fd)
11270 12:31:11.794784 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11271 12:31:11.797962 Test requirement: is_i915_device(fd)
11272 12:31:11.801165 No KMS driver or no outputs, pipes: 8, outputs: 0
11273 12:31:11.804890 <14>[ 21.486724] [IGT] kms_addfb_basic: executing
11274 12:31:11.811768 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11275 12:31:11.818314 <14>[ 21.496459] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11276 12:31:11.821691 Opened device: /dev/dri/card0
11277 12:31:11.825016 Starting subtest: clobberred-modifier
11278 12:31:11.834685 Test requirement not met in function igt_require_i915, fil<14>[ 21.514594] [IGT] kms_addfb_basic: exiting, ret=77
11279 12:31:11.837868 e ../lib/drmtest.c:721:
11280 12:31:11.841156 Test requirement: is_i915_device(fd)
11281 12:31:11.851735 [1mSubtest clobb<8>[ 21.526773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11282 12:31:11.851999 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11284 12:31:11.855065 erred-modifier: SKIP (0.000s)[0m
11285 12:31:11.861120 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11286 12:31:11.864523 Test requirement: is_i915_device(fd)
11287 12:31:11.871307 Test requirement not met in function igt_require_i91<14>[ 21.552574] [IGT] kms_addfb_basic: executing
11288 12:31:11.874700 5, file ../lib/drmtest.c:721:
11289 12:31:11.884371 Test requirement: is_i915_device(<14>[ 21.562740] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11290 12:31:11.888119 fd)
11291 12:31:11.891149 No KMS driver or no outputs, pipes: 8, outputs: 0
11292 12:31:11.897665 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11293 12:31:11.900993 Opened d<14>[ 21.581360] [IGT] kms_addfb_basic: exiting, ret=77
11294 12:31:11.904265 evice: /dev/dri/card0
11295 12:31:11.907720 Starting subtest: invalid-smem-bo-on-discrete
11296 12:31:11.917933 Test requi<8>[ 21.593751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11297 12:31:11.918571 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11299 12:31:11.924615 rement not met in function igt_require_intel, file ../lib/drmtest.c:716:
11300 12:31:11.927890 Test requirement: is_intel_device(fd)
11301 12:31:11.934523 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11302 12:31:11.941258 Test requirement not met in functio<14>[ 21.619912] [IGT] kms_addfb_basic: executing
11303 12:31:11.944368 n igt_require_i915, file ../lib/drmtest.c:721:
11304 12:31:11.951095 Test requirement<14>[ 21.630176] [IGT] kms_addfb_basic: starting subtest legacy-format
11305 12:31:11.954335 : is_i915_device(fd)
11306 12:31:11.961075 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11307 12:31:11.964642 Test requirement: is_i915_device(fd)
11308 12:31:11.970671 No KMS driver or no outputs, pipes: 8, outputs: 0
11309 12:31:11.973958 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11310 12:31:11.980554 Opened device:<14>[ 21.660326] [IGT] kms_addfb_basic: exiting, ret=0
11311 12:31:11.983817 /dev/dri/card0
11312 12:31:11.984017 Starting subtest: legacy-format
11313 12:31:11.993846 Successfully fuzzed 10000 {bpp<8>[ 21.672168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11314 12:31:11.994422 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11316 12:31:11.997698 , depth} variations
11317 12:31:12.000704 [1mSubtest legacy-format: SUCCESS (0.013s)[0m
11318 12:31:12.007177 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11319 12:31:12.010498 Test requirement: is_i915_device(fd)
11320 12:31:12.017106 Test requirement <14>[ 21.697356] [IGT] kms_addfb_basic: executing
11321 12:31:12.024068 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11322 12:31:12.030374 Test requirement: is_i915_devi<14>[ 21.710339] [IGT] kms_addfb_basic: starting subtest no-handle
11323 12:31:12.034377 ce(fd)
11324 12:31:12.037624 No KMS driver or no outputs, pipes: 8, outputs: 0
11325 12:31:12.046798 IGT-Version: 1.27.1-g766edf9 (aarch64<14>[ 21.724682] [IGT] kms_addfb_basic: exiting, ret=0
11326 12:31:12.046890 ) (Linux: 6.1.31 aarch64)
11327 12:31:12.050701 Opened device: /dev/dri/card0
11328 12:31:12.060365 Starting subtest: no-h<8>[ 21.736822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11329 12:31:12.060504 andle
11330 12:31:12.060776 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11332 12:31:12.063996 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11333 12:31:12.069996 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11334 12:31:12.073378 Test requirement: is_i915_device(fd)
11335 12:31:12.083329 Test requirement not met in function igt_require_i9<14>[ 21.762585] [IGT] kms_addfb_basic: executing
11336 12:31:12.086759 15, file ../lib/drmtest.c:721:
11337 12:31:12.089890 Test requirement: is_i915_device(fd)
11338 12:31:12.096962 No KMS driver or no output<14>[ 21.776021] [IGT] kms_addfb_basic: starting subtest basic
11339 12:31:12.100167 s, pipes: 8, outputs: 0
11340 12:31:12.106492 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11341 12:31:12.110253 Opened <14>[ 21.789943] [IGT] kms_addfb_basic: exiting, ret=0
11342 12:31:12.113758 device: /dev/dri/card0
11343 12:31:12.116303 Starting subtest: basic
11344 12:31:12.122913 [1mSubtest basic: SUCCESS (0.0<8>[ 21.801835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11345 12:31:12.123208 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11347 12:31:12.126185 00s)[0m
11348 12:31:12.133188 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11349 12:31:12.136399 Test requirement: is_i915_device(fd)
11350 12:31:12.142981 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11351 12:31:12.149668 Test requi<14>[ 21.827572] [IGT] kms_addfb_basic: executing
11352 12:31:12.149904 rement: is_i915_device(fd)
11353 12:31:12.156375 No KMS driver or no outputs, pipes: 8, outputs: 0
11354 12:31:12.162777 IGT-Version: 1.27<14>[ 21.841029] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11355 12:31:12.166154 .1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11356 12:31:12.169389 Opened device: /dev/dri/card0
11357 12:31:12.176301 Starting subtest: <14>[ 21.855469] [IGT] kms_addfb_basic: exiting, ret=0
11358 12:31:12.176417 bad-pitch-0
11359 12:31:12.183111 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11360 12:31:12.189237 Test requirement not<8>[ 21.867252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11361 12:31:12.189503 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11363 12:31:12.195949 met in function igt_require_i915, file ../lib/drmtest.c:721:
11364 12:31:12.199228 Test requirement: is_i915_device(fd)
11365 12:31:12.206160 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11366 12:31:12.209373 Test requirement: is_i915_device(fd)
11367 12:31:12.212346 No<14>[ 21.893454] [IGT] kms_addfb_basic: executing
11368 12:31:12.218974 KMS driver or no outputs, pipes: 8, outputs: 0
11369 12:31:12.228952 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: <14>[ 21.906978] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11370 12:31:12.229056 6.1.31 aarch64)
11371 12:31:12.232297 Opened device: /dev/dri/card0
11372 12:31:12.235763 Starting subtest: bad-pitch-32
11373 12:31:12.242164 [1mSubtest bad-<14>[ 21.921671] [IGT] kms_addfb_basic: exiting, ret=0
11374 12:31:12.245736 pitch-32: SUCCESS (0.000s)[0m
11375 12:31:12.255492 Test requirement not met in function igt_require<8>[ 21.933355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11376 12:31:12.255765 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11378 12:31:12.258876 _i915, file ../lib/drmtest.c:721:
11379 12:31:12.262081 Test requirement: is_i915_device(fd)
11380 12:31:12.268863 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11381 12:31:12.272250 Test requirement: is_i915_device(fd)
11382 12:31:12.279093 No KMS driver <14>[ 21.959397] [IGT] kms_addfb_basic: executing
11383 12:31:12.282326 or no outputs, pipes: 8, outputs: 0
11384 12:31:12.292092 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch<14>[ 21.971856] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11385 12:31:12.295415 64)
11386 12:31:12.295524 Opened device: /dev/dri/card0
11387 12:31:12.298925 Starting subtest: bad-pitch-63
11388 12:31:12.308971 [1mSubtest bad-pitch-63: SU<14>[ 21.986258] [IGT] kms_addfb_basic: exiting, ret=0
11389 12:31:12.309065 CCESS (0.000s)[0m
11390 12:31:12.322196 Test requirement not met in function igt_require_i915, file <8>[ 21.998641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11391 12:31:12.322294 ../lib/drmtest.c:721:
11392 12:31:12.322539 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11394 12:31:12.325374 Test requirement: is_i915_device(fd)
11395 12:31:12.331826 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11396 12:31:12.338407 Test requirement: is_i915_device(fd)
11397 12:31:12.345144 No KMS driver or no outputs, pipes: 8, out<14>[ 22.024605] [IGT] kms_addfb_basic: executing
11398 12:31:12.345238 puts: 0
11399 12:31:12.351719 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11400 12:31:12.358080 Opened device: /<14>[ 22.037929] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11401 12:31:12.361910 dev/dri/card0
11402 12:31:12.364599 Starting subtest: bad-pitch-128
11403 12:31:12.371793 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m<14>[ 22.051973] [IGT] kms_addfb_basic: exiting, ret=0
11404 12:31:12.371895
11405 12:31:12.388120 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:7<8>[ 22.063816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11406 12:31:12.388238 21:
11407 12:31:12.388514 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11409 12:31:12.391607 Test requirement: is_i915_device(fd)
11410 12:31:12.397991 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11411 12:31:12.401360 Test requirement: is_i915_device(fd)
11412 12:31:12.404793 No KMS driver or no outputs, pipes: 8, outputs: 0
11413 12:31:12.410938 <14>[ 22.090469] [IGT] kms_addfb_basic: executing
11414 12:31:12.414370 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11415 12:31:12.417566 Opened device: /dev/dri/card0
11416 12:31:12.424422 <14>[ 22.102818] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11417 12:31:12.427538 Starting subtest: bad-pitch-256
11418 12:31:12.431246 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11419 12:31:12.437575 Test requireme<14>[ 22.117345] [IGT] kms_addfb_basic: exiting, ret=0
11420 12:31:12.444199 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11421 12:31:12.450935 Test requir<8>[ 22.129712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11422 12:31:12.451235 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11424 12:31:12.454254 ement: is_i915_device(fd)
11425 12:31:12.460971 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11426 12:31:12.464194 Test requirement: is_i915_device(fd)
11427 12:31:12.470941 No KMS driver or no outputs, pipes: 8, outputs: 0
11428 12:31:12.474487 <14>[ 22.155907] [IGT] kms_addfb_basic: executing
11429 12:31:12.480676 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11430 12:31:12.484084 Opened device: /dev/dri/card0
11431 12:31:12.490693 <14>[ 22.168276] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11432 12:31:12.493967 Starting subtest: bad-pitch-1024
11433 12:31:12.497532 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11434 12:31:12.504001 Test require<14>[ 22.183013] [IGT] kms_addfb_basic: exiting, ret=0
11435 12:31:12.511282 ment not met in function igt_require_i915, file ../lib/drmtest.c:721:
11436 12:31:12.517327 Test requ<8>[ 22.195407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11437 12:31:12.518207 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11439 12:31:12.520596 irement: is_i915_device(fd)
11440 12:31:12.527433 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11441 12:31:12.531133 Test requirement: is_i915_device(fd)
11442 12:31:12.534223 No KMS driver or no outputs, pipes: 8, outputs: 0
11443 12:31:12.541283 <14>[ 22.220442] [IGT] kms_addfb_basic: executing
11444 12:31:12.547559 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11445 12:31:12.548246 Opened device: /dev/dri/card0
11446 12:31:12.554335 <14>[ 22.232734] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11447 12:31:12.557582 Starting subtest: bad-pitch-999
11448 12:31:12.564211 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11449 12:31:12.567751 Test requireme<14>[ 22.247822] [IGT] kms_addfb_basic: exiting, ret=0
11450 12:31:12.573703 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11451 12:31:12.583601 Test requir<8>[ 22.260308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11452 12:31:12.584238 ement: is_i915_device(fd)
11453 12:31:12.585099 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11455 12:31:12.593738 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11456 12:31:12.597029 Test requirement: is_i915_device(fd)
11457 12:31:12.600293 No KMS driver or no outputs, pipes: 8, outputs: 0
11458 12:31:12.603538 <14>[ 22.285287] [IGT] kms_addfb_basic: executing
11459 12:31:12.609998 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11460 12:31:12.613480 Opened device: /dev/dri/card0
11461 12:31:12.620186 <14>[ 22.297387] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11462 12:31:12.623519 Starting subtest: bad-pitch-65536
11463 12:31:12.626694 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11464 12:31:12.633116 Test requi<14>[ 22.312562] [IGT] kms_addfb_basic: exiting, ret=0
11465 12:31:12.640387 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11466 12:31:12.646605 Test re<8>[ 22.324715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11467 12:31:12.647520 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11469 12:31:12.650440 quirement: is_i915_device(fd)
11470 12:31:12.657106 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11471 12:31:12.659826 Test requirement: is_i915_device(fd)
11472 12:31:12.666965 No KMS driver or no outputs, pipes: 8, outputs: 0
11473 12:31:12.670642 <14>[ 22.351097] [IGT] kms_addfb_basic: executing
11474 12:31:12.677091 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11475 12:31:12.679789 Opened device: /dev/dri/card0
11476 12:31:12.686786 <14>[ 22.365874] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11477 12:31:12.693143 Starting subtest: invalid-get-prop-any
11478 12:31:12.699714 [1mSubtest invalid-get-<14>[ 22.378110] [IGT] kms_addfb_basic: exiting, ret=0
11479 12:31:12.700312 prop-any: SUCCESS (0.000s)[0m
11480 12:31:12.713474 Test requirement not met in function igt_require<8>[ 22.390067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11481 12:31:12.714420 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11483 12:31:12.716782 _i915, file ../lib/drmtest.c:721:
11484 12:31:12.720072 Test requirement: is_i915_device(fd)
11485 12:31:12.726222 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11486 12:31:12.729521 Test requirement: is_i915_device(fd)
11487 12:31:12.736272 No KMS driver <14>[ 22.415466] [IGT] kms_addfb_basic: executing
11488 12:31:12.739476 or no outputs, pipes: 8, outputs: 0
11489 12:31:12.745884 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11490 12:31:12.752856 Opened device: /dev/dri/car<14>[ 22.430915] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11491 12:31:12.752945 d0
11492 12:31:12.756050 Starting subtest: invalid-get-prop
11493 12:31:12.766122 [1mSubtest invalid-get-prop<14>[ 22.444078] [IGT] kms_addfb_basic: exiting, ret=0
11494 12:31:12.766245 : SUCCESS (0.000s)[0m
11495 12:31:12.779534 Test requirement not met in function igt_require_i915, f<8>[ 22.456407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11496 12:31:12.779897 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11498 12:31:12.782985 ile ../lib/drmtest.c:721:
11499 12:31:12.786227 Test requirement: is_i915_device(fd)
11500 12:31:12.792920 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11501 12:31:12.796183 Test requirement: is_i915_device(fd)
11502 12:31:12.802918 No KMS driver or no ou<14>[ 22.481294] [IGT] kms_addfb_basic: executing
11503 12:31:12.803151 tputs, pipes: 8, outputs: 0
11504 12:31:12.809553 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11505 12:31:12.819910 Opened device: /dev<14>[ 22.496529] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11506 12:31:12.820655 /dri/card0
11507 12:31:12.823233 Starting subtest: invalid-set-prop-any
11508 12:31:12.829370 [1mSubtest invalid-set-<14>[ 22.508963] [IGT] kms_addfb_basic: exiting, ret=0
11509 12:31:12.833255 prop-any: SUCCESS (0.000s)[0m
11510 12:31:12.846449 Test requirement not met in function igt_require<8>[ 22.521569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11511 12:31:12.847189 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11513 12:31:12.849556 _i915, file ../lib/drmtest.c:721:
11514 12:31:12.852685 Test requirement: is_i915_device(fd)
11515 12:31:12.859568 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11516 12:31:12.862690 Test requirement: is_i915_device(fd)
11517 12:31:12.865913 No KMS driver <14>[ 22.547197] [IGT] kms_addfb_basic: executing
11518 12:31:12.869240 or no outputs, pipes: 8, outputs: 0
11519 12:31:12.876256 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11520 12:31:12.885724 Opened device: /dev/dri/car<14>[ 22.562506] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11521 12:31:12.886326 d0
11522 12:31:12.888912 Starting subtest: invalid-set-prop
11523 12:31:12.895549 [1mSubtest invalid-set-prop<14>[ 22.575661] [IGT] kms_addfb_basic: exiting, ret=0
11524 12:31:12.898843 : SUCCESS (0.000s)[0m
11525 12:31:12.908959 Test requirement not met in function igt_require_i915, f<8>[ 22.587596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11526 12:31:12.910131 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11528 12:31:12.912620 ile ../lib/drmtest.c:721:
11529 12:31:12.915784 Test requirement: is_i915_device(fd)
11530 12:31:12.922366 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11531 12:31:12.925473 Test requirement: is_i915_device(fd)
11532 12:31:12.932137 No KMS driver or no ou<14>[ 22.612984] [IGT] kms_addfb_basic: executing
11533 12:31:12.935733 tputs, pipes: 8, outputs: 0
11534 12:31:12.942032 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11535 12:31:12.945472 Opened device: /dev/dri/card0
11536 12:31:12.952093 <14>[ 22.630484] [IGT] kms_addfb_basic: starting subtest master-rmfb
11537 12:31:12.955473 Starting subtest: master-rmfb
11538 12:31:12.962277 [1mSubtest maste<14>[ 22.639761] [IGT] kms_addfb_basic: exiting, ret=0
11539 12:31:12.962840 r-rmfb: SUCCESS (0.000s)[0m
11540 12:31:12.975699 Test requirement not met in function igt_require_i<8>[ 22.652293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11541 12:31:12.976652 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11543 12:31:12.979086 915, file ../lib/drmtest.c:721:
11544 12:31:12.982299 Test requirement: is_i915_device(fd)
11545 12:31:12.989145 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11546 12:31:12.991949 Test requirement: is_i915_device(fd)
11547 12:31:12.998591 No KMS driver or no outputs, pip<14>[ 22.678200] [IGT] kms_addfb_basic: executing
11548 12:31:13.001932 es: 8, outputs: 0
11549 12:31:13.005293 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11550 12:31:13.008883 Opened device: /dev/dri/card0
11551 12:31:13.021787 <14>[ 22.698499] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11552 12:31:13.028897 Starting subtest<14>[ 22.706427] [IGT] kms_addfb_basic: exiting, ret=0
11553 12:31:13.029325 : addfb25-modifier-no-flag
11554 12:31:13.042053 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000<8>[ 22.718717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11555 12:31:13.042631 s)[0m
11556 12:31:13.043415 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11558 12:31:13.051356 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11559 12:31:13.054652 Test requirement: is_i915_device(fd)
11560 12:31:13.061384 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11561 12:31:13.064604 Test require<14>[ 22.745944] [IGT] kms_addfb_basic: executing
11562 12:31:13.068384 ment: is_i915_device(fd)
11563 12:31:13.074679 No KMS driver or no outputs, pipes: 8, outputs: 0
11564 12:31:13.078499 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11565 12:31:13.081626 Opened device: /dev/dri/card0
11566 12:31:13.087953 <14>[ 22.766021] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11567 12:31:13.091375 Starting subtest: addfb25-bad-modifier
11568 12:31:13.104605 (kms_addfb_basic:424) CRITICAL: Test assertion failure function addfb25_tests, file ../t<14>[ 22.783446] [IGT] kms_addfb_basic: exiting, ret=98
11569 12:31:13.107963 ests/kms_addfb_basic.c:662:
11570 12:31:13.120614 (kms_addfb_basic:424) CRITICAL: Failed assertion: i<8>[ 22.796267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11571 12:31:13.121073 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11573 12:31:13.134129 gt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11574 12:31:13.137354 (kms_addfb_basic:424) CRITICAL: error: 0 != -1
11575 12:31:13.140623 Stack<14>[ 22.822098] [IGT] kms_addfb_basic: executing
11576 12:31:13.143881 trace:
11577 12:31:13.147252 #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11578 12:31:13.150433 #1 [<unknown>+0xb40647e0]
11579 12:31:13.150546 #2 [<unknown>+0xb4066278]
11580 12:31:13.153862 #3 [<unknown>+0xb406167c]
11581 12:31:13.157201 #4 [__libc_start_main+0xe8]
11582 12:31:13.163744 <14>[ 22.841851] [IGT] kms_addfb_basic: exiting, ret=77
11583 12:31:13.163833 #5 [<unknown>+0xb40616b4]
11584 12:31:13.167098 #6 [<unknown>+0xb40616b4]
11585 12:31:13.177240 Subtest addfb25-bad-mo<8>[ 22.853703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11586 12:31:13.177512 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11588 12:31:13.180278 difier failed.
11589 12:31:13.180367 **** DEBUG ****
11590 12:31:13.190602 (kms_addfb_basic:424) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11591 12:31:13.200428 (kms_addfb_basic:424) CRITICAL: Test assertion failure function addfb25_tests, f<14>[ 22.880470] [IGT] kms_addfb_basic: executing
11592 12:31:13.203793 ile ../tests/kms_addfb_basic.c:662:
11593 12:31:13.220657 (kms_addfb_basic:424) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((<14>[ 22.900454] [IGT] kms_addfb_basic: exiting, ret=77
11594 12:31:13.227397 ((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11595 12:31:13.237225 (kms_addfb_ba<8>[ 22.913197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11596 12:31:13.238105 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11598 12:31:13.240318 sic:424) CRITICAL: error: 0 != -1
11599 12:31:13.243635 (kms_addfb_basic:424) igt_core-INFO: Stack trace:
11600 12:31:13.250151 (kms_addfb_basic:424) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11601 12:31:13.260551 (kms_addfb_basic:424) igt_core-INFO: #1 [<unknown><14>[ 22.939720] [IGT] kms_addfb_basic: executing
11602 12:31:13.261099 +0xb40647e0]
11603 12:31:13.266663 (kms_addfb_basic:424) igt_core-INFO: #2 [<unknown>+0xb4066278]
11604 12:31:13.273528 (kms_addfb_basic:424) igt_core-INFO: #3 [<unknown>+0xb406167c]
11605 12:31:13.279965 (kms_addfb_basic:424) igt_core<14>[ 22.959900] [IGT] kms_addfb_basic: exiting, ret=77
11606 12:31:13.283272 -INFO: #4 [__libc_start_main+0xe8]
11607 12:31:13.296514 (kms_addfb_basic:424) igt_core-INFO: #5 <8>[ 22.972050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11608 12:31:13.297323 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11610 12:31:13.300344 [<unknown>+0xb40616b4]
11611 12:31:13.303403 (kms_addfb_basic:424) igt_core-INFO: #6 [<unknown>+0xb40616b4]
11612 12:31:13.306710 **** END ****
11613 12:31:13.309851 [1mSubtest addfb25-bad-modifier: FAIL (0.009s)[0m
11614 12:31:13.319735 Test requirement not met in function igt_require<14>[ 22.998778] [IGT] kms_addfb_basic: executing
11615 12:31:13.323021 _i915, file ../lib/drmtest.c:721:
11616 12:31:13.326980 Test requirement: is_i915_device(fd)
11617 12:31:13.332778 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11618 12:31:13.339503 Test requirement: is<14>[ 23.019031] [IGT] kms_addfb_basic: exiting, ret=77
11619 12:31:13.339589 _i915_device(fd)
11620 12:31:13.346640 No KMS driver or no outputs, pipes: 8, outputs: 0
11621 12:31:13.353060 IGT-Version<8>[ 23.030887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11622 12:31:13.353335 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11624 12:31:13.359407 : 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11625 12:31:13.359490 Opened device: /dev/dri/card0
11626 12:31:13.369810 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11627 12:31:13.373193 Test requirement: is_i915_device(fd)
11628 12:31:13.379691 [1mSubtest addfb25<14>[ 23.057511] [IGT] kms_addfb_basic: executing
11629 12:31:13.383062 -x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11630 12:31:13.389710 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11631 12:31:13.392945 Test requirement: is_i915_device(fd)
11632 12:31:13.399456 No KMS dri<14>[ 23.078308] [IGT] kms_addfb_basic: exiting, ret=77
11633 12:31:13.402843 ver or no outputs, pipes: 8, outputs: 0
11634 12:31:13.413006 IGT-Version: 1.27.1-g766edf9 (aarch64) <8>[ 23.089980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11635 12:31:13.413294 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11637 12:31:13.416539 (Linux: 6.1.31 aarch64)
11638 12:31:13.419633 Opened device: /dev/dri/card0
11639 12:31:13.426508 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11640 12:31:13.429744 Test requirement: is_i915_device(fd)
11641 12:31:13.436344 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000<14>[ 23.117108] [IGT] kms_addfb_basic: executing
11642 12:31:13.439833 s)[0m
11643 12:31:13.446319 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11644 12:31:13.449696 Test requirement: is_i915_device(fd)
11645 12:31:13.459356 No KMS driver or no outputs, pipes: 8, outputs:<14>[ 23.138017] [IGT] kms_addfb_basic: exiting, ret=77
11646 12:31:13.459800 0
11647 12:31:13.463044 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11648 12:31:13.473001 Opened devic<8>[ 23.149804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11649 12:31:13.473948 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11651 12:31:13.476305 e: /dev/dri/card0
11652 12:31:13.483173 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11653 12:31:13.486560 Test requirement: is_i915_device(fd)
11654 12:31:13.489309 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11655 12:31:13.496014 Test requirement n<14>[ 23.176258] [IGT] kms_addfb_basic: executing
11656 12:31:13.503223 ot met in function igt_require_i915, file ../lib/drmtest.c:721:
11657 12:31:13.506042 Test requirement: is_i915_device(fd)
11658 12:31:13.509307 No KMS driver or no outputs, pipes: 8, outputs: 0
11659 12:31:13.516700 IGT-Version: 1.27.1-g7<14>[ 23.197022] [IGT] kms_addfb_basic: exiting, ret=77
11660 12:31:13.519638 66edf9 (aarch64) (Linux: 6.1.31 aarch64)
11661 12:31:13.522934 Opened device: /dev/dri/card0
11662 12:31:13.532966 Test re<8>[ 23.208536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11663 12:31:13.533750 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11665 12:31:13.539686 quirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11666 12:31:13.542957 Test requirement: is_i915_device(fd)
11667 12:31:13.549685 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11668 12:31:13.556259 Test requirement: is_i915_d<14>[ 23.235541] [IGT] kms_addfb_basic: executing
11669 12:31:13.556355 evice(fd)
11670 12:31:13.562421 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11671 12:31:13.565728 No KMS driver or no outputs, pipes: 8, outputs: 0
11672 12:31:13.575914 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64<14>[ 23.256171] [IGT] kms_addfb_basic: exiting, ret=77
11673 12:31:13.576015 )
11674 12:31:13.579063 Opened device: /dev/dri/card0
11675 12:31:13.589294 Test requirement not met in function igt_requi<8>[ 23.267641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11676 12:31:13.589996 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11678 12:31:13.592708 re_i915, file ../lib/drmtest.c:721:
11679 12:31:13.596280 Test requirement: is_i915_device(fd)
11680 12:31:13.602510 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11681 12:31:13.605919 Test requirement: is_i915_device(fd)
11682 12:31:13.613114 [1mSubtest framebuffer-vs-s<14>[ 23.293419] [IGT] kms_addfb_basic: executing
11683 12:31:13.616181 et-tiling: SKIP (0.000s)[0m
11684 12:31:13.622593 No KMS driver or no outputs, pipes: 8, outputs: 0
11685 12:31:13.625700 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11686 12:31:13.629462 Opened device: /dev/dri/card0
11687 12:31:13.635738 <14>[ 23.314186] [IGT] kms_addfb_basic: exiting, ret=77
11688 12:31:13.648996 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721<8>[ 23.326198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11689 12:31:13.649577 :
11690 12:31:13.650335 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11692 12:31:13.652329 Test requirement: is_i915_device(fd)
11693 12:31:13.659012 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11694 12:31:13.662411 Test requirement: is_i915_device(fd)
11695 12:31:13.672258 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)<14>[ 23.350614] [IGT] kms_addfb_basic: executing
11696 12:31:13.672820 [0m
11697 12:31:13.675418 No KMS driver or no outputs, pipes: 8, outputs: 0
11698 12:31:13.682486 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11699 12:31:13.685769 Opened device: /dev/dri/card0
11700 12:31:13.692407 Test requirement not met<14>[ 23.370924] [IGT] kms_addfb_basic: exiting, ret=77
11701 12:31:13.695655 in function igt_require_i915, file ../lib/drmtest.c:721:
11702 12:31:13.705435 Test requirement: is_<8>[ 23.382927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11703 12:31:13.706015 i915_device(fd)
11704 12:31:13.706803 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11706 12:31:13.712483 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11707 12:31:13.715971 Test requirement: is_i915_device(fd)
11708 12:31:13.722376 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11709 12:31:13.729180 No KMS driver or <14>[ 23.407595] [IGT] kms_addfb_basic: executing
11710 12:31:13.732333 no outputs, pipes: 8, outputs: 0
11711 12:31:13.735572 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11712 12:31:13.738884 Opened device: /dev/dri/card0
11713 12:31:13.748662 Test requirement not met in function igt_requir<14>[ 23.427809] [IGT] kms_addfb_basic: exiting, ret=77
11714 12:31:13.752035 e_i915, file ../lib/drmtest.c:721:
11715 12:31:13.755607 Test requirement: is_i915_device(fd)
11716 12:31:13.762087 Test r<8>[ 23.439566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11717 12:31:13.762933 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11719 12:31:13.768728 equirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11720 12:31:13.771946 Test requirement: is_i915_device(fd)
11721 12:31:13.775216 No KMS driver or no outputs, pipes: 8, outputs: 0
11722 12:31:13.778621 [1mSubtest size-max: SKIP (0.000s)[0m
11723 12:31:13.785492 I<14>[ 23.464410] [IGT] kms_addfb_basic: executing
11724 12:31:13.791737 GT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11725 12:31:13.792281 Opened device: /dev/dri/card0
11726 12:31:13.801450 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11727 12:31:13.804864 <14>[ 23.484756] [IGT] kms_addfb_basic: exiting, ret=77
11728 12:31:13.805530
11729 12:31:13.808310 Test requirement: is_i915_device(fd)
11730 12:31:13.818030 Test requirement not met in function igt_<8>[ 23.496490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11731 12:31:13.818980 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11733 12:31:13.821442 require_i915, file ../lib/drmtest.c:721:
11734 12:31:13.824855 Test requirement: is_i915_device(fd)
11735 12:31:13.831934 No KMS driver or no outputs, pipes: 8, outputs: 0
11736 12:31:13.835006 [1mSubtest too-wide: SKIP (0.000s)[0m
11737 12:31:13.841261 IGT-Version: 1.27.1-g766edf9 (aarch6<14>[ 23.521372] [IGT] kms_addfb_basic: executing
11738 12:31:13.844667 4) (Linux: 6.1.31 aarch64)
11739 12:31:13.848450 Opened device: /dev/dri/card0
11740 12:31:13.855165 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11741 12:31:13.861309 Test requirement: is_i915_device(f<14>[ 23.541409] [IGT] kms_addfb_basic: exiting, ret=77
11742 12:31:13.861914 d)
11743 12:31:13.877841 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<8>[ 23.553292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11744 12:31:13.878480 :721:
11745 12:31:13.879294 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11747 12:31:13.881045 Test requirement: is_i915_device(fd)
11748 12:31:13.884562 No KMS driver or no outputs, pipes: 8, outputs: 0
11749 12:31:13.887809 [1mSubtest too-high: SKIP (0.000s)[0m
11750 12:31:13.894723 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11751 12:31:13.901276 Opened <14>[ 23.579417] [IGT] kms_addfb_basic: executing
11752 12:31:13.901870 device: /dev/dri/card0
11753 12:31:13.907762 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11754 12:31:13.911186 Test requirement: is_i915_device(fd)
11755 12:31:13.921180 Test requirement not met in fun<14>[ 23.599717] [IGT] kms_addfb_basic: exiting, ret=77
11756 12:31:13.924610 ction igt_require_i915, file ../lib/drmtest.c:721:
11757 12:31:13.934385 Test requirement: is_i915_de<8>[ 23.611320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11758 12:31:13.934850 vice(fd)
11759 12:31:13.935529 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11761 12:31:13.941032 No KMS driver or no outputs, pipes: 8, outputs: 0
11762 12:31:13.944077 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11763 12:31:13.950907 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11764 12:31:13.954165 Opened device: /dev/dri/card0
11765 12:31:13.957511 Test re<14>[ 23.637456] [IGT] kms_addfb_basic: executing
11766 12:31:13.963981 quirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11767 12:31:13.967124 Test requirement: is_i915_device(fd)
11768 12:31:13.977066 Test requirement not met in function igt_require_i915, file ..<14>[ 23.657537] [IGT] kms_addfb_basic: exiting, ret=77
11769 12:31:13.980424 /lib/drmtest.c:721:
11770 12:31:13.983901 Test requirement: is_i915_device(fd)
11771 12:31:13.993846 No KMS driver or no o<8>[ 23.669291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11772 12:31:13.994537 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11774 12:31:13.997020 utputs, pipes: 8, outputs: 0
11775 12:31:14.000127 [1mSubtest small-bo: SKIP (0.000s)[0m
11776 12:31:14.003895 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11777 12:31:14.007060 Opened device: /dev/dri/card0
11778 12:31:14.017149 Test requirement not met in function igt_r<14>[ 23.695502] [IGT] kms_addfb_basic: executing
11779 12:31:14.020440 equire_i915, file ../lib/drmtest.c:721:
11780 12:31:14.023636 Test requirement: is_i915_device(fd)
11781 12:31:14.030148 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11782 12:31:14.036873 Test requireme<14>[ 23.715598] [IGT] kms_addfb_basic: exiting, ret=77
11783 12:31:14.037189 nt: is_i915_device(fd)
11784 12:31:14.043178 No KMS driver or no outputs, pipes: 8, outputs: 0
11785 12:31:14.049625 [1mS<8>[ 23.727679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11786 12:31:14.049986 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11788 12:31:14.056796 ubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11789 12:31:14.063078 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11790 12:31:14.063212 Opened device: /dev/dri/card0
11791 12:31:14.073034 Test requirement not met in function igt_require_i915, file<14>[ 23.753870] [IGT] kms_addfb_basic: executing
11792 12:31:14.076828 ../lib/drmtest.c:721:
11793 12:31:14.080177 Test requirement: is_i915_device(fd)
11794 12:31:14.086494 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11795 12:31:14.093403 Test requirement: is_i915_devic<14>[ 23.774187] [IGT] kms_addfb_basic: exiting, ret=77
11796 12:31:14.096821 e(fd)
11797 12:31:14.100150 No KMS driver or no outputs, pipes: 8, outputs: 0
11798 12:31:14.109740 [1mSubtest addfb25-y-<8>[ 23.785860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11799 12:31:14.110462 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11801 12:31:14.113457 tiled-legacy: SKIP (0.000s)[0m
11802 12:31:14.116664 <8>[ 23.795707] <LAVA_SIGNAL_TESTSET STOP>
11803 12:31:14.117130
11804 12:31:14.117837 Received signal: <TESTSET> STOP
11805 12:31:14.118190 Closing test_set kms_addfb_basic
11806 12:31:14.122626 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11807 12:31:14.122720 Opened device: /dev/dri/card0
11808 12:31:14.129864 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11809 12:31:14.133349 Test requirement: is_i915_device(fd)
11810 12:31:14.142822 Test requirement not met in function ig<8>[ 23.822167] <LAVA_SIGNAL_TESTSET START kms_atomic>
11811 12:31:14.143100 Received signal: <TESTSET> START kms_atomic
11812 12:31:14.143184 Starting test_set kms_atomic
11813 12:31:14.146182 t_require_i915, file ../lib/drmtest.c:721:
11814 12:31:14.149574 Test requirement: is_i915_device(fd)
11815 12:31:14.155877 No KMS driver or no outputs, pipes: 8, outputs: 0
11816 12:31:14.159088 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11817 12:31:14.166242 IGT-Version: 1.27.1<14>[ 23.845098] [IGT] kms_atomic: executing
11818 12:31:14.172735 -g766edf9 (aarch<14>[ 23.851068] [IGT] kms_atomic: exiting, ret=77
11819 12:31:14.172907 64) (Linux: 6.1.31 aarch64)
11820 12:31:14.175904 Opened device: /dev/dri/card0
11821 12:31:14.186011 Test requirement not<8>[ 23.862494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11822 12:31:14.186659 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11824 12:31:14.192871 met in function igt_require_i915, file ../lib/drmtest.c:721:
11825 12:31:14.196282 Test requirement: is_i915_device(fd)
11826 12:31:14.202953 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11827 12:31:14.209573 Test requirement: is_i91<14>[ 23.888462] [IGT] kms_atomic: executing
11828 12:31:14.210118 5_device(fd)
11829 12:31:14.216274 No<14>[ 23.894216] [IGT] kms_atomic: exiting, ret=77
11830 12:31:14.219367 KMS driver or no outputs, pipes: 8, outputs: 0
11831 12:31:14.229080 [1mSubtest addfb25-y-tiled-sma<8>[ 23.905830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11832 12:31:14.229983 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11834 12:31:14.232376 ll-legacy: SKIP (0.000s)[0m
11835 12:31:14.236116 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11836 12:31:14.239383 Opened device: /dev/dri/card0
11837 12:31:14.245647 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11838 12:31:14.252333 <14>[ 23.931422] [IGT] kms_atomic: executing
11839 12:31:14.259241 Test requirement<14>[ 23.937307] [IGT] kms_atomic: exiting, ret=77
11840 12:31:14.259703 : is_i915_device(fd)
11841 12:31:14.272217 Test requirement not met in function igt_require_i915, fil<8>[ 23.948555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11842 12:31:14.272953 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11844 12:31:14.275435 e ../lib/drmtest.c:721:
11845 12:31:14.278574 Test requirement: is_i915_device(fd)
11846 12:31:14.281871 No KMS driver or no outputs, pipes: 8, outputs: 0
11847 12:31:14.288549 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11848 12:31:14.295277 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux:<14>[ 23.975707] [IGT] kms_atomic: executing
11849 12:31:14.301898 6.1.31 aarch64)<14>[ 23.981536] [IGT] kms_atomic: exiting, ret=77
11850 12:31:14.302331
11851 12:31:14.305414 Opened device: /dev/dri/card0
11852 12:31:14.315162 No KMS driver or no outputs, pipes: 8, outputs:<8>[ 23.992821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11853 12:31:14.315690 0
11854 12:31:14.316347 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11856 12:31:14.321678 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11857 12:31:14.325564 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11858 12:31:14.328730 Opened device: /dev/dri/card0
11859 12:31:14.335212 No KMS driver or no outputs, pipes: 8, outputs: 0
11860 12:31:14.338342 [1mS<14>[ 24.018661] [IGT] kms_atomic: executing
11861 12:31:14.345142 ubtest plane-pri<14>[ 24.024437] [IGT] kms_atomic: exiting, ret=77
11862 12:31:14.348537 mary-legacy: SKIP (0.000s)[0m
11863 12:31:14.358353 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<8>[ 24.035724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11864 12:31:14.358853 .1.31 aarch64)
11865 12:31:14.359450 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11867 12:31:14.362010 Opened device: /dev/dri/card0
11868 12:31:14.368385 No KMS driver or no outputs, pipes: 8, outputs: 0
11869 12:31:14.372007 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11870 12:31:14.381934 IGT-Version: 1.27.1-g766edf9 (aarch64) (Lin<14>[ 24.060865] [IGT] kms_atomic: executing
11871 12:31:14.388338 ux: 6.1.31 aarch<14>[ 24.066403] [IGT] kms_atomic: exiting, ret=77
11872 12:31:14.388778 64)
11873 12:31:14.391537 Opened device: /dev/dri/card0
11874 12:31:14.401292 No KMS driver or no outputs, pipes: 8, outpu<8>[ 24.077957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11875 12:31:14.401757 ts: 0
11876 12:31:14.402478 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11878 12:31:14.407928 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11879 12:31:14.411146 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11880 12:31:14.414639 Opened device: /dev/dri/card0
11881 12:31:14.418375 No KMS driver or no outputs, pipes: 8, outputs: 0
11882 12:31:14.424938 [<14>[ 24.103864] [IGT] kms_atomic: executing
11883 12:31:14.431439 1mSubtest test-o<14>[ 24.109579] [IGT] kms_atomic: exiting, ret=77
11884 12:31:14.431883 nly: SKIP (0.000s)[0m
11885 12:31:14.444541 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aa<8>[ 24.120801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11886 12:31:14.444829 rch64)
11887 12:31:14.445261 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11889 12:31:14.447778 Opened device: /dev/dri/card0
11890 12:31:14.450964 No KMS driver or no outputs, pipes: 8, outputs: 0
11891 12:31:14.457414 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11892 12:31:14.460757 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11893 12:31:14.467877 Op<14>[ 24.146768] [IGT] kms_atomic: executing
11894 12:31:14.470937 ened device: /de<14>[ 24.152316] [IGT] kms_atomic: exiting, ret=77
11895 12:31:14.474342 v/dri/card0
11896 12:31:14.477538 No KMS driver or no outputs, pipes: 8, outputs: 0
11897 12:31:14.487087 [1mSubtest plan<8>[ 24.164010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11898 12:31:14.487352 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11900 12:31:14.490830 e-invalid-params: SKIP (0.000s)[0m
11901 12:31:14.497324 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11902 12:31:14.500449 Opened device: /dev/dri/card0
11903 12:31:14.503750 No KMS driver or no outputs, pipes: 8, outputs: 0
11904 12:31:14.511009 [1mSubtest plane-invalid<14>[ 24.190392] [IGT] kms_atomic: executing
11905 12:31:14.517585 -params-fence: S<14>[ 24.195868] [IGT] kms_atomic: exiting, ret=77
11906 12:31:14.517709 KIP (0.000s)[0m
11907 12:31:14.530607 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)<8>[ 24.207472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11908 12:31:14.530749
11909 12:31:14.531041 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11911 12:31:14.533829 Opened device: /dev/dri/card0
11912 12:31:14.537201 No KMS driver or no outputs, pipes: 8, outputs: 0
11913 12:31:14.543376 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11914 12:31:14.553049 <14>[ 24.233234] [IGT] kms_atomic: executing
11915 12:31:14.560061 IGT-Version: 1.2<14>[ 24.238055] [IGT] kms_atomic: exiting, ret=77
11916 12:31:14.563268 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11917 12:31:14.566744 Opened device: /dev/dri/card0
11918 12:31:14.573307 N<8>[ 24.249662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11919 12:31:14.573575 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11921 12:31:14.576540 o KMS driver or no outputs, pipes: 8, outputs: 0
11922 12:31:14.582894 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11923 12:31:14.595515 <14>[ 24.275951] [IGT] kms_atomic: executing
11924 12:31:14.602114 IGT-Version: 1.2<14>[ 24.280676] [IGT] kms_atomic: exiting, ret=77
11925 12:31:14.605705 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11926 12:31:14.608830 Opened device: /dev/dri/card0
11927 12:31:14.615755 N<8>[ 24.292325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11928 12:31:14.616014 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11930 12:31:14.618995 o KMS driver or no outputs, pipes: 8, outputs: 0
11931 12:31:14.625017 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11932 12:31:14.637648 <14>[ 24.318204] [IGT] kms_atomic: executing
11933 12:31:14.644392 IGT-Version: 1.2<14>[ 24.322933] [IGT] kms_atomic: exiting, ret=77
11934 12:31:14.647653 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11935 12:31:14.650710 Opened device: /dev/dri/card0
11936 12:31:14.657517 N<8>[ 24.334568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11937 12:31:14.657782 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11939 12:31:14.664578 o KMS driver or no outputs, pipe<8>[ 24.344952] <LAVA_SIGNAL_TESTSET STOP>
11940 12:31:14.664838 Received signal: <TESTSET> STOP
11941 12:31:14.664911 Closing test_set kms_atomic
11942 12:31:14.667391 s: 8, outputs: 0
11943 12:31:14.670577 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11944 12:31:14.691026 <8>[ 24.371567] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11945 12:31:14.691350 Received signal: <TESTSET> START kms_flip_event_leak
11946 12:31:14.691478 Starting test_set kms_flip_event_leak
11947 12:31:14.714949 <14>[ 24.395230] [IGT] kms_flip_event_leak: executing
11948 12:31:14.721985 IGT-Version: 1.2<14>[ 24.401096] [IGT] kms_flip_event_leak: exiting, ret=77
11949 12:31:14.725192 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11950 12:31:14.728386 Opened device: /dev/dri/card0
11951 12:31:14.734770 N<8>[ 24.413434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11952 12:31:14.735069 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11954 12:31:14.741369 o KMS driver or no outputs, pipe<8>[ 24.422654] <LAVA_SIGNAL_TESTSET STOP>
11955 12:31:14.741660 Received signal: <TESTSET> STOP
11956 12:31:14.741759 Closing test_set kms_flip_event_leak
11957 12:31:14.744616 s: 8, outputs: 0
11958 12:31:14.747980 [1mSubtest basic: SKIP (0.000s)[0m
11959 12:31:14.767922 <8>[ 24.448258] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11960 12:31:14.768235 Received signal: <TESTSET> START kms_prop_blob
11961 12:31:14.768340 Starting test_set kms_prop_blob
11962 12:31:14.791627 <14>[ 24.471795] [IGT] kms_prop_blob: executing
11963 12:31:14.798093 IGT-Version: 1.2<14>[ 24.476752] [IGT] kms_prop_blob: starting subtest basic
11964 12:31:14.804564 7.1-g766edf9 (aa<14>[ 24.483838] [IGT] kms_prop_blob: exiting, ret=0
11965 12:31:14.808162 rch64) (Linux: 6.1.31 aarch64)
11966 12:31:14.811081 Opened device: /dev/dri/card0
11967 12:31:14.818107 Starting subtest:<8>[ 24.495591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11968 12:31:14.818210 basic
11969 12:31:14.818459 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11971 12:31:14.821345 [1mSubtest basic: SUCCESS (0.000s)[0m
11972 12:31:14.839785 <14>[ 24.520455] [IGT] kms_prop_blob: executing
11973 12:31:14.846436 IGT-Version: 1.2<14>[ 24.525374] [IGT] kms_prop_blob: starting subtest blob-prop-core
11974 12:31:14.853064 7.1-g766edf9 (aa<14>[ 24.533055] [IGT] kms_prop_blob: exiting, ret=0
11975 12:31:14.856411 rch64) (Linux: 6.1.31 aarch64)
11976 12:31:14.859642 Opened device: /dev/dri/card0
11977 12:31:14.866745 Starting subtest:<8>[ 24.545070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11978 12:31:14.867039 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11980 12:31:14.870007 blob-prop-core
11981 12:31:14.873208 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11982 12:31:14.890114 <14>[ 24.570620] [IGT] kms_prop_blob: executing
11983 12:31:14.896681 IGT-Version: 1.2<14>[ 24.575446] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11984 12:31:14.903796 7.1-g766edf9 (aa<14>[ 24.583602] [IGT] kms_prop_blob: exiting, ret=0
11985 12:31:14.907162 rch64) (Linux: 6.1.31 aarch64)
11986 12:31:14.910232 Opened device: /dev/dri/card0
11987 12:31:14.919975 Starting subtest:<8>[ 24.595414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11988 12:31:14.920097 blob-prop-validate
11989 12:31:14.920370 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11991 12:31:14.926285 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
11992 12:31:14.940798 <14>[ 24.621311] [IGT] kms_prop_blob: executing
11993 12:31:14.947366 IGT-Version: 1.2<14>[ 24.626153] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
11994 12:31:14.953957 7.1-g766edf9 (aa<14>[ 24.634241] [IGT] kms_prop_blob: exiting, ret=0
11995 12:31:14.957270 rch64) (Linux: 6.1.31 aarch64)
11996 12:31:14.960638 Opened device: /dev/dri/card0
11997 12:31:14.967370 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
11999 12:31:14.970459 Starting subtest:<8>[ 24.646110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12000 12:31:14.970569 blob-prop-lifetime
12001 12:31:14.977014 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12002 12:31:14.992280 <14>[ 24.672520] [IGT] kms_prop_blob: executing
12003 12:31:14.998919 IGT-Version: 1.2<14>[ 24.677482] [IGT] kms_prop_blob: starting subtest blob-multiple
12004 12:31:15.005552 7.1-g766edf9 (aa<14>[ 24.685233] [IGT] kms_prop_blob: exiting, ret=0
12005 12:31:15.008859 rch64) (Linux: 6.1.31 aarch64)
12006 12:31:15.012014 Opened device: /dev/dri/card0
12007 12:31:15.018215 Starting subtest:<8>[ 24.697710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12008 12:31:15.018475 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12010 12:31:15.021880 blob-multiple
12011 12:31:15.024815 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12012 12:31:15.042374 <14>[ 24.722561] [IGT] kms_prop_blob: executing
12013 12:31:15.048564 IGT-Version: 1.2<14>[ 24.727490] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12014 12:31:15.055785 7.1-g766edf9 (aa<14>[ 24.735631] [IGT] kms_prop_blob: exiting, ret=0
12015 12:31:15.058529 rch64) (Linux: 6.1.31 aarch64)
12016 12:31:15.062405 Opened device: /dev/dri/card0
12017 12:31:15.072218 Starting subtest:<8>[ 24.748002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12018 12:31:15.072332 invalid-get-prop-any
12019 12:31:15.072606 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12021 12:31:15.078446 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12022 12:31:15.093917 <14>[ 24.774675] [IGT] kms_prop_blob: executing
12023 12:31:15.100974 IGT-Version: 1.2<14>[ 24.779703] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12024 12:31:15.107581 7.1-g766edf9 (aa<14>[ 24.787471] [IGT] kms_prop_blob: exiting, ret=0
12025 12:31:15.110807 rch64) (Linux: 6.1.31 aarch64)
12026 12:31:15.113963 Opened device: /dev/dri/card0
12027 12:31:15.120697 Starting subtest:<8>[ 24.799586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12028 12:31:15.120979 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12030 12:31:15.123927 invalid-get-prop
12031 12:31:15.127668 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12032 12:31:15.144539 <14>[ 24.825194] [IGT] kms_prop_blob: executing
12033 12:31:15.151604 IGT-Version: 1.2<14>[ 24.830054] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12034 12:31:15.157747 7.1-g766edf9 (aa<14>[ 24.838219] [IGT] kms_prop_blob: exiting, ret=0
12035 12:31:15.160971 rch64) (Linux: 6.1.31 aarch64)
12036 12:31:15.164396 Opened device: /dev/dri/card0
12037 12:31:15.174820 Starting subtest:<8>[ 24.850210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12038 12:31:15.174937 invalid-set-prop-any
12039 12:31:15.175203 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12041 12:31:15.181118 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12042 12:31:15.195806 <14>[ 24.876140] [IGT] kms_prop_blob: executing
12043 12:31:15.202182 IGT-Version: 1.2<14>[ 24.881097] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12044 12:31:15.209057 7.1-g766edf9 (aa<14>[ 24.888861] [IGT] kms_prop_blob: exiting, ret=0
12045 12:31:15.212431 rch64) (Linux: 6.1.31 aarch64)
12046 12:31:15.215755 Opened device: /dev/dri/card0
12047 12:31:15.222188 Starting subtest:<8>[ 24.900647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12048 12:31:15.222603 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12050 12:31:15.225495 invalid-set-prop
12051 12:31:15.228974 Received signal: <TESTSET> STOP
12052 12:31:15.229163 Closing test_set kms_prop_blob
12053 12:31:15.232179 [1mSubtest i<8>[ 24.910908] <LAVA_SIGNAL_TESTSET STOP>
12054 12:31:15.235221 nvalid-set-prop: SUCCESS (0.000s)[0m
12055 12:31:15.256166 <8>[ 24.936618] <LAVA_SIGNAL_TESTSET START kms_setmode>
12056 12:31:15.256441 Received signal: <TESTSET> START kms_setmode
12057 12:31:15.256516 Starting test_set kms_setmode
12058 12:31:15.279375 <14>[ 24.959668] [IGT] kms_setmode: executing
12059 12:31:15.286102 IGT-Version: 1.2<14>[ 24.964402] [IGT] kms_setmode: starting subtest basic
12060 12:31:15.292636 7.1-g766edf9 (aa<14>[ 24.971161] [IGT] kms_setmode: exiting, ret=77
12061 12:31:15.296040 rch64) (Linux: 6.1.31 aarch64)
12062 12:31:15.296604 Opened device: /dev/dri/card0
12063 12:31:15.305709 Starting subtest:<8>[ 24.983234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12064 12:31:15.306129 basic
12065 12:31:15.306751 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12067 12:31:15.308804 No dynamic tests executed.
12068 12:31:15.312472 [1mSubtest basic: SKIP (0.000s)[0m
12069 12:31:15.327253 <14>[ 25.007680] [IGT] kms_setmode: executing
12070 12:31:15.333760 IGT-Version: 1.2<14>[ 25.012397] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12071 12:31:15.340718 7.1-g766edf9 (aa<14>[ 25.020734] [IGT] kms_setmode: exiting, ret=77
12072 12:31:15.344071 rch64) (Linux: 6.1.31 aarch64)
12073 12:31:15.347163 Opened device: /dev/dri/card0
12074 12:31:15.357117 Starting subtest:<8>[ 25.032396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12075 12:31:15.357200 basic-clone-single-crtc
12076 12:31:15.357439 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12078 12:31:15.360332 No dynamic tests executed.
12079 12:31:15.366982 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12080 12:31:15.378123 <14>[ 25.058799] [IGT] kms_setmode: executing
12081 12:31:15.385060 IGT-Version: 1.2<14>[ 25.063523] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12082 12:31:15.392057 7.1-g766edf9 (aa<14>[ 25.071906] [IGT] kms_setmode: exiting, ret=77
12083 12:31:15.395378 rch64) (Linux: 6.1.31 aarch64)
12084 12:31:15.398604 Opened device: /dev/dri/card0
12085 12:31:15.408313 Starting subtest:<8>[ 25.083643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12086 12:31:15.409122 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12088 12:31:15.412123 invalid-clone-single-crtc
12089 12:31:15.412645 No dynamic tests executed.
12090 12:31:15.418270 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12091 12:31:15.430947 <14>[ 25.111299] [IGT] kms_setmode: executing
12092 12:31:15.440993 IGT-Version: 1.2<14>[ 25.116253] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12093 12:31:15.444278 7.1-g766edf9 (aa<14>[ 25.124921] [IGT] kms_setmode: exiting, ret=77
12094 12:31:15.447538 rch64) (Linux: 6.1.31 aarch64)
12095 12:31:15.450624 Opened device: /dev/dri/card0
12096 12:31:15.461338 Starting subtest:<8>[ 25.136663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12097 12:31:15.462034 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12099 12:31:15.464256 invalid-clone-exclusive-crtc
12100 12:31:15.467369 No dynamic tests executed.
12101 12:31:15.470567 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12102 12:31:15.484372 <14>[ 25.164442] [IGT] kms_setmode: executing
12103 12:31:15.490926 IGT-Version: 1.2<14>[ 25.169582] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12104 12:31:15.497358 7.1-g766edf9 (aa<14>[ 25.177290] [IGT] kms_setmode: exiting, ret=77
12105 12:31:15.500735 rch64) (Linux: 6.1.31 aarch64)
12106 12:31:15.504029 Opened device: /dev/dri/card0
12107 12:31:15.513921 Starting subtest:<8>[ 25.189315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12108 12:31:15.514384 clone-exclusive-crtc
12109 12:31:15.515075 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12111 12:31:15.517246 No dynamic tests executed.
12112 12:31:15.520431 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12113 12:31:15.536141 <14>[ 25.216252] [IGT] kms_setmode: executing
12114 12:31:15.546014 IGT-Version: 1.2<14>[ 25.221505] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12115 12:31:15.552492 7.1-g766edf9 (aa<14>[ 25.230319] [IGT] kms_setmode: exiting, ret=77
12116 12:31:15.552929 rch64) (Linux: 6.1.31 aarch64)
12117 12:31:15.555746 Opened device: /dev/dri/card0
12118 12:31:15.565936 Starting subtest:<8>[ 25.242323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12119 12:31:15.566616 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12121 12:31:15.572125 invalid-clone-single-crtc-steal<8>[ 25.253689] <LAVA_SIGNAL_TESTSET STOP>
12122 12:31:15.572802 Received signal: <TESTSET> STOP
12123 12:31:15.573152 Closing test_set kms_setmode
12124 12:31:15.575893 ing
12125 12:31:15.576269 No dynamic tests executed.
12126 12:31:15.582031 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12127 12:31:15.599454 <8>[ 25.279677] <LAVA_SIGNAL_TESTSET START kms_vblank>
12128 12:31:15.600354 Received signal: <TESTSET> START kms_vblank
12129 12:31:15.600931 Starting test_set kms_vblank
12130 12:31:15.621273 <14>[ 25.301922] [IGT] kms_vblank: executing
12131 12:31:15.627944 IGT-Version: 1.2<14>[ 25.306904] [IGT] kms_vblank: exiting, ret=77
12132 12:31:15.631126 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12133 12:31:15.634751 Opened device: /dev/dri/card0
12134 12:31:15.641270 N<8>[ 25.318505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12135 12:31:15.641559 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12137 12:31:15.644665 o KMS driver or no outputs, pipes: 8, outputs: 0
12138 12:31:15.648087 [1mSubtest invalid: SKIP (0.000s)[0m
12139 12:31:15.662243 <14>[ 25.343040] [IGT] kms_vblank: executing
12140 12:31:15.669265 IGT-Version: 1.2<14>[ 25.348003] [IGT] kms_vblank: exiting, ret=77
12141 12:31:15.672345 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12142 12:31:15.675471 Opened device: /dev/dri/card0
12143 12:31:15.682577 N<8>[ 25.359511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12144 12:31:15.682943 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12146 12:31:15.685660 o KMS driver or no outputs, pipes: 8, outputs: 0
12147 12:31:15.688654 [1mSubtest crtc-id: SKIP (0.000s)[0m
12148 12:31:15.703965 <14>[ 25.384144] [IGT] kms_vblank: executing
12149 12:31:15.709813 IGT-Version: 1.2<14>[ 25.389168] [IGT] kms_vblank: exiting, ret=77
12150 12:31:15.713229 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12151 12:31:15.716596 Opened device: /dev/dri/card0
12152 12:31:15.723181 N<8>[ 25.400411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12153 12:31:15.723457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12155 12:31:15.726553 o KMS driver or no outputs, pipes: 8, outputs: 0
12156 12:31:15.733411 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12157 12:31:15.745840 <14>[ 25.426389] [IGT] kms_vblank: executing
12158 12:31:15.752457 IGT-Version: 1.2<14>[ 25.431460] [IGT] kms_vblank: exiting, ret=77
12159 12:31:15.755698 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12160 12:31:15.758972 Opened device: /dev/dri/card0
12161 12:31:15.765621 N<8>[ 25.442813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12162 12:31:15.765905 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12164 12:31:15.769086 o KMS driver or no outputs, pipes: 8, outputs: 0
12165 12:31:15.775323 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12166 12:31:15.787929 <14>[ 25.468654] [IGT] kms_vblank: executing
12167 12:31:15.794653 IGT-Version: 1.2<14>[ 25.473685] [IGT] kms_vblank: exiting, ret=77
12168 12:31:15.797980 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12169 12:31:15.801124 Opened device: /dev/dri/card0
12170 12:31:15.808112 N<8>[ 25.485096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12171 12:31:15.808394 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12173 12:31:15.811656 o KMS driver or no outputs, pipes: 8, outputs: 0
12174 12:31:15.818061 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12175 12:31:15.830922 <14>[ 25.511139] [IGT] kms_vblank: executing
12176 12:31:15.837454 IGT-Version: 1.2<14>[ 25.516223] [IGT] kms_vblank: exiting, ret=77
12177 12:31:15.840441 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12178 12:31:15.844259 Opened device: /dev/dri/card0
12179 12:31:15.850635 N<8>[ 25.527698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12180 12:31:15.851469 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12182 12:31:15.853856 o KMS driver or no outputs, pipes: 8, outputs: 0
12183 12:31:15.860816 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12184 12:31:15.873351 <14>[ 25.553301] [IGT] kms_vblank: executing
12185 12:31:15.879699 IGT-Version: 1.2<14>[ 25.558366] [IGT] kms_vblank: exiting, ret=77
12186 12:31:15.882781 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12187 12:31:15.886548 Opened device: /dev/dri/card0
12188 12:31:15.892908 N<8>[ 25.569896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12189 12:31:15.893729 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12191 12:31:15.896156 o KMS driver or no outputs, pipes: 8, outputs: 0
12192 12:31:15.902751 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12193 12:31:15.916567 <14>[ 25.597195] [IGT] kms_vblank: executing
12194 12:31:15.923189 IGT-Version: 1.2<14>[ 25.602150] [IGT] kms_vblank: exiting, ret=77
12195 12:31:15.926560 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12196 12:31:15.929976 Opened device: /dev/dri/card0
12197 12:31:15.936958 N<8>[ 25.614110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12198 12:31:15.937258 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12200 12:31:15.940113 o KMS driver or no outputs, pipes: 8, outputs: 0
12201 12:31:15.946510 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12202 12:31:15.958781 <14>[ 25.639369] [IGT] kms_vblank: executing
12203 12:31:15.965624 IGT-Version: 1.2<14>[ 25.644369] [IGT] kms_vblank: exiting, ret=77
12204 12:31:15.968697 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12205 12:31:15.972073 Opened device: /dev/dri/card0
12206 12:31:15.978612 N<8>[ 25.655808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12207 12:31:15.978953 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12209 12:31:15.982008 o KMS driver or no outputs, pipes: 8, outputs: 0
12210 12:31:15.988522 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12211 12:31:16.002246 <14>[ 25.681782] [IGT] kms_vblank: executing
12212 12:31:16.007985 IGT-Version: 1.2<14>[ 25.686760] [IGT] kms_vblank: exiting, ret=77
12213 12:31:16.011041 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12214 12:31:16.014117 Opened device: /dev/dri/card0
12215 12:31:16.020924 N<8>[ 25.698657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12216 12:31:16.021227 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12218 12:31:16.027431 o KMS driver or no outputs, pipes: 8, outputs: 0
12219 12:31:16.030706 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12220 12:31:16.043978 <14>[ 25.724407] [IGT] kms_vblank: executing
12221 12:31:16.050579 IGT-Version: 1.2<14>[ 25.729501] [IGT] kms_vblank: exiting, ret=77
12222 12:31:16.053712 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12223 12:31:16.057033 Opened device: /dev/dri/card0
12224 12:31:16.063606 N<8>[ 25.741124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12225 12:31:16.063918 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12227 12:31:16.070268 o KMS driver or no outputs, pipes: 8, outputs: 0
12228 12:31:16.073547 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12229 12:31:16.087004 <14>[ 25.767620] [IGT] kms_vblank: executing
12230 12:31:16.093693 IGT-Version: 1.2<14>[ 25.772780] [IGT] kms_vblank: exiting, ret=77
12231 12:31:16.096940 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12232 12:31:16.100684 Opened device: /dev/dri/card0
12233 12:31:16.106953 N<8>[ 25.784542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12234 12:31:16.107807 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12236 12:31:16.110834 o KMS driver or no outputs, pipes: 8, outputs: 0
12237 12:31:16.117036 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12238 12:31:16.129544 <14>[ 25.810004] [IGT] kms_vblank: executing
12239 12:31:16.136260 IGT-Version: 1.2<14>[ 25.814991] [IGT] kms_vblank: exiting, ret=77
12240 12:31:16.139278 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12241 12:31:16.142706 Opened device: /dev/dri/card0
12242 12:31:16.149710 N<8>[ 25.826612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12243 12:31:16.150671 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12245 12:31:16.152978 o KMS driver or no outputs, pipes: 8, outputs: 0
12246 12:31:16.159280 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12247 12:31:16.171451 <14>[ 25.852263] [IGT] kms_vblank: executing
12248 12:31:16.178600 IGT-Version: 1.2<14>[ 25.857375] [IGT] kms_vblank: exiting, ret=77
12249 12:31:16.181706 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12250 12:31:16.184801 Opened device: /dev/dri/card0
12251 12:31:16.191457 N<8>[ 25.869171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12252 12:31:16.191763 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12254 12:31:16.194724 o KMS driver or no outputs, pipes: 8, outputs: 0
12255 12:31:16.201182 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12256 12:31:16.214856 <14>[ 25.895373] [IGT] kms_vblank: executing
12257 12:31:16.221107 IGT-Version: 1.2<14>[ 25.900372] [IGT] kms_vblank: exiting, ret=77
12258 12:31:16.224905 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12259 12:31:16.227930 Opened device: /dev/dri/card0
12260 12:31:16.234620 N<8>[ 25.912059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12261 12:31:16.234976 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12263 12:31:16.238057 o KMS driver or no outputs, pipes: 8, outputs: 0
12264 12:31:16.244464 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12265 12:31:16.257251 <14>[ 25.938038] [IGT] kms_vblank: executing
12266 12:31:16.263720 IGT-Version: 1.2<14>[ 25.943139] [IGT] kms_vblank: exiting, ret=77
12267 12:31:16.266925 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12268 12:31:16.270668 Opened device: /dev/dri/card0
12269 12:31:16.277144 N<8>[ 25.954408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12270 12:31:16.277433 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12272 12:31:16.280385 o KMS driver or no outputs, pipes: 8, outputs: 0
12273 12:31:16.286881 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12274 12:31:16.299102 <14>[ 25.980054] [IGT] kms_vblank: executing
12275 12:31:16.306073 IGT-Version: 1.2<14>[ 25.985074] [IGT] kms_vblank: exiting, ret=77
12276 12:31:16.309383 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12277 12:31:16.312674 Opened device: /dev/dri/card0
12278 12:31:16.319050 N<8>[ 25.996418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12279 12:31:16.319360 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12281 12:31:16.322698 o KMS driver or no outputs, pipes: 8, outputs: 0
12282 12:31:16.329452 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12283 12:31:16.342243 <14>[ 26.022745] [IGT] kms_vblank: executing
12284 12:31:16.348979 IGT-Version: 1.2<14>[ 26.027851] [IGT] kms_vblank: exiting, ret=77
12285 12:31:16.351959 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12286 12:31:16.355407 Opened device: /dev/dri/card0
12287 12:31:16.362254 N<8>[ 26.039102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12288 12:31:16.362925 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12290 12:31:16.365597 o KMS driver or no outputs, pipes: 8, outputs: 0
12291 12:31:16.372132 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12292 12:31:16.384713 <14>[ 26.065324] [IGT] kms_vblank: executing
12293 12:31:16.391820 IGT-Version: 1.2<14>[ 26.070416] [IGT] kms_vblank: exiting, ret=77
12294 12:31:16.395075 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12295 12:31:16.398043 Opened device: /dev/dri/card0
12296 12:31:16.404759 N<8>[ 26.081853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12297 12:31:16.405533 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12299 12:31:16.411234 o KMS driver or no outputs, pipes: 8, outputs: 0
12300 12:31:16.414376 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12301 12:31:16.428442 <14>[ 26.108550] [IGT] kms_vblank: executing
12302 12:31:16.434588 IGT-Version: 1.2<14>[ 26.113803] [IGT] kms_vblank: exiting, ret=77
12303 12:31:16.438322 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12304 12:31:16.441333 Opened device: /dev/dri/card0
12305 12:31:16.448396 N<8>[ 26.125211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12306 12:31:16.449117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12308 12:31:16.454409 o KMS driver or no outputs, pipes: 8, outputs: 0
12309 12:31:16.458007 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12310 12:31:16.471112 <14>[ 26.151638] [IGT] kms_vblank: executing
12311 12:31:16.477899 IGT-Version: 1.2<14>[ 26.156794] [IGT] kms_vblank: exiting, ret=77
12312 12:31:16.481195 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12313 12:31:16.484237 Opened device: /dev/dri/card0
12314 12:31:16.491084 N<8>[ 26.168070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12315 12:31:16.491373 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12317 12:31:16.497649 o KMS driver or no outputs, pipes: 8, outputs: 0
12318 12:31:16.500928 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12319 12:31:16.514559 <14>[ 26.195157] [IGT] kms_vblank: executing
12320 12:31:16.521299 IGT-Version: 1.2<14>[ 26.200189] [IGT] kms_vblank: exiting, ret=77
12321 12:31:16.524666 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12322 12:31:16.527963 Opened device: /dev/dri/card0
12323 12:31:16.534223 N<8>[ 26.211533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12324 12:31:16.534507 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12326 12:31:16.540976 o KMS driver or no outputs, pipes: 8, outputs: 0
12327 12:31:16.544144 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12328 12:31:16.558032 <14>[ 26.238437] [IGT] kms_vblank: executing
12329 12:31:16.564094 IGT-Version: 1.2<14>[ 26.243461] [IGT] kms_vblank: exiting, ret=77
12330 12:31:16.567347 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12331 12:31:16.571477 Opened device: /dev/dri/card0
12332 12:31:16.577372 N<8>[ 26.254780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12333 12:31:16.577667 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12335 12:31:16.584001 o KMS driver or no outputs, pipes: 8, outputs: 0
12336 12:31:16.590381 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12337 12:31:16.601515 <14>[ 26.282146] [IGT] kms_vblank: executing
12338 12:31:16.608253 IGT-Version: 1.2<14>[ 26.287195] [IGT] kms_vblank: exiting, ret=77
12339 12:31:16.611376 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12340 12:31:16.614713 Opened device: /dev/dri/card0
12341 12:31:16.621350 N<8>[ 26.298560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12342 12:31:16.621640 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12344 12:31:16.627965 o KMS driver or no outputs, pipes: 8, outputs: 0
12345 12:31:16.631226 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12346 12:31:16.644573 <14>[ 26.325504] [IGT] kms_vblank: executing
12347 12:31:16.651583 IGT-Version: 1.2<14>[ 26.330519] [IGT] kms_vblank: exiting, ret=77
12348 12:31:16.654791 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12349 12:31:16.657894 Opened device: /dev/dri/card0
12350 12:31:16.664747 N<8>[ 26.341853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12351 12:31:16.665027 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12353 12:31:16.671532 o KMS driver or no outputs, pipes: 8, outputs: 0
12354 12:31:16.674229 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12355 12:31:16.687505 <14>[ 26.368565] [IGT] kms_vblank: executing
12356 12:31:16.694670 IGT-Version: 1.2<14>[ 26.373815] [IGT] kms_vblank: exiting, ret=77
12357 12:31:16.697872 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12358 12:31:16.701364 Opened device: /dev/dri/card0
12359 12:31:16.708069 N<8>[ 26.384867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12360 12:31:16.708330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12362 12:31:16.714322 o KMS driver or no outputs, pipes: 8, outputs: 0
12363 12:31:16.721334 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12364 12:31:16.731725 <14>[ 26.412264] [IGT] kms_vblank: executing
12365 12:31:16.738246 IGT-Version: 1.2<14>[ 26.417382] [IGT] kms_vblank: exiting, ret=77
12366 12:31:16.741579 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12367 12:31:16.744847 Opened device: /dev/dri/card0
12368 12:31:16.751274 N<8>[ 26.428513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12369 12:31:16.751537 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12371 12:31:16.757797 o KMS driver or no outputs, pipes: 8, outputs: 0
12372 12:31:16.761685 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12373 12:31:16.775230 <14>[ 26.455861] [IGT] kms_vblank: executing
12374 12:31:16.782055 IGT-Version: 1.2<14>[ 26.460869] [IGT] kms_vblank: exiting, ret=77
12375 12:31:16.785368 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12376 12:31:16.788666 Opened device: /dev/dri/card0
12377 12:31:16.795290 N<8>[ 26.472156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12378 12:31:16.795576 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12380 12:31:16.798695 o KMS driver or no outputs, pipes: 8, outputs: 0
12381 12:31:16.804972 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12382 12:31:16.817377 <14>[ 26.498328] [IGT] kms_vblank: executing
12383 12:31:16.824339 IGT-Version: 1.2<14>[ 26.503322] [IGT] kms_vblank: exiting, ret=77
12384 12:31:16.827416 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12385 12:31:16.830776 Opened device: /dev/dri/card0
12386 12:31:16.837437 N<8>[ 26.515000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12387 12:31:16.837714 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12389 12:31:16.840633 o KMS driver or no outputs, pipes: 8, outputs: 0
12390 12:31:16.847210 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12391 12:31:16.884011 <14>[ 26.540267] [IGT] kms_vblank: executing
12392 12:31:16.884191 IGT-Version: 1.2<14>[ 26.545378] [IGT] kms_vblank: exiting, ret=77
12393 12:31:16.884309 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12394 12:31:16.884423 Opened device: /dev/dri/card0
12395 12:31:16.884536 N<8>[ 26.557111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12396 12:31:16.884649 o KMS driver or no outputs, pipes: 8, outputs: 0
12397 12:31:16.884936 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12399 12:31:16.889510 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12400 12:31:16.903557 <14>[ 26.583987] [IGT] kms_vblank: executing
12401 12:31:16.910090 IGT-Version: 1.2<14>[ 26.589273] [IGT] kms_vblank: exiting, ret=77
12402 12:31:16.913200 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12403 12:31:16.916894 Opened device: /dev/dri/card0
12404 12:31:16.923460 N<8>[ 26.600266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12405 12:31:16.923732 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12407 12:31:16.926616 o KMS driver or no outputs, pipes: 8, outputs: 0
12408 12:31:16.933337 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12409 12:31:16.945660 <14>[ 26.626333] [IGT] kms_vblank: executing
12410 12:31:16.952249 IGT-Version: 1.2<14>[ 26.631307] [IGT] kms_vblank: exiting, ret=77
12411 12:31:16.955615 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12412 12:31:16.958822 Opened device: /dev/dri/card0
12413 12:31:16.965636 N<8>[ 26.642872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12414 12:31:16.965905 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12416 12:31:16.972240 o KMS driver or no outputs, pipes: 8, outputs: 0
12417 12:31:16.975390 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12418 12:31:16.988190 <14>[ 26.668919] [IGT] kms_vblank: executing
12419 12:31:16.994723 IGT-Version: 1.2<14>[ 26.673937] [IGT] kms_vblank: exiting, ret=77
12420 12:31:16.997844 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12421 12:31:17.001165 Opened device: /dev/dri/card0
12422 12:31:17.007728 N<8>[ 26.685386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12423 12:31:17.007977 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12425 12:31:17.011612 o KMS driver or no outputs, pipes: 8, outputs: 0
12426 12:31:17.017640 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12427 12:31:17.029952 <14>[ 26.710973] [IGT] kms_vblank: executing
12428 12:31:17.036559 IGT-Version: 1.2<14>[ 26.715975] [IGT] kms_vblank: exiting, ret=77
12429 12:31:17.040388 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12430 12:31:17.043565 Opened device: /dev/dri/card0
12431 12:31:17.050298 N<8>[ 26.727551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12432 12:31:17.050594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12434 12:31:17.053591 o KMS driver or no outputs, pipes: 8, outputs: 0
12435 12:31:17.060111 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12436 12:31:17.072781 <14>[ 26.753268] [IGT] kms_vblank: executing
12437 12:31:17.079271 IGT-Version: 1.2<14>[ 26.758387] [IGT] kms_vblank: exiting, ret=77
12438 12:31:17.082547 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12439 12:31:17.085671 Opened device: /dev/dri/card0
12440 12:31:17.092371 N<8>[ 26.769835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12441 12:31:17.092633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12443 12:31:17.099133 o KMS driver or no outputs, pipes: 8, outputs: 0
12444 12:31:17.102069 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12445 12:31:17.114923 <14>[ 26.795789] [IGT] kms_vblank: executing
12446 12:31:17.121500 IGT-Version: 1.2<14>[ 26.800769] [IGT] kms_vblank: exiting, ret=77
12447 12:31:17.124698 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12448 12:31:17.128527 Opened device: /dev/dri/card0
12449 12:31:17.134884 N<8>[ 26.812138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12450 12:31:17.135169 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12452 12:31:17.141289 o KMS driver or no outputs, pipes: 8, outputs: 0
12453 12:31:17.144541 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12454 12:31:17.158277 <14>[ 26.838786] [IGT] kms_vblank: executing
12455 12:31:17.164900 IGT-Version: 1.2<14>[ 26.843788] [IGT] kms_vblank: exiting, ret=77
12456 12:31:17.167624 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12457 12:31:17.171534 Opened device: /dev/dri/card0
12458 12:31:17.178191 N<8>[ 26.855107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12459 12:31:17.178446 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12461 12:31:17.181504 o KMS driver or no outputs, pipes: 8, outputs: 0
12462 12:31:17.188101 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12463 12:31:17.200259 <14>[ 26.880762] [IGT] kms_vblank: executing
12464 12:31:17.206467 IGT-Version: 1.2<14>[ 26.885861] [IGT] kms_vblank: exiting, ret=77
12465 12:31:17.209929 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12466 12:31:17.213299 Opened device: /dev/dri/card0
12467 12:31:17.219794 N<8>[ 26.897410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12468 12:31:17.220053 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12470 12:31:17.223037 o KMS driver or no outputs, pipes: 8, outputs: 0
12471 12:31:17.230077 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12472 12:31:17.242434 <14>[ 26.923156] [IGT] kms_vblank: executing
12473 12:31:17.249257 IGT-Version: 1.2<14>[ 26.928174] [IGT] kms_vblank: exiting, ret=77
12474 12:31:17.252329 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12475 12:31:17.255619 Opened device: /dev/dri/card0
12476 12:31:17.262304 N<8>[ 26.939595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12477 12:31:17.262588 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12479 12:31:17.265603 o KMS driver or no outputs, pipes: 8, outputs: 0
12480 12:31:17.272129 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12481 12:31:17.284302 <14>[ 26.965225] [IGT] kms_vblank: executing
12482 12:31:17.291315 IGT-Version: 1.2<14>[ 26.970228] [IGT] kms_vblank: exiting, ret=77
12483 12:31:17.294810 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12484 12:31:17.297429 Opened device: /dev/dri/card0
12485 12:31:17.304436 N<8>[ 26.981648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12486 12:31:17.304721 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12488 12:31:17.307384 o KMS driver or no outputs, pipes: 8, outputs: 0
12489 12:31:17.314180 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12490 12:31:17.367023 <14>[ 27.007509] [IGT] kms_vblank: executing
12491 12:31:17.367195 IGT-Version: 1.2<14>[ 27.012613] [IGT] kms_vblank: exiting, ret=77
12492 12:31:17.367306 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12493 12:31:17.367389 Opened device: /dev/dri/card0
12494 12:31:17.367453 N<8>[ 27.024030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12495 12:31:17.367530 o KMS driver or no outputs, pipes: 8, outputs: 0
12496 12:31:17.367591 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12497 12:31:17.367830 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12499 12:31:17.368665 <14>[ 27.049667] [IGT] kms_vblank: executing
12500 12:31:17.375377 IGT-Version: 1.2<14>[ 27.054802] [IGT] kms_vblank: exiting, ret=77
12501 12:31:17.378741 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12502 12:31:17.381921 Opened device: /dev/dri/card0
12503 12:31:17.388490 N<8>[ 27.066171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12504 12:31:17.388746 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12506 12:31:17.391756 o KMS driver or no outputs, pipes: 8, outputs: 0
12507 12:31:17.398377 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12508 12:31:17.411579 <14>[ 27.092028] [IGT] kms_vblank: executing
12509 12:31:17.418209 IGT-Version: 1.2<14>[ 27.097128] [IGT] kms_vblank: exiting, ret=77
12510 12:31:17.421076 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12511 12:31:17.424673 Opened device: /dev/dri/card0
12512 12:31:17.431297 N<8>[ 27.108413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12513 12:31:17.431567 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12515 12:31:17.434360 o KMS driver or no outputs, pipes: 8, outputs: 0
12516 12:31:17.441393 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12517 12:31:17.453754 <14>[ 27.134400] [IGT] kms_vblank: executing
12518 12:31:17.460638 IGT-Version: 1.2<14>[ 27.139505] [IGT] kms_vblank: exiting, ret=77
12519 12:31:17.463873 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12520 12:31:17.467099 Opened device: /dev/dri/card0
12521 12:31:17.473675 N<8>[ 27.150833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12522 12:31:17.473938 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12524 12:31:17.480256 o KMS driver or no outputs, pipes: 8, outputs: 0
12525 12:31:17.483527 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12526 12:31:17.497147 <14>[ 27.177495] [IGT] kms_vblank: executing
12527 12:31:17.503077 IGT-Version: 1.2<14>[ 27.182544] [IGT] kms_vblank: exiting, ret=77
12528 12:31:17.506320 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12529 12:31:17.510232 Opened device: /dev/dri/card0
12530 12:31:17.516621 N<8>[ 27.194002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12531 12:31:17.516918 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12533 12:31:17.523203 o KMS driver or no outputs, pipes: 8, outputs: 0
12534 12:31:17.526217 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12535 12:31:17.539732 <14>[ 27.220619] [IGT] kms_vblank: executing
12536 12:31:17.546256 IGT-Version: 1.2<14>[ 27.225864] [IGT] kms_vblank: exiting, ret=77
12537 12:31:17.549654 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12538 12:31:17.552958 Opened device: /dev/dri/card0
12539 12:31:17.559494 N<8>[ 27.237300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12540 12:31:17.559773 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12542 12:31:17.565868 o KMS driver or no outputs, pipes: 8, outputs: 0
12543 12:31:17.572510 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12544 12:31:17.583339 <14>[ 27.264237] [IGT] kms_vblank: executing
12545 12:31:17.590315 IGT-Version: 1.2<14>[ 27.269374] [IGT] kms_vblank: exiting, ret=77
12546 12:31:17.593557 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12547 12:31:17.596295 Opened device: /dev/dri/card0
12548 12:31:17.602981 N<8>[ 27.280545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12549 12:31:17.603231 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12551 12:31:17.609575 o KMS driver or no outputs, pipes: 8, outputs: 0
12552 12:31:17.613070 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12553 12:31:17.626552 <14>[ 27.307439] [IGT] kms_vblank: executing
12554 12:31:17.633573 IGT-Version: 1.2<14>[ 27.312416] [IGT] kms_vblank: exiting, ret=77
12555 12:31:17.636554 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12556 12:31:17.639764 Opened device: /dev/dri/card0
12557 12:31:17.646494 N<8>[ 27.323833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12558 12:31:17.646782 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12560 12:31:17.653161 o KMS driver or no outputs, pipes: 8, outputs: 0
12561 12:31:17.659652 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12562 12:31:17.669957 <14>[ 27.350846] [IGT] kms_vblank: executing
12563 12:31:17.676562 IGT-Version: 1.2<14>[ 27.355850] [IGT] kms_vblank: exiting, ret=77
12564 12:31:17.679698 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12565 12:31:17.683504 Opened device: /dev/dri/card0
12566 12:31:17.689901 N<8>[ 27.367217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12567 12:31:17.690191 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12569 12:31:17.696312 o KMS driver or no outputs, pipes: 8, outputs: 0
12570 12:31:17.699936 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12571 12:31:17.713242 <14>[ 27.394306] [IGT] kms_vblank: executing
12572 12:31:17.720090 IGT-Version: 1.2<14>[ 27.399315] [IGT] kms_vblank: exiting, ret=77
12573 12:31:17.723813 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12574 12:31:17.727052 Opened device: /dev/dri/card0
12575 12:31:17.733626 N<8>[ 27.410809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12576 12:31:17.733917 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12578 12:31:17.740072 o KMS driver or no outputs, pipes: 8, outputs: 0
12579 12:31:17.743340 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12580 12:31:17.757103 <14>[ 27.437797] [IGT] kms_vblank: executing
12581 12:31:17.763282 IGT-Version: 1.2<14>[ 27.442794] [IGT] kms_vblank: exiting, ret=77
12582 12:31:17.766747 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12583 12:31:17.769982 Opened device: /dev/dri/card0
12584 12:31:17.776806 N<8>[ 27.454174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12585 12:31:17.777066 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12587 12:31:17.783554 o KMS driver or no outputs, pipes: 8, outputs: 0
12588 12:31:17.789949 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12589 12:31:17.800838 <14>[ 27.481448] [IGT] kms_vblank: executing
12590 12:31:17.807155 IGT-Version: 1.2<14>[ 27.486525] [IGT] kms_vblank: exiting, ret=77
12591 12:31:17.810435 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12592 12:31:17.813800 Opened device: /dev/dri/card0
12593 12:31:17.852837 N<8>[ 27.497865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12594 12:31:17.852984 o KMS driver or no outputs, pipes: 8, outputs: 0
12595 12:31:17.853087 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12596 12:31:17.853182 <14>[ 27.524836] [IGT] kms_vblank: executing
12597 12:31:17.853275 IGT-Version: 1.2<14>[ 27.529962] [IGT] kms_vblank: exiting, ret=77
12598 12:31:17.853545 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12600 12:31:17.853935 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12601 12:31:17.857198 Opened device: /dev/dri/card0
12602 12:31:17.863913 N<8>[ 27.541482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12603 12:31:17.864208 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12605 12:31:17.867632 o KMS driver or no outputs, pipes: 8, outputs: 0
12606 12:31:17.873935 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12607 12:31:17.886623 <14>[ 27.567181] [IGT] kms_vblank: executing
12608 12:31:17.892968 IGT-Version: 1.2<14>[ 27.572205] [IGT] kms_vblank: exiting, ret=77
12609 12:31:17.896370 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12610 12:31:17.899609 Opened device: /dev/dri/card0
12611 12:31:17.905962 N<8>[ 27.583818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12612 12:31:17.906254 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12614 12:31:17.909854 o KMS driver or no outputs, pipes: 8, outputs: 0
12615 12:31:17.916268 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12616 12:31:17.928729 <14>[ 27.609437] [IGT] kms_vblank: executing
12617 12:31:17.935240 IGT-Version: 1.2<14>[ 27.614497] [IGT] kms_vblank: exiting, ret=77
12618 12:31:17.938533 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12619 12:31:17.941846 Opened device: /dev/dri/card0
12620 12:31:17.948371 N<8>[ 27.625904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12621 12:31:17.948633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12623 12:31:17.951807 o KMS driver or no outputs, pipes: 8, outputs: 0
12624 12:31:17.958208 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12625 12:31:17.971313 <14>[ 27.652040] [IGT] kms_vblank: executing
12626 12:31:17.977574 IGT-Version: 1.2<14>[ 27.657052] [IGT] kms_vblank: exiting, ret=77
12627 12:31:17.981372 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12628 12:31:17.984543 Opened device: /dev/dri/card0
12629 12:31:17.991161 N<8>[ 27.668288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12630 12:31:17.991446 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12632 12:31:17.994294 o KMS driver or no outputs, pipes: 8, outputs: 0
12633 12:31:18.000900 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12634 12:31:18.013396 <14>[ 27.694056] [IGT] kms_vblank: executing
12635 12:31:18.019787 IGT-Version: 1.2<14>[ 27.699155] [IGT] kms_vblank: exiting, ret=77
12636 12:31:18.023168 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12637 12:31:18.026533 Opened device: /dev/dri/card0
12638 12:31:18.033064 N<8>[ 27.710708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12639 12:31:18.033345 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12641 12:31:18.039425 o KMS driver or no outputs, pipes: 8, outputs: 0
12642 12:31:18.042643 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12643 12:31:18.056360 <14>[ 27.737035] [IGT] kms_vblank: executing
12644 12:31:18.062767 IGT-Version: 1.2<14>[ 27.742174] [IGT] kms_vblank: exiting, ret=77
12645 12:31:18.066192 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12646 12:31:18.069609 Opened device: /dev/dri/card0
12647 12:31:18.076371 N<8>[ 27.753691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12648 12:31:18.076626 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12650 12:31:18.079461 o KMS driver or no outputs, pipes: 8, outputs: 0
12651 12:31:18.085866 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12652 12:31:18.098236 <14>[ 27.779280] [IGT] kms_vblank: executing
12653 12:31:18.104822 IGT-Version: 1.2<14>[ 27.784329] [IGT] kms_vblank: exiting, ret=77
12654 12:31:18.108136 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12655 12:31:18.112054 Opened device: /dev/dri/card0
12656 12:31:18.118421 N<8>[ 27.795620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12657 12:31:18.118707 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12659 12:31:18.121592 o KMS driver or no outputs, pipes: 8, outputs: 0
12660 12:31:18.127982 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12661 12:31:18.141534 <14>[ 27.821959] [IGT] kms_vblank: executing
12662 12:31:18.148032 IGT-Version: 1.2<14>[ 27.826948] [IGT] kms_vblank: exiting, ret=77
12663 12:31:18.151383 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12664 12:31:18.154338 Opened device: /dev/dri/card0
12665 12:31:18.160881 N<8>[ 27.838537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12666 12:31:18.161138 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12668 12:31:18.164423 o KMS driver or no outputs, pipes: 8, outputs: 0
12669 12:31:18.171349 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12670 12:31:18.184008 <14>[ 27.864720] [IGT] kms_vblank: executing
12671 12:31:18.190169 IGT-Version: 1.2<14>[ 27.869868] [IGT] kms_vblank: exiting, ret=77
12672 12:31:18.193808 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12673 12:31:18.196911 Opened device: /dev/dri/card0
12674 12:31:18.203915 N<8>[ 27.881377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12675 12:31:18.204203 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12677 12:31:18.210664 o KMS driver or no outputs, pipes: 8, outputs: 0
12678 12:31:18.213618 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12679 12:31:18.226909 <14>[ 27.907972] [IGT] kms_vblank: executing
12680 12:31:18.233703 IGT-Version: 1.2<14>[ 27.913096] [IGT] kms_vblank: exiting, ret=77
12681 12:31:18.236962 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12682 12:31:18.240173 Opened device: /dev/dri/card0
12683 12:31:18.246707 N<8>[ 27.924481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12684 12:31:18.246997 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12686 12:31:18.250604 o KMS driver or no outputs, pipes: 8, outputs: 0
12687 12:31:18.257170 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12688 12:31:18.269710 <14>[ 27.950387] [IGT] kms_vblank: executing
12689 12:31:18.275889 IGT-Version: 1.2<14>[ 27.955370] [IGT] kms_vblank: exiting, ret=77
12690 12:31:18.279317 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12691 12:31:18.283071 Opened device: /dev/dri/card0
12692 12:31:18.289742 N<8>[ 27.966839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12693 12:31:18.289998 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12695 12:31:18.292990 o KMS driver or no outputs, pipes: 8, outputs: 0
12696 12:31:18.298956 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12697 12:31:18.312227 <14>[ 27.992832] [IGT] kms_vblank: executing
12698 12:31:18.318324 IGT-Version: 1.2<14>[ 27.997877] [IGT] kms_vblank: exiting, ret=77
12699 12:31:18.321968 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12700 12:31:18.324993 Opened device: /dev/dri/card0
12701 12:31:18.331735 N<8>[ 28.009319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12702 12:31:18.332027 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12704 12:31:18.371634 o KMS driver or no outputs, pipes: 8, outputs: 0
12705 12:31:18.371764 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12706 12:31:18.371911 <14>[ 28.035063] [IGT] kms_vblank: executing
12707 12:31:18.372038 IGT-Version: 1.2<14>[ 28.040144] [IGT] kms_vblank: exiting, ret=77
12708 12:31:18.372147 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12709 12:31:18.372240 Opened device: /dev/dri/card0
12710 12:31:18.374315 N<8>[ 28.051606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12711 12:31:18.374594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12713 12:31:18.377568 o KMS driver or no outputs, pipes: 8, outputs: 0
12714 12:31:18.384120 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12715 12:31:18.397979 <14>[ 28.078847] [IGT] kms_vblank: executing
12716 12:31:18.404370 IGT-Version: 1.2<14>[ 28.083949] [IGT] kms_vblank: exiting, ret=77
12717 12:31:18.408172 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12718 12:31:18.411414 Opened device: /dev/dri/card0
12719 12:31:18.417991 N<8>[ 28.096113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12720 12:31:18.418276 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12722 12:31:18.421340 o KMS driver or no outputs, pipes: 8, outputs: 0
12723 12:31:18.427544 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12724 12:31:18.441497 <14>[ 28.122025] [IGT] kms_vblank: executing
12725 12:31:18.447842 IGT-Version: 1.2<14>[ 28.127178] [IGT] kms_vblank: exiting, ret=77
12726 12:31:18.451018 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12727 12:31:18.454222 Opened device: /dev/dri/card0
12728 12:31:18.461550 N<8>[ 28.138725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12729 12:31:18.461835 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12731 12:31:18.464809 o KMS driver or no outputs, pipes: 8, outputs: 0
12732 12:31:18.471260 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12733 12:31:18.483663 <14>[ 28.164569] [IGT] kms_vblank: executing
12734 12:31:18.490316 IGT-Version: 1.2<14>[ 28.169782] [IGT] kms_vblank: exiting, ret=77
12735 12:31:18.493470 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12736 12:31:18.496936 Opened device: /dev/dri/card0
12737 12:31:18.503344 N<8>[ 28.181268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12738 12:31:18.503602 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12740 12:31:18.506713 o KMS driver or no outputs, pipes: 8, outputs: 0
12741 12:31:18.513635 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12742 12:31:18.526092 <14>[ 28.207184] [IGT] kms_vblank: executing
12743 12:31:18.533163 IGT-Version: 1.2<14>[ 28.212210] [IGT] kms_vblank: exiting, ret=77
12744 12:31:18.536460 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12745 12:31:18.539471 Opened device: /dev/dri/card0
12746 12:31:18.546554 N<8>[ 28.223777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12747 12:31:18.546824 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12749 12:31:18.553095 o KMS driver or no outputs, pipes: 8, outputs: 0
12750 12:31:18.556085 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12751 12:31:18.569724 <14>[ 28.250347] [IGT] kms_vblank: executing
12752 12:31:18.576209 IGT-Version: 1.2<14>[ 28.255439] [IGT] kms_vblank: exiting, ret=77
12753 12:31:18.579429 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12754 12:31:18.582754 Opened device: /dev/dri/card0
12755 12:31:18.589363 N<8>[ 28.267165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12756 12:31:18.589644 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12758 12:31:18.595879 o KMS driver or no outputs, pipes: 8, outputs: 0
12759 12:31:18.599107 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12760 12:31:18.613554 <14>[ 28.294409] [IGT] kms_vblank: executing
12761 12:31:18.620377 IGT-Version: 1.2<14>[ 28.299384] [IGT] kms_vblank: exiting, ret=77
12762 12:31:18.623670 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12763 12:31:18.626602 Opened device: /dev/dri/card0
12764 12:31:18.633512 N<8>[ 28.311148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12765 12:31:18.633796 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12767 12:31:18.640454 o KMS driver or no outputs, pipes: 8, outputs: 0
12768 12:31:18.643657 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12769 12:31:18.657841 <14>[ 28.338810] [IGT] kms_vblank: executing
12770 12:31:18.664774 IGT-Version: 1.2<14>[ 28.343887] [IGT] kms_vblank: exiting, ret=77
12771 12:31:18.668047 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12772 12:31:18.671320 Opened device: /dev/dri/card0
12773 12:31:18.696717 N<8>[ 28.355544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12774 12:31:18.696829 o KMS driver or no outputs, pipes: 8, outputs: 0
12775 12:31:18.696931 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12776 12:31:18.697212 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12778 12:31:18.701331 <14>[ 28.382006] [IGT] kms_vblank: executing
12779 12:31:18.708021 IGT-Version: 1.2<14>[ 28.386982] [IGT] kms_vblank: exiting, ret=77
12780 12:31:18.710793 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12781 12:31:18.714022 Opened device: /dev/dri/card0
12782 12:31:18.720671 N<8>[ 28.398388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12783 12:31:18.720951 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12785 12:31:18.727539 o KMS driver or no outputs, pipes: 8, outputs: 0
12786 12:31:18.734303 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12787 12:31:18.744435 <14>[ 28.425587] [IGT] kms_vblank: executing
12788 12:31:18.751476 IGT-Version: 1.2<14>[ 28.430692] [IGT] kms_vblank: exiting, ret=77
12789 12:31:18.754357 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12790 12:31:18.758047 Opened device: /dev/dri/card0
12791 12:31:18.764405 N<8>[ 28.442148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12792 12:31:18.764662 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12794 12:31:18.771485 o KMS driver or no outputs, pipes: 8, outputs: 0
12795 12:31:18.774729 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12796 12:31:18.788310 <14>[ 28.468912] [IGT] kms_vblank: executing
12797 12:31:18.794737 IGT-Version: 1.2<14>[ 28.473907] [IGT] kms_vblank: exiting, ret=77
12798 12:31:18.798059 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12799 12:31:18.801318 Opened device: /dev/dri/card0
12800 12:31:18.807796 N<8>[ 28.485314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12801 12:31:18.808051 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12803 12:31:18.814974 o KMS driver or no outputs, pipes: 8, outputs: 0
12804 12:31:18.817815 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12805 12:31:18.831078 <14>[ 28.512086] [IGT] kms_vblank: executing
12806 12:31:18.837873 IGT-Version: 1.2<14>[ 28.517215] [IGT] kms_vblank: exiting, ret=77
12807 12:31:18.841183 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12808 12:31:18.844371 Opened device: /dev/dri/card0
12809 12:31:18.850999 N<8>[ 28.528630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12810 12:31:18.851320 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12812 12:31:18.857810 o KMS driver or no outputs, pipes: 8, outputs: 0
12813 12:31:18.861005 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12814 12:31:18.874838 <14>[ 28.555727] [IGT] kms_vblank: executing
12815 12:31:18.881360 IGT-Version: 1.2<14>[ 28.560723] [IGT] kms_vblank: exiting, ret=77
12816 12:31:18.884415 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12817 12:31:18.887907 Opened device: /dev/dri/card0
12818 12:31:18.894884 N<8>[ 28.572041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12819 12:31:18.895218 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12821 12:31:18.901296 o KMS driver or no outputs, pipes: 8, outputs: 0
12822 12:31:18.904675 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12823 12:31:18.918167 <14>[ 28.599162] [IGT] kms_vblank: executing
12824 12:31:18.924899 IGT-Version: 1.2<14>[ 28.604151] [IGT] kms_vblank: exiting, ret=77
12825 12:31:18.928156 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12826 12:31:18.931527 Opened device: /dev/dri/card0
12827 12:31:18.938183 N<8>[ 28.615532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12828 12:31:18.938471 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12830 12:31:18.941256 o KMS driver or no outputs, pipes: 8, outputs: 0
12831 12:31:18.948205 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12832 12:31:18.960730 <14>[ 28.641325] [IGT] kms_vblank: executing
12833 12:31:18.967049 IGT-Version: 1.2<14>[ 28.646425] [IGT] kms_vblank: exiting, ret=77
12834 12:31:18.970434 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12835 12:31:18.973618 Opened device: /dev/dri/card0
12836 12:31:18.980382 N<8>[ 28.657904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12837 12:31:18.980665 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12839 12:31:18.983696 o KMS driver or no outputs, pipes: 8, outputs: 0
12840 12:31:18.990008 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12841 12:31:19.002235 <14>[ 28.683268] [IGT] kms_vblank: executing
12842 12:31:19.008930 IGT-Version: 1.2<14>[ 28.688292] [IGT] kms_vblank: exiting, ret=77
12843 12:31:19.012639 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12844 12:31:19.015865 Opened device: /dev/dri/card0
12845 12:31:19.022372 N<8>[ 28.699774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12846 12:31:19.022644 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12848 12:31:19.025731 o KMS driver or no outputs, pipes: 8, outputs: 0
12849 12:31:19.032264 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12850 12:31:19.046027 <14>[ 28.726644] [IGT] kms_vblank: executing
12851 12:31:19.052327 IGT-Version: 1.2<14>[ 28.731641] [IGT] kms_vblank: exiting, ret=77
12852 12:31:19.055525 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12853 12:31:19.059237 Opened device: /dev/dri/card0
12854 12:31:19.065667 N<8>[ 28.743829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12855 12:31:19.065926 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12857 12:31:19.068874 o KMS driver or no outputs, pipes: 8, outputs: 0
12858 12:31:19.075559 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12859 12:31:19.089174 <14>[ 28.770167] [IGT] kms_vblank: executing
12860 12:31:19.096137 IGT-Version: 1.2<14>[ 28.775162] [IGT] kms_vblank: exiting, ret=77
12861 12:31:19.099537 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12862 12:31:19.102712 Opened device: /dev/dri/card0
12863 12:31:19.109220 N<8>[ 28.787262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12864 12:31:19.109519 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12866 12:31:19.112716 o KMS driver or no outputs, pipes: 8, outputs: 0
12867 12:31:19.119089 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12868 12:31:19.132234 <14>[ 28.813085] [IGT] kms_vblank: executing
12869 12:31:19.138849 IGT-Version: 1.2<14>[ 28.818163] [IGT] kms_vblank: exiting, ret=77
12870 12:31:19.142161 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12871 12:31:19.145265 Opened device: /dev/dri/card0
12872 12:31:19.151888 N<8>[ 28.829699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12873 12:31:19.152176 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12875 12:31:19.155498 o KMS driver or no outputs, pipes: 8, outputs: 0
12876 12:31:19.161745 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12877 12:31:19.174588 <14>[ 28.855171] [IGT] kms_vblank: executing
12878 12:31:19.180664 IGT-Version: 1.2<14>[ 28.860169] [IGT] kms_vblank: exiting, ret=77
12879 12:31:19.184368 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12880 12:31:19.187439 Opened device: /dev/dri/card0
12881 12:31:19.194327 N<8>[ 28.871723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12882 12:31:19.194615 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12884 12:31:19.197359 o KMS driver or no outputs, pipes: 8, outputs: 0
12885 12:31:19.204248 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12886 12:31:19.217320 <14>[ 28.898462] [IGT] kms_vblank: executing
12887 12:31:19.224367 IGT-Version: 1.2<14>[ 28.903457] [IGT] kms_vblank: exiting, ret=77
12888 12:31:19.227636 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12889 12:31:19.230826 Opened device: /dev/dri/card0
12890 12:31:19.237539 N<8>[ 28.915786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12891 12:31:19.237800 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12893 12:31:19.240829 o KMS driver or no outputs, pipes: 8, outputs: 0
12894 12:31:19.247420 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12895 12:31:19.261198 <14>[ 28.942357] [IGT] kms_vblank: executing
12896 12:31:19.267801 IGT-Version: 1.2<14>[ 28.947411] [IGT] kms_vblank: exiting, ret=77
12897 12:31:19.271492 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12898 12:31:19.274665 Opened device: /dev/dri/card0
12899 12:31:19.281200 N<8>[ 28.959741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12900 12:31:19.281463 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12902 12:31:19.287648 o KMS driver or no outputs, pipes: 8, outputs: 0
12903 12:31:19.290797 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12904 12:31:19.306065 <14>[ 28.986856] [IGT] kms_vblank: executing
12905 12:31:19.312821 IGT-Version: 1.2<14>[ 28.992032] [IGT] kms_vblank: exiting, ret=77
12906 12:31:19.315826 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12907 12:31:19.319027 Opened device: /dev/dri/card0
12908 12:31:19.325918 N<8>[ 29.003436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12909 12:31:19.326186 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12911 12:31:19.329145 o KMS driver or no outputs, pipes: 8, outputs: 0
12912 12:31:19.335648 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12913 12:31:19.348755 <14>[ 29.029663] [IGT] kms_vblank: executing
12914 12:31:19.355267 IGT-Version: 1.2<14>[ 29.034675] [IGT] kms_vblank: exiting, ret=77
12915 12:31:19.358590 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12916 12:31:19.361938 Opened device: /dev/dri/card0
12917 12:31:19.368800 N<8>[ 29.046212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12918 12:31:19.369053 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12920 12:31:19.371945 o KMS driver or no outputs, pipes: 8, outputs: 0
12921 12:31:19.378274 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12922 12:31:19.390613 <14>[ 29.071862] [IGT] kms_vblank: executing
12923 12:31:19.397426 IGT-Version: 1.2<14>[ 29.076837] [IGT] kms_vblank: exiting, ret=77
12924 12:31:19.400448 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12925 12:31:19.403984 Opened device: /dev/dri/card0
12926 12:31:19.410469 N<8>[ 29.088309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12927 12:31:19.410731 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12929 12:31:19.414237 o KMS driver or no outputs, pipes: 8, outputs: 0
12930 12:31:19.420418 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12931 12:31:19.432945 <14>[ 29.114004] [IGT] kms_vblank: executing
12932 12:31:19.439569 IGT-Version: 1.2<14>[ 29.118982] [IGT] kms_vblank: exiting, ret=77
12933 12:31:19.442840 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12934 12:31:19.446098 Opened device: /dev/dri/card0
12935 12:31:19.452671 N<8>[ 29.130508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12936 12:31:19.452933 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12938 12:31:19.456062 o KMS driver or no outputs, pipes: 8, outputs: 0
12939 12:31:19.462589 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12940 12:31:19.475547 <14>[ 29.156774] [IGT] kms_vblank: executing
12941 12:31:19.482167 IGT-Version: 1.2<14>[ 29.161800] [IGT] kms_vblank: exiting, ret=77
12942 12:31:19.485793 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12943 12:31:19.488979 Opened device: /dev/dri/card0
12944 12:31:19.495446 N<8>[ 29.173257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12945 12:31:19.495719 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12947 12:31:19.498667 o KMS driver or no outputs, pipes: 8, outputs: 0
12948 12:31:19.505563 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12949 12:31:19.518008 <14>[ 29.198747] [IGT] kms_vblank: executing
12950 12:31:19.524629 IGT-Version: 1.2<14>[ 29.203773] [IGT] kms_vblank: exiting, ret=77
12951 12:31:19.527636 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12952 12:31:19.530879 Opened device: /dev/dri/card0
12953 12:31:19.537504 N<8>[ 29.215258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12954 12:31:19.537760 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12956 12:31:19.540875 o KMS driver or no outputs, pipes: 8, outputs: 0
12957 12:31:19.547541 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12958 12:31:19.560823 <14>[ 29.241452] [IGT] kms_vblank: executing
12959 12:31:19.566811 IGT-Version: 1.2<14>[ 29.246460] [IGT] kms_vblank: exiting, ret=77
12960 12:31:19.570745 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12961 12:31:19.574045 Opened device: /dev/dri/card0
12962 12:31:19.580653 N<8>[ 29.257908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12963 12:31:19.580958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12965 12:31:19.583909 o KMS driver or no outputs, pipes: 8, outputs: 0
12966 12:31:19.590143 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12967 12:31:19.603265 <14>[ 29.284070] [IGT] kms_vblank: executing
12968 12:31:19.609641 IGT-Version: 1.2<14>[ 29.289153] [IGT] kms_vblank: exiting, ret=77
12969 12:31:19.612869 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12970 12:31:19.616328 Opened device: /dev/dri/card0
12971 12:31:19.623195 N<8>[ 29.300350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12972 12:31:19.623456 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12974 12:31:19.629732 o KMS driver or no outputs, pipes: 8, outputs: 0
12975 12:31:19.633176 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12976 12:31:19.645973 <14>[ 29.326871] [IGT] kms_vblank: executing
12977 12:31:19.652488 IGT-Version: 1.2<14>[ 29.331866] [IGT] kms_vblank: exiting, ret=77
12978 12:31:19.655859 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12979 12:31:19.659197 Opened device: /dev/dri/card0
12980 12:31:19.665828 N<8>[ 29.343262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12981 12:31:19.666110 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
12983 12:31:19.672594 o KMS driver or no outputs, pipes: 8, outputs: 0
12984 12:31:19.675920 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
12985 12:31:19.688639 <14>[ 29.369975] [IGT] kms_vblank: executing
12986 12:31:19.695820 IGT-Version: 1.2<14>[ 29.374975] [IGT] kms_vblank: exiting, ret=77
12987 12:31:19.698720 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12988 12:31:19.702347 Opened device: /dev/dri/card0
12989 12:31:19.708633 N<8>[ 29.386555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
12990 12:31:19.708912 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
12992 12:31:19.715178 o KMS driver or no outputs, pipes: 8, outputs: 0
12993 12:31:19.718387 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
12994 12:31:19.732499 <14>[ 29.413454] [IGT] kms_vblank: executing
12995 12:31:19.739044 IGT-Version: 1.2<14>[ 29.418451] [IGT] kms_vblank: exiting, ret=77
12996 12:31:19.742328 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12997 12:31:19.745579 Opened device: /dev/dri/card0
12998 12:31:19.752274 N<8>[ 29.430020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
12999 12:31:19.752555 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13001 12:31:19.759044 o KMS driver or no outputs, pipes: 8, outputs: 0
13002 12:31:19.762290 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13003 12:31:19.775442 <14>[ 29.456658] [IGT] kms_vblank: executing
13004 12:31:19.782117 IGT-Version: 1.2<14>[ 29.461861] [IGT] kms_vblank: exiting, ret=77
13005 12:31:19.785326 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13006 12:31:19.788645 Opened device: /dev/dri/card0
13007 12:31:19.795480 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13009 12:31:19.798713 N<8>[ 29.473358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13010 12:31:19.801890 o KMS driver or no outputs, pipes: 8, outputs: 0
13011 12:31:19.808818 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13012 12:31:19.819460 <14>[ 29.500376] [IGT] kms_vblank: executing
13013 12:31:19.825927 IGT-Version: 1.2<14>[ 29.505581] [IGT] kms_vblank: exiting, ret=77
13014 12:31:19.829677 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13015 12:31:19.832864 Opened device: /dev/dri/card0
13016 12:31:19.839484 N<8>[ 29.516973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13017 12:31:19.839741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13019 12:31:19.845946 o KMS driver or no outputs, pipes: 8, outputs: 0
13020 12:31:19.849122 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13021 12:31:19.862604 <14>[ 29.543396] [IGT] kms_vblank: executing
13022 12:31:19.868878 IGT-Version: 1.2<14>[ 29.548442] [IGT] kms_vblank: exiting, ret=77
13023 12:31:19.872206 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13024 12:31:19.875451 Opened device: /dev/dri/card0
13025 12:31:19.881972 N<8>[ 29.559936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13026 12:31:19.882246 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13028 12:31:19.888686 o KMS driver or no outputs, pipes: 8, outputs: 0
13029 12:31:19.891910 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13030 12:31:19.905721 <14>[ 29.586684] [IGT] kms_vblank: executing
13031 12:31:19.912189 IGT-Version: 1.2<14>[ 29.591858] [IGT] kms_vblank: exiting, ret=77
13032 12:31:19.915811 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13033 12:31:19.919189 Opened device: /dev/dri/card0
13034 12:31:19.925316 N<8>[ 29.603285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13035 12:31:19.925569 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13037 12:31:19.932166 o KMS driver or no outputs, pipes: 8, outputs: 0
13038 12:31:19.938995 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13039 12:31:19.949457 <14>[ 29.630653] [IGT] kms_vblank: executing
13040 12:31:19.956229 IGT-Version: 1.2<14>[ 29.635709] [IGT] kms_vblank: exiting, ret=77
13041 12:31:19.959413 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13042 12:31:19.962625 Opened device: /dev/dri/card0
13043 12:31:19.969677 N<8>[ 29.647066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13044 12:31:19.969952 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13046 12:31:19.976193 o KMS driver or no outputs, pipes: 8, outputs: 0
13047 12:31:19.982901 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13048 12:31:19.993439 <14>[ 29.674348] [IGT] kms_vblank: executing
13049 12:31:20.000047 IGT-Version: 1.2<14>[ 29.679317] [IGT] kms_vblank: exiting, ret=77
13050 12:31:20.003443 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13051 12:31:20.006687 Opened device: /dev/dri/card0
13052 12:31:20.013331 N<8>[ 29.690785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13053 12:31:20.013582 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13055 12:31:20.016599 o KMS driver or no outputs, pipes: 8, outputs: 0
13056 12:31:20.023517 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13057 12:31:20.035802 <14>[ 29.716632] [IGT] kms_vblank: executing
13058 12:31:20.041950 IGT-Version: 1.2<14>[ 29.721816] [IGT] kms_vblank: exiting, ret=77
13059 12:31:20.045545 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13060 12:31:20.048694 Opened device: /dev/dri/card0
13061 12:31:20.055251 N<8>[ 29.733202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13062 12:31:20.055580 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13064 12:31:20.059050 o KMS driver or no outputs, pipes: 8, outputs: 0
13065 12:31:20.065598 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13066 12:31:20.077815 <14>[ 29.758705] [IGT] kms_vblank: executing
13067 12:31:20.084630 IGT-Version: 1.2<14>[ 29.763734] [IGT] kms_vblank: exiting, ret=77
13068 12:31:20.087864 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13069 12:31:20.091206 Opened device: /dev/dri/card0
13070 12:31:20.097954 N<8>[ 29.775323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13071 12:31:20.098217 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13073 12:31:20.101140 o KMS driver or no outputs, pipes: 8, outputs: 0
13074 12:31:20.107697 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13075 12:31:20.120708 <14>[ 29.801468] [IGT] kms_vblank: executing
13076 12:31:20.127189 IGT-Version: 1.2<14>[ 29.806462] [IGT] kms_vblank: exiting, ret=77
13077 12:31:20.130215 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13078 12:31:20.133330 Opened device: /dev/dri/card0
13079 12:31:20.140637 N<8>[ 29.817961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13080 12:31:20.140902 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13082 12:31:20.143728 o KMS driver or no outputs, pipes: 8, outputs: 0
13083 12:31:20.150075 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13084 12:31:20.162646 <14>[ 29.843515] [IGT] kms_vblank: executing
13085 12:31:20.168951 IGT-Version: 1.2<14>[ 29.848490] [IGT] kms_vblank: exiting, ret=77
13086 12:31:20.172695 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13087 12:31:20.175634 Opened device: /dev/dri/card0
13088 12:31:20.182525 N<8>[ 29.860034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13089 12:31:20.182782 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13091 12:31:20.185627 o KMS driver or no outputs, pipes: 8, outputs: 0
13092 12:31:20.192111 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13093 12:31:20.205272 <14>[ 29.886250] [IGT] kms_vblank: executing
13094 12:31:20.211937 IGT-Version: 1.2<14>[ 29.891362] [IGT] kms_vblank: exiting, ret=77
13095 12:31:20.215203 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13096 12:31:20.218331 Opened device: /dev/dri/card0
13097 12:31:20.224919 N<8>[ 29.902804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13098 12:31:20.225194 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13100 12:31:20.228202 o KMS driver or no outputs, pipes: 8, outputs: 0
13101 12:31:20.234958 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13102 12:31:20.247196 <14>[ 29.928329] [IGT] kms_vblank: executing
13103 12:31:20.254052 IGT-Version: 1.2<14>[ 29.933587] [IGT] kms_vblank: exiting, ret=77
13104 12:31:20.257127 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13105 12:31:20.260358 Opened device: /dev/dri/card0
13106 12:31:20.267191 N<8>[ 29.944720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13107 12:31:20.267459 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13109 12:31:20.270369 o KMS driver or no outputs, pipes: 8, outputs: 0
13110 12:31:20.276585 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13111 12:31:20.289666 <14>[ 29.970961] [IGT] kms_vblank: executing
13112 12:31:20.296327 IGT-Version: 1.2<14>[ 29.975986] [IGT] kms_vblank: exiting, ret=77
13113 12:31:20.299683 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13114 12:31:20.302965 Opened device: /dev/dri/card0
13115 12:31:20.309590 N<8>[ 29.987403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13116 12:31:20.309847 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13118 12:31:20.313029 o KMS driver or no outputs, pipes: 8, outputs: 0
13119 12:31:20.320153 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13120 12:31:20.333550 <14>[ 30.014697] [IGT] kms_vblank: executing
13121 12:31:20.340569 IGT-Version: 1.2<14>[ 30.019687] [IGT] kms_vblank: exiting, ret=77
13122 12:31:20.343526 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13123 12:31:20.346580 Opened device: /dev/dri/card0
13124 12:31:20.353635 N<8>[ 30.031347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13125 12:31:20.353891 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13127 12:31:20.359912 o KMS driver or no outputs, pipes: 8, outputs: 0
13128 12:31:20.362979 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13129 12:31:20.376979 <14>[ 30.058073] [IGT] kms_vblank: executing
13130 12:31:20.383789 IGT-Version: 1.2<14>[ 30.063168] [IGT] kms_vblank: exiting, ret=77
13131 12:31:20.386734 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13132 12:31:20.390304 Opened device: /dev/dri/card0
13133 12:31:20.396814 N<8>[ 30.074995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13134 12:31:20.397066 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13136 12:31:20.399941 o KMS driver or no outputs, pipes: 8, outputs: 0
13137 12:31:20.406393 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13138 12:31:20.419575 <14>[ 30.100259] [IGT] kms_vblank: executing
13139 12:31:20.425899 IGT-Version: 1.2<14>[ 30.105347] [IGT] kms_vblank: exiting, ret=77
13140 12:31:20.429261 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13141 12:31:20.432729 Opened device: /dev/dri/card0
13142 12:31:20.439408 N<8>[ 30.116760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13143 12:31:20.439763 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13145 12:31:20.442873 o KMS driver or no outputs, pipes: 8, outputs: 0
13146 12:31:20.449214 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13147 12:31:20.461929 <14>[ 30.142565] [IGT] kms_vblank: executing
13148 12:31:20.468223 IGT-Version: 1.2<14>[ 30.147648] [IGT] kms_vblank: exiting, ret=77
13149 12:31:20.471859 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13150 12:31:20.474651 Opened device: /dev/dri/card0
13151 12:31:20.481390 N<8>[ 30.159015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13152 12:31:20.481753 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13154 12:31:20.484535 o KMS driver or no outputs, pipes: 8, outputs: 0
13155 12:31:20.491229 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13156 12:31:20.503813 <14>[ 30.184907] [IGT] kms_vblank: executing
13157 12:31:20.510756 IGT-Version: 1.2<14>[ 30.190026] [IGT] kms_vblank: exiting, ret=77
13158 12:31:20.514174 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13159 12:31:20.517452 Opened device: /dev/dri/card0
13160 12:31:20.524118 N<8>[ 30.201472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13161 12:31:20.524463 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13163 12:31:20.527351 o KMS driver or no outputs, pipes: 8, outputs: 0
13164 12:31:20.534006 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13165 12:31:20.546741 <14>[ 30.227618] [IGT] kms_vblank: executing
13166 12:31:20.553365 IGT-Version: 1.2<14>[ 30.232619] [IGT] kms_vblank: exiting, ret=77
13167 12:31:20.556613 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13168 12:31:20.559894 Opened device: /dev/dri/card0
13169 12:31:20.566664 N<8>[ 30.244302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13170 12:31:20.567010 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13172 12:31:20.569567 o KMS driver or no outputs, pipes: 8, outputs: 0
13173 12:31:20.576558 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13174 12:31:20.588902 <14>[ 30.269696] [IGT] kms_vblank: executing
13175 12:31:20.595027 IGT-Version: 1.2<14>[ 30.274697] [IGT] kms_vblank: exiting, ret=77
13176 12:31:20.598724 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13177 12:31:20.601725 Opened device: /dev/dri/card0
13178 12:31:20.608522 N<8>[ 30.286225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13179 12:31:20.608907 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13181 12:31:20.611639 o KMS driver or no outputs, pipes: 8, outputs: 0
13182 12:31:20.618391 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13183 12:31:20.630900 <14>[ 30.312174] [IGT] kms_vblank: executing
13184 12:31:20.637456 IGT-Version: 1.2<14>[ 30.317200] [IGT] kms_vblank: exiting, ret=77
13185 12:31:20.640808 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13186 12:31:20.643987 Opened device: /dev/dri/card0
13187 12:31:20.650745 N<8>[ 30.328507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13188 12:31:20.651153 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13190 12:31:20.653984 o KMS driver or no outputs, pipes: 8, outputs: 0
13191 12:31:20.661155 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13192 12:31:20.673192 <14>[ 30.354587] [IGT] kms_vblank: executing
13193 12:31:20.680187 IGT-Version: 1.2<14>[ 30.359566] [IGT] kms_vblank: exiting, ret=77
13194 12:31:20.683453 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13195 12:31:20.686651 Opened device: /dev/dri/card0
13196 12:31:20.693404 N<8>[ 30.370969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13197 12:31:20.693792 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13199 12:31:20.699756 o KMS driver or no outputs, pipes: 8, outputs: 0
13200 12:31:20.703481 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13201 12:31:20.716549 <14>[ 30.397550] [IGT] kms_vblank: executing
13202 12:31:20.722832 IGT-Version: 1.2<14>[ 30.402543] [IGT] kms_vblank: exiting, ret=77
13203 12:31:20.726568 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13204 12:31:20.729926 Opened device: /dev/dri/card0
13205 12:31:20.736426 N<8>[ 30.414031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13206 12:31:20.736782 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13208 12:31:20.742888 o KMS driver or no outputs, pipes: 8, outputs: 0
13209 12:31:20.746132 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13210 12:31:20.760058 <14>[ 30.440901] [IGT] kms_vblank: executing
13211 12:31:20.766662 IGT-Version: 1.2<14>[ 30.445992] [IGT] kms_vblank: exiting, ret=77
13212 12:31:20.769950 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13213 12:31:20.773099 Opened device: /dev/dri/card0
13214 12:31:20.780133 N<8>[ 30.457524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13215 12:31:20.780391 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13217 12:31:20.786466 o KMS driver or no outputs, pipes: 8, outputs: 0
13218 12:31:20.790086 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13219 12:31:20.803205 <14>[ 30.484379] [IGT] kms_vblank: executing
13220 12:31:20.810018 IGT-Version: 1.2<14>[ 30.489587] [IGT] kms_vblank: exiting, ret=77
13221 12:31:20.813314 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13222 12:31:20.816552 Opened device: /dev/dri/card0
13223 12:31:20.823308 N<8>[ 30.500802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13224 12:31:20.823607 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13226 12:31:20.830286 o KMS driver or no outputs, pipes: 8, outputs: 0
13227 12:31:20.832806 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13228 12:31:20.846768 <14>[ 30.527720] [IGT] kms_vblank: executing
13229 12:31:20.852848 IGT-Version: 1.2<14>[ 30.532829] [IGT] kms_vblank: exiting, ret=77
13230 12:31:20.856221 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13231 12:31:20.859659 Opened device: /dev/dri/card0
13232 12:31:20.866443 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13234 12:31:20.869506 N<8>[ 30.544300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13235 12:31:20.872829 o KMS driver or no outputs, pipes: 8, outputs: 0
13236 12:31:20.879218 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13237 12:31:20.890344 <14>[ 30.571253] [IGT] kms_vblank: executing
13238 12:31:20.896719 IGT-Version: 1.2<14>[ 30.576270] [IGT] kms_vblank: exiting, ret=77
13239 12:31:20.900294 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13240 12:31:20.903493 Opened device: /dev/dri/card0
13241 12:31:20.910441 N<8>[ 30.587737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13242 12:31:20.910693 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13244 12:31:20.916788 o KMS driver or no outputs, pipes: 8, outputs: 0
13245 12:31:20.920345 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13246 12:31:20.934231 <14>[ 30.615479] [IGT] kms_vblank: executing
13247 12:31:20.941145 IGT-Version: 1.2<14>[ 30.620835] [IGT] kms_vblank: exiting, ret=77
13248 12:31:20.944265 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13249 12:31:20.947722 Opened device: /dev/dri/card0
13250 12:31:20.954326 N<8>[ 30.632302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13251 12:31:20.954589 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13253 12:31:20.960930 o KMS driver or no outputs, pipes: 8, outputs: 0
13254 12:31:20.964271 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13255 12:31:20.977652 <14>[ 30.659047] [IGT] kms_vblank: executing
13256 12:31:20.984724 IGT-Version: 1.2<14>[ 30.664061] [IGT] kms_vblank: exiting, ret=77
13257 12:31:20.987914 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13258 12:31:20.991268 Opened device: /dev/dri/card0
13259 12:31:20.997881 N<8>[ 30.675534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13260 12:31:20.998157 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13262 12:31:21.004449 o KMS driver or no outputs, pipes: 8, outputs: 0
13263 12:31:21.011196 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13264 12:31:21.021501 <14>[ 30.702667] [IGT] kms_vblank: executing
13265 12:31:21.028308 IGT-Version: 1.2<14>[ 30.707718] [IGT] kms_vblank: exiting, ret=77
13266 12:31:21.031272 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13267 12:31:21.034396 Opened device: /dev/dri/card0
13268 12:31:21.041663 N<8>[ 30.719057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13269 12:31:21.041941 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13271 12:31:21.047844 o KMS driver or no outputs, pipes: 8, outputs: 0
13272 12:31:21.054669 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13273 12:31:21.065097 <14>[ 30.746414] [IGT] kms_vblank: executing
13274 12:31:21.071687 IGT-Version: 1.2<14>[ 30.751396] [IGT] kms_vblank: exiting, ret=77
13275 12:31:21.074895 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13276 12:31:21.078818 Opened device: /dev/dri/card0
13277 12:31:21.085270 N<8>[ 30.762840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13278 12:31:21.085524 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13280 12:31:21.088428 o KMS driver or no outputs, pipes: 8, outputs: 0
13281 12:31:21.094958 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13282 12:31:21.108113 <14>[ 30.788973] [IGT] kms_vblank: executing
13283 12:31:21.114053 IGT-Version: 1.2<14>[ 30.793975] [IGT] kms_vblank: exiting, ret=77
13284 12:31:21.117818 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13285 12:31:21.120861 Opened device: /dev/dri/card0
13286 12:31:21.127786 N<8>[ 30.805434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13287 12:31:21.128045 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13289 12:31:21.131140 o KMS driver or no outputs, pipes: 8, outputs: 0
13290 12:31:21.137383 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13291 12:31:21.150087 <14>[ 30.831060] [IGT] kms_vblank: executing
13292 12:31:21.156441 IGT-Version: 1.2<14>[ 30.836166] [IGT] kms_vblank: exiting, ret=77
13293 12:31:21.159562 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13294 12:31:21.163521 Opened device: /dev/dri/card0
13295 12:31:21.170164 N<8>[ 30.847640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13296 12:31:21.170432 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13298 12:31:21.173272 o KMS driver or no outputs, pipes: 8, outputs: 0
13299 12:31:21.179711 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13300 12:31:21.192648 <14>[ 30.873790] [IGT] kms_vblank: executing
13301 12:31:21.199305 IGT-Version: 1.2<14>[ 30.878865] [IGT] kms_vblank: exiting, ret=77
13302 12:31:21.202707 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13303 12:31:21.205887 Opened device: /dev/dri/card0
13304 12:31:21.212447 N<8>[ 30.890373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13305 12:31:21.212694 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13307 12:31:21.215815 o KMS driver or no outputs, pipes: 8, outputs: 0
13308 12:31:21.222296 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13309 12:31:21.235164 <14>[ 30.916282] [IGT] kms_vblank: executing
13310 12:31:21.241734 IGT-Version: 1.2<14>[ 30.921527] [IGT] kms_vblank: exiting, ret=77
13311 12:31:21.244975 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13312 12:31:21.248486 Opened device: /dev/dri/card0
13313 12:31:21.255174 N<8>[ 30.933337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13314 12:31:21.255429 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13316 12:31:21.261991 o KMS driver or no outputs, pipes: 8, outputs: 0
13317 12:31:21.265140 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13318 12:31:21.278710 <14>[ 30.960018] [IGT] kms_vblank: executing
13319 12:31:21.285225 IGT-Version: 1.2<14>[ 30.965061] [IGT] kms_vblank: exiting, ret=77
13320 12:31:21.288584 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13321 12:31:21.291927 Opened device: /dev/dri/card0
13322 12:31:21.298322 N<8>[ 30.976469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13323 12:31:21.298587 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13325 12:31:21.301576 o KMS driver or no outputs, pipes: 8, outputs: 0
13326 12:31:21.308367 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13327 12:31:21.321331 <14>[ 31.002459] [IGT] kms_vblank: executing
13328 12:31:21.327937 IGT-Version: 1.2<14>[ 31.007448] [IGT] kms_vblank: exiting, ret=77
13329 12:31:21.331043 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13330 12:31:21.334232 Opened device: /dev/dri/card0
13331 12:31:21.340958 N<8>[ 31.019255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13332 12:31:21.341219 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13334 12:31:21.344690 o KMS driver or no outputs, pipes: 8, outputs: 0
13335 12:31:21.351113 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13336 12:31:21.364669 <14>[ 31.045918] [IGT] kms_vblank: executing
13337 12:31:21.371276 IGT-Version: 1.2<14>[ 31.050902] [IGT] kms_vblank: exiting, ret=77
13338 12:31:21.374380 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13339 12:31:21.378196 Opened device: /dev/dri/card0
13340 12:31:21.384759 N<8>[ 31.062523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13341 12:31:21.385005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13343 12:31:21.387959 o KMS driver or no outputs, pipes: 8, outputs: 0
13344 12:31:21.394556 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13345 12:31:21.407809 <14>[ 31.088872] [IGT] kms_vblank: executing
13346 12:31:21.414330 IGT-Version: 1.2<14>[ 31.093975] [IGT] kms_vblank: exiting, ret=77
13347 12:31:21.417466 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13348 12:31:21.421325 Opened device: /dev/dri/card0
13349 12:31:21.427902 N<8>[ 31.106107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13350 12:31:21.428149 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13352 12:31:21.434564 o KMS driver or no outputs, pipes: 8, outputs: 0
13353 12:31:21.437775 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13354 12:31:21.450909 <14>[ 31.131974] [IGT] kms_vblank: executing
13355 12:31:21.457652 IGT-Version: 1.2<14>[ 31.137015] [IGT] kms_vblank: exiting, ret=77
13356 12:31:21.460936 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13357 12:31:21.464132 Opened device: /dev/dri/card0
13358 12:31:21.470907 N<8>[ 31.148815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13359 12:31:21.471161 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13361 12:31:21.473867 o KMS driver or no outputs, pipes: 8, outputs: 0
13362 12:31:21.480543 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13363 12:31:21.493977 <14>[ 31.175215] [IGT] kms_vblank: executing
13364 12:31:21.500716 IGT-Version: 1.2<14>[ 31.180284] [IGT] kms_vblank: exiting, ret=77
13365 12:31:21.503941 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13366 12:31:21.507149 Opened device: /dev/dri/card0
13367 12:31:21.513761 N<8>[ 31.192007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13368 12:31:21.514015 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13370 12:31:21.517119 o KMS driver or no outputs, pipes: 8, outputs: 0
13371 12:31:21.523475 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13372 12:31:21.537907 <14>[ 31.218891] [IGT] kms_vblank: executing
13373 12:31:21.544506 IGT-Version: 1.2<14>[ 31.223842] [IGT] kms_vblank: exiting, ret=77
13374 12:31:21.547787 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13375 12:31:21.550967 Opened device: /dev/dri/card0
13376 12:31:21.557839 N<8>[ 31.236000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13377 12:31:21.558106 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13379 12:31:21.561139 o KMS driver or no outputs, pipes: 8, outputs: 0
13380 12:31:21.567470 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13381 12:31:21.580186 <14>[ 31.261242] [IGT] kms_vblank: executing
13382 12:31:21.586987 IGT-Version: 1.2<14>[ 31.266360] [IGT] kms_vblank: exiting, ret=77
13383 12:31:21.590273 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13384 12:31:21.593213 Opened device: /dev/dri/card0
13385 12:31:21.600202 N<8>[ 31.277840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13386 12:31:21.600461 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13388 12:31:21.603309 o KMS driver or no outputs, pipes: 8, outputs: 0
13389 12:31:21.610161 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13390 12:31:21.622577 <14>[ 31.303967] [IGT] kms_vblank: executing
13391 12:31:21.629665 IGT-Version: 1.2<14>[ 31.309009] [IGT] kms_vblank: exiting, ret=77
13392 12:31:21.632979 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13393 12:31:21.636347 Opened device: /dev/dri/card0
13394 12:31:21.643007 N<8>[ 31.320282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13395 12:31:21.643309 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13397 12:31:21.646200 o KMS driver or no outputs, pipes: 8, outputs: 0
13398 12:31:21.652595 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13399 12:31:21.664890 <14>[ 31.345936] [IGT] kms_vblank: executing
13400 12:31:21.671248 IGT-Version: 1.2<14>[ 31.350924] [IGT] kms_vblank: exiting, ret=77
13401 12:31:21.674708 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13402 12:31:21.678024 Opened device: /dev/dri/card0
13403 12:31:21.684509 N<8>[ 31.362487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13404 12:31:21.684765 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13406 12:31:21.688410 o KMS driver or no outputs, pipes: 8, outputs: 0
13407 12:31:21.694094 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13408 12:31:21.707564 <14>[ 31.388572] [IGT] kms_vblank: executing
13409 12:31:21.713861 IGT-Version: 1.2<14>[ 31.393744] [IGT] kms_vblank: exiting, ret=77
13410 12:31:21.717051 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13411 12:31:21.720275 Opened device: /dev/dri/card0
13412 12:31:21.727038 N<8>[ 31.405161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13413 12:31:21.727285 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13415 12:31:21.734008 o KMS driver or no outputs, pipes: 8, outputs: 0
13416 12:31:21.736590 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13417 12:31:21.749881 <14>[ 31.431347] [IGT] kms_vblank: executing
13418 12:31:21.756545 IGT-Version: 1.2<14>[ 31.436383] [IGT] kms_vblank: exiting, ret=77
13419 12:31:21.759856 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13420 12:31:21.763656 Opened device: /dev/dri/card0
13421 12:31:21.770041 N<8>[ 31.447752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13422 12:31:21.770340 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13424 12:31:21.776682 o KMS driver or no outputs, pipes: 8, outputs: 0
13425 12:31:21.780085 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13426 12:31:21.793156 <14>[ 31.474372] [IGT] kms_vblank: executing
13427 12:31:21.799871 IGT-Version: 1.2<14>[ 31.479366] [IGT] kms_vblank: exiting, ret=77
13428 12:31:21.803311 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13429 12:31:21.806673 Opened device: /dev/dri/card0
13430 12:31:21.813179 N<8>[ 31.490815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13431 12:31:21.813448 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13433 12:31:21.819274 o KMS driver or no outputs, pipes: 8, outputs: 0
13434 12:31:21.823138 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13435 12:31:21.836203 <14>[ 31.517344] [IGT] kms_vblank: executing
13436 12:31:21.842860 IGT-Version: 1.2<14>[ 31.522380] [IGT] kms_vblank: exiting, ret=77
13437 12:31:21.846033 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13438 12:31:21.849355 Opened device: /dev/dri/card0
13439 12:31:21.856037 N<8>[ 31.533830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13440 12:31:21.856330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13442 12:31:21.863052 o KMS driver or no outputs, pipes: 8, outputs: 0
13443 12:31:21.866204 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13444 12:31:21.879573 <14>[ 31.560717] [IGT] kms_vblank: executing
13445 12:31:21.886225 IGT-Version: 1.2<14>[ 31.565872] [IGT] kms_vblank: exiting, ret=77
13446 12:31:21.889592 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13447 12:31:21.892748 Opened device: /dev/dri/card0
13448 12:31:21.899544 N<8>[ 31.577323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13449 12:31:21.899845 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13451 12:31:21.906241 o KMS driver or no outputs, pipes: 8, outputs: 0
13452 12:31:21.909365 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13453 12:31:21.923033 <14>[ 31.604072] [IGT] kms_vblank: executing
13454 12:31:21.929246 IGT-Version: 1.2<14>[ 31.609162] [IGT] kms_vblank: exiting, ret=77
13455 12:31:21.932531 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13456 12:31:21.936257 Opened device: /dev/dri/card0
13457 12:31:21.942853 N<8>[ 31.620367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13458 12:31:21.943145 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13460 12:31:21.949290 o KMS driver or no outputs, pipes: 8, outputs: 0
13461 12:31:21.955971 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13462 12:31:21.966470 <14>[ 31.647636] [IGT] kms_vblank: executing
13463 12:31:21.972659 IGT-Version: 1.2<14>[ 31.652623] [IGT] kms_vblank: exiting, ret=77
13464 12:31:21.975969 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13465 12:31:21.979656 Opened device: /dev/dri/card0
13466 12:31:21.986476 N<8>[ 31.664065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13467 12:31:21.986729 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13469 12:31:21.992951 o KMS driver or no outputs, pipes: 8, outputs: 0
13470 12:31:21.996266 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13471 12:31:22.009459 <14>[ 31.690827] [IGT] kms_vblank: executing
13472 12:31:22.016188 IGT-Version: 1.2<14>[ 31.695953] [IGT] kms_vblank: exiting, ret=77
13473 12:31:22.019249 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13474 12:31:22.023019 Opened device: /dev/dri/card0
13475 12:31:22.029378 N<8>[ 31.707319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13476 12:31:22.029671 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13478 12:31:22.036169 o KMS driver or no outputs, pipes: 8, outputs: 0
13479 12:31:22.039444 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13480 12:31:22.052502 <14>[ 31.734035] [IGT] kms_vblank: executing
13481 12:31:22.059152 IGT-Version: 1.2<14>[ 31.739064] [IGT] kms_vblank: exiting, ret=77
13482 12:31:22.062468 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13483 12:31:22.065691 Opened device: /dev/dri/card0
13484 12:31:22.072937 N<8>[ 31.750581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13485 12:31:22.073214 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13487 12:31:22.079523 o KMS driver or no outputs, pipes: 8, outputs: 0
13488 12:31:22.086003 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13489 12:31:22.096893 <14>[ 31.777875] [IGT] kms_vblank: executing
13490 12:31:22.102946 IGT-Version: 1.2<14>[ 31.782909] [IGT] kms_vblank: exiting, ret=77
13491 12:31:22.106363 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13492 12:31:22.109603 Opened device: /dev/dri/card0
13493 12:31:22.116202 N<8>[ 31.794417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13494 12:31:22.116487 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13496 12:31:22.123035 o KMS driver or no outputs, pipes: 8, outputs: 0
13497 12:31:22.129733 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13498 12:31:22.140609 <14>[ 31.821503] [IGT] kms_vblank: executing
13499 12:31:22.146722 IGT-Version: 1.2<14>[ 31.826495] [IGT] kms_vblank: exiting, ret=77
13500 12:31:22.150268 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13501 12:31:22.153254 Opened device: /dev/dri/card0
13502 12:31:22.160320 N<8>[ 31.837932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13503 12:31:22.160641 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13505 12:31:22.163593 o KMS driver or no outputs, pipes: 8, outputs: 0
13506 12:31:22.170189 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13507 12:31:22.182270 <14>[ 31.863777] [IGT] kms_vblank: executing
13508 12:31:22.189375 IGT-Version: 1.2<14>[ 31.868745] [IGT] kms_vblank: exiting, ret=77
13509 12:31:22.192505 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13510 12:31:22.195693 Opened device: /dev/dri/card0
13511 12:31:22.202636 N<8>[ 31.880131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13512 12:31:22.202891 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13514 12:31:22.206129 o KMS driver or no outputs, pipes: 8, outputs: 0
13515 12:31:22.212624 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13516 12:31:22.224415 <14>[ 31.905870] [IGT] kms_vblank: executing
13517 12:31:22.231206 IGT-Version: 1.2<14>[ 31.910877] [IGT] kms_vblank: exiting, ret=77
13518 12:31:22.234338 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13519 12:31:22.237850 Opened device: /dev/dri/card0
13520 12:31:22.244282 N<8>[ 31.922378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13521 12:31:22.244535 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13523 12:31:22.248217 o KMS driver or no outputs, pipes: 8, outputs: 0
13524 12:31:22.254709 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13525 12:31:22.267183 <14>[ 31.948429] [IGT] kms_vblank: executing
13526 12:31:22.273738 IGT-Version: 1.2<14>[ 31.953679] [IGT] kms_vblank: exiting, ret=77
13527 12:31:22.277030 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13528 12:31:22.280389 Opened device: /dev/dri/card0
13529 12:31:22.286890 N<8>[ 31.965542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13530 12:31:22.287149 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13532 12:31:22.290118 o KMS driver or no outputs, pipes: 8, outputs: 0
13533 12:31:22.297226 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13534 12:31:22.310834 <14>[ 31.991950] [IGT] kms_vblank: executing
13535 12:31:22.317392 IGT-Version: 1.2<14>[ 31.997046] [IGT] kms_vblank: exiting, ret=77
13536 12:31:22.320583 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13537 12:31:22.323870 Opened device: /dev/dri/card0
13538 12:31:22.330595 N<8>[ 32.008572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13539 12:31:22.330854 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13541 12:31:22.333868 o KMS driver or no outputs, pipes: 8, outputs: 0
13542 12:31:22.340679 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13543 12:31:22.353465 <14>[ 32.034397] [IGT] kms_vblank: executing
13544 12:31:22.359938 IGT-Version: 1.2<14>[ 32.039480] [IGT] kms_vblank: exiting, ret=77
13545 12:31:22.363083 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13546 12:31:22.366421 Opened device: /dev/dri/card0
13547 12:31:22.373131 N<8>[ 32.050885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13548 12:31:22.373388 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13550 12:31:22.376380 o KMS driver or no outputs, pipes: 8, outputs: 0
13551 12:31:22.383075 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13552 12:31:22.395628 <14>[ 32.076575] [IGT] kms_vblank: executing
13553 12:31:22.402197 IGT-Version: 1.2<14>[ 32.081825] [IGT] kms_vblank: exiting, ret=77
13554 12:31:22.405353 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13555 12:31:22.408410 Opened device: /dev/dri/card0
13556 12:31:22.415101 N<8>[ 32.093171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13557 12:31:22.415397 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13559 12:31:22.418232 o KMS driver or no outputs, pipes: 8, outputs: 0
13560 12:31:22.424797 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13561 12:31:22.437332 <14>[ 32.118948] [IGT] kms_vblank: executing
13562 12:31:22.444346 IGT-Version: 1.2<14>[ 32.124051] [IGT] kms_vblank: exiting, ret=77
13563 12:31:22.447480 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13564 12:31:22.450809 Opened device: /dev/dri/card0
13565 12:31:22.457226 N<8>[ 32.135405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13566 12:31:22.457482 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13568 12:31:22.463756 o KMS driver or no outputs, pipes: 8, outputs: 0
13569 12:31:22.467017 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13570 12:31:22.481151 <14>[ 32.162560] [IGT] kms_vblank: executing
13571 12:31:22.487744 IGT-Version: 1.2<14>[ 32.167816] [IGT] kms_vblank: exiting, ret=77
13572 12:31:22.491119 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13573 12:31:22.494340 Opened device: /dev/dri/card0
13574 12:31:22.501111 N<8>[ 32.179220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13575 12:31:22.501403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13577 12:31:22.507584 o KMS driver or no outputs, pipes: 8, outputs: 0
13578 12:31:22.510809 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13579 12:31:22.524969 <14>[ 32.206362] [IGT] kms_vblank: executing
13580 12:31:22.531774 IGT-Version: 1.2<14>[ 32.211381] [IGT] kms_vblank: exiting, ret=77
13581 12:31:22.535067 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13582 12:31:22.538395 Opened device: /dev/dri/card0
13583 12:31:22.544940 N<8>[ 32.223300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13584 12:31:22.545194 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13586 12:31:22.548018 o KMS driver or no outputs, pipes: 8, outputs: 0
13587 12:31:22.554857 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13588 12:31:22.566915 <14>[ 32.248538] [IGT] kms_vblank: executing
13589 12:31:22.573972 IGT-Version: 1.2<14>[ 32.253776] [IGT] kms_vblank: exiting, ret=77
13590 12:31:22.577323 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13591 12:31:22.580071 Opened device: /dev/dri/card0
13592 12:31:22.587420 N<8>[ 32.265220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13593 12:31:22.587686 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13595 12:31:22.590443 o KMS driver or no outputs, pipes: 8, outputs: 0
13596 12:31:22.597028 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13597 12:31:22.609608 <14>[ 32.290931] [IGT] kms_vblank: executing
13598 12:31:22.615995 IGT-Version: 1.2<14>[ 32.296024] [IGT] kms_vblank: exiting, ret=77
13599 12:31:22.619295 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13600 12:31:22.623181 Opened device: /dev/dri/card0
13601 12:31:22.629257 N<8>[ 32.307436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13602 12:31:22.629527 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13604 12:31:22.632892 o KMS driver or no outputs, pipes: 8, outputs: 0
13605 12:31:22.639611 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13606 12:31:22.651868 <14>[ 32.333176] [IGT] kms_vblank: executing
13607 12:31:22.658792 IGT-Version: 1.2<14>[ 32.338315] [IGT] kms_vblank: exiting, ret=77
13608 12:31:22.661915 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13609 12:31:22.665079 Opened device: /dev/dri/card0
13610 12:31:22.671414 N<8>[ 32.349794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13611 12:31:22.671676 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13613 12:31:22.675192 o KMS driver or no outputs, pipes: 8, outputs: 0
13614 12:31:22.681732 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13615 12:31:22.694274 <14>[ 32.375841] [IGT] kms_vblank: executing
13616 12:31:22.701278 IGT-Version: 1.2<14>[ 32.381050] [IGT] kms_vblank: exiting, ret=77
13617 12:31:22.704619 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13618 12:31:22.707981 Opened device: /dev/dri/card0
13619 12:31:22.713994 N<8>[ 32.392673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13620 12:31:22.714265 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13622 12:31:22.717787 o KMS driver or no outputs, pipes: 8, outputs: 0
13623 12:31:22.724366 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13624 12:31:22.737748 <14>[ 32.419323] [IGT] kms_vblank: executing
13625 12:31:22.744474 IGT-Version: 1.2<14>[ 32.424281] [IGT] kms_vblank: exiting, ret=77
13626 12:31:22.747524 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13627 12:31:22.750830 Opened device: /dev/dri/card0
13628 12:31:22.758057 N<8>[ 32.436549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13629 12:31:22.758314 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13631 12:31:22.761134 o KMS driver or no outputs, pipes: 8, outputs: 0
13632 12:31:22.768024 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13633 12:31:22.781778 <14>[ 32.463177] [IGT] kms_vblank: executing
13634 12:31:22.788500 IGT-Version: 1.2<14>[ 32.468153] [IGT] kms_vblank: exiting, ret=77
13635 12:31:22.791659 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13636 12:31:22.794920 Opened device: /dev/dri/card0
13637 12:31:22.801554 N<8>[ 32.480127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13638 12:31:22.801805 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13640 12:31:22.805359 o KMS driver or no outputs, pipes: 8, outputs: 0
13641 12:31:22.811833 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13642 12:31:22.824561 <14>[ 32.505822] [IGT] kms_vblank: executing
13643 12:31:22.831125 IGT-Version: 1.2<14>[ 32.510899] [IGT] kms_vblank: exiting, ret=77
13644 12:31:22.834516 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13645 12:31:22.837987 Opened device: /dev/dri/card0
13646 12:31:22.844126 N<8>[ 32.522478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13647 12:31:22.844377 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13649 12:31:22.850874 o KMS driver or no outputs, pipes: 8, outputs: 0
13650 12:31:22.854190 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13651 12:31:22.867987 <14>[ 32.549219] [IGT] kms_vblank: executing
13652 12:31:22.874315 IGT-Version: 1.2<14>[ 32.554308] [IGT] kms_vblank: exiting, ret=77
13653 12:31:22.877948 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13654 12:31:22.881086 Opened device: /dev/dri/card0
13655 12:31:22.887757 N<8>[ 32.565694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13656 12:31:22.888019 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13658 12:31:22.894260 o KMS driver or no outputs, pipes: 8, outputs: 0
13659 12:31:22.897399 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13660 12:31:22.910430 <14>[ 32.591916] [IGT] kms_vblank: executing
13661 12:31:22.917016 IGT-Version: 1.2<14>[ 32.597079] [IGT] kms_vblank: exiting, ret=77
13662 12:31:22.920215 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13663 12:31:22.924082 Opened device: /dev/dri/card0
13664 12:31:22.930554 N<8>[ 32.608323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13665 12:31:22.930809 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13667 12:31:22.937219 o KMS driver or no outputs, pipes: 8, outputs: 0
13668 12:31:22.940662 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13669 12:31:22.953847 <14>[ 32.635041] [IGT] kms_vblank: executing
13670 12:31:22.960135 IGT-Version: 1.2<14>[ 32.640158] [IGT] kms_vblank: exiting, ret=77
13671 12:31:22.963879 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13672 12:31:22.966950 Opened device: /dev/dri/card0
13673 12:31:22.973457 N<8>[ 32.651510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13674 12:31:22.973712 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13676 12:31:22.980262 o KMS driver or no outputs, pipes: 8, outputs: 0
13677 12:31:22.983320 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13678 12:31:22.996908 <14>[ 32.678281] [IGT] kms_vblank: executing
13679 12:31:23.004183 IGT-Version: 1.2<14>[ 32.683387] [IGT] kms_vblank: exiting, ret=77
13680 12:31:23.007478 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13681 12:31:23.010267 Opened device: /dev/dri/card0
13682 12:31:23.017256 N<8>[ 32.694924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13683 12:31:23.017936 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13685 12:31:23.024126 o KMS driver or no outputs, pipes: 8, outputs: 0
13686 12:31:23.030425 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13687 12:31:23.041022 <14>[ 32.721890] [IGT] kms_vblank: executing
13688 12:31:23.047614 IGT-Version: 1.2<14>[ 32.727026] [IGT] kms_vblank: exiting, ret=77
13689 12:31:23.050914 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13690 12:31:23.054258 Opened device: /dev/dri/card0
13691 12:31:23.060644 N<8>[ 32.738687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13692 12:31:23.061532 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13694 12:31:23.066871 o KMS driver or no outputs, pipes: 8, outputs: 0
13695 12:31:23.070501 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13696 12:31:23.084008 <14>[ 32.765152] [IGT] kms_vblank: executing
13697 12:31:23.091131 IGT-Version: 1.2<14>[ 32.770248] [IGT] kms_vblank: exiting, ret=77
13698 12:31:23.094270 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13699 12:31:23.097213 Opened device: /dev/dri/card0
13700 12:31:23.104156 N<8>[ 32.781595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13701 12:31:23.104842 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13703 12:31:23.110900 o KMS driver or no outputs, pipes: 8, outputs: 0
13704 12:31:23.114148 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13705 12:31:23.127317 <14>[ 32.808553] [IGT] kms_vblank: executing
13706 12:31:23.133912 IGT-Version: 1.2<14>[ 32.813808] [IGT] kms_vblank: exiting, ret=77
13707 12:31:23.137091 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13708 12:31:23.140375 Opened device: /dev/dri/card0
13709 12:31:23.147189 N<8>[ 32.824903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13710 12:31:23.147468 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13712 12:31:23.153743 o KMS driver or no outputs, pipes: 8, outputs: 0
13713 12:31:23.160800 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13714 12:31:23.171483 <14>[ 32.852132] [IGT] kms_vblank: executing
13715 12:31:23.177589 IGT-Version: 1.2<14>[ 32.857226] [IGT] kms_vblank: exiting, ret=77
13716 12:31:23.181253 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13717 12:31:23.184394 Opened device: /dev/dri/card0
13718 12:31:23.191182 N<8>[ 32.868287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13719 12:31:23.191890 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13721 12:31:23.197294 o KMS driver or no outputs, pipes: 8, outputs: 0
13722 12:31:23.200757 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13723 12:31:23.214528 <14>[ 32.895772] [IGT] kms_vblank: executing
13724 12:31:23.221621 IGT-Version: 1.2<14>[ 32.900793] [IGT] kms_vblank: exiting, ret=77
13725 12:31:23.224960 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13726 12:31:23.228077 Opened device: /dev/dri/card0
13727 12:31:23.234639 N<8>[ 32.912178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13728 12:31:23.235452 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13730 12:31:23.237971 o KMS driver or no outputs, pipes: 8, outputs: 0
13731 12:31:23.244257 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13732 12:31:23.256805 <14>[ 32.937992] [IGT] kms_vblank: executing
13733 12:31:23.263414 IGT-Version: 1.2<14>[ 32.943104] [IGT] kms_vblank: exiting, ret=77
13734 12:31:23.266936 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13735 12:31:23.270574 Opened device: /dev/dri/card0
13736 12:31:23.277148 N<8>[ 32.954684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13737 12:31:23.277838 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13739 12:31:23.280343 o KMS driver or no outputs, pipes: 8, outputs: 0
13740 12:31:23.286483 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13741 12:31:23.299445 <14>[ 32.980297] [IGT] kms_vblank: executing
13742 12:31:23.306124 IGT-Version: 1.2<14>[ 32.985520] [IGT] kms_vblank: exiting, ret=77
13743 12:31:23.309347 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13744 12:31:23.312581 Opened device: /dev/dri/card0
13745 12:31:23.319353 N<8>[ 32.997022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13746 12:31:23.320083 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13748 12:31:23.322439 o KMS driver or no outputs, pipes: 8, outputs: 0
13749 12:31:23.328740 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13750 12:31:23.342323 <14>[ 33.022966] [IGT] kms_vblank: executing
13751 12:31:23.348629 IGT-Version: 1.2<14>[ 33.028073] [IGT] kms_vblank: exiting, ret=77
13752 12:31:23.351947 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13753 12:31:23.355065 Opened device: /dev/dri/card0
13754 12:31:23.361724 N<8>[ 33.039404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13755 12:31:23.362583 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13757 12:31:23.364999 o KMS driver or no outputs, pipes: 8, outputs: 0
13758 12:31:23.371787 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13759 12:31:23.384203 <14>[ 33.065366] [IGT] kms_vblank: executing
13760 12:31:23.390738 IGT-Version: 1.2<14>[ 33.070374] [IGT] kms_vblank: exiting, ret=77
13761 12:31:23.394502 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13762 12:31:23.397414 Opened device: /dev/dri/card0
13763 12:31:23.403961 N<8>[ 33.082032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13764 12:31:23.404871 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13766 12:31:23.410728 o KMS driver or no outputs, pipes: 8, outputs: 0
13767 12:31:23.413678 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13768 12:31:23.426792 <14>[ 33.108053] [IGT] kms_vblank: executing
13769 12:31:23.433581 IGT-Version: 1.2<14>[ 33.113146] [IGT] kms_vblank: exiting, ret=77
13770 12:31:23.437420 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13771 12:31:23.440271 Opened device: /dev/dri/card0
13772 12:31:23.447141 N<8>[ 33.124386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13773 12:31:23.448145 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13775 12:31:23.450080 o KMS driver or no outputs, pipes: 8, outputs: 0
13776 12:31:23.456603 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13777 12:31:23.469348 <14>[ 33.150131] [IGT] kms_vblank: executing
13778 12:31:23.475990 IGT-Version: 1.2<14>[ 33.155258] [IGT] kms_vblank: exiting, ret=77
13779 12:31:23.479276 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13780 12:31:23.482060 Opened device: /dev/dri/card0
13781 12:31:23.489179 N<8>[ 33.166714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13782 12:31:23.490099 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13784 12:31:23.492533 o KMS driver or no outputs, pipes: 8, outputs: 0
13785 12:31:23.498945 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13786 12:31:23.511402 <14>[ 33.192496] [IGT] kms_vblank: executing
13787 12:31:23.517918 IGT-Version: 1.2<14>[ 33.197777] [IGT] kms_vblank: exiting, ret=77
13788 12:31:23.521513 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13789 12:31:23.524680 Opened device: /dev/dri/card0
13790 12:31:23.531797 N<8>[ 33.209216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13791 12:31:23.532623 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13793 12:31:23.534873 o KMS driver or no outputs, pipes: 8, outputs: 0
13794 12:31:23.541646 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13795 12:31:23.553912 <14>[ 33.235279] [IGT] kms_vblank: executing
13796 12:31:23.560964 IGT-Version: 1.2<14>[ 33.240267] [IGT] kms_vblank: exiting, ret=77
13797 12:31:23.564560 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13798 12:31:23.567556 Opened device: /dev/dri/card0
13799 12:31:23.574262 N<8>[ 33.251895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13800 12:31:23.574996 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13802 12:31:23.580788 o KMS driver or no outputs, pipes: 8, outputs: 0
13803 12:31:23.583970 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13804 12:31:23.597188 <14>[ 33.278466] [IGT] kms_vblank: executing
13805 12:31:23.604314 IGT-Version: 1.2<14>[ 33.283505] [IGT] kms_vblank: exiting, ret=77
13806 12:31:23.607034 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13807 12:31:23.610323 Opened device: /dev/dri/card0
13808 12:31:23.617425 N<8>[ 33.294931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13809 12:31:23.618224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13811 12:31:23.620504 o KMS driver or no outputs, pipes: 8, outputs: 0
13812 12:31:23.627120 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13813 12:31:23.639602 <14>[ 33.320542] [IGT] kms_vblank: executing
13814 12:31:23.645798 IGT-Version: 1.2<14>[ 33.325779] [IGT] kms_vblank: exiting, ret=77
13815 12:31:23.649440 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13816 12:31:23.652065 Opened device: /dev/dri/card0
13817 12:31:23.658997 N<8>[ 33.336926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13818 12:31:23.659262 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13820 12:31:23.662186 o KMS driver or no outputs, pipes: 8, outputs: 0
13821 12:31:23.668966 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13822 12:31:23.681606 <14>[ 33.362803] [IGT] kms_vblank: executing
13823 12:31:23.688039 IGT-Version: 1.2<14>[ 33.367825] [IGT] kms_vblank: exiting, ret=77
13824 12:31:23.691337 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13825 12:31:23.694728 Opened device: /dev/dri/card0
13826 12:31:23.701358 N<8>[ 33.379113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13827 12:31:23.701628 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13829 12:31:23.704784 o KMS driver or no outputs, pipes: 8, outputs: 0
13830 12:31:23.711545 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13831 12:31:23.724592 <14>[ 33.405852] [IGT] kms_vblank: executing
13832 12:31:23.730904 IGT-Version: 1.2<14>[ 33.410837] [IGT] kms_vblank: exiting, ret=77
13833 12:31:23.734852 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13834 12:31:23.737736 Opened device: /dev/dri/card0
13835 12:31:23.744533 N<8>[ 33.422657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13836 12:31:23.744910 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13838 12:31:23.747738 o KMS driver or no outputs, pipes: 8, outputs: 0
13839 12:31:23.754194 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13840 12:31:23.767173 <14>[ 33.448074] [IGT] kms_vblank: executing
13841 12:31:23.773423 IGT-Version: 1.2<14>[ 33.453151] [IGT] kms_vblank: exiting, ret=77
13842 12:31:23.777074 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13843 12:31:23.780351 Opened device: /dev/dri/card0
13844 12:31:23.787398 N<8>[ 33.464513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13845 12:31:23.788223 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13847 12:31:23.790105 o KMS driver or no outputs, pipes: 8, outputs: 0
13848 12:31:23.796917 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13849 12:31:23.809133 <14>[ 33.490103] [IGT] kms_vblank: executing
13850 12:31:23.815939 IGT-Version: 1.2<14>[ 33.495078] [IGT] kms_vblank: exiting, ret=77
13851 12:31:23.819195 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13852 12:31:23.822285 Opened device: /dev/dri/card0
13853 12:31:23.828880 N<8>[ 33.506536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13854 12:31:23.829843 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13856 12:31:23.832329 o KMS driver or no outputs, pipes: 8, outputs: 0
13857 12:31:23.838583 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13858 12:31:23.851488 <14>[ 33.532439] [IGT] kms_vblank: executing
13859 12:31:23.858212 IGT-Version: 1.2<14>[ 33.537515] [IGT] kms_vblank: exiting, ret=77
13860 12:31:23.861529 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13861 12:31:23.864343 Opened device: /dev/dri/card0
13862 12:31:23.871051 N<8>[ 33.548633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13863 12:31:23.871951 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13865 12:31:23.874271 o KMS driver or no outputs, pipes: 8, outputs: 0
13866 12:31:23.881249 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13867 12:31:23.893993 <14>[ 33.574794] [IGT] kms_vblank: executing
13868 12:31:23.900480 IGT-Version: 1.2<14>[ 33.579767] [IGT] kms_vblank: exiting, ret=77
13869 12:31:23.903161 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13870 12:31:23.906541 Opened device: /dev/dri/card0
13871 12:31:23.913371 N<8>[ 33.591397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13872 12:31:23.914175 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13874 12:31:23.919925 o KMS driver or no outputs, pipes: 8, outputs: 0
13875 12:31:23.923292 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13876 12:31:23.937599 <14>[ 33.618626] [IGT] kms_vblank: executing
13877 12:31:23.943869 IGT-Version: 1.2<14>[ 33.623867] [IGT] kms_vblank: exiting, ret=77
13878 12:31:23.947535 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13879 12:31:23.950589 Opened device: /dev/dri/card0
13880 12:31:23.957080 N<8>[ 33.635072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13881 12:31:23.957806 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13883 12:31:23.964151 o KMS driver or no outputs, pipes: 8, outputs: 0
13884 12:31:23.967378 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13885 12:31:23.980206 <14>[ 33.661388] [IGT] kms_vblank: executing
13886 12:31:23.987116 IGT-Version: 1.2<14>[ 33.666519] [IGT] kms_vblank: exiting, ret=77
13887 12:31:23.990186 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13888 12:31:23.993757 Opened device: /dev/dri/card0
13889 12:31:24.000482 N<8>[ 33.677911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13890 12:31:24.001179 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13892 12:31:24.006695 o KMS driver or no outputs, pipes: 8, outputs: 0
13893 12:31:24.010341 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13894 12:31:24.024067 <14>[ 33.704954] [IGT] kms_vblank: executing
13895 12:31:24.030573 IGT-Version: 1.2<14>[ 33.709946] [IGT] kms_vblank: exiting, ret=77
13896 12:31:24.033890 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13897 12:31:24.037174 Opened device: /dev/dri/card0
13898 12:31:24.043682 N<8>[ 33.721341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13899 12:31:24.044463 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13901 12:31:24.050142 o KMS driver or no outputs, pipes: 8, outputs: 0
13902 12:31:24.053279 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13903 12:31:24.066902 <14>[ 33.748058] [IGT] kms_vblank: executing
13904 12:31:24.073401 IGT-Version: 1.2<14>[ 33.753120] [IGT] kms_vblank: exiting, ret=77
13905 12:31:24.076524 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13906 12:31:24.080562 Opened device: /dev/dri/card0
13907 12:31:24.086723 N<8>[ 33.764318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13908 12:31:24.087695 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13910 12:31:24.093303 o KMS driver or no outputs, pipes: 8, outputs: 0
13911 12:31:24.099674 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13912 12:31:24.110257 <14>[ 33.791624] [IGT] kms_vblank: executing
13913 12:31:24.116939 IGT-Version: 1.2<14>[ 33.796608] [IGT] kms_vblank: exiting, ret=77
13914 12:31:24.120714 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13915 12:31:24.124126 Opened device: /dev/dri/card0
13916 12:31:24.130204 N<8>[ 33.808037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13917 12:31:24.130895 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13919 12:31:24.137530 o KMS driver or no outputs, pipes: 8, outputs: 0
13920 12:31:24.140681 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13921 12:31:24.153333 <14>[ 33.834593] [IGT] kms_vblank: executing
13922 12:31:24.160407 IGT-Version: 1.2<14>[ 33.839595] [IGT] kms_vblank: exiting, ret=77
13923 12:31:24.163667 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13924 12:31:24.166927 Opened device: /dev/dri/card0
13925 12:31:24.173399 N<8>[ 33.851424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13926 12:31:24.174319 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13928 12:31:24.180234 o KMS driver or no outputs, pipes: 8, outputs: 0
13929 12:31:24.183418 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13930 12:31:24.197175 <14>[ 33.878709] [IGT] kms_vblank: executing
13931 12:31:24.204012 IGT-Version: 1.2<14>[ 33.883920] [IGT] kms_vblank: exiting, ret=77
13932 12:31:24.207178 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13933 12:31:24.210962 Opened device: /dev/dri/card0
13934 12:31:24.217298 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13936 12:31:24.220874 N<8>[ 33.895373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13937 12:31:24.224197 o KMS driver or no outputs, pipes: 8, outputs: 0
13938 12:31:24.230075 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13939 12:31:24.241112 <14>[ 33.922551] [IGT] kms_vblank: executing
13940 12:31:24.247709 IGT-Version: 1.2<14>[ 33.927556] [IGT] kms_vblank: exiting, ret=77
13941 12:31:24.251058 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13942 12:31:24.254401 Opened device: /dev/dri/card0
13943 12:31:24.261495 N<8>[ 33.938833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13944 12:31:24.262334 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13946 12:31:24.267513 o KMS driver or no outputs, pipe<8>[ 33.950668] <LAVA_SIGNAL_TESTSET STOP>
13947 12:31:24.268288 Received signal: <TESTSET> STOP
13948 12:31:24.268808 Closing test_set kms_vblank
13949 12:31:24.277780 s: 8, outputs: 0<8>[ 33.956487] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 10605787_1.5.2.3.1>
13950 12:31:24.278365
13951 12:31:24.279104 Received signal: <ENDRUN> 0_igt-kms-mediatek 10605787_1.5.2.3.1
13952 12:31:24.279665 Ending use of test pattern.
13953 12:31:24.280062 Ending test lava.0_igt-kms-mediatek (10605787_1.5.2.3.1), duration 13.59
13955 12:31:24.284406 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13956 12:31:24.284874 + set +x
13957 12:31:24.287630 <LAVA_TEST_RUNNER EXIT>
13958 12:31:24.288303 ok: lava_test_shell seems to have completed
13959 12:31:24.308697 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13960 12:31:24.309897 end: 3.1 lava-test-shell (duration 00:00:14) [common]
13961 12:31:24.310228 end: 3 lava-test-retry (duration 00:00:14) [common]
13962 12:31:24.310541 start: 4 finalize (timeout 00:07:36) [common]
13963 12:31:24.310867 start: 4.1 power-off (timeout 00:00:30) [common]
13964 12:31:24.311424 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
13965 12:31:24.414939 >> Command sent successfully.
13966 12:31:24.418559 Returned 0 in 0 seconds
13967 12:31:24.519063 end: 4.1 power-off (duration 00:00:00) [common]
13969 12:31:24.519472 start: 4.2 read-feedback (timeout 00:07:36) [common]
13970 12:31:24.519784 Listened to connection for namespace 'common' for up to 1s
13971 12:31:25.520850 Finalising connection for namespace 'common'
13972 12:31:25.521595 Disconnecting from shell: Finalise
13973 12:31:25.522155 / #
13974 12:31:25.623209 end: 4.2 read-feedback (duration 00:00:01) [common]
13975 12:31:25.623879 end: 4 finalize (duration 00:00:01) [common]
13976 12:31:25.624428 Cleaning after the job
13977 12:31:25.624902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/ramdisk
13978 12:31:25.650768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/kernel
13979 12:31:25.660985 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/dtb
13980 12:31:25.661165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605787/tftp-deploy-0onrf3em/modules
13981 12:31:25.666613 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605787
13982 12:31:25.760852 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605787
13983 12:31:25.761012 Job finished correctly