Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 12:30:57.129899 lava-dispatcher, installed at version: 2023.05.1
2 12:30:57.130097 start: 0 validate
3 12:30:57.130223 Start time: 2023-06-06 12:30:57.130215+00:00 (UTC)
4 12:30:57.130341 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:30:57.130466 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:30:57.426343 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:30:57.427081 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:30:57.716993 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:30:57.717748 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:30:58.005533 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:30:58.006239 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:30:58.301192 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:30:58.301857 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:30:58.605777 validate duration: 1.48
16 12:30:58.606947 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:30:58.607438 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:30:58.607894 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:30:58.608512 Not decompressing ramdisk as can be used compressed.
20 12:30:58.608937 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:30:58.609267 saving as /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/ramdisk/initrd.cpio.gz
22 12:30:58.609585 total size: 4665601 (4MB)
23 12:30:58.614284 progress 0% (0MB)
24 12:30:58.621434 progress 5% (0MB)
25 12:30:58.627678 progress 10% (0MB)
26 12:30:58.632576 progress 15% (0MB)
27 12:30:58.636286 progress 20% (0MB)
28 12:30:58.639499 progress 25% (1MB)
29 12:30:58.642113 progress 30% (1MB)
30 12:30:58.644678 progress 35% (1MB)
31 12:30:58.646888 progress 40% (1MB)
32 12:30:58.649390 progress 45% (2MB)
33 12:30:58.651334 progress 50% (2MB)
34 12:30:58.653256 progress 55% (2MB)
35 12:30:58.655071 progress 60% (2MB)
36 12:30:58.656752 progress 65% (2MB)
37 12:30:58.658419 progress 70% (3MB)
38 12:30:58.660027 progress 75% (3MB)
39 12:30:58.661511 progress 80% (3MB)
40 12:30:58.663215 progress 85% (3MB)
41 12:30:58.664688 progress 90% (4MB)
42 12:30:58.666068 progress 95% (4MB)
43 12:30:58.667418 progress 100% (4MB)
44 12:30:58.667588 4MB downloaded in 0.06s (76.71MB/s)
45 12:30:58.667751 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:30:58.668013 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:30:58.668123 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:30:58.668221 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:30:58.668359 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:30:58.668438 saving as /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/kernel/Image
52 12:30:58.668506 total size: 45746688 (43MB)
53 12:30:58.668572 No compression specified
54 12:30:58.669737 progress 0% (0MB)
55 12:30:58.681207 progress 5% (2MB)
56 12:30:58.692605 progress 10% (4MB)
57 12:30:58.704018 progress 15% (6MB)
58 12:30:58.715408 progress 20% (8MB)
59 12:30:58.726721 progress 25% (10MB)
60 12:30:58.737944 progress 30% (13MB)
61 12:30:58.749260 progress 35% (15MB)
62 12:30:58.760740 progress 40% (17MB)
63 12:30:58.772329 progress 45% (19MB)
64 12:30:58.783799 progress 50% (21MB)
65 12:30:58.796412 progress 55% (24MB)
66 12:30:58.807880 progress 60% (26MB)
67 12:30:58.819467 progress 65% (28MB)
68 12:30:58.832127 progress 70% (30MB)
69 12:30:58.844527 progress 75% (32MB)
70 12:30:58.856446 progress 80% (34MB)
71 12:30:58.868168 progress 85% (37MB)
72 12:30:58.879984 progress 90% (39MB)
73 12:30:58.891550 progress 95% (41MB)
74 12:30:58.903023 progress 100% (43MB)
75 12:30:58.903163 43MB downloaded in 0.23s (185.92MB/s)
76 12:30:58.903314 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:30:58.903554 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:30:58.903647 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:30:58.903738 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:30:58.903874 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:30:58.903944 saving as /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/dtb/mt8192-asurada-spherion-r0.dtb
83 12:30:58.904007 total size: 46924 (0MB)
84 12:30:58.904081 No compression specified
85 12:30:58.905158 progress 69% (0MB)
86 12:30:58.905427 progress 100% (0MB)
87 12:30:58.905580 0MB downloaded in 0.00s (28.49MB/s)
88 12:30:58.905701 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:30:58.905929 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:30:58.906015 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:30:58.906098 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:30:58.906204 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:30:58.906272 saving as /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/nfsrootfs/full.rootfs.tar
95 12:30:58.906334 total size: 200770336 (191MB)
96 12:30:58.906394 Using unxz to decompress xz
97 12:30:58.909829 progress 0% (0MB)
98 12:30:59.430943 progress 5% (9MB)
99 12:30:59.940977 progress 10% (19MB)
100 12:31:00.515774 progress 15% (28MB)
101 12:31:00.880192 progress 20% (38MB)
102 12:31:01.200278 progress 25% (47MB)
103 12:31:01.792954 progress 30% (57MB)
104 12:31:02.341639 progress 35% (67MB)
105 12:31:02.928025 progress 40% (76MB)
106 12:31:03.482485 progress 45% (86MB)
107 12:31:04.053053 progress 50% (95MB)
108 12:31:04.669706 progress 55% (105MB)
109 12:31:05.332801 progress 60% (114MB)
110 12:31:05.606573 progress 65% (124MB)
111 12:31:05.745618 progress 70% (134MB)
112 12:31:05.842995 progress 75% (143MB)
113 12:31:05.921318 progress 80% (153MB)
114 12:31:05.992845 progress 85% (162MB)
115 12:31:06.094904 progress 90% (172MB)
116 12:31:06.369337 progress 95% (181MB)
117 12:31:06.935953 progress 100% (191MB)
118 12:31:06.940579 191MB downloaded in 8.03s (23.83MB/s)
119 12:31:06.940850 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:31:06.941108 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:31:06.941201 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:31:06.941301 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:31:06.941450 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:31:06.941522 saving as /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/modules/modules.tar
126 12:31:06.941585 total size: 8539116 (8MB)
127 12:31:06.941647 Using unxz to decompress xz
128 12:31:06.945484 progress 0% (0MB)
129 12:31:06.966969 progress 5% (0MB)
130 12:31:06.991815 progress 10% (0MB)
131 12:31:07.014876 progress 15% (1MB)
132 12:31:07.042108 progress 20% (1MB)
133 12:31:07.066952 progress 25% (2MB)
134 12:31:07.091388 progress 30% (2MB)
135 12:31:07.116487 progress 35% (2MB)
136 12:31:07.140627 progress 40% (3MB)
137 12:31:07.163702 progress 45% (3MB)
138 12:31:07.188374 progress 50% (4MB)
139 12:31:07.211874 progress 55% (4MB)
140 12:31:07.236227 progress 60% (4MB)
141 12:31:07.260886 progress 65% (5MB)
142 12:31:07.285651 progress 70% (5MB)
143 12:31:07.311627 progress 75% (6MB)
144 12:31:07.341187 progress 80% (6MB)
145 12:31:07.363076 progress 85% (6MB)
146 12:31:07.386960 progress 90% (7MB)
147 12:31:07.410825 progress 95% (7MB)
148 12:31:07.433995 progress 100% (8MB)
149 12:31:07.439245 8MB downloaded in 0.50s (16.36MB/s)
150 12:31:07.439514 end: 1.5.1 http-download (duration 00:00:00) [common]
152 12:31:07.439774 end: 1.5 download-retry (duration 00:00:00) [common]
153 12:31:07.439868 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:31:07.439962 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:31:10.933628 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps
156 12:31:10.933821 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:31:10.933924 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:31:10.934089 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_
159 12:31:10.934217 makedir: /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin
160 12:31:10.934318 makedir: /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/tests
161 12:31:10.934415 makedir: /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/results
162 12:31:10.934518 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-add-keys
163 12:31:10.934657 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-add-sources
164 12:31:10.934783 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-background-process-start
165 12:31:10.934908 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-background-process-stop
166 12:31:10.935031 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-common-functions
167 12:31:10.935154 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-echo-ipv4
168 12:31:10.935280 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-install-packages
169 12:31:10.935401 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-installed-packages
170 12:31:10.935522 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-os-build
171 12:31:10.935646 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-probe-channel
172 12:31:10.935768 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-probe-ip
173 12:31:10.935892 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-target-ip
174 12:31:10.936013 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-target-mac
175 12:31:10.936185 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-target-storage
176 12:31:10.936312 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-case
177 12:31:10.936433 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-event
178 12:31:10.936555 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-feedback
179 12:31:10.936687 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-raise
180 12:31:10.936810 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-reference
181 12:31:10.936932 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-runner
182 12:31:10.937053 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-set
183 12:31:10.937173 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-test-shell
184 12:31:10.937300 Updating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-add-keys (debian)
185 12:31:10.937587 Updating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-add-sources (debian)
186 12:31:10.937901 Updating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-install-packages (debian)
187 12:31:10.938151 Updating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-installed-packages (debian)
188 12:31:10.938416 Updating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/bin/lava-os-build (debian)
189 12:31:10.938806 Creating /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/environment
190 12:31:10.938911 LAVA metadata
191 12:31:10.938985 - LAVA_JOB_ID=10605801
192 12:31:10.939052 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:31:10.939154 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:31:10.939223 skipped lava-vland-overlay
195 12:31:10.939299 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:31:10.939379 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:31:10.939442 skipped lava-multinode-overlay
198 12:31:10.939516 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:31:10.939595 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:31:10.939669 Loading test definitions
201 12:31:10.939765 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 12:31:10.939838 Using /lava-10605801 at stage 0
203 12:31:10.940125 uuid=10605801_1.6.2.3.1 testdef=None
204 12:31:10.940225 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:31:10.940312 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 12:31:10.940762 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:31:10.940984 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 12:31:10.941529 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:31:10.941765 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 12:31:10.942293 runner path: /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/0/tests/0_timesync-off test_uuid 10605801_1.6.2.3.1
213 12:31:10.942449 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:31:10.942675 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 12:31:10.942750 Using /lava-10605801 at stage 0
217 12:31:10.942846 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:31:10.942926 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/0/tests/1_kselftest-rtc'
219 12:31:14.844715 Running '/usr/bin/git checkout kernelci.org
220 12:31:14.988581 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 12:31:14.989301 uuid=10605801_1.6.2.3.5 testdef=None
222 12:31:14.989456 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 12:31:14.989702 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 12:31:14.990447 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:31:14.990684 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 12:31:14.991635 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:31:14.991869 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 12:31:14.992845 runner path: /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/0/tests/1_kselftest-rtc test_uuid 10605801_1.6.2.3.5
232 12:31:14.992937 BOARD='mt8192-asurada-spherion-r0'
233 12:31:14.993003 BRANCH='cip'
234 12:31:14.993063 SKIPFILE='/dev/null'
235 12:31:14.993122 SKIP_INSTALL='True'
236 12:31:14.993181 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:31:14.993239 TST_CASENAME=''
238 12:31:14.993295 TST_CMDFILES='rtc'
239 12:31:14.993435 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:31:14.993642 Creating lava-test-runner.conf files
242 12:31:14.993707 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605801/lava-overlay-i9uilyi_/lava-10605801/0 for stage 0
243 12:31:14.993798 - 0_timesync-off
244 12:31:14.993869 - 1_kselftest-rtc
245 12:31:14.993962 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 12:31:14.994054 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 12:31:22.485714 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:31:22.485879 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 12:31:22.485973 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:31:22.486103 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 12:31:22.486194 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 12:31:22.601058 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:31:22.601412 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 12:31:22.601537 extracting modules file /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps
255 12:31:22.802632 extracting modules file /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605801/extract-overlay-ramdisk-uiz1zxvx/ramdisk
256 12:31:23.008659 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:31:23.008864 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 12:31:23.008969 [common] Applying overlay to NFS
259 12:31:23.009041 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605801/compress-overlay-_71lm562/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps
260 12:31:23.901920 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:31:23.902094 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 12:31:23.902191 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:31:23.902284 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 12:31:23.902364 Building ramdisk /var/lib/lava/dispatcher/tmp/10605801/extract-overlay-ramdisk-uiz1zxvx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605801/extract-overlay-ramdisk-uiz1zxvx/ramdisk
265 12:31:24.169888 >> 117807 blocks
266 12:31:26.077906 rename /var/lib/lava/dispatcher/tmp/10605801/extract-overlay-ramdisk-uiz1zxvx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/ramdisk/ramdisk.cpio.gz
267 12:31:26.078347 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:31:26.078476 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 12:31:26.078576 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 12:31:26.078679 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/kernel/Image'
271 12:31:37.600757 Returned 0 in 11 seconds
272 12:31:37.701388 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/kernel/image.itb
273 12:31:38.014048 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:31:38.014425 output: Created: Tue Jun 6 13:31:37 2023
275 12:31:38.014533 output: Image 0 (kernel-1)
276 12:31:38.014621 output: Description:
277 12:31:38.014704 output: Created: Tue Jun 6 13:31:37 2023
278 12:31:38.014789 output: Type: Kernel Image
279 12:31:38.014870 output: Compression: lzma compressed
280 12:31:38.014950 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
281 12:31:38.015052 output: Architecture: AArch64
282 12:31:38.015150 output: OS: Linux
283 12:31:38.015248 output: Load Address: 0x00000000
284 12:31:38.015344 output: Entry Point: 0x00000000
285 12:31:38.015443 output: Hash algo: crc32
286 12:31:38.015537 output: Hash value: a26c3f91
287 12:31:38.015631 output: Image 1 (fdt-1)
288 12:31:38.015724 output: Description: mt8192-asurada-spherion-r0
289 12:31:38.015818 output: Created: Tue Jun 6 13:31:37 2023
290 12:31:38.015911 output: Type: Flat Device Tree
291 12:31:38.016004 output: Compression: uncompressed
292 12:31:38.016142 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:31:38.016237 output: Architecture: AArch64
294 12:31:38.016330 output: Hash algo: crc32
295 12:31:38.016423 output: Hash value: 1df858fa
296 12:31:38.016516 output: Image 2 (ramdisk-1)
297 12:31:38.016609 output: Description: unavailable
298 12:31:38.016702 output: Created: Tue Jun 6 13:31:37 2023
299 12:31:38.016795 output: Type: RAMDisk Image
300 12:31:38.016888 output: Compression: Unknown Compression
301 12:31:38.016981 output: Data Size: 17638593 Bytes = 17225.19 KiB = 16.82 MiB
302 12:31:38.017074 output: Architecture: AArch64
303 12:31:38.017167 output: OS: Linux
304 12:31:38.017259 output: Load Address: unavailable
305 12:31:38.017351 output: Entry Point: unavailable
306 12:31:38.017443 output: Hash algo: crc32
307 12:31:38.017535 output: Hash value: b12c71f5
308 12:31:38.017627 output: Default Configuration: 'conf-1'
309 12:31:38.017728 output: Configuration 0 (conf-1)
310 12:31:38.017821 output: Description: mt8192-asurada-spherion-r0
311 12:31:38.017913 output: Kernel: kernel-1
312 12:31:38.018005 output: Init Ramdisk: ramdisk-1
313 12:31:38.018098 output: FDT: fdt-1
314 12:31:38.018190 output: Loadables: kernel-1
315 12:31:38.018282 output:
316 12:31:38.018533 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 12:31:38.018675 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 12:31:38.018820 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 12:31:38.018961 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 12:31:38.019077 No LXC device requested
321 12:31:38.019198 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:31:38.019330 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 12:31:38.019450 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:31:38.019558 Checking files for TFTP limit of 4294967296 bytes.
325 12:31:38.020254 end: 1 tftp-deploy (duration 00:00:39) [common]
326 12:31:38.020404 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:31:38.020539 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:31:38.020742 substitutions:
329 12:31:38.020861 - {DTB}: 10605801/tftp-deploy-l8ntmx1e/dtb/mt8192-asurada-spherion-r0.dtb
330 12:31:38.020946 - {INITRD}: 10605801/tftp-deploy-l8ntmx1e/ramdisk/ramdisk.cpio.gz
331 12:31:38.021028 - {KERNEL}: 10605801/tftp-deploy-l8ntmx1e/kernel/Image
332 12:31:38.021106 - {LAVA_MAC}: None
333 12:31:38.021184 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps
334 12:31:38.021261 - {NFS_SERVER_IP}: 192.168.201.1
335 12:31:38.021338 - {PRESEED_CONFIG}: None
336 12:31:38.021434 - {PRESEED_LOCAL}: None
337 12:31:38.021530 - {RAMDISK}: 10605801/tftp-deploy-l8ntmx1e/ramdisk/ramdisk.cpio.gz
338 12:31:38.021626 - {ROOT_PART}: None
339 12:31:38.021722 - {ROOT}: None
340 12:31:38.021817 - {SERVER_IP}: 192.168.201.1
341 12:31:38.021912 - {TEE}: None
342 12:31:38.022007 Parsed boot commands:
343 12:31:38.022101 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:31:38.022347 Parsed boot commands: tftpboot 192.168.201.1 10605801/tftp-deploy-l8ntmx1e/kernel/image.itb 10605801/tftp-deploy-l8ntmx1e/kernel/cmdline
345 12:31:38.022481 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:31:38.022612 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:31:38.022748 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:31:38.022882 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:31:38.022993 Not connected, no need to disconnect.
350 12:31:38.023113 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:31:38.023242 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:31:38.023348 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
353 12:31:38.027129 Setting prompt string to ['lava-test: # ']
354 12:31:38.027542 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:31:38.027695 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:31:38.027812 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:31:38.027923 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:31:38.028285 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 12:31:43.158659 >> Command sent successfully.
360 12:31:43.161795 Returned 0 in 5 seconds
361 12:31:43.262228 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:31:43.262642 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:31:43.262785 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:31:43.262900 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:31:43.263034 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:31:43.263122 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:31:43.263396 [Enter `^Ec?' for help]
369 12:31:43.437551
370 12:31:43.437707
371 12:31:43.437776 F0: 102B 0000
372 12:31:43.437841
373 12:31:43.437903 F3: 1001 0000 [0200]
374 12:31:43.440802
375 12:31:43.440887 F3: 1001 0000
376 12:31:43.440956
377 12:31:43.441021 F7: 102D 0000
378 12:31:43.441083
379 12:31:43.443706 F1: 0000 0000
380 12:31:43.443792
381 12:31:43.443860 V0: 0000 0000 [0001]
382 12:31:43.443923
383 12:31:43.447089 00: 0007 8000
384 12:31:43.447179
385 12:31:43.447252 01: 0000 0000
386 12:31:43.447333
387 12:31:43.450650 BP: 0C00 0209 [0000]
388 12:31:43.450735
389 12:31:43.450803 G0: 1182 0000
390 12:31:43.450867
391 12:31:43.454151 EC: 0000 0021 [4000]
392 12:31:43.454236
393 12:31:43.454304 S7: 0000 0000 [0000]
394 12:31:43.454367
395 12:31:43.457713 CC: 0000 0000 [0001]
396 12:31:43.457798
397 12:31:43.457866 T0: 0000 0040 [010F]
398 12:31:43.457929
399 12:31:43.461142 Jump to BL
400 12:31:43.461226
401 12:31:43.484755
402 12:31:43.484849
403 12:31:43.484918
404 12:31:43.491718 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:31:43.495266 ARM64: Exception handlers installed.
406 12:31:43.499344 ARM64: Testing exception
407 12:31:43.502229 ARM64: Done test exception
408 12:31:43.509140 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:31:43.519439 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:31:43.525712 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:31:43.535817 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:31:43.542666 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:31:43.549038 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:31:43.561037 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:31:43.567949 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:31:43.586955 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:31:43.590237 WDT: Last reset was cold boot
418 12:31:43.593864 SPI1(PAD0) initialized at 2873684 Hz
419 12:31:43.597358 SPI5(PAD0) initialized at 992727 Hz
420 12:31:43.600259 VBOOT: Loading verstage.
421 12:31:43.607204 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:31:43.610591 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:31:43.613874 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:31:43.616939 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:31:43.624744 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:31:43.630923 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:31:43.642235 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:31:43.642325
429 12:31:43.642392
430 12:31:43.651954 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:31:43.655254 ARM64: Exception handlers installed.
432 12:31:43.658895 ARM64: Testing exception
433 12:31:43.659012 ARM64: Done test exception
434 12:31:43.666019 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:31:43.669766 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:31:43.683029 Probing TPM: . done!
437 12:31:43.683112 TPM ready after 0 ms
438 12:31:43.690142 Connected to device vid:did:rid of 1ae0:0028:00
439 12:31:43.697029 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 12:31:43.755523 Initialized TPM device CR50 revision 0
441 12:31:43.767400 tlcl_send_startup: Startup return code is 0
442 12:31:43.767495 TPM: setup succeeded
443 12:31:43.778523 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:31:43.787422 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:31:43.799704 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:31:43.809744 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:31:43.813060 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:31:43.817892 in-header: 03 07 00 00 08 00 00 00
449 12:31:43.821872 in-data: aa e4 47 04 13 02 00 00
450 12:31:43.825496 Chrome EC: UHEPI supported
451 12:31:43.832584 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:31:43.835962 in-header: 03 95 00 00 08 00 00 00
453 12:31:43.839928 in-data: 18 20 20 08 00 00 00 00
454 12:31:43.840072 Phase 1
455 12:31:43.842911 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:31:43.850273 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:31:43.854219 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:31:43.857543 Recovery requested (1009000e)
459 12:31:43.866841 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:31:43.872271 tlcl_extend: response is 0
461 12:31:43.881604 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:31:43.887590 tlcl_extend: response is 0
463 12:31:43.894082 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:31:43.913917 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:31:43.920930 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:31:43.921018
467 12:31:43.921086
468 12:31:43.930788 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:31:43.934105 ARM64: Exception handlers installed.
470 12:31:43.937322 ARM64: Testing exception
471 12:31:43.937407 ARM64: Done test exception
472 12:31:43.959687 pmic_efuse_setting: Set efuses in 11 msecs
473 12:31:43.963123 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:31:43.969383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:31:43.972777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:31:43.979851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:31:43.983499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:31:43.987170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:31:43.994294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:31:43.997903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:31:44.001395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:31:44.008349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:31:44.012441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:31:44.015914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:31:44.020071 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:31:44.026734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:31:44.030696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:31:44.037798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:31:44.044634 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:31:44.048472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:31:44.055847 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:31:44.059771 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:31:44.067022 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:31:44.070549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:31:44.077824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:31:44.081354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:31:44.088433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:31:44.092522 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:31:44.099511 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:31:44.103054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:31:44.110120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:31:44.113596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:31:44.117790 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:31:44.124943 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:31:44.128438 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:31:44.131891 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:31:44.138933 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:31:44.142909 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:31:44.150036 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:31:44.153472 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:31:44.157566 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:31:44.164835 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:31:44.168289 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:31:44.172123 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:31:44.175530 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:31:44.182542 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:31:44.186089 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:31:44.189705 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:31:44.193708 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:31:44.196675 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:31:44.200224 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:31:44.207389 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:31:44.211596 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:31:44.215079 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:31:44.222769 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:31:44.230249 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:31:44.233896 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:31:44.244873 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:31:44.252861 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:31:44.256397 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:31:44.259807 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:31:44.267088 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:31:44.271119 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x1c
534 12:31:44.277945 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:31:44.281910 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 12:31:44.285490 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:31:44.297292 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 12:31:44.306186 [RTC]rtc_get_frequency_meter,154: input=7, output=723
539 12:31:44.316242 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 12:31:44.325444 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 12:31:44.334833 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 12:31:44.344384 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 12:31:44.354593 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 12:31:44.358475 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 12:31:44.362490 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 12:31:44.365897 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:31:44.373356 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
548 12:31:44.377066 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:31:44.380895 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:31:44.384387 ADC[4]: Raw value=905172 ID=7
551 12:31:44.384468 ADC[3]: Raw value=213546 ID=1
552 12:31:44.387861 RAM Code: 0x71
553 12:31:44.391996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:31:44.395516 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:31:44.406580 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:31:44.409991 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:31:44.413615 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:31:44.417785 in-header: 03 07 00 00 08 00 00 00
559 12:31:44.421229 in-data: aa e4 47 04 13 02 00 00
560 12:31:44.425271 Chrome EC: UHEPI supported
561 12:31:44.432193 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:31:44.435884 in-header: 03 95 00 00 08 00 00 00
563 12:31:44.439462 in-data: 18 20 20 08 00 00 00 00
564 12:31:44.443090 MRC: failed to locate region type 0.
565 12:31:44.447050 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:31:44.451038 DRAM-K: Running full calibration
567 12:31:44.457763 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:31:44.457857 header.status = 0x0
569 12:31:44.461769 header.version = 0x6 (expected: 0x6)
570 12:31:44.465129 header.size = 0xd00 (expected: 0xd00)
571 12:31:44.469239 header.flags = 0x0
572 12:31:44.472646 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:31:44.492190 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:31:44.499874 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:31:44.499972 dram_init: ddr_geometry: 2
576 12:31:44.503515 [EMI] MDL number = 2
577 12:31:44.507053 [EMI] Get MDL freq = 0
578 12:31:44.507188 dram_init: ddr_type: 0
579 12:31:44.511183 is_discrete_lpddr4: 1
580 12:31:44.514623 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:31:44.514707
582 12:31:44.514775
583 12:31:44.514838 [Bian_co] ETT version 0.0.0.1
584 12:31:44.521816 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:31:44.521901
586 12:31:44.524709 dramc_set_vcore_voltage set vcore to 650000
587 12:31:44.524794 Read voltage for 800, 4
588 12:31:44.528156 Vio18 = 0
589 12:31:44.528239 Vcore = 650000
590 12:31:44.528306 Vdram = 0
591 12:31:44.531304 Vddq = 0
592 12:31:44.531388 Vmddr = 0
593 12:31:44.534825 dram_init: config_dvfs: 1
594 12:31:44.538377 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:31:44.546176 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:31:44.550234 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 12:31:44.550386 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 12:31:44.557575 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 12:31:44.560982 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 12:31:44.561068 MEM_TYPE=3, freq_sel=18
601 12:31:44.564385 sv_algorithm_assistance_LP4_1600
602 12:31:44.567251 ============ PULL DRAM RESETB DOWN ============
603 12:31:44.573942 ========== PULL DRAM RESETB DOWN end =========
604 12:31:44.577468 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:31:44.580693 ===================================
606 12:31:44.583919 LPDDR4 DRAM CONFIGURATION
607 12:31:44.587406 ===================================
608 12:31:44.587503 EX_ROW_EN[0] = 0x0
609 12:31:44.590796 EX_ROW_EN[1] = 0x0
610 12:31:44.590896 LP4Y_EN = 0x0
611 12:31:44.594107 WORK_FSP = 0x0
612 12:31:44.594210 WL = 0x2
613 12:31:44.597612 RL = 0x2
614 12:31:44.597688 BL = 0x2
615 12:31:44.601150 RPST = 0x0
616 12:31:44.604202 RD_PRE = 0x0
617 12:31:44.604274 WR_PRE = 0x1
618 12:31:44.607583 WR_PST = 0x0
619 12:31:44.607652 DBI_WR = 0x0
620 12:31:44.610685 DBI_RD = 0x0
621 12:31:44.610754 OTF = 0x1
622 12:31:44.614065 ===================================
623 12:31:44.617542 ===================================
624 12:31:44.617612 ANA top config
625 12:31:44.621019 ===================================
626 12:31:44.623902 DLL_ASYNC_EN = 0
627 12:31:44.627461 ALL_SLAVE_EN = 1
628 12:31:44.630872 NEW_RANK_MODE = 1
629 12:31:44.634103 DLL_IDLE_MODE = 1
630 12:31:44.634179 LP45_APHY_COMB_EN = 1
631 12:31:44.637452 TX_ODT_DIS = 1
632 12:31:44.641029 NEW_8X_MODE = 1
633 12:31:44.643996 ===================================
634 12:31:44.647336 ===================================
635 12:31:44.650833 data_rate = 1600
636 12:31:44.653765 CKR = 1
637 12:31:44.653851 DQ_P2S_RATIO = 8
638 12:31:44.657276 ===================================
639 12:31:44.660804 CA_P2S_RATIO = 8
640 12:31:44.664231 DQ_CA_OPEN = 0
641 12:31:44.667714 DQ_SEMI_OPEN = 0
642 12:31:44.671083 CA_SEMI_OPEN = 0
643 12:31:44.674483 CA_FULL_RATE = 0
644 12:31:44.674568 DQ_CKDIV4_EN = 1
645 12:31:44.677408 CA_CKDIV4_EN = 1
646 12:31:44.680762 CA_PREDIV_EN = 0
647 12:31:44.684026 PH8_DLY = 0
648 12:31:44.687921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:31:44.690740 DQ_AAMCK_DIV = 4
650 12:31:44.690825 CA_AAMCK_DIV = 4
651 12:31:44.694065 CA_ADMCK_DIV = 4
652 12:31:44.697553 DQ_TRACK_CA_EN = 0
653 12:31:44.700945 CA_PICK = 800
654 12:31:44.703869 CA_MCKIO = 800
655 12:31:44.707930 MCKIO_SEMI = 0
656 12:31:44.708015 PLL_FREQ = 3068
657 12:31:44.711570 DQ_UI_PI_RATIO = 32
658 12:31:44.714576 CA_UI_PI_RATIO = 0
659 12:31:44.718648 ===================================
660 12:31:44.722031 ===================================
661 12:31:44.722138 memory_type:LPDDR4
662 12:31:44.725503 GP_NUM : 10
663 12:31:44.729179 SRAM_EN : 1
664 12:31:44.729259 MD32_EN : 0
665 12:31:44.732863 ===================================
666 12:31:44.736420 [ANA_INIT] >>>>>>>>>>>>>>
667 12:31:44.740314 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:31:44.740396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:31:44.743970 ===================================
670 12:31:44.747472 data_rate = 1600,PCW = 0X7600
671 12:31:44.751050 ===================================
672 12:31:44.753992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:31:44.760980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:31:44.763893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:31:44.770749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:31:44.774135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:31:44.777548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:31:44.780332 [ANA_INIT] flow start
679 12:31:44.780407 [ANA_INIT] PLL >>>>>>>>
680 12:31:44.784255 [ANA_INIT] PLL <<<<<<<<
681 12:31:44.787079 [ANA_INIT] MIDPI >>>>>>>>
682 12:31:44.787181 [ANA_INIT] MIDPI <<<<<<<<
683 12:31:44.790535 [ANA_INIT] DLL >>>>>>>>
684 12:31:44.793833 [ANA_INIT] flow end
685 12:31:44.797215 ============ LP4 DIFF to SE enter ============
686 12:31:44.800617 ============ LP4 DIFF to SE exit ============
687 12:31:44.803982 [ANA_INIT] <<<<<<<<<<<<<
688 12:31:44.806930 [Flow] Enable top DCM control >>>>>
689 12:31:44.810569 [Flow] Enable top DCM control <<<<<
690 12:31:44.814136 Enable DLL master slave shuffle
691 12:31:44.817101 ==============================================================
692 12:31:44.820725 Gating Mode config
693 12:31:44.827078 ==============================================================
694 12:31:44.827163 Config description:
695 12:31:44.837111 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:31:44.843507 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:31:44.846994 SELPH_MODE 0: By rank 1: By Phase
698 12:31:44.854029 ==============================================================
699 12:31:44.857059 GAT_TRACK_EN = 1
700 12:31:44.860520 RX_GATING_MODE = 2
701 12:31:44.863485 RX_GATING_TRACK_MODE = 2
702 12:31:44.866980 SELPH_MODE = 1
703 12:31:44.870520 PICG_EARLY_EN = 1
704 12:31:44.873730 VALID_LAT_VALUE = 1
705 12:31:44.877095 ==============================================================
706 12:31:44.880615 Enter into Gating configuration >>>>
707 12:31:44.883480 Exit from Gating configuration <<<<
708 12:31:44.887351 Enter into DVFS_PRE_config >>>>>
709 12:31:44.897209 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:31:44.900548 Exit from DVFS_PRE_config <<<<<
711 12:31:44.903994 Enter into PICG configuration >>>>
712 12:31:44.906901 Exit from PICG configuration <<<<
713 12:31:44.910326 [RX_INPUT] configuration >>>>>
714 12:31:44.914009 [RX_INPUT] configuration <<<<<
715 12:31:44.916857 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:31:44.923875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:31:44.930425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:31:44.936845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:31:44.943669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:31:44.950204 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:31:44.953662 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:31:44.956953 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:31:44.959877 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:31:44.966884 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:31:44.970323 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:31:44.973231 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:31:44.976813 ===================================
728 12:31:44.980201 LPDDR4 DRAM CONFIGURATION
729 12:31:44.983408 ===================================
730 12:31:44.983494 EX_ROW_EN[0] = 0x0
731 12:31:44.986852 EX_ROW_EN[1] = 0x0
732 12:31:44.986938 LP4Y_EN = 0x0
733 12:31:44.989761 WORK_FSP = 0x0
734 12:31:44.993194 WL = 0x2
735 12:31:44.993279 RL = 0x2
736 12:31:44.996555 BL = 0x2
737 12:31:44.996640 RPST = 0x0
738 12:31:44.999923 RD_PRE = 0x0
739 12:31:45.000008 WR_PRE = 0x1
740 12:31:45.003173 WR_PST = 0x0
741 12:31:45.003258 DBI_WR = 0x0
742 12:31:45.006627 DBI_RD = 0x0
743 12:31:45.006712 OTF = 0x1
744 12:31:45.009626 ===================================
745 12:31:45.013017 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:31:45.019525 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:31:45.023036 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:31:45.026723 ===================================
749 12:31:45.029701 LPDDR4 DRAM CONFIGURATION
750 12:31:45.033296 ===================================
751 12:31:45.033408 EX_ROW_EN[0] = 0x10
752 12:31:45.036273 EX_ROW_EN[1] = 0x0
753 12:31:45.036358 LP4Y_EN = 0x0
754 12:31:45.039545 WORK_FSP = 0x0
755 12:31:45.039630 WL = 0x2
756 12:31:45.043025 RL = 0x2
757 12:31:45.043135 BL = 0x2
758 12:31:45.046537 RPST = 0x0
759 12:31:45.049552 RD_PRE = 0x0
760 12:31:45.049637 WR_PRE = 0x1
761 12:31:45.052932 WR_PST = 0x0
762 12:31:45.053017 DBI_WR = 0x0
763 12:31:45.056347 DBI_RD = 0x0
764 12:31:45.056431 OTF = 0x1
765 12:31:45.059701 ===================================
766 12:31:45.066029 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:31:45.070209 nWR fixed to 40
768 12:31:45.073092 [ModeRegInit_LP4] CH0 RK0
769 12:31:45.073176 [ModeRegInit_LP4] CH0 RK1
770 12:31:45.076398 [ModeRegInit_LP4] CH1 RK0
771 12:31:45.079826 [ModeRegInit_LP4] CH1 RK1
772 12:31:45.079910 match AC timing 13
773 12:31:45.086029 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:31:45.089450 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:31:45.092918 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:31:45.099706 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:31:45.103167 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:31:45.106038 [EMI DOE] emi_dcm 0
779 12:31:45.109506 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:31:45.109604 ==
781 12:31:45.112837 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:31:45.116329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:31:45.116417 ==
784 12:31:45.122776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:31:45.129037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:31:45.137393 [CA 0] Center 37 (7~68) winsize 62
787 12:31:45.140934 [CA 1] Center 37 (7~68) winsize 62
788 12:31:45.143869 [CA 2] Center 34 (4~65) winsize 62
789 12:31:45.147348 [CA 3] Center 35 (4~66) winsize 63
790 12:31:45.150922 [CA 4] Center 33 (3~64) winsize 62
791 12:31:45.153883 [CA 5] Center 33 (3~64) winsize 62
792 12:31:45.153998
793 12:31:45.157332 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:31:45.157416
795 12:31:45.160736 [CATrainingPosCal] consider 1 rank data
796 12:31:45.163908 u2DelayCellTimex100 = 270/100 ps
797 12:31:45.167446 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:31:45.173870 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 12:31:45.176946 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 12:31:45.180406 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 12:31:45.183876 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 12:31:45.187059 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:31:45.187143
804 12:31:45.190438 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:31:45.190523
806 12:31:45.193852 [CBTSetCACLKResult] CA Dly = 33
807 12:31:45.196938 CS Dly: 5 (0~36)
808 12:31:45.197015 ==
809 12:31:45.200319 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:31:45.203643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:31:45.203756 ==
812 12:31:45.210436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:31:45.213227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:31:45.223749 [CA 0] Center 38 (7~69) winsize 63
815 12:31:45.227276 [CA 1] Center 37 (7~68) winsize 62
816 12:31:45.230231 [CA 2] Center 35 (4~66) winsize 63
817 12:31:45.233736 [CA 3] Center 35 (4~66) winsize 63
818 12:31:45.236758 [CA 4] Center 34 (3~65) winsize 63
819 12:31:45.240099 [CA 5] Center 33 (3~64) winsize 62
820 12:31:45.240210
821 12:31:45.243669 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:31:45.243769
823 12:31:45.247082 [CATrainingPosCal] consider 2 rank data
824 12:31:45.250009 u2DelayCellTimex100 = 270/100 ps
825 12:31:45.253482 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 12:31:45.259721 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 12:31:45.263191 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 12:31:45.266706 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 12:31:45.270189 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 12:31:45.272986 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:31:45.273064
832 12:31:45.276654 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:31:45.276728
834 12:31:45.280177 [CBTSetCACLKResult] CA Dly = 33
835 12:31:45.282968 CS Dly: 6 (0~38)
836 12:31:45.283051
837 12:31:45.287080 ----->DramcWriteLeveling(PI) begin...
838 12:31:45.287165 ==
839 12:31:45.290454 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:31:45.293978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:31:45.294063 ==
842 12:31:45.297842 Write leveling (Byte 0): 31 => 31
843 12:31:45.297926 Write leveling (Byte 1): 30 => 30
844 12:31:45.301192 DramcWriteLeveling(PI) end<-----
845 12:31:45.301276
846 12:31:45.301342 ==
847 12:31:45.304533 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:31:45.311695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:31:45.311809 ==
850 12:31:45.311880 [Gating] SW mode calibration
851 12:31:45.318525 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:31:45.325210 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:31:45.328696 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:31:45.335054 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
855 12:31:45.338518 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 12:31:45.341981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 12:31:45.348358 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:31:45.351854 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:31:45.355475 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:31:45.362027 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:31:45.364995 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:31:45.368623 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:31:45.375127 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:31:45.378593 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:31:45.382060 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:31:45.388529 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:31:45.391448 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:31:45.394928 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:31:45.398231 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:31:45.405069 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:31:45.408505 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:31:45.411832 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 12:31:45.418285 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:31:45.421743 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:31:45.424985 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:31:45.431648 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:31:45.434616 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:31:45.437625 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:31:45.444755 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
880 12:31:45.447590 0 9 12 | B1->B0 | 2c2b 3434 | 1 1 | (1 1) (1 1)
881 12:31:45.451107 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:31:45.457631 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:31:45.461150 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:31:45.464745 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:31:45.471297 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:31:45.474204 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
887 12:31:45.477591 0 10 8 | B1->B0 | 3333 2727 | 1 1 | (1 1) (1 0)
888 12:31:45.484505 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 12:31:45.487545 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:31:45.490657 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:31:45.497499 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:31:45.501054 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:31:45.504563 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:31:45.510744 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
895 12:31:45.513931 0 11 8 | B1->B0 | 2424 4242 | 0 0 | (0 0) (1 1)
896 12:31:45.517546 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
897 12:31:45.524345 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:31:45.527680 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:31:45.530436 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:31:45.537298 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:31:45.540847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:31:45.543789 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:31:45.550708 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 12:31:45.554198 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:31:45.557171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:31:45.563688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:31:45.567238 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:31:45.570666 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:31:45.576947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:31:45.580400 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:31:45.583912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:31:45.590286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:31:45.593691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:31:45.597216 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:31:45.603546 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:31:45.607035 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:31:45.610423 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:31:45.616751 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:31:45.620010 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 12:31:45.623398 Total UI for P1: 0, mck2ui 16
921 12:31:45.626811 best dqsien dly found for B0: ( 0, 14, 6)
922 12:31:45.630259 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 12:31:45.633690 Total UI for P1: 0, mck2ui 16
924 12:31:45.636330 best dqsien dly found for B1: ( 0, 14, 8)
925 12:31:45.639750 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 12:31:45.643079 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 12:31:45.643164
928 12:31:45.646602 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 12:31:45.653135 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:31:45.653220 [Gating] SW calibration Done
931 12:31:45.653288 ==
932 12:31:45.656723 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:31:45.663176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:31:45.663287 ==
935 12:31:45.663383 RX Vref Scan: 0
936 12:31:45.663475
937 12:31:45.666534 RX Vref 0 -> 0, step: 1
938 12:31:45.666637
939 12:31:45.670095 RX Delay -130 -> 252, step: 16
940 12:31:45.673083 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:31:45.676540 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 12:31:45.679950 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:31:45.686384 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:31:45.689835 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 12:31:45.693327 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 12:31:45.696297 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 12:31:45.699784 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 12:31:45.706720 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 12:31:45.709602 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 12:31:45.713062 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 12:31:45.716394 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 12:31:45.719963 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 12:31:45.726163 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 12:31:45.729389 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 12:31:45.732924 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 12:31:45.733008 ==
957 12:31:45.736322 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:31:45.739706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:31:45.739790 ==
960 12:31:45.743093 DQS Delay:
961 12:31:45.743176 DQS0 = 0, DQS1 = 0
962 12:31:45.746502 DQM Delay:
963 12:31:45.746585 DQM0 = 88, DQM1 = 75
964 12:31:45.746652 DQ Delay:
965 12:31:45.749593 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 12:31:45.752936 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 12:31:45.755959 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
968 12:31:45.759313 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 12:31:45.759397
970 12:31:45.759465
971 12:31:45.762915 ==
972 12:31:45.765956 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:31:45.769496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:31:45.769581 ==
975 12:31:45.769648
976 12:31:45.769712
977 12:31:45.773046 TX Vref Scan disable
978 12:31:45.773130 == TX Byte 0 ==
979 12:31:45.776062 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 12:31:45.782981 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 12:31:45.783066 == TX Byte 1 ==
982 12:31:45.785891 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 12:31:45.792706 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 12:31:45.792800 ==
985 12:31:45.795717 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:31:45.799258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:31:45.799333 ==
988 12:31:45.812498 TX Vref=22, minBit 0, minWin=27, winSum=439
989 12:31:45.815833 TX Vref=24, minBit 1, minWin=27, winSum=446
990 12:31:45.819305 TX Vref=26, minBit 1, minWin=27, winSum=445
991 12:31:45.822163 TX Vref=28, minBit 1, minWin=27, winSum=450
992 12:31:45.825613 TX Vref=30, minBit 1, minWin=27, winSum=452
993 12:31:45.832314 TX Vref=32, minBit 1, minWin=27, winSum=448
994 12:31:45.835614 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
995 12:31:45.835701
996 12:31:45.838979 Final TX Range 1 Vref 30
997 12:31:45.839066
998 12:31:45.839144 ==
999 12:31:45.841931 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:31:45.845234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:31:45.848896 ==
1002 12:31:45.848981
1003 12:31:45.849049
1004 12:31:45.849111 TX Vref Scan disable
1005 12:31:45.852331 == TX Byte 0 ==
1006 12:31:45.855779 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 12:31:45.862353 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 12:31:45.862438 == TX Byte 1 ==
1009 12:31:45.865858 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 12:31:45.872302 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 12:31:45.872389
1012 12:31:45.872457 [DATLAT]
1013 12:31:45.872521 Freq=800, CH0 RK0
1014 12:31:45.872581
1015 12:31:45.875808 DATLAT Default: 0xa
1016 12:31:45.875892 0, 0xFFFF, sum = 0
1017 12:31:45.878762 1, 0xFFFF, sum = 0
1018 12:31:45.882148 2, 0xFFFF, sum = 0
1019 12:31:45.882234 3, 0xFFFF, sum = 0
1020 12:31:45.885643 4, 0xFFFF, sum = 0
1021 12:31:45.885728 5, 0xFFFF, sum = 0
1022 12:31:45.889038 6, 0xFFFF, sum = 0
1023 12:31:45.889124 7, 0xFFFF, sum = 0
1024 12:31:45.891944 8, 0xFFFF, sum = 0
1025 12:31:45.892102 9, 0x0, sum = 1
1026 12:31:45.892173 10, 0x0, sum = 2
1027 12:31:45.895544 11, 0x0, sum = 3
1028 12:31:45.895628 12, 0x0, sum = 4
1029 12:31:45.898975 best_step = 10
1030 12:31:45.899058
1031 12:31:45.899124 ==
1032 12:31:45.902008 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:31:45.905594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:31:45.905678 ==
1035 12:31:45.908539 RX Vref Scan: 1
1036 12:31:45.908623
1037 12:31:45.911996 Set Vref Range= 32 -> 127
1038 12:31:45.912101
1039 12:31:45.912169 RX Vref 32 -> 127, step: 1
1040 12:31:45.912231
1041 12:31:45.915495 RX Delay -111 -> 252, step: 8
1042 12:31:45.915578
1043 12:31:45.918718 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:31:45.921626 [Byte1]: 32
1045 12:31:45.925072
1046 12:31:45.925165 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:31:45.928441 [Byte1]: 33
1048 12:31:45.933184
1049 12:31:45.933282 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:31:45.936339 [Byte1]: 34
1051 12:31:45.940317
1052 12:31:45.940402 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:31:45.943841 [Byte1]: 35
1054 12:31:45.948367
1055 12:31:45.948466 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:31:45.951779 [Byte1]: 36
1057 12:31:45.956300
1058 12:31:45.956380 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:31:45.959735 [Byte1]: 37
1060 12:31:45.963795
1061 12:31:45.963904 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:31:45.966707 [Byte1]: 38
1063 12:31:45.970984
1064 12:31:45.974614 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:31:45.974708 [Byte1]: 39
1066 12:31:45.979311
1067 12:31:45.979393 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:31:45.982791 [Byte1]: 40
1069 12:31:45.986921
1070 12:31:45.987003 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:31:45.990512 [Byte1]: 41
1072 12:31:45.993943
1073 12:31:45.994034 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:31:45.997358 [Byte1]: 42
1075 12:31:46.001953
1076 12:31:46.002036 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:31:46.005009 [Byte1]: 43
1078 12:31:46.009699
1079 12:31:46.009781 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:31:46.012582 [Byte1]: 44
1081 12:31:46.017379
1082 12:31:46.017481 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:31:46.020205 [Byte1]: 45
1084 12:31:46.024752
1085 12:31:46.024834 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:31:46.028065 [Byte1]: 46
1087 12:31:46.032191
1088 12:31:46.032273 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:31:46.035762 [Byte1]: 47
1090 12:31:46.039776
1091 12:31:46.039858 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:31:46.043173 [Byte1]: 48
1093 12:31:46.047822
1094 12:31:46.047905 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:31:46.050663 [Byte1]: 49
1096 12:31:46.055180
1097 12:31:46.055296 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:31:46.058832 [Byte1]: 50
1099 12:31:46.062671
1100 12:31:46.062753 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:31:46.066304 [Byte1]: 51
1102 12:31:46.070379
1103 12:31:46.070484 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:31:46.073859 [Byte1]: 52
1105 12:31:46.077900
1106 12:31:46.077982 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:31:46.081449 [Byte1]: 53
1108 12:31:46.085615
1109 12:31:46.085698 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:31:46.089134 [Byte1]: 54
1111 12:31:46.093746
1112 12:31:46.093836 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:31:46.096747 [Byte1]: 55
1114 12:31:46.100902
1115 12:31:46.100985 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:31:46.104399 [Byte1]: 56
1117 12:31:46.108989
1118 12:31:46.109071 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:31:46.111938 [Byte1]: 57
1120 12:31:46.116750
1121 12:31:46.116854 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:31:46.119607 [Byte1]: 58
1123 12:31:46.124036
1124 12:31:46.124135 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:31:46.127074 [Byte1]: 59
1126 12:31:46.131475
1127 12:31:46.131558 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:31:46.134803 [Byte1]: 60
1129 12:31:46.139359
1130 12:31:46.139441 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:31:46.142716 [Byte1]: 61
1132 12:31:46.147218
1133 12:31:46.147300 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:31:46.150247 [Byte1]: 62
1135 12:31:46.154785
1136 12:31:46.154867 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:31:46.158180 [Byte1]: 63
1138 12:31:46.162084
1139 12:31:46.162166 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:31:46.165497 [Byte1]: 64
1141 12:31:46.170166
1142 12:31:46.170249 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:31:46.173062 [Byte1]: 65
1144 12:31:46.177609
1145 12:31:46.177691 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:31:46.180582 [Byte1]: 66
1147 12:31:46.185269
1148 12:31:46.185351 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:31:46.188228 [Byte1]: 67
1150 12:31:46.192868
1151 12:31:46.192951 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:31:46.196408 [Byte1]: 68
1153 12:31:46.200609
1154 12:31:46.200692 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:31:46.203943 [Byte1]: 69
1156 12:31:46.208087
1157 12:31:46.208171 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:31:46.211482 [Byte1]: 70
1159 12:31:46.215690
1160 12:31:46.215797 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:31:46.219140 [Byte1]: 71
1162 12:31:46.223295
1163 12:31:46.223377 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:31:46.226884 [Byte1]: 72
1165 12:31:46.230822
1166 12:31:46.230904 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:31:46.234262 [Byte1]: 73
1168 12:31:46.238654
1169 12:31:46.238737 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:31:46.242082 [Byte1]: 74
1171 12:31:46.246190
1172 12:31:46.246272 Final RX Vref Byte 0 = 56 to rank0
1173 12:31:46.249514 Final RX Vref Byte 1 = 59 to rank0
1174 12:31:46.252779 Final RX Vref Byte 0 = 56 to rank1
1175 12:31:46.256420 Final RX Vref Byte 1 = 59 to rank1==
1176 12:31:46.259325 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 12:31:46.265918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 12:31:46.266001 ==
1179 12:31:46.266067 DQS Delay:
1180 12:31:46.269207 DQS0 = 0, DQS1 = 0
1181 12:31:46.269290 DQM Delay:
1182 12:31:46.269356 DQM0 = 88, DQM1 = 76
1183 12:31:46.272685 DQ Delay:
1184 12:31:46.276171 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1185 12:31:46.279296 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1186 12:31:46.282706 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1187 12:31:46.285747 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1188 12:31:46.285830
1189 12:31:46.285896
1190 12:31:46.292703 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1191 12:31:46.295704 CH0 RK0: MR19=606, MR18=2C25
1192 12:31:46.302839 CH0_RK0: MR19=0x606, MR18=0x2C25, DQSOSC=398, MR23=63, INC=93, DEC=62
1193 12:31:46.302922
1194 12:31:46.305837 ----->DramcWriteLeveling(PI) begin...
1195 12:31:46.305921 ==
1196 12:31:46.309262 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 12:31:46.312615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 12:31:46.312698 ==
1199 12:31:46.315588 Write leveling (Byte 0): 32 => 32
1200 12:31:46.318954 Write leveling (Byte 1): 27 => 27
1201 12:31:46.322582 DramcWriteLeveling(PI) end<-----
1202 12:31:46.322664
1203 12:31:46.322729 ==
1204 12:31:46.326081 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 12:31:46.329126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 12:31:46.329210 ==
1207 12:31:46.332545 [Gating] SW mode calibration
1208 12:31:46.339036 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 12:31:46.345772 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 12:31:46.349180 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 12:31:46.392958 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1212 12:31:46.393237 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1213 12:31:46.393310 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:31:46.393374 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:31:46.393432 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:31:46.393499 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:31:46.393559 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:31:46.393615 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:31:46.393671 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:31:46.393736 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:31:46.397254 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:31:46.403800 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:31:46.407183 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:31:46.410113 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:31:46.416682 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:31:46.419983 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1227 12:31:46.423520 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1228 12:31:46.429990 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1229 12:31:46.433497 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:31:46.436898 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:31:46.443101 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:31:46.446827 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:31:46.450234 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:31:46.456234 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:31:46.460290 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1236 12:31:46.463092 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
1237 12:31:46.469968 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1238 12:31:46.473355 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 12:31:46.476655 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 12:31:46.482956 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 12:31:46.486491 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 12:31:46.489936 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 12:31:46.492916 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1244 12:31:46.499516 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
1245 12:31:46.503137 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:31:46.506147 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:31:46.512557 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:31:46.516248 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:31:46.519794 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:31:46.526152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:31:46.529803 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1252 12:31:46.533385 0 11 8 | B1->B0 | 2d2d 4444 | 0 0 | (0 0) (0 0)
1253 12:31:46.540368 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1254 12:31:46.543883 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 12:31:46.547259 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 12:31:46.551197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 12:31:46.557471 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 12:31:46.560853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 12:31:46.564657 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1260 12:31:46.568253 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1261 12:31:46.575036 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:31:46.577890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:31:46.581541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:31:46.587891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:31:46.591343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:31:46.594837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:31:46.601154 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:31:46.604672 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:31:46.607634 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:31:46.614782 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:31:46.617649 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:31:46.621219 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:31:46.627635 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:31:46.631023 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:31:46.634573 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1276 12:31:46.641147 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1277 12:31:46.641232 Total UI for P1: 0, mck2ui 16
1278 12:31:46.647527 best dqsien dly found for B0: ( 0, 14, 4)
1279 12:31:46.650873 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 12:31:46.654361 Total UI for P1: 0, mck2ui 16
1281 12:31:46.657048 best dqsien dly found for B1: ( 0, 14, 6)
1282 12:31:46.660383 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1283 12:31:46.663817 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1284 12:31:46.663906
1285 12:31:46.667127 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1286 12:31:46.670474 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1287 12:31:46.673938 [Gating] SW calibration Done
1288 12:31:46.674015 ==
1289 12:31:46.676797 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 12:31:46.680212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 12:31:46.683624 ==
1292 12:31:46.683707 RX Vref Scan: 0
1293 12:31:46.683774
1294 12:31:46.686879 RX Vref 0 -> 0, step: 1
1295 12:31:46.686977
1296 12:31:46.690278 RX Delay -130 -> 252, step: 16
1297 12:31:46.693795 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1298 12:31:46.696766 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1299 12:31:46.700381 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1300 12:31:46.703770 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1301 12:31:46.710308 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1302 12:31:46.713399 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1303 12:31:46.716864 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1304 12:31:46.719932 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1305 12:31:46.723396 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1306 12:31:46.730330 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1307 12:31:46.733295 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1308 12:31:46.736871 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1309 12:31:46.739801 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1310 12:31:46.743279 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1311 12:31:46.749644 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1312 12:31:46.753063 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1313 12:31:46.753147 ==
1314 12:31:46.756519 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 12:31:46.759889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 12:31:46.759982 ==
1317 12:31:46.763207 DQS Delay:
1318 12:31:46.763284 DQS0 = 0, DQS1 = 0
1319 12:31:46.763349 DQM Delay:
1320 12:31:46.766697 DQM0 = 83, DQM1 = 76
1321 12:31:46.766785 DQ Delay:
1322 12:31:46.770010 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1323 12:31:46.773309 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1324 12:31:46.776674 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1325 12:31:46.779539 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1326 12:31:46.779643
1327 12:31:46.779745
1328 12:31:46.779837 ==
1329 12:31:46.783269 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 12:31:46.789489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 12:31:46.789578 ==
1332 12:31:46.789644
1333 12:31:46.789706
1334 12:31:46.789807 TX Vref Scan disable
1335 12:31:46.793558 == TX Byte 0 ==
1336 12:31:46.796479 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1337 12:31:46.803524 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1338 12:31:46.803639 == TX Byte 1 ==
1339 12:31:46.806797 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1340 12:31:46.813523 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1341 12:31:46.813602 ==
1342 12:31:46.816526 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 12:31:46.819983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 12:31:46.820090 ==
1345 12:31:46.833074 TX Vref=22, minBit 1, minWin=27, winSum=444
1346 12:31:46.836482 TX Vref=24, minBit 1, minWin=27, winSum=443
1347 12:31:46.839406 TX Vref=26, minBit 1, minWin=27, winSum=445
1348 12:31:46.842954 TX Vref=28, minBit 2, minWin=27, winSum=449
1349 12:31:46.845874 TX Vref=30, minBit 0, minWin=28, winSum=453
1350 12:31:46.852691 TX Vref=32, minBit 1, minWin=27, winSum=450
1351 12:31:46.856166 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1352 12:31:46.856249
1353 12:31:46.859467 Final TX Range 1 Vref 30
1354 12:31:46.859607
1355 12:31:46.859702 ==
1356 12:31:46.862377 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 12:31:46.865639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 12:31:46.868970 ==
1359 12:31:46.869075
1360 12:31:46.869190
1361 12:31:46.869302 TX Vref Scan disable
1362 12:31:46.872931 == TX Byte 0 ==
1363 12:31:46.876453 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1364 12:31:46.882670 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1365 12:31:46.882770 == TX Byte 1 ==
1366 12:31:46.886031 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1367 12:31:46.892742 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1368 12:31:46.892867
1369 12:31:46.892962 [DATLAT]
1370 12:31:46.893036 Freq=800, CH0 RK1
1371 12:31:46.893114
1372 12:31:46.895939 DATLAT Default: 0xa
1373 12:31:46.896071 0, 0xFFFF, sum = 0
1374 12:31:46.899428 1, 0xFFFF, sum = 0
1375 12:31:46.899511 2, 0xFFFF, sum = 0
1376 12:31:46.902785 3, 0xFFFF, sum = 0
1377 12:31:46.906270 4, 0xFFFF, sum = 0
1378 12:31:46.906377 5, 0xFFFF, sum = 0
1379 12:31:46.909579 6, 0xFFFF, sum = 0
1380 12:31:46.909709 7, 0xFFFF, sum = 0
1381 12:31:46.913046 8, 0xFFFF, sum = 0
1382 12:31:46.913162 9, 0x0, sum = 1
1383 12:31:46.913239 10, 0x0, sum = 2
1384 12:31:46.915971 11, 0x0, sum = 3
1385 12:31:46.916096 12, 0x0, sum = 4
1386 12:31:46.919548 best_step = 10
1387 12:31:46.919653
1388 12:31:46.919743 ==
1389 12:31:46.922600 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 12:31:46.926011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 12:31:46.926088 ==
1392 12:31:46.929595 RX Vref Scan: 0
1393 12:31:46.929743
1394 12:31:46.929810 RX Vref 0 -> 0, step: 1
1395 12:31:46.932653
1396 12:31:46.932733 RX Delay -95 -> 252, step: 8
1397 12:31:46.939661 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1398 12:31:46.942568 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1399 12:31:46.946141 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1400 12:31:46.949584 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1401 12:31:46.952579 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1402 12:31:46.959410 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1403 12:31:46.962875 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1404 12:31:46.965842 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1405 12:31:46.969042 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1406 12:31:46.972443 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1407 12:31:46.979103 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1408 12:31:46.982531 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1409 12:31:46.985860 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1410 12:31:46.988646 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1411 12:31:46.995449 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1412 12:31:46.998964 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1413 12:31:46.999069 ==
1414 12:31:47.002160 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 12:31:47.005712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 12:31:47.005824 ==
1417 12:31:47.008986 DQS Delay:
1418 12:31:47.009091 DQS0 = 0, DQS1 = 0
1419 12:31:47.009189 DQM Delay:
1420 12:31:47.012283 DQM0 = 86, DQM1 = 77
1421 12:31:47.012390 DQ Delay:
1422 12:31:47.015830 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1423 12:31:47.018698 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1424 12:31:47.022380 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1425 12:31:47.025216 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1426 12:31:47.025291
1427 12:31:47.025355
1428 12:31:47.035266 [DQSOSCAuto] RK1, (LSB)MR18= 0x221f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1429 12:31:47.038678 CH0 RK1: MR19=606, MR18=221F
1430 12:31:47.041636 CH0_RK1: MR19=0x606, MR18=0x221F, DQSOSC=401, MR23=63, INC=91, DEC=61
1431 12:31:47.045095 [RxdqsGatingPostProcess] freq 800
1432 12:31:47.051575 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 12:31:47.055036 Pre-setting of DQS Precalculation
1434 12:31:47.058591 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 12:31:47.058694 ==
1436 12:31:47.061377 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:31:47.068082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:31:47.068185 ==
1439 12:31:47.071706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 12:31:47.078527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 12:31:47.088048 [CA 0] Center 36 (6~67) winsize 62
1442 12:31:47.090919 [CA 1] Center 37 (6~68) winsize 63
1443 12:31:47.094430 [CA 2] Center 35 (5~66) winsize 62
1444 12:31:47.098107 [CA 3] Center 34 (4~65) winsize 62
1445 12:31:47.101492 [CA 4] Center 35 (4~66) winsize 63
1446 12:31:47.104263 [CA 5] Center 34 (4~65) winsize 62
1447 12:31:47.104342
1448 12:31:47.107573 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1449 12:31:47.107653
1450 12:31:47.111095 [CATrainingPosCal] consider 1 rank data
1451 12:31:47.114423 u2DelayCellTimex100 = 270/100 ps
1452 12:31:47.117922 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 12:31:47.120901 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1454 12:31:47.127823 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1455 12:31:47.130783 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 12:31:47.134453 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1457 12:31:47.137895 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 12:31:47.137970
1459 12:31:47.140879 CA PerBit enable=1, Macro0, CA PI delay=34
1460 12:31:47.140949
1461 12:31:47.144548 [CBTSetCACLKResult] CA Dly = 34
1462 12:31:47.144630 CS Dly: 4 (0~35)
1463 12:31:47.147767 ==
1464 12:31:47.150799 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 12:31:47.154264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 12:31:47.154338 ==
1467 12:31:47.157758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 12:31:47.164220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 12:31:47.173825 [CA 0] Center 36 (6~67) winsize 62
1470 12:31:47.177207 [CA 1] Center 36 (6~67) winsize 62
1471 12:31:47.180864 [CA 2] Center 35 (5~66) winsize 62
1472 12:31:47.184220 [CA 3] Center 34 (4~65) winsize 62
1473 12:31:47.187143 [CA 4] Center 34 (4~65) winsize 62
1474 12:31:47.190347 [CA 5] Center 34 (4~65) winsize 62
1475 12:31:47.190430
1476 12:31:47.193707 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 12:31:47.193824
1478 12:31:47.197020 [CATrainingPosCal] consider 2 rank data
1479 12:31:47.201054 u2DelayCellTimex100 = 270/100 ps
1480 12:31:47.204138 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 12:31:47.207698 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 12:31:47.211659 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1483 12:31:47.215052 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 12:31:47.218861 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 12:31:47.222340 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 12:31:47.222458
1487 12:31:47.226031 CA PerBit enable=1, Macro0, CA PI delay=34
1488 12:31:47.226117
1489 12:31:47.229540 [CBTSetCACLKResult] CA Dly = 34
1490 12:31:47.233683 CS Dly: 5 (0~37)
1491 12:31:47.233773
1492 12:31:47.236598 ----->DramcWriteLeveling(PI) begin...
1493 12:31:47.236687 ==
1494 12:31:47.240083 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 12:31:47.243528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 12:31:47.243643 ==
1497 12:31:47.247086 Write leveling (Byte 0): 26 => 26
1498 12:31:47.250027 Write leveling (Byte 1): 28 => 28
1499 12:31:47.253528 DramcWriteLeveling(PI) end<-----
1500 12:31:47.253611
1501 12:31:47.253678 ==
1502 12:31:47.257124 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 12:31:47.260527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 12:31:47.260609 ==
1505 12:31:47.263511 [Gating] SW mode calibration
1506 12:31:47.269855 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 12:31:47.276729 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 12:31:47.280278 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1509 12:31:47.283458 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1510 12:31:47.289913 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:31:47.293392 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:31:47.296836 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:31:47.303038 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:31:47.306524 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:31:47.309918 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:31:47.316309 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:31:47.319578 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:31:47.322939 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:31:47.329803 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:31:47.332726 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:31:47.336395 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:31:47.342753 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:31:47.346323 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:31:47.349322 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:31:47.352739 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1526 12:31:47.359890 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:31:47.362850 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:31:47.366320 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:31:47.373021 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:31:47.376172 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:31:47.379601 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:31:47.385933 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:31:47.389372 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1534 12:31:47.392275 0 9 8 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (1 1)
1535 12:31:47.399051 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:31:47.402585 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 12:31:47.405940 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 12:31:47.412280 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 12:31:47.415714 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 12:31:47.419164 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1541 12:31:47.425439 0 10 4 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 1)
1542 12:31:47.428975 0 10 8 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (0 0)
1543 12:31:47.432364 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:31:47.438700 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:31:47.442110 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:31:47.445693 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:31:47.451961 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:31:47.455690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:31:47.458964 0 11 4 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
1550 12:31:47.465632 0 11 8 | B1->B0 | 3434 3e3d | 1 1 | (1 1) (0 0)
1551 12:31:47.468597 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:31:47.472038 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:31:47.478585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 12:31:47.482128 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 12:31:47.485377 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 12:31:47.492276 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 12:31:47.495155 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1558 12:31:47.498644 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:31:47.505247 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:31:47.508645 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:31:47.512073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:31:47.518297 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:31:47.521752 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:31:47.525263 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:31:47.531417 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:31:47.534738 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:31:47.538251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:31:47.544655 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:31:47.547622 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:31:47.551245 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:31:47.557637 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:31:47.561299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:31:47.564513 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1574 12:31:47.571153 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1575 12:31:47.571249 Total UI for P1: 0, mck2ui 16
1576 12:31:47.577682 best dqsien dly found for B0: ( 0, 14, 4)
1577 12:31:47.580636 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 12:31:47.584211 Total UI for P1: 0, mck2ui 16
1579 12:31:47.587659 best dqsien dly found for B1: ( 0, 14, 6)
1580 12:31:47.591115 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1581 12:31:47.594506 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1582 12:31:47.594619
1583 12:31:47.597224 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1584 12:31:47.600899 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1585 12:31:47.604312 [Gating] SW calibration Done
1586 12:31:47.604412 ==
1587 12:31:47.607670 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 12:31:47.610939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 12:31:47.614184 ==
1590 12:31:47.614275 RX Vref Scan: 0
1591 12:31:47.614343
1592 12:31:47.617033 RX Vref 0 -> 0, step: 1
1593 12:31:47.617148
1594 12:31:47.620364 RX Delay -130 -> 252, step: 16
1595 12:31:47.623741 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1596 12:31:47.627169 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1597 12:31:47.630590 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1598 12:31:47.633943 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1599 12:31:47.640311 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1600 12:31:47.643869 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1601 12:31:47.646840 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1602 12:31:47.650773 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1603 12:31:47.653747 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1604 12:31:47.660270 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1605 12:31:47.663826 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1606 12:31:47.667116 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1607 12:31:47.670645 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1608 12:31:47.674084 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1609 12:31:47.680660 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1610 12:31:47.683572 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1611 12:31:47.683673 ==
1612 12:31:47.687047 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 12:31:47.690483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 12:31:47.690577 ==
1615 12:31:47.693762 DQS Delay:
1616 12:31:47.693852 DQS0 = 0, DQS1 = 0
1617 12:31:47.693920 DQM Delay:
1618 12:31:47.697214 DQM0 = 88, DQM1 = 84
1619 12:31:47.697304 DQ Delay:
1620 12:31:47.700682 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1621 12:31:47.703647 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1622 12:31:47.707044 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1623 12:31:47.710312 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1624 12:31:47.710412
1625 12:31:47.710480
1626 12:31:47.710539 ==
1627 12:31:47.713853 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 12:31:47.720394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 12:31:47.720519 ==
1630 12:31:47.720586
1631 12:31:47.720647
1632 12:31:47.720706 TX Vref Scan disable
1633 12:31:47.723726 == TX Byte 0 ==
1634 12:31:47.727216 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1635 12:31:47.734082 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1636 12:31:47.734214 == TX Byte 1 ==
1637 12:31:47.737496 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 12:31:47.743788 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 12:31:47.743917 ==
1640 12:31:47.747214 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 12:31:47.750219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 12:31:47.750315 ==
1643 12:31:47.762950 TX Vref=22, minBit 4, minWin=26, winSum=439
1644 12:31:47.766371 TX Vref=24, minBit 4, minWin=26, winSum=444
1645 12:31:47.769808 TX Vref=26, minBit 0, minWin=27, winSum=445
1646 12:31:47.773114 TX Vref=28, minBit 0, minWin=27, winSum=452
1647 12:31:47.776540 TX Vref=30, minBit 1, minWin=27, winSum=449
1648 12:31:47.783526 TX Vref=32, minBit 1, minWin=27, winSum=451
1649 12:31:47.787102 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 28
1650 12:31:47.787208
1651 12:31:47.789992 Final TX Range 1 Vref 28
1652 12:31:47.790085
1653 12:31:47.790152 ==
1654 12:31:47.793602 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 12:31:47.797087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 12:31:47.797187 ==
1657 12:31:47.797254
1658 12:31:47.797315
1659 12:31:47.799927 TX Vref Scan disable
1660 12:31:47.803248 == TX Byte 0 ==
1661 12:31:47.806840 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1662 12:31:47.809867 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1663 12:31:47.813242 == TX Byte 1 ==
1664 12:31:47.816495 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1665 12:31:47.820398 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1666 12:31:47.820506
1667 12:31:47.823664 [DATLAT]
1668 12:31:47.823773 Freq=800, CH1 RK0
1669 12:31:47.823845
1670 12:31:47.826689 DATLAT Default: 0xa
1671 12:31:47.826786 0, 0xFFFF, sum = 0
1672 12:31:47.829957 1, 0xFFFF, sum = 0
1673 12:31:47.830070 2, 0xFFFF, sum = 0
1674 12:31:47.833329 3, 0xFFFF, sum = 0
1675 12:31:47.833443 4, 0xFFFF, sum = 0
1676 12:31:47.836786 5, 0xFFFF, sum = 0
1677 12:31:47.836881 6, 0xFFFF, sum = 0
1678 12:31:47.839992 7, 0xFFFF, sum = 0
1679 12:31:47.840132 8, 0xFFFF, sum = 0
1680 12:31:47.843303 9, 0x0, sum = 1
1681 12:31:47.843402 10, 0x0, sum = 2
1682 12:31:47.846836 11, 0x0, sum = 3
1683 12:31:47.846931 12, 0x0, sum = 4
1684 12:31:47.850125 best_step = 10
1685 12:31:47.850220
1686 12:31:47.850287 ==
1687 12:31:47.853013 Dram Type= 6, Freq= 0, CH_1, rank 0
1688 12:31:47.856595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1689 12:31:47.856698 ==
1690 12:31:47.859596 RX Vref Scan: 1
1691 12:31:47.859685
1692 12:31:47.859754 Set Vref Range= 32 -> 127
1693 12:31:47.859817
1694 12:31:47.863063 RX Vref 32 -> 127, step: 1
1695 12:31:47.863153
1696 12:31:47.866671 RX Delay -95 -> 252, step: 8
1697 12:31:47.866759
1698 12:31:47.869723 Set Vref, RX VrefLevel [Byte0]: 32
1699 12:31:47.873081 [Byte1]: 32
1700 12:31:47.873174
1701 12:31:47.876387 Set Vref, RX VrefLevel [Byte0]: 33
1702 12:31:47.879833 [Byte1]: 33
1703 12:31:47.883295
1704 12:31:47.883401 Set Vref, RX VrefLevel [Byte0]: 34
1705 12:31:47.886865 [Byte1]: 34
1706 12:31:47.891094
1707 12:31:47.891201 Set Vref, RX VrefLevel [Byte0]: 35
1708 12:31:47.894629 [Byte1]: 35
1709 12:31:47.898574
1710 12:31:47.898674 Set Vref, RX VrefLevel [Byte0]: 36
1711 12:31:47.901881 [Byte1]: 36
1712 12:31:47.905983
1713 12:31:47.909504 Set Vref, RX VrefLevel [Byte0]: 37
1714 12:31:47.912893 [Byte1]: 37
1715 12:31:47.912991
1716 12:31:47.915835 Set Vref, RX VrefLevel [Byte0]: 38
1717 12:31:47.919092 [Byte1]: 38
1718 12:31:47.919189
1719 12:31:47.922603 Set Vref, RX VrefLevel [Byte0]: 39
1720 12:31:47.926114 [Byte1]: 39
1721 12:31:47.926212
1722 12:31:47.928939 Set Vref, RX VrefLevel [Byte0]: 40
1723 12:31:47.932427 [Byte1]: 40
1724 12:31:47.936531
1725 12:31:47.936631 Set Vref, RX VrefLevel [Byte0]: 41
1726 12:31:47.939984 [Byte1]: 41
1727 12:31:47.944446
1728 12:31:47.944558 Set Vref, RX VrefLevel [Byte0]: 42
1729 12:31:47.947862 [Byte1]: 42
1730 12:31:47.951692
1731 12:31:47.951800 Set Vref, RX VrefLevel [Byte0]: 43
1732 12:31:47.955330 [Byte1]: 43
1733 12:31:47.959389
1734 12:31:47.959493 Set Vref, RX VrefLevel [Byte0]: 44
1735 12:31:47.962321 [Byte1]: 44
1736 12:31:47.966998
1737 12:31:47.967122 Set Vref, RX VrefLevel [Byte0]: 45
1738 12:31:47.970505 [Byte1]: 45
1739 12:31:47.974744
1740 12:31:47.974854 Set Vref, RX VrefLevel [Byte0]: 46
1741 12:31:47.978169 [Byte1]: 46
1742 12:31:47.981968
1743 12:31:47.982067 Set Vref, RX VrefLevel [Byte0]: 47
1744 12:31:47.985484 [Byte1]: 47
1745 12:31:47.989583
1746 12:31:47.989694 Set Vref, RX VrefLevel [Byte0]: 48
1747 12:31:47.993113 [Byte1]: 48
1748 12:31:47.997086
1749 12:31:47.997186 Set Vref, RX VrefLevel [Byte0]: 49
1750 12:31:48.000750 [Byte1]: 49
1751 12:31:48.005274
1752 12:31:48.005380 Set Vref, RX VrefLevel [Byte0]: 50
1753 12:31:48.008181 [Byte1]: 50
1754 12:31:48.012783
1755 12:31:48.012892 Set Vref, RX VrefLevel [Byte0]: 51
1756 12:31:48.015667 [Byte1]: 51
1757 12:31:48.020239
1758 12:31:48.020343 Set Vref, RX VrefLevel [Byte0]: 52
1759 12:31:48.023153 [Byte1]: 52
1760 12:31:48.027689
1761 12:31:48.027797 Set Vref, RX VrefLevel [Byte0]: 53
1762 12:31:48.031047 [Byte1]: 53
1763 12:31:48.035587
1764 12:31:48.035698 Set Vref, RX VrefLevel [Byte0]: 54
1765 12:31:48.038346 [Byte1]: 54
1766 12:31:48.043019
1767 12:31:48.043130 Set Vref, RX VrefLevel [Byte0]: 55
1768 12:31:48.046085 [Byte1]: 55
1769 12:31:48.050592
1770 12:31:48.050701 Set Vref, RX VrefLevel [Byte0]: 56
1771 12:31:48.053886 [Byte1]: 56
1772 12:31:48.057977
1773 12:31:48.058084 Set Vref, RX VrefLevel [Byte0]: 57
1774 12:31:48.061543 [Byte1]: 57
1775 12:31:48.065542
1776 12:31:48.065647 Set Vref, RX VrefLevel [Byte0]: 58
1777 12:31:48.068985 [Byte1]: 58
1778 12:31:48.073689
1779 12:31:48.073797 Set Vref, RX VrefLevel [Byte0]: 59
1780 12:31:48.076638 [Byte1]: 59
1781 12:31:48.080772
1782 12:31:48.080875 Set Vref, RX VrefLevel [Byte0]: 60
1783 12:31:48.084171 [Byte1]: 60
1784 12:31:48.088583
1785 12:31:48.088693 Set Vref, RX VrefLevel [Byte0]: 61
1786 12:31:48.091981 [Byte1]: 61
1787 12:31:48.096176
1788 12:31:48.096282 Set Vref, RX VrefLevel [Byte0]: 62
1789 12:31:48.099103 [Byte1]: 62
1790 12:31:48.103674
1791 12:31:48.103776 Set Vref, RX VrefLevel [Byte0]: 63
1792 12:31:48.107172 [Byte1]: 63
1793 12:31:48.111200
1794 12:31:48.111302 Set Vref, RX VrefLevel [Byte0]: 64
1795 12:31:48.114584 [Byte1]: 64
1796 12:31:48.119106
1797 12:31:48.119211 Set Vref, RX VrefLevel [Byte0]: 65
1798 12:31:48.122499 [Byte1]: 65
1799 12:31:48.126760
1800 12:31:48.126861 Set Vref, RX VrefLevel [Byte0]: 66
1801 12:31:48.129620 [Byte1]: 66
1802 12:31:48.134052
1803 12:31:48.134148 Set Vref, RX VrefLevel [Byte0]: 67
1804 12:31:48.137496 [Byte1]: 67
1805 12:31:48.141916
1806 12:31:48.142022 Set Vref, RX VrefLevel [Byte0]: 68
1807 12:31:48.144718 [Byte1]: 68
1808 12:31:48.149543
1809 12:31:48.149652 Set Vref, RX VrefLevel [Byte0]: 69
1810 12:31:48.152349 [Byte1]: 69
1811 12:31:48.156882
1812 12:31:48.156986 Set Vref, RX VrefLevel [Byte0]: 70
1813 12:31:48.160254 [Byte1]: 70
1814 12:31:48.164288
1815 12:31:48.164390 Set Vref, RX VrefLevel [Byte0]: 71
1816 12:31:48.167921 [Byte1]: 71
1817 12:31:48.171990
1818 12:31:48.172115 Set Vref, RX VrefLevel [Byte0]: 72
1819 12:31:48.175480 [Byte1]: 72
1820 12:31:48.179726
1821 12:31:48.179823 Set Vref, RX VrefLevel [Byte0]: 73
1822 12:31:48.183216 [Byte1]: 73
1823 12:31:48.187200
1824 12:31:48.187299 Final RX Vref Byte 0 = 58 to rank0
1825 12:31:48.190754 Final RX Vref Byte 1 = 59 to rank0
1826 12:31:48.193906 Final RX Vref Byte 0 = 58 to rank1
1827 12:31:48.197552 Final RX Vref Byte 1 = 59 to rank1==
1828 12:31:48.200213 Dram Type= 6, Freq= 0, CH_1, rank 0
1829 12:31:48.206822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 12:31:48.206937 ==
1831 12:31:48.207005 DQS Delay:
1832 12:31:48.210278 DQS0 = 0, DQS1 = 0
1833 12:31:48.210389 DQM Delay:
1834 12:31:48.210469 DQM0 = 87, DQM1 = 82
1835 12:31:48.213960 DQ Delay:
1836 12:31:48.216731 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1837 12:31:48.220547 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1838 12:31:48.223646 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1839 12:31:48.226704 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1840 12:31:48.226805
1841 12:31:48.226872
1842 12:31:48.233589 [DQSOSCAuto] RK0, (LSB)MR18= 0x1528, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1843 12:31:48.236917 CH1 RK0: MR19=606, MR18=1528
1844 12:31:48.243788 CH1_RK0: MR19=0x606, MR18=0x1528, DQSOSC=399, MR23=63, INC=92, DEC=61
1845 12:31:48.243918
1846 12:31:48.246955 ----->DramcWriteLeveling(PI) begin...
1847 12:31:48.247048 ==
1848 12:31:48.250382 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 12:31:48.253325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 12:31:48.253426 ==
1851 12:31:48.256827 Write leveling (Byte 0): 24 => 24
1852 12:31:48.259851 Write leveling (Byte 1): 28 => 28
1853 12:31:48.263189 DramcWriteLeveling(PI) end<-----
1854 12:31:48.263287
1855 12:31:48.263353 ==
1856 12:31:48.266626 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 12:31:48.270133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 12:31:48.270233 ==
1859 12:31:48.273142 [Gating] SW mode calibration
1860 12:31:48.279625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1861 12:31:48.286524 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1862 12:31:48.290081 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1863 12:31:48.296394 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1864 12:31:48.300258 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1865 12:31:48.303249 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:31:48.309772 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:31:48.312664 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:31:48.316196 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:31:48.323008 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:31:48.326366 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:31:48.329615 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:31:48.336173 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:31:48.339515 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:31:48.342899 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:31:48.346203 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:31:48.352990 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:31:48.356291 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:31:48.359281 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:31:48.366130 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1880 12:31:48.369734 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:31:48.373253 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:31:48.379726 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:31:48.383154 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:31:48.386262 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:31:48.392747 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:31:48.396260 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:31:48.399488 0 9 4 | B1->B0 | 2323 2525 | 1 1 | (1 1) (1 1)
1888 12:31:48.406078 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1889 12:31:48.408997 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 12:31:48.412599 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 12:31:48.419080 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 12:31:48.422407 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 12:31:48.425830 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 12:31:48.432140 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1895 12:31:48.435697 0 10 4 | B1->B0 | 3434 2b2b | 0 1 | (0 0) (1 0)
1896 12:31:48.439168 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1897 12:31:48.445490 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:31:48.448796 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:31:48.452176 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:31:48.458653 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:31:48.461978 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:31:48.465409 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:31:48.471678 0 11 4 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
1904 12:31:48.474764 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1905 12:31:48.478191 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 12:31:48.484754 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 12:31:48.488245 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 12:31:48.491884 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 12:31:48.498338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 12:31:48.501366 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1911 12:31:48.504862 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1912 12:31:48.511386 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:31:48.514960 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:31:48.518004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:31:48.524473 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:31:48.527927 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:31:48.531227 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:31:48.538091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:31:48.540939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:31:48.544440 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:31:48.551260 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:31:48.554590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:31:48.557939 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:31:48.564642 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:31:48.568051 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:31:48.570848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1927 12:31:48.577877 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1928 12:31:48.577989 Total UI for P1: 0, mck2ui 16
1929 12:31:48.584380 best dqsien dly found for B0: ( 0, 14, 0)
1930 12:31:48.587451 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 12:31:48.591090 Total UI for P1: 0, mck2ui 16
1932 12:31:48.593965 best dqsien dly found for B1: ( 0, 14, 4)
1933 12:31:48.597643 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1934 12:31:48.600700 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1935 12:31:48.600787
1936 12:31:48.604249 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1937 12:31:48.607761 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1938 12:31:48.610753 [Gating] SW calibration Done
1939 12:31:48.610838 ==
1940 12:31:48.614008 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 12:31:48.617513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 12:31:48.617598 ==
1943 12:31:48.620477 RX Vref Scan: 0
1944 12:31:48.620561
1945 12:31:48.623962 RX Vref 0 -> 0, step: 1
1946 12:31:48.624073
1947 12:31:48.624155 RX Delay -130 -> 252, step: 16
1948 12:31:48.630942 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1949 12:31:48.634136 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1950 12:31:48.637549 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1951 12:31:48.640781 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1952 12:31:48.643709 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1953 12:31:48.650578 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1954 12:31:48.654095 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1955 12:31:48.657351 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1956 12:31:48.660368 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1957 12:31:48.663518 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1958 12:31:48.670322 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1959 12:31:48.673543 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1960 12:31:48.677032 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1961 12:31:48.679946 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1962 12:31:48.686497 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1963 12:31:48.689959 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1964 12:31:48.690057 ==
1965 12:31:48.693526 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 12:31:48.696509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 12:31:48.696599 ==
1968 12:31:48.699998 DQS Delay:
1969 12:31:48.700122 DQS0 = 0, DQS1 = 0
1970 12:31:48.700192 DQM Delay:
1971 12:31:48.703442 DQM0 = 86, DQM1 = 85
1972 12:31:48.703554 DQ Delay:
1973 12:31:48.706964 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1974 12:31:48.709896 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1975 12:31:48.713331 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1976 12:31:48.716899 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1977 12:31:48.716993
1978 12:31:48.717060
1979 12:31:48.717122 ==
1980 12:31:48.720353 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:31:48.726857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:31:48.726957 ==
1983 12:31:48.727028
1984 12:31:48.727089
1985 12:31:48.727147 TX Vref Scan disable
1986 12:31:48.730466 == TX Byte 0 ==
1987 12:31:48.733335 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1988 12:31:48.739927 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1989 12:31:48.740099 == TX Byte 1 ==
1990 12:31:48.743332 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1991 12:31:48.750108 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1992 12:31:48.750221 ==
1993 12:31:48.753029 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 12:31:48.756438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 12:31:48.756578 ==
1996 12:31:48.769788 TX Vref=22, minBit 1, minWin=26, winSum=438
1997 12:31:48.773135 TX Vref=24, minBit 1, minWin=26, winSum=443
1998 12:31:48.776622 TX Vref=26, minBit 5, minWin=26, winSum=443
1999 12:31:48.779348 TX Vref=28, minBit 2, minWin=27, winSum=452
2000 12:31:48.782942 TX Vref=30, minBit 3, minWin=27, winSum=454
2001 12:31:48.789487 TX Vref=32, minBit 1, minWin=27, winSum=452
2002 12:31:48.793012 [TxChooseVref] Worse bit 3, Min win 27, Win sum 454, Final Vref 30
2003 12:31:48.793122
2004 12:31:48.796106 Final TX Range 1 Vref 30
2005 12:31:48.796197
2006 12:31:48.796270 ==
2007 12:31:48.799623 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 12:31:48.802792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 12:31:48.802888 ==
2010 12:31:48.806276
2011 12:31:48.806362
2012 12:31:48.806428 TX Vref Scan disable
2013 12:31:48.809919 == TX Byte 0 ==
2014 12:31:48.812770 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
2015 12:31:48.819717 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
2016 12:31:48.819825 == TX Byte 1 ==
2017 12:31:48.822577 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2018 12:31:48.826102 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2019 12:31:48.829555
2020 12:31:48.829679 [DATLAT]
2021 12:31:48.829773 Freq=800, CH1 RK1
2022 12:31:48.829863
2023 12:31:48.833232 DATLAT Default: 0xa
2024 12:31:48.833327 0, 0xFFFF, sum = 0
2025 12:31:48.836236 1, 0xFFFF, sum = 0
2026 12:31:48.836349 2, 0xFFFF, sum = 0
2027 12:31:48.839733 3, 0xFFFF, sum = 0
2028 12:31:48.839847 4, 0xFFFF, sum = 0
2029 12:31:48.842670 5, 0xFFFF, sum = 0
2030 12:31:48.842793 6, 0xFFFF, sum = 0
2031 12:31:48.846537 7, 0xFFFF, sum = 0
2032 12:31:48.849812 8, 0xFFFF, sum = 0
2033 12:31:48.849911 9, 0x0, sum = 1
2034 12:31:48.849981 10, 0x0, sum = 2
2035 12:31:48.852667 11, 0x0, sum = 3
2036 12:31:48.852754 12, 0x0, sum = 4
2037 12:31:48.856042 best_step = 10
2038 12:31:48.856146
2039 12:31:48.856215 ==
2040 12:31:48.859607 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 12:31:48.863066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 12:31:48.863172 ==
2043 12:31:48.865866 RX Vref Scan: 0
2044 12:31:48.865997
2045 12:31:48.866101 RX Vref 0 -> 0, step: 1
2046 12:31:48.866203
2047 12:31:48.869386 RX Delay -95 -> 252, step: 8
2048 12:31:48.875914 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2049 12:31:48.879506 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2050 12:31:48.883041 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2051 12:31:48.885912 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2052 12:31:48.889329 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2053 12:31:48.895932 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2054 12:31:48.899664 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2055 12:31:48.902699 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2056 12:31:48.906157 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2057 12:31:48.909527 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2058 12:31:48.915966 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2059 12:31:48.919628 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2060 12:31:48.922529 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2061 12:31:48.925933 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2062 12:31:48.932394 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2063 12:31:48.936041 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2064 12:31:48.936160 ==
2065 12:31:48.939000 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 12:31:48.942521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 12:31:48.942647 ==
2068 12:31:48.946029 DQS Delay:
2069 12:31:48.946114 DQS0 = 0, DQS1 = 0
2070 12:31:48.946182 DQM Delay:
2071 12:31:48.948851 DQM0 = 86, DQM1 = 84
2072 12:31:48.948937 DQ Delay:
2073 12:31:48.952271 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2074 12:31:48.955503 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2075 12:31:48.959084 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
2076 12:31:48.962471 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
2077 12:31:48.962556
2078 12:31:48.962632
2079 12:31:48.972655 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2080 12:31:48.972749 CH1 RK1: MR19=606, MR18=1E39
2081 12:31:48.978789 CH1_RK1: MR19=0x606, MR18=0x1E39, DQSOSC=395, MR23=63, INC=94, DEC=63
2082 12:31:48.982206 [RxdqsGatingPostProcess] freq 800
2083 12:31:48.989016 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2084 12:31:48.992388 Pre-setting of DQS Precalculation
2085 12:31:48.995378 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2086 12:31:49.002513 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2087 12:31:49.012396 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2088 12:31:49.012486
2089 12:31:49.012563
2090 12:31:49.015878 [Calibration Summary] 1600 Mbps
2091 12:31:49.015964 CH 0, Rank 0
2092 12:31:49.018896 SW Impedance : PASS
2093 12:31:49.018979 DUTY Scan : NO K
2094 12:31:49.022307 ZQ Calibration : PASS
2095 12:31:49.022398 Jitter Meter : NO K
2096 12:31:49.025253 CBT Training : PASS
2097 12:31:49.028885 Write leveling : PASS
2098 12:31:49.028970 RX DQS gating : PASS
2099 12:31:49.032212 RX DQ/DQS(RDDQC) : PASS
2100 12:31:49.035652 TX DQ/DQS : PASS
2101 12:31:49.035729 RX DATLAT : PASS
2102 12:31:49.038554 RX DQ/DQS(Engine): PASS
2103 12:31:49.042055 TX OE : NO K
2104 12:31:49.042141 All Pass.
2105 12:31:49.042208
2106 12:31:49.042271 CH 0, Rank 1
2107 12:31:49.045598 SW Impedance : PASS
2108 12:31:49.048498 DUTY Scan : NO K
2109 12:31:49.048584 ZQ Calibration : PASS
2110 12:31:49.051930 Jitter Meter : NO K
2111 12:31:49.055263 CBT Training : PASS
2112 12:31:49.055357 Write leveling : PASS
2113 12:31:49.058712 RX DQS gating : PASS
2114 12:31:49.061663 RX DQ/DQS(RDDQC) : PASS
2115 12:31:49.061740 TX DQ/DQS : PASS
2116 12:31:49.065223 RX DATLAT : PASS
2117 12:31:49.068438 RX DQ/DQS(Engine): PASS
2118 12:31:49.068537 TX OE : NO K
2119 12:31:49.071566 All Pass.
2120 12:31:49.071646
2121 12:31:49.071712 CH 1, Rank 0
2122 12:31:49.074663 SW Impedance : PASS
2123 12:31:49.074814 DUTY Scan : NO K
2124 12:31:49.078511 ZQ Calibration : PASS
2125 12:31:49.081657 Jitter Meter : NO K
2126 12:31:49.081740 CBT Training : PASS
2127 12:31:49.084900 Write leveling : PASS
2128 12:31:49.084976 RX DQS gating : PASS
2129 12:31:49.088424 RX DQ/DQS(RDDQC) : PASS
2130 12:31:49.091338 TX DQ/DQS : PASS
2131 12:31:49.091425 RX DATLAT : PASS
2132 12:31:49.094675 RX DQ/DQS(Engine): PASS
2133 12:31:49.097995 TX OE : NO K
2134 12:31:49.098082 All Pass.
2135 12:31:49.098147
2136 12:31:49.098208 CH 1, Rank 1
2137 12:31:49.101583 SW Impedance : PASS
2138 12:31:49.105118 DUTY Scan : NO K
2139 12:31:49.105205 ZQ Calibration : PASS
2140 12:31:49.108135 Jitter Meter : NO K
2141 12:31:49.111613 CBT Training : PASS
2142 12:31:49.111689 Write leveling : PASS
2143 12:31:49.114937 RX DQS gating : PASS
2144 12:31:49.118315 RX DQ/DQS(RDDQC) : PASS
2145 12:31:49.118393 TX DQ/DQS : PASS
2146 12:31:49.121247 RX DATLAT : PASS
2147 12:31:49.124706 RX DQ/DQS(Engine): PASS
2148 12:31:49.124797 TX OE : NO K
2149 12:31:49.128244 All Pass.
2150 12:31:49.128325
2151 12:31:49.128390 DramC Write-DBI off
2152 12:31:49.131154 PER_BANK_REFRESH: Hybrid Mode
2153 12:31:49.131228 TX_TRACKING: ON
2154 12:31:49.134730 [GetDramInforAfterCalByMRR] Vendor 6.
2155 12:31:49.141538 [GetDramInforAfterCalByMRR] Revision 606.
2156 12:31:49.144508 [GetDramInforAfterCalByMRR] Revision 2 0.
2157 12:31:49.144617 MR0 0x3b3b
2158 12:31:49.144687 MR8 0x5151
2159 12:31:49.147917 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 12:31:49.148001
2161 12:31:49.151490 MR0 0x3b3b
2162 12:31:49.151572 MR8 0x5151
2163 12:31:49.154422 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 12:31:49.154499
2165 12:31:49.164796 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2166 12:31:49.167743 [FAST_K] Save calibration result to emmc
2167 12:31:49.171145 [FAST_K] Save calibration result to emmc
2168 12:31:49.174619 dram_init: config_dvfs: 1
2169 12:31:49.178083 dramc_set_vcore_voltage set vcore to 662500
2170 12:31:49.180898 Read voltage for 1200, 2
2171 12:31:49.180979 Vio18 = 0
2172 12:31:49.181089 Vcore = 662500
2173 12:31:49.184727 Vdram = 0
2174 12:31:49.184819 Vddq = 0
2175 12:31:49.184884 Vmddr = 0
2176 12:31:49.191109 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2177 12:31:49.194506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2178 12:31:49.198069 MEM_TYPE=3, freq_sel=15
2179 12:31:49.200954 sv_algorithm_assistance_LP4_1600
2180 12:31:49.204417 ============ PULL DRAM RESETB DOWN ============
2181 12:31:49.207906 ========== PULL DRAM RESETB DOWN end =========
2182 12:31:49.214352 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 12:31:49.217428 ===================================
2184 12:31:49.217519 LPDDR4 DRAM CONFIGURATION
2185 12:31:49.220789 ===================================
2186 12:31:49.224301 EX_ROW_EN[0] = 0x0
2187 12:31:49.227842 EX_ROW_EN[1] = 0x0
2188 12:31:49.227954 LP4Y_EN = 0x0
2189 12:31:49.230795 WORK_FSP = 0x0
2190 12:31:49.230886 WL = 0x4
2191 12:31:49.234368 RL = 0x4
2192 12:31:49.234471 BL = 0x2
2193 12:31:49.237311 RPST = 0x0
2194 12:31:49.237401 RD_PRE = 0x0
2195 12:31:49.240700 WR_PRE = 0x1
2196 12:31:49.240791 WR_PST = 0x0
2197 12:31:49.244214 DBI_WR = 0x0
2198 12:31:49.244324 DBI_RD = 0x0
2199 12:31:49.247822 OTF = 0x1
2200 12:31:49.250754 ===================================
2201 12:31:49.254288 ===================================
2202 12:31:49.254372 ANA top config
2203 12:31:49.257219 ===================================
2204 12:31:49.260581 DLL_ASYNC_EN = 0
2205 12:31:49.263939 ALL_SLAVE_EN = 0
2206 12:31:49.267315 NEW_RANK_MODE = 1
2207 12:31:49.267430 DLL_IDLE_MODE = 1
2208 12:31:49.270214 LP45_APHY_COMB_EN = 1
2209 12:31:49.273679 TX_ODT_DIS = 1
2210 12:31:49.277071 NEW_8X_MODE = 1
2211 12:31:49.280611 ===================================
2212 12:31:49.283952 ===================================
2213 12:31:49.286848 data_rate = 2400
2214 12:31:49.290095 CKR = 1
2215 12:31:49.290206 DQ_P2S_RATIO = 8
2216 12:31:49.293520 ===================================
2217 12:31:49.297012 CA_P2S_RATIO = 8
2218 12:31:49.299933 DQ_CA_OPEN = 0
2219 12:31:49.303422 DQ_SEMI_OPEN = 0
2220 12:31:49.306677 CA_SEMI_OPEN = 0
2221 12:31:49.306761 CA_FULL_RATE = 0
2222 12:31:49.310392 DQ_CKDIV4_EN = 0
2223 12:31:49.313195 CA_CKDIV4_EN = 0
2224 12:31:49.316675 CA_PREDIV_EN = 0
2225 12:31:49.319920 PH8_DLY = 17
2226 12:31:49.323594 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2227 12:31:49.323677 DQ_AAMCK_DIV = 4
2228 12:31:49.326639 CA_AAMCK_DIV = 4
2229 12:31:49.330145 CA_ADMCK_DIV = 4
2230 12:31:49.333680 DQ_TRACK_CA_EN = 0
2231 12:31:49.336655 CA_PICK = 1200
2232 12:31:49.340309 CA_MCKIO = 1200
2233 12:31:49.343624 MCKIO_SEMI = 0
2234 12:31:49.346572 PLL_FREQ = 2366
2235 12:31:49.346655 DQ_UI_PI_RATIO = 32
2236 12:31:49.349986 CA_UI_PI_RATIO = 0
2237 12:31:49.353490 ===================================
2238 12:31:49.356495 ===================================
2239 12:31:49.359939 memory_type:LPDDR4
2240 12:31:49.363322 GP_NUM : 10
2241 12:31:49.363405 SRAM_EN : 1
2242 12:31:49.366687 MD32_EN : 0
2243 12:31:49.370046 ===================================
2244 12:31:49.370129 [ANA_INIT] >>>>>>>>>>>>>>
2245 12:31:49.372915 <<<<<< [CONFIGURE PHASE]: ANA_TX
2246 12:31:49.376456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2247 12:31:49.379856 ===================================
2248 12:31:49.383161 data_rate = 2400,PCW = 0X5b00
2249 12:31:49.386095 ===================================
2250 12:31:49.389445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2251 12:31:49.396191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 12:31:49.402976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 12:31:49.406599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2254 12:31:49.409919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2255 12:31:49.412844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2256 12:31:49.416246 [ANA_INIT] flow start
2257 12:31:49.416328 [ANA_INIT] PLL >>>>>>>>
2258 12:31:49.419756 [ANA_INIT] PLL <<<<<<<<
2259 12:31:49.423082 [ANA_INIT] MIDPI >>>>>>>>
2260 12:31:49.423165 [ANA_INIT] MIDPI <<<<<<<<
2261 12:31:49.425975 [ANA_INIT] DLL >>>>>>>>
2262 12:31:49.429546 [ANA_INIT] DLL <<<<<<<<
2263 12:31:49.429628 [ANA_INIT] flow end
2264 12:31:49.435958 ============ LP4 DIFF to SE enter ============
2265 12:31:49.439482 ============ LP4 DIFF to SE exit ============
2266 12:31:49.442513 [ANA_INIT] <<<<<<<<<<<<<
2267 12:31:49.446017 [Flow] Enable top DCM control >>>>>
2268 12:31:49.449402 [Flow] Enable top DCM control <<<<<
2269 12:31:49.449484 Enable DLL master slave shuffle
2270 12:31:49.456203 ==============================================================
2271 12:31:49.459012 Gating Mode config
2272 12:31:49.462641 ==============================================================
2273 12:31:49.466071 Config description:
2274 12:31:49.475693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2275 12:31:49.482793 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2276 12:31:49.485701 SELPH_MODE 0: By rank 1: By Phase
2277 12:31:49.492288 ==============================================================
2278 12:31:49.495617 GAT_TRACK_EN = 1
2279 12:31:49.498823 RX_GATING_MODE = 2
2280 12:31:49.502292 RX_GATING_TRACK_MODE = 2
2281 12:31:49.505632 SELPH_MODE = 1
2282 12:31:49.505718 PICG_EARLY_EN = 1
2283 12:31:49.509187 VALID_LAT_VALUE = 1
2284 12:31:49.516077 ==============================================================
2285 12:31:49.518915 Enter into Gating configuration >>>>
2286 12:31:49.522389 Exit from Gating configuration <<<<
2287 12:31:49.525757 Enter into DVFS_PRE_config >>>>>
2288 12:31:49.535557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2289 12:31:49.539216 Exit from DVFS_PRE_config <<<<<
2290 12:31:49.542220 Enter into PICG configuration >>>>
2291 12:31:49.545873 Exit from PICG configuration <<<<
2292 12:31:49.548930 [RX_INPUT] configuration >>>>>
2293 12:31:49.552327 [RX_INPUT] configuration <<<<<
2294 12:31:49.555447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2295 12:31:49.562406 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2296 12:31:49.568947 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 12:31:49.575224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 12:31:49.581984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 12:31:49.588492 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 12:31:49.591868 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2301 12:31:49.595258 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2302 12:31:49.598680 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2303 12:31:49.601980 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2304 12:31:49.608289 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2305 12:31:49.611629 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 12:31:49.615084 ===================================
2307 12:31:49.618508 LPDDR4 DRAM CONFIGURATION
2308 12:31:49.621988 ===================================
2309 12:31:49.622097 EX_ROW_EN[0] = 0x0
2310 12:31:49.624915 EX_ROW_EN[1] = 0x0
2311 12:31:49.624997 LP4Y_EN = 0x0
2312 12:31:49.628336 WORK_FSP = 0x0
2313 12:31:49.628418 WL = 0x4
2314 12:31:49.631787 RL = 0x4
2315 12:31:49.634718 BL = 0x2
2316 12:31:49.634800 RPST = 0x0
2317 12:31:49.638274 RD_PRE = 0x0
2318 12:31:49.638356 WR_PRE = 0x1
2319 12:31:49.641764 WR_PST = 0x0
2320 12:31:49.641846 DBI_WR = 0x0
2321 12:31:49.644808 DBI_RD = 0x0
2322 12:31:49.644890 OTF = 0x1
2323 12:31:49.648234 ===================================
2324 12:31:49.651782 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2325 12:31:49.657953 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2326 12:31:49.661255 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 12:31:49.664728 ===================================
2328 12:31:49.667696 LPDDR4 DRAM CONFIGURATION
2329 12:31:49.671182 ===================================
2330 12:31:49.671265 EX_ROW_EN[0] = 0x10
2331 12:31:49.674762 EX_ROW_EN[1] = 0x0
2332 12:31:49.674843 LP4Y_EN = 0x0
2333 12:31:49.678130 WORK_FSP = 0x0
2334 12:31:49.678212 WL = 0x4
2335 12:31:49.680934 RL = 0x4
2336 12:31:49.684392 BL = 0x2
2337 12:31:49.684473 RPST = 0x0
2338 12:31:49.687947 RD_PRE = 0x0
2339 12:31:49.688050 WR_PRE = 0x1
2340 12:31:49.690883 WR_PST = 0x0
2341 12:31:49.690964 DBI_WR = 0x0
2342 12:31:49.694378 DBI_RD = 0x0
2343 12:31:49.694460 OTF = 0x1
2344 12:31:49.697730 ===================================
2345 12:31:49.704416 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2346 12:31:49.704499 ==
2347 12:31:49.707841 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 12:31:49.711046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2349 12:31:49.711154 ==
2350 12:31:49.714021 [Duty_Offset_Calibration]
2351 12:31:49.717492 B0:2 B1:0 CA:4
2352 12:31:49.717574
2353 12:31:49.720377 [DutyScan_Calibration_Flow] k_type=0
2354 12:31:49.727882
2355 12:31:49.727964 ==CLK 0==
2356 12:31:49.731413 Final CLK duty delay cell = -4
2357 12:31:49.734960 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2358 12:31:49.738335 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2359 12:31:49.741249 [-4] AVG Duty = 4937%(X100)
2360 12:31:49.741330
2361 12:31:49.744866 CH0 CLK Duty spec in!! Max-Min= 187%
2362 12:31:49.748355 [DutyScan_Calibration_Flow] ====Done====
2363 12:31:49.748437
2364 12:31:49.751115 [DutyScan_Calibration_Flow] k_type=1
2365 12:31:49.766932
2366 12:31:49.767029 ==DQS 0 ==
2367 12:31:49.770311 Final DQS duty delay cell = -4
2368 12:31:49.773848 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2369 12:31:49.776735 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2370 12:31:49.780260 [-4] AVG Duty = 4922%(X100)
2371 12:31:49.780342
2372 12:31:49.780405 ==DQS 1 ==
2373 12:31:49.783654 Final DQS duty delay cell = 0
2374 12:31:49.786926 [0] MAX Duty = 5125%(X100), DQS PI = 4
2375 12:31:49.790292 [0] MIN Duty = 5000%(X100), DQS PI = 0
2376 12:31:49.793318 [0] AVG Duty = 5062%(X100)
2377 12:31:49.793392
2378 12:31:49.796788 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2379 12:31:49.796858
2380 12:31:49.800135 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2381 12:31:49.803568 [DutyScan_Calibration_Flow] ====Done====
2382 12:31:49.803643
2383 12:31:49.806785 [DutyScan_Calibration_Flow] k_type=3
2384 12:31:49.823265
2385 12:31:49.823349 ==DQM 0 ==
2386 12:31:49.826756 Final DQM duty delay cell = 0
2387 12:31:49.830223 [0] MAX Duty = 5094%(X100), DQS PI = 18
2388 12:31:49.833561 [0] MIN Duty = 4844%(X100), DQS PI = 50
2389 12:31:49.836507 [0] AVG Duty = 4969%(X100)
2390 12:31:49.836588
2391 12:31:49.836652 ==DQM 1 ==
2392 12:31:49.839940 Final DQM duty delay cell = 0
2393 12:31:49.843430 [0] MAX Duty = 4969%(X100), DQS PI = 0
2394 12:31:49.846453 [0] MIN Duty = 4876%(X100), DQS PI = 20
2395 12:31:49.850014 [0] AVG Duty = 4922%(X100)
2396 12:31:49.850094
2397 12:31:49.853619 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2398 12:31:49.853700
2399 12:31:49.856622 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2400 12:31:49.859994 [DutyScan_Calibration_Flow] ====Done====
2401 12:31:49.860086
2402 12:31:49.863501 [DutyScan_Calibration_Flow] k_type=2
2403 12:31:49.879895
2404 12:31:49.879985 ==DQ 0 ==
2405 12:31:49.882889 Final DQ duty delay cell = 0
2406 12:31:49.886423 [0] MAX Duty = 5125%(X100), DQS PI = 18
2407 12:31:49.889928 [0] MIN Duty = 5000%(X100), DQS PI = 8
2408 12:31:49.890012 [0] AVG Duty = 5062%(X100)
2409 12:31:49.893183
2410 12:31:49.893265 ==DQ 1 ==
2411 12:31:49.896247 Final DQ duty delay cell = 0
2412 12:31:49.899703 [0] MAX Duty = 5125%(X100), DQS PI = 6
2413 12:31:49.903326 [0] MIN Duty = 4938%(X100), DQS PI = 14
2414 12:31:49.903410 [0] AVG Duty = 5031%(X100)
2415 12:31:49.903475
2416 12:31:49.906137 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2417 12:31:49.909755
2418 12:31:49.913316 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2419 12:31:49.916062 [DutyScan_Calibration_Flow] ====Done====
2420 12:31:49.916160 ==
2421 12:31:49.919889 Dram Type= 6, Freq= 0, CH_1, rank 0
2422 12:31:49.922833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2423 12:31:49.922918 ==
2424 12:31:49.926320 [Duty_Offset_Calibration]
2425 12:31:49.926429 B0:0 B1:-1 CA:3
2426 12:31:49.926523
2427 12:31:49.929758 [DutyScan_Calibration_Flow] k_type=0
2428 12:31:49.939512
2429 12:31:49.939598 ==CLK 0==
2430 12:31:49.943015 Final CLK duty delay cell = 0
2431 12:31:49.946607 [0] MAX Duty = 5156%(X100), DQS PI = 0
2432 12:31:49.949494 [0] MIN Duty = 5031%(X100), DQS PI = 36
2433 12:31:49.949578 [0] AVG Duty = 5093%(X100)
2434 12:31:49.953033
2435 12:31:49.956781 CH1 CLK Duty spec in!! Max-Min= 125%
2436 12:31:49.959715 [DutyScan_Calibration_Flow] ====Done====
2437 12:31:49.959798
2438 12:31:49.963159 [DutyScan_Calibration_Flow] k_type=1
2439 12:31:49.978024
2440 12:31:49.978110 ==DQS 0 ==
2441 12:31:49.981493 Final DQS duty delay cell = 0
2442 12:31:49.984998 [0] MAX Duty = 5187%(X100), DQS PI = 18
2443 12:31:49.987905 [0] MIN Duty = 4907%(X100), DQS PI = 38
2444 12:31:49.991340 [0] AVG Duty = 5047%(X100)
2445 12:31:49.991423
2446 12:31:49.991489 ==DQS 1 ==
2447 12:31:49.994728 Final DQS duty delay cell = -4
2448 12:31:49.998089 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2449 12:31:50.001113 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2450 12:31:50.004761 [-4] AVG Duty = 4937%(X100)
2451 12:31:50.004844
2452 12:31:50.007949 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2453 12:31:50.008094
2454 12:31:50.011384 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2455 12:31:50.014165 [DutyScan_Calibration_Flow] ====Done====
2456 12:31:50.014247
2457 12:31:50.017467 [DutyScan_Calibration_Flow] k_type=3
2458 12:31:50.035592
2459 12:31:50.035683 ==DQM 0 ==
2460 12:31:50.039098 Final DQM duty delay cell = 0
2461 12:31:50.042599 [0] MAX Duty = 5031%(X100), DQS PI = 28
2462 12:31:50.045490 [0] MIN Duty = 4813%(X100), DQS PI = 38
2463 12:31:50.049138 [0] AVG Duty = 4922%(X100)
2464 12:31:50.049223
2465 12:31:50.049307 ==DQM 1 ==
2466 12:31:50.052020 Final DQM duty delay cell = 4
2467 12:31:50.055647 [4] MAX Duty = 5187%(X100), DQS PI = 30
2468 12:31:50.059205 [4] MIN Duty = 5062%(X100), DQS PI = 0
2469 12:31:50.062235 [4] AVG Duty = 5124%(X100)
2470 12:31:50.062320
2471 12:31:50.065727 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2472 12:31:50.065812
2473 12:31:50.068582 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2474 12:31:50.072160 [DutyScan_Calibration_Flow] ====Done====
2475 12:31:50.072245
2476 12:31:50.075631 [DutyScan_Calibration_Flow] k_type=2
2477 12:31:50.091203
2478 12:31:50.091292 ==DQ 0 ==
2479 12:31:50.094709 Final DQ duty delay cell = -4
2480 12:31:50.098041 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2481 12:31:50.101342 [-4] MIN Duty = 4876%(X100), DQS PI = 34
2482 12:31:50.104840 [-4] AVG Duty = 4938%(X100)
2483 12:31:50.104925
2484 12:31:50.105009 ==DQ 1 ==
2485 12:31:50.107731 Final DQ duty delay cell = 0
2486 12:31:50.111140 [0] MAX Duty = 5031%(X100), DQS PI = 34
2487 12:31:50.114539 [0] MIN Duty = 4844%(X100), DQS PI = 62
2488 12:31:50.117992 [0] AVG Duty = 4937%(X100)
2489 12:31:50.118077
2490 12:31:50.121141 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2491 12:31:50.121225
2492 12:31:50.124588 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2493 12:31:50.127966 [DutyScan_Calibration_Flow] ====Done====
2494 12:31:50.131329 nWR fixed to 30
2495 12:31:50.134806 [ModeRegInit_LP4] CH0 RK0
2496 12:31:50.134889 [ModeRegInit_LP4] CH0 RK1
2497 12:31:50.137606 [ModeRegInit_LP4] CH1 RK0
2498 12:31:50.141118 [ModeRegInit_LP4] CH1 RK1
2499 12:31:50.141200 match AC timing 7
2500 12:31:50.147707 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2501 12:31:50.151127 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2502 12:31:50.154747 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2503 12:31:50.161176 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2504 12:31:50.164148 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2505 12:31:50.164231 ==
2506 12:31:50.167701 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 12:31:50.170987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 12:31:50.171069 ==
2509 12:31:50.177532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 12:31:50.183742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 12:31:50.191535 [CA 0] Center 39 (9~70) winsize 62
2512 12:31:50.195105 [CA 1] Center 39 (9~70) winsize 62
2513 12:31:50.198009 [CA 2] Center 35 (5~66) winsize 62
2514 12:31:50.201494 [CA 3] Center 35 (5~66) winsize 62
2515 12:31:50.204875 [CA 4] Center 33 (3~64) winsize 62
2516 12:31:50.208419 [CA 5] Center 33 (3~64) winsize 62
2517 12:31:50.208544
2518 12:31:50.211310 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 12:31:50.211409
2520 12:31:50.214933 [CATrainingPosCal] consider 1 rank data
2521 12:31:50.218484 u2DelayCellTimex100 = 270/100 ps
2522 12:31:50.221183 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 12:31:50.227955 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 12:31:50.231315 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 12:31:50.234678 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 12:31:50.237620 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2527 12:31:50.241080 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2528 12:31:50.241163
2529 12:31:50.244466 CA PerBit enable=1, Macro0, CA PI delay=33
2530 12:31:50.244574
2531 12:31:50.247944 [CBTSetCACLKResult] CA Dly = 33
2532 12:31:50.250712 CS Dly: 7 (0~38)
2533 12:31:50.250794 ==
2534 12:31:50.254478 Dram Type= 6, Freq= 0, CH_0, rank 1
2535 12:31:50.257434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 12:31:50.257523 ==
2537 12:31:50.264590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 12:31:50.267316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2539 12:31:50.277405 [CA 0] Center 39 (9~70) winsize 62
2540 12:31:50.280804 [CA 1] Center 39 (9~70) winsize 62
2541 12:31:50.283806 [CA 2] Center 35 (5~66) winsize 62
2542 12:31:50.287352 [CA 3] Center 35 (5~66) winsize 62
2543 12:31:50.290725 [CA 4] Center 34 (4~65) winsize 62
2544 12:31:50.293832 [CA 5] Center 33 (3~64) winsize 62
2545 12:31:50.293915
2546 12:31:50.297356 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2547 12:31:50.297438
2548 12:31:50.300897 [CATrainingPosCal] consider 2 rank data
2549 12:31:50.303817 u2DelayCellTimex100 = 270/100 ps
2550 12:31:50.307281 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 12:31:50.313761 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2552 12:31:50.317206 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 12:31:50.320612 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 12:31:50.323919 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2555 12:31:50.327334 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2556 12:31:50.327414
2557 12:31:50.330665 CA PerBit enable=1, Macro0, CA PI delay=33
2558 12:31:50.330769
2559 12:31:50.334101 [CBTSetCACLKResult] CA Dly = 33
2560 12:31:50.334206 CS Dly: 8 (0~41)
2561 12:31:50.337491
2562 12:31:50.340357 ----->DramcWriteLeveling(PI) begin...
2563 12:31:50.340435 ==
2564 12:31:50.343898 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 12:31:50.347153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 12:31:50.347229 ==
2567 12:31:50.350546 Write leveling (Byte 0): 32 => 32
2568 12:31:50.354147 Write leveling (Byte 1): 28 => 28
2569 12:31:50.356846 DramcWriteLeveling(PI) end<-----
2570 12:31:50.356929
2571 12:31:50.356995 ==
2572 12:31:50.360325 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 12:31:50.363926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 12:31:50.364078 ==
2575 12:31:50.366805 [Gating] SW mode calibration
2576 12:31:50.373743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2577 12:31:50.380258 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2578 12:31:50.383124 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2579 12:31:50.386658 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2580 12:31:50.393581 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 12:31:50.396428 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 12:31:50.399889 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 12:31:50.406717 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 12:31:50.409707 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2585 12:31:50.412945 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
2586 12:31:50.419856 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
2587 12:31:50.423248 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2588 12:31:50.426676 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 12:31:50.433433 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 12:31:50.436143 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 12:31:50.439460 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 12:31:50.446273 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2593 12:31:50.449746 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2594 12:31:50.452609 1 1 0 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
2595 12:31:50.459429 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 12:31:50.462872 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 12:31:50.465914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 12:31:50.472931 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 12:31:50.476001 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 12:31:50.479575 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 12:31:50.482549 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2602 12:31:50.489573 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 12:31:50.492562 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:31:50.496070 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:31:50.502506 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:31:50.505860 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:31:50.509390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:31:50.515970 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:31:50.519518 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:31:50.522369 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:31:50.529152 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:31:50.532542 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:31:50.535911 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:31:50.542255 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:31:50.545588 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:31:50.549079 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:31:50.555500 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 12:31:50.559060 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2619 12:31:50.562313 Total UI for P1: 0, mck2ui 16
2620 12:31:50.565862 best dqsien dly found for B0: ( 1, 3, 28)
2621 12:31:50.568781 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 12:31:50.572530 Total UI for P1: 0, mck2ui 16
2623 12:31:50.575903 best dqsien dly found for B1: ( 1, 4, 0)
2624 12:31:50.578941 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2625 12:31:50.582422 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2626 12:31:50.582507
2627 12:31:50.588979 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2628 12:31:50.591942 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2629 12:31:50.592083 [Gating] SW calibration Done
2630 12:31:50.595400 ==
2631 12:31:50.598938 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 12:31:50.601807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 12:31:50.601893 ==
2634 12:31:50.601960 RX Vref Scan: 0
2635 12:31:50.602021
2636 12:31:50.605083 RX Vref 0 -> 0, step: 1
2637 12:31:50.605167
2638 12:31:50.608540 RX Delay -40 -> 252, step: 8
2639 12:31:50.611675 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2640 12:31:50.615072 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2641 12:31:50.621869 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2642 12:31:50.625473 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2643 12:31:50.628449 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2644 12:31:50.631934 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2645 12:31:50.635057 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2646 12:31:50.641409 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2647 12:31:50.644853 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2648 12:31:50.648206 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2649 12:31:50.651713 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2650 12:31:50.655188 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2651 12:31:50.661605 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2652 12:31:50.665013 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2653 12:31:50.668296 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2654 12:31:50.671672 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2655 12:31:50.671750 ==
2656 12:31:50.675049 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 12:31:50.678624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 12:31:50.681612 ==
2659 12:31:50.681689 DQS Delay:
2660 12:31:50.681752 DQS0 = 0, DQS1 = 0
2661 12:31:50.685045 DQM Delay:
2662 12:31:50.685127 DQM0 = 118, DQM1 = 107
2663 12:31:50.688669 DQ Delay:
2664 12:31:50.691903 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2665 12:31:50.694861 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2666 12:31:50.698556 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2667 12:31:50.701396 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2668 12:31:50.701500
2669 12:31:50.701569
2670 12:31:50.701628 ==
2671 12:31:50.704874 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 12:31:50.708360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 12:31:50.708448 ==
2674 12:31:50.708517
2675 12:31:50.708579
2676 12:31:50.711321 TX Vref Scan disable
2677 12:31:50.714848 == TX Byte 0 ==
2678 12:31:50.718296 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2679 12:31:50.721668 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2680 12:31:50.724528 == TX Byte 1 ==
2681 12:31:50.728519 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2682 12:31:50.731506 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2683 12:31:50.731591 ==
2684 12:31:50.734916 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 12:31:50.741657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 12:31:50.741746 ==
2687 12:31:50.751966 TX Vref=22, minBit 1, minWin=25, winSum=412
2688 12:31:50.755306 TX Vref=24, minBit 1, minWin=25, winSum=419
2689 12:31:50.758678 TX Vref=26, minBit 1, minWin=26, winSum=430
2690 12:31:50.762180 TX Vref=28, minBit 5, minWin=26, winSum=431
2691 12:31:50.765629 TX Vref=30, minBit 4, minWin=26, winSum=430
2692 12:31:50.771862 TX Vref=32, minBit 4, minWin=26, winSum=430
2693 12:31:50.775414 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 28
2694 12:31:50.775500
2695 12:31:50.778611 Final TX Range 1 Vref 28
2696 12:31:50.778695
2697 12:31:50.778761 ==
2698 12:31:50.781600 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 12:31:50.785093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 12:31:50.788029 ==
2701 12:31:50.788151
2702 12:31:50.788221
2703 12:31:50.788285 TX Vref Scan disable
2704 12:31:50.791722 == TX Byte 0 ==
2705 12:31:50.795148 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2706 12:31:50.798548 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2707 12:31:50.802171 == TX Byte 1 ==
2708 12:31:50.805079 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2709 12:31:50.808580 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2710 12:31:50.812014
2711 12:31:50.812133 [DATLAT]
2712 12:31:50.812199 Freq=1200, CH0 RK0
2713 12:31:50.812260
2714 12:31:50.814984 DATLAT Default: 0xd
2715 12:31:50.815066 0, 0xFFFF, sum = 0
2716 12:31:50.818416 1, 0xFFFF, sum = 0
2717 12:31:50.818500 2, 0xFFFF, sum = 0
2718 12:31:50.821893 3, 0xFFFF, sum = 0
2719 12:31:50.825456 4, 0xFFFF, sum = 0
2720 12:31:50.825566 5, 0xFFFF, sum = 0
2721 12:31:50.828333 6, 0xFFFF, sum = 0
2722 12:31:50.828417 7, 0xFFFF, sum = 0
2723 12:31:50.831650 8, 0xFFFF, sum = 0
2724 12:31:50.831734 9, 0xFFFF, sum = 0
2725 12:31:50.834598 10, 0xFFFF, sum = 0
2726 12:31:50.834681 11, 0xFFFF, sum = 0
2727 12:31:50.838097 12, 0x0, sum = 1
2728 12:31:50.838181 13, 0x0, sum = 2
2729 12:31:50.841521 14, 0x0, sum = 3
2730 12:31:50.841605 15, 0x0, sum = 4
2731 12:31:50.844998 best_step = 13
2732 12:31:50.845107
2733 12:31:50.845188 ==
2734 12:31:50.848268 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 12:31:50.851328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 12:31:50.851412 ==
2737 12:31:50.851476 RX Vref Scan: 1
2738 12:31:50.854792
2739 12:31:50.854874 Set Vref Range= 32 -> 127
2740 12:31:50.854939
2741 12:31:50.858194 RX Vref 32 -> 127, step: 1
2742 12:31:50.858329
2743 12:31:50.860912 RX Delay -21 -> 252, step: 4
2744 12:31:50.861045
2745 12:31:50.864393 Set Vref, RX VrefLevel [Byte0]: 32
2746 12:31:50.867888 [Byte1]: 32
2747 12:31:50.868019
2748 12:31:50.871189 Set Vref, RX VrefLevel [Byte0]: 33
2749 12:31:50.874406 [Byte1]: 33
2750 12:31:50.878263
2751 12:31:50.878396 Set Vref, RX VrefLevel [Byte0]: 34
2752 12:31:50.881694 [Byte1]: 34
2753 12:31:50.886328
2754 12:31:50.886463 Set Vref, RX VrefLevel [Byte0]: 35
2755 12:31:50.889376 [Byte1]: 35
2756 12:31:50.894053
2757 12:31:50.894184 Set Vref, RX VrefLevel [Byte0]: 36
2758 12:31:50.900496 [Byte1]: 36
2759 12:31:50.900629
2760 12:31:50.904035 Set Vref, RX VrefLevel [Byte0]: 37
2761 12:31:50.907047 [Byte1]: 37
2762 12:31:50.907175
2763 12:31:50.910589 Set Vref, RX VrefLevel [Byte0]: 38
2764 12:31:50.914018 [Byte1]: 38
2765 12:31:50.918086
2766 12:31:50.918214 Set Vref, RX VrefLevel [Byte0]: 39
2767 12:31:50.921042 [Byte1]: 39
2768 12:31:50.925682
2769 12:31:50.925815 Set Vref, RX VrefLevel [Byte0]: 40
2770 12:31:50.929043 [Byte1]: 40
2771 12:31:50.934254
2772 12:31:50.934385 Set Vref, RX VrefLevel [Byte0]: 41
2773 12:31:50.937404 [Byte1]: 41
2774 12:31:50.941526
2775 12:31:50.941659 Set Vref, RX VrefLevel [Byte0]: 42
2776 12:31:50.944857 [Byte1]: 42
2777 12:31:50.949655
2778 12:31:50.949797 Set Vref, RX VrefLevel [Byte0]: 43
2779 12:31:50.953027 [Byte1]: 43
2780 12:31:50.957536
2781 12:31:50.957697 Set Vref, RX VrefLevel [Byte0]: 44
2782 12:31:50.960910 [Byte1]: 44
2783 12:31:50.965649
2784 12:31:50.965820 Set Vref, RX VrefLevel [Byte0]: 45
2785 12:31:50.968647 [Byte1]: 45
2786 12:31:50.973183
2787 12:31:50.973282 Set Vref, RX VrefLevel [Byte0]: 46
2788 12:31:50.976567 [Byte1]: 46
2789 12:31:50.981159
2790 12:31:50.981245 Set Vref, RX VrefLevel [Byte0]: 47
2791 12:31:50.984532 [Byte1]: 47
2792 12:31:50.989322
2793 12:31:50.989405 Set Vref, RX VrefLevel [Byte0]: 48
2794 12:31:50.992831 [Byte1]: 48
2795 12:31:50.997103
2796 12:31:50.997185 Set Vref, RX VrefLevel [Byte0]: 49
2797 12:31:51.000538 [Byte1]: 49
2798 12:31:51.005081
2799 12:31:51.005164 Set Vref, RX VrefLevel [Byte0]: 50
2800 12:31:51.008536 [Byte1]: 50
2801 12:31:51.012800
2802 12:31:51.012882 Set Vref, RX VrefLevel [Byte0]: 51
2803 12:31:51.016219 [Byte1]: 51
2804 12:31:51.021266
2805 12:31:51.021361 Set Vref, RX VrefLevel [Byte0]: 52
2806 12:31:51.024219 [Byte1]: 52
2807 12:31:51.028947
2808 12:31:51.032319 Set Vref, RX VrefLevel [Byte0]: 53
2809 12:31:51.032488 [Byte1]: 53
2810 12:31:51.036860
2811 12:31:51.036988 Set Vref, RX VrefLevel [Byte0]: 54
2812 12:31:51.040101 [Byte1]: 54
2813 12:31:51.044736
2814 12:31:51.044824 Set Vref, RX VrefLevel [Byte0]: 55
2815 12:31:51.048176 [Byte1]: 55
2816 12:31:51.052734
2817 12:31:51.052818 Set Vref, RX VrefLevel [Byte0]: 56
2818 12:31:51.056083 [Byte1]: 56
2819 12:31:51.060576
2820 12:31:51.060659 Set Vref, RX VrefLevel [Byte0]: 57
2821 12:31:51.063996 [Byte1]: 57
2822 12:31:51.068498
2823 12:31:51.068582 Set Vref, RX VrefLevel [Byte0]: 58
2824 12:31:51.072090 [Byte1]: 58
2825 12:31:51.076576
2826 12:31:51.076659 Set Vref, RX VrefLevel [Byte0]: 59
2827 12:31:51.079967 [Byte1]: 59
2828 12:31:51.084508
2829 12:31:51.084591 Set Vref, RX VrefLevel [Byte0]: 60
2830 12:31:51.087893 [Byte1]: 60
2831 12:31:51.092480
2832 12:31:51.092564 Set Vref, RX VrefLevel [Byte0]: 61
2833 12:31:51.095486 [Byte1]: 61
2834 12:31:51.100183
2835 12:31:51.100292 Set Vref, RX VrefLevel [Byte0]: 62
2836 12:31:51.103556 [Byte1]: 62
2837 12:31:51.108307
2838 12:31:51.108390 Set Vref, RX VrefLevel [Byte0]: 63
2839 12:31:51.111303 [Byte1]: 63
2840 12:31:51.116056
2841 12:31:51.116153 Set Vref, RX VrefLevel [Byte0]: 64
2842 12:31:51.119549 [Byte1]: 64
2843 12:31:51.124238
2844 12:31:51.124321 Set Vref, RX VrefLevel [Byte0]: 65
2845 12:31:51.127130 [Byte1]: 65
2846 12:31:51.131859
2847 12:31:51.131942 Set Vref, RX VrefLevel [Byte0]: 66
2848 12:31:51.135360 [Byte1]: 66
2849 12:31:51.140017
2850 12:31:51.140135 Set Vref, RX VrefLevel [Byte0]: 67
2851 12:31:51.143388 [Byte1]: 67
2852 12:31:51.147833
2853 12:31:51.147917 Final RX Vref Byte 0 = 52 to rank0
2854 12:31:51.150817 Final RX Vref Byte 1 = 59 to rank0
2855 12:31:51.154242 Final RX Vref Byte 0 = 52 to rank1
2856 12:31:51.157893 Final RX Vref Byte 1 = 59 to rank1==
2857 12:31:51.161245 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 12:31:51.167545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 12:31:51.167630 ==
2860 12:31:51.167697 DQS Delay:
2861 12:31:51.170855 DQS0 = 0, DQS1 = 0
2862 12:31:51.170938 DQM Delay:
2863 12:31:51.171005 DQM0 = 117, DQM1 = 105
2864 12:31:51.174320 DQ Delay:
2865 12:31:51.177296 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2866 12:31:51.180808 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2867 12:31:51.184246 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2868 12:31:51.187363 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2869 12:31:51.187446
2870 12:31:51.187512
2871 12:31:51.197471 [DQSOSCAuto] RK0, (LSB)MR18= 0xfef9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2872 12:31:51.197559 CH0 RK0: MR19=303, MR18=FEF9
2873 12:31:51.203997 CH0_RK0: MR19=0x303, MR18=0xFEF9, DQSOSC=410, MR23=63, INC=39, DEC=26
2874 12:31:51.204121
2875 12:31:51.207335 ----->DramcWriteLeveling(PI) begin...
2876 12:31:51.207421 ==
2877 12:31:51.210849 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 12:31:51.217480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 12:31:51.217593 ==
2880 12:31:51.220847 Write leveling (Byte 0): 32 => 32
2881 12:31:51.220935 Write leveling (Byte 1): 27 => 27
2882 12:31:51.223754 DramcWriteLeveling(PI) end<-----
2883 12:31:51.223840
2884 12:31:51.227233 ==
2885 12:31:51.227322 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 12:31:51.233701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 12:31:51.233811 ==
2888 12:31:51.237290 [Gating] SW mode calibration
2889 12:31:51.243680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 12:31:51.247080 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 12:31:51.253993 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2892 12:31:51.257555 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 12:31:51.260508 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 12:31:51.267182 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 12:31:51.270540 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 12:31:51.273733 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 12:31:51.280495 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2898 12:31:51.283366 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
2899 12:31:51.286757 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2900 12:31:51.293485 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2901 12:31:51.297132 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 12:31:51.299969 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 12:31:51.303586 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 12:31:51.310319 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 12:31:51.313654 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2906 12:31:51.316616 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2907 12:31:51.323272 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2908 12:31:51.326784 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 12:31:51.330153 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 12:31:51.336520 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 12:31:51.340064 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 12:31:51.343509 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 12:31:51.349781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 12:31:51.353092 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 12:31:51.356491 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2916 12:31:51.363076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:31:51.366333 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:31:51.369853 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:31:51.376498 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:31:51.379929 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:31:51.382696 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:31:51.389688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:31:51.393009 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:31:51.396409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:31:51.402551 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 12:31:51.405959 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:31:51.409365 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:31:51.415796 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:31:51.419269 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2930 12:31:51.422817 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2931 12:31:51.425751 Total UI for P1: 0, mck2ui 16
2932 12:31:51.429235 best dqsien dly found for B0: ( 1, 3, 24)
2933 12:31:51.435767 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2934 12:31:51.439225 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 12:31:51.442232 Total UI for P1: 0, mck2ui 16
2936 12:31:51.445641 best dqsien dly found for B1: ( 1, 4, 0)
2937 12:31:51.449200 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2938 12:31:51.452564 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2939 12:31:51.452678
2940 12:31:51.455876 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2941 12:31:51.458819 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2942 12:31:51.462439 [Gating] SW calibration Done
2943 12:31:51.462556 ==
2944 12:31:51.465883 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 12:31:51.468844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 12:31:51.472018 ==
2947 12:31:51.472148 RX Vref Scan: 0
2948 12:31:51.472218
2949 12:31:51.475467 RX Vref 0 -> 0, step: 1
2950 12:31:51.475556
2951 12:31:51.478971 RX Delay -40 -> 252, step: 8
2952 12:31:51.482237 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2953 12:31:51.485831 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2954 12:31:51.488831 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2955 12:31:51.492115 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2956 12:31:51.498865 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2957 12:31:51.502230 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2958 12:31:51.505420 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2959 12:31:51.508505 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2960 12:31:51.512006 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2961 12:31:51.518465 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2962 12:31:51.521880 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2963 12:31:51.524925 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2964 12:31:51.528527 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2965 12:31:51.531536 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2966 12:31:51.538286 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2967 12:31:51.541715 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2968 12:31:51.541823 ==
2969 12:31:51.545220 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 12:31:51.548331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 12:31:51.548439 ==
2972 12:31:51.551721 DQS Delay:
2973 12:31:51.551831 DQS0 = 0, DQS1 = 0
2974 12:31:51.551903 DQM Delay:
2975 12:31:51.555073 DQM0 = 116, DQM1 = 109
2976 12:31:51.555195 DQ Delay:
2977 12:31:51.558459 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2978 12:31:51.561393 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =123
2979 12:31:51.568211 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2980 12:31:51.571723 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2981 12:31:51.571863
2982 12:31:51.571975
2983 12:31:51.572109 ==
2984 12:31:51.574635 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 12:31:51.577795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 12:31:51.577918 ==
2987 12:31:51.578015
2988 12:31:51.578137
2989 12:31:51.581301 TX Vref Scan disable
2990 12:31:51.581419 == TX Byte 0 ==
2991 12:31:51.587926 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2992 12:31:51.591446 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2993 12:31:51.591576 == TX Byte 1 ==
2994 12:31:51.597918 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2995 12:31:51.601465 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2996 12:31:51.601661 ==
2997 12:31:51.604720 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 12:31:51.607916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 12:31:51.608091 ==
3000 12:31:51.621449 TX Vref=22, minBit 10, minWin=25, winSum=415
3001 12:31:51.624949 TX Vref=24, minBit 3, minWin=25, winSum=421
3002 12:31:51.628354 TX Vref=26, minBit 2, minWin=26, winSum=425
3003 12:31:51.631244 TX Vref=28, minBit 2, minWin=26, winSum=425
3004 12:31:51.634927 TX Vref=30, minBit 10, minWin=26, winSum=429
3005 12:31:51.641222 TX Vref=32, minBit 12, minWin=25, winSum=427
3006 12:31:51.644644 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 30
3007 12:31:51.644731
3008 12:31:51.648099 Final TX Range 1 Vref 30
3009 12:31:51.648184
3010 12:31:51.648253 ==
3011 12:31:51.651052 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 12:31:51.654546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 12:31:51.657956 ==
3014 12:31:51.658069
3015 12:31:51.658164
3016 12:31:51.658256 TX Vref Scan disable
3017 12:31:51.661863 == TX Byte 0 ==
3018 12:31:51.664745 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3019 12:31:51.671523 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3020 12:31:51.671613 == TX Byte 1 ==
3021 12:31:51.675021 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3022 12:31:51.681222 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3023 12:31:51.681315
3024 12:31:51.681384 [DATLAT]
3025 12:31:51.681446 Freq=1200, CH0 RK1
3026 12:31:51.681507
3027 12:31:51.684669 DATLAT Default: 0xd
3028 12:31:51.687950 0, 0xFFFF, sum = 0
3029 12:31:51.688096 1, 0xFFFF, sum = 0
3030 12:31:51.691383 2, 0xFFFF, sum = 0
3031 12:31:51.691469 3, 0xFFFF, sum = 0
3032 12:31:51.694660 4, 0xFFFF, sum = 0
3033 12:31:51.694747 5, 0xFFFF, sum = 0
3034 12:31:51.697619 6, 0xFFFF, sum = 0
3035 12:31:51.697702 7, 0xFFFF, sum = 0
3036 12:31:51.701206 8, 0xFFFF, sum = 0
3037 12:31:51.701302 9, 0xFFFF, sum = 0
3038 12:31:51.704716 10, 0xFFFF, sum = 0
3039 12:31:51.704813 11, 0xFFFF, sum = 0
3040 12:31:51.707569 12, 0x0, sum = 1
3041 12:31:51.707659 13, 0x0, sum = 2
3042 12:31:51.711003 14, 0x0, sum = 3
3043 12:31:51.711102 15, 0x0, sum = 4
3044 12:31:51.714560 best_step = 13
3045 12:31:51.714654
3046 12:31:51.714723 ==
3047 12:31:51.718042 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 12:31:51.720848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 12:31:51.720941 ==
3050 12:31:51.721010 RX Vref Scan: 0
3051 12:31:51.724423
3052 12:31:51.724558 RX Vref 0 -> 0, step: 1
3053 12:31:51.724628
3054 12:31:51.727944 RX Delay -21 -> 252, step: 4
3055 12:31:51.734517 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3056 12:31:51.737483 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3057 12:31:51.740748 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3058 12:31:51.744326 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3059 12:31:51.747603 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3060 12:31:51.754209 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3061 12:31:51.757776 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3062 12:31:51.760683 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3063 12:31:51.763886 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3064 12:31:51.767217 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3065 12:31:51.770691 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3066 12:31:51.777418 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3067 12:31:51.780871 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3068 12:31:51.783806 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3069 12:31:51.787742 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3070 12:31:51.793829 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3071 12:31:51.793918 ==
3072 12:31:51.797222 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 12:31:51.800469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 12:31:51.800568 ==
3075 12:31:51.800663 DQS Delay:
3076 12:31:51.803992 DQS0 = 0, DQS1 = 0
3077 12:31:51.804117 DQM Delay:
3078 12:31:51.807327 DQM0 = 115, DQM1 = 106
3079 12:31:51.807410 DQ Delay:
3080 12:31:51.810924 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3081 12:31:51.813709 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3082 12:31:51.817060 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3083 12:31:51.820537 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3084 12:31:51.820622
3085 12:31:51.820689
3086 12:31:51.830459 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3087 12:31:51.833989 CH0 RK1: MR19=303, MR18=FEFC
3088 12:31:51.836828 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3089 12:31:51.840427 [RxdqsGatingPostProcess] freq 1200
3090 12:31:51.846940 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 12:31:51.850220 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 12:31:51.853709 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 12:31:51.857200 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 12:31:51.860181 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 12:31:51.863618 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 12:31:51.867173 best DQS1 dly(2T, 0.5T) = (0, 12)
3097 12:31:51.870424 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 12:31:51.874014 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3099 12:31:51.874103 Pre-setting of DQS Precalculation
3100 12:31:51.880696 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 12:31:51.880799 ==
3102 12:31:51.883595 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 12:31:51.887067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 12:31:51.887155 ==
3105 12:31:51.894041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 12:31:51.900248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 12:31:51.908192 [CA 0] Center 37 (7~68) winsize 62
3108 12:31:51.911489 [CA 1] Center 37 (7~68) winsize 62
3109 12:31:51.914378 [CA 2] Center 35 (6~65) winsize 60
3110 12:31:51.917808 [CA 3] Center 34 (4~64) winsize 61
3111 12:31:51.921194 [CA 4] Center 34 (4~65) winsize 62
3112 12:31:51.924741 [CA 5] Center 34 (4~64) winsize 61
3113 12:31:51.924880
3114 12:31:51.927741 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3115 12:31:51.927874
3116 12:31:51.931273 [CATrainingPosCal] consider 1 rank data
3117 12:31:51.934763 u2DelayCellTimex100 = 270/100 ps
3118 12:31:51.937674 CA0 delay=37 (7~68),Diff = 3 PI (14 cell)
3119 12:31:51.941222 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3120 12:31:51.947835 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3121 12:31:51.951564 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3122 12:31:51.954176 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3123 12:31:51.957507 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3124 12:31:51.957664
3125 12:31:51.960982 CA PerBit enable=1, Macro0, CA PI delay=34
3126 12:31:51.961147
3127 12:31:51.964647 [CBTSetCACLKResult] CA Dly = 34
3128 12:31:51.964816 CS Dly: 5 (0~36)
3129 12:31:51.968091 ==
3130 12:31:51.968246 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 12:31:51.974368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 12:31:51.974548 ==
3133 12:31:51.977824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 12:31:51.984529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 12:31:51.993788 [CA 0] Center 38 (8~68) winsize 61
3136 12:31:51.996584 [CA 1] Center 38 (8~69) winsize 62
3137 12:31:51.999918 [CA 2] Center 35 (5~65) winsize 61
3138 12:31:52.003362 [CA 3] Center 33 (3~64) winsize 62
3139 12:31:52.006691 [CA 4] Center 34 (4~64) winsize 61
3140 12:31:52.009953 [CA 5] Center 33 (3~64) winsize 62
3141 12:31:52.010058
3142 12:31:52.013323 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 12:31:52.013424
3144 12:31:52.016778 [CATrainingPosCal] consider 2 rank data
3145 12:31:52.020297 u2DelayCellTimex100 = 270/100 ps
3146 12:31:52.023693 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3147 12:31:52.026670 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3148 12:31:52.033727 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3149 12:31:52.036619 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3150 12:31:52.040201 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3151 12:31:52.043464 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3152 12:31:52.043562
3153 12:31:52.046480 CA PerBit enable=1, Macro0, CA PI delay=34
3154 12:31:52.046568
3155 12:31:52.050013 [CBTSetCACLKResult] CA Dly = 34
3156 12:31:52.050130 CS Dly: 6 (0~39)
3157 12:31:52.050234
3158 12:31:52.056616 ----->DramcWriteLeveling(PI) begin...
3159 12:31:52.056757 ==
3160 12:31:52.060138 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 12:31:52.063105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 12:31:52.063212 ==
3163 12:31:52.066550 Write leveling (Byte 0): 26 => 26
3164 12:31:52.069920 Write leveling (Byte 1): 27 => 27
3165 12:31:52.073494 DramcWriteLeveling(PI) end<-----
3166 12:31:52.073621
3167 12:31:52.073741 ==
3168 12:31:52.076481 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 12:31:52.079805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 12:31:52.079906 ==
3171 12:31:52.083179 [Gating] SW mode calibration
3172 12:31:52.089905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 12:31:52.096200 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 12:31:52.099658 0 15 0 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
3175 12:31:52.103153 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 12:31:52.109885 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 12:31:52.112733 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 12:31:52.116514 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 12:31:52.122784 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 12:31:52.126266 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3181 12:31:52.129619 0 15 28 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (1 0)
3182 12:31:52.135986 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 12:31:52.139562 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 12:31:52.142481 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 12:31:52.149464 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 12:31:52.152537 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 12:31:52.156089 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 12:31:52.162506 1 0 24 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
3189 12:31:52.166061 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3190 12:31:52.168899 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3191 12:31:52.175932 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 12:31:52.179380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 12:31:52.182303 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 12:31:52.185670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 12:31:52.192573 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 12:31:52.195901 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3197 12:31:52.198776 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3198 12:31:52.205838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:31:52.209220 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 12:31:52.211892 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:31:52.218742 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:31:52.221867 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:31:52.225805 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:31:52.232285 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:31:52.235640 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:31:52.238467 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:31:52.245487 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:31:52.248531 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:31:52.252149 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:31:52.258523 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:31:52.262008 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:31:52.264896 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3213 12:31:52.271868 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3214 12:31:52.272042 Total UI for P1: 0, mck2ui 16
3215 12:31:52.278323 best dqsien dly found for B0: ( 1, 3, 24)
3216 12:31:52.281836 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 12:31:52.285274 Total UI for P1: 0, mck2ui 16
3218 12:31:52.288678 best dqsien dly found for B1: ( 1, 3, 26)
3219 12:31:52.291570 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3220 12:31:52.294913 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3221 12:31:52.295048
3222 12:31:52.298122 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3223 12:31:52.301423 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3224 12:31:52.304837 [Gating] SW calibration Done
3225 12:31:52.304941 ==
3226 12:31:52.308311 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 12:31:52.314991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 12:31:52.315128 ==
3229 12:31:52.315240 RX Vref Scan: 0
3230 12:31:52.315304
3231 12:31:52.318211 RX Vref 0 -> 0, step: 1
3232 12:31:52.318302
3233 12:31:52.321125 RX Delay -40 -> 252, step: 8
3234 12:31:52.324879 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3235 12:31:52.328483 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3236 12:31:52.331048 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3237 12:31:52.334676 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3238 12:31:52.340992 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3239 12:31:52.344580 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3240 12:31:52.347553 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3241 12:31:52.351123 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3242 12:31:52.354591 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3243 12:31:52.361060 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3244 12:31:52.364478 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3245 12:31:52.367382 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3246 12:31:52.370773 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3247 12:31:52.377597 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3248 12:31:52.380726 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3249 12:31:52.384216 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3250 12:31:52.384319 ==
3251 12:31:52.387710 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 12:31:52.391312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 12:31:52.391411 ==
3254 12:31:52.394214 DQS Delay:
3255 12:31:52.394308 DQS0 = 0, DQS1 = 0
3256 12:31:52.394375 DQM Delay:
3257 12:31:52.397678 DQM0 = 118, DQM1 = 114
3258 12:31:52.397772 DQ Delay:
3259 12:31:52.400863 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3260 12:31:52.404653 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3261 12:31:52.410965 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3262 12:31:52.413940 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3263 12:31:52.414054
3264 12:31:52.414121
3265 12:31:52.414180 ==
3266 12:31:52.417471 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 12:31:52.420759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 12:31:52.420861 ==
3269 12:31:52.420929
3270 12:31:52.420991
3271 12:31:52.423953 TX Vref Scan disable
3272 12:31:52.427350 == TX Byte 0 ==
3273 12:31:52.430604 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3274 12:31:52.433962 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3275 12:31:52.437553 == TX Byte 1 ==
3276 12:31:52.440933 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3277 12:31:52.444436 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3278 12:31:52.444564 ==
3279 12:31:52.447271 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 12:31:52.450812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 12:31:52.453799 ==
3282 12:31:52.463957 TX Vref=22, minBit 9, minWin=23, winSum=411
3283 12:31:52.466983 TX Vref=24, minBit 8, minWin=24, winSum=410
3284 12:31:52.470668 TX Vref=26, minBit 9, minWin=25, winSum=423
3285 12:31:52.473945 TX Vref=28, minBit 9, minWin=25, winSum=426
3286 12:31:52.476841 TX Vref=30, minBit 9, minWin=25, winSum=423
3287 12:31:52.480704 TX Vref=32, minBit 8, minWin=25, winSum=424
3288 12:31:52.487159 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 28
3289 12:31:52.487243
3290 12:31:52.490759 Final TX Range 1 Vref 28
3291 12:31:52.490850
3292 12:31:52.490916 ==
3293 12:31:52.493715 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 12:31:52.497188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 12:31:52.497275 ==
3296 12:31:52.497341
3297 12:31:52.500156
3298 12:31:52.500238 TX Vref Scan disable
3299 12:31:52.503585 == TX Byte 0 ==
3300 12:31:52.506922 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3301 12:31:52.510292 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3302 12:31:52.513865 == TX Byte 1 ==
3303 12:31:52.517326 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3304 12:31:52.520235 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3305 12:31:52.520319
3306 12:31:52.523704 [DATLAT]
3307 12:31:52.523786 Freq=1200, CH1 RK0
3308 12:31:52.523851
3309 12:31:52.527055 DATLAT Default: 0xd
3310 12:31:52.527137 0, 0xFFFF, sum = 0
3311 12:31:52.530523 1, 0xFFFF, sum = 0
3312 12:31:52.530608 2, 0xFFFF, sum = 0
3313 12:31:52.533695 3, 0xFFFF, sum = 0
3314 12:31:52.533778 4, 0xFFFF, sum = 0
3315 12:31:52.536890 5, 0xFFFF, sum = 0
3316 12:31:52.536976 6, 0xFFFF, sum = 0
3317 12:31:52.540347 7, 0xFFFF, sum = 0
3318 12:31:52.543284 8, 0xFFFF, sum = 0
3319 12:31:52.543367 9, 0xFFFF, sum = 0
3320 12:31:52.546781 10, 0xFFFF, sum = 0
3321 12:31:52.546863 11, 0xFFFF, sum = 0
3322 12:31:52.550074 12, 0x0, sum = 1
3323 12:31:52.550157 13, 0x0, sum = 2
3324 12:31:52.553741 14, 0x0, sum = 3
3325 12:31:52.553824 15, 0x0, sum = 4
3326 12:31:52.553891 best_step = 13
3327 12:31:52.556607
3328 12:31:52.556700 ==
3329 12:31:52.560140 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 12:31:52.563191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 12:31:52.563274 ==
3332 12:31:52.563339 RX Vref Scan: 1
3333 12:31:52.563400
3334 12:31:52.566684 Set Vref Range= 32 -> 127
3335 12:31:52.566767
3336 12:31:52.570145 RX Vref 32 -> 127, step: 1
3337 12:31:52.570227
3338 12:31:52.573586 RX Delay -13 -> 252, step: 4
3339 12:31:52.573668
3340 12:31:52.576479 Set Vref, RX VrefLevel [Byte0]: 32
3341 12:31:52.579710 [Byte1]: 32
3342 12:31:52.579792
3343 12:31:52.583195 Set Vref, RX VrefLevel [Byte0]: 33
3344 12:31:52.586644 [Byte1]: 33
3345 12:31:52.590078
3346 12:31:52.590160 Set Vref, RX VrefLevel [Byte0]: 34
3347 12:31:52.593042 [Byte1]: 34
3348 12:31:52.597838
3349 12:31:52.597921 Set Vref, RX VrefLevel [Byte0]: 35
3350 12:31:52.601347 [Byte1]: 35
3351 12:31:52.605746
3352 12:31:52.605833 Set Vref, RX VrefLevel [Byte0]: 36
3353 12:31:52.609180 [Byte1]: 36
3354 12:31:52.613587
3355 12:31:52.613670 Set Vref, RX VrefLevel [Byte0]: 37
3356 12:31:52.616648 [Byte1]: 37
3357 12:31:52.621181
3358 12:31:52.621266 Set Vref, RX VrefLevel [Byte0]: 38
3359 12:31:52.624425 [Byte1]: 38
3360 12:31:52.629025
3361 12:31:52.629139 Set Vref, RX VrefLevel [Byte0]: 39
3362 12:31:52.632371 [Byte1]: 39
3363 12:31:52.637547
3364 12:31:52.637668 Set Vref, RX VrefLevel [Byte0]: 40
3365 12:31:52.640194 [Byte1]: 40
3366 12:31:52.644836
3367 12:31:52.644924 Set Vref, RX VrefLevel [Byte0]: 41
3368 12:31:52.648438 [Byte1]: 41
3369 12:31:52.653024
3370 12:31:52.653116 Set Vref, RX VrefLevel [Byte0]: 42
3371 12:31:52.655964 [Byte1]: 42
3372 12:31:52.660952
3373 12:31:52.661277 Set Vref, RX VrefLevel [Byte0]: 43
3374 12:31:52.664551 [Byte1]: 43
3375 12:31:52.668852
3376 12:31:52.669180 Set Vref, RX VrefLevel [Byte0]: 44
3377 12:31:52.672333 [Byte1]: 44
3378 12:31:52.676535
3379 12:31:52.676948 Set Vref, RX VrefLevel [Byte0]: 45
3380 12:31:52.680094 [Byte1]: 45
3381 12:31:52.684811
3382 12:31:52.685151 Set Vref, RX VrefLevel [Byte0]: 46
3383 12:31:52.688181 [Byte1]: 46
3384 12:31:52.692465
3385 12:31:52.692784 Set Vref, RX VrefLevel [Byte0]: 47
3386 12:31:52.695978 [Byte1]: 47
3387 12:31:52.700135
3388 12:31:52.700444 Set Vref, RX VrefLevel [Byte0]: 48
3389 12:31:52.703847 [Byte1]: 48
3390 12:31:52.708484
3391 12:31:52.708814 Set Vref, RX VrefLevel [Byte0]: 49
3392 12:31:52.711437 [Byte1]: 49
3393 12:31:52.715981
3394 12:31:52.716333 Set Vref, RX VrefLevel [Byte0]: 50
3395 12:31:52.719493 [Byte1]: 50
3396 12:31:52.724256
3397 12:31:52.724576 Set Vref, RX VrefLevel [Byte0]: 51
3398 12:31:52.727351 [Byte1]: 51
3399 12:31:52.731879
3400 12:31:52.732277 Set Vref, RX VrefLevel [Byte0]: 52
3401 12:31:52.735346 [Byte1]: 52
3402 12:31:52.739930
3403 12:31:52.740321 Set Vref, RX VrefLevel [Byte0]: 53
3404 12:31:52.742915 [Byte1]: 53
3405 12:31:52.747510
3406 12:31:52.747869 Set Vref, RX VrefLevel [Byte0]: 54
3407 12:31:52.750978 [Byte1]: 54
3408 12:31:52.755647
3409 12:31:52.755999 Set Vref, RX VrefLevel [Byte0]: 55
3410 12:31:52.758580 [Byte1]: 55
3411 12:31:52.763481
3412 12:31:52.763971 Set Vref, RX VrefLevel [Byte0]: 56
3413 12:31:52.767086 [Byte1]: 56
3414 12:31:52.771274
3415 12:31:52.774268 Set Vref, RX VrefLevel [Byte0]: 57
3416 12:31:52.777963 [Byte1]: 57
3417 12:31:52.778417
3418 12:31:52.780841 Set Vref, RX VrefLevel [Byte0]: 58
3419 12:31:52.784367 [Byte1]: 58
3420 12:31:52.784755
3421 12:31:52.787919 Set Vref, RX VrefLevel [Byte0]: 59
3422 12:31:52.790991 [Byte1]: 59
3423 12:31:52.795030
3424 12:31:52.795515 Set Vref, RX VrefLevel [Byte0]: 60
3425 12:31:52.798519 [Byte1]: 60
3426 12:31:52.803228
3427 12:31:52.803586 Set Vref, RX VrefLevel [Byte0]: 61
3428 12:31:52.806221 [Byte1]: 61
3429 12:31:52.811350
3430 12:31:52.811809 Set Vref, RX VrefLevel [Byte0]: 62
3431 12:31:52.813827 [Byte1]: 62
3432 12:31:52.818482
3433 12:31:52.818872 Set Vref, RX VrefLevel [Byte0]: 63
3434 12:31:52.821753 [Byte1]: 63
3435 12:31:52.826560
3436 12:31:52.826922 Set Vref, RX VrefLevel [Byte0]: 64
3437 12:31:52.830113 [Byte1]: 64
3438 12:31:52.834820
3439 12:31:52.835196 Set Vref, RX VrefLevel [Byte0]: 65
3440 12:31:52.837736 [Byte1]: 65
3441 12:31:52.842331
3442 12:31:52.842713 Set Vref, RX VrefLevel [Byte0]: 66
3443 12:31:52.845536 [Byte1]: 66
3444 12:31:52.850223
3445 12:31:52.850629 Set Vref, RX VrefLevel [Byte0]: 67
3446 12:31:52.853525 [Byte1]: 67
3447 12:31:52.858436
3448 12:31:52.858975 Set Vref, RX VrefLevel [Byte0]: 68
3449 12:31:52.861605 [Byte1]: 68
3450 12:31:52.865882
3451 12:31:52.866276 Set Vref, RX VrefLevel [Byte0]: 69
3452 12:31:52.869449 [Byte1]: 69
3453 12:31:52.873682
3454 12:31:52.874119 Set Vref, RX VrefLevel [Byte0]: 70
3455 12:31:52.877288 [Byte1]: 70
3456 12:31:52.882199
3457 12:31:52.882660 Final RX Vref Byte 0 = 53 to rank0
3458 12:31:52.885122 Final RX Vref Byte 1 = 53 to rank0
3459 12:31:52.888111 Final RX Vref Byte 0 = 53 to rank1
3460 12:31:52.891554 Final RX Vref Byte 1 = 53 to rank1==
3461 12:31:52.894997 Dram Type= 6, Freq= 0, CH_1, rank 0
3462 12:31:52.901487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 12:31:52.901860 ==
3464 12:31:52.902157 DQS Delay:
3465 12:31:52.904538 DQS0 = 0, DQS1 = 0
3466 12:31:52.904935 DQM Delay:
3467 12:31:52.905236 DQM0 = 116, DQM1 = 115
3468 12:31:52.907961 DQ Delay:
3469 12:31:52.911480 DQ0 =124, DQ1 =112, DQ2 =108, DQ3 =116
3470 12:31:52.914552 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3471 12:31:52.918199 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =110
3472 12:31:52.921673 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3473 12:31:52.922040
3474 12:31:52.922335
3475 12:31:52.931207 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3476 12:31:52.931665 CH1 RK0: MR19=304, MR18=F501
3477 12:31:52.937895 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3478 12:31:52.938290
3479 12:31:52.941061 ----->DramcWriteLeveling(PI) begin...
3480 12:31:52.941454 ==
3481 12:31:52.944658 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 12:31:52.951290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 12:31:52.951677 ==
3484 12:31:52.954482 Write leveling (Byte 0): 24 => 24
3485 12:31:52.957898 Write leveling (Byte 1): 27 => 27
3486 12:31:52.958268 DramcWriteLeveling(PI) end<-----
3487 12:31:52.958560
3488 12:31:52.960936 ==
3489 12:31:52.964315 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 12:31:52.967791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 12:31:52.968184 ==
3492 12:31:52.971240 [Gating] SW mode calibration
3493 12:31:52.977921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3494 12:31:52.980973 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3495 12:31:52.988003 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3496 12:31:52.991047 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 12:31:52.994359 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 12:31:53.000916 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 12:31:53.004439 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 12:31:53.007487 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3501 12:31:53.014452 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
3502 12:31:53.017831 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3503 12:31:53.020640 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 12:31:53.027353 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 12:31:53.030837 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 12:31:53.034313 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 12:31:53.040580 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 12:31:53.043500 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3509 12:31:53.047203 1 0 24 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
3510 12:31:53.053676 1 0 28 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
3511 12:31:53.057229 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 12:31:53.060116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 12:31:53.067216 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 12:31:53.070072 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 12:31:53.073635 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 12:31:53.080120 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3517 12:31:53.083067 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3518 12:31:53.086643 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3519 12:31:53.093327 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:31:53.096204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 12:31:53.099789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 12:31:53.106153 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:31:53.109299 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:31:53.112760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:31:53.119267 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:31:53.122885 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:31:53.126822 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:31:53.132691 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:31:53.136220 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:31:53.139720 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:31:53.145890 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:31:53.149132 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3533 12:31:53.152515 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3534 12:31:53.158775 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3535 12:31:53.159168 Total UI for P1: 0, mck2ui 16
3536 12:31:53.165941 best dqsien dly found for B0: ( 1, 3, 22)
3537 12:31:53.168673 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3538 12:31:53.172365 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 12:31:53.175894 Total UI for P1: 0, mck2ui 16
3540 12:31:53.178825 best dqsien dly found for B1: ( 1, 3, 30)
3541 12:31:53.181889 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3542 12:31:53.185418 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3543 12:31:53.185805
3544 12:31:53.192249 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3545 12:31:53.195303 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3546 12:31:53.198842 [Gating] SW calibration Done
3547 12:31:53.199233 ==
3548 12:31:53.201820 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 12:31:53.205600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 12:31:53.206089 ==
3551 12:31:53.206413 RX Vref Scan: 0
3552 12:31:53.206743
3553 12:31:53.208307 RX Vref 0 -> 0, step: 1
3554 12:31:53.208704
3555 12:31:53.211883 RX Delay -40 -> 252, step: 8
3556 12:31:53.214850 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3557 12:31:53.218666 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3558 12:31:53.225016 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3559 12:31:53.227997 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3560 12:31:53.231498 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3561 12:31:53.235246 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3562 12:31:53.237956 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3563 12:31:53.244875 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3564 12:31:53.247805 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3565 12:31:53.251221 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3566 12:31:53.254890 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3567 12:31:53.261122 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3568 12:31:53.264822 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3569 12:31:53.267925 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3570 12:31:53.271259 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3571 12:31:53.274217 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3572 12:31:53.279244 ==
3573 12:31:53.280599 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 12:31:53.284204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 12:31:53.284610 ==
3576 12:31:53.285017 DQS Delay:
3577 12:31:53.287229 DQS0 = 0, DQS1 = 0
3578 12:31:53.287630 DQM Delay:
3579 12:31:53.290800 DQM0 = 118, DQM1 = 115
3580 12:31:53.291202 DQ Delay:
3581 12:31:53.293847 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3582 12:31:53.297398 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =119
3583 12:31:53.300445 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3584 12:31:53.303835 DQ12 =127, DQ13 =123, DQ14 =119, DQ15 =123
3585 12:31:53.304147
3586 12:31:53.304376
3587 12:31:53.307205 ==
3588 12:31:53.310359 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 12:31:53.313808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 12:31:53.313986 ==
3591 12:31:53.314129
3592 12:31:53.314261
3593 12:31:53.316667 TX Vref Scan disable
3594 12:31:53.316817 == TX Byte 0 ==
3595 12:31:53.320253 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3596 12:31:53.327009 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3597 12:31:53.327374 == TX Byte 1 ==
3598 12:31:53.333517 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3599 12:31:53.336545 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3600 12:31:53.336967 ==
3601 12:31:53.340068 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 12:31:53.343368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 12:31:53.343766 ==
3604 12:31:53.355654 TX Vref=22, minBit 3, minWin=25, winSum=417
3605 12:31:53.359168 TX Vref=24, minBit 9, minWin=25, winSum=422
3606 12:31:53.362197 TX Vref=26, minBit 9, minWin=25, winSum=426
3607 12:31:53.365653 TX Vref=28, minBit 1, minWin=26, winSum=431
3608 12:31:53.369154 TX Vref=30, minBit 8, minWin=25, winSum=431
3609 12:31:53.375486 TX Vref=32, minBit 8, minWin=25, winSum=431
3610 12:31:53.379265 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3611 12:31:53.379731
3612 12:31:53.382020 Final TX Range 1 Vref 28
3613 12:31:53.382407
3614 12:31:53.382717 ==
3615 12:31:53.385509 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 12:31:53.388534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 12:31:53.392467 ==
3618 12:31:53.392995
3619 12:31:53.393357
3620 12:31:53.393687 TX Vref Scan disable
3621 12:31:53.395125 == TX Byte 0 ==
3622 12:31:53.398771 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3623 12:31:53.405191 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3624 12:31:53.405688 == TX Byte 1 ==
3625 12:31:53.408929 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3626 12:31:53.415665 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3627 12:31:53.416200
3628 12:31:53.416520 [DATLAT]
3629 12:31:53.416808 Freq=1200, CH1 RK1
3630 12:31:53.417086
3631 12:31:53.418404 DATLAT Default: 0xd
3632 12:31:53.421835 0, 0xFFFF, sum = 0
3633 12:31:53.422392 1, 0xFFFF, sum = 0
3634 12:31:53.425398 2, 0xFFFF, sum = 0
3635 12:31:53.425893 3, 0xFFFF, sum = 0
3636 12:31:53.428317 4, 0xFFFF, sum = 0
3637 12:31:53.428706 5, 0xFFFF, sum = 0
3638 12:31:53.431477 6, 0xFFFF, sum = 0
3639 12:31:53.431972 7, 0xFFFF, sum = 0
3640 12:31:53.434975 8, 0xFFFF, sum = 0
3641 12:31:53.435510 9, 0xFFFF, sum = 0
3642 12:31:53.437829 10, 0xFFFF, sum = 0
3643 12:31:53.438225 11, 0xFFFF, sum = 0
3644 12:31:53.441285 12, 0x0, sum = 1
3645 12:31:53.441677 13, 0x0, sum = 2
3646 12:31:53.444777 14, 0x0, sum = 3
3647 12:31:53.445209 15, 0x0, sum = 4
3648 12:31:53.448079 best_step = 13
3649 12:31:53.448514
3650 12:31:53.448854 ==
3651 12:31:53.450971 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 12:31:53.454196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 12:31:53.454593 ==
3654 12:31:53.457693 RX Vref Scan: 0
3655 12:31:53.458184
3656 12:31:53.458519 RX Vref 0 -> 0, step: 1
3657 12:31:53.458888
3658 12:31:53.460506 RX Delay -13 -> 252, step: 4
3659 12:31:53.467707 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3660 12:31:53.470534 iDelay=191, Bit 1, Center 116 (51 ~ 182) 132
3661 12:31:53.473985 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3662 12:31:53.477016 iDelay=191, Bit 3, Center 114 (51 ~ 178) 128
3663 12:31:53.483876 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3664 12:31:53.487405 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3665 12:31:53.490325 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3666 12:31:53.494077 iDelay=191, Bit 7, Center 116 (51 ~ 182) 132
3667 12:31:53.497187 iDelay=191, Bit 8, Center 102 (43 ~ 162) 120
3668 12:31:53.503472 iDelay=191, Bit 9, Center 104 (43 ~ 166) 124
3669 12:31:53.507060 iDelay=191, Bit 10, Center 116 (55 ~ 178) 124
3670 12:31:53.509959 iDelay=191, Bit 11, Center 110 (51 ~ 170) 120
3671 12:31:53.513504 iDelay=191, Bit 12, Center 122 (63 ~ 182) 120
3672 12:31:53.516590 iDelay=191, Bit 13, Center 122 (63 ~ 182) 120
3673 12:31:53.523153 iDelay=191, Bit 14, Center 122 (63 ~ 182) 120
3674 12:31:53.526640 iDelay=191, Bit 15, Center 124 (63 ~ 186) 124
3675 12:31:53.526981 ==
3676 12:31:53.530150 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 12:31:53.533100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 12:31:53.533434 ==
3679 12:31:53.536650 DQS Delay:
3680 12:31:53.537035 DQS0 = 0, DQS1 = 0
3681 12:31:53.540214 DQM Delay:
3682 12:31:53.540600 DQM0 = 117, DQM1 = 115
3683 12:31:53.540927 DQ Delay:
3684 12:31:53.543137 DQ0 =118, DQ1 =116, DQ2 =108, DQ3 =114
3685 12:31:53.550207 DQ4 =116, DQ5 =124, DQ6 =124, DQ7 =116
3686 12:31:53.552901 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =110
3687 12:31:53.556563 DQ12 =122, DQ13 =122, DQ14 =122, DQ15 =124
3688 12:31:53.556952
3689 12:31:53.557260
3690 12:31:53.562742 [DQSOSCAuto] RK1, (LSB)MR18= 0xf506, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3691 12:31:53.565829 CH1 RK1: MR19=304, MR18=F506
3692 12:31:53.572784 CH1_RK1: MR19=0x304, MR18=0xF506, DQSOSC=407, MR23=63, INC=39, DEC=26
3693 12:31:53.575848 [RxdqsGatingPostProcess] freq 1200
3694 12:31:53.582333 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3695 12:31:53.585606 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 12:31:53.589204 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 12:31:53.592600 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 12:31:53.593002 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 12:31:53.595566 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 12:31:53.599297 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 12:31:53.602643 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 12:31:53.605412 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 12:31:53.609022 Pre-setting of DQS Precalculation
3704 12:31:53.615871 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3705 12:31:53.622338 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3706 12:31:53.628657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3707 12:31:53.629105
3708 12:31:53.629548
3709 12:31:53.632222 [Calibration Summary] 2400 Mbps
3710 12:31:53.632662 CH 0, Rank 0
3711 12:31:53.635095 SW Impedance : PASS
3712 12:31:53.638942 DUTY Scan : NO K
3713 12:31:53.639462 ZQ Calibration : PASS
3714 12:31:53.641618 Jitter Meter : NO K
3715 12:31:53.645093 CBT Training : PASS
3716 12:31:53.645492 Write leveling : PASS
3717 12:31:53.648206 RX DQS gating : PASS
3718 12:31:53.651854 RX DQ/DQS(RDDQC) : PASS
3719 12:31:53.652406 TX DQ/DQS : PASS
3720 12:31:53.654958 RX DATLAT : PASS
3721 12:31:53.657930 RX DQ/DQS(Engine): PASS
3722 12:31:53.658428 TX OE : NO K
3723 12:31:53.661388 All Pass.
3724 12:31:53.661779
3725 12:31:53.662091 CH 0, Rank 1
3726 12:31:53.664850 SW Impedance : PASS
3727 12:31:53.665241 DUTY Scan : NO K
3728 12:31:53.668233 ZQ Calibration : PASS
3729 12:31:53.671421 Jitter Meter : NO K
3730 12:31:53.671828 CBT Training : PASS
3731 12:31:53.674433 Write leveling : PASS
3732 12:31:53.678029 RX DQS gating : PASS
3733 12:31:53.678418 RX DQ/DQS(RDDQC) : PASS
3734 12:31:53.680991 TX DQ/DQS : PASS
3735 12:31:53.684514 RX DATLAT : PASS
3736 12:31:53.684902 RX DQ/DQS(Engine): PASS
3737 12:31:53.687957 TX OE : NO K
3738 12:31:53.688389 All Pass.
3739 12:31:53.688706
3740 12:31:53.690836 CH 1, Rank 0
3741 12:31:53.691226 SW Impedance : PASS
3742 12:31:53.694433 DUTY Scan : NO K
3743 12:31:53.697685 ZQ Calibration : PASS
3744 12:31:53.698075 Jitter Meter : NO K
3745 12:31:53.700782 CBT Training : PASS
3746 12:31:53.704295 Write leveling : PASS
3747 12:31:53.704687 RX DQS gating : PASS
3748 12:31:53.707753 RX DQ/DQS(RDDQC) : PASS
3749 12:31:53.710806 TX DQ/DQS : PASS
3750 12:31:53.711197 RX DATLAT : PASS
3751 12:31:53.714129 RX DQ/DQS(Engine): PASS
3752 12:31:53.714490 TX OE : NO K
3753 12:31:53.717273 All Pass.
3754 12:31:53.717632
3755 12:31:53.717923 CH 1, Rank 1
3756 12:31:53.720910 SW Impedance : PASS
3757 12:31:53.723700 DUTY Scan : NO K
3758 12:31:53.724085 ZQ Calibration : PASS
3759 12:31:53.727604 Jitter Meter : NO K
3760 12:31:53.728104 CBT Training : PASS
3761 12:31:53.730386 Write leveling : PASS
3762 12:31:53.733962 RX DQS gating : PASS
3763 12:31:53.734429 RX DQ/DQS(RDDQC) : PASS
3764 12:31:53.737185 TX DQ/DQS : PASS
3765 12:31:53.740551 RX DATLAT : PASS
3766 12:31:53.741012 RX DQ/DQS(Engine): PASS
3767 12:31:53.743336 TX OE : NO K
3768 12:31:53.743694 All Pass.
3769 12:31:53.743980
3770 12:31:53.746902 DramC Write-DBI off
3771 12:31:53.750123 PER_BANK_REFRESH: Hybrid Mode
3772 12:31:53.750660 TX_TRACKING: ON
3773 12:31:53.760333 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3774 12:31:53.763674 [FAST_K] Save calibration result to emmc
3775 12:31:53.766924 dramc_set_vcore_voltage set vcore to 650000
3776 12:31:53.769790 Read voltage for 600, 5
3777 12:31:53.770214 Vio18 = 0
3778 12:31:53.773139 Vcore = 650000
3779 12:31:53.773562 Vdram = 0
3780 12:31:53.773901 Vddq = 0
3781 12:31:53.774214 Vmddr = 0
3782 12:31:53.779990 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3783 12:31:53.786409 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3784 12:31:53.786834 MEM_TYPE=3, freq_sel=19
3785 12:31:53.789523 sv_algorithm_assistance_LP4_1600
3786 12:31:53.792990 ============ PULL DRAM RESETB DOWN ============
3787 12:31:53.799271 ========== PULL DRAM RESETB DOWN end =========
3788 12:31:53.802707 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3789 12:31:53.806322 ===================================
3790 12:31:53.809326 LPDDR4 DRAM CONFIGURATION
3791 12:31:53.812996 ===================================
3792 12:31:53.813384 EX_ROW_EN[0] = 0x0
3793 12:31:53.815961 EX_ROW_EN[1] = 0x0
3794 12:31:53.819021 LP4Y_EN = 0x0
3795 12:31:53.819408 WORK_FSP = 0x0
3796 12:31:53.822594 WL = 0x2
3797 12:31:53.822976 RL = 0x2
3798 12:31:53.825740 BL = 0x2
3799 12:31:53.826128 RPST = 0x0
3800 12:31:53.829352 RD_PRE = 0x0
3801 12:31:53.829748 WR_PRE = 0x1
3802 12:31:53.832339 WR_PST = 0x0
3803 12:31:53.832724 DBI_WR = 0x0
3804 12:31:53.836115 DBI_RD = 0x0
3805 12:31:53.836609 OTF = 0x1
3806 12:31:53.839507 ===================================
3807 12:31:53.842084 ===================================
3808 12:31:53.845315 ANA top config
3809 12:31:53.848991 ===================================
3810 12:31:53.849463 DLL_ASYNC_EN = 0
3811 12:31:53.852123 ALL_SLAVE_EN = 1
3812 12:31:53.855538 NEW_RANK_MODE = 1
3813 12:31:53.858874 DLL_IDLE_MODE = 1
3814 12:31:53.862386 LP45_APHY_COMB_EN = 1
3815 12:31:53.862911 TX_ODT_DIS = 1
3816 12:31:53.865226 NEW_8X_MODE = 1
3817 12:31:53.868727 ===================================
3818 12:31:53.871945 ===================================
3819 12:31:53.875093 data_rate = 1200
3820 12:31:53.878181 CKR = 1
3821 12:31:53.881962 DQ_P2S_RATIO = 8
3822 12:31:53.885039 ===================================
3823 12:31:53.888013 CA_P2S_RATIO = 8
3824 12:31:53.891503 DQ_CA_OPEN = 0
3825 12:31:53.891929 DQ_SEMI_OPEN = 0
3826 12:31:53.894408 CA_SEMI_OPEN = 0
3827 12:31:53.897986 CA_FULL_RATE = 0
3828 12:31:53.900878 DQ_CKDIV4_EN = 1
3829 12:31:53.904317 CA_CKDIV4_EN = 1
3830 12:31:53.907863 CA_PREDIV_EN = 0
3831 12:31:53.908284 PH8_DLY = 0
3832 12:31:53.910895 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3833 12:31:53.914385 DQ_AAMCK_DIV = 4
3834 12:31:53.918005 CA_AAMCK_DIV = 4
3835 12:31:53.921355 CA_ADMCK_DIV = 4
3836 12:31:53.924683 DQ_TRACK_CA_EN = 0
3837 12:31:53.925075 CA_PICK = 600
3838 12:31:53.927645 CA_MCKIO = 600
3839 12:31:53.930957 MCKIO_SEMI = 0
3840 12:31:53.934535 PLL_FREQ = 2288
3841 12:31:53.937584 DQ_UI_PI_RATIO = 32
3842 12:31:53.941037 CA_UI_PI_RATIO = 0
3843 12:31:53.943997 ===================================
3844 12:31:53.947692 ===================================
3845 12:31:53.951191 memory_type:LPDDR4
3846 12:31:53.951729 GP_NUM : 10
3847 12:31:53.953853 SRAM_EN : 1
3848 12:31:53.954279 MD32_EN : 0
3849 12:31:53.957725 ===================================
3850 12:31:53.960508 [ANA_INIT] >>>>>>>>>>>>>>
3851 12:31:53.963994 <<<<<< [CONFIGURE PHASE]: ANA_TX
3852 12:31:53.967259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3853 12:31:53.970618 ===================================
3854 12:31:53.974062 data_rate = 1200,PCW = 0X5800
3855 12:31:53.977162 ===================================
3856 12:31:53.980102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3857 12:31:53.986857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 12:31:53.990437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 12:31:53.997132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3860 12:31:54.000362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3861 12:31:54.003391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3862 12:31:54.003820 [ANA_INIT] flow start
3863 12:31:54.006562 [ANA_INIT] PLL >>>>>>>>
3864 12:31:54.010519 [ANA_INIT] PLL <<<<<<<<
3865 12:31:54.011058 [ANA_INIT] MIDPI >>>>>>>>
3866 12:31:54.013285 [ANA_INIT] MIDPI <<<<<<<<
3867 12:31:54.016899 [ANA_INIT] DLL >>>>>>>>
3868 12:31:54.017424 [ANA_INIT] flow end
3869 12:31:54.023563 ============ LP4 DIFF to SE enter ============
3870 12:31:54.026740 ============ LP4 DIFF to SE exit ============
3871 12:31:54.029877 [ANA_INIT] <<<<<<<<<<<<<
3872 12:31:54.032550 [Flow] Enable top DCM control >>>>>
3873 12:31:54.036098 [Flow] Enable top DCM control <<<<<
3874 12:31:54.039604 Enable DLL master slave shuffle
3875 12:31:54.042641 ==============================================================
3876 12:31:54.046465 Gating Mode config
3877 12:31:54.052629 ==============================================================
3878 12:31:54.053080 Config description:
3879 12:31:54.062694 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3880 12:31:54.069011 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3881 12:31:54.072551 SELPH_MODE 0: By rank 1: By Phase
3882 12:31:54.079399 ==============================================================
3883 12:31:54.082229 GAT_TRACK_EN = 1
3884 12:31:54.085550 RX_GATING_MODE = 2
3885 12:31:54.088767 RX_GATING_TRACK_MODE = 2
3886 12:31:54.092114 SELPH_MODE = 1
3887 12:31:54.095098 PICG_EARLY_EN = 1
3888 12:31:54.098694 VALID_LAT_VALUE = 1
3889 12:31:54.101853 ==============================================================
3890 12:31:54.105318 Enter into Gating configuration >>>>
3891 12:31:54.108796 Exit from Gating configuration <<<<
3892 12:31:54.111713 Enter into DVFS_PRE_config >>>>>
3893 12:31:54.125551 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3894 12:31:54.128135 Exit from DVFS_PRE_config <<<<<
3895 12:31:54.131632 Enter into PICG configuration >>>>
3896 12:31:54.132259 Exit from PICG configuration <<<<
3897 12:31:54.134790 [RX_INPUT] configuration >>>>>
3898 12:31:54.138300 [RX_INPUT] configuration <<<<<
3899 12:31:54.144558 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3900 12:31:54.148133 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3901 12:31:54.154504 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 12:31:54.161038 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 12:31:54.167187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 12:31:54.174615 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 12:31:54.177507 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3906 12:31:54.180769 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3907 12:31:54.187352 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3908 12:31:54.190756 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3909 12:31:54.193514 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3910 12:31:54.200268 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 12:31:54.203517 ===================================
3912 12:31:54.203683 LPDDR4 DRAM CONFIGURATION
3913 12:31:54.206595 ===================================
3914 12:31:54.209572 EX_ROW_EN[0] = 0x0
3915 12:31:54.213031 EX_ROW_EN[1] = 0x0
3916 12:31:54.213120 LP4Y_EN = 0x0
3917 12:31:54.216890 WORK_FSP = 0x0
3918 12:31:54.217290 WL = 0x2
3919 12:31:54.220477 RL = 0x2
3920 12:31:54.220889 BL = 0x2
3921 12:31:54.223424 RPST = 0x0
3922 12:31:54.223820 RD_PRE = 0x0
3923 12:31:54.226772 WR_PRE = 0x1
3924 12:31:54.227167 WR_PST = 0x0
3925 12:31:54.229947 DBI_WR = 0x0
3926 12:31:54.230358 DBI_RD = 0x0
3927 12:31:54.233500 OTF = 0x1
3928 12:31:54.236513 ===================================
3929 12:31:54.240023 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3930 12:31:54.242991 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3931 12:31:54.249815 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 12:31:54.253170 ===================================
3933 12:31:54.253569 LPDDR4 DRAM CONFIGURATION
3934 12:31:54.256131 ===================================
3935 12:31:54.259650 EX_ROW_EN[0] = 0x10
3936 12:31:54.263030 EX_ROW_EN[1] = 0x0
3937 12:31:54.263426 LP4Y_EN = 0x0
3938 12:31:54.265975 WORK_FSP = 0x0
3939 12:31:54.266398 WL = 0x2
3940 12:31:54.269266 RL = 0x2
3941 12:31:54.269661 BL = 0x2
3942 12:31:54.272999 RPST = 0x0
3943 12:31:54.273565 RD_PRE = 0x0
3944 12:31:54.275925 WR_PRE = 0x1
3945 12:31:54.276365 WR_PST = 0x0
3946 12:31:54.278935 DBI_WR = 0x0
3947 12:31:54.279323 DBI_RD = 0x0
3948 12:31:54.282697 OTF = 0x1
3949 12:31:54.285798 ===================================
3950 12:31:54.292089 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3951 12:31:54.295439 nWR fixed to 30
3952 12:31:54.298902 [ModeRegInit_LP4] CH0 RK0
3953 12:31:54.299339 [ModeRegInit_LP4] CH0 RK1
3954 12:31:54.302280 [ModeRegInit_LP4] CH1 RK0
3955 12:31:54.305299 [ModeRegInit_LP4] CH1 RK1
3956 12:31:54.305689 match AC timing 17
3957 12:31:54.312206 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3958 12:31:54.315276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 12:31:54.318415 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3960 12:31:54.325398 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3961 12:31:54.328297 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3962 12:31:54.328749 ==
3963 12:31:54.331892 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 12:31:54.334851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 12:31:54.335472 ==
3966 12:31:54.341451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 12:31:54.347928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3968 12:31:54.351695 [CA 0] Center 36 (6~67) winsize 62
3969 12:31:54.354703 [CA 1] Center 36 (5~67) winsize 63
3970 12:31:54.357789 [CA 2] Center 34 (4~65) winsize 62
3971 12:31:54.361312 [CA 3] Center 34 (4~65) winsize 62
3972 12:31:54.364807 [CA 4] Center 33 (3~64) winsize 62
3973 12:31:54.367792 [CA 5] Center 33 (3~64) winsize 62
3974 12:31:54.368202
3975 12:31:54.371348 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3976 12:31:54.371735
3977 12:31:54.374818 [CATrainingPosCal] consider 1 rank data
3978 12:31:54.377795 u2DelayCellTimex100 = 270/100 ps
3979 12:31:54.380720 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3980 12:31:54.384366 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3981 12:31:54.388021 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 12:31:54.393864 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 12:31:54.397415 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 12:31:54.400857 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 12:31:54.401430
3986 12:31:54.404140 CA PerBit enable=1, Macro0, CA PI delay=33
3987 12:31:54.404687
3988 12:31:54.406952 [CBTSetCACLKResult] CA Dly = 33
3989 12:31:54.407548 CS Dly: 4 (0~35)
3990 12:31:54.408098 ==
3991 12:31:54.410457 Dram Type= 6, Freq= 0, CH_0, rank 1
3992 12:31:54.417032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 12:31:54.417449 ==
3994 12:31:54.420520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 12:31:54.426999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3996 12:31:54.430974 [CA 0] Center 36 (6~67) winsize 62
3997 12:31:54.433711 [CA 1] Center 36 (6~67) winsize 62
3998 12:31:54.437354 [CA 2] Center 34 (4~65) winsize 62
3999 12:31:54.439983 [CA 3] Center 34 (4~65) winsize 62
4000 12:31:54.443583 [CA 4] Center 34 (3~65) winsize 63
4001 12:31:54.446652 [CA 5] Center 33 (3~64) winsize 62
4002 12:31:54.446752
4003 12:31:54.450178 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4004 12:31:54.450263
4005 12:31:54.453154 [CATrainingPosCal] consider 2 rank data
4006 12:31:54.456657 u2DelayCellTimex100 = 270/100 ps
4007 12:31:54.462845 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4008 12:31:54.466356 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4009 12:31:54.469405 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4010 12:31:54.472872 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4011 12:31:54.476448 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 12:31:54.479283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 12:31:54.479368
4014 12:31:54.482751 CA PerBit enable=1, Macro0, CA PI delay=33
4015 12:31:54.482835
4016 12:31:54.485736 [CBTSetCACLKResult] CA Dly = 33
4017 12:31:54.489423 CS Dly: 5 (0~37)
4018 12:31:54.489509
4019 12:31:54.492328 ----->DramcWriteLeveling(PI) begin...
4020 12:31:54.492414 ==
4021 12:31:54.495848 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 12:31:54.498909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 12:31:54.498995 ==
4024 12:31:54.502437 Write leveling (Byte 0): 36 => 36
4025 12:31:54.505891 Write leveling (Byte 1): 29 => 29
4026 12:31:54.508634 DramcWriteLeveling(PI) end<-----
4027 12:31:54.508719
4028 12:31:54.508803 ==
4029 12:31:54.511983 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 12:31:54.515650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 12:31:54.515736 ==
4032 12:31:54.518521 [Gating] SW mode calibration
4033 12:31:54.525601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4034 12:31:54.531653 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4035 12:31:54.535127 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 12:31:54.541462 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 12:31:54.544968 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 12:31:54.548621 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4039 12:31:54.555191 0 9 16 | B1->B0 | 2d2d 2727 | 0 0 | (0 1) (0 0)
4040 12:31:54.558107 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 12:31:54.561747 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 12:31:54.568307 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 12:31:54.571436 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 12:31:54.575088 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 12:31:54.581764 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 12:31:54.584587 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4047 12:31:54.588192 0 10 16 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
4048 12:31:54.594444 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 12:31:54.597962 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 12:31:54.601314 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 12:31:54.607956 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 12:31:54.610848 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 12:31:54.614715 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 12:31:54.621184 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4055 12:31:54.624359 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4056 12:31:54.627438 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:31:54.634402 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:31:54.637359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:31:54.640836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:31:54.647373 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:31:54.650805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:31:54.653789 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:31:54.660725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:31:54.663790 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:31:54.666952 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:31:54.673423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:31:54.677202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:31:54.680606 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:31:54.686907 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:31:54.690245 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4071 12:31:54.693374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4072 12:31:54.696342 Total UI for P1: 0, mck2ui 16
4073 12:31:54.699983 best dqsien dly found for B0: ( 0, 13, 12)
4074 12:31:54.706477 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 12:31:54.710125 Total UI for P1: 0, mck2ui 16
4076 12:31:54.713375 best dqsien dly found for B1: ( 0, 13, 18)
4077 12:31:54.716561 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4078 12:31:54.720007 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4079 12:31:54.720614
4080 12:31:54.722881 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4081 12:31:54.726578 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4082 12:31:54.729939 [Gating] SW calibration Done
4083 12:31:54.730460 ==
4084 12:31:54.732666 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 12:31:54.736255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 12:31:54.736855 ==
4087 12:31:54.739740 RX Vref Scan: 0
4088 12:31:54.740289
4089 12:31:54.742690 RX Vref 0 -> 0, step: 1
4090 12:31:54.743162
4091 12:31:54.743512 RX Delay -230 -> 252, step: 16
4092 12:31:54.749609 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4093 12:31:54.753070 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4094 12:31:54.756018 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4095 12:31:54.759449 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4096 12:31:54.766308 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4097 12:31:54.769578 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4098 12:31:54.772603 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4099 12:31:54.776151 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4100 12:31:54.782878 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4101 12:31:54.785886 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4102 12:31:54.789292 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4103 12:31:54.792317 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4104 12:31:54.798590 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4105 12:31:54.802251 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4106 12:31:54.805894 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4107 12:31:54.808760 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4108 12:31:54.809192 ==
4109 12:31:54.811818 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 12:31:54.818995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 12:31:54.819521 ==
4112 12:31:54.819872 DQS Delay:
4113 12:31:54.822214 DQS0 = 0, DQS1 = 0
4114 12:31:54.822658 DQM Delay:
4115 12:31:54.823041 DQM0 = 42, DQM1 = 35
4116 12:31:54.825000 DQ Delay:
4117 12:31:54.828566 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4118 12:31:54.832291 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4119 12:31:54.835254 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4120 12:31:54.839140 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4121 12:31:54.839668
4122 12:31:54.840019
4123 12:31:54.840392 ==
4124 12:31:54.841954 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 12:31:54.844910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 12:31:54.845344 ==
4127 12:31:54.845690
4128 12:31:54.846008
4129 12:31:54.848544 TX Vref Scan disable
4130 12:31:54.851446 == TX Byte 0 ==
4131 12:31:54.854945 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4132 12:31:54.857911 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4133 12:31:54.861485 == TX Byte 1 ==
4134 12:31:54.864505 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4135 12:31:54.868385 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4136 12:31:54.868924 ==
4137 12:31:54.871260 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 12:31:54.877990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 12:31:54.878549 ==
4140 12:31:54.878965
4141 12:31:54.879290
4142 12:31:54.879595 TX Vref Scan disable
4143 12:31:54.882879 == TX Byte 0 ==
4144 12:31:54.885857 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4145 12:31:54.892409 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4146 12:31:54.892890 == TX Byte 1 ==
4147 12:31:54.895908 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4148 12:31:54.902355 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4149 12:31:54.902882
4150 12:31:54.903253 [DATLAT]
4151 12:31:54.903609 Freq=600, CH0 RK0
4152 12:31:54.903925
4153 12:31:54.905257 DATLAT Default: 0x9
4154 12:31:54.905687 0, 0xFFFF, sum = 0
4155 12:31:54.909017 1, 0xFFFF, sum = 0
4156 12:31:54.911986 2, 0xFFFF, sum = 0
4157 12:31:54.912451 3, 0xFFFF, sum = 0
4158 12:31:54.915515 4, 0xFFFF, sum = 0
4159 12:31:54.915949 5, 0xFFFF, sum = 0
4160 12:31:54.918682 6, 0xFFFF, sum = 0
4161 12:31:54.919223 7, 0xFFFF, sum = 0
4162 12:31:54.922448 8, 0x0, sum = 1
4163 12:31:54.923041 9, 0x0, sum = 2
4164 12:31:54.925109 10, 0x0, sum = 3
4165 12:31:54.925706 11, 0x0, sum = 4
4166 12:31:54.926074 best_step = 9
4167 12:31:54.926406
4168 12:31:54.928523 ==
4169 12:31:54.931946 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 12:31:54.934942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 12:31:54.935377 ==
4172 12:31:54.935721 RX Vref Scan: 1
4173 12:31:54.936138
4174 12:31:54.938394 RX Vref 0 -> 0, step: 1
4175 12:31:54.938918
4176 12:31:54.941343 RX Delay -179 -> 252, step: 8
4177 12:31:54.941774
4178 12:31:54.944735 Set Vref, RX VrefLevel [Byte0]: 52
4179 12:31:54.948014 [Byte1]: 59
4180 12:31:54.948485
4181 12:31:54.951503 Final RX Vref Byte 0 = 52 to rank0
4182 12:31:54.954824 Final RX Vref Byte 1 = 59 to rank0
4183 12:31:54.958332 Final RX Vref Byte 0 = 52 to rank1
4184 12:31:54.961779 Final RX Vref Byte 1 = 59 to rank1==
4185 12:31:54.965319 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 12:31:54.968268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 12:31:54.971186 ==
4188 12:31:54.971724 DQS Delay:
4189 12:31:54.972124 DQS0 = 0, DQS1 = 0
4190 12:31:54.974678 DQM Delay:
4191 12:31:54.975112 DQM0 = 42, DQM1 = 34
4192 12:31:54.978454 DQ Delay:
4193 12:31:54.978988 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4194 12:31:54.981474 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4195 12:31:54.984745 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =32
4196 12:31:54.987805 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4197 12:31:54.991783
4198 12:31:54.992384
4199 12:31:54.998407 [DQSOSCAuto] RK0, (LSB)MR18= 0x483f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4200 12:31:55.001460 CH0 RK0: MR19=808, MR18=483F
4201 12:31:55.007639 CH0_RK0: MR19=0x808, MR18=0x483F, DQSOSC=396, MR23=63, INC=167, DEC=111
4202 12:31:55.008111
4203 12:31:55.010607 ----->DramcWriteLeveling(PI) begin...
4204 12:31:55.011043 ==
4205 12:31:55.014227 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 12:31:55.017148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 12:31:55.017588 ==
4208 12:31:55.020666 Write leveling (Byte 0): 35 => 35
4209 12:31:55.024138 Write leveling (Byte 1): 31 => 31
4210 12:31:55.027518 DramcWriteLeveling(PI) end<-----
4211 12:31:55.028114
4212 12:31:55.028471 ==
4213 12:31:55.030376 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 12:31:55.033843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 12:31:55.037231 ==
4216 12:31:55.037717 [Gating] SW mode calibration
4217 12:31:55.046680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 12:31:55.050162 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 12:31:55.053447 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 12:31:55.059923 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 12:31:55.063524 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 12:31:55.067139 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
4223 12:31:55.073482 0 9 16 | B1->B0 | 2b2b 2626 | 1 0 | (1 0) (0 0)
4224 12:31:55.076347 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 12:31:55.079759 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 12:31:55.086209 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 12:31:55.089309 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 12:31:55.092993 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 12:31:55.099423 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 12:31:55.102581 0 10 12 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
4231 12:31:55.106111 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4232 12:31:55.112488 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 12:31:55.116099 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 12:31:55.119250 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 12:31:55.125428 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 12:31:55.128960 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 12:31:55.132019 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 12:31:55.139010 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4239 12:31:55.141998 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4240 12:31:55.145523 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 12:31:55.151829 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:31:55.155429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:31:55.158667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:31:55.165090 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 12:31:55.168504 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:31:55.171794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:31:55.178219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:31:55.181762 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:31:55.185101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:31:55.191726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:31:55.194785 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:31:55.198547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:31:55.204728 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:31:55.207690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4255 12:31:55.214640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4256 12:31:55.215180 Total UI for P1: 0, mck2ui 16
4257 12:31:55.217665 best dqsien dly found for B0: ( 0, 13, 12)
4258 12:31:55.224201 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 12:31:55.227659 Total UI for P1: 0, mck2ui 16
4260 12:31:55.230616 best dqsien dly found for B1: ( 0, 13, 16)
4261 12:31:55.234112 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4262 12:31:55.237695 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4263 12:31:55.238146
4264 12:31:55.240584 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 12:31:55.244087 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4266 12:31:55.246963 [Gating] SW calibration Done
4267 12:31:55.247371 ==
4268 12:31:55.250490 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 12:31:55.254068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 12:31:55.257317 ==
4271 12:31:55.257745 RX Vref Scan: 0
4272 12:31:55.258091
4273 12:31:55.260749 RX Vref 0 -> 0, step: 1
4274 12:31:55.261187
4275 12:31:55.263464 RX Delay -230 -> 252, step: 16
4276 12:31:55.267054 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4277 12:31:55.270558 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4278 12:31:55.273490 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4279 12:31:55.280459 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4280 12:31:55.283402 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4281 12:31:55.287190 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4282 12:31:55.289881 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4283 12:31:55.293428 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4284 12:31:55.300207 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4285 12:31:55.303105 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4286 12:31:55.306808 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4287 12:31:55.309674 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4288 12:31:55.316399 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4289 12:31:55.319574 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4290 12:31:55.323061 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4291 12:31:55.326474 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4292 12:31:55.329736 ==
4293 12:31:55.333464 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 12:31:55.336435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 12:31:55.337137 ==
4296 12:31:55.337548 DQS Delay:
4297 12:31:55.339331 DQS0 = 0, DQS1 = 0
4298 12:31:55.339752 DQM Delay:
4299 12:31:55.342916 DQM0 = 41, DQM1 = 33
4300 12:31:55.343336 DQ Delay:
4301 12:31:55.345907 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4302 12:31:55.349191 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4303 12:31:55.352756 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4304 12:31:55.355728 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4305 12:31:55.356287
4306 12:31:55.356775
4307 12:31:55.357218 ==
4308 12:31:55.359314 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 12:31:55.362053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 12:31:55.362766 ==
4311 12:31:55.363261
4312 12:31:55.365788
4313 12:31:55.366205 TX Vref Scan disable
4314 12:31:55.369116 == TX Byte 0 ==
4315 12:31:55.372130 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4316 12:31:55.375734 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4317 12:31:55.378608 == TX Byte 1 ==
4318 12:31:55.382066 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4319 12:31:55.385134 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4320 12:31:55.388745 ==
4321 12:31:55.391663 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 12:31:55.395259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 12:31:55.395692 ==
4324 12:31:55.396173
4325 12:31:55.396535
4326 12:31:55.398166 TX Vref Scan disable
4327 12:31:55.401482 == TX Byte 0 ==
4328 12:31:55.405157 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4329 12:31:55.408148 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4330 12:31:55.411626 == TX Byte 1 ==
4331 12:31:55.414699 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4332 12:31:55.418279 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4333 12:31:55.418810
4334 12:31:55.419249 [DATLAT]
4335 12:31:55.421603 Freq=600, CH0 RK1
4336 12:31:55.422121
4337 12:31:55.425015 DATLAT Default: 0x9
4338 12:31:55.425429 0, 0xFFFF, sum = 0
4339 12:31:55.427944 1, 0xFFFF, sum = 0
4340 12:31:55.428407 2, 0xFFFF, sum = 0
4341 12:31:55.431375 3, 0xFFFF, sum = 0
4342 12:31:55.431764 4, 0xFFFF, sum = 0
4343 12:31:55.434961 5, 0xFFFF, sum = 0
4344 12:31:55.435352 6, 0xFFFF, sum = 0
4345 12:31:55.437848 7, 0xFFFF, sum = 0
4346 12:31:55.438404 8, 0x0, sum = 1
4347 12:31:55.441524 9, 0x0, sum = 2
4348 12:31:55.442019 10, 0x0, sum = 3
4349 12:31:55.442357 11, 0x0, sum = 4
4350 12:31:55.445078 best_step = 9
4351 12:31:55.445545
4352 12:31:55.445903 ==
4353 12:31:55.447904 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 12:31:55.451386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 12:31:55.451779 ==
4356 12:31:55.455029 RX Vref Scan: 0
4357 12:31:55.455411
4358 12:31:55.455721 RX Vref 0 -> 0, step: 1
4359 12:31:55.457784
4360 12:31:55.458161 RX Delay -179 -> 252, step: 8
4361 12:31:55.465305 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4362 12:31:55.468900 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4363 12:31:55.472281 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4364 12:31:55.475368 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4365 12:31:55.482190 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4366 12:31:55.485433 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4367 12:31:55.488597 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4368 12:31:55.491964 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4369 12:31:55.499050 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4370 12:31:55.502007 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4371 12:31:55.505300 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4372 12:31:55.508474 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4373 12:31:55.515256 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4374 12:31:55.518200 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4375 12:31:55.521711 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4376 12:31:55.524696 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4377 12:31:55.525118 ==
4378 12:31:55.528376 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 12:31:55.535091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 12:31:55.535640 ==
4381 12:31:55.535983 DQS Delay:
4382 12:31:55.538344 DQS0 = 0, DQS1 = 0
4383 12:31:55.538870 DQM Delay:
4384 12:31:55.539214 DQM0 = 40, DQM1 = 34
4385 12:31:55.541418 DQ Delay:
4386 12:31:55.544575 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4387 12:31:55.547645 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4388 12:31:55.551423 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4389 12:31:55.554342 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4390 12:31:55.554761
4391 12:31:55.555097
4392 12:31:55.561310 [DQSOSCAuto] RK1, (LSB)MR18= 0x3935, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4393 12:31:55.564426 CH0 RK1: MR19=808, MR18=3935
4394 12:31:55.570948 CH0_RK1: MR19=0x808, MR18=0x3935, DQSOSC=399, MR23=63, INC=164, DEC=109
4395 12:31:55.574049 [RxdqsGatingPostProcess] freq 600
4396 12:31:55.581042 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 12:31:55.581585 Pre-setting of DQS Precalculation
4398 12:31:55.587355 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 12:31:55.587815 ==
4400 12:31:55.590838 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 12:31:55.593968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 12:31:55.594495 ==
4403 12:31:55.600707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 12:31:55.607302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4405 12:31:55.610112 [CA 0] Center 36 (6~66) winsize 61
4406 12:31:55.613620 [CA 1] Center 36 (6~66) winsize 61
4407 12:31:55.617392 [CA 2] Center 34 (4~65) winsize 62
4408 12:31:55.620318 [CA 3] Center 34 (4~65) winsize 62
4409 12:31:55.623829 [CA 4] Center 34 (4~65) winsize 62
4410 12:31:55.626797 [CA 5] Center 34 (3~65) winsize 63
4411 12:31:55.627237
4412 12:31:55.630171 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4413 12:31:55.630713
4414 12:31:55.633614 [CATrainingPosCal] consider 1 rank data
4415 12:31:55.636377 u2DelayCellTimex100 = 270/100 ps
4416 12:31:55.639897 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4417 12:31:55.643396 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4418 12:31:55.646563 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 12:31:55.649588 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 12:31:55.656219 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 12:31:55.660063 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4422 12:31:55.660621
4423 12:31:55.663390 CA PerBit enable=1, Macro0, CA PI delay=34
4424 12:31:55.663819
4425 12:31:55.665854 [CBTSetCACLKResult] CA Dly = 34
4426 12:31:55.666315 CS Dly: 3 (0~34)
4427 12:31:55.666665 ==
4428 12:31:55.669268 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 12:31:55.675891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 12:31:55.676494 ==
4431 12:31:55.679359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 12:31:55.686155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4433 12:31:55.688961 [CA 0] Center 35 (5~66) winsize 62
4434 12:31:55.692134 [CA 1] Center 35 (5~66) winsize 62
4435 12:31:55.695549 [CA 2] Center 34 (4~65) winsize 62
4436 12:31:55.698726 [CA 3] Center 34 (3~65) winsize 63
4437 12:31:55.701576 [CA 4] Center 34 (4~65) winsize 62
4438 12:31:55.705308 [CA 5] Center 33 (3~64) winsize 62
4439 12:31:55.705392
4440 12:31:55.708826 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4441 12:31:55.708910
4442 12:31:55.711767 [CATrainingPosCal] consider 2 rank data
4443 12:31:55.715306 u2DelayCellTimex100 = 270/100 ps
4444 12:31:55.718517 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4445 12:31:55.725127 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 12:31:55.728815 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 12:31:55.731691 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 12:31:55.735478 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 12:31:55.738448 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 12:31:55.738633
4451 12:31:55.741789 CA PerBit enable=1, Macro0, CA PI delay=33
4452 12:31:55.741968
4453 12:31:55.744656 [CBTSetCACLKResult] CA Dly = 33
4454 12:31:55.747902 CS Dly: 4 (0~36)
4455 12:31:55.748160
4456 12:31:55.751461 ----->DramcWriteLeveling(PI) begin...
4457 12:31:55.751633 ==
4458 12:31:55.754882 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 12:31:55.758517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 12:31:55.758779 ==
4461 12:31:55.761497 Write leveling (Byte 0): 28 => 28
4462 12:31:55.764313 Write leveling (Byte 1): 29 => 29
4463 12:31:55.767895 DramcWriteLeveling(PI) end<-----
4464 12:31:55.768183
4465 12:31:55.768403 ==
4466 12:31:55.771490 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 12:31:55.774408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 12:31:55.774745 ==
4469 12:31:55.778111 [Gating] SW mode calibration
4470 12:31:55.784168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 12:31:55.791432 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 12:31:55.794277 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 12:31:55.800840 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 12:31:55.804160 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 12:31:55.807670 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
4476 12:31:55.810512 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 12:31:55.817670 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 12:31:55.820334 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 12:31:55.823938 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 12:31:55.829961 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 12:31:55.833577 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 12:31:55.839986 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 12:31:55.843660 0 10 12 | B1->B0 | 3232 3232 | 0 1 | (0 0) (0 0)
4484 12:31:55.846618 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 12:31:55.853308 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 12:31:55.857160 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 12:31:55.860114 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 12:31:55.866884 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 12:31:55.870120 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:31:55.873443 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:31:55.879799 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4492 12:31:55.883471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:31:55.886276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:31:55.893107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:31:55.896686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:31:55.899643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:31:55.906306 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:31:55.909334 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:31:55.912864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:31:55.919392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:31:55.922887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:31:55.926051 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:31:55.932604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:31:55.936167 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:31:55.939146 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:31:55.945772 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4507 12:31:55.949343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4508 12:31:55.952285 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:31:55.955901 Total UI for P1: 0, mck2ui 16
4510 12:31:55.958894 best dqsien dly found for B0: ( 0, 13, 10)
4511 12:31:55.961882 Total UI for P1: 0, mck2ui 16
4512 12:31:55.965434 best dqsien dly found for B1: ( 0, 13, 14)
4513 12:31:55.968548 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4514 12:31:55.972097 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4515 12:31:55.972542
4516 12:31:55.978892 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4517 12:31:55.981614 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4518 12:31:55.985069 [Gating] SW calibration Done
4519 12:31:55.985584 ==
4520 12:31:55.988531 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 12:31:55.991976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 12:31:55.992459 ==
4523 12:31:55.992808 RX Vref Scan: 0
4524 12:31:55.993132
4525 12:31:55.994840 RX Vref 0 -> 0, step: 1
4526 12:31:55.995264
4527 12:31:55.998321 RX Delay -230 -> 252, step: 16
4528 12:31:56.001760 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4529 12:31:56.008193 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4530 12:31:56.011465 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4531 12:31:56.014884 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4532 12:31:56.018245 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4533 12:31:56.021287 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4534 12:31:56.027699 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4535 12:31:56.031372 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4536 12:31:56.034251 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4537 12:31:56.037845 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4538 12:31:56.044496 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4539 12:31:56.047461 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4540 12:31:56.051127 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4541 12:31:56.054030 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4542 12:31:56.060981 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4543 12:31:56.064115 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4544 12:31:56.064510 ==
4545 12:31:56.067747 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 12:31:56.071075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 12:31:56.071610 ==
4548 12:31:56.074516 DQS Delay:
4549 12:31:56.075047 DQS0 = 0, DQS1 = 0
4550 12:31:56.075393 DQM Delay:
4551 12:31:56.077293 DQM0 = 50, DQM1 = 42
4552 12:31:56.077738 DQ Delay:
4553 12:31:56.080712 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4554 12:31:56.083493 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4555 12:31:56.086969 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4556 12:31:56.090382 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4557 12:31:56.090810
4558 12:31:56.091154
4559 12:31:56.093835 ==
4560 12:31:56.094261 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 12:31:56.100337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 12:31:56.100764 ==
4563 12:31:56.101166
4564 12:31:56.101491
4565 12:31:56.103257 TX Vref Scan disable
4566 12:31:56.103682 == TX Byte 0 ==
4567 12:31:56.110203 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4568 12:31:56.113164 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4569 12:31:56.113603 == TX Byte 1 ==
4570 12:31:56.119823 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 12:31:56.123364 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 12:31:56.123793 ==
4573 12:31:56.126462 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 12:31:56.129519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:31:56.129950 ==
4576 12:31:56.130291
4577 12:31:56.130641
4578 12:31:56.133006 TX Vref Scan disable
4579 12:31:56.136570 == TX Byte 0 ==
4580 12:31:56.139475 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4581 12:31:56.142941 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4582 12:31:56.146488 == TX Byte 1 ==
4583 12:31:56.149515 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4584 12:31:56.152562 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4585 12:31:56.156007
4586 12:31:56.156451 [DATLAT]
4587 12:31:56.156763 Freq=600, CH1 RK0
4588 12:31:56.157060
4589 12:31:56.159089 DATLAT Default: 0x9
4590 12:31:56.159480 0, 0xFFFF, sum = 0
4591 12:31:56.162786 1, 0xFFFF, sum = 0
4592 12:31:56.163288 2, 0xFFFF, sum = 0
4593 12:31:56.166216 3, 0xFFFF, sum = 0
4594 12:31:56.169150 4, 0xFFFF, sum = 0
4595 12:31:56.169544 5, 0xFFFF, sum = 0
4596 12:31:56.172681 6, 0xFFFF, sum = 0
4597 12:31:56.173113 7, 0xFFFF, sum = 0
4598 12:31:56.175488 8, 0x0, sum = 1
4599 12:31:56.175921 9, 0x0, sum = 2
4600 12:31:56.176348 10, 0x0, sum = 3
4601 12:31:56.178966 11, 0x0, sum = 4
4602 12:31:56.179396 best_step = 9
4603 12:31:56.179741
4604 12:31:56.180103 ==
4605 12:31:56.182374 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 12:31:56.189358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 12:31:56.189912 ==
4608 12:31:56.190369 RX Vref Scan: 1
4609 12:31:56.190790
4610 12:31:56.192150 RX Vref 0 -> 0, step: 1
4611 12:31:56.192598
4612 12:31:56.195596 RX Delay -179 -> 252, step: 8
4613 12:31:56.196085
4614 12:31:56.198714 Set Vref, RX VrefLevel [Byte0]: 53
4615 12:31:56.202163 [Byte1]: 53
4616 12:31:56.202662
4617 12:31:56.205688 Final RX Vref Byte 0 = 53 to rank0
4618 12:31:56.208562 Final RX Vref Byte 1 = 53 to rank0
4619 12:31:56.211842 Final RX Vref Byte 0 = 53 to rank1
4620 12:31:56.215301 Final RX Vref Byte 1 = 53 to rank1==
4621 12:31:56.218787 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 12:31:56.221710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 12:31:56.225464 ==
4624 12:31:56.226015 DQS Delay:
4625 12:31:56.226364 DQS0 = 0, DQS1 = 0
4626 12:31:56.228979 DQM Delay:
4627 12:31:56.229502 DQM0 = 45, DQM1 = 37
4628 12:31:56.231830 DQ Delay:
4629 12:31:56.232291 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4630 12:31:56.234996 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =40
4631 12:31:56.238684 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4632 12:31:56.241422 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =44
4633 12:31:56.245228
4634 12:31:56.245772
4635 12:31:56.251721 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4636 12:31:56.254407 CH1 RK0: MR19=808, MR18=2C45
4637 12:31:56.261196 CH1_RK0: MR19=0x808, MR18=0x2C45, DQSOSC=396, MR23=63, INC=167, DEC=111
4638 12:31:56.261625
4639 12:31:56.264633 ----->DramcWriteLeveling(PI) begin...
4640 12:31:56.265064 ==
4641 12:31:56.267448 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 12:31:56.271123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 12:31:56.271568 ==
4644 12:31:56.274332 Write leveling (Byte 0): 28 => 28
4645 12:31:56.277733 Write leveling (Byte 1): 28 => 28
4646 12:31:56.280736 DramcWriteLeveling(PI) end<-----
4647 12:31:56.281180
4648 12:31:56.281526 ==
4649 12:31:56.284302 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 12:31:56.287922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 12:31:56.288775 ==
4652 12:31:56.290778 [Gating] SW mode calibration
4653 12:31:56.297758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 12:31:56.303961 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 12:31:56.307429 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 12:31:56.313667 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 12:31:56.317346 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 12:31:56.320496 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (1 0) (0 0)
4659 12:31:56.326952 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4660 12:31:56.330425 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 12:31:56.333856 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 12:31:56.340434 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 12:31:56.343337 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 12:31:56.346751 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 12:31:56.353392 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4666 12:31:56.356242 0 10 12 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
4667 12:31:56.359853 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 12:31:56.366496 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 12:31:56.369545 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 12:31:56.373114 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 12:31:56.379791 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 12:31:56.382779 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 12:31:56.386259 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:31:56.392701 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4675 12:31:56.396217 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:31:56.399251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:31:56.405987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:31:56.409276 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:31:56.413112 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:31:56.419098 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:31:56.422970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:31:56.425438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:31:56.432441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:31:56.435621 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:31:56.438464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:31:56.445472 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:31:56.448475 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:31:56.452006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:31:56.458103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:31:56.461738 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 12:31:56.464643 Total UI for P1: 0, mck2ui 16
4692 12:31:56.468342 best dqsien dly found for B0: ( 0, 13, 10)
4693 12:31:56.471679 Total UI for P1: 0, mck2ui 16
4694 12:31:56.475134 best dqsien dly found for B1: ( 0, 13, 10)
4695 12:31:56.478713 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4696 12:31:56.481524 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4697 12:31:56.481953
4698 12:31:56.485213 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4699 12:31:56.491504 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4700 12:31:56.492224 [Gating] SW calibration Done
4701 12:31:56.492671 ==
4702 12:31:56.495021 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 12:31:56.501336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 12:31:56.501874 ==
4705 12:31:56.502218 RX Vref Scan: 0
4706 12:31:56.502540
4707 12:31:56.504613 RX Vref 0 -> 0, step: 1
4708 12:31:56.505035
4709 12:31:56.507615 RX Delay -230 -> 252, step: 16
4710 12:31:56.511212 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4711 12:31:56.514254 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4712 12:31:56.521353 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4713 12:31:56.524697 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4714 12:31:56.527488 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4715 12:31:56.530621 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4716 12:31:56.534064 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4717 12:31:56.540576 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4718 12:31:56.543988 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4719 12:31:56.547666 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4720 12:31:56.550507 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4721 12:31:56.556598 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4722 12:31:56.560068 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4723 12:31:56.563506 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4724 12:31:56.567106 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4725 12:31:56.573760 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4726 12:31:56.574183 ==
4727 12:31:56.576901 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 12:31:56.580466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 12:31:56.580894 ==
4730 12:31:56.581238 DQS Delay:
4731 12:31:56.583651 DQS0 = 0, DQS1 = 0
4732 12:31:56.584218 DQM Delay:
4733 12:31:56.587177 DQM0 = 44, DQM1 = 44
4734 12:31:56.587707 DQ Delay:
4735 12:31:56.590445 DQ0 =57, DQ1 =33, DQ2 =33, DQ3 =33
4736 12:31:56.593145 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =33
4737 12:31:56.596691 DQ8 =25, DQ9 =25, DQ10 =49, DQ11 =33
4738 12:31:56.599773 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4739 12:31:56.600332
4740 12:31:56.600674
4741 12:31:56.600986 ==
4742 12:31:56.603580 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 12:31:56.609633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 12:31:56.610065 ==
4745 12:31:56.610407
4746 12:31:56.610725
4747 12:31:56.611032 TX Vref Scan disable
4748 12:31:56.613655 == TX Byte 0 ==
4749 12:31:56.616446 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4750 12:31:56.620087 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4751 12:31:56.623090 == TX Byte 1 ==
4752 12:31:56.626527 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4753 12:31:56.633225 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4754 12:31:56.633670 ==
4755 12:31:56.636720 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 12:31:56.639685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 12:31:56.640153 ==
4758 12:31:56.640506
4759 12:31:56.640824
4760 12:31:56.643218 TX Vref Scan disable
4761 12:31:56.646515 == TX Byte 0 ==
4762 12:31:56.649367 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4763 12:31:56.653000 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4764 12:31:56.655954 == TX Byte 1 ==
4765 12:31:56.659531 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4766 12:31:56.662463 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4767 12:31:56.662955
4768 12:31:56.663303 [DATLAT]
4769 12:31:56.666117 Freq=600, CH1 RK1
4770 12:31:56.666591
4771 12:31:56.669076 DATLAT Default: 0x9
4772 12:31:56.669506 0, 0xFFFF, sum = 0
4773 12:31:56.672770 1, 0xFFFF, sum = 0
4774 12:31:56.673208 2, 0xFFFF, sum = 0
4775 12:31:56.675730 3, 0xFFFF, sum = 0
4776 12:31:56.676348 4, 0xFFFF, sum = 0
4777 12:31:56.679229 5, 0xFFFF, sum = 0
4778 12:31:56.680055 6, 0xFFFF, sum = 0
4779 12:31:56.682310 7, 0xFFFF, sum = 0
4780 12:31:56.682860 8, 0x0, sum = 1
4781 12:31:56.685547 9, 0x0, sum = 2
4782 12:31:56.686096 10, 0x0, sum = 3
4783 12:31:56.688826 11, 0x0, sum = 4
4784 12:31:56.689330 best_step = 9
4785 12:31:56.689789
4786 12:31:56.690185 ==
4787 12:31:56.692199 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 12:31:56.695268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 12:31:56.698807 ==
4790 12:31:56.699416 RX Vref Scan: 0
4791 12:31:56.700020
4792 12:31:56.701648 RX Vref 0 -> 0, step: 1
4793 12:31:56.702305
4794 12:31:56.705162 RX Delay -179 -> 252, step: 8
4795 12:31:56.707961 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4796 12:31:56.711515 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4797 12:31:56.717860 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4798 12:31:56.720873 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4799 12:31:56.724503 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4800 12:31:56.727809 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4801 12:31:56.734191 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4802 12:31:56.737586 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4803 12:31:56.740930 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4804 12:31:56.744350 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4805 12:31:56.750759 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4806 12:31:56.754143 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4807 12:31:56.757532 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4808 12:31:56.760430 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4809 12:31:56.767034 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4810 12:31:56.770571 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4811 12:31:56.770657 ==
4812 12:31:56.773552 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 12:31:56.777168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 12:31:56.777252 ==
4815 12:31:56.780115 DQS Delay:
4816 12:31:56.780199 DQS0 = 0, DQS1 = 0
4817 12:31:56.780265 DQM Delay:
4818 12:31:56.783932 DQM0 = 41, DQM1 = 39
4819 12:31:56.784014 DQ Delay:
4820 12:31:56.786924 DQ0 =44, DQ1 =40, DQ2 =32, DQ3 =40
4821 12:31:56.790368 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =40
4822 12:31:56.793262 DQ8 =24, DQ9 =28, DQ10 =44, DQ11 =32
4823 12:31:56.796790 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4824 12:31:56.796873
4825 12:31:56.796938
4826 12:31:56.806875 [DQSOSCAuto] RK1, (LSB)MR18= 0x3357, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4827 12:31:56.809807 CH1 RK1: MR19=808, MR18=3357
4828 12:31:56.816386 CH1_RK1: MR19=0x808, MR18=0x3357, DQSOSC=393, MR23=63, INC=169, DEC=113
4829 12:31:56.816469 [RxdqsGatingPostProcess] freq 600
4830 12:31:56.823161 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4831 12:31:56.826483 Pre-setting of DQS Precalculation
4832 12:31:56.829426 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4833 12:31:56.839219 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4834 12:31:56.845961 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4835 12:31:56.846061
4836 12:31:56.846159
4837 12:31:56.849525 [Calibration Summary] 1200 Mbps
4838 12:31:56.849611 CH 0, Rank 0
4839 12:31:56.852531 SW Impedance : PASS
4840 12:31:56.855936 DUTY Scan : NO K
4841 12:31:56.856017 ZQ Calibration : PASS
4842 12:31:56.859552 Jitter Meter : NO K
4843 12:31:56.859635 CBT Training : PASS
4844 12:31:56.862852 Write leveling : PASS
4845 12:31:56.865663 RX DQS gating : PASS
4846 12:31:56.865746 RX DQ/DQS(RDDQC) : PASS
4847 12:31:56.869197 TX DQ/DQS : PASS
4848 12:31:56.872223 RX DATLAT : PASS
4849 12:31:56.872305 RX DQ/DQS(Engine): PASS
4850 12:31:56.875832 TX OE : NO K
4851 12:31:56.875915 All Pass.
4852 12:31:56.875982
4853 12:31:56.878866 CH 0, Rank 1
4854 12:31:56.878949 SW Impedance : PASS
4855 12:31:56.882422 DUTY Scan : NO K
4856 12:31:56.886051 ZQ Calibration : PASS
4857 12:31:56.886134 Jitter Meter : NO K
4858 12:31:56.888966 CBT Training : PASS
4859 12:31:56.892262 Write leveling : PASS
4860 12:31:56.892346 RX DQS gating : PASS
4861 12:31:56.895763 RX DQ/DQS(RDDQC) : PASS
4862 12:31:56.898711 TX DQ/DQS : PASS
4863 12:31:56.898795 RX DATLAT : PASS
4864 12:31:56.902251 RX DQ/DQS(Engine): PASS
4865 12:31:56.905288 TX OE : NO K
4866 12:31:56.905371 All Pass.
4867 12:31:56.905438
4868 12:31:56.905499 CH 1, Rank 0
4869 12:31:56.908803 SW Impedance : PASS
4870 12:31:56.911784 DUTY Scan : NO K
4871 12:31:56.911867 ZQ Calibration : PASS
4872 12:31:56.915267 Jitter Meter : NO K
4873 12:31:56.918137 CBT Training : PASS
4874 12:31:56.918220 Write leveling : PASS
4875 12:31:56.921853 RX DQS gating : PASS
4876 12:31:56.924606 RX DQ/DQS(RDDQC) : PASS
4877 12:31:56.924688 TX DQ/DQS : PASS
4878 12:31:56.928162 RX DATLAT : PASS
4879 12:31:56.931456 RX DQ/DQS(Engine): PASS
4880 12:31:56.931539 TX OE : NO K
4881 12:31:56.934959 All Pass.
4882 12:31:56.935041
4883 12:31:56.935108 CH 1, Rank 1
4884 12:31:56.937910 SW Impedance : PASS
4885 12:31:56.937992 DUTY Scan : NO K
4886 12:31:56.941486 ZQ Calibration : PASS
4887 12:31:56.944402 Jitter Meter : NO K
4888 12:31:56.944485 CBT Training : PASS
4889 12:31:56.947792 Write leveling : PASS
4890 12:31:56.951306 RX DQS gating : PASS
4891 12:31:56.951389 RX DQ/DQS(RDDQC) : PASS
4892 12:31:56.954290 TX DQ/DQS : PASS
4893 12:31:56.957674 RX DATLAT : PASS
4894 12:31:56.957757 RX DQ/DQS(Engine): PASS
4895 12:31:56.961181 TX OE : NO K
4896 12:31:56.961264 All Pass.
4897 12:31:56.961330
4898 12:31:56.964539 DramC Write-DBI off
4899 12:31:56.967929 PER_BANK_REFRESH: Hybrid Mode
4900 12:31:56.968019 TX_TRACKING: ON
4901 12:31:56.977650 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4902 12:31:56.980651 [FAST_K] Save calibration result to emmc
4903 12:31:56.984270 dramc_set_vcore_voltage set vcore to 662500
4904 12:31:56.987229 Read voltage for 933, 3
4905 12:31:56.987312 Vio18 = 0
4906 12:31:56.987379 Vcore = 662500
4907 12:31:56.990724 Vdram = 0
4908 12:31:56.990806 Vddq = 0
4909 12:31:56.990872 Vmddr = 0
4910 12:31:56.997214 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4911 12:31:57.000077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4912 12:31:57.003611 MEM_TYPE=3, freq_sel=17
4913 12:31:57.007113 sv_algorithm_assistance_LP4_1600
4914 12:31:57.010162 ============ PULL DRAM RESETB DOWN ============
4915 12:31:57.013705 ========== PULL DRAM RESETB DOWN end =========
4916 12:31:57.020205 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4917 12:31:57.023371 ===================================
4918 12:31:57.026824 LPDDR4 DRAM CONFIGURATION
4919 12:31:57.030229 ===================================
4920 12:31:57.030329 EX_ROW_EN[0] = 0x0
4921 12:31:57.033642 EX_ROW_EN[1] = 0x0
4922 12:31:57.033740 LP4Y_EN = 0x0
4923 12:31:57.037083 WORK_FSP = 0x0
4924 12:31:57.037160 WL = 0x3
4925 12:31:57.039981 RL = 0x3
4926 12:31:57.040106 BL = 0x2
4927 12:31:57.043601 RPST = 0x0
4928 12:31:57.043698 RD_PRE = 0x0
4929 12:31:57.046302 WR_PRE = 0x1
4930 12:31:57.046381 WR_PST = 0x0
4931 12:31:57.049894 DBI_WR = 0x0
4932 12:31:57.049967 DBI_RD = 0x0
4933 12:31:57.053362 OTF = 0x1
4934 12:31:57.056722 ===================================
4935 12:31:57.059745 ===================================
4936 12:31:57.059827 ANA top config
4937 12:31:57.063087 ===================================
4938 12:31:57.066122 DLL_ASYNC_EN = 0
4939 12:31:57.069447 ALL_SLAVE_EN = 1
4940 12:31:57.072842 NEW_RANK_MODE = 1
4941 12:31:57.075835 DLL_IDLE_MODE = 1
4942 12:31:57.075918 LP45_APHY_COMB_EN = 1
4943 12:31:57.079415 TX_ODT_DIS = 1
4944 12:31:57.082614 NEW_8X_MODE = 1
4945 12:31:57.086166 ===================================
4946 12:31:57.089334 ===================================
4947 12:31:57.092300 data_rate = 1866
4948 12:31:57.095889 CKR = 1
4949 12:31:57.098825 DQ_P2S_RATIO = 8
4950 12:31:57.102361 ===================================
4951 12:31:57.102461 CA_P2S_RATIO = 8
4952 12:31:57.105921 DQ_CA_OPEN = 0
4953 12:31:57.108922 DQ_SEMI_OPEN = 0
4954 12:31:57.111888 CA_SEMI_OPEN = 0
4955 12:31:57.115638 CA_FULL_RATE = 0
4956 12:31:57.118523 DQ_CKDIV4_EN = 1
4957 12:31:57.118605 CA_CKDIV4_EN = 1
4958 12:31:57.122160 CA_PREDIV_EN = 0
4959 12:31:57.125047 PH8_DLY = 0
4960 12:31:57.128693 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4961 12:31:57.131956 DQ_AAMCK_DIV = 4
4962 12:31:57.135452 CA_AAMCK_DIV = 4
4963 12:31:57.135534 CA_ADMCK_DIV = 4
4964 12:31:57.138166 DQ_TRACK_CA_EN = 0
4965 12:31:57.141557 CA_PICK = 933
4966 12:31:57.145114 CA_MCKIO = 933
4967 12:31:57.148166 MCKIO_SEMI = 0
4968 12:31:57.151519 PLL_FREQ = 3732
4969 12:31:57.154955 DQ_UI_PI_RATIO = 32
4970 12:31:57.158324 CA_UI_PI_RATIO = 0
4971 12:31:57.161433 ===================================
4972 12:31:57.164918 ===================================
4973 12:31:57.165001 memory_type:LPDDR4
4974 12:31:57.168422 GP_NUM : 10
4975 12:31:57.171097 SRAM_EN : 1
4976 12:31:57.171179 MD32_EN : 0
4977 12:31:57.174424 ===================================
4978 12:31:57.177820 [ANA_INIT] >>>>>>>>>>>>>>
4979 12:31:57.181582 <<<<<< [CONFIGURE PHASE]: ANA_TX
4980 12:31:57.184555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4981 12:31:57.188022 ===================================
4982 12:31:57.191066 data_rate = 1866,PCW = 0X8f00
4983 12:31:57.194127 ===================================
4984 12:31:57.197724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4985 12:31:57.200737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4986 12:31:57.207155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 12:31:57.210655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4988 12:31:57.214239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4989 12:31:57.217221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4990 12:31:57.220636 [ANA_INIT] flow start
4991 12:31:57.223644 [ANA_INIT] PLL >>>>>>>>
4992 12:31:57.223726 [ANA_INIT] PLL <<<<<<<<
4993 12:31:57.227310 [ANA_INIT] MIDPI >>>>>>>>
4994 12:31:57.230211 [ANA_INIT] MIDPI <<<<<<<<
4995 12:31:57.233820 [ANA_INIT] DLL >>>>>>>>
4996 12:31:57.233928 [ANA_INIT] flow end
4997 12:31:57.237252 ============ LP4 DIFF to SE enter ============
4998 12:31:57.243303 ============ LP4 DIFF to SE exit ============
4999 12:31:57.243408 [ANA_INIT] <<<<<<<<<<<<<
5000 12:31:57.246580 [Flow] Enable top DCM control >>>>>
5001 12:31:57.250228 [Flow] Enable top DCM control <<<<<
5002 12:31:57.253708 Enable DLL master slave shuffle
5003 12:31:57.259809 ==============================================================
5004 12:31:57.263197 Gating Mode config
5005 12:31:57.266777 ==============================================================
5006 12:31:57.269701 Config description:
5007 12:31:57.279447 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5008 12:31:57.286100 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5009 12:31:57.289655 SELPH_MODE 0: By rank 1: By Phase
5010 12:31:57.295815 ==============================================================
5011 12:31:57.299341 GAT_TRACK_EN = 1
5012 12:31:57.302418 RX_GATING_MODE = 2
5013 12:31:57.305949 RX_GATING_TRACK_MODE = 2
5014 12:31:57.309030 SELPH_MODE = 1
5015 12:31:57.309133 PICG_EARLY_EN = 1
5016 12:31:57.312516 VALID_LAT_VALUE = 1
5017 12:31:57.318956 ==============================================================
5018 12:31:57.322472 Enter into Gating configuration >>>>
5019 12:31:57.325435 Exit from Gating configuration <<<<
5020 12:31:57.329002 Enter into DVFS_PRE_config >>>>>
5021 12:31:57.338732 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5022 12:31:57.342114 Exit from DVFS_PRE_config <<<<<
5023 12:31:57.345652 Enter into PICG configuration >>>>
5024 12:31:57.348409 Exit from PICG configuration <<<<
5025 12:31:57.351971 [RX_INPUT] configuration >>>>>
5026 12:31:57.354926 [RX_INPUT] configuration <<<<<
5027 12:31:57.362044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5028 12:31:57.364747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5029 12:31:57.371686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 12:31:57.378088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 12:31:57.384842 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 12:31:57.391573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 12:31:57.394686 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5034 12:31:57.397635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5035 12:31:57.401264 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5036 12:31:57.407897 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5037 12:31:57.411035 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5038 12:31:57.413842 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 12:31:57.417398 ===================================
5040 12:31:57.420760 LPDDR4 DRAM CONFIGURATION
5041 12:31:57.424168 ===================================
5042 12:31:57.427130 EX_ROW_EN[0] = 0x0
5043 12:31:57.427207 EX_ROW_EN[1] = 0x0
5044 12:31:57.430710 LP4Y_EN = 0x0
5045 12:31:57.430783 WORK_FSP = 0x0
5046 12:31:57.433723 WL = 0x3
5047 12:31:57.433793 RL = 0x3
5048 12:31:57.437401 BL = 0x2
5049 12:31:57.437473 RPST = 0x0
5050 12:31:57.440423 RD_PRE = 0x0
5051 12:31:57.440501 WR_PRE = 0x1
5052 12:31:57.443952 WR_PST = 0x0
5053 12:31:57.444087 DBI_WR = 0x0
5054 12:31:57.447274 DBI_RD = 0x0
5055 12:31:57.450312 OTF = 0x1
5056 12:31:57.453865 ===================================
5057 12:31:57.457261 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5058 12:31:57.460203 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5059 12:31:57.463644 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5060 12:31:57.466677 ===================================
5061 12:31:57.469930 LPDDR4 DRAM CONFIGURATION
5062 12:31:57.473487 ===================================
5063 12:31:57.477038 EX_ROW_EN[0] = 0x10
5064 12:31:57.477112 EX_ROW_EN[1] = 0x0
5065 12:31:57.480001 LP4Y_EN = 0x0
5066 12:31:57.480129 WORK_FSP = 0x0
5067 12:31:57.483352 WL = 0x3
5068 12:31:57.483467 RL = 0x3
5069 12:31:57.486677 BL = 0x2
5070 12:31:57.486796 RPST = 0x0
5071 12:31:57.489672 RD_PRE = 0x0
5072 12:31:57.493316 WR_PRE = 0x1
5073 12:31:57.493423 WR_PST = 0x0
5074 12:31:57.496358 DBI_WR = 0x0
5075 12:31:57.496461 DBI_RD = 0x0
5076 12:31:57.499469 OTF = 0x1
5077 12:31:57.503054 ===================================
5078 12:31:57.509569 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5079 12:31:57.512669 nWR fixed to 30
5080 12:31:57.512774 [ModeRegInit_LP4] CH0 RK0
5081 12:31:57.516271 [ModeRegInit_LP4] CH0 RK1
5082 12:31:57.519273 [ModeRegInit_LP4] CH1 RK0
5083 12:31:57.519376 [ModeRegInit_LP4] CH1 RK1
5084 12:31:57.522683 match AC timing 9
5085 12:31:57.525755 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5086 12:31:57.529116 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5087 12:31:57.535884 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5088 12:31:57.539270 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5089 12:31:57.545589 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5090 12:31:57.545666 ==
5091 12:31:57.549124 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 12:31:57.552101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 12:31:57.552189 ==
5094 12:31:57.558709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 12:31:57.565559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5096 12:31:57.568525 [CA 0] Center 37 (7~68) winsize 62
5097 12:31:57.571930 [CA 1] Center 37 (7~68) winsize 62
5098 12:31:57.574811 [CA 2] Center 34 (4~65) winsize 62
5099 12:31:57.578205 [CA 3] Center 34 (4~65) winsize 62
5100 12:31:57.581588 [CA 4] Center 33 (3~64) winsize 62
5101 12:31:57.585140 [CA 5] Center 32 (2~63) winsize 62
5102 12:31:57.585242
5103 12:31:57.588024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5104 12:31:57.588139
5105 12:31:57.591394 [CATrainingPosCal] consider 1 rank data
5106 12:31:57.594962 u2DelayCellTimex100 = 270/100 ps
5107 12:31:57.597975 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5108 12:31:57.601537 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5109 12:31:57.604592 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5110 12:31:57.607976 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5111 12:31:57.611704 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5112 12:31:57.618169 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5113 12:31:57.618268
5114 12:31:57.621223 CA PerBit enable=1, Macro0, CA PI delay=32
5115 12:31:57.621318
5116 12:31:57.624446 [CBTSetCACLKResult] CA Dly = 32
5117 12:31:57.624542 CS Dly: 5 (0~36)
5118 12:31:57.624635 ==
5119 12:31:57.627742 Dram Type= 6, Freq= 0, CH_0, rank 1
5120 12:31:57.631207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 12:31:57.634119 ==
5122 12:31:57.638160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5123 12:31:57.644676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5124 12:31:57.647662 [CA 0] Center 37 (7~68) winsize 62
5125 12:31:57.651139 [CA 1] Center 37 (7~68) winsize 62
5126 12:31:57.654120 [CA 2] Center 34 (4~65) winsize 62
5127 12:31:57.657490 [CA 3] Center 34 (4~65) winsize 62
5128 12:31:57.660968 [CA 4] Center 33 (3~64) winsize 62
5129 12:31:57.664497 [CA 5] Center 32 (2~63) winsize 62
5130 12:31:57.665028
5131 12:31:57.667234 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5132 12:31:57.667730
5133 12:31:57.670774 [CATrainingPosCal] consider 2 rank data
5134 12:31:57.673649 u2DelayCellTimex100 = 270/100 ps
5135 12:31:57.677184 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5136 12:31:57.680529 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5137 12:31:57.686863 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5138 12:31:57.690447 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5139 12:31:57.693744 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5140 12:31:57.697139 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5141 12:31:57.697646
5142 12:31:57.700228 CA PerBit enable=1, Macro0, CA PI delay=32
5143 12:31:57.700653
5144 12:31:57.703844 [CBTSetCACLKResult] CA Dly = 32
5145 12:31:57.704369 CS Dly: 6 (0~39)
5146 12:31:57.706909
5147 12:31:57.710610 ----->DramcWriteLeveling(PI) begin...
5148 12:31:57.711225 ==
5149 12:31:57.713241 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 12:31:57.716814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 12:31:57.716905 ==
5152 12:31:57.719899 Write leveling (Byte 0): 34 => 34
5153 12:31:57.723542 Write leveling (Byte 1): 26 => 26
5154 12:31:57.726620 DramcWriteLeveling(PI) end<-----
5155 12:31:57.726706
5156 12:31:57.726774 ==
5157 12:31:57.730149 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 12:31:57.732992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 12:31:57.733078 ==
5160 12:31:57.736469 [Gating] SW mode calibration
5161 12:31:57.743052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5162 12:31:57.749602 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5163 12:31:57.753143 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5164 12:31:57.755942 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 12:31:57.762452 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 12:31:57.765901 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 12:31:57.768959 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 12:31:57.775742 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 12:31:57.779260 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 12:31:57.782217 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
5171 12:31:57.788978 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5172 12:31:57.792011 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5173 12:31:57.795512 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 12:31:57.801937 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 12:31:57.805599 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 12:31:57.808801 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 12:31:57.815420 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 12:31:57.818881 0 15 28 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
5179 12:31:57.821835 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5180 12:31:57.828804 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 12:31:57.831778 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 12:31:57.835172 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 12:31:57.841697 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 12:31:57.845294 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 12:31:57.848304 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 12:31:57.855225 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 12:31:57.858346 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5188 12:31:57.864760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:31:57.867827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:31:57.871288 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:31:57.878018 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:31:57.881400 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:31:57.884220 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:31:57.890975 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:31:57.894301 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:31:57.897965 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:31:57.904252 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:31:57.907439 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:31:57.910929 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:31:57.917678 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:31:57.920680 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:31:57.924165 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5203 12:31:57.927208 Total UI for P1: 0, mck2ui 16
5204 12:31:57.930706 best dqsien dly found for B0: ( 1, 2, 26)
5205 12:31:57.937218 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5206 12:31:57.940133 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5207 12:31:57.943600 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 12:31:57.946501 Total UI for P1: 0, mck2ui 16
5209 12:31:57.950266 best dqsien dly found for B1: ( 1, 3, 4)
5210 12:31:57.953181 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5211 12:31:57.956744 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5212 12:31:57.957170
5213 12:31:57.963689 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5214 12:31:57.966946 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5215 12:31:57.967371 [Gating] SW calibration Done
5216 12:31:57.969857 ==
5217 12:31:57.973264 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 12:31:57.976402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 12:31:57.976847 ==
5220 12:31:57.977199 RX Vref Scan: 0
5221 12:31:57.977524
5222 12:31:57.979924 RX Vref 0 -> 0, step: 1
5223 12:31:57.980399
5224 12:31:57.983253 RX Delay -80 -> 252, step: 8
5225 12:31:57.986155 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5226 12:31:57.989577 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5227 12:31:57.992935 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5228 12:31:57.999039 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5229 12:31:58.002395 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5230 12:31:58.006083 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5231 12:31:58.009551 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5232 12:31:58.012595 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5233 12:31:58.019000 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5234 12:31:58.022174 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5235 12:31:58.025775 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5236 12:31:58.028759 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5237 12:31:58.032298 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5238 12:31:58.038775 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5239 12:31:58.041852 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5240 12:31:58.045162 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5241 12:31:58.045562 ==
5242 12:31:58.048620 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 12:31:58.051611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 12:31:58.052055 ==
5245 12:31:58.055285 DQS Delay:
5246 12:31:58.055683 DQS0 = 0, DQS1 = 0
5247 12:31:58.056048 DQM Delay:
5248 12:31:58.058693 DQM0 = 100, DQM1 = 88
5249 12:31:58.059106 DQ Delay:
5250 12:31:58.061828 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5251 12:31:58.065200 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5252 12:31:58.068028 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5253 12:31:58.071631 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5254 12:31:58.074656
5255 12:31:58.075051
5256 12:31:58.075396 ==
5257 12:31:58.078351 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 12:31:58.081145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 12:31:58.081456 ==
5260 12:31:58.081704
5261 12:31:58.081932
5262 12:31:58.084688 TX Vref Scan disable
5263 12:31:58.084999 == TX Byte 0 ==
5264 12:31:58.091062 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5265 12:31:58.094584 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5266 12:31:58.094897 == TX Byte 1 ==
5267 12:31:58.101245 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5268 12:31:58.104433 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5269 12:31:58.104745 ==
5270 12:31:58.107965 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 12:31:58.111066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 12:31:58.111376 ==
5273 12:31:58.111662
5274 12:31:58.114493
5275 12:31:58.114818 TX Vref Scan disable
5276 12:31:58.117429 == TX Byte 0 ==
5277 12:31:58.121190 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5278 12:31:58.124053 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5279 12:31:58.127646 == TX Byte 1 ==
5280 12:31:58.130716 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5281 12:31:58.137103 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5282 12:31:58.137586
5283 12:31:58.137918 [DATLAT]
5284 12:31:58.138152 Freq=933, CH0 RK0
5285 12:31:58.138376
5286 12:31:58.140751 DATLAT Default: 0xd
5287 12:31:58.143756 0, 0xFFFF, sum = 0
5288 12:31:58.144093 1, 0xFFFF, sum = 0
5289 12:31:58.147337 2, 0xFFFF, sum = 0
5290 12:31:58.147648 3, 0xFFFF, sum = 0
5291 12:31:58.150204 4, 0xFFFF, sum = 0
5292 12:31:58.150516 5, 0xFFFF, sum = 0
5293 12:31:58.153789 6, 0xFFFF, sum = 0
5294 12:31:58.154101 7, 0xFFFF, sum = 0
5295 12:31:58.156931 8, 0xFFFF, sum = 0
5296 12:31:58.157334 9, 0xFFFF, sum = 0
5297 12:31:58.160463 10, 0x0, sum = 1
5298 12:31:58.161088 11, 0x0, sum = 2
5299 12:31:58.163194 12, 0x0, sum = 3
5300 12:31:58.163507 13, 0x0, sum = 4
5301 12:31:58.166834 best_step = 11
5302 12:31:58.167310
5303 12:31:58.167733 ==
5304 12:31:58.170206 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 12:31:58.173139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 12:31:58.173450 ==
5307 12:31:58.176666 RX Vref Scan: 1
5308 12:31:58.177144
5309 12:31:58.177397 RX Vref 0 -> 0, step: 1
5310 12:31:58.177631
5311 12:31:58.179764 RX Delay -61 -> 252, step: 4
5312 12:31:58.180182
5313 12:31:58.183340 Set Vref, RX VrefLevel [Byte0]: 52
5314 12:31:58.186329 [Byte1]: 59
5315 12:31:58.190362
5316 12:31:58.190849 Final RX Vref Byte 0 = 52 to rank0
5317 12:31:58.193708 Final RX Vref Byte 1 = 59 to rank0
5318 12:31:58.196443 Final RX Vref Byte 0 = 52 to rank1
5319 12:31:58.199768 Final RX Vref Byte 1 = 59 to rank1==
5320 12:31:58.203197 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 12:31:58.210021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 12:31:58.210605 ==
5323 12:31:58.211101 DQS Delay:
5324 12:31:58.212978 DQS0 = 0, DQS1 = 0
5325 12:31:58.213574 DQM Delay:
5326 12:31:58.214098 DQM0 = 99, DQM1 = 88
5327 12:31:58.216509 DQ Delay:
5328 12:31:58.220007 DQ0 =100, DQ1 =98, DQ2 =96, DQ3 =94
5329 12:31:58.223395 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5330 12:31:58.226547 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5331 12:31:58.229885 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =94
5332 12:31:58.230195
5333 12:31:58.230444
5334 12:31:58.235799 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5335 12:31:58.239272 CH0 RK0: MR19=505, MR18=1610
5336 12:31:58.246021 CH0_RK0: MR19=0x505, MR18=0x1610, DQSOSC=414, MR23=63, INC=63, DEC=42
5337 12:31:58.246189
5338 12:31:58.248943 ----->DramcWriteLeveling(PI) begin...
5339 12:31:58.249081 ==
5340 12:31:58.252579 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 12:31:58.255551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 12:31:58.255669 ==
5343 12:31:58.259065 Write leveling (Byte 0): 32 => 32
5344 12:31:58.262738 Write leveling (Byte 1): 30 => 30
5345 12:31:58.265781 DramcWriteLeveling(PI) end<-----
5346 12:31:58.265885
5347 12:31:58.265968 ==
5348 12:31:58.269301 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 12:31:58.275782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 12:31:58.275914 ==
5351 12:31:58.276041 [Gating] SW mode calibration
5352 12:31:58.285375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 12:31:58.289061 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 12:31:58.295355 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5355 12:31:58.298234 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5356 12:31:58.301720 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 12:31:58.307952 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 12:31:58.311464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 12:31:58.314682 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 12:31:58.321375 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5361 12:31:58.324997 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
5362 12:31:58.328116 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5363 12:31:58.334497 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 12:31:58.337933 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 12:31:58.341494 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 12:31:58.347652 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 12:31:58.351127 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 12:31:58.354574 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5369 12:31:58.361356 0 15 28 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)
5370 12:31:58.364329 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5371 12:31:58.367896 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 12:31:58.374455 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 12:31:58.377953 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 12:31:58.380952 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 12:31:58.387752 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:31:58.390740 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:31:58.394160 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 12:31:58.400933 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:31:58.404125 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:31:58.407438 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:31:58.413547 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:31:58.416817 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:31:58.420070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:31:58.426355 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:31:58.429785 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:31:58.433342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:31:58.439813 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:31:58.442869 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:31:58.446031 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:31:58.452762 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:31:58.456222 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:31:58.459281 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5393 12:31:58.466069 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5394 12:31:58.469123 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5395 12:31:58.472721 Total UI for P1: 0, mck2ui 16
5396 12:31:58.475570 best dqsien dly found for B0: ( 1, 2, 26)
5397 12:31:58.479080 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 12:31:58.482790 Total UI for P1: 0, mck2ui 16
5399 12:31:58.485783 best dqsien dly found for B1: ( 1, 3, 0)
5400 12:31:58.489331 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5401 12:31:58.492173 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5402 12:31:58.492308
5403 12:31:58.498642 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5404 12:31:58.502083 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5405 12:31:58.505119 [Gating] SW calibration Done
5406 12:31:58.505298 ==
5407 12:31:58.508564 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 12:31:58.512040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 12:31:58.512151 ==
5410 12:31:58.512221 RX Vref Scan: 0
5411 12:31:58.512284
5412 12:31:58.515066 RX Vref 0 -> 0, step: 1
5413 12:31:58.515167
5414 12:31:58.518480 RX Delay -80 -> 252, step: 8
5415 12:31:58.521778 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5416 12:31:58.525362 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5417 12:31:58.531735 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5418 12:31:58.535273 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5419 12:31:58.538371 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5420 12:31:58.541954 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5421 12:31:58.544861 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5422 12:31:58.548423 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5423 12:31:58.554869 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5424 12:31:58.557835 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5425 12:31:58.561405 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5426 12:31:58.564889 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5427 12:31:58.567862 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5428 12:31:58.571302 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5429 12:31:58.578004 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5430 12:31:58.581485 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5431 12:31:58.581589 ==
5432 12:31:58.584521 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 12:31:58.587444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 12:31:58.587537 ==
5435 12:31:58.591100 DQS Delay:
5436 12:31:58.591188 DQS0 = 0, DQS1 = 0
5437 12:31:58.591257 DQM Delay:
5438 12:31:58.594053 DQM0 = 97, DQM1 = 89
5439 12:31:58.594157 DQ Delay:
5440 12:31:58.597702 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5441 12:31:58.600677 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5442 12:31:58.604081 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5443 12:31:58.607585 DQ12 =95, DQ13 =95, DQ14 =103, DQ15 =91
5444 12:31:58.607689
5445 12:31:58.607756
5446 12:31:58.610576 ==
5447 12:31:58.613994 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 12:31:58.617288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 12:31:58.617495 ==
5450 12:31:58.617617
5451 12:31:58.617725
5452 12:31:58.620575 TX Vref Scan disable
5453 12:31:58.620721 == TX Byte 0 ==
5454 12:31:58.627051 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5455 12:31:58.630607 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5456 12:31:58.630780 == TX Byte 1 ==
5457 12:31:58.636961 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5458 12:31:58.639880 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5459 12:31:58.639995 ==
5460 12:31:58.643650 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 12:31:58.646605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 12:31:58.646782 ==
5463 12:31:58.646908
5464 12:31:58.647025
5465 12:31:58.650233 TX Vref Scan disable
5466 12:31:58.653699 == TX Byte 0 ==
5467 12:31:58.656648 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5468 12:31:58.660191 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5469 12:31:58.663113 == TX Byte 1 ==
5470 12:31:58.666809 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5471 12:31:58.669701 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5472 12:31:58.669788
5473 12:31:58.673167 [DATLAT]
5474 12:31:58.673277 Freq=933, CH0 RK1
5475 12:31:58.673383
5476 12:31:58.676675 DATLAT Default: 0xb
5477 12:31:58.676810 0, 0xFFFF, sum = 0
5478 12:31:58.679591 1, 0xFFFF, sum = 0
5479 12:31:58.679696 2, 0xFFFF, sum = 0
5480 12:31:58.683223 3, 0xFFFF, sum = 0
5481 12:31:58.683310 4, 0xFFFF, sum = 0
5482 12:31:58.686306 5, 0xFFFF, sum = 0
5483 12:31:58.689851 6, 0xFFFF, sum = 0
5484 12:31:58.689940 7, 0xFFFF, sum = 0
5485 12:31:58.692774 8, 0xFFFF, sum = 0
5486 12:31:58.692861 9, 0xFFFF, sum = 0
5487 12:31:58.696323 10, 0x0, sum = 1
5488 12:31:58.696410 11, 0x0, sum = 2
5489 12:31:58.699219 12, 0x0, sum = 3
5490 12:31:58.699306 13, 0x0, sum = 4
5491 12:31:58.699376 best_step = 11
5492 12:31:58.699437
5493 12:31:58.702901 ==
5494 12:31:58.705860 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 12:31:58.709311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 12:31:58.709399 ==
5497 12:31:58.709467 RX Vref Scan: 0
5498 12:31:58.709531
5499 12:31:58.712760 RX Vref 0 -> 0, step: 1
5500 12:31:58.712844
5501 12:31:58.716164 RX Delay -53 -> 252, step: 4
5502 12:31:58.719170 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5503 12:31:58.726147 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5504 12:31:58.729213 iDelay=195, Bit 2, Center 92 (-1 ~ 186) 188
5505 12:31:58.732263 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5506 12:31:58.735909 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5507 12:31:58.738868 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5508 12:31:58.746196 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5509 12:31:58.749050 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5510 12:31:58.752801 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5511 12:31:58.755881 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5512 12:31:58.759353 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5513 12:31:58.765796 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5514 12:31:58.768797 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5515 12:31:58.772262 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5516 12:31:58.775253 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5517 12:31:58.778749 iDelay=195, Bit 15, Center 96 (7 ~ 186) 180
5518 12:31:58.779284 ==
5519 12:31:58.782193 Dram Type= 6, Freq= 0, CH_0, rank 1
5520 12:31:58.788707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 12:31:58.789274 ==
5522 12:31:58.789765 DQS Delay:
5523 12:31:58.790238 DQS0 = 0, DQS1 = 0
5524 12:31:58.791747 DQM Delay:
5525 12:31:58.792421 DQM0 = 98, DQM1 = 88
5526 12:31:58.795259 DQ Delay:
5527 12:31:58.798216 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =96
5528 12:31:58.801873 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =106
5529 12:31:58.805204 DQ8 =82, DQ9 =76, DQ10 =88, DQ11 =82
5530 12:31:58.808184 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5531 12:31:58.808729
5532 12:31:58.809209
5533 12:31:58.815023 [DQSOSCAuto] RK1, (LSB)MR18= 0x1511, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5534 12:31:58.817868 CH0 RK1: MR19=505, MR18=1511
5535 12:31:58.824921 CH0_RK1: MR19=0x505, MR18=0x1511, DQSOSC=415, MR23=63, INC=62, DEC=41
5536 12:31:58.827666 [RxdqsGatingPostProcess] freq 933
5537 12:31:58.834555 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5538 12:31:58.834998 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 12:31:58.838003 best DQS1 dly(2T, 0.5T) = (0, 11)
5540 12:31:58.840856 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 12:31:58.844352 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5542 12:31:58.847786 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 12:31:58.850796 best DQS1 dly(2T, 0.5T) = (0, 11)
5544 12:31:58.854534 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 12:31:58.857561 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5546 12:31:58.860576 Pre-setting of DQS Precalculation
5547 12:31:58.867131 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5548 12:31:58.867557 ==
5549 12:31:58.870696 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 12:31:58.873533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 12:31:58.873919 ==
5552 12:31:58.880671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 12:31:58.887334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 12:31:58.890305 [CA 0] Center 36 (6~67) winsize 62
5555 12:31:58.893812 [CA 1] Center 36 (6~67) winsize 62
5556 12:31:58.896757 [CA 2] Center 34 (4~65) winsize 62
5557 12:31:58.900503 [CA 3] Center 34 (4~65) winsize 62
5558 12:31:58.903427 [CA 4] Center 34 (4~65) winsize 62
5559 12:31:58.903881 [CA 5] Center 33 (3~64) winsize 62
5560 12:31:58.906891
5561 12:31:58.910046 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 12:31:58.910510
5563 12:31:58.913521 [CATrainingPosCal] consider 1 rank data
5564 12:31:58.916570 u2DelayCellTimex100 = 270/100 ps
5565 12:31:58.920304 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 12:31:58.922943 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 12:31:58.926554 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 12:31:58.929396 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 12:31:58.932825 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 12:31:58.936085 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 12:31:58.936512
5572 12:31:58.942812 CA PerBit enable=1, Macro0, CA PI delay=33
5573 12:31:58.943232
5574 12:31:58.946251 [CBTSetCACLKResult] CA Dly = 33
5575 12:31:58.946671 CS Dly: 5 (0~36)
5576 12:31:58.947009 ==
5577 12:31:58.949156 Dram Type= 6, Freq= 0, CH_1, rank 1
5578 12:31:58.952577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 12:31:58.953004 ==
5580 12:31:58.959219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 12:31:58.965585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5582 12:31:58.969167 [CA 0] Center 36 (6~67) winsize 62
5583 12:31:58.972723 [CA 1] Center 36 (6~67) winsize 62
5584 12:31:58.975788 [CA 2] Center 34 (4~65) winsize 62
5585 12:31:58.978784 [CA 3] Center 34 (3~65) winsize 63
5586 12:31:58.982307 [CA 4] Center 34 (4~65) winsize 62
5587 12:31:58.985187 [CA 5] Center 33 (3~64) winsize 62
5588 12:31:58.985413
5589 12:31:58.988521 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5590 12:31:58.988703
5591 12:31:58.992095 [CATrainingPosCal] consider 2 rank data
5592 12:31:58.994987 u2DelayCellTimex100 = 270/100 ps
5593 12:31:58.998580 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5594 12:31:59.001587 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 12:31:59.004960 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5596 12:31:59.008057 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5597 12:31:59.014694 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5598 12:31:59.018176 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 12:31:59.018266
5600 12:31:59.021035 CA PerBit enable=1, Macro0, CA PI delay=33
5601 12:31:59.021123
5602 12:31:59.024532 [CBTSetCACLKResult] CA Dly = 33
5603 12:31:59.024618 CS Dly: 6 (0~38)
5604 12:31:59.024687
5605 12:31:59.027992 ----->DramcWriteLeveling(PI) begin...
5606 12:31:59.030938 ==
5607 12:31:59.031047 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 12:31:59.037679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 12:31:59.037764 ==
5610 12:31:59.040983 Write leveling (Byte 0): 28 => 28
5611 12:31:59.044550 Write leveling (Byte 1): 29 => 29
5612 12:31:59.048014 DramcWriteLeveling(PI) end<-----
5613 12:31:59.048122
5614 12:31:59.048188 ==
5615 12:31:59.050927 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 12:31:59.054327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 12:31:59.054437 ==
5618 12:31:59.057839 [Gating] SW mode calibration
5619 12:31:59.064306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5620 12:31:59.071072 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5621 12:31:59.074186 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 12:31:59.077737 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 12:31:59.083708 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 12:31:59.087231 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 12:31:59.090778 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 12:31:59.097078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 12:31:59.100778 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5628 12:31:59.103722 0 14 28 | B1->B0 | 2d2d 2a2a | 1 0 | (1 0) (0 0)
5629 12:31:59.110305 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 12:31:59.113445 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 12:31:59.116993 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 12:31:59.123534 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 12:31:59.126998 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 12:31:59.129825 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 12:31:59.137214 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5636 12:31:59.140002 0 15 28 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
5637 12:31:59.143354 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 12:31:59.150020 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 12:31:59.153216 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 12:31:59.156202 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 12:31:59.163060 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 12:31:59.165953 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 12:31:59.169430 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5644 12:31:59.176093 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5645 12:31:59.179615 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:31:59.182698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:31:59.189091 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:31:59.192667 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:31:59.195582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:31:59.202112 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:31:59.205871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:31:59.208976 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:31:59.215578 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:31:59.218549 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:31:59.222039 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:31:59.228723 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:31:59.232368 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:31:59.235150 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:31:59.241715 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5660 12:31:59.245273 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 12:31:59.248521 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 12:31:59.251490 Total UI for P1: 0, mck2ui 16
5663 12:31:59.254863 best dqsien dly found for B0: ( 1, 2, 26)
5664 12:31:59.258294 Total UI for P1: 0, mck2ui 16
5665 12:31:59.261576 best dqsien dly found for B1: ( 1, 2, 26)
5666 12:31:59.265042 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5667 12:31:59.268094 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5668 12:31:59.271756
5669 12:31:59.274544 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5670 12:31:59.278341 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5671 12:31:59.281287 [Gating] SW calibration Done
5672 12:31:59.281727 ==
5673 12:31:59.284976 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 12:31:59.287928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 12:31:59.288406 ==
5676 12:31:59.288756 RX Vref Scan: 0
5677 12:31:59.291436
5678 12:31:59.291867 RX Vref 0 -> 0, step: 1
5679 12:31:59.292264
5680 12:31:59.294327 RX Delay -80 -> 252, step: 8
5681 12:31:59.297807 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5682 12:31:59.301287 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5683 12:31:59.307551 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5684 12:31:59.310946 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5685 12:31:59.314258 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5686 12:31:59.317291 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5687 12:31:59.320678 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5688 12:31:59.324062 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5689 12:31:59.330716 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5690 12:31:59.333711 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5691 12:31:59.337204 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5692 12:31:59.340002 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5693 12:31:59.343694 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5694 12:31:59.350076 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5695 12:31:59.353421 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5696 12:31:59.356308 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5697 12:31:59.356421 ==
5698 12:31:59.359593 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 12:31:59.363412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 12:31:59.363517 ==
5701 12:31:59.366324 DQS Delay:
5702 12:31:59.366426 DQS0 = 0, DQS1 = 0
5703 12:31:59.369769 DQM Delay:
5704 12:31:59.369874 DQM0 = 98, DQM1 = 92
5705 12:31:59.369979 DQ Delay:
5706 12:31:59.373237 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5707 12:31:59.376295 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5708 12:31:59.379808 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5709 12:31:59.382990 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5710 12:31:59.386038
5711 12:31:59.386121
5712 12:31:59.386187 ==
5713 12:31:59.389666 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:31:59.393165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:31:59.393249 ==
5716 12:31:59.393316
5717 12:31:59.393377
5718 12:31:59.396173 TX Vref Scan disable
5719 12:31:59.396282 == TX Byte 0 ==
5720 12:31:59.402688 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5721 12:31:59.406428 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5722 12:31:59.406540 == TX Byte 1 ==
5723 12:31:59.412841 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5724 12:31:59.415718 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5725 12:31:59.415837 ==
5726 12:31:59.419732 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 12:31:59.422543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 12:31:59.422659 ==
5729 12:31:59.422776
5730 12:31:59.422886
5731 12:31:59.426131 TX Vref Scan disable
5732 12:31:59.429210 == TX Byte 0 ==
5733 12:31:59.432608 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5734 12:31:59.435594 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5735 12:31:59.439802 == TX Byte 1 ==
5736 12:31:59.442624 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5737 12:31:59.446134 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5738 12:31:59.446739
5739 12:31:59.449600 [DATLAT]
5740 12:31:59.450154 Freq=933, CH1 RK0
5741 12:31:59.450636
5742 12:31:59.452700 DATLAT Default: 0xd
5743 12:31:59.453206 0, 0xFFFF, sum = 0
5744 12:31:59.456286 1, 0xFFFF, sum = 0
5745 12:31:59.456731 2, 0xFFFF, sum = 0
5746 12:31:59.459383 3, 0xFFFF, sum = 0
5747 12:31:59.459829 4, 0xFFFF, sum = 0
5748 12:31:59.462224 5, 0xFFFF, sum = 0
5749 12:31:59.462666 6, 0xFFFF, sum = 0
5750 12:31:59.465512 7, 0xFFFF, sum = 0
5751 12:31:59.469043 8, 0xFFFF, sum = 0
5752 12:31:59.469617 9, 0xFFFF, sum = 0
5753 12:31:59.472451 10, 0x0, sum = 1
5754 12:31:59.472897 11, 0x0, sum = 2
5755 12:31:59.473345 12, 0x0, sum = 3
5756 12:31:59.475897 13, 0x0, sum = 4
5757 12:31:59.476537 best_step = 11
5758 12:31:59.477064
5759 12:31:59.478836 ==
5760 12:31:59.479370 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 12:31:59.485621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 12:31:59.486064 ==
5763 12:31:59.486598 RX Vref Scan: 1
5764 12:31:59.487116
5765 12:31:59.488586 RX Vref 0 -> 0, step: 1
5766 12:31:59.489063
5767 12:31:59.492176 RX Delay -61 -> 252, step: 4
5768 12:31:59.492709
5769 12:31:59.495133 Set Vref, RX VrefLevel [Byte0]: 53
5770 12:31:59.498604 [Byte1]: 53
5771 12:31:59.499031
5772 12:31:59.502700 Final RX Vref Byte 0 = 53 to rank0
5773 12:31:59.505107 Final RX Vref Byte 1 = 53 to rank0
5774 12:31:59.508468 Final RX Vref Byte 0 = 53 to rank1
5775 12:31:59.511526 Final RX Vref Byte 1 = 53 to rank1==
5776 12:31:59.515016 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 12:31:59.518582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 12:31:59.521442 ==
5779 12:31:59.521882 DQS Delay:
5780 12:31:59.522320 DQS0 = 0, DQS1 = 0
5781 12:31:59.525134 DQM Delay:
5782 12:31:59.525572 DQM0 = 98, DQM1 = 95
5783 12:31:59.527988 DQ Delay:
5784 12:31:59.531548 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5785 12:31:59.534907 DQ4 =96, DQ5 =106, DQ6 =110, DQ7 =92
5786 12:31:59.537919 DQ8 =82, DQ9 =86, DQ10 =90, DQ11 =88
5787 12:31:59.541575 DQ12 =106, DQ13 =106, DQ14 =100, DQ15 =106
5788 12:31:59.542012
5789 12:31:59.542476
5790 12:31:59.548109 [DQSOSCAuto] RK0, (LSB)MR18= 0x211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 421 ps
5791 12:31:59.550949 CH1 RK0: MR19=505, MR18=211
5792 12:31:59.557726 CH1_RK0: MR19=0x505, MR18=0x211, DQSOSC=416, MR23=63, INC=62, DEC=41
5793 12:31:59.558152
5794 12:31:59.561021 ----->DramcWriteLeveling(PI) begin...
5795 12:31:59.561455 ==
5796 12:31:59.564515 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 12:31:59.567473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 12:31:59.567915 ==
5799 12:31:59.570738 Write leveling (Byte 0): 27 => 27
5800 12:31:59.574206 Write leveling (Byte 1): 27 => 27
5801 12:31:59.577702 DramcWriteLeveling(PI) end<-----
5802 12:31:59.578142
5803 12:31:59.578671 ==
5804 12:31:59.580510 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 12:31:59.587028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 12:31:59.587453 ==
5807 12:31:59.587797 [Gating] SW mode calibration
5808 12:31:59.597266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 12:31:59.600723 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 12:31:59.603577 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5811 12:31:59.610229 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 12:31:59.613824 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 12:31:59.619970 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 12:31:59.623435 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 12:31:59.626429 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5816 12:31:59.633409 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5817 12:31:59.636363 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5818 12:31:59.639872 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 12:31:59.646463 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 12:31:59.649322 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 12:31:59.653021 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 12:31:59.659457 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 12:31:59.662966 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 12:31:59.665673 0 15 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (1 1)
5825 12:31:59.671943 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5826 12:31:59.675689 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 12:31:59.678674 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 12:31:59.685492 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 12:31:59.688804 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 12:31:59.691760 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 12:31:59.698301 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 12:31:59.701892 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5833 12:31:59.704766 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5834 12:31:59.711811 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5835 12:31:59.714879 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 12:31:59.718215 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 12:31:59.724838 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:31:59.728456 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:31:59.731439 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:31:59.738174 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:31:59.741365 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:31:59.744880 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:31:59.751442 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:31:59.754479 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:31:59.757944 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:31:59.764367 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:31:59.767899 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:31:59.771339 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5849 12:31:59.777654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5850 12:31:59.781096 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 12:31:59.784134 Total UI for P1: 0, mck2ui 16
5852 12:31:59.787363 best dqsien dly found for B0: ( 1, 2, 26)
5853 12:31:59.790833 Total UI for P1: 0, mck2ui 16
5854 12:31:59.794391 best dqsien dly found for B1: ( 1, 2, 26)
5855 12:31:59.797314 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5856 12:31:59.800355 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5857 12:31:59.800756
5858 12:31:59.804017 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5859 12:31:59.807466 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5860 12:31:59.810879 [Gating] SW calibration Done
5861 12:31:59.811302 ==
5862 12:31:59.813945 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 12:31:59.820656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 12:31:59.821166 ==
5865 12:31:59.821509 RX Vref Scan: 0
5866 12:31:59.821827
5867 12:31:59.823525 RX Vref 0 -> 0, step: 1
5868 12:31:59.824071
5869 12:31:59.827202 RX Delay -80 -> 252, step: 8
5870 12:31:59.830176 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5871 12:31:59.833640 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5872 12:31:59.836480 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5873 12:31:59.839876 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5874 12:31:59.846768 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5875 12:31:59.849678 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5876 12:31:59.853438 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5877 12:31:59.856354 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5878 12:31:59.859943 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5879 12:31:59.862895 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5880 12:31:59.869927 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5881 12:31:59.872834 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5882 12:31:59.876145 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5883 12:31:59.879544 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5884 12:31:59.882902 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5885 12:31:59.889462 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5886 12:31:59.890149 ==
5887 12:31:59.892470 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 12:31:59.895899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 12:31:59.896583 ==
5890 12:31:59.897186 DQS Delay:
5891 12:31:59.898845 DQS0 = 0, DQS1 = 0
5892 12:31:59.899472 DQM Delay:
5893 12:31:59.902438 DQM0 = 96, DQM1 = 93
5894 12:31:59.903080 DQ Delay:
5895 12:31:59.905404 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5896 12:31:59.908919 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5897 12:31:59.911865 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5898 12:31:59.915355 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5899 12:31:59.915690
5900 12:31:59.915997
5901 12:31:59.916317 ==
5902 12:31:59.918825 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 12:31:59.924844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 12:31:59.925080 ==
5905 12:31:59.925293
5906 12:31:59.925499
5907 12:31:59.925704 TX Vref Scan disable
5908 12:31:59.928316 == TX Byte 0 ==
5909 12:31:59.931871 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5910 12:31:59.938392 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5911 12:31:59.938496 == TX Byte 1 ==
5912 12:31:59.941889 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5913 12:31:59.948135 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5914 12:31:59.948228 ==
5915 12:31:59.951800 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 12:31:59.954729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 12:31:59.954822 ==
5918 12:31:59.954897
5919 12:31:59.954965
5920 12:31:59.958363 TX Vref Scan disable
5921 12:31:59.958456 == TX Byte 0 ==
5922 12:31:59.965025 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5923 12:31:59.967894 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5924 12:31:59.971349 == TX Byte 1 ==
5925 12:31:59.975005 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 12:31:59.978000 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 12:31:59.978110
5928 12:31:59.978197 [DATLAT]
5929 12:31:59.981310 Freq=933, CH1 RK1
5930 12:31:59.981420
5931 12:31:59.981507 DATLAT Default: 0xb
5932 12:31:59.984874 0, 0xFFFF, sum = 0
5933 12:31:59.987661 1, 0xFFFF, sum = 0
5934 12:31:59.987796 2, 0xFFFF, sum = 0
5935 12:31:59.990933 3, 0xFFFF, sum = 0
5936 12:31:59.991068 4, 0xFFFF, sum = 0
5937 12:31:59.994439 5, 0xFFFF, sum = 0
5938 12:31:59.994589 6, 0xFFFF, sum = 0
5939 12:31:59.997840 7, 0xFFFF, sum = 0
5940 12:31:59.998009 8, 0xFFFF, sum = 0
5941 12:32:00.001160 9, 0xFFFF, sum = 0
5942 12:32:00.001437 10, 0x0, sum = 1
5943 12:32:00.004273 11, 0x0, sum = 2
5944 12:32:00.004468 12, 0x0, sum = 3
5945 12:32:00.007908 13, 0x0, sum = 4
5946 12:32:00.008220 best_step = 11
5947 12:32:00.008409
5948 12:32:00.008580 ==
5949 12:32:00.010964 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 12:32:00.014534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 12:32:00.014868 ==
5952 12:32:00.017540 RX Vref Scan: 0
5953 12:32:00.017921
5954 12:32:00.021158 RX Vref 0 -> 0, step: 1
5955 12:32:00.021521
5956 12:32:00.021817 RX Delay -61 -> 252, step: 4
5957 12:32:00.028992 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5958 12:32:00.032326 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5959 12:32:00.035337 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5960 12:32:00.038846 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5961 12:32:00.042291 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5962 12:32:00.048853 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5963 12:32:00.052202 iDelay=199, Bit 6, Center 106 (19 ~ 194) 176
5964 12:32:00.055202 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5965 12:32:00.058806 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5966 12:32:00.061924 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5967 12:32:00.065511 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5968 12:32:00.071447 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5969 12:32:00.074888 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5970 12:32:00.078533 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5971 12:32:00.081520 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5972 12:32:00.087973 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5973 12:32:00.088663 ==
5974 12:32:00.091371 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 12:32:00.094835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 12:32:00.095262 ==
5977 12:32:00.095602 DQS Delay:
5978 12:32:00.098136 DQS0 = 0, DQS1 = 0
5979 12:32:00.098562 DQM Delay:
5980 12:32:00.101081 DQM0 = 97, DQM1 = 95
5981 12:32:00.101463 DQ Delay:
5982 12:32:00.104433 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5983 12:32:00.107925 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =94
5984 12:32:00.111008 DQ8 =84, DQ9 =86, DQ10 =94, DQ11 =88
5985 12:32:00.114537 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =104
5986 12:32:00.114959
5987 12:32:00.115292
5988 12:32:00.124187 [DQSOSCAuto] RK1, (LSB)MR18= 0xe25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5989 12:32:00.127397 CH1 RK1: MR19=505, MR18=E25
5990 12:32:00.130718 CH1_RK1: MR19=0x505, MR18=0xE25, DQSOSC=410, MR23=63, INC=64, DEC=42
5991 12:32:00.134337 [RxdqsGatingPostProcess] freq 933
5992 12:32:00.140651 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5993 12:32:00.144275 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 12:32:00.147070 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 12:32:00.150757 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 12:32:00.153559 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 12:32:00.157148 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 12:32:00.160563 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 12:32:00.163476 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 12:32:00.166893 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 12:32:00.169916 Pre-setting of DQS Precalculation
6002 12:32:00.173407 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6003 12:32:00.179874 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6004 12:32:00.186370 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6005 12:32:00.189708
6006 12:32:00.189950
6007 12:32:00.190165 [Calibration Summary] 1866 Mbps
6008 12:32:00.193178 CH 0, Rank 0
6009 12:32:00.193405 SW Impedance : PASS
6010 12:32:00.196367 DUTY Scan : NO K
6011 12:32:00.199213 ZQ Calibration : PASS
6012 12:32:00.199322 Jitter Meter : NO K
6013 12:32:00.202889 CBT Training : PASS
6014 12:32:00.206333 Write leveling : PASS
6015 12:32:00.206774 RX DQS gating : PASS
6016 12:32:00.209812 RX DQ/DQS(RDDQC) : PASS
6017 12:32:00.213195 TX DQ/DQS : PASS
6018 12:32:00.213625 RX DATLAT : PASS
6019 12:32:00.216098 RX DQ/DQS(Engine): PASS
6020 12:32:00.219743 TX OE : NO K
6021 12:32:00.220210 All Pass.
6022 12:32:00.220560
6023 12:32:00.220876 CH 0, Rank 1
6024 12:32:00.222837 SW Impedance : PASS
6025 12:32:00.225895 DUTY Scan : NO K
6026 12:32:00.226321 ZQ Calibration : PASS
6027 12:32:00.229479 Jitter Meter : NO K
6028 12:32:00.233236 CBT Training : PASS
6029 12:32:00.233660 Write leveling : PASS
6030 12:32:00.236129 RX DQS gating : PASS
6031 12:32:00.239669 RX DQ/DQS(RDDQC) : PASS
6032 12:32:00.240118 TX DQ/DQS : PASS
6033 12:32:00.242648 RX DATLAT : PASS
6034 12:32:00.245982 RX DQ/DQS(Engine): PASS
6035 12:32:00.246405 TX OE : NO K
6036 12:32:00.246940 All Pass.
6037 12:32:00.248930
6038 12:32:00.249232 CH 1, Rank 0
6039 12:32:00.252398 SW Impedance : PASS
6040 12:32:00.252698 DUTY Scan : NO K
6041 12:32:00.255891 ZQ Calibration : PASS
6042 12:32:00.258821 Jitter Meter : NO K
6043 12:32:00.259123 CBT Training : PASS
6044 12:32:00.262258 Write leveling : PASS
6045 12:32:00.262565 RX DQS gating : PASS
6046 12:32:00.265874 RX DQ/DQS(RDDQC) : PASS
6047 12:32:00.268920 TX DQ/DQS : PASS
6048 12:32:00.269222 RX DATLAT : PASS
6049 12:32:00.272337 RX DQ/DQS(Engine): PASS
6050 12:32:00.275324 TX OE : NO K
6051 12:32:00.275630 All Pass.
6052 12:32:00.275877
6053 12:32:00.276135 CH 1, Rank 1
6054 12:32:00.278875 SW Impedance : PASS
6055 12:32:00.282305 DUTY Scan : NO K
6056 12:32:00.282623 ZQ Calibration : PASS
6057 12:32:00.285082 Jitter Meter : NO K
6058 12:32:00.288824 CBT Training : PASS
6059 12:32:00.289391 Write leveling : PASS
6060 12:32:00.291752 RX DQS gating : PASS
6061 12:32:00.295290 RX DQ/DQS(RDDQC) : PASS
6062 12:32:00.295776 TX DQ/DQS : PASS
6063 12:32:00.298803 RX DATLAT : PASS
6064 12:32:00.302158 RX DQ/DQS(Engine): PASS
6065 12:32:00.302582 TX OE : NO K
6066 12:32:00.305436 All Pass.
6067 12:32:00.305865
6068 12:32:00.306208 DramC Write-DBI off
6069 12:32:00.308177 PER_BANK_REFRESH: Hybrid Mode
6070 12:32:00.311655 TX_TRACKING: ON
6071 12:32:00.318465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6072 12:32:00.321990 [FAST_K] Save calibration result to emmc
6073 12:32:00.324827 dramc_set_vcore_voltage set vcore to 650000
6074 12:32:00.328296 Read voltage for 400, 6
6075 12:32:00.328525 Vio18 = 0
6076 12:32:00.331244 Vcore = 650000
6077 12:32:00.331472 Vdram = 0
6078 12:32:00.331657 Vddq = 0
6079 12:32:00.334923 Vmddr = 0
6080 12:32:00.337841 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6081 12:32:00.344316 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6082 12:32:00.344500 MEM_TYPE=3, freq_sel=20
6083 12:32:00.347679 sv_algorithm_assistance_LP4_800
6084 12:32:00.354632 ============ PULL DRAM RESETB DOWN ============
6085 12:32:00.357631 ========== PULL DRAM RESETB DOWN end =========
6086 12:32:00.361069 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6087 12:32:00.364117 ===================================
6088 12:32:00.367709 LPDDR4 DRAM CONFIGURATION
6089 12:32:00.370884 ===================================
6090 12:32:00.374459 EX_ROW_EN[0] = 0x0
6091 12:32:00.374646 EX_ROW_EN[1] = 0x0
6092 12:32:00.377473 LP4Y_EN = 0x0
6093 12:32:00.377689 WORK_FSP = 0x0
6094 12:32:00.380365 WL = 0x2
6095 12:32:00.380581 RL = 0x2
6096 12:32:00.383985 BL = 0x2
6097 12:32:00.384230 RPST = 0x0
6098 12:32:00.387445 RD_PRE = 0x0
6099 12:32:00.387663 WR_PRE = 0x1
6100 12:32:00.390257 WR_PST = 0x0
6101 12:32:00.390473 DBI_WR = 0x0
6102 12:32:00.394047 DBI_RD = 0x0
6103 12:32:00.394263 OTF = 0x1
6104 12:32:00.396988 ===================================
6105 12:32:00.400469 ===================================
6106 12:32:00.403772 ANA top config
6107 12:32:00.407233 ===================================
6108 12:32:00.410312 DLL_ASYNC_EN = 0
6109 12:32:00.410600 ALL_SLAVE_EN = 1
6110 12:32:00.413827 NEW_RANK_MODE = 1
6111 12:32:00.417103 DLL_IDLE_MODE = 1
6112 12:32:00.420751 LP45_APHY_COMB_EN = 1
6113 12:32:00.423497 TX_ODT_DIS = 1
6114 12:32:00.423917 NEW_8X_MODE = 1
6115 12:32:00.427082 ===================================
6116 12:32:00.430032 ===================================
6117 12:32:00.433692 data_rate = 800
6118 12:32:00.436695 CKR = 1
6119 12:32:00.440141 DQ_P2S_RATIO = 4
6120 12:32:00.443155 ===================================
6121 12:32:00.446738 CA_P2S_RATIO = 4
6122 12:32:00.449724 DQ_CA_OPEN = 0
6123 12:32:00.453343 DQ_SEMI_OPEN = 1
6124 12:32:00.453766 CA_SEMI_OPEN = 1
6125 12:32:00.456868 CA_FULL_RATE = 0
6126 12:32:00.459852 DQ_CKDIV4_EN = 0
6127 12:32:00.462747 CA_CKDIV4_EN = 1
6128 12:32:00.466176 CA_PREDIV_EN = 0
6129 12:32:00.469659 PH8_DLY = 0
6130 12:32:00.469841 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6131 12:32:00.472579 DQ_AAMCK_DIV = 0
6132 12:32:00.476166 CA_AAMCK_DIV = 0
6133 12:32:00.479220 CA_ADMCK_DIV = 4
6134 12:32:00.482833 DQ_TRACK_CA_EN = 0
6135 12:32:00.485779 CA_PICK = 800
6136 12:32:00.489259 CA_MCKIO = 400
6137 12:32:00.489413 MCKIO_SEMI = 400
6138 12:32:00.492268 PLL_FREQ = 3016
6139 12:32:00.495644 DQ_UI_PI_RATIO = 32
6140 12:32:00.499469 CA_UI_PI_RATIO = 32
6141 12:32:00.502594 ===================================
6142 12:32:00.505698 ===================================
6143 12:32:00.508885 memory_type:LPDDR4
6144 12:32:00.509311 GP_NUM : 10
6145 12:32:00.512653 SRAM_EN : 1
6146 12:32:00.515981 MD32_EN : 0
6147 12:32:00.518884 ===================================
6148 12:32:00.519530 [ANA_INIT] >>>>>>>>>>>>>>
6149 12:32:00.522403 <<<<<< [CONFIGURE PHASE]: ANA_TX
6150 12:32:00.525875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6151 12:32:00.529112 ===================================
6152 12:32:00.532265 data_rate = 800,PCW = 0X7400
6153 12:32:00.535931 ===================================
6154 12:32:00.538818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6155 12:32:00.545771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 12:32:00.555878 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 12:32:00.562461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6158 12:32:00.565521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6159 12:32:00.568300 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6160 12:32:00.568752 [ANA_INIT] flow start
6161 12:32:00.571818 [ANA_INIT] PLL >>>>>>>>
6162 12:32:00.575186 [ANA_INIT] PLL <<<<<<<<
6163 12:32:00.575839 [ANA_INIT] MIDPI >>>>>>>>
6164 12:32:00.578207 [ANA_INIT] MIDPI <<<<<<<<
6165 12:32:00.581769 [ANA_INIT] DLL >>>>>>>>
6166 12:32:00.582449 [ANA_INIT] flow end
6167 12:32:00.588339 ============ LP4 DIFF to SE enter ============
6168 12:32:00.591217 ============ LP4 DIFF to SE exit ============
6169 12:32:00.594504 [ANA_INIT] <<<<<<<<<<<<<
6170 12:32:00.597828 [Flow] Enable top DCM control >>>>>
6171 12:32:00.601344 [Flow] Enable top DCM control <<<<<
6172 12:32:00.604234 Enable DLL master slave shuffle
6173 12:32:00.607732 ==============================================================
6174 12:32:00.610539 Gating Mode config
6175 12:32:00.617369 ==============================================================
6176 12:32:00.617550 Config description:
6177 12:32:00.627191 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6178 12:32:00.634051 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6179 12:32:00.637021 SELPH_MODE 0: By rank 1: By Phase
6180 12:32:00.643693 ==============================================================
6181 12:32:00.646804 GAT_TRACK_EN = 0
6182 12:32:00.650331 RX_GATING_MODE = 2
6183 12:32:00.653882 RX_GATING_TRACK_MODE = 2
6184 12:32:00.656756 SELPH_MODE = 1
6185 12:32:00.660255 PICG_EARLY_EN = 1
6186 12:32:00.663301 VALID_LAT_VALUE = 1
6187 12:32:00.666957 ==============================================================
6188 12:32:00.669942 Enter into Gating configuration >>>>
6189 12:32:00.673530 Exit from Gating configuration <<<<
6190 12:32:00.676488 Enter into DVFS_PRE_config >>>>>
6191 12:32:00.689844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6192 12:32:00.693488 Exit from DVFS_PRE_config <<<<<
6193 12:32:00.696907 Enter into PICG configuration >>>>
6194 12:32:00.699789 Exit from PICG configuration <<<<
6195 12:32:00.700378 [RX_INPUT] configuration >>>>>
6196 12:32:00.703243 [RX_INPUT] configuration <<<<<
6197 12:32:00.709998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6198 12:32:00.713533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6199 12:32:00.719857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 12:32:00.726361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 12:32:00.733051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 12:32:00.739512 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 12:32:00.742545 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6204 12:32:00.746053 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6205 12:32:00.752735 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6206 12:32:00.756198 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6207 12:32:00.759016 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6208 12:32:00.765897 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6209 12:32:00.769048 ===================================
6210 12:32:00.769606 LPDDR4 DRAM CONFIGURATION
6211 12:32:00.772670 ===================================
6212 12:32:00.775655 EX_ROW_EN[0] = 0x0
6213 12:32:00.776111 EX_ROW_EN[1] = 0x0
6214 12:32:00.779146 LP4Y_EN = 0x0
6215 12:32:00.779228 WORK_FSP = 0x0
6216 12:32:00.781789 WL = 0x2
6217 12:32:00.785314 RL = 0x2
6218 12:32:00.785396 BL = 0x2
6219 12:32:00.788269 RPST = 0x0
6220 12:32:00.788350 RD_PRE = 0x0
6221 12:32:00.791845 WR_PRE = 0x1
6222 12:32:00.791927 WR_PST = 0x0
6223 12:32:00.794962 DBI_WR = 0x0
6224 12:32:00.795044 DBI_RD = 0x0
6225 12:32:00.798252 OTF = 0x1
6226 12:32:00.801871 ===================================
6227 12:32:00.804766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6228 12:32:00.808192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6229 12:32:00.814630 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 12:32:00.818137 ===================================
6231 12:32:00.818240 LPDDR4 DRAM CONFIGURATION
6232 12:32:00.820995 ===================================
6233 12:32:00.824542 EX_ROW_EN[0] = 0x10
6234 12:32:00.827969 EX_ROW_EN[1] = 0x0
6235 12:32:00.828080 LP4Y_EN = 0x0
6236 12:32:00.830913 WORK_FSP = 0x0
6237 12:32:00.830995 WL = 0x2
6238 12:32:00.834214 RL = 0x2
6239 12:32:00.834296 BL = 0x2
6240 12:32:00.837600 RPST = 0x0
6241 12:32:00.837683 RD_PRE = 0x0
6242 12:32:00.841032 WR_PRE = 0x1
6243 12:32:00.841115 WR_PST = 0x0
6244 12:32:00.843987 DBI_WR = 0x0
6245 12:32:00.844120 DBI_RD = 0x0
6246 12:32:00.847544 OTF = 0x1
6247 12:32:00.850417 ===================================
6248 12:32:00.856998 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6249 12:32:00.860493 nWR fixed to 30
6250 12:32:00.863953 [ModeRegInit_LP4] CH0 RK0
6251 12:32:00.864088 [ModeRegInit_LP4] CH0 RK1
6252 12:32:00.866893 [ModeRegInit_LP4] CH1 RK0
6253 12:32:00.870520 [ModeRegInit_LP4] CH1 RK1
6254 12:32:00.870618 match AC timing 19
6255 12:32:00.877051 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6256 12:32:00.880067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6257 12:32:00.883609 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6258 12:32:00.890012 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6259 12:32:00.893643 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6260 12:32:00.893744 ==
6261 12:32:00.896724 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 12:32:00.900260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 12:32:00.900334 ==
6264 12:32:00.906680 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 12:32:00.913158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6266 12:32:00.916694 [CA 0] Center 36 (8~64) winsize 57
6267 12:32:00.919627 [CA 1] Center 36 (8~64) winsize 57
6268 12:32:00.923191 [CA 2] Center 36 (8~64) winsize 57
6269 12:32:00.926663 [CA 3] Center 36 (8~64) winsize 57
6270 12:32:00.926745 [CA 4] Center 36 (8~64) winsize 57
6271 12:32:00.929592 [CA 5] Center 36 (8~64) winsize 57
6272 12:32:00.929674
6273 12:32:00.935956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6274 12:32:00.936049
6275 12:32:00.939387 [CATrainingPosCal] consider 1 rank data
6276 12:32:00.942836 u2DelayCellTimex100 = 270/100 ps
6277 12:32:00.946364 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:32:00.949386 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:32:00.952869 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:32:00.955835 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:32:00.959406 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:32:00.962797 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:32:00.962880
6284 12:32:00.965774 CA PerBit enable=1, Macro0, CA PI delay=36
6285 12:32:00.965857
6286 12:32:00.969182 [CBTSetCACLKResult] CA Dly = 36
6287 12:32:00.972221 CS Dly: 1 (0~32)
6288 12:32:00.972304 ==
6289 12:32:00.975884 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 12:32:00.978847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 12:32:00.978931 ==
6292 12:32:00.985620 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6293 12:32:00.992354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6294 12:32:00.995436 [CA 0] Center 36 (8~64) winsize 57
6295 12:32:00.998969 [CA 1] Center 36 (8~64) winsize 57
6296 12:32:01.002357 [CA 2] Center 36 (8~64) winsize 57
6297 12:32:01.005965 [CA 3] Center 36 (8~64) winsize 57
6298 12:32:01.006157 [CA 4] Center 36 (8~64) winsize 57
6299 12:32:01.008927 [CA 5] Center 36 (8~64) winsize 57
6300 12:32:01.009145
6301 12:32:01.015567 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6302 12:32:01.015778
6303 12:32:01.018338 [CATrainingPosCal] consider 2 rank data
6304 12:32:01.022181 u2DelayCellTimex100 = 270/100 ps
6305 12:32:01.025132 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 12:32:01.028535 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 12:32:01.031926 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 12:32:01.034825 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 12:32:01.038292 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 12:32:01.041829 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 12:32:01.042133
6312 12:32:01.045244 CA PerBit enable=1, Macro0, CA PI delay=36
6313 12:32:01.045639
6314 12:32:01.048583 [CBTSetCACLKResult] CA Dly = 36
6315 12:32:01.051456 CS Dly: 1 (0~32)
6316 12:32:01.051878
6317 12:32:01.055223 ----->DramcWriteLeveling(PI) begin...
6318 12:32:01.055772 ==
6319 12:32:01.058077 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 12:32:01.061595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 12:32:01.062021 ==
6322 12:32:01.064439 Write leveling (Byte 0): 40 => 8
6323 12:32:01.068118 Write leveling (Byte 1): 40 => 8
6324 12:32:01.071527 DramcWriteLeveling(PI) end<-----
6325 12:32:01.071953
6326 12:32:01.072323 ==
6327 12:32:01.074625 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 12:32:01.078174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 12:32:01.078630 ==
6330 12:32:01.081057 [Gating] SW mode calibration
6331 12:32:01.087910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6332 12:32:01.095000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6333 12:32:01.097589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 12:32:01.104165 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 12:32:01.107675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 12:32:01.110591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 12:32:01.117262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 12:32:01.120879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 12:32:01.124307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 12:32:01.131040 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 12:32:01.133845 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 12:32:01.137378 Total UI for P1: 0, mck2ui 16
6343 12:32:01.140781 best dqsien dly found for B0: ( 0, 14, 24)
6344 12:32:01.144244 Total UI for P1: 0, mck2ui 16
6345 12:32:01.146898 best dqsien dly found for B1: ( 0, 14, 24)
6346 12:32:01.150208 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6347 12:32:01.153572 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6348 12:32:01.154010
6349 12:32:01.157164 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 12:32:01.160093 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 12:32:01.163611 [Gating] SW calibration Done
6352 12:32:01.164102 ==
6353 12:32:01.167082 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 12:32:01.173616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 12:32:01.174202 ==
6356 12:32:01.174556 RX Vref Scan: 0
6357 12:32:01.174882
6358 12:32:01.176528 RX Vref 0 -> 0, step: 1
6359 12:32:01.176958
6360 12:32:01.180139 RX Delay -410 -> 252, step: 16
6361 12:32:01.183065 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6362 12:32:01.186626 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6363 12:32:01.192776 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6364 12:32:01.196141 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6365 12:32:01.199287 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6366 12:32:01.202861 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6367 12:32:01.209403 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6368 12:32:01.212399 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6369 12:32:01.216123 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6370 12:32:01.219087 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6371 12:32:01.225559 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6372 12:32:01.229340 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6373 12:32:01.232709 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6374 12:32:01.239513 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6375 12:32:01.242089 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6376 12:32:01.245648 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6377 12:32:01.246145 ==
6378 12:32:01.249139 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 12:32:01.255621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 12:32:01.256235 ==
6381 12:32:01.256582 DQS Delay:
6382 12:32:01.258390 DQS0 = 35, DQS1 = 51
6383 12:32:01.258801 DQM Delay:
6384 12:32:01.259128 DQM0 = 4, DQM1 = 11
6385 12:32:01.261984 DQ Delay:
6386 12:32:01.265459 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6387 12:32:01.265873 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6388 12:32:01.268504 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6389 12:32:01.271599 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6390 12:32:01.272013
6391 12:32:01.272576
6392 12:32:01.275068 ==
6393 12:32:01.278528 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:32:01.281443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:32:01.281860 ==
6396 12:32:01.282214
6397 12:32:01.282518
6398 12:32:01.285013 TX Vref Scan disable
6399 12:32:01.285426 == TX Byte 0 ==
6400 12:32:01.288072 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 12:32:01.294881 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 12:32:01.295294 == TX Byte 1 ==
6403 12:32:01.297955 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 12:32:01.304353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 12:32:01.304766 ==
6406 12:32:01.307960 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 12:32:01.311345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 12:32:01.311758 ==
6409 12:32:01.312135
6410 12:32:01.312446
6411 12:32:01.314346 TX Vref Scan disable
6412 12:32:01.314776 == TX Byte 0 ==
6413 12:32:01.317939 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 12:32:01.324341 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 12:32:01.324755 == TX Byte 1 ==
6416 12:32:01.327934 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 12:32:01.334626 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 12:32:01.335170
6419 12:32:01.335508 [DATLAT]
6420 12:32:01.337490 Freq=400, CH0 RK0
6421 12:32:01.337902
6422 12:32:01.338230 DATLAT Default: 0xf
6423 12:32:01.341010 0, 0xFFFF, sum = 0
6424 12:32:01.341440 1, 0xFFFF, sum = 0
6425 12:32:01.344540 2, 0xFFFF, sum = 0
6426 12:32:01.344996 3, 0xFFFF, sum = 0
6427 12:32:01.347723 4, 0xFFFF, sum = 0
6428 12:32:01.348190 5, 0xFFFF, sum = 0
6429 12:32:01.350789 6, 0xFFFF, sum = 0
6430 12:32:01.351217 7, 0xFFFF, sum = 0
6431 12:32:01.354196 8, 0xFFFF, sum = 0
6432 12:32:01.354650 9, 0xFFFF, sum = 0
6433 12:32:01.357217 10, 0xFFFF, sum = 0
6434 12:32:01.357668 11, 0xFFFF, sum = 0
6435 12:32:01.360698 12, 0xFFFF, sum = 0
6436 12:32:01.361131 13, 0x0, sum = 1
6437 12:32:01.364094 14, 0x0, sum = 2
6438 12:32:01.364524 15, 0x0, sum = 3
6439 12:32:01.367274 16, 0x0, sum = 4
6440 12:32:01.367705 best_step = 14
6441 12:32:01.368075
6442 12:32:01.368402 ==
6443 12:32:01.370921 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 12:32:01.377134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 12:32:01.377558 ==
6446 12:32:01.377917 RX Vref Scan: 1
6447 12:32:01.378238
6448 12:32:01.380628 RX Vref 0 -> 0, step: 1
6449 12:32:01.381050
6450 12:32:01.383549 RX Delay -343 -> 252, step: 8
6451 12:32:01.384024
6452 12:32:01.387072 Set Vref, RX VrefLevel [Byte0]: 52
6453 12:32:01.390219 [Byte1]: 59
6454 12:32:01.393790
6455 12:32:01.394228 Final RX Vref Byte 0 = 52 to rank0
6456 12:32:01.397344 Final RX Vref Byte 1 = 59 to rank0
6457 12:32:01.400225 Final RX Vref Byte 0 = 52 to rank1
6458 12:32:01.403810 Final RX Vref Byte 1 = 59 to rank1==
6459 12:32:01.406796 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 12:32:01.413699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 12:32:01.414259 ==
6462 12:32:01.414632 DQS Delay:
6463 12:32:01.417041 DQS0 = 44, DQS1 = 60
6464 12:32:01.417474 DQM Delay:
6465 12:32:01.417816 DQM0 = 10, DQM1 = 16
6466 12:32:01.419979 DQ Delay:
6467 12:32:01.423628 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6468 12:32:01.426599 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6469 12:32:01.430263 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6470 12:32:01.433298 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6471 12:32:01.433728
6472 12:32:01.434146
6473 12:32:01.440204 [DQSOSCAuto] RK0, (LSB)MR18= 0x877b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
6474 12:32:01.443329 CH0 RK0: MR19=C0C, MR18=877B
6475 12:32:01.449819 CH0_RK0: MR19=0xC0C, MR18=0x877B, DQSOSC=392, MR23=63, INC=384, DEC=256
6476 12:32:01.450112 ==
6477 12:32:01.452994 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 12:32:01.455936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 12:32:01.456025 ==
6480 12:32:01.459411 [Gating] SW mode calibration
6481 12:32:01.465694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6482 12:32:01.472909 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6483 12:32:01.476298 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 12:32:01.479153 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 12:32:01.486172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 12:32:01.489009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 12:32:01.492685 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 12:32:01.499190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 12:32:01.502025 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 12:32:01.505927 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 12:32:01.512450 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 12:32:01.515294 Total UI for P1: 0, mck2ui 16
6493 12:32:01.518917 best dqsien dly found for B0: ( 0, 14, 24)
6494 12:32:01.522146 Total UI for P1: 0, mck2ui 16
6495 12:32:01.525665 best dqsien dly found for B1: ( 0, 14, 24)
6496 12:32:01.528696 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6497 12:32:01.532451 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6498 12:32:01.532988
6499 12:32:01.535296 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 12:32:01.538870 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 12:32:01.541969 [Gating] SW calibration Done
6502 12:32:01.542506 ==
6503 12:32:01.545355 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 12:32:01.548479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 12:32:01.551901 ==
6506 12:32:01.552371 RX Vref Scan: 0
6507 12:32:01.552713
6508 12:32:01.554819 RX Vref 0 -> 0, step: 1
6509 12:32:01.555240
6510 12:32:01.558035 RX Delay -410 -> 252, step: 16
6511 12:32:01.561773 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6512 12:32:01.565078 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6513 12:32:01.568447 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6514 12:32:01.574830 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6515 12:32:01.578087 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6516 12:32:01.581749 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6517 12:32:01.584274 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6518 12:32:01.591070 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6519 12:32:01.594550 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6520 12:32:01.597416 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6521 12:32:01.604453 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6522 12:32:01.607484 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6523 12:32:01.611137 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6524 12:32:01.614139 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6525 12:32:01.620686 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6526 12:32:01.624108 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6527 12:32:01.624537 ==
6528 12:32:01.627507 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 12:32:01.630469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 12:32:01.630899 ==
6531 12:32:01.634044 DQS Delay:
6532 12:32:01.634517 DQS0 = 35, DQS1 = 59
6533 12:32:01.637173 DQM Delay:
6534 12:32:01.637596 DQM0 = 7, DQM1 = 16
6535 12:32:01.637939 DQ Delay:
6536 12:32:01.640731 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6537 12:32:01.643669 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6538 12:32:01.647551 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6539 12:32:01.650184 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6540 12:32:01.650611
6541 12:32:01.650953
6542 12:32:01.651268 ==
6543 12:32:01.653762 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:32:01.660485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:32:01.661007 ==
6546 12:32:01.661351
6547 12:32:01.661664
6548 12:32:01.661967 TX Vref Scan disable
6549 12:32:01.663762 == TX Byte 0 ==
6550 12:32:01.666746 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6551 12:32:01.670214 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6552 12:32:01.673726 == TX Byte 1 ==
6553 12:32:01.676527 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6554 12:32:01.680131 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6555 12:32:01.680560 ==
6556 12:32:01.683466 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 12:32:01.690028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 12:32:01.690573 ==
6559 12:32:01.690919
6560 12:32:01.691236
6561 12:32:01.691536 TX Vref Scan disable
6562 12:32:01.693041 == TX Byte 0 ==
6563 12:32:01.696515 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6564 12:32:01.699434 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6565 12:32:01.702993 == TX Byte 1 ==
6566 12:32:01.706654 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6567 12:32:01.709644 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6568 12:32:01.710071
6569 12:32:01.713247 [DATLAT]
6570 12:32:01.713668 Freq=400, CH0 RK1
6571 12:32:01.714013
6572 12:32:01.716346 DATLAT Default: 0xe
6573 12:32:01.716767 0, 0xFFFF, sum = 0
6574 12:32:01.719358 1, 0xFFFF, sum = 0
6575 12:32:01.719787 2, 0xFFFF, sum = 0
6576 12:32:01.722864 3, 0xFFFF, sum = 0
6577 12:32:01.723296 4, 0xFFFF, sum = 0
6578 12:32:01.725881 5, 0xFFFF, sum = 0
6579 12:32:01.729443 6, 0xFFFF, sum = 0
6580 12:32:01.729871 7, 0xFFFF, sum = 0
6581 12:32:01.732372 8, 0xFFFF, sum = 0
6582 12:32:01.732804 9, 0xFFFF, sum = 0
6583 12:32:01.735957 10, 0xFFFF, sum = 0
6584 12:32:01.736433 11, 0xFFFF, sum = 0
6585 12:32:01.738919 12, 0xFFFF, sum = 0
6586 12:32:01.739350 13, 0x0, sum = 1
6587 12:32:01.742712 14, 0x0, sum = 2
6588 12:32:01.743142 15, 0x0, sum = 3
6589 12:32:01.745697 16, 0x0, sum = 4
6590 12:32:01.746128 best_step = 14
6591 12:32:01.746468
6592 12:32:01.746785 ==
6593 12:32:01.749306 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 12:32:01.752182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 12:32:01.755657 ==
6596 12:32:01.756108 RX Vref Scan: 0
6597 12:32:01.756454
6598 12:32:01.758614 RX Vref 0 -> 0, step: 1
6599 12:32:01.759039
6600 12:32:01.762409 RX Delay -359 -> 252, step: 8
6601 12:32:01.768500 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6602 12:32:01.772175 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6603 12:32:01.775662 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6604 12:32:01.778835 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6605 12:32:01.785114 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6606 12:32:01.788773 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6607 12:32:01.791775 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6608 12:32:01.795445 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6609 12:32:01.801935 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6610 12:32:01.804889 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6611 12:32:01.808439 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6612 12:32:01.811409 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6613 12:32:01.818002 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6614 12:32:01.821424 iDelay=209, Bit 13, Center -40 (-287 ~ 208) 496
6615 12:32:01.824424 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6616 12:32:01.830896 iDelay=209, Bit 15, Center -40 (-287 ~ 208) 496
6617 12:32:01.831340 ==
6618 12:32:01.834488 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 12:32:01.838042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 12:32:01.838477 ==
6621 12:32:01.838855 DQS Delay:
6622 12:32:01.840921 DQS0 = 44, DQS1 = 60
6623 12:32:01.841387 DQM Delay:
6624 12:32:01.844595 DQM0 = 9, DQM1 = 15
6625 12:32:01.845025 DQ Delay:
6626 12:32:01.847709 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6627 12:32:01.850656 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6628 12:32:01.854183 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6629 12:32:01.857752 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6630 12:32:01.858175
6631 12:32:01.858532
6632 12:32:01.863871 [DQSOSCAuto] RK1, (LSB)MR18= 0x857e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6633 12:32:01.867453 CH0 RK1: MR19=C0C, MR18=857E
6634 12:32:01.873887 CH0_RK1: MR19=0xC0C, MR18=0x857E, DQSOSC=393, MR23=63, INC=382, DEC=254
6635 12:32:01.877416 [RxdqsGatingPostProcess] freq 400
6636 12:32:01.883548 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6637 12:32:01.887038 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 12:32:01.890351 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 12:32:01.893866 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 12:32:01.897331 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 12:32:01.897902 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 12:32:01.899896 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 12:32:01.903419 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 12:32:01.906957 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 12:32:01.909951 Pre-setting of DQS Precalculation
6646 12:32:01.916942 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6647 12:32:01.917423 ==
6648 12:32:01.919967 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 12:32:01.922882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 12:32:01.923320 ==
6651 12:32:01.929510 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 12:32:01.935797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6653 12:32:01.939224 [CA 0] Center 36 (8~64) winsize 57
6654 12:32:01.942805 [CA 1] Center 36 (8~64) winsize 57
6655 12:32:01.942882 [CA 2] Center 36 (8~64) winsize 57
6656 12:32:01.945560 [CA 3] Center 36 (8~64) winsize 57
6657 12:32:01.949129 [CA 4] Center 36 (8~64) winsize 57
6658 12:32:01.952658 [CA 5] Center 36 (8~64) winsize 57
6659 12:32:01.952732
6660 12:32:01.958715 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6661 12:32:01.958792
6662 12:32:01.962086 [CATrainingPosCal] consider 1 rank data
6663 12:32:01.965589 u2DelayCellTimex100 = 270/100 ps
6664 12:32:01.968938 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:32:01.971948 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:32:01.975317 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:32:01.978677 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:32:01.982186 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:32:01.985150 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:32:01.985224
6671 12:32:01.988564 CA PerBit enable=1, Macro0, CA PI delay=36
6672 12:32:01.988645
6673 12:32:01.992144 [CBTSetCACLKResult] CA Dly = 36
6674 12:32:01.995471 CS Dly: 1 (0~32)
6675 12:32:01.995541 ==
6676 12:32:01.998265 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 12:32:02.001802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 12:32:02.001876 ==
6679 12:32:02.008611 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6680 12:32:02.015219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6681 12:32:02.018082 [CA 0] Center 36 (8~64) winsize 57
6682 12:32:02.018157 [CA 1] Center 36 (8~64) winsize 57
6683 12:32:02.021714 [CA 2] Center 36 (8~64) winsize 57
6684 12:32:02.024740 [CA 3] Center 36 (8~64) winsize 57
6685 12:32:02.028637 [CA 4] Center 36 (8~64) winsize 57
6686 12:32:02.031897 [CA 5] Center 36 (8~64) winsize 57
6687 12:32:02.032097
6688 12:32:02.034714 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6689 12:32:02.034859
6690 12:32:02.041375 [CATrainingPosCal] consider 2 rank data
6691 12:32:02.041458 u2DelayCellTimex100 = 270/100 ps
6692 12:32:02.047918 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 12:32:02.051175 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 12:32:02.054964 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 12:32:02.057806 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 12:32:02.061431 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 12:32:02.065129 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 12:32:02.065654
6699 12:32:02.068221 CA PerBit enable=1, Macro0, CA PI delay=36
6700 12:32:02.068743
6701 12:32:02.071019 [CBTSetCACLKResult] CA Dly = 36
6702 12:32:02.074569 CS Dly: 1 (0~32)
6703 12:32:02.074992
6704 12:32:02.078398 ----->DramcWriteLeveling(PI) begin...
6705 12:32:02.078931 ==
6706 12:32:02.080988 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 12:32:02.084217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 12:32:02.084663 ==
6709 12:32:02.087687 Write leveling (Byte 0): 40 => 8
6710 12:32:02.091082 Write leveling (Byte 1): 40 => 8
6711 12:32:02.094563 DramcWriteLeveling(PI) end<-----
6712 12:32:02.095107
6713 12:32:02.095459 ==
6714 12:32:02.097638 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 12:32:02.100747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 12:32:02.101401 ==
6717 12:32:02.104159 [Gating] SW mode calibration
6718 12:32:02.110385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6719 12:32:02.116991 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6720 12:32:02.120523 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 12:32:02.127411 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 12:32:02.130448 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 12:32:02.133914 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 12:32:02.140391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 12:32:02.143811 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 12:32:02.146775 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 12:32:02.153150 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 12:32:02.156865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 12:32:02.159791 Total UI for P1: 0, mck2ui 16
6730 12:32:02.163597 best dqsien dly found for B0: ( 0, 14, 24)
6731 12:32:02.166314 Total UI for P1: 0, mck2ui 16
6732 12:32:02.170074 best dqsien dly found for B1: ( 0, 14, 24)
6733 12:32:02.173660 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6734 12:32:02.176180 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6735 12:32:02.176608
6736 12:32:02.179978 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 12:32:02.182920 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 12:32:02.186195 [Gating] SW calibration Done
6739 12:32:02.186626 ==
6740 12:32:02.189457 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 12:32:02.195847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 12:32:02.196314 ==
6743 12:32:02.196660 RX Vref Scan: 0
6744 12:32:02.196983
6745 12:32:02.199230 RX Vref 0 -> 0, step: 1
6746 12:32:02.199658
6747 12:32:02.202747 RX Delay -410 -> 252, step: 16
6748 12:32:02.205912 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6749 12:32:02.208907 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6750 12:32:02.215835 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6751 12:32:02.218906 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6752 12:32:02.222375 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6753 12:32:02.225513 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6754 12:32:02.232211 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6755 12:32:02.235841 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6756 12:32:02.239391 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6757 12:32:02.241899 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6758 12:32:02.248709 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6759 12:32:02.252215 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6760 12:32:02.255399 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6761 12:32:02.258674 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6762 12:32:02.265270 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6763 12:32:02.268621 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6764 12:32:02.269116 ==
6765 12:32:02.271541 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 12:32:02.275294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 12:32:02.275836 ==
6768 12:32:02.277985 DQS Delay:
6769 12:32:02.278410 DQS0 = 35, DQS1 = 51
6770 12:32:02.281448 DQM Delay:
6771 12:32:02.281923 DQM0 = 6, DQM1 = 13
6772 12:32:02.282275 DQ Delay:
6773 12:32:02.284986 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6774 12:32:02.287898 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6775 12:32:02.291409 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6776 12:32:02.294739 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6777 12:32:02.295166
6778 12:32:02.295508
6779 12:32:02.295826 ==
6780 12:32:02.298000 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:32:02.304340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:32:02.304766 ==
6783 12:32:02.305134
6784 12:32:02.305452
6785 12:32:02.307824 TX Vref Scan disable
6786 12:32:02.308286 == TX Byte 0 ==
6787 12:32:02.311177 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 12:32:02.317887 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 12:32:02.318314 == TX Byte 1 ==
6790 12:32:02.320806 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 12:32:02.327578 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 12:32:02.328007 ==
6793 12:32:02.330671 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 12:32:02.334010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 12:32:02.334448 ==
6796 12:32:02.334794
6797 12:32:02.335110
6798 12:32:02.337342 TX Vref Scan disable
6799 12:32:02.337769 == TX Byte 0 ==
6800 12:32:02.340623 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 12:32:02.347190 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 12:32:02.347728 == TX Byte 1 ==
6803 12:32:02.350660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 12:32:02.356933 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 12:32:02.357364
6806 12:32:02.357708 [DATLAT]
6807 12:32:02.358029 Freq=400, CH1 RK0
6808 12:32:02.359974
6809 12:32:02.360435 DATLAT Default: 0xf
6810 12:32:02.363617 0, 0xFFFF, sum = 0
6811 12:32:02.364071 1, 0xFFFF, sum = 0
6812 12:32:02.366621 2, 0xFFFF, sum = 0
6813 12:32:02.367054 3, 0xFFFF, sum = 0
6814 12:32:02.370450 4, 0xFFFF, sum = 0
6815 12:32:02.371002 5, 0xFFFF, sum = 0
6816 12:32:02.373900 6, 0xFFFF, sum = 0
6817 12:32:02.374440 7, 0xFFFF, sum = 0
6818 12:32:02.376671 8, 0xFFFF, sum = 0
6819 12:32:02.377105 9, 0xFFFF, sum = 0
6820 12:32:02.380257 10, 0xFFFF, sum = 0
6821 12:32:02.380687 11, 0xFFFF, sum = 0
6822 12:32:02.383129 12, 0xFFFF, sum = 0
6823 12:32:02.383562 13, 0x0, sum = 1
6824 12:32:02.386729 14, 0x0, sum = 2
6825 12:32:02.387162 15, 0x0, sum = 3
6826 12:32:02.390304 16, 0x0, sum = 4
6827 12:32:02.390844 best_step = 14
6828 12:32:02.391186
6829 12:32:02.391501 ==
6830 12:32:02.393288 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 12:32:02.399746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 12:32:02.400336 ==
6833 12:32:02.400687 RX Vref Scan: 1
6834 12:32:02.401012
6835 12:32:02.402857 RX Vref 0 -> 0, step: 1
6836 12:32:02.403285
6837 12:32:02.406305 RX Delay -343 -> 252, step: 8
6838 12:32:02.406730
6839 12:32:02.409987 Set Vref, RX VrefLevel [Byte0]: 53
6840 12:32:02.412608 [Byte1]: 53
6841 12:32:02.416237
6842 12:32:02.416760 Final RX Vref Byte 0 = 53 to rank0
6843 12:32:02.419475 Final RX Vref Byte 1 = 53 to rank0
6844 12:32:02.422832 Final RX Vref Byte 0 = 53 to rank1
6845 12:32:02.426380 Final RX Vref Byte 1 = 53 to rank1==
6846 12:32:02.429386 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 12:32:02.435874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 12:32:02.436436 ==
6849 12:32:02.436809 DQS Delay:
6850 12:32:02.439339 DQS0 = 44, DQS1 = 52
6851 12:32:02.439764 DQM Delay:
6852 12:32:02.440145 DQM0 = 10, DQM1 = 11
6853 12:32:02.442204 DQ Delay:
6854 12:32:02.445922 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6855 12:32:02.449097 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6856 12:32:02.449524 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6857 12:32:02.455580 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6858 12:32:02.456009
6859 12:32:02.456387
6860 12:32:02.462290 [DQSOSCAuto] RK0, (LSB)MR18= 0x6288, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6861 12:32:02.465705 CH1 RK0: MR19=C0C, MR18=6288
6862 12:32:02.472462 CH1_RK0: MR19=0xC0C, MR18=0x6288, DQSOSC=392, MR23=63, INC=384, DEC=256
6863 12:32:02.472891 ==
6864 12:32:02.475247 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 12:32:02.478883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 12:32:02.479312 ==
6867 12:32:02.481880 [Gating] SW mode calibration
6868 12:32:02.488854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6869 12:32:02.495289 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6870 12:32:02.499092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 12:32:02.501776 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 12:32:02.508609 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 12:32:02.511743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 12:32:02.515115 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 12:32:02.521416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 12:32:02.524798 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 12:32:02.528263 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 12:32:02.534595 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 12:32:02.538214 Total UI for P1: 0, mck2ui 16
6880 12:32:02.541225 best dqsien dly found for B0: ( 0, 14, 24)
6881 12:32:02.544745 Total UI for P1: 0, mck2ui 16
6882 12:32:02.547661 best dqsien dly found for B1: ( 0, 14, 24)
6883 12:32:02.551529 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6884 12:32:02.554275 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6885 12:32:02.554704
6886 12:32:02.557787 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 12:32:02.560865 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 12:32:02.563949 [Gating] SW calibration Done
6889 12:32:02.564410 ==
6890 12:32:02.567457 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 12:32:02.571033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 12:32:02.571461 ==
6893 12:32:02.574025 RX Vref Scan: 0
6894 12:32:02.574475
6895 12:32:02.577431 RX Vref 0 -> 0, step: 1
6896 12:32:02.577853
6897 12:32:02.578194 RX Delay -410 -> 252, step: 16
6898 12:32:02.584132 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6899 12:32:02.587771 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6900 12:32:02.590771 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6901 12:32:02.597172 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6902 12:32:02.600661 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6903 12:32:02.604264 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6904 12:32:02.607165 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6905 12:32:02.613998 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6906 12:32:02.616925 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6907 12:32:02.620487 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6908 12:32:02.623327 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6909 12:32:02.630385 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6910 12:32:02.633852 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6911 12:32:02.637489 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6912 12:32:02.640270 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6913 12:32:02.646610 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6914 12:32:02.647037 ==
6915 12:32:02.650087 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 12:32:02.653110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 12:32:02.653740 ==
6918 12:32:02.656703 DQS Delay:
6919 12:32:02.657126 DQS0 = 43, DQS1 = 51
6920 12:32:02.657467 DQM Delay:
6921 12:32:02.659704 DQM0 = 10, DQM1 = 15
6922 12:32:02.660166 DQ Delay:
6923 12:32:02.663130 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6924 12:32:02.666851 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6925 12:32:02.669901 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6926 12:32:02.673037 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6927 12:32:02.673480
6928 12:32:02.673824
6929 12:32:02.674140 ==
6930 12:32:02.676360 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:32:02.679663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:32:02.683306 ==
6933 12:32:02.683769
6934 12:32:02.684248
6935 12:32:02.684730 TX Vref Scan disable
6936 12:32:02.686276 == TX Byte 0 ==
6937 12:32:02.689951 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6938 12:32:02.693064 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6939 12:32:02.696074 == TX Byte 1 ==
6940 12:32:02.699460 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6941 12:32:02.702850 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6942 12:32:02.703405 ==
6943 12:32:02.706246 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 12:32:02.709360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 12:32:02.712985 ==
6946 12:32:02.713410
6947 12:32:02.713753
6948 12:32:02.714068 TX Vref Scan disable
6949 12:32:02.715886 == TX Byte 0 ==
6950 12:32:02.719123 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6951 12:32:02.722406 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6952 12:32:02.725896 == TX Byte 1 ==
6953 12:32:02.729307 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6954 12:32:02.732735 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6955 12:32:02.733344
6956 12:32:02.736125 [DATLAT]
6957 12:32:02.736665 Freq=400, CH1 RK1
6958 12:32:02.737187
6959 12:32:02.739015 DATLAT Default: 0xe
6960 12:32:02.739609 0, 0xFFFF, sum = 0
6961 12:32:02.742392 1, 0xFFFF, sum = 0
6962 12:32:02.742957 2, 0xFFFF, sum = 0
6963 12:32:02.746135 3, 0xFFFF, sum = 0
6964 12:32:02.746768 4, 0xFFFF, sum = 0
6965 12:32:02.749128 5, 0xFFFF, sum = 0
6966 12:32:02.749685 6, 0xFFFF, sum = 0
6967 12:32:02.751975 7, 0xFFFF, sum = 0
6968 12:32:02.752599 8, 0xFFFF, sum = 0
6969 12:32:02.755492 9, 0xFFFF, sum = 0
6970 12:32:02.756074 10, 0xFFFF, sum = 0
6971 12:32:02.758773 11, 0xFFFF, sum = 0
6972 12:32:02.762330 12, 0xFFFF, sum = 0
6973 12:32:02.762940 13, 0x0, sum = 1
6974 12:32:02.765235 14, 0x0, sum = 2
6975 12:32:02.765761 15, 0x0, sum = 3
6976 12:32:02.766274 16, 0x0, sum = 4
6977 12:32:02.768925 best_step = 14
6978 12:32:02.769464
6979 12:32:02.769975 ==
6980 12:32:02.771895 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 12:32:02.775576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 12:32:02.776221 ==
6983 12:32:02.778503 RX Vref Scan: 0
6984 12:32:02.779024
6985 12:32:02.782061 RX Vref 0 -> 0, step: 1
6986 12:32:02.782669
6987 12:32:02.783194 RX Delay -343 -> 252, step: 8
6988 12:32:02.790380 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6989 12:32:02.793516 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6990 12:32:02.796978 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6991 12:32:02.803369 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6992 12:32:02.806790 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6993 12:32:02.810290 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6994 12:32:02.813339 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6995 12:32:02.819732 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6996 12:32:02.823220 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6997 12:32:02.826527 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6998 12:32:02.829569 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6999 12:32:02.836322 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7000 12:32:02.839831 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
7001 12:32:02.842440 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
7002 12:32:02.845737 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
7003 12:32:02.852288 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
7004 12:32:02.852371 ==
7005 12:32:02.855958 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 12:32:02.859070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 12:32:02.859154 ==
7008 12:32:02.862521 DQS Delay:
7009 12:32:02.862603 DQS0 = 48, DQS1 = 52
7010 12:32:02.862669 DQM Delay:
7011 12:32:02.865597 DQM0 = 10, DQM1 = 10
7012 12:32:02.865679 DQ Delay:
7013 12:32:02.869238 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7014 12:32:02.872263 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
7015 12:32:02.875905 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7016 12:32:02.878877 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7017 12:32:02.878958
7018 12:32:02.879024
7019 12:32:02.888602 [DQSOSCAuto] RK1, (LSB)MR18= 0x68a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
7020 12:32:02.888686 CH1 RK1: MR19=C0C, MR18=68A0
7021 12:32:02.895088 CH1_RK1: MR19=0xC0C, MR18=0x68A0, DQSOSC=389, MR23=63, INC=390, DEC=260
7022 12:32:02.898782 [RxdqsGatingPostProcess] freq 400
7023 12:32:02.905170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7024 12:32:02.908180 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 12:32:02.911859 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 12:32:02.914765 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 12:32:02.918409 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 12:32:02.921427 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 12:32:02.925040 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 12:32:02.928383 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 12:32:02.931797 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 12:32:02.931879 Pre-setting of DQS Precalculation
7033 12:32:02.938350 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7034 12:32:02.944968 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7035 12:32:02.951475 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7036 12:32:02.951558
7037 12:32:02.951641
7038 12:32:02.954472 [Calibration Summary] 800 Mbps
7039 12:32:02.957938 CH 0, Rank 0
7040 12:32:02.958021 SW Impedance : PASS
7041 12:32:02.961436 DUTY Scan : NO K
7042 12:32:02.964330 ZQ Calibration : PASS
7043 12:32:02.964413 Jitter Meter : NO K
7044 12:32:02.968005 CBT Training : PASS
7045 12:32:02.970997 Write leveling : PASS
7046 12:32:02.971079 RX DQS gating : PASS
7047 12:32:02.974558 RX DQ/DQS(RDDQC) : PASS
7048 12:32:02.974641 TX DQ/DQS : PASS
7049 12:32:02.978062 RX DATLAT : PASS
7050 12:32:02.981047 RX DQ/DQS(Engine): PASS
7051 12:32:02.981129 TX OE : NO K
7052 12:32:02.984667 All Pass.
7053 12:32:02.984750
7054 12:32:02.984851 CH 0, Rank 1
7055 12:32:02.987527 SW Impedance : PASS
7056 12:32:02.987610 DUTY Scan : NO K
7057 12:32:02.990960 ZQ Calibration : PASS
7058 12:32:02.994497 Jitter Meter : NO K
7059 12:32:02.994580 CBT Training : PASS
7060 12:32:02.997555 Write leveling : NO K
7061 12:32:03.000675 RX DQS gating : PASS
7062 12:32:03.000758 RX DQ/DQS(RDDQC) : PASS
7063 12:32:03.004214 TX DQ/DQS : PASS
7064 12:32:03.007706 RX DATLAT : PASS
7065 12:32:03.007814 RX DQ/DQS(Engine): PASS
7066 12:32:03.010692 TX OE : NO K
7067 12:32:03.010775 All Pass.
7068 12:32:03.010841
7069 12:32:03.013741 CH 1, Rank 0
7070 12:32:03.013823 SW Impedance : PASS
7071 12:32:03.017115 DUTY Scan : NO K
7072 12:32:03.020731 ZQ Calibration : PASS
7073 12:32:03.020813 Jitter Meter : NO K
7074 12:32:03.024171 CBT Training : PASS
7075 12:32:03.027125 Write leveling : PASS
7076 12:32:03.027225 RX DQS gating : PASS
7077 12:32:03.030842 RX DQ/DQS(RDDQC) : PASS
7078 12:32:03.033632 TX DQ/DQS : PASS
7079 12:32:03.033718 RX DATLAT : PASS
7080 12:32:03.037120 RX DQ/DQS(Engine): PASS
7081 12:32:03.040504 TX OE : NO K
7082 12:32:03.040586 All Pass.
7083 12:32:03.040651
7084 12:32:03.040711 CH 1, Rank 1
7085 12:32:03.043421 SW Impedance : PASS
7086 12:32:03.046769 DUTY Scan : NO K
7087 12:32:03.046851 ZQ Calibration : PASS
7088 12:32:03.050200 Jitter Meter : NO K
7089 12:32:03.053632 CBT Training : PASS
7090 12:32:03.053714 Write leveling : NO K
7091 12:32:03.056950 RX DQS gating : PASS
7092 12:32:03.059864 RX DQ/DQS(RDDQC) : PASS
7093 12:32:03.059946 TX DQ/DQS : PASS
7094 12:32:03.063386 RX DATLAT : PASS
7095 12:32:03.066391 RX DQ/DQS(Engine): PASS
7096 12:32:03.066473 TX OE : NO K
7097 12:32:03.066540 All Pass.
7098 12:32:03.070025
7099 12:32:03.070107 DramC Write-DBI off
7100 12:32:03.073096 PER_BANK_REFRESH: Hybrid Mode
7101 12:32:03.073178 TX_TRACKING: ON
7102 12:32:03.083306 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7103 12:32:03.086329 [FAST_K] Save calibration result to emmc
7104 12:32:03.089878 dramc_set_vcore_voltage set vcore to 725000
7105 12:32:03.092850 Read voltage for 1600, 0
7106 12:32:03.092932 Vio18 = 0
7107 12:32:03.096365 Vcore = 725000
7108 12:32:03.096447 Vdram = 0
7109 12:32:03.096512 Vddq = 0
7110 12:32:03.099425 Vmddr = 0
7111 12:32:03.103000 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7112 12:32:03.109323 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7113 12:32:03.109508 MEM_TYPE=3, freq_sel=13
7114 12:32:03.112889 sv_algorithm_assistance_LP4_3733
7115 12:32:03.119795 ============ PULL DRAM RESETB DOWN ============
7116 12:32:03.122803 ========== PULL DRAM RESETB DOWN end =========
7117 12:32:03.126153 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7118 12:32:03.129624 ===================================
7119 12:32:03.132562 LPDDR4 DRAM CONFIGURATION
7120 12:32:03.136169 ===================================
7121 12:32:03.139063 EX_ROW_EN[0] = 0x0
7122 12:32:03.139507 EX_ROW_EN[1] = 0x0
7123 12:32:03.142436 LP4Y_EN = 0x0
7124 12:32:03.142882 WORK_FSP = 0x1
7125 12:32:03.145836 WL = 0x5
7126 12:32:03.146297 RL = 0x5
7127 12:32:03.149408 BL = 0x2
7128 12:32:03.149835 RPST = 0x0
7129 12:32:03.152245 RD_PRE = 0x0
7130 12:32:03.152667 WR_PRE = 0x1
7131 12:32:03.155594 WR_PST = 0x1
7132 12:32:03.156239 DBI_WR = 0x0
7133 12:32:03.158946 DBI_RD = 0x0
7134 12:32:03.159514 OTF = 0x1
7135 12:32:03.162360 ===================================
7136 12:32:03.165822 ===================================
7137 12:32:03.168680 ANA top config
7138 12:32:03.172422 ===================================
7139 12:32:03.175959 DLL_ASYNC_EN = 0
7140 12:32:03.176428 ALL_SLAVE_EN = 0
7141 12:32:03.179071 NEW_RANK_MODE = 1
7142 12:32:03.182577 DLL_IDLE_MODE = 1
7143 12:32:03.185606 LP45_APHY_COMB_EN = 1
7144 12:32:03.186029 TX_ODT_DIS = 0
7145 12:32:03.189288 NEW_8X_MODE = 1
7146 12:32:03.192150 ===================================
7147 12:32:03.195807 ===================================
7148 12:32:03.198656 data_rate = 3200
7149 12:32:03.202092 CKR = 1
7150 12:32:03.205589 DQ_P2S_RATIO = 8
7151 12:32:03.208569 ===================================
7152 12:32:03.211768 CA_P2S_RATIO = 8
7153 12:32:03.215196 DQ_CA_OPEN = 0
7154 12:32:03.215625 DQ_SEMI_OPEN = 0
7155 12:32:03.218598 CA_SEMI_OPEN = 0
7156 12:32:03.221844 CA_FULL_RATE = 0
7157 12:32:03.224848 DQ_CKDIV4_EN = 0
7158 12:32:03.228356 CA_CKDIV4_EN = 0
7159 12:32:03.231758 CA_PREDIV_EN = 0
7160 12:32:03.232214 PH8_DLY = 12
7161 12:32:03.234718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7162 12:32:03.238246 DQ_AAMCK_DIV = 4
7163 12:32:03.241260 CA_AAMCK_DIV = 4
7164 12:32:03.244496 CA_ADMCK_DIV = 4
7165 12:32:03.248551 DQ_TRACK_CA_EN = 0
7166 12:32:03.251271 CA_PICK = 1600
7167 12:32:03.251798 CA_MCKIO = 1600
7168 12:32:03.254563 MCKIO_SEMI = 0
7169 12:32:03.257917 PLL_FREQ = 3068
7170 12:32:03.260809 DQ_UI_PI_RATIO = 32
7171 12:32:03.264375 CA_UI_PI_RATIO = 0
7172 12:32:03.267533 ===================================
7173 12:32:03.271252 ===================================
7174 12:32:03.274129 memory_type:LPDDR4
7175 12:32:03.274687 GP_NUM : 10
7176 12:32:03.277659 SRAM_EN : 1
7177 12:32:03.280679 MD32_EN : 0
7178 12:32:03.284282 ===================================
7179 12:32:03.284733 [ANA_INIT] >>>>>>>>>>>>>>
7180 12:32:03.287503 <<<<<< [CONFIGURE PHASE]: ANA_TX
7181 12:32:03.290327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7182 12:32:03.294057 ===================================
7183 12:32:03.296908 data_rate = 3200,PCW = 0X7600
7184 12:32:03.300599 ===================================
7185 12:32:03.303458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7186 12:32:03.310411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 12:32:03.313379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 12:32:03.319927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7189 12:32:03.322926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7190 12:32:03.326410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7191 12:32:03.330029 [ANA_INIT] flow start
7192 12:32:03.330493 [ANA_INIT] PLL >>>>>>>>
7193 12:32:03.332915 [ANA_INIT] PLL <<<<<<<<
7194 12:32:03.336518 [ANA_INIT] MIDPI >>>>>>>>
7195 12:32:03.336962 [ANA_INIT] MIDPI <<<<<<<<
7196 12:32:03.339515 [ANA_INIT] DLL >>>>>>>>
7197 12:32:03.343405 [ANA_INIT] DLL <<<<<<<<
7198 12:32:03.343945 [ANA_INIT] flow end
7199 12:32:03.349516 ============ LP4 DIFF to SE enter ============
7200 12:32:03.352598 ============ LP4 DIFF to SE exit ============
7201 12:32:03.356060 [ANA_INIT] <<<<<<<<<<<<<
7202 12:32:03.359309 [Flow] Enable top DCM control >>>>>
7203 12:32:03.362615 [Flow] Enable top DCM control <<<<<
7204 12:32:03.363062 Enable DLL master slave shuffle
7205 12:32:03.369376 ==============================================================
7206 12:32:03.372297 Gating Mode config
7207 12:32:03.375829 ==============================================================
7208 12:32:03.378817 Config description:
7209 12:32:03.388938 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7210 12:32:03.395769 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7211 12:32:03.398949 SELPH_MODE 0: By rank 1: By Phase
7212 12:32:03.405405 ==============================================================
7213 12:32:03.409139 GAT_TRACK_EN = 1
7214 12:32:03.411836 RX_GATING_MODE = 2
7215 12:32:03.415374 RX_GATING_TRACK_MODE = 2
7216 12:32:03.418618 SELPH_MODE = 1
7217 12:32:03.422082 PICG_EARLY_EN = 1
7218 12:32:03.424969 VALID_LAT_VALUE = 1
7219 12:32:03.428642 ==============================================================
7220 12:32:03.431675 Enter into Gating configuration >>>>
7221 12:32:03.435475 Exit from Gating configuration <<<<
7222 12:32:03.438472 Enter into DVFS_PRE_config >>>>>
7223 12:32:03.451525 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7224 12:32:03.452110 Exit from DVFS_PRE_config <<<<<
7225 12:32:03.454659 Enter into PICG configuration >>>>
7226 12:32:03.458265 Exit from PICG configuration <<<<
7227 12:32:03.461172 [RX_INPUT] configuration >>>>>
7228 12:32:03.464595 [RX_INPUT] configuration <<<<<
7229 12:32:03.471403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7230 12:32:03.474447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7231 12:32:03.481217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 12:32:03.487737 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 12:32:03.494481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 12:32:03.500784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 12:32:03.503714 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7236 12:32:03.507144 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7237 12:32:03.513889 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7238 12:32:03.517402 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7239 12:32:03.520323 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7240 12:32:03.523812 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7241 12:32:03.526904 ===================================
7242 12:32:03.530625 LPDDR4 DRAM CONFIGURATION
7243 12:32:03.533782 ===================================
7244 12:32:03.536679 EX_ROW_EN[0] = 0x0
7245 12:32:03.537101 EX_ROW_EN[1] = 0x0
7246 12:32:03.540473 LP4Y_EN = 0x0
7247 12:32:03.540924 WORK_FSP = 0x1
7248 12:32:03.543933 WL = 0x5
7249 12:32:03.544474 RL = 0x5
7250 12:32:03.546919 BL = 0x2
7251 12:32:03.547347 RPST = 0x0
7252 12:32:03.550185 RD_PRE = 0x0
7253 12:32:03.553379 WR_PRE = 0x1
7254 12:32:03.553826 WR_PST = 0x1
7255 12:32:03.556471 DBI_WR = 0x0
7256 12:32:03.556913 DBI_RD = 0x0
7257 12:32:03.559889 OTF = 0x1
7258 12:32:03.563388 ===================================
7259 12:32:03.566754 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7260 12:32:03.569908 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7261 12:32:03.576350 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 12:32:03.579763 ===================================
7263 12:32:03.580265 LPDDR4 DRAM CONFIGURATION
7264 12:32:03.582701 ===================================
7265 12:32:03.586873 EX_ROW_EN[0] = 0x10
7266 12:32:03.587430 EX_ROW_EN[1] = 0x0
7267 12:32:03.589818 LP4Y_EN = 0x0
7268 12:32:03.592558 WORK_FSP = 0x1
7269 12:32:03.593001 WL = 0x5
7270 12:32:03.596195 RL = 0x5
7271 12:32:03.596640 BL = 0x2
7272 12:32:03.599326 RPST = 0x0
7273 12:32:03.599767 RD_PRE = 0x0
7274 12:32:03.602368 WR_PRE = 0x1
7275 12:32:03.602813 WR_PST = 0x1
7276 12:32:03.605931 DBI_WR = 0x0
7277 12:32:03.606371 DBI_RD = 0x0
7278 12:32:03.608905 OTF = 0x1
7279 12:32:03.612527 ===================================
7280 12:32:03.618931 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7281 12:32:03.619469 ==
7282 12:32:03.622578 Dram Type= 6, Freq= 0, CH_0, rank 0
7283 12:32:03.625890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 12:32:03.626368 ==
7285 12:32:03.628946 [Duty_Offset_Calibration]
7286 12:32:03.629488 B0:2 B1:0 CA:4
7287 12:32:03.629939
7288 12:32:03.632378 [DutyScan_Calibration_Flow] k_type=0
7289 12:32:03.642292
7290 12:32:03.642849 ==CLK 0==
7291 12:32:03.645579 Final CLK duty delay cell = -4
7292 12:32:03.648437 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7293 12:32:03.651741 [-4] MIN Duty = 4844%(X100), DQS PI = 8
7294 12:32:03.654989 [-4] AVG Duty = 4937%(X100)
7295 12:32:03.655100
7296 12:32:03.658081 CH0 CLK Duty spec in!! Max-Min= 187%
7297 12:32:03.661149 [DutyScan_Calibration_Flow] ====Done====
7298 12:32:03.661236
7299 12:32:03.664288 [DutyScan_Calibration_Flow] k_type=1
7300 12:32:03.681718
7301 12:32:03.681809 ==DQS 0 ==
7302 12:32:03.685286 Final DQS duty delay cell = 0
7303 12:32:03.688004 [0] MAX Duty = 5249%(X100), DQS PI = 38
7304 12:32:03.691711 [0] MIN Duty = 5093%(X100), DQS PI = 10
7305 12:32:03.694792 [0] AVG Duty = 5171%(X100)
7306 12:32:03.694885
7307 12:32:03.694977 ==DQS 1 ==
7308 12:32:03.698350 Final DQS duty delay cell = 0
7309 12:32:03.701344 [0] MAX Duty = 5187%(X100), DQS PI = 2
7310 12:32:03.705250 [0] MIN Duty = 4969%(X100), DQS PI = 10
7311 12:32:03.708182 [0] AVG Duty = 5078%(X100)
7312 12:32:03.708625
7313 12:32:03.711832 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7314 12:32:03.712369
7315 12:32:03.714759 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7316 12:32:03.718247 [DutyScan_Calibration_Flow] ====Done====
7317 12:32:03.718690
7318 12:32:03.721684 [DutyScan_Calibration_Flow] k_type=3
7319 12:32:03.739274
7320 12:32:03.739862 ==DQM 0 ==
7321 12:32:03.742899 Final DQM duty delay cell = 0
7322 12:32:03.745840 [0] MAX Duty = 5124%(X100), DQS PI = 22
7323 12:32:03.749441 [0] MIN Duty = 4875%(X100), DQS PI = 56
7324 12:32:03.752376 [0] AVG Duty = 4999%(X100)
7325 12:32:03.752803
7326 12:32:03.753154 ==DQM 1 ==
7327 12:32:03.755936 Final DQM duty delay cell = 0
7328 12:32:03.759367 [0] MAX Duty = 4969%(X100), DQS PI = 0
7329 12:32:03.762439 [0] MIN Duty = 4844%(X100), DQS PI = 10
7330 12:32:03.766012 [0] AVG Duty = 4906%(X100)
7331 12:32:03.766555
7332 12:32:03.768981 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7333 12:32:03.769408
7334 12:32:03.772420 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7335 12:32:03.776017 [DutyScan_Calibration_Flow] ====Done====
7336 12:32:03.776486
7337 12:32:03.778901 [DutyScan_Calibration_Flow] k_type=2
7338 12:32:03.796490
7339 12:32:03.797026 ==DQ 0 ==
7340 12:32:03.799487 Final DQ duty delay cell = 0
7341 12:32:03.802905 [0] MAX Duty = 5156%(X100), DQS PI = 22
7342 12:32:03.805949 [0] MIN Duty = 4938%(X100), DQS PI = 12
7343 12:32:03.808851 [0] AVG Duty = 5047%(X100)
7344 12:32:03.808944
7345 12:32:03.809010 ==DQ 1 ==
7346 12:32:03.812551 Final DQ duty delay cell = 0
7347 12:32:03.815574 [0] MAX Duty = 5187%(X100), DQS PI = 2
7348 12:32:03.819026 [0] MIN Duty = 4938%(X100), DQS PI = 12
7349 12:32:03.819108 [0] AVG Duty = 5062%(X100)
7350 12:32:03.822707
7351 12:32:03.825670 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7352 12:32:03.825781
7353 12:32:03.828830 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7354 12:32:03.832058 [DutyScan_Calibration_Flow] ====Done====
7355 12:32:03.832147 ==
7356 12:32:03.835845 Dram Type= 6, Freq= 0, CH_1, rank 0
7357 12:32:03.839086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7358 12:32:03.839586 ==
7359 12:32:03.842632 [Duty_Offset_Calibration]
7360 12:32:03.843048 B0:0 B1:-1 CA:3
7361 12:32:03.843383
7362 12:32:03.845538 [DutyScan_Calibration_Flow] k_type=0
7363 12:32:03.855716
7364 12:32:03.856182 ==CLK 0==
7365 12:32:03.859231 Final CLK duty delay cell = -4
7366 12:32:03.862166 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7367 12:32:03.865825 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7368 12:32:03.869440 [-4] AVG Duty = 4922%(X100)
7369 12:32:03.869854
7370 12:32:03.872670 CH1 CLK Duty spec in!! Max-Min= 156%
7371 12:32:03.875675 [DutyScan_Calibration_Flow] ====Done====
7372 12:32:03.876365
7373 12:32:03.878961 [DutyScan_Calibration_Flow] k_type=1
7374 12:32:03.895348
7375 12:32:03.895855 ==DQS 0 ==
7376 12:32:03.898175 Final DQS duty delay cell = 0
7377 12:32:03.901781 [0] MAX Duty = 5250%(X100), DQS PI = 30
7378 12:32:03.904675 [0] MIN Duty = 4907%(X100), DQS PI = 60
7379 12:32:03.908290 [0] AVG Duty = 5078%(X100)
7380 12:32:03.908703
7381 12:32:03.909030 ==DQS 1 ==
7382 12:32:03.911157 Final DQS duty delay cell = -4
7383 12:32:03.915001 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7384 12:32:03.917912 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7385 12:32:03.921533 [-4] AVG Duty = 4922%(X100)
7386 12:32:03.921945
7387 12:32:03.924463 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7388 12:32:03.924934
7389 12:32:03.927948 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7390 12:32:03.930944 [DutyScan_Calibration_Flow] ====Done====
7391 12:32:03.931363
7392 12:32:03.934827 [DutyScan_Calibration_Flow] k_type=3
7393 12:32:03.952264
7394 12:32:03.952821 ==DQM 0 ==
7395 12:32:03.955812 Final DQM duty delay cell = 0
7396 12:32:03.958825 [0] MAX Duty = 5062%(X100), DQS PI = 30
7397 12:32:03.962580 [0] MIN Duty = 4750%(X100), DQS PI = 40
7398 12:32:03.965486 [0] AVG Duty = 4906%(X100)
7399 12:32:03.965973
7400 12:32:03.966385 ==DQM 1 ==
7401 12:32:03.968836 Final DQM duty delay cell = 0
7402 12:32:03.971732 [0] MAX Duty = 5000%(X100), DQS PI = 30
7403 12:32:03.975317 [0] MIN Duty = 4813%(X100), DQS PI = 0
7404 12:32:03.978718 [0] AVG Duty = 4906%(X100)
7405 12:32:03.979137
7406 12:32:03.981890 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7407 12:32:03.982414
7408 12:32:03.985579 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7409 12:32:03.988163 [DutyScan_Calibration_Flow] ====Done====
7410 12:32:03.988690
7411 12:32:03.991599 [DutyScan_Calibration_Flow] k_type=2
7412 12:32:04.008751
7413 12:32:04.009274 ==DQ 0 ==
7414 12:32:04.011767 Final DQ duty delay cell = -4
7415 12:32:04.015383 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7416 12:32:04.018117 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7417 12:32:04.021919 [-4] AVG Duty = 4891%(X100)
7418 12:32:04.022438
7419 12:32:04.022774 ==DQ 1 ==
7420 12:32:04.024668 Final DQ duty delay cell = 0
7421 12:32:04.028265 [0] MAX Duty = 5062%(X100), DQS PI = 32
7422 12:32:04.031278 [0] MIN Duty = 4875%(X100), DQS PI = 0
7423 12:32:04.034845 [0] AVG Duty = 4968%(X100)
7424 12:32:04.035333
7425 12:32:04.037777 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7426 12:32:04.038198
7427 12:32:04.041319 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7428 12:32:04.044642 [DutyScan_Calibration_Flow] ====Done====
7429 12:32:04.047868 nWR fixed to 30
7430 12:32:04.050914 [ModeRegInit_LP4] CH0 RK0
7431 12:32:04.051325 [ModeRegInit_LP4] CH0 RK1
7432 12:32:04.054282 [ModeRegInit_LP4] CH1 RK0
7433 12:32:04.057377 [ModeRegInit_LP4] CH1 RK1
7434 12:32:04.057792 match AC timing 5
7435 12:32:04.064007 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7436 12:32:04.067577 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7437 12:32:04.070421 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7438 12:32:04.077033 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7439 12:32:04.080672 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7440 12:32:04.083861 [MiockJmeterHQA]
7441 12:32:04.084437
7442 12:32:04.086799 [DramcMiockJmeter] u1RxGatingPI = 0
7443 12:32:04.087215 0 : 4365, 4137
7444 12:32:04.087554 4 : 4253, 4026
7445 12:32:04.090406 8 : 4363, 4138
7446 12:32:04.090827 12 : 4253, 4026
7447 12:32:04.093881 16 : 4363, 4137
7448 12:32:04.094343 20 : 4252, 4027
7449 12:32:04.096809 24 : 4361, 4137
7450 12:32:04.097230 28 : 4253, 4027
7451 12:32:04.100016 32 : 4250, 4026
7452 12:32:04.100480 36 : 4250, 4027
7453 12:32:04.100833 40 : 4253, 4027
7454 12:32:04.103378 44 : 4363, 4139
7455 12:32:04.103796 48 : 4253, 4027
7456 12:32:04.106509 52 : 4253, 4026
7457 12:32:04.106947 56 : 4250, 4027
7458 12:32:04.110112 60 : 4253, 4027
7459 12:32:04.110560 64 : 4253, 4029
7460 12:32:04.113495 68 : 4360, 4138
7461 12:32:04.113914 72 : 4252, 4026
7462 12:32:04.114250 76 : 4250, 4027
7463 12:32:04.116606 80 : 4250, 4027
7464 12:32:04.117027 84 : 4253, 4029
7465 12:32:04.120321 88 : 4250, 4027
7466 12:32:04.120744 92 : 4361, 4137
7467 12:32:04.123185 96 : 4361, 3591
7468 12:32:04.123604 100 : 4250, 0
7469 12:32:04.123939 104 : 4360, 0
7470 12:32:04.126689 108 : 4252, 0
7471 12:32:04.127112 112 : 4250, 0
7472 12:32:04.129632 116 : 4250, 0
7473 12:32:04.130056 120 : 4253, 0
7474 12:32:04.130395 124 : 4250, 0
7475 12:32:04.133552 128 : 4250, 0
7476 12:32:04.134097 132 : 4253, 0
7477 12:32:04.136286 136 : 4361, 0
7478 12:32:04.136721 140 : 4250, 0
7479 12:32:04.137068 144 : 4361, 0
7480 12:32:04.140122 148 : 4250, 0
7481 12:32:04.140694 152 : 4361, 0
7482 12:32:04.143560 156 : 4250, 0
7483 12:32:04.144142 160 : 4252, 0
7484 12:32:04.144505 164 : 4250, 0
7485 12:32:04.146432 168 : 4250, 0
7486 12:32:04.146884 172 : 4250, 0
7487 12:32:04.147231 176 : 4250, 0
7488 12:32:04.149784 180 : 4250, 0
7489 12:32:04.150219 184 : 4253, 0
7490 12:32:04.152672 188 : 4361, 0
7491 12:32:04.153106 192 : 4250, 0
7492 12:32:04.153456 196 : 4250, 0
7493 12:32:04.156105 200 : 4361, 0
7494 12:32:04.156542 204 : 4250, 0
7495 12:32:04.159577 208 : 4250, 0
7496 12:32:04.160006 212 : 4250, 0
7497 12:32:04.160389 216 : 4250, 0
7498 12:32:04.163130 220 : 4250, 576
7499 12:32:04.163567 224 : 4250, 3947
7500 12:32:04.166260 228 : 4250, 4027
7501 12:32:04.166706 232 : 4361, 4138
7502 12:32:04.169345 236 : 4250, 4027
7503 12:32:04.169799 240 : 4250, 4027
7504 12:32:04.172593 244 : 4250, 4026
7505 12:32:04.173027 248 : 4253, 4029
7506 12:32:04.176170 252 : 4250, 4027
7507 12:32:04.176603 256 : 4250, 4027
7508 12:32:04.179545 260 : 4361, 4137
7509 12:32:04.179977 264 : 4250, 4026
7510 12:32:04.182676 268 : 4250, 4027
7511 12:32:04.183129 272 : 4360, 4138
7512 12:32:04.183478 276 : 4250, 4027
7513 12:32:04.186108 280 : 4250, 4026
7514 12:32:04.186539 284 : 4363, 4139
7515 12:32:04.189430 288 : 4250, 4027
7516 12:32:04.189883 292 : 4250, 4027
7517 12:32:04.192340 296 : 4250, 4027
7518 12:32:04.192904 300 : 4253, 4029
7519 12:32:04.196028 304 : 4250, 4027
7520 12:32:04.196503 308 : 4250, 4027
7521 12:32:04.198989 312 : 4361, 4137
7522 12:32:04.199506 316 : 4250, 4026
7523 12:32:04.202293 320 : 4250, 4027
7524 12:32:04.202849 324 : 4360, 4138
7525 12:32:04.205907 328 : 4250, 4027
7526 12:32:04.206457 332 : 4250, 4022
7527 12:32:04.206820 336 : 4363, 2475
7528 12:32:04.209211 340 : 4250, 70
7529 12:32:04.209648
7530 12:32:04.212178 MIOCK jitter meter ch=0
7531 12:32:04.212749
7532 12:32:04.215648 1T = (340-100) = 240 dly cells
7533 12:32:04.218567 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7534 12:32:04.219072 ==
7535 12:32:04.222315 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 12:32:04.228763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 12:32:04.229322 ==
7538 12:32:04.231898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 12:32:04.238345 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 12:32:04.242130 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 12:32:04.248220 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 12:32:04.256521 [CA 0] Center 43 (13~73) winsize 61
7543 12:32:04.259817 [CA 1] Center 42 (12~73) winsize 62
7544 12:32:04.262945 [CA 2] Center 37 (8~67) winsize 60
7545 12:32:04.266246 [CA 3] Center 37 (8~67) winsize 60
7546 12:32:04.269284 [CA 4] Center 36 (6~66) winsize 61
7547 12:32:04.272932 [CA 5] Center 35 (5~66) winsize 62
7548 12:32:04.273594
7549 12:32:04.275999 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 12:32:04.276704
7551 12:32:04.279499 [CATrainingPosCal] consider 1 rank data
7552 12:32:04.282298 u2DelayCellTimex100 = 271/100 ps
7553 12:32:04.288815 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7554 12:32:04.292142 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7555 12:32:04.295406 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7556 12:32:04.299074 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7557 12:32:04.301994 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7558 12:32:04.305478 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7559 12:32:04.305928
7560 12:32:04.308938 CA PerBit enable=1, Macro0, CA PI delay=35
7561 12:32:04.309418
7562 12:32:04.311922 [CBTSetCACLKResult] CA Dly = 35
7563 12:32:04.315364 CS Dly: 10 (0~41)
7564 12:32:04.318884 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 12:32:04.321951 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 12:32:04.322553 ==
7567 12:32:04.325006 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 12:32:04.331554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 12:32:04.332106 ==
7570 12:32:04.335166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 12:32:04.341836 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 12:32:04.344787 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 12:32:04.351324 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 12:32:04.359936 [CA 0] Center 44 (13~75) winsize 63
7575 12:32:04.362579 [CA 1] Center 43 (13~74) winsize 62
7576 12:32:04.365995 [CA 2] Center 38 (9~68) winsize 60
7577 12:32:04.369650 [CA 3] Center 38 (9~68) winsize 60
7578 12:32:04.372626 [CA 4] Center 37 (7~67) winsize 61
7579 12:32:04.376006 [CA 5] Center 36 (7~66) winsize 60
7580 12:32:04.376513
7581 12:32:04.379533 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 12:32:04.379982
7583 12:32:04.385803 [CATrainingPosCal] consider 2 rank data
7584 12:32:04.386231 u2DelayCellTimex100 = 271/100 ps
7585 12:32:04.392429 CA0 delay=43 (13~73),Diff = 7 PI (25 cell)
7586 12:32:04.395945 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7587 12:32:04.399355 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7588 12:32:04.402107 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7589 12:32:04.405879 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7590 12:32:04.408774 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7591 12:32:04.409359
7592 12:32:04.412130 CA PerBit enable=1, Macro0, CA PI delay=36
7593 12:32:04.412588
7594 12:32:04.415645 [CBTSetCACLKResult] CA Dly = 36
7595 12:32:04.419138 CS Dly: 11 (0~44)
7596 12:32:04.421941 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 12:32:04.425568 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 12:32:04.426002
7599 12:32:04.428501 ----->DramcWriteLeveling(PI) begin...
7600 12:32:04.428938 ==
7601 12:32:04.432165 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 12:32:04.438949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 12:32:04.439535 ==
7604 12:32:04.441683 Write leveling (Byte 0): 33 => 33
7605 12:32:04.445146 Write leveling (Byte 1): 25 => 25
7606 12:32:04.448736 DramcWriteLeveling(PI) end<-----
7607 12:32:04.449210
7608 12:32:04.449562 ==
7609 12:32:04.451738 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 12:32:04.454743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 12:32:04.455177 ==
7612 12:32:04.458255 [Gating] SW mode calibration
7613 12:32:04.464704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 12:32:04.471612 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 12:32:04.474755 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 12:32:04.477789 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 12:32:04.484299 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 12:32:04.487825 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7619 12:32:04.491187 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7620 12:32:04.497532 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7621 12:32:04.501281 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 12:32:04.504117 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 12:32:04.511105 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 12:32:04.513966 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 12:32:04.517455 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7626 12:32:04.523744 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7627 12:32:04.527363 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7628 12:32:04.530594 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7629 12:32:04.537238 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7630 12:32:04.540138 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 12:32:04.543856 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:32:04.550276 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 12:32:04.553299 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7634 12:32:04.556873 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7635 12:32:04.563252 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7636 12:32:04.566928 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7637 12:32:04.569827 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 12:32:04.576691 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 12:32:04.579681 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 12:32:04.582758 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 12:32:04.589495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 12:32:04.592413 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 12:32:04.595707 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7644 12:32:04.602152 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 12:32:04.605782 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 12:32:04.608702 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 12:32:04.615806 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 12:32:04.618674 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:32:04.622194 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:32:04.628599 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 12:32:04.631922 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:32:04.635484 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:32:04.642072 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 12:32:04.645036 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 12:32:04.648651 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 12:32:04.655196 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 12:32:04.658222 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 12:32:04.661773 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 12:32:04.668505 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7660 12:32:04.668585 Total UI for P1: 0, mck2ui 16
7661 12:32:04.674846 best dqsien dly found for B0: ( 1, 9, 10)
7662 12:32:04.678319 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 12:32:04.681372 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 12:32:04.684977 Total UI for P1: 0, mck2ui 16
7665 12:32:04.687954 best dqsien dly found for B1: ( 1, 9, 20)
7666 12:32:04.691622 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7667 12:32:04.694551 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7668 12:32:04.694634
7669 12:32:04.701476 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7670 12:32:04.704452 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7671 12:32:04.707961 [Gating] SW calibration Done
7672 12:32:04.708102 ==
7673 12:32:04.710951 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 12:32:04.714425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 12:32:04.714510 ==
7676 12:32:04.717849 RX Vref Scan: 0
7677 12:32:04.717932
7678 12:32:04.717999 RX Vref 0 -> 0, step: 1
7679 12:32:04.718062
7680 12:32:04.720780 RX Delay 0 -> 252, step: 8
7681 12:32:04.724290 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7682 12:32:04.727744 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7683 12:32:04.733853 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7684 12:32:04.737576 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7685 12:32:04.740433 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7686 12:32:04.743910 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7687 12:32:04.750455 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7688 12:32:04.753485 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7689 12:32:04.757150 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7690 12:32:04.760065 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7691 12:32:04.763770 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7692 12:32:04.769823 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7693 12:32:04.773280 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7694 12:32:04.776789 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7695 12:32:04.779859 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7696 12:32:04.786334 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7697 12:32:04.786438 ==
7698 12:32:04.789986 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 12:32:04.793019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 12:32:04.793094 ==
7701 12:32:04.793159 DQS Delay:
7702 12:32:04.796545 DQS0 = 0, DQS1 = 0
7703 12:32:04.796617 DQM Delay:
7704 12:32:04.799350 DQM0 = 131, DQM1 = 126
7705 12:32:04.799447 DQ Delay:
7706 12:32:04.802870 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7707 12:32:04.806236 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7708 12:32:04.809814 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7709 12:32:04.812671 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7710 12:32:04.812774
7711 12:32:04.812865
7712 12:32:04.816307 ==
7713 12:32:04.819696 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 12:32:04.822723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 12:32:04.822826 ==
7716 12:32:04.822917
7717 12:32:04.823004
7718 12:32:04.825767 TX Vref Scan disable
7719 12:32:04.825864 == TX Byte 0 ==
7720 12:32:04.832326 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7721 12:32:04.835794 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7722 12:32:04.835878 == TX Byte 1 ==
7723 12:32:04.842286 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7724 12:32:04.845846 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7725 12:32:04.845930 ==
7726 12:32:04.849442 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 12:32:04.852357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 12:32:04.852454 ==
7729 12:32:04.866842
7730 12:32:04.870381 TX Vref early break, caculate TX vref
7731 12:32:04.873792 TX Vref=16, minBit 4, minWin=22, winSum=371
7732 12:32:04.876672 TX Vref=18, minBit 10, minWin=22, winSum=376
7733 12:32:04.880240 TX Vref=20, minBit 8, minWin=23, winSum=391
7734 12:32:04.883312 TX Vref=22, minBit 3, minWin=24, winSum=398
7735 12:32:04.886766 TX Vref=24, minBit 0, minWin=25, winSum=410
7736 12:32:04.893391 TX Vref=26, minBit 6, minWin=25, winSum=415
7737 12:32:04.896788 TX Vref=28, minBit 0, minWin=26, winSum=424
7738 12:32:04.899803 TX Vref=30, minBit 2, minWin=25, winSum=415
7739 12:32:04.903191 TX Vref=32, minBit 4, minWin=24, winSum=406
7740 12:32:04.906180 TX Vref=34, minBit 0, minWin=24, winSum=397
7741 12:32:04.912633 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
7742 12:32:04.913093
7743 12:32:04.916109 Final TX Range 0 Vref 28
7744 12:32:04.916544
7745 12:32:04.916890 ==
7746 12:32:04.919165 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 12:32:04.922544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 12:32:04.922997 ==
7749 12:32:04.923343
7750 12:32:04.923658
7751 12:32:04.925969 TX Vref Scan disable
7752 12:32:04.932592 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7753 12:32:04.933022 == TX Byte 0 ==
7754 12:32:04.936095 u2DelayCellOfst[0]=14 cells (4 PI)
7755 12:32:04.939140 u2DelayCellOfst[1]=18 cells (5 PI)
7756 12:32:04.942507 u2DelayCellOfst[2]=10 cells (3 PI)
7757 12:32:04.945956 u2DelayCellOfst[3]=10 cells (3 PI)
7758 12:32:04.948945 u2DelayCellOfst[4]=7 cells (2 PI)
7759 12:32:04.952282 u2DelayCellOfst[5]=0 cells (0 PI)
7760 12:32:04.955807 u2DelayCellOfst[6]=18 cells (5 PI)
7761 12:32:04.959241 u2DelayCellOfst[7]=18 cells (5 PI)
7762 12:32:04.962189 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7763 12:32:04.965798 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7764 12:32:04.968822 == TX Byte 1 ==
7765 12:32:04.972395 u2DelayCellOfst[8]=0 cells (0 PI)
7766 12:32:04.975388 u2DelayCellOfst[9]=0 cells (0 PI)
7767 12:32:04.978922 u2DelayCellOfst[10]=3 cells (1 PI)
7768 12:32:04.982396 u2DelayCellOfst[11]=0 cells (0 PI)
7769 12:32:04.982827 u2DelayCellOfst[12]=10 cells (3 PI)
7770 12:32:04.985386 u2DelayCellOfst[13]=7 cells (2 PI)
7771 12:32:04.988968 u2DelayCellOfst[14]=14 cells (4 PI)
7772 12:32:04.991962 u2DelayCellOfst[15]=10 cells (3 PI)
7773 12:32:04.998999 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7774 12:32:05.001954 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7775 12:32:05.002389 DramC Write-DBI on
7776 12:32:05.002734 ==
7777 12:32:05.005629 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 12:32:05.012221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 12:32:05.012655 ==
7780 12:32:05.013000
7781 12:32:05.013378
7782 12:32:05.015166 TX Vref Scan disable
7783 12:32:05.015784 == TX Byte 0 ==
7784 12:32:05.022155 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7785 12:32:05.022582 == TX Byte 1 ==
7786 12:32:05.025224 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7787 12:32:05.028496 DramC Write-DBI off
7788 12:32:05.028950
7789 12:32:05.029310 [DATLAT]
7790 12:32:05.032106 Freq=1600, CH0 RK0
7791 12:32:05.032533
7792 12:32:05.032873 DATLAT Default: 0xf
7793 12:32:05.035129 0, 0xFFFF, sum = 0
7794 12:32:05.035562 1, 0xFFFF, sum = 0
7795 12:32:05.038135 2, 0xFFFF, sum = 0
7796 12:32:05.038569 3, 0xFFFF, sum = 0
7797 12:32:05.041661 4, 0xFFFF, sum = 0
7798 12:32:05.042094 5, 0xFFFF, sum = 0
7799 12:32:05.045043 6, 0xFFFF, sum = 0
7800 12:32:05.048084 7, 0xFFFF, sum = 0
7801 12:32:05.048515 8, 0xFFFF, sum = 0
7802 12:32:05.051521 9, 0xFFFF, sum = 0
7803 12:32:05.051967 10, 0xFFFF, sum = 0
7804 12:32:05.055124 11, 0xFFFF, sum = 0
7805 12:32:05.055552 12, 0xFFFF, sum = 0
7806 12:32:05.058172 13, 0xFFFF, sum = 0
7807 12:32:05.058606 14, 0x0, sum = 1
7808 12:32:05.061355 15, 0x0, sum = 2
7809 12:32:05.061786 16, 0x0, sum = 3
7810 12:32:05.064698 17, 0x0, sum = 4
7811 12:32:05.065129 best_step = 15
7812 12:32:05.065470
7813 12:32:05.065786 ==
7814 12:32:05.067776 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 12:32:05.071426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 12:32:05.074433 ==
7817 12:32:05.074932 RX Vref Scan: 1
7818 12:32:05.075277
7819 12:32:05.077934 Set Vref Range= 24 -> 127
7820 12:32:05.078376
7821 12:32:05.081484 RX Vref 24 -> 127, step: 1
7822 12:32:05.081910
7823 12:32:05.082311 RX Delay 11 -> 252, step: 4
7824 12:32:05.082649
7825 12:32:05.084417 Set Vref, RX VrefLevel [Byte0]: 24
7826 12:32:05.087434 [Byte1]: 24
7827 12:32:05.091751
7828 12:32:05.092288 Set Vref, RX VrefLevel [Byte0]: 25
7829 12:32:05.095244 [Byte1]: 25
7830 12:32:05.099223
7831 12:32:05.099818 Set Vref, RX VrefLevel [Byte0]: 26
7832 12:32:05.103042 [Byte1]: 26
7833 12:32:05.106971
7834 12:32:05.107392 Set Vref, RX VrefLevel [Byte0]: 27
7835 12:32:05.109913 [Byte1]: 27
7836 12:32:05.114075
7837 12:32:05.114497 Set Vref, RX VrefLevel [Byte0]: 28
7838 12:32:05.117765 [Byte1]: 28
7839 12:32:05.121757
7840 12:32:05.122177 Set Vref, RX VrefLevel [Byte0]: 29
7841 12:32:05.125206 [Byte1]: 29
7842 12:32:05.129443
7843 12:32:05.129882 Set Vref, RX VrefLevel [Byte0]: 30
7844 12:32:05.132801 [Byte1]: 30
7845 12:32:05.137261
7846 12:32:05.137693 Set Vref, RX VrefLevel [Byte0]: 31
7847 12:32:05.140205 [Byte1]: 31
7848 12:32:05.144956
7849 12:32:05.145380 Set Vref, RX VrefLevel [Byte0]: 32
7850 12:32:05.148415 [Byte1]: 32
7851 12:32:05.152564
7852 12:32:05.153042 Set Vref, RX VrefLevel [Byte0]: 33
7853 12:32:05.155842 [Byte1]: 33
7854 12:32:05.159808
7855 12:32:05.163334 Set Vref, RX VrefLevel [Byte0]: 34
7856 12:32:05.166368 [Byte1]: 34
7857 12:32:05.167045
7858 12:32:05.169613 Set Vref, RX VrefLevel [Byte0]: 35
7859 12:32:05.173144 [Byte1]: 35
7860 12:32:05.173807
7861 12:32:05.176781 Set Vref, RX VrefLevel [Byte0]: 36
7862 12:32:05.179733 [Byte1]: 36
7863 12:32:05.180388
7864 12:32:05.183210 Set Vref, RX VrefLevel [Byte0]: 37
7865 12:32:05.186156 [Byte1]: 37
7866 12:32:05.190266
7867 12:32:05.190872 Set Vref, RX VrefLevel [Byte0]: 38
7868 12:32:05.193887 [Byte1]: 38
7869 12:32:05.198174
7870 12:32:05.198806 Set Vref, RX VrefLevel [Byte0]: 39
7871 12:32:05.201608 [Byte1]: 39
7872 12:32:05.205703
7873 12:32:05.206300 Set Vref, RX VrefLevel [Byte0]: 40
7874 12:32:05.208692 [Byte1]: 40
7875 12:32:05.213446
7876 12:32:05.214045 Set Vref, RX VrefLevel [Byte0]: 41
7877 12:32:05.216576 [Byte1]: 41
7878 12:32:05.220742
7879 12:32:05.221289 Set Vref, RX VrefLevel [Byte0]: 42
7880 12:32:05.224086 [Byte1]: 42
7881 12:32:05.228676
7882 12:32:05.229117 Set Vref, RX VrefLevel [Byte0]: 43
7883 12:32:05.231743 [Byte1]: 43
7884 12:32:05.235954
7885 12:32:05.236424 Set Vref, RX VrefLevel [Byte0]: 44
7886 12:32:05.239332 [Byte1]: 44
7887 12:32:05.243600
7888 12:32:05.244023 Set Vref, RX VrefLevel [Byte0]: 45
7889 12:32:05.246899 [Byte1]: 45
7890 12:32:05.251359
7891 12:32:05.251442 Set Vref, RX VrefLevel [Byte0]: 46
7892 12:32:05.254228 [Byte1]: 46
7893 12:32:05.258321
7894 12:32:05.258404 Set Vref, RX VrefLevel [Byte0]: 47
7895 12:32:05.261818 [Byte1]: 47
7896 12:32:05.265972
7897 12:32:05.266056 Set Vref, RX VrefLevel [Byte0]: 48
7898 12:32:05.269600 [Byte1]: 48
7899 12:32:05.273595
7900 12:32:05.273678 Set Vref, RX VrefLevel [Byte0]: 49
7901 12:32:05.277207 [Byte1]: 49
7902 12:32:05.281486
7903 12:32:05.281571 Set Vref, RX VrefLevel [Byte0]: 50
7904 12:32:05.284521 [Byte1]: 50
7905 12:32:05.289200
7906 12:32:05.289287 Set Vref, RX VrefLevel [Byte0]: 51
7907 12:32:05.292196 [Byte1]: 51
7908 12:32:05.296738
7909 12:32:05.296822 Set Vref, RX VrefLevel [Byte0]: 52
7910 12:32:05.299886 [Byte1]: 52
7911 12:32:05.304049
7912 12:32:05.304137 Set Vref, RX VrefLevel [Byte0]: 53
7913 12:32:05.307607 [Byte1]: 53
7914 12:32:05.311971
7915 12:32:05.312076 Set Vref, RX VrefLevel [Byte0]: 54
7916 12:32:05.315016 [Byte1]: 54
7917 12:32:05.319264
7918 12:32:05.319350 Set Vref, RX VrefLevel [Byte0]: 55
7919 12:32:05.322837 [Byte1]: 55
7920 12:32:05.327042
7921 12:32:05.327127 Set Vref, RX VrefLevel [Byte0]: 56
7922 12:32:05.330509 [Byte1]: 56
7923 12:32:05.334797
7924 12:32:05.334881 Set Vref, RX VrefLevel [Byte0]: 57
7925 12:32:05.338320 [Byte1]: 57
7926 12:32:05.342340
7927 12:32:05.342440 Set Vref, RX VrefLevel [Byte0]: 58
7928 12:32:05.345927 [Byte1]: 58
7929 12:32:05.350069
7930 12:32:05.350144 Set Vref, RX VrefLevel [Byte0]: 59
7931 12:32:05.352993 [Byte1]: 59
7932 12:32:05.357569
7933 12:32:05.357650 Set Vref, RX VrefLevel [Byte0]: 60
7934 12:32:05.361116 [Byte1]: 60
7935 12:32:05.365463
7936 12:32:05.365547 Set Vref, RX VrefLevel [Byte0]: 61
7937 12:32:05.368689 [Byte1]: 61
7938 12:32:05.373112
7939 12:32:05.373220 Set Vref, RX VrefLevel [Byte0]: 62
7940 12:32:05.375891 [Byte1]: 62
7941 12:32:05.380607
7942 12:32:05.380683 Set Vref, RX VrefLevel [Byte0]: 63
7943 12:32:05.383565 [Byte1]: 63
7944 12:32:05.388303
7945 12:32:05.388386 Set Vref, RX VrefLevel [Byte0]: 64
7946 12:32:05.391223 [Byte1]: 64
7947 12:32:05.395885
7948 12:32:05.395996 Set Vref, RX VrefLevel [Byte0]: 65
7949 12:32:05.398869 [Byte1]: 65
7950 12:32:05.403105
7951 12:32:05.403189 Set Vref, RX VrefLevel [Byte0]: 66
7952 12:32:05.406615 [Byte1]: 66
7953 12:32:05.410684
7954 12:32:05.410781 Set Vref, RX VrefLevel [Byte0]: 67
7955 12:32:05.414097 [Byte1]: 67
7956 12:32:05.418829
7957 12:32:05.418941 Set Vref, RX VrefLevel [Byte0]: 68
7958 12:32:05.421850 [Byte1]: 68
7959 12:32:05.426223
7960 12:32:05.426305 Set Vref, RX VrefLevel [Byte0]: 69
7961 12:32:05.429639 [Byte1]: 69
7962 12:32:05.433642
7963 12:32:05.433724 Set Vref, RX VrefLevel [Byte0]: 70
7964 12:32:05.437323 [Byte1]: 70
7965 12:32:05.441460
7966 12:32:05.441542 Set Vref, RX VrefLevel [Byte0]: 71
7967 12:32:05.444454 [Byte1]: 71
7968 12:32:05.449257
7969 12:32:05.449340 Set Vref, RX VrefLevel [Byte0]: 72
7970 12:32:05.452231 [Byte1]: 72
7971 12:32:05.456379
7972 12:32:05.456462 Set Vref, RX VrefLevel [Byte0]: 73
7973 12:32:05.459929 [Byte1]: 73
7974 12:32:05.464541
7975 12:32:05.464623 Set Vref, RX VrefLevel [Byte0]: 74
7976 12:32:05.467470 [Byte1]: 74
7977 12:32:05.472052
7978 12:32:05.472148 Set Vref, RX VrefLevel [Byte0]: 75
7979 12:32:05.474997 [Byte1]: 75
7980 12:32:05.479633
7981 12:32:05.479737 Set Vref, RX VrefLevel [Byte0]: 76
7982 12:32:05.482739 [Byte1]: 76
7983 12:32:05.487305
7984 12:32:05.487409 Final RX Vref Byte 0 = 57 to rank0
7985 12:32:05.490156 Final RX Vref Byte 1 = 59 to rank0
7986 12:32:05.493722 Final RX Vref Byte 0 = 57 to rank1
7987 12:32:05.496741 Final RX Vref Byte 1 = 59 to rank1==
7988 12:32:05.500326 Dram Type= 6, Freq= 0, CH_0, rank 0
7989 12:32:05.506747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 12:32:05.506852 ==
7991 12:32:05.506949 DQS Delay:
7992 12:32:05.509707 DQS0 = 0, DQS1 = 0
7993 12:32:05.509810 DQM Delay:
7994 12:32:05.509903 DQM0 = 128, DQM1 = 124
7995 12:32:05.513486 DQ Delay:
7996 12:32:05.516730 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7997 12:32:05.519949 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7998 12:32:05.523487 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7999 12:32:05.526387 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =132
8000 12:32:05.526489
8001 12:32:05.526580
8002 12:32:05.526667
8003 12:32:05.529464 [DramC_TX_OE_Calibration] TA2
8004 12:32:05.533079 Original DQ_B0 (3 6) =30, OEN = 27
8005 12:32:05.535960 Original DQ_B1 (3 6) =30, OEN = 27
8006 12:32:05.539555 24, 0x0, End_B0=24 End_B1=24
8007 12:32:05.543053 25, 0x0, End_B0=25 End_B1=25
8008 12:32:05.543158 26, 0x0, End_B0=26 End_B1=26
8009 12:32:05.546234 27, 0x0, End_B0=27 End_B1=27
8010 12:32:05.549042 28, 0x0, End_B0=28 End_B1=28
8011 12:32:05.552394 29, 0x0, End_B0=29 End_B1=29
8012 12:32:05.555981 30, 0x0, End_B0=30 End_B1=30
8013 12:32:05.556118 31, 0x4141, End_B0=30 End_B1=30
8014 12:32:05.558984 Byte0 end_step=30 best_step=27
8015 12:32:05.562319 Byte1 end_step=30 best_step=27
8016 12:32:05.565916 Byte0 TX OE(2T, 0.5T) = (3, 3)
8017 12:32:05.568880 Byte1 TX OE(2T, 0.5T) = (3, 3)
8018 12:32:05.568974
8019 12:32:05.569049
8020 12:32:05.575250 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8021 12:32:05.579010 CH0 RK0: MR19=303, MR18=1512
8022 12:32:05.585775 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
8023 12:32:05.585912
8024 12:32:05.588611 ----->DramcWriteLeveling(PI) begin...
8025 12:32:05.588796 ==
8026 12:32:05.592002 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 12:32:05.595613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 12:32:05.598629 ==
8029 12:32:05.598853 Write leveling (Byte 0): 33 => 33
8030 12:32:05.602273 Write leveling (Byte 1): 26 => 26
8031 12:32:05.605230 DramcWriteLeveling(PI) end<-----
8032 12:32:05.605544
8033 12:32:05.605813 ==
8034 12:32:05.608746 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 12:32:05.615786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 12:32:05.616290 ==
8037 12:32:05.618585 [Gating] SW mode calibration
8038 12:32:05.625404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8039 12:32:05.628519 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8040 12:32:05.635393 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 12:32:05.638596 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 12:32:05.641586 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8043 12:32:05.648377 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8044 12:32:05.651893 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8045 12:32:05.655372 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
8046 12:32:05.661406 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 12:32:05.664834 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 12:32:05.667796 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 12:32:05.674814 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8050 12:32:05.677690 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8051 12:32:05.681210 1 5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
8052 12:32:05.687781 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8053 12:32:05.690667 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8054 12:32:05.694065 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 12:32:05.700598 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 12:32:05.704261 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 12:32:05.707315 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 12:32:05.713833 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8059 12:32:05.717499 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8060 12:32:05.720348 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8061 12:32:05.726793 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8062 12:32:05.730409 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 12:32:05.733559 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 12:32:05.740289 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 12:32:05.743353 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8066 12:32:05.746819 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8067 12:32:05.753773 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8068 12:32:05.756923 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8069 12:32:05.759851 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8070 12:32:05.766464 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 12:32:05.769968 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 12:32:05.772949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 12:32:05.779673 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 12:32:05.783157 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 12:32:05.786159 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 12:32:05.792634 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 12:32:05.796090 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 12:32:05.799369 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 12:32:05.805930 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 12:32:05.809140 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 12:32:05.812694 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8082 12:32:05.819434 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8083 12:32:05.822361 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8084 12:32:05.825752 Total UI for P1: 0, mck2ui 16
8085 12:32:05.829060 best dqsien dly found for B0: ( 1, 9, 6)
8086 12:32:05.832541 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8087 12:32:05.838979 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8088 12:32:05.842027 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8089 12:32:05.845628 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 12:32:05.848601 Total UI for P1: 0, mck2ui 16
8091 12:32:05.852346 best dqsien dly found for B1: ( 1, 9, 22)
8092 12:32:05.855138 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8093 12:32:05.861801 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8094 12:32:05.862240
8095 12:32:05.865317 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8096 12:32:05.868366 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8097 12:32:05.872000 [Gating] SW calibration Done
8098 12:32:05.872629 ==
8099 12:32:05.875101 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 12:32:05.878695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 12:32:05.879236 ==
8102 12:32:05.881634 RX Vref Scan: 0
8103 12:32:05.882152
8104 12:32:05.882491 RX Vref 0 -> 0, step: 1
8105 12:32:05.882808
8106 12:32:05.885160 RX Delay 0 -> 252, step: 8
8107 12:32:05.888501 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8108 12:32:05.891975 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8109 12:32:05.898023 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8110 12:32:05.901579 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8111 12:32:05.904574 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8112 12:32:05.908008 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8113 12:32:05.914375 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8114 12:32:05.917922 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8115 12:32:05.920871 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8116 12:32:05.924395 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8117 12:32:05.927871 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8118 12:32:05.934018 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8119 12:32:05.937460 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8120 12:32:05.940985 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8121 12:32:05.943937 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8122 12:32:05.950574 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8123 12:32:05.951007 ==
8124 12:32:05.954166 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 12:32:05.957197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 12:32:05.957743 ==
8127 12:32:05.958149 DQS Delay:
8128 12:32:05.960752 DQS0 = 0, DQS1 = 0
8129 12:32:05.961196 DQM Delay:
8130 12:32:05.963808 DQM0 = 133, DQM1 = 126
8131 12:32:05.964284 DQ Delay:
8132 12:32:05.967399 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8133 12:32:05.970330 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =139
8134 12:32:05.973832 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8135 12:32:05.976883 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =135
8136 12:32:05.977337
8137 12:32:05.980323
8138 12:32:05.980749 ==
8139 12:32:05.983780 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 12:32:05.987072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 12:32:05.987687 ==
8142 12:32:05.988303
8143 12:32:05.988864
8144 12:32:05.990040 TX Vref Scan disable
8145 12:32:05.990473 == TX Byte 0 ==
8146 12:32:05.997080 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8147 12:32:06.000090 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8148 12:32:06.000665 == TX Byte 1 ==
8149 12:32:06.006551 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8150 12:32:06.010296 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8151 12:32:06.010720 ==
8152 12:32:06.013233 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:32:06.016806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:32:06.017230 ==
8155 12:32:06.030680
8156 12:32:06.033826 TX Vref early break, caculate TX vref
8157 12:32:06.037418 TX Vref=16, minBit 3, minWin=23, winSum=380
8158 12:32:06.040375 TX Vref=18, minBit 9, minWin=23, winSum=385
8159 12:32:06.043661 TX Vref=20, minBit 0, minWin=24, winSum=399
8160 12:32:06.047242 TX Vref=22, minBit 0, minWin=24, winSum=404
8161 12:32:06.050337 TX Vref=24, minBit 1, minWin=25, winSum=412
8162 12:32:06.057051 TX Vref=26, minBit 3, minWin=25, winSum=420
8163 12:32:06.059996 TX Vref=28, minBit 4, minWin=25, winSum=419
8164 12:32:06.063711 TX Vref=30, minBit 1, minWin=25, winSum=416
8165 12:32:06.066650 TX Vref=32, minBit 1, minWin=24, winSum=408
8166 12:32:06.070249 TX Vref=34, minBit 0, minWin=24, winSum=398
8167 12:32:06.076546 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 26
8168 12:32:06.076979
8169 12:32:06.079972 Final TX Range 0 Vref 26
8170 12:32:06.080430
8171 12:32:06.080858 ==
8172 12:32:06.083680 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 12:32:06.086373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 12:32:06.086837 ==
8175 12:32:06.087219
8176 12:32:06.087569
8177 12:32:06.089793 TX Vref Scan disable
8178 12:32:06.096604 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8179 12:32:06.097112 == TX Byte 0 ==
8180 12:32:06.099515 u2DelayCellOfst[0]=10 cells (3 PI)
8181 12:32:06.103008 u2DelayCellOfst[1]=14 cells (4 PI)
8182 12:32:06.106238 u2DelayCellOfst[2]=7 cells (2 PI)
8183 12:32:06.109433 u2DelayCellOfst[3]=7 cells (2 PI)
8184 12:32:06.113047 u2DelayCellOfst[4]=3 cells (1 PI)
8185 12:32:06.115989 u2DelayCellOfst[5]=0 cells (0 PI)
8186 12:32:06.119677 u2DelayCellOfst[6]=14 cells (4 PI)
8187 12:32:06.122618 u2DelayCellOfst[7]=14 cells (4 PI)
8188 12:32:06.126137 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8189 12:32:06.129519 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8190 12:32:06.132482 == TX Byte 1 ==
8191 12:32:06.136158 u2DelayCellOfst[8]=0 cells (0 PI)
8192 12:32:06.139116 u2DelayCellOfst[9]=0 cells (0 PI)
8193 12:32:06.142191 u2DelayCellOfst[10]=7 cells (2 PI)
8194 12:32:06.145888 u2DelayCellOfst[11]=3 cells (1 PI)
8195 12:32:06.146497 u2DelayCellOfst[12]=10 cells (3 PI)
8196 12:32:06.148751 u2DelayCellOfst[13]=10 cells (3 PI)
8197 12:32:06.152078 u2DelayCellOfst[14]=14 cells (4 PI)
8198 12:32:06.155645 u2DelayCellOfst[15]=10 cells (3 PI)
8199 12:32:06.161911 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8200 12:32:06.165459 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8201 12:32:06.168970 DramC Write-DBI on
8202 12:32:06.169422 ==
8203 12:32:06.171833 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 12:32:06.175357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 12:32:06.175791 ==
8206 12:32:06.176308
8207 12:32:06.176718
8208 12:32:06.178951 TX Vref Scan disable
8209 12:32:06.179402 == TX Byte 0 ==
8210 12:32:06.185340 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8211 12:32:06.185779 == TX Byte 1 ==
8212 12:32:06.188172 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8213 12:32:06.191839 DramC Write-DBI off
8214 12:32:06.192327
8215 12:32:06.192757 [DATLAT]
8216 12:32:06.195239 Freq=1600, CH0 RK1
8217 12:32:06.195672
8218 12:32:06.196282 DATLAT Default: 0xf
8219 12:32:06.198670 0, 0xFFFF, sum = 0
8220 12:32:06.199145 1, 0xFFFF, sum = 0
8221 12:32:06.201593 2, 0xFFFF, sum = 0
8222 12:32:06.204997 3, 0xFFFF, sum = 0
8223 12:32:06.205653 4, 0xFFFF, sum = 0
8224 12:32:06.208503 5, 0xFFFF, sum = 0
8225 12:32:06.209062 6, 0xFFFF, sum = 0
8226 12:32:06.211584 7, 0xFFFF, sum = 0
8227 12:32:06.212207 8, 0xFFFF, sum = 0
8228 12:32:06.214554 9, 0xFFFF, sum = 0
8229 12:32:06.215148 10, 0xFFFF, sum = 0
8230 12:32:06.217775 11, 0xFFFF, sum = 0
8231 12:32:06.218205 12, 0xFFFF, sum = 0
8232 12:32:06.221365 13, 0xFFFF, sum = 0
8233 12:32:06.221793 14, 0x0, sum = 1
8234 12:32:06.224262 15, 0x0, sum = 2
8235 12:32:06.224745 16, 0x0, sum = 3
8236 12:32:06.227756 17, 0x0, sum = 4
8237 12:32:06.228316 best_step = 15
8238 12:32:06.228735
8239 12:32:06.229065 ==
8240 12:32:06.231339 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 12:32:06.237813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 12:32:06.238282 ==
8243 12:32:06.238631 RX Vref Scan: 0
8244 12:32:06.238951
8245 12:32:06.241413 RX Vref 0 -> 0, step: 1
8246 12:32:06.241834
8247 12:32:06.244528 RX Delay 11 -> 252, step: 4
8248 12:32:06.247398 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8249 12:32:06.251119 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8250 12:32:06.254589 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8251 12:32:06.261092 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8252 12:32:06.264160 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8253 12:32:06.267736 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8254 12:32:06.270720 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8255 12:32:06.274124 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8256 12:32:06.280728 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8257 12:32:06.283549 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8258 12:32:06.286960 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8259 12:32:06.290537 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8260 12:32:06.296979 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8261 12:32:06.300066 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8262 12:32:06.303460 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8263 12:32:06.306348 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8264 12:32:06.306923 ==
8265 12:32:06.309829 Dram Type= 6, Freq= 0, CH_0, rank 1
8266 12:32:06.316632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 12:32:06.317160 ==
8268 12:32:06.317676 DQS Delay:
8269 12:32:06.319570 DQS0 = 0, DQS1 = 0
8270 12:32:06.320156 DQM Delay:
8271 12:32:06.323166 DQM0 = 129, DQM1 = 124
8272 12:32:06.323682 DQ Delay:
8273 12:32:06.326255 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8274 12:32:06.329792 DQ4 =130, DQ5 =120, DQ6 =140, DQ7 =134
8275 12:32:06.332881 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8276 12:32:06.336328 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8277 12:32:06.336766
8278 12:32:06.337139
8279 12:32:06.337485
8280 12:32:06.339643 [DramC_TX_OE_Calibration] TA2
8281 12:32:06.342716 Original DQ_B0 (3 6) =30, OEN = 27
8282 12:32:06.346192 Original DQ_B1 (3 6) =30, OEN = 27
8283 12:32:06.349125 24, 0x0, End_B0=24 End_B1=24
8284 12:32:06.352665 25, 0x0, End_B0=25 End_B1=25
8285 12:32:06.353220 26, 0x0, End_B0=26 End_B1=26
8286 12:32:06.356402 27, 0x0, End_B0=27 End_B1=27
8287 12:32:06.359319 28, 0x0, End_B0=28 End_B1=28
8288 12:32:06.362762 29, 0x0, End_B0=29 End_B1=29
8289 12:32:06.365819 30, 0x0, End_B0=30 End_B1=30
8290 12:32:06.366267 31, 0x4141, End_B0=30 End_B1=30
8291 12:32:06.369447 Byte0 end_step=30 best_step=27
8292 12:32:06.372497 Byte1 end_step=30 best_step=27
8293 12:32:06.375500 Byte0 TX OE(2T, 0.5T) = (3, 3)
8294 12:32:06.379107 Byte1 TX OE(2T, 0.5T) = (3, 3)
8295 12:32:06.379535
8296 12:32:06.379878
8297 12:32:06.385597 [DQSOSCAuto] RK1, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8298 12:32:06.388728 CH0 RK1: MR19=303, MR18=1312
8299 12:32:06.395439 CH0_RK1: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8300 12:32:06.399008 [RxdqsGatingPostProcess] freq 1600
8301 12:32:06.405553 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8302 12:32:06.408993 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 12:32:06.409529 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 12:32:06.411775 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 12:32:06.415265 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 12:32:06.418171 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 12:32:06.421715 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 12:32:06.424723 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 12:32:06.428429 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 12:32:06.431321 Pre-setting of DQS Precalculation
8311 12:32:06.438143 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8312 12:32:06.438709 ==
8313 12:32:06.441504 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 12:32:06.444737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 12:32:06.445235 ==
8316 12:32:06.451477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 12:32:06.455033 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 12:32:06.458031 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 12:32:06.464463 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 12:32:06.473315 [CA 0] Center 42 (13~72) winsize 60
8321 12:32:06.476866 [CA 1] Center 42 (13~72) winsize 60
8322 12:32:06.480291 [CA 2] Center 38 (9~68) winsize 60
8323 12:32:06.483047 [CA 3] Center 37 (8~67) winsize 60
8324 12:32:06.486400 [CA 4] Center 38 (8~68) winsize 61
8325 12:32:06.489708 [CA 5] Center 37 (7~67) winsize 61
8326 12:32:06.490145
8327 12:32:06.493100 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8328 12:32:06.493521
8329 12:32:06.496613 [CATrainingPosCal] consider 1 rank data
8330 12:32:06.499314 u2DelayCellTimex100 = 271/100 ps
8331 12:32:06.506573 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8332 12:32:06.509411 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8333 12:32:06.512837 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8334 12:32:06.516108 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8335 12:32:06.519363 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8336 12:32:06.523015 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8337 12:32:06.523457
8338 12:32:06.526238 CA PerBit enable=1, Macro0, CA PI delay=37
8339 12:32:06.526666
8340 12:32:06.529341 [CBTSetCACLKResult] CA Dly = 37
8341 12:32:06.532951 CS Dly: 8 (0~39)
8342 12:32:06.535890 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 12:32:06.539538 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 12:32:06.539965 ==
8345 12:32:06.542742 Dram Type= 6, Freq= 0, CH_1, rank 1
8346 12:32:06.549003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 12:32:06.549435 ==
8348 12:32:06.552632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8349 12:32:06.559002 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8350 12:32:06.562096 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8351 12:32:06.568422 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8352 12:32:06.576318 [CA 0] Center 42 (12~72) winsize 61
8353 12:32:06.579858 [CA 1] Center 42 (12~72) winsize 61
8354 12:32:06.582898 [CA 2] Center 38 (8~68) winsize 61
8355 12:32:06.586454 [CA 3] Center 37 (7~67) winsize 61
8356 12:32:06.589399 [CA 4] Center 37 (8~67) winsize 60
8357 12:32:06.593090 [CA 5] Center 37 (7~67) winsize 61
8358 12:32:06.593515
8359 12:32:06.595960 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8360 12:32:06.596419
8361 12:32:06.599386 [CATrainingPosCal] consider 2 rank data
8362 12:32:06.602866 u2DelayCellTimex100 = 271/100 ps
8363 12:32:06.609245 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8364 12:32:06.612638 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8365 12:32:06.615660 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8366 12:32:06.619135 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8367 12:32:06.622453 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8368 12:32:06.625415 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8369 12:32:06.625631
8370 12:32:06.629062 CA PerBit enable=1, Macro0, CA PI delay=37
8371 12:32:06.629287
8372 12:32:06.631957 [CBTSetCACLKResult] CA Dly = 37
8373 12:32:06.635152 CS Dly: 9 (0~42)
8374 12:32:06.638764 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8375 12:32:06.641776 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8376 12:32:06.642001
8377 12:32:06.645360 ----->DramcWriteLeveling(PI) begin...
8378 12:32:06.645586 ==
8379 12:32:06.648262 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 12:32:06.654830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 12:32:06.655054 ==
8382 12:32:06.658276 Write leveling (Byte 0): 24 => 24
8383 12:32:06.661958 Write leveling (Byte 1): 27 => 27
8384 12:32:06.664973 DramcWriteLeveling(PI) end<-----
8385 12:32:06.665196
8386 12:32:06.665373 ==
8387 12:32:06.667993 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 12:32:06.671585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 12:32:06.671810 ==
8390 12:32:06.675038 [Gating] SW mode calibration
8391 12:32:06.681809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8392 12:32:06.688294 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8393 12:32:06.691247 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 12:32:06.694787 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 12:32:06.701314 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8396 12:32:06.704441 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8397 12:32:06.708074 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 12:32:06.714306 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 12:32:06.717851 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 12:32:06.720964 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 12:32:06.727329 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 12:32:06.730829 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 12:32:06.734358 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8404 12:32:06.740954 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8405 12:32:06.743978 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8406 12:32:06.747508 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 12:32:06.754047 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 12:32:06.756968 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 12:32:06.760570 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 12:32:06.767278 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 12:32:06.770157 1 6 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8412 12:32:06.774103 1 6 12 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
8413 12:32:06.780444 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 12:32:06.783535 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 12:32:06.787153 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 12:32:06.793776 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 12:32:06.796733 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 12:32:06.800456 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 12:32:06.806934 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 12:32:06.809640 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8421 12:32:06.813286 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8422 12:32:06.820016 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 12:32:06.823066 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 12:32:06.826144 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 12:32:06.832974 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 12:32:06.836415 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 12:32:06.839791 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 12:32:06.846235 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 12:32:06.849287 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 12:32:06.853105 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 12:32:06.859606 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 12:32:06.862579 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 12:32:06.865712 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 12:32:06.872377 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 12:32:06.876095 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 12:32:06.878978 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8437 12:32:06.885788 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 12:32:06.886448 Total UI for P1: 0, mck2ui 16
8439 12:32:06.892427 best dqsien dly found for B0: ( 1, 9, 12)
8440 12:32:06.892930 Total UI for P1: 0, mck2ui 16
8441 12:32:06.898880 best dqsien dly found for B1: ( 1, 9, 12)
8442 12:32:06.902093 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8443 12:32:06.905176 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8444 12:32:06.905613
8445 12:32:06.908709 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8446 12:32:06.911704 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8447 12:32:06.915103 [Gating] SW calibration Done
8448 12:32:06.915534 ==
8449 12:32:06.918478 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 12:32:06.922157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 12:32:06.922594 ==
8452 12:32:06.925053 RX Vref Scan: 0
8453 12:32:06.925481
8454 12:32:06.925822 RX Vref 0 -> 0, step: 1
8455 12:32:06.926142
8456 12:32:06.928340 RX Delay 0 -> 252, step: 8
8457 12:32:06.931925 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8458 12:32:06.938117 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8459 12:32:06.941511 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8460 12:32:06.944960 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8461 12:32:06.947941 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8462 12:32:06.954399 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8463 12:32:06.958002 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8464 12:32:06.961003 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8465 12:32:06.964102 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8466 12:32:06.967867 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8467 12:32:06.974075 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8468 12:32:06.977567 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8469 12:32:06.981016 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8470 12:32:06.983825 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8471 12:32:06.990756 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8472 12:32:06.993593 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8473 12:32:06.994022 ==
8474 12:32:06.997209 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 12:32:07.000298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 12:32:07.000733 ==
8477 12:32:07.003871 DQS Delay:
8478 12:32:07.004459 DQS0 = 0, DQS1 = 0
8479 12:32:07.004978 DQM Delay:
8480 12:32:07.006909 DQM0 = 134, DQM1 = 130
8481 12:32:07.007338 DQ Delay:
8482 12:32:07.010353 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8483 12:32:07.014007 DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =127
8484 12:32:07.016887 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8485 12:32:07.023828 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8486 12:32:07.024409
8487 12:32:07.024761
8488 12:32:07.025081 ==
8489 12:32:07.026727 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 12:32:07.030444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 12:32:07.031130 ==
8492 12:32:07.031502
8493 12:32:07.031978
8494 12:32:07.033868 TX Vref Scan disable
8495 12:32:07.034343 == TX Byte 0 ==
8496 12:32:07.040191 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8497 12:32:07.043566 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8498 12:32:07.046492 == TX Byte 1 ==
8499 12:32:07.049989 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8500 12:32:07.052958 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8501 12:32:07.053385 ==
8502 12:32:07.056492 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 12:32:07.059344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 12:32:07.062965 ==
8505 12:32:07.074312
8506 12:32:07.077301 TX Vref early break, caculate TX vref
8507 12:32:07.080340 TX Vref=16, minBit 8, minWin=21, winSum=364
8508 12:32:07.084015 TX Vref=18, minBit 9, minWin=21, winSum=377
8509 12:32:07.087429 TX Vref=20, minBit 5, minWin=23, winSum=383
8510 12:32:07.090484 TX Vref=22, minBit 8, minWin=23, winSum=398
8511 12:32:07.093672 TX Vref=24, minBit 8, minWin=23, winSum=407
8512 12:32:07.100175 TX Vref=26, minBit 8, minWin=24, winSum=413
8513 12:32:07.103890 TX Vref=28, minBit 8, minWin=25, winSum=417
8514 12:32:07.106765 TX Vref=30, minBit 9, minWin=24, winSum=411
8515 12:32:07.110433 TX Vref=32, minBit 9, minWin=23, winSum=405
8516 12:32:07.113245 TX Vref=34, minBit 0, minWin=23, winSum=394
8517 12:32:07.120193 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8518 12:32:07.120662
8519 12:32:07.123053 Final TX Range 0 Vref 28
8520 12:32:07.123493
8521 12:32:07.123949 ==
8522 12:32:07.126541 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 12:32:07.130060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 12:32:07.130503 ==
8525 12:32:07.130942
8526 12:32:07.131354
8527 12:32:07.133130 TX Vref Scan disable
8528 12:32:07.139437 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8529 12:32:07.139875 == TX Byte 0 ==
8530 12:32:07.142763 u2DelayCellOfst[0]=14 cells (4 PI)
8531 12:32:07.146001 u2DelayCellOfst[1]=10 cells (3 PI)
8532 12:32:07.149483 u2DelayCellOfst[2]=0 cells (0 PI)
8533 12:32:07.152898 u2DelayCellOfst[3]=7 cells (2 PI)
8534 12:32:07.156049 u2DelayCellOfst[4]=10 cells (3 PI)
8535 12:32:07.159513 u2DelayCellOfst[5]=18 cells (5 PI)
8536 12:32:07.162486 u2DelayCellOfst[6]=18 cells (5 PI)
8537 12:32:07.166089 u2DelayCellOfst[7]=7 cells (2 PI)
8538 12:32:07.169160 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8539 12:32:07.172578 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8540 12:32:07.175990 == TX Byte 1 ==
8541 12:32:07.179034 u2DelayCellOfst[8]=0 cells (0 PI)
8542 12:32:07.182508 u2DelayCellOfst[9]=0 cells (0 PI)
8543 12:32:07.186054 u2DelayCellOfst[10]=10 cells (3 PI)
8544 12:32:07.188963 u2DelayCellOfst[11]=3 cells (1 PI)
8545 12:32:07.192512 u2DelayCellOfst[12]=10 cells (3 PI)
8546 12:32:07.192944 u2DelayCellOfst[13]=10 cells (3 PI)
8547 12:32:07.196021 u2DelayCellOfst[14]=14 cells (4 PI)
8548 12:32:07.199013 u2DelayCellOfst[15]=14 cells (4 PI)
8549 12:32:07.205456 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8550 12:32:07.209145 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8551 12:32:07.212149 DramC Write-DBI on
8552 12:32:07.212580 ==
8553 12:32:07.214954 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 12:32:07.218388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 12:32:07.218824 ==
8556 12:32:07.219169
8557 12:32:07.219487
8558 12:32:07.221953 TX Vref Scan disable
8559 12:32:07.222385 == TX Byte 0 ==
8560 12:32:07.228898 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8561 12:32:07.229388 == TX Byte 1 ==
8562 12:32:07.232457 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8563 12:32:07.235070 DramC Write-DBI off
8564 12:32:07.235501
8565 12:32:07.235842 [DATLAT]
8566 12:32:07.238543 Freq=1600, CH1 RK0
8567 12:32:07.238975
8568 12:32:07.239321 DATLAT Default: 0xf
8569 12:32:07.241687 0, 0xFFFF, sum = 0
8570 12:32:07.242124 1, 0xFFFF, sum = 0
8571 12:32:07.245126 2, 0xFFFF, sum = 0
8572 12:32:07.245564 3, 0xFFFF, sum = 0
8573 12:32:07.248654 4, 0xFFFF, sum = 0
8574 12:32:07.249092 5, 0xFFFF, sum = 0
8575 12:32:07.252053 6, 0xFFFF, sum = 0
8576 12:32:07.254995 7, 0xFFFF, sum = 0
8577 12:32:07.255431 8, 0xFFFF, sum = 0
8578 12:32:07.258464 9, 0xFFFF, sum = 0
8579 12:32:07.258901 10, 0xFFFF, sum = 0
8580 12:32:07.262034 11, 0xFFFF, sum = 0
8581 12:32:07.262468 12, 0xFFFF, sum = 0
8582 12:32:07.265068 13, 0xFFFF, sum = 0
8583 12:32:07.265565 14, 0x0, sum = 1
8584 12:32:07.268592 15, 0x0, sum = 2
8585 12:32:07.269028 16, 0x0, sum = 3
8586 12:32:07.271589 17, 0x0, sum = 4
8587 12:32:07.272025 best_step = 15
8588 12:32:07.272444
8589 12:32:07.272768 ==
8590 12:32:07.275135 Dram Type= 6, Freq= 0, CH_1, rank 0
8591 12:32:07.278548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8592 12:32:07.281485 ==
8593 12:32:07.281918 RX Vref Scan: 1
8594 12:32:07.282263
8595 12:32:07.284666 Set Vref Range= 24 -> 127
8596 12:32:07.285098
8597 12:32:07.288126 RX Vref 24 -> 127, step: 1
8598 12:32:07.288573
8599 12:32:07.288919 RX Delay 11 -> 252, step: 4
8600 12:32:07.289239
8601 12:32:07.291337 Set Vref, RX VrefLevel [Byte0]: 24
8602 12:32:07.294655 [Byte1]: 24
8603 12:32:07.298347
8604 12:32:07.298781 Set Vref, RX VrefLevel [Byte0]: 25
8605 12:32:07.301638 [Byte1]: 25
8606 12:32:07.306342
8607 12:32:07.306983 Set Vref, RX VrefLevel [Byte0]: 26
8608 12:32:07.309437 [Byte1]: 26
8609 12:32:07.313611
8610 12:32:07.314038 Set Vref, RX VrefLevel [Byte0]: 27
8611 12:32:07.317168 [Byte1]: 27
8612 12:32:07.321394
8613 12:32:07.321952 Set Vref, RX VrefLevel [Byte0]: 28
8614 12:32:07.324807 [Byte1]: 28
8615 12:32:07.329080
8616 12:32:07.329497 Set Vref, RX VrefLevel [Byte0]: 29
8617 12:32:07.332059 [Byte1]: 29
8618 12:32:07.336679
8619 12:32:07.337114 Set Vref, RX VrefLevel [Byte0]: 30
8620 12:32:07.340069 [Byte1]: 30
8621 12:32:07.344217
8622 12:32:07.344636 Set Vref, RX VrefLevel [Byte0]: 31
8623 12:32:07.347195 [Byte1]: 31
8624 12:32:07.351822
8625 12:32:07.352284 Set Vref, RX VrefLevel [Byte0]: 32
8626 12:32:07.354780 [Byte1]: 32
8627 12:32:07.359529
8628 12:32:07.359952 Set Vref, RX VrefLevel [Byte0]: 33
8629 12:32:07.363135 [Byte1]: 33
8630 12:32:07.367059
8631 12:32:07.367481 Set Vref, RX VrefLevel [Byte0]: 34
8632 12:32:07.369970 [Byte1]: 34
8633 12:32:07.374857
8634 12:32:07.375275 Set Vref, RX VrefLevel [Byte0]: 35
8635 12:32:07.377689 [Byte1]: 35
8636 12:32:07.382401
8637 12:32:07.382819 Set Vref, RX VrefLevel [Byte0]: 36
8638 12:32:07.385427 [Byte1]: 36
8639 12:32:07.389570
8640 12:32:07.389992 Set Vref, RX VrefLevel [Byte0]: 37
8641 12:32:07.396241 [Byte1]: 37
8642 12:32:07.396663
8643 12:32:07.399766 Set Vref, RX VrefLevel [Byte0]: 38
8644 12:32:07.402848 [Byte1]: 38
8645 12:32:07.403269
8646 12:32:07.406279 Set Vref, RX VrefLevel [Byte0]: 39
8647 12:32:07.409892 [Byte1]: 39
8648 12:32:07.412706
8649 12:32:07.413125 Set Vref, RX VrefLevel [Byte0]: 40
8650 12:32:07.415797 [Byte1]: 40
8651 12:32:07.420607
8652 12:32:07.421026 Set Vref, RX VrefLevel [Byte0]: 41
8653 12:32:07.423946 [Byte1]: 41
8654 12:32:07.427956
8655 12:32:07.428539 Set Vref, RX VrefLevel [Byte0]: 42
8656 12:32:07.431382 [Byte1]: 42
8657 12:32:07.435333
8658 12:32:07.435765 Set Vref, RX VrefLevel [Byte0]: 43
8659 12:32:07.438812 [Byte1]: 43
8660 12:32:07.442986
8661 12:32:07.443406 Set Vref, RX VrefLevel [Byte0]: 44
8662 12:32:07.446418 [Byte1]: 44
8663 12:32:07.450618
8664 12:32:07.451040 Set Vref, RX VrefLevel [Byte0]: 45
8665 12:32:07.454023 [Byte1]: 45
8666 12:32:07.458679
8667 12:32:07.459100 Set Vref, RX VrefLevel [Byte0]: 46
8668 12:32:07.461472 [Byte1]: 46
8669 12:32:07.466212
8670 12:32:07.466632 Set Vref, RX VrefLevel [Byte0]: 47
8671 12:32:07.469361 [Byte1]: 47
8672 12:32:07.473875
8673 12:32:07.474300 Set Vref, RX VrefLevel [Byte0]: 48
8674 12:32:07.476832 [Byte1]: 48
8675 12:32:07.481015
8676 12:32:07.481435 Set Vref, RX VrefLevel [Byte0]: 49
8677 12:32:07.484519 [Byte1]: 49
8678 12:32:07.488860
8679 12:32:07.489408 Set Vref, RX VrefLevel [Byte0]: 50
8680 12:32:07.492388 [Byte1]: 50
8681 12:32:07.496409
8682 12:32:07.496834 Set Vref, RX VrefLevel [Byte0]: 51
8683 12:32:07.499350 [Byte1]: 51
8684 12:32:07.504104
8685 12:32:07.504530 Set Vref, RX VrefLevel [Byte0]: 52
8686 12:32:07.507441 [Byte1]: 52
8687 12:32:07.511685
8688 12:32:07.512269 Set Vref, RX VrefLevel [Byte0]: 53
8689 12:32:07.514841 [Byte1]: 53
8690 12:32:07.519144
8691 12:32:07.519768 Set Vref, RX VrefLevel [Byte0]: 54
8692 12:32:07.522828 [Byte1]: 54
8693 12:32:07.526962
8694 12:32:07.527386 Set Vref, RX VrefLevel [Byte0]: 55
8695 12:32:07.530268 [Byte1]: 55
8696 12:32:07.535089
8697 12:32:07.535648 Set Vref, RX VrefLevel [Byte0]: 56
8698 12:32:07.537839 [Byte1]: 56
8699 12:32:07.541895
8700 12:32:07.542315 Set Vref, RX VrefLevel [Byte0]: 57
8701 12:32:07.545648 [Byte1]: 57
8702 12:32:07.549467
8703 12:32:07.549893 Set Vref, RX VrefLevel [Byte0]: 58
8704 12:32:07.553091 [Byte1]: 58
8705 12:32:07.557350
8706 12:32:07.557776 Set Vref, RX VrefLevel [Byte0]: 59
8707 12:32:07.560403 [Byte1]: 59
8708 12:32:07.564978
8709 12:32:07.565399 Set Vref, RX VrefLevel [Byte0]: 60
8710 12:32:07.568387 [Byte1]: 60
8711 12:32:07.572448
8712 12:32:07.572870 Set Vref, RX VrefLevel [Byte0]: 61
8713 12:32:07.575925 [Byte1]: 61
8714 12:32:07.580085
8715 12:32:07.580512 Set Vref, RX VrefLevel [Byte0]: 62
8716 12:32:07.583698 [Byte1]: 62
8717 12:32:07.587810
8718 12:32:07.588282 Set Vref, RX VrefLevel [Byte0]: 63
8719 12:32:07.591307 [Byte1]: 63
8720 12:32:07.595511
8721 12:32:07.595969 Set Vref, RX VrefLevel [Byte0]: 64
8722 12:32:07.598584 [Byte1]: 64
8723 12:32:07.603322
8724 12:32:07.603757 Set Vref, RX VrefLevel [Byte0]: 65
8725 12:32:07.606394 [Byte1]: 65
8726 12:32:07.610595
8727 12:32:07.611024 Set Vref, RX VrefLevel [Byte0]: 66
8728 12:32:07.614120 [Byte1]: 66
8729 12:32:07.618220
8730 12:32:07.618649 Set Vref, RX VrefLevel [Byte0]: 67
8731 12:32:07.621823 [Byte1]: 67
8732 12:32:07.625947
8733 12:32:07.626377 Set Vref, RX VrefLevel [Byte0]: 68
8734 12:32:07.628982 [Byte1]: 68
8735 12:32:07.633314
8736 12:32:07.633740 Set Vref, RX VrefLevel [Byte0]: 69
8737 12:32:07.636789 [Byte1]: 69
8738 12:32:07.641071
8739 12:32:07.641500 Set Vref, RX VrefLevel [Byte0]: 70
8740 12:32:07.644512 [Byte1]: 70
8741 12:32:07.648610
8742 12:32:07.649037 Final RX Vref Byte 0 = 59 to rank0
8743 12:32:07.652121 Final RX Vref Byte 1 = 62 to rank0
8744 12:32:07.655658 Final RX Vref Byte 0 = 59 to rank1
8745 12:32:07.658834 Final RX Vref Byte 1 = 62 to rank1==
8746 12:32:07.662161 Dram Type= 6, Freq= 0, CH_1, rank 0
8747 12:32:07.668714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 12:32:07.669262 ==
8749 12:32:07.669614 DQS Delay:
8750 12:32:07.669934 DQS0 = 0, DQS1 = 0
8751 12:32:07.671711 DQM Delay:
8752 12:32:07.672171 DQM0 = 131, DQM1 = 128
8753 12:32:07.675500 DQ Delay:
8754 12:32:07.679140 DQ0 =140, DQ1 =128, DQ2 =116, DQ3 =130
8755 12:32:07.682148 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8756 12:32:07.684896 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8757 12:32:07.688104 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8758 12:32:07.688538
8759 12:32:07.688878
8760 12:32:07.689193
8761 12:32:07.691714 [DramC_TX_OE_Calibration] TA2
8762 12:32:07.694785 Original DQ_B0 (3 6) =30, OEN = 27
8763 12:32:07.698299 Original DQ_B1 (3 6) =30, OEN = 27
8764 12:32:07.701255 24, 0x0, End_B0=24 End_B1=24
8765 12:32:07.705043 25, 0x0, End_B0=25 End_B1=25
8766 12:32:07.705477 26, 0x0, End_B0=26 End_B1=26
8767 12:32:07.708109 27, 0x0, End_B0=27 End_B1=27
8768 12:32:07.711032 28, 0x0, End_B0=28 End_B1=28
8769 12:32:07.714607 29, 0x0, End_B0=29 End_B1=29
8770 12:32:07.715045 30, 0x0, End_B0=30 End_B1=30
8771 12:32:07.717625 31, 0x4141, End_B0=30 End_B1=30
8772 12:32:07.720868 Byte0 end_step=30 best_step=27
8773 12:32:07.724362 Byte1 end_step=30 best_step=27
8774 12:32:07.727967 Byte0 TX OE(2T, 0.5T) = (3, 3)
8775 12:32:07.730888 Byte1 TX OE(2T, 0.5T) = (3, 3)
8776 12:32:07.731317
8777 12:32:07.731657
8778 12:32:07.737466 [DQSOSCAuto] RK0, (LSB)MR18= 0x912, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8779 12:32:07.741018 CH1 RK0: MR19=303, MR18=912
8780 12:32:07.747582 CH1_RK0: MR19=0x303, MR18=0x912, DQSOSC=400, MR23=63, INC=23, DEC=15
8781 12:32:07.748154
8782 12:32:07.751082 ----->DramcWriteLeveling(PI) begin...
8783 12:32:07.751628 ==
8784 12:32:07.753788 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 12:32:07.757287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 12:32:07.757738 ==
8787 12:32:07.760661 Write leveling (Byte 0): 24 => 24
8788 12:32:07.763517 Write leveling (Byte 1): 25 => 25
8789 12:32:07.767174 DramcWriteLeveling(PI) end<-----
8790 12:32:07.767612
8791 12:32:07.767956 ==
8792 12:32:07.770577 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 12:32:07.773974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 12:32:07.776759 ==
8795 12:32:07.777179 [Gating] SW mode calibration
8796 12:32:07.787420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8797 12:32:07.790294 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8798 12:32:07.793703 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 12:32:07.799876 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8800 12:32:07.803455 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8801 12:32:07.806481 1 4 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8802 12:32:07.813577 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 12:32:07.816479 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 12:32:07.819475 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 12:32:07.826682 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 12:32:07.829541 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 12:32:07.833153 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8808 12:32:07.839834 1 5 8 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8809 12:32:07.842703 1 5 12 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8810 12:32:07.846584 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8811 12:32:07.852611 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 12:32:07.856095 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 12:32:07.859262 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 12:32:07.866208 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 12:32:07.868959 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8816 12:32:07.875448 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8817 12:32:07.879139 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8818 12:32:07.882408 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 12:32:07.889074 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 12:32:07.891954 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 12:32:07.895474 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 12:32:07.902363 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 12:32:07.905178 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 12:32:07.908886 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8825 12:32:07.915315 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8826 12:32:07.918352 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8827 12:32:07.921875 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:32:07.928687 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 12:32:07.931937 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 12:32:07.934696 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 12:32:07.941599 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 12:32:07.945084 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 12:32:07.948051 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 12:32:07.954602 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 12:32:07.957841 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 12:32:07.961233 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 12:32:07.967929 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 12:32:07.971355 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 12:32:07.974339 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8840 12:32:07.980985 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8841 12:32:07.983910 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8842 12:32:07.987542 Total UI for P1: 0, mck2ui 16
8843 12:32:07.990903 best dqsien dly found for B0: ( 1, 9, 6)
8844 12:32:07.993991 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 12:32:07.997130 Total UI for P1: 0, mck2ui 16
8846 12:32:08.000187 best dqsien dly found for B1: ( 1, 9, 10)
8847 12:32:08.004022 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8848 12:32:08.007520 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8849 12:32:08.008098
8850 12:32:08.013763 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8851 12:32:08.016666 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 12:32:08.020204 [Gating] SW calibration Done
8853 12:32:08.020629 ==
8854 12:32:08.024109 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 12:32:08.027164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 12:32:08.027762 ==
8857 12:32:08.028161 RX Vref Scan: 0
8858 12:32:08.028543
8859 12:32:08.030621 RX Vref 0 -> 0, step: 1
8860 12:32:08.031150
8861 12:32:08.033353 RX Delay 0 -> 252, step: 8
8862 12:32:08.036782 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8863 12:32:08.040254 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8864 12:32:08.043828 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8865 12:32:08.050212 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8866 12:32:08.053410 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8867 12:32:08.056842 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8868 12:32:08.059741 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8869 12:32:08.066182 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8870 12:32:08.069877 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8871 12:32:08.073144 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8872 12:32:08.076158 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8873 12:32:08.080028 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8874 12:32:08.086034 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8875 12:32:08.089398 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8876 12:32:08.092900 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8877 12:32:08.095924 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8878 12:32:08.096407 ==
8879 12:32:08.099120 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 12:32:08.105917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 12:32:08.106442 ==
8882 12:32:08.106787 DQS Delay:
8883 12:32:08.109174 DQS0 = 0, DQS1 = 0
8884 12:32:08.109601 DQM Delay:
8885 12:32:08.112204 DQM0 = 133, DQM1 = 131
8886 12:32:08.112631 DQ Delay:
8887 12:32:08.115900 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8888 12:32:08.118792 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8889 12:32:08.122260 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8890 12:32:08.125430 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8891 12:32:08.125855
8892 12:32:08.126191
8893 12:32:08.126503 ==
8894 12:32:08.128387 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 12:32:08.135125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 12:32:08.135558 ==
8897 12:32:08.136134
8898 12:32:08.136594
8899 12:32:08.136911 TX Vref Scan disable
8900 12:32:08.139107 == TX Byte 0 ==
8901 12:32:08.142021 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8902 12:32:08.149008 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8903 12:32:08.149578 == TX Byte 1 ==
8904 12:32:08.151850 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8905 12:32:08.158589 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8906 12:32:08.159017 ==
8907 12:32:08.162110 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 12:32:08.164879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 12:32:08.165313 ==
8910 12:32:08.178806
8911 12:32:08.181814 TX Vref early break, caculate TX vref
8912 12:32:08.185329 TX Vref=16, minBit 9, minWin=21, winSum=375
8913 12:32:08.188276 TX Vref=18, minBit 9, minWin=22, winSum=385
8914 12:32:08.191741 TX Vref=20, minBit 9, minWin=22, winSum=394
8915 12:32:08.195324 TX Vref=22, minBit 9, minWin=23, winSum=403
8916 12:32:08.198687 TX Vref=24, minBit 9, minWin=24, winSum=409
8917 12:32:08.205377 TX Vref=26, minBit 9, minWin=24, winSum=418
8918 12:32:08.208248 TX Vref=28, minBit 5, minWin=25, winSum=420
8919 12:32:08.211840 TX Vref=30, minBit 5, minWin=25, winSum=421
8920 12:32:08.214872 TX Vref=32, minBit 0, minWin=24, winSum=408
8921 12:32:08.218583 TX Vref=34, minBit 8, minWin=24, winSum=404
8922 12:32:08.224953 TX Vref=36, minBit 8, minWin=23, winSum=395
8923 12:32:08.227878 [TxChooseVref] Worse bit 5, Min win 25, Win sum 421, Final Vref 30
8924 12:32:08.228371
8925 12:32:08.231558 Final TX Range 0 Vref 30
8926 12:32:08.231979
8927 12:32:08.232411 ==
8928 12:32:08.234573 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 12:32:08.238450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 12:32:08.241251 ==
8931 12:32:08.241713
8932 12:32:08.242208
8933 12:32:08.242614 TX Vref Scan disable
8934 12:32:08.247496 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8935 12:32:08.247959 == TX Byte 0 ==
8936 12:32:08.251056 u2DelayCellOfst[0]=14 cells (4 PI)
8937 12:32:08.254208 u2DelayCellOfst[1]=10 cells (3 PI)
8938 12:32:08.257656 u2DelayCellOfst[2]=0 cells (0 PI)
8939 12:32:08.260815 u2DelayCellOfst[3]=7 cells (2 PI)
8940 12:32:08.264333 u2DelayCellOfst[4]=7 cells (2 PI)
8941 12:32:08.267627 u2DelayCellOfst[5]=18 cells (5 PI)
8942 12:32:08.270756 u2DelayCellOfst[6]=14 cells (4 PI)
8943 12:32:08.274199 u2DelayCellOfst[7]=7 cells (2 PI)
8944 12:32:08.277276 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8945 12:32:08.280943 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8946 12:32:08.283713 == TX Byte 1 ==
8947 12:32:08.287144 u2DelayCellOfst[8]=0 cells (0 PI)
8948 12:32:08.290754 u2DelayCellOfst[9]=3 cells (1 PI)
8949 12:32:08.293637 u2DelayCellOfst[10]=10 cells (3 PI)
8950 12:32:08.297268 u2DelayCellOfst[11]=7 cells (2 PI)
8951 12:32:08.300764 u2DelayCellOfst[12]=14 cells (4 PI)
8952 12:32:08.303935 u2DelayCellOfst[13]=18 cells (5 PI)
8953 12:32:08.306973 u2DelayCellOfst[14]=18 cells (5 PI)
8954 12:32:08.310422 u2DelayCellOfst[15]=18 cells (5 PI)
8955 12:32:08.313864 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8956 12:32:08.316852 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8957 12:32:08.320299 DramC Write-DBI on
8958 12:32:08.320736 ==
8959 12:32:08.324074 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 12:32:08.326879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 12:32:08.327324 ==
8962 12:32:08.327765
8963 12:32:08.328273
8964 12:32:08.330506 TX Vref Scan disable
8965 12:32:08.330942 == TX Byte 0 ==
8966 12:32:08.337175 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8967 12:32:08.337617 == TX Byte 1 ==
8968 12:32:08.339932 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8969 12:32:08.343669 DramC Write-DBI off
8970 12:32:08.344276
8971 12:32:08.344720 [DATLAT]
8972 12:32:08.346458 Freq=1600, CH1 RK1
8973 12:32:08.346894
8974 12:32:08.347331 DATLAT Default: 0xf
8975 12:32:08.349819 0, 0xFFFF, sum = 0
8976 12:32:08.353391 1, 0xFFFF, sum = 0
8977 12:32:08.353853 2, 0xFFFF, sum = 0
8978 12:32:08.356280 3, 0xFFFF, sum = 0
8979 12:32:08.356726 4, 0xFFFF, sum = 0
8980 12:32:08.359954 5, 0xFFFF, sum = 0
8981 12:32:08.360433 6, 0xFFFF, sum = 0
8982 12:32:08.363087 7, 0xFFFF, sum = 0
8983 12:32:08.363529 8, 0xFFFF, sum = 0
8984 12:32:08.366611 9, 0xFFFF, sum = 0
8985 12:32:08.367054 10, 0xFFFF, sum = 0
8986 12:32:08.369486 11, 0xFFFF, sum = 0
8987 12:32:08.369928 12, 0xFFFF, sum = 0
8988 12:32:08.373024 13, 0xFFFF, sum = 0
8989 12:32:08.373464 14, 0x0, sum = 1
8990 12:32:08.376002 15, 0x0, sum = 2
8991 12:32:08.376475 16, 0x0, sum = 3
8992 12:32:08.379519 17, 0x0, sum = 4
8993 12:32:08.379964 best_step = 15
8994 12:32:08.380439
8995 12:32:08.380852 ==
8996 12:32:08.382790 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 12:32:08.389649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 12:32:08.390093 ==
8999 12:32:08.390538 RX Vref Scan: 0
9000 12:32:08.390956
9001 12:32:08.392532 RX Vref 0 -> 0, step: 1
9002 12:32:08.392956
9003 12:32:08.395960 RX Delay 19 -> 252, step: 4
9004 12:32:08.399523 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9005 12:32:08.402408 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9006 12:32:08.405871 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9007 12:32:08.412788 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9008 12:32:08.415808 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9009 12:32:08.419245 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9010 12:32:08.422277 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9011 12:32:08.425801 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9012 12:32:08.432220 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9013 12:32:08.435390 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9014 12:32:08.438779 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9015 12:32:08.441979 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9016 12:32:08.448562 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9017 12:32:08.451578 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9018 12:32:08.454940 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9019 12:32:08.458437 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9020 12:32:08.459042 ==
9021 12:32:08.461404 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 12:32:08.468341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 12:32:08.468841 ==
9024 12:32:08.469272 DQS Delay:
9025 12:32:08.471868 DQS0 = 0, DQS1 = 0
9026 12:32:08.472439 DQM Delay:
9027 12:32:08.474906 DQM0 = 131, DQM1 = 128
9028 12:32:08.475493 DQ Delay:
9029 12:32:08.478410 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9030 12:32:08.480951 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9031 12:32:08.484425 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9032 12:32:08.487299 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9033 12:32:08.487407
9034 12:32:08.487500
9035 12:32:08.487588
9036 12:32:08.490852 [DramC_TX_OE_Calibration] TA2
9037 12:32:08.494384 Original DQ_B0 (3 6) =30, OEN = 27
9038 12:32:08.497795 Original DQ_B1 (3 6) =30, OEN = 27
9039 12:32:08.500854 24, 0x0, End_B0=24 End_B1=24
9040 12:32:08.504319 25, 0x0, End_B0=25 End_B1=25
9041 12:32:08.504421 26, 0x0, End_B0=26 End_B1=26
9042 12:32:08.507118 27, 0x0, End_B0=27 End_B1=27
9043 12:32:08.510610 28, 0x0, End_B0=28 End_B1=28
9044 12:32:08.514031 29, 0x0, End_B0=29 End_B1=29
9045 12:32:08.517436 30, 0x0, End_B0=30 End_B1=30
9046 12:32:08.517511 31, 0x4141, End_B0=30 End_B1=30
9047 12:32:08.520348 Byte0 end_step=30 best_step=27
9048 12:32:08.523690 Byte1 end_step=30 best_step=27
9049 12:32:08.527316 Byte0 TX OE(2T, 0.5T) = (3, 3)
9050 12:32:08.530271 Byte1 TX OE(2T, 0.5T) = (3, 3)
9051 12:32:08.530352
9052 12:32:08.530429
9053 12:32:08.536873 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9054 12:32:08.540557 CH1 RK1: MR19=303, MR18=101E
9055 12:32:08.547101 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
9056 12:32:08.550123 [RxdqsGatingPostProcess] freq 1600
9057 12:32:08.556796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9058 12:32:08.560176 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 12:32:08.560248 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 12:32:08.563527 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 12:32:08.566493 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 12:32:08.570133 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 12:32:08.573033 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 12:32:08.576716 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 12:32:08.579639 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 12:32:08.582712 Pre-setting of DQS Precalculation
9067 12:32:08.589639 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9068 12:32:08.595950 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9069 12:32:08.602844 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 12:32:08.602927
9071 12:32:08.602994
9072 12:32:08.605839 [Calibration Summary] 3200 Mbps
9073 12:32:08.605908 CH 0, Rank 0
9074 12:32:08.609230 SW Impedance : PASS
9075 12:32:08.612579 DUTY Scan : NO K
9076 12:32:08.612686 ZQ Calibration : PASS
9077 12:32:08.616111 Jitter Meter : NO K
9078 12:32:08.619101 CBT Training : PASS
9079 12:32:08.619188 Write leveling : PASS
9080 12:32:08.622621 RX DQS gating : PASS
9081 12:32:08.622696 RX DQ/DQS(RDDQC) : PASS
9082 12:32:08.626043 TX DQ/DQS : PASS
9083 12:32:08.629005 RX DATLAT : PASS
9084 12:32:08.629106 RX DQ/DQS(Engine): PASS
9085 12:32:08.632585 TX OE : PASS
9086 12:32:08.632680 All Pass.
9087 12:32:08.632750
9088 12:32:08.635597 CH 0, Rank 1
9089 12:32:08.635669 SW Impedance : PASS
9090 12:32:08.639051 DUTY Scan : NO K
9091 12:32:08.642100 ZQ Calibration : PASS
9092 12:32:08.642169 Jitter Meter : NO K
9093 12:32:08.645675 CBT Training : PASS
9094 12:32:08.649233 Write leveling : PASS
9095 12:32:08.649302 RX DQS gating : PASS
9096 12:32:08.652150 RX DQ/DQS(RDDQC) : PASS
9097 12:32:08.655204 TX DQ/DQS : PASS
9098 12:32:08.655272 RX DATLAT : PASS
9099 12:32:08.658786 RX DQ/DQS(Engine): PASS
9100 12:32:08.662285 TX OE : PASS
9101 12:32:08.662356 All Pass.
9102 12:32:08.662417
9103 12:32:08.662479 CH 1, Rank 0
9104 12:32:08.665109 SW Impedance : PASS
9105 12:32:08.668469 DUTY Scan : NO K
9106 12:32:08.668547 ZQ Calibration : PASS
9107 12:32:08.672027 Jitter Meter : NO K
9108 12:32:08.674989 CBT Training : PASS
9109 12:32:08.675067 Write leveling : PASS
9110 12:32:08.678556 RX DQS gating : PASS
9111 12:32:08.681453 RX DQ/DQS(RDDQC) : PASS
9112 12:32:08.681533 TX DQ/DQS : PASS
9113 12:32:08.685013 RX DATLAT : PASS
9114 12:32:08.688533 RX DQ/DQS(Engine): PASS
9115 12:32:08.688606 TX OE : PASS
9116 12:32:08.691548 All Pass.
9117 12:32:08.691616
9118 12:32:08.691676 CH 1, Rank 1
9119 12:32:08.694532 SW Impedance : PASS
9120 12:32:08.694601 DUTY Scan : NO K
9121 12:32:08.698075 ZQ Calibration : PASS
9122 12:32:08.701524 Jitter Meter : NO K
9123 12:32:08.701605 CBT Training : PASS
9124 12:32:08.704951 Write leveling : PASS
9125 12:32:08.707937 RX DQS gating : PASS
9126 12:32:08.708062 RX DQ/DQS(RDDQC) : PASS
9127 12:32:08.711404 TX DQ/DQS : PASS
9128 12:32:08.714298 RX DATLAT : PASS
9129 12:32:08.714414 RX DQ/DQS(Engine): PASS
9130 12:32:08.717736 TX OE : PASS
9131 12:32:08.717816 All Pass.
9132 12:32:08.717877
9133 12:32:08.720748 DramC Write-DBI on
9134 12:32:08.723989 PER_BANK_REFRESH: Hybrid Mode
9135 12:32:08.724128 TX_TRACKING: ON
9136 12:32:08.734098 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9137 12:32:08.740742 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9138 12:32:08.747185 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 12:32:08.750809 [FAST_K] Save calibration result to emmc
9140 12:32:08.753803 sync common calibartion params.
9141 12:32:08.757368 sync cbt_mode0:1, 1:1
9142 12:32:08.760372 dram_init: ddr_geometry: 2
9143 12:32:08.760474 dram_init: ddr_geometry: 2
9144 12:32:08.763966 dram_init: ddr_geometry: 2
9145 12:32:08.766921 0:dram_rank_size:100000000
9146 12:32:08.770462 1:dram_rank_size:100000000
9147 12:32:08.773435 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9148 12:32:08.776909 DFS_SHUFFLE_HW_MODE: ON
9149 12:32:08.780461 dramc_set_vcore_voltage set vcore to 725000
9150 12:32:08.783415 Read voltage for 1600, 0
9151 12:32:08.783513 Vio18 = 0
9152 12:32:08.786595 Vcore = 725000
9153 12:32:08.786699 Vdram = 0
9154 12:32:08.786794 Vddq = 0
9155 12:32:08.786882 Vmddr = 0
9156 12:32:08.790025 switch to 3200 Mbps bootup
9157 12:32:08.793195 [DramcRunTimeConfig]
9158 12:32:08.793290 PHYPLL
9159 12:32:08.793379 DPM_CONTROL_AFTERK: ON
9160 12:32:08.796672 PER_BANK_REFRESH: ON
9161 12:32:08.800219 REFRESH_OVERHEAD_REDUCTION: ON
9162 12:32:08.803040 CMD_PICG_NEW_MODE: OFF
9163 12:32:08.803138 XRTWTW_NEW_MODE: ON
9164 12:32:08.806842 XRTRTR_NEW_MODE: ON
9165 12:32:08.806942 TX_TRACKING: ON
9166 12:32:08.809673 RDSEL_TRACKING: OFF
9167 12:32:08.809778 DQS Precalculation for DVFS: ON
9168 12:32:08.813178 RX_TRACKING: OFF
9169 12:32:08.813263 HW_GATING DBG: ON
9170 12:32:08.816635 ZQCS_ENABLE_LP4: ON
9171 12:32:08.819647 RX_PICG_NEW_MODE: ON
9172 12:32:08.819746 TX_PICG_NEW_MODE: ON
9173 12:32:08.823001 ENABLE_RX_DCM_DPHY: ON
9174 12:32:08.826491 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9175 12:32:08.826594 DUMMY_READ_FOR_TRACKING: OFF
9176 12:32:08.829418 !!! SPM_CONTROL_AFTERK: OFF
9177 12:32:08.832879 !!! SPM could not control APHY
9178 12:32:08.836345 IMPEDANCE_TRACKING: ON
9179 12:32:08.836421 TEMP_SENSOR: ON
9180 12:32:08.839291 HW_SAVE_FOR_SR: OFF
9181 12:32:08.842788 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9182 12:32:08.846395 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9183 12:32:08.846501 Read ODT Tracking: ON
9184 12:32:08.849323 Refresh Rate DeBounce: ON
9185 12:32:08.852906 DFS_NO_QUEUE_FLUSH: ON
9186 12:32:08.855917 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9187 12:32:08.856015 ENABLE_DFS_RUNTIME_MRW: OFF
9188 12:32:08.859587 DDR_RESERVE_NEW_MODE: ON
9189 12:32:08.862620 MR_CBT_SWITCH_FREQ: ON
9190 12:32:08.862720 =========================
9191 12:32:08.882954 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9192 12:32:08.885993 dram_init: ddr_geometry: 2
9193 12:32:08.904342 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9194 12:32:08.907794 dram_init: dram init end (result: 0)
9195 12:32:08.914168 DRAM-K: Full calibration passed in 24451 msecs
9196 12:32:08.917747 MRC: failed to locate region type 0.
9197 12:32:08.917832 DRAM rank0 size:0x100000000,
9198 12:32:08.920761 DRAM rank1 size=0x100000000
9199 12:32:08.930680 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9200 12:32:08.937151 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9201 12:32:08.943678 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9202 12:32:08.953812 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9203 12:32:08.953902 DRAM rank0 size:0x100000000,
9204 12:32:08.956678 DRAM rank1 size=0x100000000
9205 12:32:08.956763 CBMEM:
9206 12:32:08.960366 IMD: root @ 0xfffff000 254 entries.
9207 12:32:08.963273 IMD: root @ 0xffffec00 62 entries.
9208 12:32:08.969815 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9209 12:32:08.973442 WARNING: RO_VPD is uninitialized or empty.
9210 12:32:08.976255 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9211 12:32:08.984337 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9212 12:32:08.996998 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9213 12:32:09.008318 BS: romstage times (exec / console): total (unknown) / 23975 ms
9214 12:32:09.008403
9215 12:32:09.008504
9216 12:32:09.018201 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9217 12:32:09.021624 ARM64: Exception handlers installed.
9218 12:32:09.025251 ARM64: Testing exception
9219 12:32:09.028185 ARM64: Done test exception
9220 12:32:09.028278 Enumerating buses...
9221 12:32:09.031495 Show all devs... Before device enumeration.
9222 12:32:09.034533 Root Device: enabled 1
9223 12:32:09.037957 CPU_CLUSTER: 0: enabled 1
9224 12:32:09.038034 CPU: 00: enabled 1
9225 12:32:09.041384 Compare with tree...
9226 12:32:09.041466 Root Device: enabled 1
9227 12:32:09.044760 CPU_CLUSTER: 0: enabled 1
9228 12:32:09.048186 CPU: 00: enabled 1
9229 12:32:09.048268 Root Device scanning...
9230 12:32:09.051183 scan_static_bus for Root Device
9231 12:32:09.054764 CPU_CLUSTER: 0 enabled
9232 12:32:09.057782 scan_static_bus for Root Device done
9233 12:32:09.061301 scan_bus: bus Root Device finished in 8 msecs
9234 12:32:09.061383 done
9235 12:32:09.067444 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9236 12:32:09.070993 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9237 12:32:09.077604 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9238 12:32:09.084021 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9239 12:32:09.084117 Allocating resources...
9240 12:32:09.087480 Reading resources...
9241 12:32:09.090977 Root Device read_resources bus 0 link: 0
9242 12:32:09.093898 DRAM rank0 size:0x100000000,
9243 12:32:09.093980 DRAM rank1 size=0x100000000
9244 12:32:09.100421 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9245 12:32:09.100503 CPU: 00 missing read_resources
9246 12:32:09.106978 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9247 12:32:09.110446 Root Device read_resources bus 0 link: 0 done
9248 12:32:09.113397 Done reading resources.
9249 12:32:09.117053 Show resources in subtree (Root Device)...After reading.
9250 12:32:09.120473 Root Device child on link 0 CPU_CLUSTER: 0
9251 12:32:09.123252 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 12:32:09.133386 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 12:32:09.133473 CPU: 00
9254 12:32:09.140475 Root Device assign_resources, bus 0 link: 0
9255 12:32:09.143668 CPU_CLUSTER: 0 missing set_resources
9256 12:32:09.146755 Root Device assign_resources, bus 0 link: 0 done
9257 12:32:09.150166 Done setting resources.
9258 12:32:09.153677 Show resources in subtree (Root Device)...After assigning values.
9259 12:32:09.156548 Root Device child on link 0 CPU_CLUSTER: 0
9260 12:32:09.163045 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 12:32:09.169718 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 12:32:09.173410 CPU: 00
9263 12:32:09.173481 Done allocating resources.
9264 12:32:09.179931 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9265 12:32:09.180041 Enabling resources...
9266 12:32:09.182914 done.
9267 12:32:09.186375 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9268 12:32:09.189510 Initializing devices...
9269 12:32:09.189610 Root Device init
9270 12:32:09.192812 init hardware done!
9271 12:32:09.192886 0x00000018: ctrlr->caps
9272 12:32:09.196167 52.000 MHz: ctrlr->f_max
9273 12:32:09.199740 0.400 MHz: ctrlr->f_min
9274 12:32:09.202714 0x40ff8080: ctrlr->voltages
9275 12:32:09.202811 sclk: 390625
9276 12:32:09.202902 Bus Width = 1
9277 12:32:09.206362 sclk: 390625
9278 12:32:09.206455 Bus Width = 1
9279 12:32:09.209342 Early init status = 3
9280 12:32:09.212714 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9281 12:32:09.216181 in-header: 03 fc 00 00 01 00 00 00
9282 12:32:09.219135 in-data: 00
9283 12:32:09.222284 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9284 12:32:09.227208 in-header: 03 fd 00 00 00 00 00 00
9285 12:32:09.230733 in-data:
9286 12:32:09.233742 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9287 12:32:09.237336 in-header: 03 fc 00 00 01 00 00 00
9288 12:32:09.240842 in-data: 00
9289 12:32:09.243887 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9290 12:32:09.249495 in-header: 03 fd 00 00 00 00 00 00
9291 12:32:09.252449 in-data:
9292 12:32:09.255988 [SSUSB] Setting up USB HOST controller...
9293 12:32:09.258994 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9294 12:32:09.262517 [SSUSB] phy power-on done.
9295 12:32:09.265574 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9296 12:32:09.272223 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9297 12:32:09.275825 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9298 12:32:09.282792 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9299 12:32:09.288737 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9300 12:32:09.295500 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9301 12:32:09.301802 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9302 12:32:09.308454 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9303 12:32:09.311964 SPM: binary array size = 0x9dc
9304 12:32:09.315045 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9305 12:32:09.321773 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9306 12:32:09.328369 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9307 12:32:09.335073 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9308 12:32:09.337988 configure_display: Starting display init
9309 12:32:09.372531 anx7625_power_on_init: Init interface.
9310 12:32:09.375672 anx7625_disable_pd_protocol: Disabled PD feature.
9311 12:32:09.379369 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9312 12:32:09.407199 anx7625_start_dp_work: Secure OCM version=00
9313 12:32:09.410119 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9314 12:32:09.425211 sp_tx_get_edid_block: EDID Block = 1
9315 12:32:09.527738 Extracted contents:
9316 12:32:09.530938 header: 00 ff ff ff ff ff ff 00
9317 12:32:09.534073 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9318 12:32:09.537769 version: 01 04
9319 12:32:09.540826 basic params: 95 1f 11 78 0a
9320 12:32:09.544260 chroma info: 76 90 94 55 54 90 27 21 50 54
9321 12:32:09.547104 established: 00 00 00
9322 12:32:09.553700 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9323 12:32:09.560533 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9324 12:32:09.563553 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 12:32:09.570580 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9326 12:32:09.577121 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9327 12:32:09.580085 extensions: 00
9328 12:32:09.580187 checksum: fb
9329 12:32:09.580252
9330 12:32:09.587148 Manufacturer: IVO Model 57d Serial Number 0
9331 12:32:09.587244 Made week 0 of 2020
9332 12:32:09.590056 EDID version: 1.4
9333 12:32:09.590138 Digital display
9334 12:32:09.593142 6 bits per primary color channel
9335 12:32:09.596710 DisplayPort interface
9336 12:32:09.596792 Maximum image size: 31 cm x 17 cm
9337 12:32:09.599774 Gamma: 220%
9338 12:32:09.599855 Check DPMS levels
9339 12:32:09.606318 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9340 12:32:09.609650 First detailed timing is preferred timing
9341 12:32:09.613306 Established timings supported:
9342 12:32:09.613387 Standard timings supported:
9343 12:32:09.616631 Detailed timings
9344 12:32:09.619572 Hex of detail: 383680a07038204018303c0035ae10000019
9345 12:32:09.626219 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9346 12:32:09.629779 0780 0798 07c8 0820 hborder 0
9347 12:32:09.632653 0438 043b 0447 0458 vborder 0
9348 12:32:09.636120 -hsync -vsync
9349 12:32:09.636227 Did detailed timing
9350 12:32:09.642591 Hex of detail: 000000000000000000000000000000000000
9351 12:32:09.645987 Manufacturer-specified data, tag 0
9352 12:32:09.649378 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9353 12:32:09.652338 ASCII string: InfoVision
9354 12:32:09.655931 Hex of detail: 000000fe00523134304e574635205248200a
9355 12:32:09.658873 ASCII string: R140NWF5 RH
9356 12:32:09.658986 Checksum
9357 12:32:09.662332 Checksum: 0xfb (valid)
9358 12:32:09.665821 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9359 12:32:09.669331 DSI data_rate: 832800000 bps
9360 12:32:09.675794 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9361 12:32:09.678730 anx7625_parse_edid: pixelclock(138800).
9362 12:32:09.682261 hactive(1920), hsync(48), hfp(24), hbp(88)
9363 12:32:09.685286 vactive(1080), vsync(12), vfp(3), vbp(17)
9364 12:32:09.688972 anx7625_dsi_config: config dsi.
9365 12:32:09.695431 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9366 12:32:09.709523 anx7625_dsi_config: success to config DSI
9367 12:32:09.713070 anx7625_dp_start: MIPI phy setup OK.
9368 12:32:09.716391 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9369 12:32:09.719306 mtk_ddp_mode_set invalid vrefresh 60
9370 12:32:09.722796 main_disp_path_setup
9371 12:32:09.722931 ovl_layer_smi_id_en
9372 12:32:09.725800 ovl_layer_smi_id_en
9373 12:32:09.725887 ccorr_config
9374 12:32:09.725946 aal_config
9375 12:32:09.729406 gamma_config
9376 12:32:09.729486 postmask_config
9377 12:32:09.732450 dither_config
9378 12:32:09.735808 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9379 12:32:09.742312 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9380 12:32:09.745728 Root Device init finished in 552 msecs
9381 12:32:09.749315 CPU_CLUSTER: 0 init
9382 12:32:09.755564 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9383 12:32:09.762587 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9384 12:32:09.762670 APU_MBOX 0x190000b0 = 0x10001
9385 12:32:09.765479 APU_MBOX 0x190001b0 = 0x10001
9386 12:32:09.768854 APU_MBOX 0x190005b0 = 0x10001
9387 12:32:09.772539 APU_MBOX 0x190006b0 = 0x10001
9388 12:32:09.778749 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9389 12:32:09.788689 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9390 12:32:09.801166 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9391 12:32:09.807627 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9392 12:32:09.819273 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9393 12:32:09.828492 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9394 12:32:09.831520 CPU_CLUSTER: 0 init finished in 81 msecs
9395 12:32:09.835131 Devices initialized
9396 12:32:09.837862 Show all devs... After init.
9397 12:32:09.837968 Root Device: enabled 1
9398 12:32:09.841313 CPU_CLUSTER: 0: enabled 1
9399 12:32:09.844558 CPU: 00: enabled 1
9400 12:32:09.848095 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9401 12:32:09.850959 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9402 12:32:09.854281 ELOG: NV offset 0x57f000 size 0x1000
9403 12:32:09.861331 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9404 12:32:09.867861 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9405 12:32:09.871369 ELOG: Event(17) added with size 13 at 2023-06-06 12:32:09 UTC
9406 12:32:09.878167 out: cmd=0x121: 03 db 21 01 00 00 00 00
9407 12:32:09.881026 in-header: 03 0d 00 00 2c 00 00 00
9408 12:32:09.891157 in-data: 52 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9409 12:32:09.897625 ELOG: Event(A1) added with size 10 at 2023-06-06 12:32:10 UTC
9410 12:32:09.904266 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9411 12:32:09.910852 ELOG: Event(A0) added with size 9 at 2023-06-06 12:32:10 UTC
9412 12:32:09.917440 ELOG: Event(16) added with size 11 at 2023-06-06 12:32:10 UTC
9413 12:32:09.990725 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9414 12:32:09.993810 elog_add_boot_reason: Logged dev mode boot
9415 12:32:10.000270 BS: BS_POST_DEVICE entry times (exec / console): 72 / 74 ms
9416 12:32:10.000354 Finalize devices...
9417 12:32:10.003303 Devices finalized
9418 12:32:10.006932 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9419 12:32:10.009935 Writing coreboot table at 0xffe64000
9420 12:32:10.016561 0. 000000000010a000-0000000000113fff: RAMSTAGE
9421 12:32:10.020260 1. 0000000040000000-00000000400fffff: RAM
9422 12:32:10.023128 2. 0000000040100000-000000004032afff: RAMSTAGE
9423 12:32:10.026194 3. 000000004032b000-00000000545fffff: RAM
9424 12:32:10.029536 4. 0000000054600000-000000005465ffff: BL31
9425 12:32:10.036564 5. 0000000054660000-00000000ffe63fff: RAM
9426 12:32:10.039529 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9427 12:32:10.043005 7. 0000000100000000-000000023fffffff: RAM
9428 12:32:10.045897 Passing 5 GPIOs to payload:
9429 12:32:10.052431 NAME | PORT | POLARITY | VALUE
9430 12:32:10.055793 EC in RW | 0x000000aa | low | undefined
9431 12:32:10.059230 EC interrupt | 0x00000005 | low | undefined
9432 12:32:10.065571 TPM interrupt | 0x000000ab | high | undefined
9433 12:32:10.069387 SD card detect | 0x00000011 | high | undefined
9434 12:32:10.075819 speaker enable | 0x00000093 | high | undefined
9435 12:32:10.078761 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9436 12:32:10.082119 in-header: 03 f9 00 00 02 00 00 00
9437 12:32:10.082202 in-data: 02 00
9438 12:32:10.085752 ADC[4]: Raw value=902955 ID=7
9439 12:32:10.089324 ADC[3]: Raw value=213916 ID=1
9440 12:32:10.089406 RAM Code: 0x71
9441 12:32:10.092438 ADC[6]: Raw value=74630 ID=0
9442 12:32:10.095910 ADC[5]: Raw value=213916 ID=1
9443 12:32:10.095992 SKU Code: 0x1
9444 12:32:10.102640 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a51a
9445 12:32:10.105560 coreboot table: 964 bytes.
9446 12:32:10.109151 IMD ROOT 0. 0xfffff000 0x00001000
9447 12:32:10.112267 IMD SMALL 1. 0xffffe000 0x00001000
9448 12:32:10.115780 RO MCACHE 2. 0xffffc000 0x00001104
9449 12:32:10.118769 CONSOLE 3. 0xfff7c000 0x00080000
9450 12:32:10.122308 FMAP 4. 0xfff7b000 0x00000452
9451 12:32:10.125305 TIME STAMP 5. 0xfff7a000 0x00000910
9452 12:32:10.128923 VBOOT WORK 6. 0xfff66000 0x00014000
9453 12:32:10.131763 RAMOOPS 7. 0xffe66000 0x00100000
9454 12:32:10.135149 COREBOOT 8. 0xffe64000 0x00002000
9455 12:32:10.135233 IMD small region:
9456 12:32:10.138557 IMD ROOT 0. 0xffffec00 0x00000400
9457 12:32:10.141530 VPD 1. 0xffffeba0 0x0000004c
9458 12:32:10.144988 MMC STATUS 2. 0xffffeb80 0x00000004
9459 12:32:10.151608 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9460 12:32:10.151694 Probing TPM: done!
9461 12:32:10.158601 Connected to device vid:did:rid of 1ae0:0028:00
9462 12:32:10.165034 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9463 12:32:10.172900 Initialized TPM device CR50 revision 0
9464 12:32:10.172983 Checking cr50 for pending updates
9465 12:32:10.178293 Reading cr50 TPM mode
9466 12:32:10.187050 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9467 12:32:10.193402 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9468 12:32:10.233359 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9469 12:32:10.236799 Checking segment from ROM address 0x40100000
9470 12:32:10.240242 Checking segment from ROM address 0x4010001c
9471 12:32:10.246584 Loading segment from ROM address 0x40100000
9472 12:32:10.246670 code (compression=0)
9473 12:32:10.256791 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9474 12:32:10.263480 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9475 12:32:10.263566 it's not compressed!
9476 12:32:10.270363 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9477 12:32:10.276484 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9478 12:32:10.295115 Loading segment from ROM address 0x4010001c
9479 12:32:10.295203 Entry Point 0x80000000
9480 12:32:10.298537 Loaded segments
9481 12:32:10.301595 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9482 12:32:10.308579 Jumping to boot code at 0x80000000(0xffe64000)
9483 12:32:10.315210 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9484 12:32:10.321640 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9485 12:32:10.329238 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9486 12:32:10.332898 Checking segment from ROM address 0x40100000
9487 12:32:10.335822 Checking segment from ROM address 0x4010001c
9488 12:32:10.342838 Loading segment from ROM address 0x40100000
9489 12:32:10.342924 code (compression=1)
9490 12:32:10.349194 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9491 12:32:10.359200 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9492 12:32:10.359287 using LZMA
9493 12:32:10.367487 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9494 12:32:10.374298 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9495 12:32:10.377757 Loading segment from ROM address 0x4010001c
9496 12:32:10.377843 Entry Point 0x54601000
9497 12:32:10.381043 Loaded segments
9498 12:32:10.383915 NOTICE: MT8192 bl31_setup
9499 12:32:10.391353 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9500 12:32:10.394832 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9501 12:32:10.397724 WARNING: region 0:
9502 12:32:10.401137 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 12:32:10.401223 WARNING: region 1:
9504 12:32:10.407752 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9505 12:32:10.411312 WARNING: region 2:
9506 12:32:10.414357 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9507 12:32:10.417997 WARNING: region 3:
9508 12:32:10.421043 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9509 12:32:10.424609 WARNING: region 4:
9510 12:32:10.431016 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9511 12:32:10.431104 WARNING: region 5:
9512 12:32:10.434161 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 12:32:10.437727 WARNING: region 6:
9514 12:32:10.440787 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 12:32:10.444310 WARNING: region 7:
9516 12:32:10.447700 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 12:32:10.453955 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9518 12:32:10.457316 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9519 12:32:10.463920 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9520 12:32:10.467434 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9521 12:32:10.470968 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9522 12:32:10.477361 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9523 12:32:10.481334 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9524 12:32:10.484225 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9525 12:32:10.490791 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9526 12:32:10.494226 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9527 12:32:10.500446 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9528 12:32:10.503967 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9529 12:32:10.506910 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9530 12:32:10.513455 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9531 12:32:10.516971 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9532 12:32:10.520068 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9533 12:32:10.527052 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9534 12:32:10.530007 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9535 12:32:10.537115 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9536 12:32:10.540026 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9537 12:32:10.543794 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9538 12:32:10.550126 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9539 12:32:10.553584 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9540 12:32:10.559863 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9541 12:32:10.563561 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9542 12:32:10.566572 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9543 12:32:10.573141 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9544 12:32:10.576708 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9545 12:32:10.583139 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9546 12:32:10.586669 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9547 12:32:10.590161 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9548 12:32:10.596631 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9549 12:32:10.600236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9550 12:32:10.603432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9551 12:32:10.606784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9552 12:32:10.613042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9553 12:32:10.616701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9554 12:32:10.619692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9555 12:32:10.623363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9556 12:32:10.630029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9557 12:32:10.632971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9558 12:32:10.636592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9559 12:32:10.639591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9560 12:32:10.646149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9561 12:32:10.649576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9562 12:32:10.652658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9563 12:32:10.659792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9564 12:32:10.662799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9565 12:32:10.666347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9566 12:32:10.672943 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9567 12:32:10.675831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9568 12:32:10.682923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9569 12:32:10.686351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9570 12:32:10.689242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9571 12:32:10.695648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9572 12:32:10.699356 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9573 12:32:10.705722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9574 12:32:10.709161 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9575 12:32:10.715868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9576 12:32:10.719662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9577 12:32:10.722588 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9578 12:32:10.728998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9579 12:32:10.732681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9580 12:32:10.739306 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9581 12:32:10.742276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9582 12:32:10.748886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9583 12:32:10.752555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9584 12:32:10.758944 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9585 12:32:10.762408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9586 12:32:10.765849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9587 12:32:10.772281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9588 12:32:10.775297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9589 12:32:10.782302 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9590 12:32:10.785260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9591 12:32:10.792295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9592 12:32:10.795193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9593 12:32:10.802272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9594 12:32:10.805334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9595 12:32:10.808750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9596 12:32:10.815654 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9597 12:32:10.818496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9598 12:32:10.825553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9599 12:32:10.828519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9600 12:32:10.835100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9601 12:32:10.838599 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9602 12:32:10.842135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9603 12:32:10.848634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9604 12:32:10.851745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9605 12:32:10.858864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9606 12:32:10.861621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9607 12:32:10.868720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9608 12:32:10.871661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9609 12:32:10.878659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9610 12:32:10.881570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9611 12:32:10.884978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9612 12:32:10.891510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9613 12:32:10.894512 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9614 12:32:10.897965 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9615 12:32:10.904462 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9616 12:32:10.908058 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9617 12:32:10.911092 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9618 12:32:10.918036 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9619 12:32:10.921295 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9620 12:32:10.927604 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9621 12:32:10.931050 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9622 12:32:10.934098 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9623 12:32:10.940739 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9624 12:32:10.944368 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9625 12:32:10.950400 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9626 12:32:10.953919 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9627 12:32:10.957505 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9628 12:32:10.963977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9629 12:32:10.966908 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9630 12:32:10.973884 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9631 12:32:10.976765 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9632 12:32:10.980390 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9633 12:32:10.986832 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9634 12:32:10.990597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9635 12:32:10.993548 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9636 12:32:10.999970 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9637 12:32:11.003510 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9638 12:32:11.006882 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9639 12:32:11.010428 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9640 12:32:11.016866 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9641 12:32:11.019865 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9642 12:32:11.023361 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9643 12:32:11.030234 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9644 12:32:11.033072 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9645 12:32:11.039616 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9646 12:32:11.043196 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9647 12:32:11.046787 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9648 12:32:11.052929 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9649 12:32:11.056553 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9650 12:32:11.063224 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9651 12:32:11.066181 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9652 12:32:11.069794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9653 12:32:11.076275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9654 12:32:11.079678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9655 12:32:11.086225 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9656 12:32:11.089706 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9657 12:32:11.092786 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9658 12:32:11.099375 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9659 12:32:11.102743 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9660 12:32:11.109200 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9661 12:32:11.112562 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9662 12:32:11.115587 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9663 12:32:11.122615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9664 12:32:11.125970 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9665 12:32:11.132255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9666 12:32:11.136232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9667 12:32:11.138961 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9668 12:32:11.145610 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9669 12:32:11.149002 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9670 12:32:11.155667 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9671 12:32:11.159136 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9672 12:32:11.162139 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9673 12:32:11.168673 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9674 12:32:11.172273 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9675 12:32:11.175783 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9676 12:32:11.182046 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9677 12:32:11.185373 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9678 12:32:11.192028 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9679 12:32:11.194942 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9680 12:32:11.201554 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9681 12:32:11.205165 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9682 12:32:11.207994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9683 12:32:11.214743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9684 12:32:11.218275 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9685 12:32:11.224705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9686 12:32:11.228183 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9687 12:32:11.231561 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9688 12:32:11.237933 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9689 12:32:11.241229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9690 12:32:11.247691 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9691 12:32:11.250742 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9692 12:32:11.254398 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9693 12:32:11.261003 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9694 12:32:11.264054 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9695 12:32:11.270532 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9696 12:32:11.274150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9697 12:32:11.277129 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9698 12:32:11.283673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9699 12:32:11.286815 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9700 12:32:11.293755 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9701 12:32:11.296727 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9702 12:32:11.303354 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9703 12:32:11.306935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9704 12:32:11.309889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9705 12:32:11.316784 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9706 12:32:11.319657 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9707 12:32:11.326776 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9708 12:32:11.329666 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9709 12:32:11.336417 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9710 12:32:11.339678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9711 12:32:11.342879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9712 12:32:11.349171 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9713 12:32:11.352788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9714 12:32:11.359262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9715 12:32:11.362326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9716 12:32:11.369029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9717 12:32:11.372513 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9718 12:32:11.375462 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9719 12:32:11.382237 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9720 12:32:11.385357 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9721 12:32:11.392289 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9722 12:32:11.395611 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9723 12:32:11.402039 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9724 12:32:11.405119 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9725 12:32:11.408755 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9726 12:32:11.415295 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9727 12:32:11.418263 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9728 12:32:11.425285 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9729 12:32:11.428179 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9730 12:32:11.434875 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9731 12:32:11.438340 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9732 12:32:11.441326 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9733 12:32:11.448065 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9734 12:32:11.451523 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9735 12:32:11.458014 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9736 12:32:11.460975 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9737 12:32:11.467505 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9738 12:32:11.470957 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9739 12:32:11.474443 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9740 12:32:11.480989 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9741 12:32:11.484049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9742 12:32:11.490648 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9743 12:32:11.493718 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9744 12:32:11.500617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9745 12:32:11.503853 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9746 12:32:11.507515 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9747 12:32:11.510401 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9748 12:32:11.516917 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9749 12:32:11.520397 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9750 12:32:11.523904 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9751 12:32:11.530082 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9752 12:32:11.533609 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9753 12:32:11.536497 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9754 12:32:11.543679 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9755 12:32:11.546531 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9756 12:32:11.549893 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9757 12:32:11.556390 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9758 12:32:11.559895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9759 12:32:11.566528 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9760 12:32:11.569523 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9761 12:32:11.572597 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9762 12:32:11.579575 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9763 12:32:11.582572 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9764 12:32:11.589739 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9765 12:32:11.592637 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9766 12:32:11.596214 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9767 12:32:11.602598 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9768 12:32:11.606050 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9769 12:32:11.609475 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9770 12:32:11.615455 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9771 12:32:11.619147 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9772 12:32:11.622083 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9773 12:32:11.628830 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9774 12:32:11.632215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9775 12:32:11.639105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9776 12:32:11.642185 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9777 12:32:11.645648 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9778 12:32:11.651876 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9779 12:32:11.655326 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9780 12:32:11.658702 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9781 12:32:11.665184 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9782 12:32:11.668121 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9783 12:32:11.675209 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9784 12:32:11.678105 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9785 12:32:11.681734 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9786 12:32:11.688327 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9787 12:32:11.691367 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9788 12:32:11.694786 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9789 12:32:11.697800 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9790 12:32:11.701421 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9791 12:32:11.707675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9792 12:32:11.711200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9793 12:32:11.714069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9794 12:32:11.720776 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9795 12:32:11.724181 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9796 12:32:11.727785 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9797 12:32:11.734143 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9798 12:32:11.737550 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9799 12:32:11.740406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9800 12:32:11.747412 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9801 12:32:11.750313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9802 12:32:11.753655 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9803 12:32:11.760448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9804 12:32:11.763740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9805 12:32:11.770325 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9806 12:32:11.773814 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9807 12:32:11.780359 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9808 12:32:11.783363 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9809 12:32:11.786885 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9810 12:32:11.793416 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9811 12:32:11.796952 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9812 12:32:11.803542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9813 12:32:11.806339 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9814 12:32:11.809892 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9815 12:32:11.816197 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9816 12:32:11.819702 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9817 12:32:11.826408 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9818 12:32:11.829449 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9819 12:32:11.836255 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9820 12:32:11.839217 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9821 12:32:11.845588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9822 12:32:11.849344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9823 12:32:11.852365 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9824 12:32:11.859373 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9825 12:32:11.862182 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9826 12:32:11.868905 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9827 12:32:11.872627 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9828 12:32:11.875570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9829 12:32:11.881889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9830 12:32:11.885555 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9831 12:32:11.892098 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9832 12:32:11.895138 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9833 12:32:11.901816 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9834 12:32:11.904847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9835 12:32:11.908384 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9836 12:32:11.914821 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9837 12:32:11.918310 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9838 12:32:11.924823 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9839 12:32:11.927815 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9840 12:32:11.934384 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9841 12:32:11.937862 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9842 12:32:11.941074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9843 12:32:11.947666 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9844 12:32:11.950545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9845 12:32:11.957153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9846 12:32:11.960723 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9847 12:32:11.964145 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9848 12:32:11.970493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9849 12:32:11.974037 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9850 12:32:11.980468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9851 12:32:11.983902 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9852 12:32:11.990490 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9853 12:32:11.993542 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9854 12:32:11.997165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9855 12:32:12.003639 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9856 12:32:12.006634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9857 12:32:12.013376 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9858 12:32:12.016377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9859 12:32:12.023496 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9860 12:32:12.026319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9861 12:32:12.032957 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9862 12:32:12.035957 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9863 12:32:12.039515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9864 12:32:12.045891 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9865 12:32:12.049379 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9866 12:32:12.055670 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9867 12:32:12.058977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9868 12:32:12.065899 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9869 12:32:12.068778 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9870 12:32:12.072171 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9871 12:32:12.078914 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9872 12:32:12.081973 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9873 12:32:12.088510 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9874 12:32:12.092152 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9875 12:32:12.098136 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9876 12:32:12.101748 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9877 12:32:12.108288 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9878 12:32:12.111890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9879 12:32:12.114920 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9880 12:32:12.121465 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9881 12:32:12.124487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9882 12:32:12.131477 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9883 12:32:12.134430 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9884 12:32:12.141077 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9885 12:32:12.144633 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9886 12:32:12.147557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9887 12:32:12.154319 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9888 12:32:12.157344 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9889 12:32:12.164123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9890 12:32:12.167461 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9891 12:32:12.173960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9892 12:32:12.177309 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9893 12:32:12.183766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9894 12:32:12.187252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9895 12:32:12.193673 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9896 12:32:12.197290 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9897 12:32:12.200212 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9898 12:32:12.206800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9899 12:32:12.210349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9900 12:32:12.216504 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9901 12:32:12.219949 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9902 12:32:12.226505 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9903 12:32:12.230108 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9904 12:32:12.236362 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9905 12:32:12.239838 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9906 12:32:12.242831 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9907 12:32:12.249815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9908 12:32:12.252935 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9909 12:32:12.259405 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9910 12:32:12.262900 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9911 12:32:12.269133 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9912 12:32:12.272537 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9913 12:32:12.278872 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9914 12:32:12.282248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9915 12:32:12.288975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9916 12:32:12.292398 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9917 12:32:12.299050 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9918 12:32:12.301935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9919 12:32:12.305574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9920 12:32:12.312225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9921 12:32:12.315152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9922 12:32:12.321760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9923 12:32:12.325258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9924 12:32:12.331827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9925 12:32:12.335262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9926 12:32:12.341553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9927 12:32:12.345138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9928 12:32:12.351145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9929 12:32:12.354700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9930 12:32:12.361176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9931 12:32:12.364605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9932 12:32:12.371416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9933 12:32:12.374425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9934 12:32:12.380876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9935 12:32:12.384217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9936 12:32:12.387518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9937 12:32:12.394455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9938 12:32:12.397350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9939 12:32:12.403906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9940 12:32:12.410594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9941 12:32:12.414280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9942 12:32:12.420808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9943 12:32:12.423735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9944 12:32:12.430374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9945 12:32:12.433506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9946 12:32:12.440729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9947 12:32:12.443506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9948 12:32:12.450084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9949 12:32:12.453584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9950 12:32:12.460009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9951 12:32:12.463645 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9952 12:32:12.466421 INFO: [APUAPC] vio 0
9953 12:32:12.470113 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9954 12:32:12.476436 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9955 12:32:12.479771 INFO: [APUAPC] D0_APC_0: 0x400510
9956 12:32:12.479855 INFO: [APUAPC] D0_APC_1: 0x0
9957 12:32:12.483301 INFO: [APUAPC] D0_APC_2: 0x1540
9958 12:32:12.486798 INFO: [APUAPC] D0_APC_3: 0x0
9959 12:32:12.489674 INFO: [APUAPC] D1_APC_0: 0xffffffff
9960 12:32:12.493089 INFO: [APUAPC] D1_APC_1: 0xffffffff
9961 12:32:12.496415 INFO: [APUAPC] D1_APC_2: 0x3fffff
9962 12:32:12.499730 INFO: [APUAPC] D1_APC_3: 0x0
9963 12:32:12.502802 INFO: [APUAPC] D2_APC_0: 0xffffffff
9964 12:32:12.506166 INFO: [APUAPC] D2_APC_1: 0xffffffff
9965 12:32:12.509242 INFO: [APUAPC] D2_APC_2: 0x3fffff
9966 12:32:12.512914 INFO: [APUAPC] D2_APC_3: 0x0
9967 12:32:12.515826 INFO: [APUAPC] D3_APC_0: 0xffffffff
9968 12:32:12.519397 INFO: [APUAPC] D3_APC_1: 0xffffffff
9969 12:32:12.522457 INFO: [APUAPC] D3_APC_2: 0x3fffff
9970 12:32:12.525958 INFO: [APUAPC] D3_APC_3: 0x0
9971 12:32:12.528941 INFO: [APUAPC] D4_APC_0: 0xffffffff
9972 12:32:12.532457 INFO: [APUAPC] D4_APC_1: 0xffffffff
9973 12:32:12.535463 INFO: [APUAPC] D4_APC_2: 0x3fffff
9974 12:32:12.539043 INFO: [APUAPC] D4_APC_3: 0x0
9975 12:32:12.542508 INFO: [APUAPC] D5_APC_0: 0xffffffff
9976 12:32:12.545330 INFO: [APUAPC] D5_APC_1: 0xffffffff
9977 12:32:12.548755 INFO: [APUAPC] D5_APC_2: 0x3fffff
9978 12:32:12.552205 INFO: [APUAPC] D5_APC_3: 0x0
9979 12:32:12.555131 INFO: [APUAPC] D6_APC_0: 0xffffffff
9980 12:32:12.558905 INFO: [APUAPC] D6_APC_1: 0xffffffff
9981 12:32:12.561765 INFO: [APUAPC] D6_APC_2: 0x3fffff
9982 12:32:12.565363 INFO: [APUAPC] D6_APC_3: 0x0
9983 12:32:12.568311 INFO: [APUAPC] D7_APC_0: 0xffffffff
9984 12:32:12.571829 INFO: [APUAPC] D7_APC_1: 0xffffffff
9985 12:32:12.575192 INFO: [APUAPC] D7_APC_2: 0x3fffff
9986 12:32:12.578756 INFO: [APUAPC] D7_APC_3: 0x0
9987 12:32:12.581589 INFO: [APUAPC] D8_APC_0: 0xffffffff
9988 12:32:12.585242 INFO: [APUAPC] D8_APC_1: 0xffffffff
9989 12:32:12.588581 INFO: [APUAPC] D8_APC_2: 0x3fffff
9990 12:32:12.591633 INFO: [APUAPC] D8_APC_3: 0x0
9991 12:32:12.594975 INFO: [APUAPC] D9_APC_0: 0xffffffff
9992 12:32:12.598391 INFO: [APUAPC] D9_APC_1: 0xffffffff
9993 12:32:12.601726 INFO: [APUAPC] D9_APC_2: 0x3fffff
9994 12:32:12.604526 INFO: [APUAPC] D9_APC_3: 0x0
9995 12:32:12.607996 INFO: [APUAPC] D10_APC_0: 0xffffffff
9996 12:32:12.611138 INFO: [APUAPC] D10_APC_1: 0xffffffff
9997 12:32:12.614675 INFO: [APUAPC] D10_APC_2: 0x3fffff
9998 12:32:12.617629 INFO: [APUAPC] D10_APC_3: 0x0
9999 12:32:12.621173 INFO: [APUAPC] D11_APC_0: 0xffffffff
10000 12:32:12.624757 INFO: [APUAPC] D11_APC_1: 0xffffffff
10001 12:32:12.627750 INFO: [APUAPC] D11_APC_2: 0x3fffff
10002 12:32:12.631355 INFO: [APUAPC] D11_APC_3: 0x0
10003 12:32:12.634182 INFO: [APUAPC] D12_APC_0: 0xffffffff
10004 12:32:12.637818 INFO: [APUAPC] D12_APC_1: 0xffffffff
10005 12:32:12.640822 INFO: [APUAPC] D12_APC_2: 0x3fffff
10006 12:32:12.644481 INFO: [APUAPC] D12_APC_3: 0x0
10007 12:32:12.647441 INFO: [APUAPC] D13_APC_0: 0xffffffff
10008 12:32:12.650703 INFO: [APUAPC] D13_APC_1: 0xffffffff
10009 12:32:12.654112 INFO: [APUAPC] D13_APC_2: 0x3fffff
10010 12:32:12.657085 INFO: [APUAPC] D13_APC_3: 0x0
10011 12:32:12.660770 INFO: [APUAPC] D14_APC_0: 0xffffffff
10012 12:32:12.663668 INFO: [APUAPC] D14_APC_1: 0xffffffff
10013 12:32:12.667061 INFO: [APUAPC] D14_APC_2: 0x3fffff
10014 12:32:12.670136 INFO: [APUAPC] D14_APC_3: 0x0
10015 12:32:12.673634 INFO: [APUAPC] D15_APC_0: 0xffffffff
10016 12:32:12.677026 INFO: [APUAPC] D15_APC_1: 0xffffffff
10017 12:32:12.680268 INFO: [APUAPC] D15_APC_2: 0x3fffff
10018 12:32:12.683241 INFO: [APUAPC] D15_APC_3: 0x0
10019 12:32:12.686608 INFO: [APUAPC] APC_CON: 0x4
10020 12:32:12.690106 INFO: [NOCDAPC] D0_APC_0: 0x0
10021 12:32:12.693216 INFO: [NOCDAPC] D0_APC_1: 0x0
10022 12:32:12.696672 INFO: [NOCDAPC] D1_APC_0: 0x0
10023 12:32:12.700194 INFO: [NOCDAPC] D1_APC_1: 0xfff
10024 12:32:12.703424 INFO: [NOCDAPC] D2_APC_0: 0x0
10025 12:32:12.703507 INFO: [NOCDAPC] D2_APC_1: 0xfff
10026 12:32:12.706666 INFO: [NOCDAPC] D3_APC_0: 0x0
10027 12:32:12.709786 INFO: [NOCDAPC] D3_APC_1: 0xfff
10028 12:32:12.713431 INFO: [NOCDAPC] D4_APC_0: 0x0
10029 12:32:12.716348 INFO: [NOCDAPC] D4_APC_1: 0xfff
10030 12:32:12.719948 INFO: [NOCDAPC] D5_APC_0: 0x0
10031 12:32:12.722915 INFO: [NOCDAPC] D5_APC_1: 0xfff
10032 12:32:12.725947 INFO: [NOCDAPC] D6_APC_0: 0x0
10033 12:32:12.729536 INFO: [NOCDAPC] D6_APC_1: 0xfff
10034 12:32:12.732880 INFO: [NOCDAPC] D7_APC_0: 0x0
10035 12:32:12.735960 INFO: [NOCDAPC] D7_APC_1: 0xfff
10036 12:32:12.739356 INFO: [NOCDAPC] D8_APC_0: 0x0
10037 12:32:12.739440 INFO: [NOCDAPC] D8_APC_1: 0xfff
10038 12:32:12.742493 INFO: [NOCDAPC] D9_APC_0: 0x0
10039 12:32:12.745909 INFO: [NOCDAPC] D9_APC_1: 0xfff
10040 12:32:12.749557 INFO: [NOCDAPC] D10_APC_0: 0x0
10041 12:32:12.752470 INFO: [NOCDAPC] D10_APC_1: 0xfff
10042 12:32:12.755953 INFO: [NOCDAPC] D11_APC_0: 0x0
10043 12:32:12.759512 INFO: [NOCDAPC] D11_APC_1: 0xfff
10044 12:32:12.762392 INFO: [NOCDAPC] D12_APC_0: 0x0
10045 12:32:12.765530 INFO: [NOCDAPC] D12_APC_1: 0xfff
10046 12:32:12.769040 INFO: [NOCDAPC] D13_APC_0: 0x0
10047 12:32:12.772592 INFO: [NOCDAPC] D13_APC_1: 0xfff
10048 12:32:12.775628 INFO: [NOCDAPC] D14_APC_0: 0x0
10049 12:32:12.779099 INFO: [NOCDAPC] D14_APC_1: 0xfff
10050 12:32:12.782508 INFO: [NOCDAPC] D15_APC_0: 0x0
10051 12:32:12.785557 INFO: [NOCDAPC] D15_APC_1: 0xfff
10052 12:32:12.785640 INFO: [NOCDAPC] APC_CON: 0x4
10053 12:32:12.792347 INFO: [APUAPC] set_apusys_apc done
10054 12:32:12.792431 INFO: [DEVAPC] devapc_init done
10055 12:32:12.798885 INFO: GICv3 without legacy support detected.
10056 12:32:12.801837 INFO: ARM GICv3 driver initialized in EL3
10057 12:32:12.805179 INFO: Maximum SPI INTID supported: 639
10058 12:32:12.808493 INFO: BL31: Initializing runtime services
10059 12:32:12.815004 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10060 12:32:12.818640 INFO: SPM: enable CPC mode
10061 12:32:12.821561 INFO: mcdi ready for mcusys-off-idle and system suspend
10062 12:32:12.828257 INFO: BL31: Preparing for EL3 exit to normal world
10063 12:32:12.831234 INFO: Entry point address = 0x80000000
10064 12:32:12.834688 INFO: SPSR = 0x8
10065 12:32:12.839371
10066 12:32:12.839454
10067 12:32:12.839520
10068 12:32:12.842350 Starting depthcharge on Spherion...
10069 12:32:12.842463
10070 12:32:12.842529 Wipe memory regions:
10071 12:32:12.842591
10072 12:32:12.843227 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10073 12:32:12.843329 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10074 12:32:12.843426 Setting prompt string to ['asurada:']
10075 12:32:12.843556 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10076 12:32:12.845995 [0x00000040000000, 0x00000054600000)
10077 12:32:12.968041
10078 12:32:12.968181 [0x00000054660000, 0x00000080000000)
10079 12:32:13.227852
10080 12:32:13.228006 [0x000000821a7280, 0x000000ffe64000)
10081 12:32:13.972432
10082 12:32:13.972570 [0x00000100000000, 0x00000240000000)
10083 12:32:15.862120
10084 12:32:15.865430 Initializing XHCI USB controller at 0x11200000.
10085 12:32:16.903008
10086 12:32:16.906334 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10087 12:32:16.906808
10088 12:32:16.907195
10089 12:32:16.907563
10090 12:32:16.908354 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 12:32:17.009489 asurada: tftpboot 192.168.201.1 10605801/tftp-deploy-l8ntmx1e/kernel/image.itb 10605801/tftp-deploy-l8ntmx1e/kernel/cmdline
10093 12:32:17.009838 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 12:32:17.010145 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10095 12:32:17.014302 tftpboot 192.168.201.1 10605801/tftp-deploy-l8ntmx1e/kernel/image.itp-deploy-l8ntmx1e/kernel/cmdline
10096 12:32:17.014543
10097 12:32:17.014728 Waiting for link
10098 12:32:17.174441
10099 12:32:17.174625 R8152: Initializing
10100 12:32:17.174740
10101 12:32:17.177936 Version 6 (ocp_data = 5c30)
10102 12:32:17.178042
10103 12:32:17.181462 R8152: Done initializing
10104 12:32:17.181564
10105 12:32:17.181658 Adding net device
10106 12:32:19.144016
10107 12:32:19.144223 done.
10108 12:32:19.144331
10109 12:32:19.144432 MAC: 00:24:32:30:7c:7b
10110 12:32:19.144530
10111 12:32:19.147615 Sending DHCP discover... done.
10112 12:32:19.147725
10113 12:32:22.538100 Waiting for reply... done.
10114 12:32:22.538361
10115 12:32:22.538506 Sending DHCP request... done.
10116 12:32:22.541638
10117 12:32:22.541839 Waiting for reply... done.
10118 12:32:22.542001
10119 12:32:22.544538 My ip is 192.168.201.14
10120 12:32:22.544739
10121 12:32:22.548415 The DHCP server ip is 192.168.201.1
10122 12:32:22.548751
10123 12:32:22.551234 TFTP server IP predefined by user: 192.168.201.1
10124 12:32:22.551546
10125 12:32:22.557921 Bootfile predefined by user: 10605801/tftp-deploy-l8ntmx1e/kernel/image.itb
10126 12:32:22.558313
10127 12:32:22.561520 Sending tftp read request... done.
10128 12:32:22.561947
10129 12:32:22.569287 Waiting for the transfer...
10130 12:32:22.569730
10131 12:32:23.167570 00000000 ################################################################
10132 12:32:23.167748
10133 12:32:23.765159 00080000 ################################################################
10134 12:32:23.765297
10135 12:32:24.327915 00100000 ################################################################
10136 12:32:24.328089
10137 12:32:24.929540 00180000 ################################################################
10138 12:32:24.929691
10139 12:32:25.513830 00200000 ################################################################
10140 12:32:25.513968
10141 12:32:26.120691 00280000 ################################################################
10142 12:32:26.120825
10143 12:32:26.656638 00300000 ################################################################
10144 12:32:26.656793
10145 12:32:27.225310 00380000 ################################################################
10146 12:32:27.225464
10147 12:32:27.771013 00400000 ################################################################
10148 12:32:27.771170
10149 12:32:28.328521 00480000 ################################################################
10150 12:32:28.328734
10151 12:32:28.966208 00500000 ################################################################
10152 12:32:28.966379
10153 12:32:29.579020 00580000 ################################################################
10154 12:32:29.579668
10155 12:32:30.253293 00600000 ################################################################
10156 12:32:30.253893
10157 12:32:30.860834 00680000 ################################################################
10158 12:32:30.861004
10159 12:32:31.540004 00700000 ################################################################
10160 12:32:31.540550
10161 12:32:32.146638 00780000 ################################################################
10162 12:32:32.146805
10163 12:32:32.779030 00800000 ################################################################
10164 12:32:32.779183
10165 12:32:33.333863 00880000 ################################################################
10166 12:32:33.334019
10167 12:32:33.935404 00900000 ################################################################
10168 12:32:33.935558
10169 12:32:34.503848 00980000 ################################################################
10170 12:32:34.504007
10171 12:32:35.046793 00a00000 ################################################################
10172 12:32:35.046941
10173 12:32:35.607544 00a80000 ################################################################
10174 12:32:35.607697
10175 12:32:36.159885 00b00000 ################################################################
10176 12:32:36.160082
10177 12:32:36.698947 00b80000 ################################################################
10178 12:32:36.699101
10179 12:32:37.229753 00c00000 ################################################################
10180 12:32:37.229907
10181 12:32:37.765518 00c80000 ################################################################
10182 12:32:37.765670
10183 12:32:38.305191 00d00000 ################################################################
10184 12:32:38.305328
10185 12:32:38.835701 00d80000 ################################################################
10186 12:32:38.835879
10187 12:32:39.393589 00e00000 ################################################################
10188 12:32:39.393774
10189 12:32:39.947188 00e80000 ################################################################
10190 12:32:39.947340
10191 12:32:40.480226 00f00000 ################################################################
10192 12:32:40.480407
10193 12:32:41.001936 00f80000 ################################################################
10194 12:32:41.002115
10195 12:32:41.540347 01000000 ################################################################
10196 12:32:41.540501
10197 12:32:42.066028 01080000 ################################################################
10198 12:32:42.066184
10199 12:32:42.591981 01100000 ################################################################
10200 12:32:42.592150
10201 12:32:43.125298 01180000 ################################################################
10202 12:32:43.125478
10203 12:32:43.667151 01200000 ################################################################
10204 12:32:43.667302
10205 12:32:44.219136 01280000 ################################################################
10206 12:32:44.219322
10207 12:32:44.769476 01300000 ################################################################
10208 12:32:44.769632
10209 12:32:45.296672 01380000 ################################################################
10210 12:32:45.296857
10211 12:32:45.823490 01400000 ################################################################
10212 12:32:45.823676
10213 12:32:46.355875 01480000 ################################################################
10214 12:32:46.356051
10215 12:32:46.902143 01500000 ################################################################
10216 12:32:46.902309
10217 12:32:47.443106 01580000 ################################################################
10218 12:32:47.443255
10219 12:32:47.979277 01600000 ################################################################
10220 12:32:47.979424
10221 12:32:48.525413 01680000 ################################################################
10222 12:32:48.525562
10223 12:32:49.076878 01700000 ################################################################
10224 12:32:49.077038
10225 12:32:49.609228 01780000 ################################################################
10226 12:32:49.609432
10227 12:32:50.177281 01800000 ################################################################
10228 12:32:50.177461
10229 12:32:50.715856 01880000 ################################################################
10230 12:32:50.716061
10231 12:32:51.244872 01900000 ################################################################
10232 12:32:51.245024
10233 12:32:51.784082 01980000 ################################################################
10234 12:32:51.784227
10235 12:32:52.309663 01a00000 ############################################################### done.
10236 12:32:52.309816
10237 12:32:52.313417 The bootfile was 27774302 bytes long.
10238 12:32:52.313558
10239 12:32:52.316293 Sending tftp read request... done.
10240 12:32:52.316376
10241 12:32:52.316442 Waiting for the transfer...
10242 12:32:52.316504
10243 12:32:52.319768 00000000 # done.
10244 12:32:52.319854
10245 12:32:52.326173 Command line loaded dynamically from TFTP file: 10605801/tftp-deploy-l8ntmx1e/kernel/cmdline
10246 12:32:52.326268
10247 12:32:52.345594 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10248 12:32:52.345695
10249 12:32:52.348955 Loading FIT.
10250 12:32:52.349032
10251 12:32:52.352266 Image ramdisk-1 has 17638593 bytes.
10252 12:32:52.352345
10253 12:32:52.355680 Image fdt-1 has 46924 bytes.
10254 12:32:52.355765
10255 12:32:52.355832 Image kernel-1 has 10086749 bytes.
10256 12:32:52.358938
10257 12:32:52.365667 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10258 12:32:52.365748
10259 12:32:52.385687 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10260 12:32:52.385777
10261 12:32:52.388600 Choosing best match conf-1 for compat google,spherion-rev2.
10262 12:32:52.393356
10263 12:32:52.397957 Connected to device vid:did:rid of 1ae0:0028:00
10264 12:32:52.405661
10265 12:32:52.409258 tpm_get_response: command 0x17b, return code 0x0
10266 12:32:52.409343
10267 12:32:52.412258 ec_init: CrosEC protocol v3 supported (256, 248)
10268 12:32:52.416516
10269 12:32:52.420134 tpm_cleanup: add release locality here.
10270 12:32:52.420209
10271 12:32:52.420283 Shutting down all USB controllers.
10272 12:32:52.423075
10273 12:32:52.423187 Removing current net device
10274 12:32:52.423259
10275 12:32:52.429509 Exiting depthcharge with code 4 at timestamp: 68941938
10276 12:32:52.429602
10277 12:32:52.433084 LZMA decompressing kernel-1 to 0x821a6718
10278 12:32:52.433158
10279 12:32:52.436111 LZMA decompressing kernel-1 to 0x40000000
10280 12:32:53.702845
10281 12:32:53.703000 jumping to kernel
10282 12:32:53.703400 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10283 12:32:53.703501 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10284 12:32:53.703581 Setting prompt string to ['Linux version [0-9]']
10285 12:32:53.703690 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10286 12:32:53.703759 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10287 12:32:53.784806
10288 12:32:53.787687 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10289 12:32:53.791314 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10290 12:32:53.791408 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10291 12:32:53.791493 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10292 12:32:53.791572 Using line separator: #'\n'#
10293 12:32:53.791633 No login prompt set.
10294 12:32:53.791694 Parsing kernel messages
10295 12:32:53.791750 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10296 12:32:53.791850 [login-action] Waiting for messages, (timeout 00:03:44)
10297 12:32:53.810941 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10298 12:32:53.814464 [ 0.000000] random: crng init done
10299 12:32:53.821001 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10300 12:32:53.823900 [ 0.000000] efi: UEFI not found.
10301 12:32:53.830532 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10302 12:32:53.836873 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10303 12:32:53.846749 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10304 12:32:53.856687 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10305 12:32:53.863380 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10306 12:32:53.869943 [ 0.000000] printk: bootconsole [mtk8250] enabled
10307 12:32:53.876537 [ 0.000000] NUMA: No NUMA configuration found
10308 12:32:53.883501 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10309 12:32:53.886354 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10310 12:32:53.889819 [ 0.000000] Zone ranges:
10311 12:32:53.896753 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10312 12:32:53.899723 [ 0.000000] DMA32 empty
10313 12:32:53.906421 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10314 12:32:53.909477 [ 0.000000] Movable zone start for each node
10315 12:32:53.912833 [ 0.000000] Early memory node ranges
10316 12:32:53.919213 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10317 12:32:53.925718 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10318 12:32:53.932321 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10319 12:32:53.938898 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10320 12:32:53.945692 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10321 12:32:53.952671 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10322 12:32:54.008279 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10323 12:32:54.015374 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10324 12:32:54.021722 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10325 12:32:54.025334 [ 0.000000] psci: probing for conduit method from DT.
10326 12:32:54.031710 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10327 12:32:54.034666 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10328 12:32:54.041328 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10329 12:32:54.044826 [ 0.000000] psci: SMC Calling Convention v1.2
10330 12:32:54.051627 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10331 12:32:54.054530 [ 0.000000] Detected VIPT I-cache on CPU0
10332 12:32:54.061109 [ 0.000000] CPU features: detected: GIC system register CPU interface
10333 12:32:54.068078 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10334 12:32:54.074483 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10335 12:32:54.080899 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10336 12:32:54.090885 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10337 12:32:54.097261 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10338 12:32:54.100645 [ 0.000000] alternatives: applying boot alternatives
10339 12:32:54.107147 [ 0.000000] Fallback order for Node 0: 0
10340 12:32:54.113730 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10341 12:32:54.117428 [ 0.000000] Policy zone: Normal
10342 12:32:54.137107 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10343 12:32:54.146643 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10344 12:32:54.159200 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10345 12:32:54.168806 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10346 12:32:54.175510 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10347 12:32:54.178534 <6>[ 0.000000] software IO TLB: area num 8.
10348 12:32:54.234982 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10349 12:32:54.383927 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10350 12:32:54.390464 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10351 12:32:54.397057 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10352 12:32:54.400571 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10353 12:32:54.407122 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10354 12:32:54.413880 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10355 12:32:54.416796 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10356 12:32:54.426511 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10357 12:32:54.433651 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10358 12:32:54.440108 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10359 12:32:54.446463 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10360 12:32:54.450088 <6>[ 0.000000] GICv3: 608 SPIs implemented
10361 12:32:54.453184 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10362 12:32:54.459667 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10363 12:32:54.462990 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10364 12:32:54.469879 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10365 12:32:54.482824 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10366 12:32:54.495753 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10367 12:32:54.502793 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10368 12:32:54.510975 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10369 12:32:54.523758 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10370 12:32:54.530352 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10371 12:32:54.537486 <6>[ 0.009227] Console: colour dummy device 80x25
10372 12:32:54.547216 <6>[ 0.013983] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10373 12:32:54.553685 <6>[ 0.024425] pid_max: default: 32768 minimum: 301
10374 12:32:54.557290 <6>[ 0.029299] LSM: Security Framework initializing
10375 12:32:54.563909 <6>[ 0.034267] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10376 12:32:54.573564 <6>[ 0.042129] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 12:32:54.583013 <6>[ 0.051562] cblist_init_generic: Setting adjustable number of callback queues.
10378 12:32:54.586579 <6>[ 0.059015] cblist_init_generic: Setting shift to 3 and lim to 1.
10379 12:32:54.593288 <6>[ 0.065354] cblist_init_generic: Setting shift to 3 and lim to 1.
10380 12:32:54.599857 <6>[ 0.071762] rcu: Hierarchical SRCU implementation.
10381 12:32:54.606331 <6>[ 0.076777] rcu: Max phase no-delay instances is 1000.
10382 12:32:54.612994 <6>[ 0.083832] EFI services will not be available.
10383 12:32:54.616608 <6>[ 0.088802] smp: Bringing up secondary CPUs ...
10384 12:32:54.624208 <6>[ 0.093853] Detected VIPT I-cache on CPU1
10385 12:32:54.630982 <6>[ 0.093926] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10386 12:32:54.637670 <6>[ 0.093956] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10387 12:32:54.640568 <6>[ 0.094291] Detected VIPT I-cache on CPU2
10388 12:32:54.650268 <6>[ 0.094340] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10389 12:32:54.657244 <6>[ 0.094355] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10390 12:32:54.660180 <6>[ 0.094615] Detected VIPT I-cache on CPU3
10391 12:32:54.666720 <6>[ 0.094662] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10392 12:32:54.673771 <6>[ 0.094676] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10393 12:32:54.679955 <6>[ 0.094982] CPU features: detected: Spectre-v4
10394 12:32:54.683615 <6>[ 0.094989] CPU features: detected: Spectre-BHB
10395 12:32:54.686593 <6>[ 0.094995] Detected PIPT I-cache on CPU4
10396 12:32:54.696454 <6>[ 0.095053] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10397 12:32:54.703071 <6>[ 0.095070] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10398 12:32:54.706594 <6>[ 0.095365] Detected PIPT I-cache on CPU5
10399 12:32:54.713155 <6>[ 0.095428] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10400 12:32:54.719366 <6>[ 0.095445] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10401 12:32:54.722899 <6>[ 0.095730] Detected PIPT I-cache on CPU6
10402 12:32:54.732367 <6>[ 0.095795] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10403 12:32:54.738861 <6>[ 0.095810] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10404 12:32:54.742489 <6>[ 0.096109] Detected PIPT I-cache on CPU7
10405 12:32:54.748885 <6>[ 0.096174] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10406 12:32:54.755698 <6>[ 0.096190] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10407 12:32:54.762326 <6>[ 0.096237] smp: Brought up 1 node, 8 CPUs
10408 12:32:54.765230 <6>[ 0.237644] SMP: Total of 8 processors activated.
10409 12:32:54.771847 <6>[ 0.242595] CPU features: detected: 32-bit EL0 Support
10410 12:32:54.778773 <6>[ 0.247958] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10411 12:32:54.785203 <6>[ 0.256758] CPU features: detected: Common not Private translations
10412 12:32:54.791917 <6>[ 0.263234] CPU features: detected: CRC32 instructions
10413 12:32:54.798255 <6>[ 0.268585] CPU features: detected: RCpc load-acquire (LDAPR)
10414 12:32:54.805204 <6>[ 0.274545] CPU features: detected: LSE atomic instructions
10415 12:32:54.808163 <6>[ 0.280326] CPU features: detected: Privileged Access Never
10416 12:32:54.814660 <6>[ 0.286105] CPU features: detected: RAS Extension Support
10417 12:32:54.821308 <6>[ 0.291713] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10418 12:32:54.824760 <6>[ 0.298933] CPU: All CPU(s) started at EL2
10419 12:32:54.831114 <6>[ 0.303277] alternatives: applying system-wide alternatives
10420 12:32:54.841846 <6>[ 0.313992] devtmpfs: initialized
10421 12:32:54.854323 <6>[ 0.322968] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10422 12:32:54.864210 <6>[ 0.332927] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10423 12:32:54.867187 <6>[ 0.340540] pinctrl core: initialized pinctrl subsystem
10424 12:32:54.874830 <6>[ 0.347205] DMI not present or invalid.
10425 12:32:54.881814 <6>[ 0.351617] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10426 12:32:54.888149 <6>[ 0.358510] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10427 12:32:54.898125 <6>[ 0.366089] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10428 12:32:54.904767 <6>[ 0.374315] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10429 12:32:54.911273 <6>[ 0.382559] audit: initializing netlink subsys (disabled)
10430 12:32:54.918358 <5>[ 0.388249] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10431 12:32:54.925055 <6>[ 0.388951] thermal_sys: Registered thermal governor 'step_wise'
10432 12:32:54.931531 <6>[ 0.396219] thermal_sys: Registered thermal governor 'power_allocator'
10433 12:32:54.937769 <6>[ 0.402475] cpuidle: using governor menu
10434 12:32:54.941169 <6>[ 0.413440] NET: Registered PF_QIPCRTR protocol family
10435 12:32:54.947740 <6>[ 0.418926] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10436 12:32:54.954261 <6>[ 0.426028] ASID allocator initialised with 32768 entries
10437 12:32:54.961278 <6>[ 0.432596] Serial: AMBA PL011 UART driver
10438 12:32:54.969192 <4>[ 0.441310] Trying to register duplicate clock ID: 134
10439 12:32:55.025124 <6>[ 0.500793] KASLR enabled
10440 12:32:55.039772 <6>[ 0.508502] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10441 12:32:55.046361 <6>[ 0.515513] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10442 12:32:55.052928 <6>[ 0.522001] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10443 12:32:55.059378 <6>[ 0.529008] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10444 12:32:55.065785 <6>[ 0.535494] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10445 12:32:55.072486 <6>[ 0.542500] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10446 12:32:55.079089 <6>[ 0.548989] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10447 12:32:55.085852 <6>[ 0.555994] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10448 12:32:55.089345 <6>[ 0.563488] ACPI: Interpreter disabled.
10449 12:32:55.097574 <6>[ 0.569891] iommu: Default domain type: Translated
10450 12:32:55.104505 <6>[ 0.575030] iommu: DMA domain TLB invalidation policy: strict mode
10451 12:32:55.107884 <5>[ 0.581688] SCSI subsystem initialized
10452 12:32:55.114183 <6>[ 0.585926] usbcore: registered new interface driver usbfs
10453 12:32:55.120817 <6>[ 0.591655] usbcore: registered new interface driver hub
10454 12:32:55.124368 <6>[ 0.597210] usbcore: registered new device driver usb
10455 12:32:55.131476 <6>[ 0.603324] pps_core: LinuxPPS API ver. 1 registered
10456 12:32:55.141088 <6>[ 0.608516] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10457 12:32:55.144557 <6>[ 0.617857] PTP clock support registered
10458 12:32:55.147451 <6>[ 0.622096] EDAC MC: Ver: 3.0.0
10459 12:32:55.155377 <6>[ 0.627272] FPGA manager framework
10460 12:32:55.161563 <6>[ 0.630949] Advanced Linux Sound Architecture Driver Initialized.
10461 12:32:55.164970 <6>[ 0.637730] vgaarb: loaded
10462 12:32:55.171850 <6>[ 0.640906] clocksource: Switched to clocksource arch_sys_counter
10463 12:32:55.175196 <5>[ 0.647354] VFS: Disk quotas dquot_6.6.0
10464 12:32:55.181469 <6>[ 0.651541] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10465 12:32:55.184885 <6>[ 0.658713] pnp: PnP ACPI: disabled
10466 12:32:55.193167 <6>[ 0.665405] NET: Registered PF_INET protocol family
10467 12:32:55.203410 <6>[ 0.670981] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10468 12:32:55.214244 <6>[ 0.683279] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10469 12:32:55.224180 <6>[ 0.692088] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10470 12:32:55.231022 <6>[ 0.700057] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10471 12:32:55.241081 <6>[ 0.708758] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10472 12:32:55.247448 <6>[ 0.718493] TCP: Hash tables configured (established 65536 bind 65536)
10473 12:32:55.253776 <6>[ 0.725348] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10474 12:32:55.263924 <6>[ 0.732542] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10475 12:32:55.270083 <6>[ 0.740247] NET: Registered PF_UNIX/PF_LOCAL protocol family
10476 12:32:55.276622 <6>[ 0.746415] RPC: Registered named UNIX socket transport module.
10477 12:32:55.280462 <6>[ 0.752569] RPC: Registered udp transport module.
10478 12:32:55.286880 <6>[ 0.757499] RPC: Registered tcp transport module.
10479 12:32:55.293258 <6>[ 0.762433] RPC: Registered tcp NFSv4.1 backchannel transport module.
10480 12:32:55.296669 <6>[ 0.769103] PCI: CLS 0 bytes, default 64
10481 12:32:55.299957 <6>[ 0.773495] Unpacking initramfs...
10482 12:32:55.309949 <6>[ 0.777591] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10483 12:32:55.316447 <6>[ 0.786230] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10484 12:32:55.323135 <6>[ 0.795067] kvm [1]: IPA Size Limit: 40 bits
10485 12:32:55.326466 <6>[ 0.799602] kvm [1]: GICv3: no GICV resource entry
10486 12:32:55.332989 <6>[ 0.804620] kvm [1]: disabling GICv2 emulation
10487 12:32:55.339350 <6>[ 0.809305] kvm [1]: GIC system register CPU interface enabled
10488 12:32:55.342947 <6>[ 0.815469] kvm [1]: vgic interrupt IRQ18
10489 12:32:55.349205 <6>[ 0.819846] kvm [1]: VHE mode initialized successfully
10490 12:32:55.352675 <5>[ 0.826295] Initialise system trusted keyrings
10491 12:32:55.359093 <6>[ 0.831133] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10492 12:32:55.369494 <6>[ 0.841418] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10493 12:32:55.376273 <5>[ 0.847801] NFS: Registering the id_resolver key type
10494 12:32:55.379025 <5>[ 0.853106] Key type id_resolver registered
10495 12:32:55.385803 <5>[ 0.857519] Key type id_legacy registered
10496 12:32:55.392089 <6>[ 0.861818] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10497 12:32:55.398942 <6>[ 0.868737] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10498 12:32:55.405162 <6>[ 0.876456] 9p: Installing v9fs 9p2000 file system support
10499 12:32:55.441879 <5>[ 0.913716] Key type asymmetric registered
10500 12:32:55.444925 <5>[ 0.918045] Asymmetric key parser 'x509' registered
10501 12:32:55.455166 <6>[ 0.923186] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10502 12:32:55.458638 <6>[ 0.930800] io scheduler mq-deadline registered
10503 12:32:55.461518 <6>[ 0.935561] io scheduler kyber registered
10504 12:32:55.480364 <6>[ 0.952420] EINJ: ACPI disabled.
10505 12:32:55.512424 <4>[ 0.977791] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10506 12:32:55.522256 <4>[ 0.988417] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10507 12:32:55.537236 <6>[ 1.009117] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10508 12:32:55.545138 <6>[ 1.017173] printk: console [ttyS0] disabled
10509 12:32:55.572825 <6>[ 1.041836] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10510 12:32:55.579684 <6>[ 1.051312] printk: console [ttyS0] enabled
10511 12:32:55.583222 <6>[ 1.051312] printk: console [ttyS0] enabled
10512 12:32:55.589808 <6>[ 1.060207] printk: bootconsole [mtk8250] disabled
10513 12:32:55.593069 <6>[ 1.060207] printk: bootconsole [mtk8250] disabled
10514 12:32:55.599724 <6>[ 1.071480] SuperH (H)SCI(F) driver initialized
10515 12:32:55.602620 <6>[ 1.076756] msm_serial: driver initialized
10516 12:32:55.616829 <6>[ 1.085656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10517 12:32:55.626774 <6>[ 1.094203] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10518 12:32:55.633551 <6>[ 1.102745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10519 12:32:55.643406 <6>[ 1.111374] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10520 12:32:55.653382 <6>[ 1.120081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10521 12:32:55.659660 <6>[ 1.128805] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10522 12:32:55.669537 <6>[ 1.137346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10523 12:32:55.676546 <6>[ 1.146163] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10524 12:32:55.685877 <6>[ 1.154709] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10525 12:32:55.698457 <6>[ 1.170324] loop: module loaded
10526 12:32:55.704556 <6>[ 1.176352] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10527 12:32:55.727703 <4>[ 1.199705] mtk-pmic-keys: Failed to locate of_node [id: -1]
10528 12:32:55.734177 <6>[ 1.206478] megasas: 07.719.03.00-rc1
10529 12:32:55.743488 <6>[ 1.216009] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10530 12:32:55.756395 <6>[ 1.228323] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10531 12:32:55.772134 <6>[ 1.244337] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10532 12:32:55.828927 <6>[ 1.294152] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10533 12:32:56.070470 <6>[ 1.542862] Freeing initrd memory: 17220K
10534 12:32:56.081042 <6>[ 1.553139] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10535 12:32:56.091915 <6>[ 1.563999] tun: Universal TUN/TAP device driver, 1.6
10536 12:32:56.095445 <6>[ 1.570054] thunder_xcv, ver 1.0
10537 12:32:56.098298 <6>[ 1.573560] thunder_bgx, ver 1.0
10538 12:32:56.101813 <6>[ 1.577058] nicpf, ver 1.0
10539 12:32:56.112145 <6>[ 1.581056] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10540 12:32:56.115565 <6>[ 1.588531] hns3: Copyright (c) 2017 Huawei Corporation.
10541 12:32:56.121909 <6>[ 1.594118] hclge is initializing
10542 12:32:56.125309 <6>[ 1.597697] e1000: Intel(R) PRO/1000 Network Driver
10543 12:32:56.132074 <6>[ 1.602826] e1000: Copyright (c) 1999-2006 Intel Corporation.
10544 12:32:56.135412 <6>[ 1.608843] e1000e: Intel(R) PRO/1000 Network Driver
10545 12:32:56.142124 <6>[ 1.614058] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10546 12:32:56.148431 <6>[ 1.620243] igb: Intel(R) Gigabit Ethernet Network Driver
10547 12:32:56.155344 <6>[ 1.625894] igb: Copyright (c) 2007-2014 Intel Corporation.
10548 12:32:56.161611 <6>[ 1.631729] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10549 12:32:56.168522 <6>[ 1.638248] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10550 12:32:56.172076 <6>[ 1.644707] sky2: driver version 1.30
10551 12:32:56.178578 <6>[ 1.649702] VFIO - User Level meta-driver version: 0.3
10552 12:32:56.185617 <6>[ 1.657904] usbcore: registered new interface driver usb-storage
10553 12:32:56.192484 <6>[ 1.664344] usbcore: registered new device driver onboard-usb-hub
10554 12:32:56.201093 <6>[ 1.673455] mt6397-rtc mt6359-rtc: registered as rtc0
10555 12:32:56.211096 <6>[ 1.678924] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:32:56 UTC (1686054776)
10556 12:32:56.214604 <6>[ 1.688482] i2c_dev: i2c /dev entries driver
10557 12:32:56.231079 <6>[ 1.700136] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10558 12:32:56.238457 <6>[ 1.710335] sdhci: Secure Digital Host Controller Interface driver
10559 12:32:56.244625 <6>[ 1.716773] sdhci: Copyright(c) Pierre Ossman
10560 12:32:56.251282 <6>[ 1.722185] Synopsys Designware Multimedia Card Interface Driver
10561 12:32:56.254555 <6>[ 1.728759] mmc0: CQHCI version 5.10
10562 12:32:56.261055 <6>[ 1.729338] sdhci-pltfm: SDHCI platform and OF driver helper
10563 12:32:56.268374 <6>[ 1.740604] ledtrig-cpu: registered to indicate activity on CPUs
10564 12:32:56.278915 <6>[ 1.747925] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10565 12:32:56.282495 <6>[ 1.755337] usbcore: registered new interface driver usbhid
10566 12:32:56.288785 <6>[ 1.761171] usbhid: USB HID core driver
10567 12:32:56.295557 <6>[ 1.765412] spi_master spi0: will run message pump with realtime priority
10568 12:32:56.342310 <6>[ 1.808003] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10569 12:32:56.361144 <6>[ 1.823362] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10570 12:32:56.364043 <6>[ 1.836960] mmc0: Command Queue Engine enabled
10571 12:32:56.371386 <6>[ 1.838267] cros-ec-spi spi0.0: Chrome EC device registered
10572 12:32:56.377937 <6>[ 1.841695] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10573 12:32:56.380860 <6>[ 1.854800] mmcblk0: mmc0:0001 DA4128 116 GiB
10574 12:32:56.395182 <6>[ 1.864233] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10575 12:32:56.401955 <6>[ 1.864753] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10576 12:32:56.408810 <6>[ 1.875658] NET: Registered PF_PACKET protocol family
10577 12:32:56.411773 <6>[ 1.880709] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10578 12:32:56.418656 <6>[ 1.884921] 9pnet: Installing 9P2000 support
10579 12:32:56.421605 <6>[ 1.890681] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10580 12:32:56.428457 <5>[ 1.894573] Key type dns_resolver registered
10581 12:32:56.435422 <6>[ 1.900416] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10582 12:32:56.438319 <6>[ 1.904811] registered taskstats version 1
10583 12:32:56.441606 <5>[ 1.915174] Loading compiled-in X.509 certificates
10584 12:32:56.476275 <4>[ 1.942043] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 12:32:56.486559 <4>[ 1.952726] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 12:32:56.496511 <3>[ 1.965610] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10587 12:32:56.508721 <6>[ 1.981158] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10588 12:32:56.515759 <6>[ 1.987984] xhci-mtk 11200000.usb: xHCI Host Controller
10589 12:32:56.522158 <6>[ 1.993485] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10590 12:32:56.532633 <6>[ 2.001356] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10591 12:32:56.538864 <6>[ 2.010786] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10592 12:32:56.545708 <6>[ 2.016977] xhci-mtk 11200000.usb: xHCI Host Controller
10593 12:32:56.552424 <6>[ 2.022476] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10594 12:32:56.559220 <6>[ 2.030138] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10595 12:32:56.566017 <6>[ 2.038044] hub 1-0:1.0: USB hub found
10596 12:32:56.568978 <6>[ 2.042083] hub 1-0:1.0: 1 port detected
10597 12:32:56.579204 <6>[ 2.046441] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10598 12:32:56.582706 <6>[ 2.055237] hub 2-0:1.0: USB hub found
10599 12:32:56.585535 <6>[ 2.059271] hub 2-0:1.0: 1 port detected
10600 12:32:56.594151 <6>[ 2.066352] mtk-msdc 11f70000.mmc: Got CD GPIO
10601 12:32:56.611590 <6>[ 2.080203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 12:32:56.617941 <6>[ 2.088269] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 12:32:56.628055 <4>[ 2.096277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 12:32:56.638098 <6>[ 2.105938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 12:32:56.644784 <6>[ 2.114020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 12:32:56.651018 <6>[ 2.122053] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 12:32:56.661577 <6>[ 2.129969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 12:32:56.667773 <6>[ 2.137789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 12:32:56.677587 <6>[ 2.145617] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 12:32:56.687823 <6>[ 2.156295] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 12:32:56.694536 <6>[ 2.164683] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 12:32:56.704527 <6>[ 2.173038] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 12:32:56.710765 <6>[ 2.181382] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 12:32:56.720809 <6>[ 2.189726] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 12:32:56.730682 <6>[ 2.198068] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 12:32:56.737532 <6>[ 2.206412] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 12:32:56.747286 <6>[ 2.214754] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 12:32:56.753686 <6>[ 2.223097] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 12:32:56.763671 <6>[ 2.231439] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 12:32:56.770511 <6>[ 2.239782] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 12:32:56.780259 <6>[ 2.248125] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 12:32:56.786926 <6>[ 2.256473] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 12:32:56.797187 <6>[ 2.264816] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 12:32:56.803583 <6>[ 2.273161] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 12:32:56.809936 <6>[ 2.282084] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 12:32:56.817333 <6>[ 2.289569] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 12:32:56.824248 <6>[ 2.296600] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 12:32:56.834528 <6>[ 2.303688] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 12:32:56.841141 <6>[ 2.310958] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 12:32:56.851180 <6>[ 2.317828] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 12:32:56.858244 <6>[ 2.326983] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 12:32:56.868037 <6>[ 2.336129] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 12:32:56.877624 <6>[ 2.345432] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 12:32:56.887554 <6>[ 2.354907] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 12:32:56.897879 <6>[ 2.364381] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 12:32:56.904204 <6>[ 2.373511] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 12:32:56.914082 <6>[ 2.382986] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 12:32:56.923977 <6>[ 2.392113] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 12:32:56.933933 <6>[ 2.401415] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 12:32:56.943973 <6>[ 2.411581] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 12:32:56.953882 <6>[ 2.422906] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 12:32:56.960824 <6>[ 2.432836] Trying to probe devices needed for running init ...
10643 12:32:56.976082 <6>[ 2.445331] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10644 12:32:57.005130 <6>[ 2.477233] hub 2-1:1.0: USB hub found
10645 12:32:57.007910 <6>[ 2.481765] hub 2-1:1.0: 3 ports detected
10646 12:32:57.128424 <6>[ 2.597152] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10647 12:32:57.280889 <6>[ 2.753503] hub 1-1:1.0: USB hub found
10648 12:32:57.284338 <6>[ 2.757930] hub 1-1:1.0: 4 ports detected
10649 12:32:57.360424 <6>[ 2.829426] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10650 12:32:57.604390 <6>[ 3.073179] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10651 12:32:57.737047 <6>[ 3.209437] hub 1-1.4:1.0: USB hub found
10652 12:32:57.740291 <6>[ 3.214090] hub 1-1.4:1.0: 2 ports detected
10653 12:32:58.036274 <6>[ 3.505180] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10654 12:32:58.228196 <6>[ 3.697180] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10655 12:33:09.260945 <6>[ 14.737732] ALSA device list:
10656 12:33:09.267554 <6>[ 14.740988] No soundcards found.
10657 12:33:09.279800 <6>[ 14.753390] Freeing unused kernel memory: 8384K
10658 12:33:09.282824 <6>[ 14.758328] Run /init as init process
10659 12:33:09.293259 Loading, please wait...
10660 12:33:09.312580 Starting version 247.3-7+deb11u2
10661 12:33:09.630583 <6>[ 15.100784] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10662 12:33:09.644993 <6>[ 15.118377] remoteproc remoteproc0: scp is available
10663 12:33:09.657906 <4>[ 15.127883] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10664 12:33:09.664304 <6>[ 15.137839] remoteproc remoteproc0: powering up scp
10665 12:33:09.674308 <4>[ 15.143015] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10666 12:33:09.680780 <3>[ 15.149448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 12:33:09.687202 <3>[ 15.153188] remoteproc remoteproc0: request_firmware failed: -2
10668 12:33:09.697232 <3>[ 15.160961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 12:33:09.703819 <3>[ 15.160977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 12:33:09.714362 <3>[ 15.184339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 12:33:09.720801 <6>[ 15.186896] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10672 12:33:09.730569 <3>[ 15.192544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 12:33:09.737422 <6>[ 15.200475] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10674 12:33:09.747328 <3>[ 15.208221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 12:33:09.753796 <6>[ 15.216973] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10676 12:33:09.763737 <3>[ 15.224988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 12:33:09.766958 <6>[ 15.227667] mc: Linux media interface: v0.10
10678 12:33:09.773881 <6>[ 15.242915] videodev: Linux video capture interface: v2.00
10679 12:33:09.780000 <3>[ 15.246315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 12:33:09.789944 <6>[ 15.246757] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10681 12:33:09.796550 <3>[ 15.267843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 12:33:09.807468 <4>[ 15.277882] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10683 12:33:09.813863 <3>[ 15.285460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 12:33:09.823788 <4>[ 15.285534] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10685 12:33:09.827329 <4>[ 15.285534] Fallback method does not support PEC.
10686 12:33:09.837096 <4>[ 15.291914] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10687 12:33:09.844429 <3>[ 15.293609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 12:33:09.850830 <3>[ 15.293620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 12:33:09.860993 <3>[ 15.293742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 12:33:09.864367 <6>[ 15.316296] usbcore: registered new interface driver r8152
10691 12:33:09.874654 <3>[ 15.322857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 12:33:09.881509 <3>[ 15.325773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10693 12:33:09.891447 <3>[ 15.349255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 12:33:09.901412 <3>[ 15.352752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 12:33:09.907644 <6>[ 15.366093] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10696 12:33:09.914706 <3>[ 15.370285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 12:33:09.921061 <6>[ 15.378371] pci_bus 0000:00: root bus resource [bus 00-ff]
10698 12:33:09.927969 <3>[ 15.385233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 12:33:09.934362 <6>[ 15.393311] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10700 12:33:09.944167 <3>[ 15.399077] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 12:33:09.953775 <6>[ 15.399757] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10702 12:33:09.964433 <6>[ 15.401907] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10703 12:33:09.970683 <6>[ 15.402180] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10704 12:33:09.980586 <6>[ 15.407139] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10705 12:33:09.987255 <6>[ 15.422947] usbcore: registered new interface driver cdc_ether
10706 12:33:09.993554 <6>[ 15.431982] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10707 12:33:10.000484 <6>[ 15.432007] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10708 12:33:10.010100 <6>[ 15.432528] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10709 12:33:10.013520 <6>[ 15.432622] pci 0000:00:00.0: supports D1 D2
10710 12:33:10.019817 <6>[ 15.432627] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 12:33:10.026970 <6>[ 15.433397] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10712 12:33:10.036849 <6>[ 15.434772] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10713 12:33:10.043215 <6>[ 15.434994] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10714 12:33:10.050115 <6>[ 15.435029] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10715 12:33:10.056400 <6>[ 15.435053] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10716 12:33:10.063442 <6>[ 15.435077] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10717 12:33:10.069770 <6>[ 15.435207] pci 0000:01:00.0: supports D1 D2
10718 12:33:10.076264 <6>[ 15.435211] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 12:33:10.089652 <6>[ 15.435258] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10720 12:33:10.092964 <6>[ 15.435444] usbcore: registered new interface driver uvcvideo
10721 12:33:10.103174 <6>[ 15.444962] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10722 12:33:10.106502 <6>[ 15.451668] usbcore: registered new interface driver r8153_ecm
10723 12:33:10.113282 <6>[ 15.451696] Bluetooth: Core ver 2.22
10724 12:33:10.116516 <6>[ 15.451766] NET: Registered PF_BLUETOOTH protocol family
10725 12:33:10.122794 <6>[ 15.451769] Bluetooth: HCI device and connection manager initialized
10726 12:33:10.129227 <6>[ 15.451792] Bluetooth: HCI socket layer initialized
10727 12:33:10.132758 <6>[ 15.451800] Bluetooth: L2CAP socket layer initialized
10728 12:33:10.139055 <6>[ 15.451814] Bluetooth: SCO socket layer initialized
10729 12:33:10.146012 <6>[ 15.452604] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10730 12:33:10.152228 <6>[ 15.460808] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10731 12:33:10.162526 <4>[ 15.477038] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10732 12:33:10.168938 <6>[ 15.480256] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10733 12:33:10.178782 <4>[ 15.487738] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10734 12:33:10.185501 <6>[ 15.492264] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10735 12:33:10.191986 <6>[ 15.506861] usbcore: registered new interface driver btusb
10736 12:33:10.202016 <4>[ 15.507467] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10737 12:33:10.208687 <3>[ 15.507475] Bluetooth: hci0: Failed to load firmware file (-2)
10738 12:33:10.215259 <3>[ 15.507479] Bluetooth: hci0: Failed to set up firmware (-2)
10739 12:33:10.224965 <4>[ 15.507483] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10740 12:33:10.231961 <6>[ 15.514432] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10741 12:33:10.238265 <6>[ 15.545241] r8152 2-1.3:1.0 eth0: v1.12.13
10742 12:33:10.244967 <6>[ 15.547627] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10743 12:33:10.251426 <6>[ 15.562924] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10744 12:33:10.257866 <6>[ 15.566906] pci 0000:00:00.0: PCI bridge to [bus 01]
10745 12:33:10.265081 <6>[ 15.735280] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10746 12:33:10.271664 <6>[ 15.743527] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10747 12:33:10.277933 <6>[ 15.750776] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10748 12:33:10.284775 <6>[ 15.757493] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10749 12:33:10.303695 <5>[ 15.773901] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10750 12:33:10.322865 <5>[ 15.793136] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10751 12:33:10.329728 <4>[ 15.800067] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10752 12:33:10.335847 <6>[ 15.808967] cfg80211: failed to load regulatory.db
10753 12:33:10.381923 <6>[ 15.851777] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10754 12:33:10.387976 <6>[ 15.859382] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10755 12:33:10.412594 <6>[ 15.886094] mt7921e 0000:01:00.0: ASIC revision: 79610010
10756 12:33:10.518455 <4>[ 15.985409] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10757 12:33:10.535844 Begin: Loading essential drivers ... done.
10758 12:33:10.538599 Begin: Running /scripts/init-premount ... done.
10759 12:33:10.545590 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10760 12:33:10.555335 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10761 12:33:10.558678 Device /sys/class/net/enx002432307c7b found
10762 12:33:10.559147 done.
10763 12:33:10.594837 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10764 12:33:10.640349 <4>[ 16.107236] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10765 12:33:10.755971 <4>[ 16.222712] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 12:33:10.871188 <4>[ 16.338579] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 12:33:10.987480 <4>[ 16.454486] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 12:33:11.103474 <4>[ 16.570447] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 12:33:11.218880 <4>[ 16.686499] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 12:33:11.334986 <4>[ 16.802425] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 12:33:11.450884 <4>[ 16.918435] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 12:33:11.566894 <4>[ 17.034260] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 12:33:11.674023 <3>[ 17.148283] mt7921e 0000:01:00.0: hardware init failed
10774 12:33:11.704870 IP-Config: no response after 2 secs - giving up
10775 12:33:11.750601 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10776 12:33:11.798875 <6>[ 17.272799] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10777 12:33:12.855085 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10778 12:33:12.861793 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10779 12:33:12.868531 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10780 12:33:12.874991 host : mt8192-asurada-spherion-r0-cbg-2
10781 12:33:12.881658 domain : lava-rack
10782 12:33:12.887844 rootserver: 192.168.201.1 rootpath:
10783 12:33:12.887928 filename :
10784 12:33:12.923548 done.
10785 12:33:12.930366 Begin: Running /scripts/nfs-bottom ... done.
10786 12:33:12.949012 Begin: Running /scripts/init-bottom ... done.
10787 12:33:14.103503 <6>[ 19.577581] NET: Registered PF_INET6 protocol family
10788 12:33:14.110311 <6>[ 19.584649] Segment Routing with IPv6
10789 12:33:14.113674 <6>[ 19.588639] In-situ OAM (IOAM) with IPv6
10790 12:33:14.227657 <30>[ 19.685416] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10791 12:33:14.235144 <30>[ 19.709224] systemd[1]: Detected architecture arm64.
10792 12:33:14.254238
10793 12:33:14.257116 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10794 12:33:14.257200
10795 12:33:14.273313 <30>[ 19.747323] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10796 12:33:14.922627 <30>[ 20.393419] systemd[1]: Queued start job for default target Graphical Interface.
10797 12:33:14.948822 <30>[ 20.422405] systemd[1]: Created slice system-getty.slice.
10798 12:33:14.954806 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10799 12:33:14.971985 <30>[ 20.445928] systemd[1]: Created slice system-modprobe.slice.
10800 12:33:14.978345 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10801 12:33:14.995793 <30>[ 20.469809] systemd[1]: Created slice system-serial\x2dgetty.slice.
10802 12:33:15.005603 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10803 12:33:15.020192 <30>[ 20.494217] systemd[1]: Created slice User and Session Slice.
10804 12:33:15.027062 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10805 12:33:15.046915 <30>[ 20.517353] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10806 12:33:15.056571 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10807 12:33:15.070870 <30>[ 20.541350] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10808 12:33:15.077043 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10809 12:33:15.098193 <30>[ 20.565281] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10810 12:33:15.104522 <30>[ 20.577323] systemd[1]: Reached target Local Encrypted Volumes.
10811 12:33:15.111261 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10812 12:33:15.127091 <30>[ 20.601259] systemd[1]: Reached target Paths.
10813 12:33:15.130630 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10814 12:33:15.147405 <30>[ 20.621490] systemd[1]: Reached target Remote File Systems.
10815 12:33:15.154212 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10816 12:33:15.170963 <30>[ 20.645234] systemd[1]: Reached target Slices.
10817 12:33:15.177625 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10818 12:33:15.191178 <30>[ 20.665189] systemd[1]: Reached target Swap.
10819 12:33:15.194169 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10820 12:33:15.214869 <30>[ 20.685556] systemd[1]: Listening on initctl Compatibility Named Pipe.
10821 12:33:15.221341 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10822 12:33:15.228189 <30>[ 20.701223] systemd[1]: Listening on Journal Audit Socket.
10823 12:33:15.234604 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10824 12:33:15.247847 <30>[ 20.722124] systemd[1]: Listening on Journal Socket (/dev/log).
10825 12:33:15.254096 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10826 12:33:15.271806 <30>[ 20.745987] systemd[1]: Listening on Journal Socket.
10827 12:33:15.278208 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10828 12:33:15.291978 <30>[ 20.766508] systemd[1]: Listening on Network Service Netlink Socket.
10829 12:33:15.302241 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10830 12:33:15.317353 <30>[ 20.791681] systemd[1]: Listening on udev Control Socket.
10831 12:33:15.323921 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10832 12:33:15.339164 <30>[ 20.813490] systemd[1]: Listening on udev Kernel Socket.
10833 12:33:15.345734 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10834 12:33:15.391187 <30>[ 20.865578] systemd[1]: Mounting Huge Pages File System...
10835 12:33:15.397490 Mounting [0;1;39mHuge Pages File System[0m...
10836 12:33:15.413157 <30>[ 20.887467] systemd[1]: Mounting POSIX Message Queue File System...
10837 12:33:15.419717 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10838 12:33:15.436888 <30>[ 20.911503] systemd[1]: Mounting Kernel Debug File System...
10839 12:33:15.443567 Mounting [0;1;39mKernel Debug File System[0m...
10840 12:33:15.462094 <30>[ 20.933532] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10841 12:33:15.502652 <30>[ 20.973838] systemd[1]: Starting Create list of static device nodes for the current kernel...
10842 12:33:15.509234 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10843 12:33:15.529535 <30>[ 21.003814] systemd[1]: Starting Load Kernel Module configfs...
10844 12:33:15.535865 Starting [0;1;39mLoad Kernel Module configfs[0m...
10845 12:33:15.553501 <30>[ 21.027676] systemd[1]: Starting Load Kernel Module drm...
10846 12:33:15.559735 Starting [0;1;39mLoad Kernel Module drm[0m...
10847 12:33:15.577194 <30>[ 21.051831] systemd[1]: Starting Load Kernel Module fuse...
10848 12:33:15.583715 Starting [0;1;39mLoad Kernel Module fuse[0m...
10849 12:33:15.615935 <6>[ 21.090055] fuse: init (API version 7.37)
10850 12:33:15.625241 <30>[ 21.092810] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10851 12:33:15.655729 <30>[ 21.129806] systemd[1]: Starting Journal Service...
10852 12:33:15.658585 Starting [0;1;39mJournal Service[0m...
10853 12:33:15.684054 <30>[ 21.158313] systemd[1]: Starting Load Kernel Modules...
10854 12:33:15.690563 Starting [0;1;39mLoad Kernel Modules[0m...
10855 12:33:15.713013 <30>[ 21.184047] systemd[1]: Starting Remount Root and Kernel File Systems...
10856 12:33:15.719408 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10857 12:33:15.763387 <30>[ 21.237922] systemd[1]: Starting Coldplug All udev Devices...
10858 12:33:15.770331 Starting [0;1;39mColdplug All udev Devices[0m...
10859 12:33:15.790388 <30>[ 21.264838] systemd[1]: Mounted Huge Pages File System.
10860 12:33:15.797002 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10861 12:33:15.811256 <30>[ 21.285645] systemd[1]: Mounted POSIX Message Queue File System.
10862 12:33:15.817665 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10863 12:33:15.837960 <3>[ 21.309082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 12:33:15.844537 <30>[ 21.309668] systemd[1]: Mounted Kernel Debug File System.
10865 12:33:15.851346 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10866 12:33:15.868196 <3>[ 21.338976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 12:33:15.877475 <30>[ 21.348921] systemd[1]: Finished Create list of static device nodes for the current kernel.
10868 12:33:15.887680 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10869 12:33:15.903658 <30>[ 21.378226] systemd[1]: modprobe@configfs.service: Succeeded.
10870 12:33:15.910971 <30>[ 21.384884] systemd[1]: Finished Load Kernel Module configfs.
10871 12:33:15.921037 <3>[ 21.389585] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 12:33:15.927449 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10873 12:33:15.944429 <30>[ 21.418223] systemd[1]: modprobe@drm.service: Succeeded.
10874 12:33:15.951262 <30>[ 21.424458] systemd[1]: Finished Load Kernel Module drm.
10875 12:33:15.960978 <3>[ 21.425504] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:33:15.963877 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10877 12:33:15.980514 <30>[ 21.454464] systemd[1]: modprobe@fuse.service: Succeeded.
10878 12:33:15.987445 <30>[ 21.460839] systemd[1]: Finished Load Kernel Module fuse.
10879 12:33:15.997023 <3>[ 21.461781] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 12:33:16.003578 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10881 12:33:16.020065 <30>[ 21.494293] systemd[1]: Finished Load Kernel Modules.
10882 12:33:16.030374 <3>[ 21.496654] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 12:33:16.033283 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10884 12:33:16.052225 <30>[ 21.526384] systemd[1]: Finished Remount Root and Kernel File Systems.
10885 12:33:16.062034 <3>[ 21.531464] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 12:33:16.068875 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10887 12:33:16.092722 <3>[ 21.564143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 12:33:16.114828 <30>[ 21.588615] systemd[1]: Mounting FUSE Control File System...
10889 12:33:16.124279 <3>[ 21.593919] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 12:33:16.131257 Mounting [0;1;39mFUSE Control File System[0m...
10891 12:33:16.146270 <30>[ 21.620126] systemd[1]: Mounting Kernel Configuration File System...
10892 12:33:16.156127 <3>[ 21.625284] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:33:16.163191 Mounting [0;1;39mKernel Configuration File System[0m...
10894 12:33:16.186986 <30>[ 21.657954] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10895 12:33:16.197268 <30>[ 21.666975] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10896 12:33:16.205320 <30>[ 21.679741] systemd[1]: Starting Load/Save Random Seed...
10897 12:33:16.211810 Starting [0;1;39mLoad/Save Random Seed[0m...
10898 12:33:16.267022 <30>[ 21.741726] systemd[1]: Starting Apply Kernel Variables...
10899 12:33:16.274013 Starting [0;1;39mApply Kernel Variables[0m...
10900 12:33:16.290215 <30>[ 21.764368] systemd[1]: Starting Create System Users...
10901 12:33:16.296707 Starting [0;1;39mCreate System Users[0m...
10902 12:33:16.316134 <4>[ 21.780541] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10903 12:33:16.326166 <3>[ 21.796357] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10904 12:33:16.329050 <30>[ 21.798225] systemd[1]: Started Journal Service.
10905 12:33:16.335709 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10906 12:33:16.357742 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10907 12:33:16.370958 See 'systemctl status systemd-udev-trigger.service' for details.
10908 12:33:16.387398 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10909 12:33:16.403173 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10910 12:33:16.419705 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10911 12:33:16.435577 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10912 12:33:16.451371 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10913 12:33:16.491626 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10914 12:33:16.513512 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10915 12:33:16.550358 <46>[ 22.021658] systemd-journald[293]: Received client request to flush runtime journal.
10916 12:33:17.316213 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10917 12:33:17.331200 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10918 12:33:17.350719 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10919 12:33:17.398780 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10920 12:33:17.943277 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10921 12:33:17.975279 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10922 12:33:18.043789 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10923 12:33:18.112609 Starting [0;1;39mNetwork Service[0m...
10924 12:33:18.436885 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10925 12:33:18.460798 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10926 12:33:18.518420 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10927 12:33:18.534434 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10928 12:33:18.645337 <6>[ 24.120237] remoteproc remoteproc0: powering up scp
10929 12:33:18.684386 <4>[ 24.155833] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10930 12:33:18.691286 <3>[ 24.165779] remoteproc remoteproc0: request_firmware failed: -2
10931 12:33:18.701091 <3>[ 24.171966] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10932 12:33:18.835822 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10933 12:33:18.855284 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10934 12:33:18.887834 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10935 12:33:18.906197 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10936 12:33:18.963212 Starting [0;1;39mNetwork Name Resolution[0m...
10937 12:33:18.987029 Starting [0;1;39mNetwork Time Synchronization[0m...
10938 12:33:19.005342 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10939 12:33:19.030710 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10940 12:33:19.072601 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10941 12:33:19.099879 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10942 12:33:19.277482 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10943 12:33:19.295478 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10944 12:33:19.318043 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10945 12:33:19.330036 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10946 12:33:19.346310 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10947 12:33:19.457994 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10948 12:33:19.491456 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10949 12:33:19.520734 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10950 12:33:19.552196 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10951 12:33:19.566061 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10952 12:33:19.590581 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10953 12:33:19.602727 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10954 12:33:19.618673 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10955 12:33:19.651102 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10956 12:33:19.683132 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10957 12:33:19.750801 Starting [0;1;39mUser Login Management[0m...
10958 12:33:19.771064 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10959 12:33:19.787695 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10960 12:33:19.805792 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10961 12:33:19.846812 Starting [0;1;39mPermit User Sessions[0m...
10962 12:33:19.963600 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10963 12:33:20.015508 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10964 12:33:20.033495 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 12:33:20.051319 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 12:33:20.075833 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10967 12:33:20.084438 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10968 12:33:20.108138 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10969 12:33:20.126462 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10970 12:33:20.178724 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 12:33:20.220976 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10972 12:33:20.280298
10973 12:33:20.280463
10974 12:33:20.283747 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10975 12:33:20.283845
10976 12:33:20.286962 debian-bullseye-arm64 login: root (automatic login)
10977 12:33:20.287073
10978 12:33:20.287138
10979 12:33:20.609202 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
10980 12:33:20.609348
10981 12:33:20.615166 The programs included with the Debian GNU/Linux system are free software;
10982 12:33:20.621960 the exact distribution terms for each program are described in the
10983 12:33:20.625423 individual files in /usr/share/doc/*/copyright.
10984 12:33:20.625506
10985 12:33:20.632159 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10986 12:33:20.634938 permitted by applicable law.
10987 12:33:21.508945 Matched prompt #10: / #
10989 12:33:21.509248 Setting prompt string to ['/ #']
10990 12:33:21.509345 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10992 12:33:21.509546 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10993 12:33:21.509640 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
10994 12:33:21.509713 Setting prompt string to ['/ #']
10995 12:33:21.509778 Forcing a shell prompt, looking for ['/ #']
10997 12:33:21.559978 / #
10998 12:33:21.560165 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10999 12:33:21.560244 Waiting using forced prompt support (timeout 00:02:30)
11000 12:33:21.565586
11001 12:33:21.565856 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11002 12:33:21.565951 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11004 12:33:21.666323 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps'
11005 12:33:21.671045 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605801/extract-nfsrootfs-o9dta4ps'
11007 12:33:21.771584 / # export NFS_SERVER_IP='192.168.201.1'
11008 12:33:21.776350 export NFS_SERVER_IP='192.168.201.1'
11009 12:33:21.776633 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 12:33:21.776733 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11011 12:33:21.776830 end: 2 depthcharge-action (duration 00:01:44) [common]
11012 12:33:21.776927 start: 3 lava-test-retry (timeout 00:07:37) [common]
11013 12:33:21.777016 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
11014 12:33:21.777092 Using namespace: common
11016 12:33:21.877432 / # #
11017 12:33:21.877583 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11018 12:33:21.882196 #
11019 12:33:21.882463 Using /lava-10605801
11021 12:33:21.982801 / # export SHELL=/bin/bash
11022 12:33:21.987676 export SHELL=/bin/bash
11024 12:33:22.088202 / # . /lava-10605801/environment
11025 12:33:22.092811 . /lava-10605801/environment
11027 12:33:22.198999 / # /lava-10605801/bin/lava-test-runner /lava-10605801/0
11028 12:33:22.199141 Test shell timeout: 10s (minimum of the action and connection timeout)
11029 12:33:22.204118 /lava-10605801/bin/lava-test-runner /lava-10605801/0
11030 12:33:22.503804 + export TESTRUN_ID=0_timesync-off
11031 12:33:22.507230 + TESTRUN_ID=0_timesync-off
11032 12:33:22.509888 + cd /lava-10605801/0/tests/0_timesync-off
11033 12:33:22.513256 ++ cat uuid
11034 12:33:22.518307 + UUID=10605801_1.6.2.3.1
11035 12:33:22.518390 + set +x
11036 12:33:22.524653 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605801_1.6.2.3.1>
11037 12:33:22.524911 Received signal: <STARTRUN> 0_timesync-off 10605801_1.6.2.3.1
11038 12:33:22.524987 Starting test lava.0_timesync-off (10605801_1.6.2.3.1)
11039 12:33:22.525075 Skipping test definition patterns.
11040 12:33:22.527954 + systemctl stop systemd-timesyncd
11041 12:33:22.567346 + set +x
11042 12:33:22.570762 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605801_1.6.2.3.1>
11043 12:33:22.571015 Received signal: <ENDRUN> 0_timesync-off 10605801_1.6.2.3.1
11044 12:33:22.571103 Ending use of test pattern.
11045 12:33:22.571168 Ending test lava.0_timesync-off (10605801_1.6.2.3.1), duration 0.05
11047 12:33:22.650243 + export TESTRUN_ID=1_kselftest-rtc
11048 12:33:22.653134 + TESTRUN_ID=1_kselftest-rtc
11049 12:33:22.656448 + cd /lava-10605801/0/tests/1_kselftest-rtc
11050 12:33:22.659801 ++ cat uuid
11051 12:33:22.665708 + UUID=10605801_1.6.2.3.5
11052 12:33:22.665791 + set +x
11053 12:33:22.672172 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10605801_1.6.2.3.5>
11054 12:33:22.672428 Received signal: <STARTRUN> 1_kselftest-rtc 10605801_1.6.2.3.5
11055 12:33:22.672501 Starting test lava.1_kselftest-rtc (10605801_1.6.2.3.5)
11056 12:33:22.672582 Skipping test definition patterns.
11057 12:33:22.675648 + cd ./automated/linux/kselftest/
11058 12:33:22.702262 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11059 12:33:22.749986 INFO: install_deps skipped
11060 12:33:22.869740 --2023-06-06 12:33:23-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11061 12:33:22.889588 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11062 12:33:23.033456 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11063 12:33:23.176076 HTTP request sent, awaiting response... 200 OK
11064 12:33:23.179418 Length: 2699740 (2.6M) [application/octet-stream]
11065 12:33:23.182794 Saving to: 'kselftest.tar.xz'
11066 12:33:23.182893
11067 12:33:23.182989
11068 12:33:23.462121 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11069 12:33:23.747416 kselftest.tar.xz 1%[ ] 47.81K 168KB/s
11070 12:33:24.091894 kselftest.tar.xz 8%[> ] 217.50K 382KB/s
11071 12:33:24.451237 kselftest.tar.xz 29%[====> ] 774.64K 847KB/s
11072 12:33:24.481515 kselftest.tar.xz 53%[=========> ] 1.38M 1.08MB/s
11073 12:33:24.487921 kselftest.tar.xz 100%[===================>] 2.57M 1.97MB/s in 1.3s
11074 12:33:24.488011
11075 12:33:24.721351 2023-06-06 12:33:25 (1.97 MB/s) - 'kselftest.tar.xz' saved [2699740/2699740]
11076 12:33:24.721509
11077 12:33:30.336508 skiplist:
11078 12:33:30.339804 ========================================
11079 12:33:30.343263 ========================================
11080 12:33:30.389157 rtc:rtctest
11081 12:33:30.408055 ============== Tests to run ===============
11082 12:33:30.408207 rtc:rtctest
11083 12:33:30.411695 ===========End Tests to run ===============
11084 12:33:30.503198 <12>[ 35.979173] kselftest: Running tests in rtc
11085 12:33:30.512148 TAP version 13
11086 12:33:30.524481 1..1
11087 12:33:30.553028 # selftests: rtc: rtctest
11088 12:33:30.930467 # TAP version 13
11089 12:33:30.930634 # 1..8
11090 12:33:30.933318 # # Starting 8 tests from 2 test cases.
11091 12:33:30.936818 # # RUN rtc.date_read ...
11092 12:33:30.943131 # # rtctest.c:49:date_read:Current RTC date/time is 06/06/2023 12:33:30.
11093 12:33:30.946649 # # OK rtc.date_read
11094 12:33:30.950053 # ok 1 rtc.date_read
11095 12:33:30.952999 # # RUN rtc.date_read_loop ...
11096 12:33:30.962913 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11097 12:33:40.680811 <6>[ 46.161114] vpu: disabling
11098 12:33:40.683644 <6>[ 46.164163] vproc2: disabling
11099 12:33:40.687130 <6>[ 46.167434] vproc1: disabling
11100 12:33:40.690160 <6>[ 46.170697] vaud18: disabling
11101 12:33:40.697045 <6>[ 46.174103] vsram_others: disabling
11102 12:33:40.700321 <6>[ 46.177973] va09: disabling
11103 12:33:40.703969 <6>[ 46.181075] vsram_md: disabling
11104 12:33:40.706581 <6>[ 46.184561] Vgpu: disabling
11105 12:34:00.877423 # # rtctest.c:115:date_read_loop:Performed 2692 RTC time reads.
11106 12:34:00.880405 # # OK rtc.date_read_loop
11107 12:34:00.883423 # ok 2 rtc.date_read_loop
11108 12:34:00.887208 # # RUN rtc.uie_read ...
11109 12:34:03.862853 # # OK rtc.uie_read
11110 12:34:03.866389 # ok 3 rtc.uie_read
11111 12:34:03.869559 # # RUN rtc.uie_select ...
11112 12:34:06.862379 # # OK rtc.uie_select
11113 12:34:06.865807 # ok 4 rtc.uie_select
11114 12:34:06.869050 # # RUN rtc.alarm_alm_set ...
11115 12:34:06.875917 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 12:34:10.
11116 12:34:06.878828 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11117 12:34:06.885867 # # alarm_alm_set: Test terminated by assertion
11118 12:34:06.888875 # # FAIL rtc.alarm_alm_set
11119 12:34:06.892127 # not ok 5 rtc.alarm_alm_set
11120 12:34:06.895716 # # RUN rtc.alarm_wkalm_set ...
11121 12:34:06.901974 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 06/06/2023 12:34:10.
11122 12:34:09.865185 # # OK rtc.alarm_wkalm_set
11123 12:34:09.865337 # ok 6 rtc.alarm_wkalm_set
11124 12:34:09.871323 # # RUN rtc.alarm_alm_set_minute ...
11125 12:34:09.875073 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 12:35:00.
11126 12:34:09.881372 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11127 12:34:09.887939 # # alarm_alm_set_minute: Test terminated by assertion
11128 12:34:09.891053 # # FAIL rtc.alarm_alm_set_minute
11129 12:34:09.894940 # not ok 7 rtc.alarm_alm_set_minute
11130 12:34:09.897845 # # RUN rtc.alarm_wkalm_set_minute ...
11131 12:34:09.904718 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 06/06/2023 12:35:00.
11132 12:34:59.859163 # # OK rtc.alarm_wkalm_set_minute
11133 12:34:59.862903 # ok 8 rtc.alarm_wkalm_set_minute
11134 12:34:59.865881 # # FAILED: 6 / 8 tests passed.
11135 12:34:59.869597 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11136 12:34:59.872394 not ok 1 selftests: rtc: rtctest # exit=1
11137 12:35:00.388495 rtc_rtctest_rtc_date_read pass
11138 12:35:00.392053 rtc_rtctest_rtc_date_read_loop pass
11139 12:35:00.395240 rtc_rtctest_rtc_uie_read pass
11140 12:35:00.398820 rtc_rtctest_rtc_uie_select pass
11141 12:35:00.401974 rtc_rtctest_rtc_alarm_alm_set fail
11142 12:35:00.405009 rtc_rtctest_rtc_alarm_wkalm_set pass
11143 12:35:00.408740 rtc_rtctest_rtc_alarm_alm_set_minute fail
11144 12:35:00.411772 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11145 12:35:00.414795 rtc_rtctest fail
11146 12:35:00.418096 + ../../utils/send-to-lava.sh ./output/result.txt
11147 12:35:00.484296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11148 12:35:00.484629 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11150 12:35:00.538003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11151 12:35:00.538312 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11153 12:35:00.584118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11154 12:35:00.584424 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11156 12:35:00.637487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11157 12:35:00.637823 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11159 12:35:00.693386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11160 12:35:00.693694 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11162 12:35:00.745145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11163 12:35:00.745485 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11165 12:35:00.798255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11166 12:35:00.798551 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11168 12:35:00.845419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11169 12:35:00.845710 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11171 12:35:00.894987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11172 12:35:00.895111 + set +x
11173 12:35:00.895394 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11175 12:35:00.902038 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10605801_1.6.2.3.5>
11176 12:35:00.902298 Received signal: <ENDRUN> 1_kselftest-rtc 10605801_1.6.2.3.5
11177 12:35:00.902375 Ending use of test pattern.
11178 12:35:00.902438 Ending test lava.1_kselftest-rtc (10605801_1.6.2.3.5), duration 98.23
11180 12:35:00.902679 ok: lava_test_shell seems to have completed
11181 12:35:00.902808 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11182 12:35:00.902912 end: 3.1 lava-test-shell (duration 00:01:39) [common]
11183 12:35:00.902999 end: 3 lava-test-retry (duration 00:01:39) [common]
11184 12:35:00.903095 start: 4 finalize (timeout 00:05:58) [common]
11185 12:35:00.903186 start: 4.1 power-off (timeout 00:00:30) [common]
11186 12:35:00.903359 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11187 12:35:00.978910 >> Command sent successfully.
11188 12:35:00.981418 Returned 0 in 0 seconds
11189 12:35:01.081825 end: 4.1 power-off (duration 00:00:00) [common]
11191 12:35:01.082210 start: 4.2 read-feedback (timeout 00:05:58) [common]
11193 12:35:01.082768 Listened to connection for namespace 'common' for up to 1s
11194 12:35:02.083412 Finalising connection for namespace 'common'
11195 12:35:02.083587 Disconnecting from shell: Finalise
11196 12:35:02.083665 / #
11197 12:35:02.184002 end: 4.2 read-feedback (duration 00:00:01) [common]
11198 12:35:02.184219 end: 4 finalize (duration 00:00:01) [common]
11199 12:35:02.184338 Cleaning after the job
11200 12:35:02.184435 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/ramdisk
11201 12:35:02.186589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/kernel
11202 12:35:02.195476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/dtb
11203 12:35:02.195647 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/nfsrootfs
11204 12:35:02.262022 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605801/tftp-deploy-l8ntmx1e/modules
11205 12:35:02.267849 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605801
11206 12:35:02.808013 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605801
11207 12:35:02.808209 Job finished correctly