Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 44
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 31
1 12:31:59.506615 lava-dispatcher, installed at version: 2023.05.1
2 12:31:59.506876 start: 0 validate
3 12:31:59.507049 Start time: 2023-06-06 12:31:59.507041+00:00 (UTC)
4 12:31:59.507230 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:31:59.507421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:31:59.807027 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:31:59.807273 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:32:00.100585 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:32:00.100816 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:32:00.386715 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:32:00.386999 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:32:00.679281 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:32:00.679515 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:32:00.974618 validate duration: 1.47
16 12:32:00.974971 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:32:00.975100 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:32:00.975224 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:32:00.975417 Not decompressing ramdisk as can be used compressed.
20 12:32:00.975535 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:32:00.975630 saving as /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/ramdisk/initrd.cpio.gz
22 12:32:00.975723 total size: 4665601 (4MB)
23 12:32:00.977252 progress 0% (0MB)
24 12:32:00.978772 progress 5% (0MB)
25 12:32:00.980119 progress 10% (0MB)
26 12:32:00.981354 progress 15% (0MB)
27 12:32:00.982681 progress 20% (0MB)
28 12:32:00.983959 progress 25% (1MB)
29 12:32:00.985224 progress 30% (1MB)
30 12:32:00.986552 progress 35% (1MB)
31 12:32:00.987895 progress 40% (1MB)
32 12:32:00.989271 progress 45% (2MB)
33 12:32:00.990471 progress 50% (2MB)
34 12:32:00.991734 progress 55% (2MB)
35 12:32:00.992936 progress 60% (2MB)
36 12:32:00.994145 progress 65% (2MB)
37 12:32:00.995439 progress 70% (3MB)
38 12:32:00.996691 progress 75% (3MB)
39 12:32:00.997922 progress 80% (3MB)
40 12:32:00.999440 progress 85% (3MB)
41 12:32:01.000751 progress 90% (4MB)
42 12:32:01.002107 progress 95% (4MB)
43 12:32:01.003430 progress 100% (4MB)
44 12:32:01.003604 4MB downloaded in 0.03s (159.61MB/s)
45 12:32:01.003752 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:32:01.003994 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:32:01.004082 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:32:01.004171 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:32:01.004295 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:32:01.004369 saving as /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/kernel/Image
52 12:32:01.004433 total size: 45746688 (43MB)
53 12:32:01.004493 No compression specified
54 12:32:01.005567 progress 0% (0MB)
55 12:32:01.017367 progress 5% (2MB)
56 12:32:01.029365 progress 10% (4MB)
57 12:32:01.041645 progress 15% (6MB)
58 12:32:01.054308 progress 20% (8MB)
59 12:32:01.067490 progress 25% (10MB)
60 12:32:01.079875 progress 30% (13MB)
61 12:32:01.092296 progress 35% (15MB)
62 12:32:01.105135 progress 40% (17MB)
63 12:32:01.117950 progress 45% (19MB)
64 12:32:01.131381 progress 50% (21MB)
65 12:32:01.143726 progress 55% (24MB)
66 12:32:01.156562 progress 60% (26MB)
67 12:32:01.170372 progress 65% (28MB)
68 12:32:01.182580 progress 70% (30MB)
69 12:32:01.195062 progress 75% (32MB)
70 12:32:01.207436 progress 80% (34MB)
71 12:32:01.219901 progress 85% (37MB)
72 12:32:01.232530 progress 90% (39MB)
73 12:32:01.245104 progress 95% (41MB)
74 12:32:01.257443 progress 100% (43MB)
75 12:32:01.257648 43MB downloaded in 0.25s (172.30MB/s)
76 12:32:01.257858 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:32:01.258249 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:32:01.258372 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:32:01.258492 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:32:01.258660 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:32:01.258762 saving as /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/dtb/mt8192-asurada-spherion-r0.dtb
83 12:32:01.258863 total size: 46924 (0MB)
84 12:32:01.258958 No compression specified
85 12:32:01.260633 progress 69% (0MB)
86 12:32:01.260944 progress 100% (0MB)
87 12:32:01.261128 0MB downloaded in 0.00s (19.78MB/s)
88 12:32:01.261298 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:32:01.261660 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:32:01.261777 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:32:01.261892 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:32:01.262038 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:32:01.262136 saving as /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/nfsrootfs/full.rootfs.tar
95 12:32:01.262229 total size: 200770336 (191MB)
96 12:32:01.262320 Using unxz to decompress xz
97 12:32:01.266438 progress 0% (0MB)
98 12:32:01.814480 progress 5% (9MB)
99 12:32:02.355641 progress 10% (19MB)
100 12:32:02.978911 progress 15% (28MB)
101 12:32:03.371945 progress 20% (38MB)
102 12:32:03.708021 progress 25% (47MB)
103 12:32:04.341810 progress 30% (57MB)
104 12:32:04.927520 progress 35% (67MB)
105 12:32:05.552243 progress 40% (76MB)
106 12:32:06.154219 progress 45% (86MB)
107 12:32:06.778341 progress 50% (95MB)
108 12:32:07.465685 progress 55% (105MB)
109 12:32:08.190673 progress 60% (114MB)
110 12:32:08.323402 progress 65% (124MB)
111 12:32:08.479529 progress 70% (134MB)
112 12:32:08.593854 progress 75% (143MB)
113 12:32:08.682907 progress 80% (153MB)
114 12:32:08.757468 progress 85% (162MB)
115 12:32:08.858354 progress 90% (172MB)
116 12:32:09.141773 progress 95% (181MB)
117 12:32:09.736403 progress 100% (191MB)
118 12:32:09.741426 191MB downloaded in 8.48s (22.58MB/s)
119 12:32:09.741789 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:32:09.742234 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:32:09.742366 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:32:09.742471 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:32:09.742624 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:32:09.742702 saving as /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/modules/modules.tar
126 12:32:09.742784 total size: 8539116 (8MB)
127 12:32:09.742888 Using unxz to decompress xz
128 12:32:09.747313 progress 0% (0MB)
129 12:32:09.769650 progress 5% (0MB)
130 12:32:09.797345 progress 10% (0MB)
131 12:32:09.823233 progress 15% (1MB)
132 12:32:09.853777 progress 20% (1MB)
133 12:32:09.881339 progress 25% (2MB)
134 12:32:09.908877 progress 30% (2MB)
135 12:32:09.936692 progress 35% (2MB)
136 12:32:09.962773 progress 40% (3MB)
137 12:32:09.994405 progress 45% (3MB)
138 12:32:10.021006 progress 50% (4MB)
139 12:32:10.046650 progress 55% (4MB)
140 12:32:10.073840 progress 60% (4MB)
141 12:32:10.102006 progress 65% (5MB)
142 12:32:10.129417 progress 70% (5MB)
143 12:32:10.158407 progress 75% (6MB)
144 12:32:10.192972 progress 80% (6MB)
145 12:32:10.218313 progress 85% (6MB)
146 12:32:10.245447 progress 90% (7MB)
147 12:32:10.272437 progress 95% (7MB)
148 12:32:10.302977 progress 100% (8MB)
149 12:32:10.308538 8MB downloaded in 0.57s (14.39MB/s)
150 12:32:10.308892 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:32:10.309328 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:32:10.309462 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:32:10.309612 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:32:14.823018 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0
156 12:32:14.823229 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
157 12:32:14.823365 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 12:32:14.823533 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi
159 12:32:14.823664 makedir: /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin
160 12:32:14.823767 makedir: /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/tests
161 12:32:14.823865 makedir: /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/results
162 12:32:14.823964 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-add-keys
163 12:32:14.824109 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-add-sources
164 12:32:14.824234 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-background-process-start
165 12:32:14.824357 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-background-process-stop
166 12:32:14.824477 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-common-functions
167 12:32:14.824595 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-echo-ipv4
168 12:32:14.824715 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-install-packages
169 12:32:14.824832 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-installed-packages
170 12:32:14.824950 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-os-build
171 12:32:14.825070 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-probe-channel
172 12:32:14.825192 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-probe-ip
173 12:32:14.825309 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-target-ip
174 12:32:14.825427 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-target-mac
175 12:32:14.825549 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-target-storage
176 12:32:14.825668 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-case
177 12:32:14.825824 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-event
178 12:32:14.825946 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-feedback
179 12:32:14.826084 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-raise
180 12:32:14.826221 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-reference
181 12:32:14.826340 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-runner
182 12:32:14.826532 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-set
183 12:32:14.826652 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-test-shell
184 12:32:14.826774 Updating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-add-keys (debian)
185 12:32:14.826923 Updating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-add-sources (debian)
186 12:32:14.827101 Updating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-install-packages (debian)
187 12:32:14.827239 Updating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-installed-packages (debian)
188 12:32:14.827414 Updating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/bin/lava-os-build (debian)
189 12:32:14.827536 Creating /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/environment
190 12:32:14.827632 LAVA metadata
191 12:32:14.827702 - LAVA_JOB_ID=10605812
192 12:32:14.827812 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:32:14.827964 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 12:32:14.828030 skipped lava-vland-overlay
195 12:32:14.828104 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:32:14.828182 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 12:32:14.828244 skipped lava-multinode-overlay
198 12:32:14.828362 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:32:14.828444 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 12:32:14.828517 Loading test definitions
201 12:32:14.828608 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 12:32:14.828680 Using /lava-10605812 at stage 0
203 12:32:14.828980 uuid=10605812_1.6.2.3.1 testdef=None
204 12:32:14.829115 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:32:14.829243 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 12:32:14.829715 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:32:14.829940 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 12:32:14.830669 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:32:14.830933 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 12:32:14.831519 runner path: /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/0/tests/0_timesync-off test_uuid 10605812_1.6.2.3.1
213 12:32:14.831725 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:32:14.831981 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 12:32:14.832052 Using /lava-10605812 at stage 0
217 12:32:14.832173 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:32:14.832277 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/0/tests/1_kselftest-tpm2'
219 12:32:20.220966 Running '/usr/bin/git checkout kernelci.org
220 12:32:20.358434 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 12:32:20.359296 uuid=10605812_1.6.2.3.5 testdef=None
222 12:32:20.359475 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 12:32:20.359751 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 12:32:20.360527 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:32:20.360775 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 12:32:20.362433 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:32:20.362726 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 12:32:20.364122 runner path: /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/0/tests/1_kselftest-tpm2 test_uuid 10605812_1.6.2.3.5
232 12:32:20.364249 BOARD='mt8192-asurada-spherion-r0'
233 12:32:20.364347 BRANCH='cip'
234 12:32:20.364449 SKIPFILE='/dev/null'
235 12:32:20.364548 SKIP_INSTALL='True'
236 12:32:20.364638 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:32:20.364737 TST_CASENAME=''
238 12:32:20.364830 TST_CMDFILES='tpm2'
239 12:32:20.365018 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:32:20.365385 Creating lava-test-runner.conf files
242 12:32:20.365488 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605812/lava-overlay-y1xitwfi/lava-10605812/0 for stage 0
243 12:32:20.365615 - 0_timesync-off
244 12:32:20.365716 - 1_kselftest-tpm2
245 12:32:20.365849 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 12:32:20.365978 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 12:32:27.976116 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:32:27.976308 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 12:32:27.976437 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:32:27.976570 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 12:32:27.976701 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 12:32:28.096975 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:32:28.097337 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 12:32:28.097456 extracting modules file /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0
255 12:32:28.373920 extracting modules file /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605812/extract-overlay-ramdisk-nclahkaw/ramdisk
256 12:32:28.589070 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:32:28.589243 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 12:32:28.589342 [common] Applying overlay to NFS
259 12:32:28.589418 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605812/compress-overlay-uq5p71sg/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0
260 12:32:29.566996 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:32:29.567168 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 12:32:29.567272 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:32:29.567384 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 12:32:29.567480 Building ramdisk /var/lib/lava/dispatcher/tmp/10605812/extract-overlay-ramdisk-nclahkaw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605812/extract-overlay-ramdisk-nclahkaw/ramdisk
265 12:32:29.843104 >> 117807 blocks
266 12:32:31.783923 rename /var/lib/lava/dispatcher/tmp/10605812/extract-overlay-ramdisk-nclahkaw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/ramdisk/ramdisk.cpio.gz
267 12:32:31.784394 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:32:31.784540 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 12:32:31.784641 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 12:32:31.784787 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/kernel/Image'
271 12:32:44.709307 Returned 0 in 12 seconds
272 12:32:44.809983 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/kernel/image.itb
273 12:32:45.132587 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:32:45.133038 output: Created: Tue Jun 6 13:32:45 2023
275 12:32:45.133135 output: Image 0 (kernel-1)
276 12:32:45.133209 output: Description:
277 12:32:45.133275 output: Created: Tue Jun 6 13:32:45 2023
278 12:32:45.133342 output: Type: Kernel Image
279 12:32:45.133402 output: Compression: lzma compressed
280 12:32:45.133462 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
281 12:32:45.133525 output: Architecture: AArch64
282 12:32:45.133592 output: OS: Linux
283 12:32:45.133654 output: Load Address: 0x00000000
284 12:32:45.133717 output: Entry Point: 0x00000000
285 12:32:45.133780 output: Hash algo: crc32
286 12:32:45.133835 output: Hash value: a26c3f91
287 12:32:45.133890 output: Image 1 (fdt-1)
288 12:32:45.133948 output: Description: mt8192-asurada-spherion-r0
289 12:32:45.134005 output: Created: Tue Jun 6 13:32:45 2023
290 12:32:45.134063 output: Type: Flat Device Tree
291 12:32:45.134122 output: Compression: uncompressed
292 12:32:45.134178 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:32:45.134236 output: Architecture: AArch64
294 12:32:45.134291 output: Hash algo: crc32
295 12:32:45.134349 output: Hash value: 1df858fa
296 12:32:45.134405 output: Image 2 (ramdisk-1)
297 12:32:45.134462 output: Description: unavailable
298 12:32:45.134518 output: Created: Tue Jun 6 13:32:45 2023
299 12:32:45.134574 output: Type: RAMDisk Image
300 12:32:45.134641 output: Compression: Unknown Compression
301 12:32:45.134697 output: Data Size: 17642329 Bytes = 17228.84 KiB = 16.83 MiB
302 12:32:45.134754 output: Architecture: AArch64
303 12:32:45.134810 output: OS: Linux
304 12:32:45.134867 output: Load Address: unavailable
305 12:32:45.134923 output: Entry Point: unavailable
306 12:32:45.134981 output: Hash algo: crc32
307 12:32:45.135037 output: Hash value: f227f42d
308 12:32:45.135096 output: Default Configuration: 'conf-1'
309 12:32:45.135153 output: Configuration 0 (conf-1)
310 12:32:45.135207 output: Description: mt8192-asurada-spherion-r0
311 12:32:45.135261 output: Kernel: kernel-1
312 12:32:45.135317 output: Init Ramdisk: ramdisk-1
313 12:32:45.135392 output: FDT: fdt-1
314 12:32:45.135451 output: Loadables: kernel-1
315 12:32:45.135509 output:
316 12:32:45.135711 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:32:45.135832 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:32:45.135955 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 12:32:45.136067 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 12:32:45.136151 No LXC device requested
321 12:32:45.136230 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:32:45.136327 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 12:32:45.136413 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:32:45.136484 Checking files for TFTP limit of 4294967296 bytes.
325 12:32:45.136991 end: 1 tftp-deploy (duration 00:00:44) [common]
326 12:32:45.137115 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:32:45.137218 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:32:45.137341 substitutions:
329 12:32:45.137413 - {DTB}: 10605812/tftp-deploy-xnewfqnq/dtb/mt8192-asurada-spherion-r0.dtb
330 12:32:45.137482 - {INITRD}: 10605812/tftp-deploy-xnewfqnq/ramdisk/ramdisk.cpio.gz
331 12:32:45.137545 - {KERNEL}: 10605812/tftp-deploy-xnewfqnq/kernel/Image
332 12:32:45.137603 - {LAVA_MAC}: None
333 12:32:45.137664 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0
334 12:32:45.137724 - {NFS_SERVER_IP}: 192.168.201.1
335 12:32:45.137783 - {PRESEED_CONFIG}: None
336 12:32:45.137840 - {PRESEED_LOCAL}: None
337 12:32:45.137896 - {RAMDISK}: 10605812/tftp-deploy-xnewfqnq/ramdisk/ramdisk.cpio.gz
338 12:32:45.137950 - {ROOT_PART}: None
339 12:32:45.138008 - {ROOT}: None
340 12:32:45.138065 - {SERVER_IP}: 192.168.201.1
341 12:32:45.138120 - {TEE}: None
342 12:32:45.138174 Parsed boot commands:
343 12:32:45.138228 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:32:45.138399 Parsed boot commands: tftpboot 192.168.201.1 10605812/tftp-deploy-xnewfqnq/kernel/image.itb 10605812/tftp-deploy-xnewfqnq/kernel/cmdline
345 12:32:45.138495 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:32:45.138579 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:32:45.138684 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:32:45.138788 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:32:45.138866 Not connected, no need to disconnect.
350 12:32:45.138944 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:32:45.139037 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:32:45.139108 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 12:32:45.142626 Setting prompt string to ['lava-test: # ']
354 12:32:45.142989 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:32:45.143102 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:32:45.143210 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:32:45.143307 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:32:45.143523 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 12:32:50.275120 >> Command sent successfully.
360 12:32:50.277524 Returned 0 in 5 seconds
361 12:32:50.377899 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:32:50.378247 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:32:50.378378 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:32:50.378474 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:32:50.378559 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:32:50.378644 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:32:50.378928 [Enter `^Ec?' for help]
369 12:32:50.553528
370 12:32:50.553776
371 12:32:50.553913 F0: 102B 0000
372 12:32:50.554041
373 12:32:50.554171 F3: 1001 0000 [0200]
374 12:32:50.554296
375 12:32:50.557689 F3: 1001 0000
376 12:32:50.557798
377 12:32:50.557894 F7: 102D 0000
378 12:32:50.558035
379 12:32:50.558132 F1: 0000 0000
380 12:32:50.561035
381 12:32:50.561152 V0: 0000 0000 [0001]
382 12:32:50.561254
383 12:32:50.561348 00: 0007 8000
384 12:32:50.561446
385 12:32:50.564533 01: 0000 0000
386 12:32:50.564645
387 12:32:50.564743 BP: 0C00 0209 [0000]
388 12:32:50.564839
389 12:32:50.568520 G0: 1182 0000
390 12:32:50.568604
391 12:32:50.568668 EC: 0000 0021 [4000]
392 12:32:50.568727
393 12:32:50.572621 S7: 0000 0000 [0000]
394 12:32:50.572718
395 12:32:50.572788 CC: 0000 0000 [0001]
396 12:32:50.572860
397 12:32:50.575701 T0: 0000 0040 [010F]
398 12:32:50.575811
399 12:32:50.575909 Jump to BL
400 12:32:50.576008
401 12:32:50.600891
402 12:32:50.600992
403 12:32:50.601063
404 12:32:50.607960 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:32:50.612164 ARM64: Exception handlers installed.
406 12:32:50.615531 ARM64: Testing exception
407 12:32:50.619401 ARM64: Done test exception
408 12:32:50.626589 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:32:50.633271 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:32:50.643291 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:32:50.653866 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:32:50.660464 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:32:50.666424 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:32:50.677317 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:32:50.683996 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:32:50.703357 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:32:50.706516 WDT: Last reset was cold boot
418 12:32:50.709781 SPI1(PAD0) initialized at 2873684 Hz
419 12:32:50.713041 SPI5(PAD0) initialized at 992727 Hz
420 12:32:50.716381 VBOOT: Loading verstage.
421 12:32:50.723808 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:32:50.727805 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:32:50.731054 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:32:50.734362 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:32:50.740965 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:32:50.748074 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:32:50.758192 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:32:50.758275
429 12:32:50.758348
430 12:32:50.768554 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:32:50.771964 ARM64: Exception handlers installed.
432 12:32:50.775219 ARM64: Testing exception
433 12:32:50.775309 ARM64: Done test exception
434 12:32:50.782106 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:32:50.785361 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:32:50.799445 Probing TPM: . done!
437 12:32:50.799535 TPM ready after 0 ms
438 12:32:50.806553 Connected to device vid:did:rid of 1ae0:0028:00
439 12:32:50.812839 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 12:32:50.873531 Initialized TPM device CR50 revision 0
441 12:32:50.885813 tlcl_send_startup: Startup return code is 0
442 12:32:50.886480 TPM: setup succeeded
443 12:32:50.896988 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:32:50.905797 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:32:50.918388 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:32:50.928210 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:32:50.931961 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:32:50.935358 in-header: 03 07 00 00 08 00 00 00
449 12:32:50.939384 in-data: aa e4 47 04 13 02 00 00
450 12:32:50.939906 Chrome EC: UHEPI supported
451 12:32:50.946073 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:32:50.950565 in-header: 03 95 00 00 08 00 00 00
453 12:32:50.954655 in-data: 18 20 20 08 00 00 00 00
454 12:32:50.955192 Phase 1
455 12:32:50.957962 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:32:50.966046 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:32:50.973297 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:32:50.973951 Recovery requested (1009000e)
459 12:32:50.985461 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:32:50.989532 tlcl_extend: response is 0
461 12:32:51.000702 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:32:51.003932 tlcl_extend: response is 0
463 12:32:51.010882 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:32:51.030736 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:32:51.037370 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:32:51.037966
467 12:32:51.038361
468 12:32:51.047798 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:32:51.051076 ARM64: Exception handlers installed.
470 12:32:51.054335 ARM64: Testing exception
471 12:32:51.054767 ARM64: Done test exception
472 12:32:51.076106 pmic_efuse_setting: Set efuses in 11 msecs
473 12:32:51.080266 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:32:51.086181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:32:51.090364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:32:51.096884 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:32:51.100578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:32:51.104584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:32:51.107848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:32:51.115676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:32:51.119458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:32:51.122725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:32:51.129969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:32:51.133996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:32:51.137335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:32:51.141078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:32:51.148536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:32:51.155523 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:32:51.159535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:32:51.166613 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:32:51.170341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:32:51.177852 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:32:51.181690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:32:51.189216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:32:51.192542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:32:51.200098 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:32:51.203587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:32:51.211032 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:32:51.214547 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:32:51.222217 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:32:51.226151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:32:51.229383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:32:51.236838 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:32:51.240736 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:32:51.244089 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:32:51.251692 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:32:51.255471 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:32:51.259413 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:32:51.265979 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:32:51.269954 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:32:51.273788 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:32:51.280959 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:32:51.285051 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:32:51.288410 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:32:51.292242 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:32:51.296276 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:32:51.299800 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:32:51.307197 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:32:51.311214 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:32:51.314612 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:32:51.318154 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:32:51.322090 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:32:51.325838 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:32:51.329640 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:32:51.337552 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:32:51.348573 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:32:51.351880 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:32:51.359265 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:32:51.370616 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:32:51.373717 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:32:51.377503 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:32:51.380554 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:32:51.388977 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 12:32:51.392845 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:32:51.401193 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:32:51.404779 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:32:51.413309 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 12:32:51.423743 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 12:32:51.432239 [RTC]rtc_get_frequency_meter,154: input=19, output=849
540 12:32:51.441711 [RTC]rtc_get_frequency_meter,154: input=17, output=804
541 12:32:51.451819 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 12:32:51.461257 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 12:32:51.471628 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 12:32:51.474592 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 12:32:51.479356 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 12:32:51.482458 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:32:51.490827 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:32:51.493945 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:32:51.497561 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:32:51.501245 ADC[4]: Raw value=905834 ID=7
551 12:32:51.501912 ADC[3]: Raw value=213441 ID=1
552 12:32:51.505339 RAM Code: 0x71
553 12:32:51.508805 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:32:51.512842 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:32:51.520303 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:32:51.527833 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:32:51.532214 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:32:51.536012 in-header: 03 07 00 00 08 00 00 00
559 12:32:51.539174 in-data: aa e4 47 04 13 02 00 00
560 12:32:51.543112 Chrome EC: UHEPI supported
561 12:32:51.546202 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:32:51.551002 in-header: 03 95 00 00 08 00 00 00
563 12:32:51.554942 in-data: 18 20 20 08 00 00 00 00
564 12:32:51.558251 MRC: failed to locate region type 0.
565 12:32:51.566198 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:32:51.569552 DRAM-K: Running full calibration
567 12:32:51.573524 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:32:51.576895 header.status = 0x0
569 12:32:51.580768 header.version = 0x6 (expected: 0x6)
570 12:32:51.584477 header.size = 0xd00 (expected: 0xd00)
571 12:32:51.585154 header.flags = 0x0
572 12:32:51.591798 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:32:51.609057 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:32:51.617157 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:32:51.617251 dram_init: ddr_geometry: 2
576 12:32:51.621131 [EMI] MDL number = 2
577 12:32:51.621223 [EMI] Get MDL freq = 0
578 12:32:51.624412 dram_init: ddr_type: 0
579 12:32:51.628515 is_discrete_lpddr4: 1
580 12:32:51.628602 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:32:51.628672
582 12:32:51.628737
583 12:32:51.631860 [Bian_co] ETT version 0.0.0.1
584 12:32:51.636419 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:32:51.636532
586 12:32:51.640548 dramc_set_vcore_voltage set vcore to 650000
587 12:32:51.644409 Read voltage for 800, 4
588 12:32:51.644523 Vio18 = 0
589 12:32:51.644632 Vcore = 650000
590 12:32:51.647757 Vdram = 0
591 12:32:51.647867 Vddq = 0
592 12:32:51.647960 Vmddr = 0
593 12:32:51.651822 dram_init: config_dvfs: 1
594 12:32:51.655603 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:32:51.662802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:32:51.666636 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 12:32:51.669904 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 12:32:51.673368 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 12:32:51.676682 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 12:32:51.679897 MEM_TYPE=3, freq_sel=18
601 12:32:51.683319 sv_algorithm_assistance_LP4_1600
602 12:32:51.686516 ============ PULL DRAM RESETB DOWN ============
603 12:32:51.690282 ========== PULL DRAM RESETB DOWN end =========
604 12:32:51.693561 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:32:51.697493 ===================================
606 12:32:51.701289 LPDDR4 DRAM CONFIGURATION
607 12:32:51.705174 ===================================
608 12:32:51.705291 EX_ROW_EN[0] = 0x0
609 12:32:51.708427 EX_ROW_EN[1] = 0x0
610 12:32:51.708552 LP4Y_EN = 0x0
611 12:32:51.711753 WORK_FSP = 0x0
612 12:32:51.711895 WL = 0x2
613 12:32:51.715189 RL = 0x2
614 12:32:51.715299 BL = 0x2
615 12:32:51.718464 RPST = 0x0
616 12:32:51.718574 RD_PRE = 0x0
617 12:32:51.721714 WR_PRE = 0x1
618 12:32:51.721835 WR_PST = 0x0
619 12:32:51.725474 DBI_WR = 0x0
620 12:32:51.725599 DBI_RD = 0x0
621 12:32:51.728361 OTF = 0x1
622 12:32:51.732467 ===================================
623 12:32:51.735843 ===================================
624 12:32:51.735977 ANA top config
625 12:32:51.739374 ===================================
626 12:32:51.742785 DLL_ASYNC_EN = 0
627 12:32:51.746265 ALL_SLAVE_EN = 1
628 12:32:51.746387 NEW_RANK_MODE = 1
629 12:32:51.749507 DLL_IDLE_MODE = 1
630 12:32:51.752773 LP45_APHY_COMB_EN = 1
631 12:32:51.756801 TX_ODT_DIS = 1
632 12:32:51.756925 NEW_8X_MODE = 1
633 12:32:51.760143 ===================================
634 12:32:51.763832 ===================================
635 12:32:51.767015 data_rate = 1600
636 12:32:51.770808 CKR = 1
637 12:32:51.774149 DQ_P2S_RATIO = 8
638 12:32:51.777386 ===================================
639 12:32:51.777506 CA_P2S_RATIO = 8
640 12:32:51.780580 DQ_CA_OPEN = 0
641 12:32:51.783910 DQ_SEMI_OPEN = 0
642 12:32:51.787266 CA_SEMI_OPEN = 0
643 12:32:51.790502 CA_FULL_RATE = 0
644 12:32:51.793671 DQ_CKDIV4_EN = 1
645 12:32:51.793757 CA_CKDIV4_EN = 1
646 12:32:51.796859 CA_PREDIV_EN = 0
647 12:32:51.800726 PH8_DLY = 0
648 12:32:51.803945 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:32:51.807075 DQ_AAMCK_DIV = 4
650 12:32:51.810167 CA_AAMCK_DIV = 4
651 12:32:51.810266 CA_ADMCK_DIV = 4
652 12:32:51.814048 DQ_TRACK_CA_EN = 0
653 12:32:51.817184 CA_PICK = 800
654 12:32:51.821180 CA_MCKIO = 800
655 12:32:51.824620 MCKIO_SEMI = 0
656 12:32:51.824702 PLL_FREQ = 3068
657 12:32:51.828579 DQ_UI_PI_RATIO = 32
658 12:32:51.832423 CA_UI_PI_RATIO = 0
659 12:32:51.835912 ===================================
660 12:32:51.839216 ===================================
661 12:32:51.839332 memory_type:LPDDR4
662 12:32:51.843361 GP_NUM : 10
663 12:32:51.843449 SRAM_EN : 1
664 12:32:51.847497 MD32_EN : 0
665 12:32:51.851426 ===================================
666 12:32:51.851515 [ANA_INIT] >>>>>>>>>>>>>>
667 12:32:51.854790 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:32:51.858200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:32:51.861610 ===================================
670 12:32:51.864878 data_rate = 1600,PCW = 0X7600
671 12:32:51.868200 ===================================
672 12:32:51.871959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:32:51.878483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:32:51.881584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:32:51.888248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:32:51.891615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:32:51.894818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:32:51.894905 [ANA_INIT] flow start
679 12:32:51.898550 [ANA_INIT] PLL >>>>>>>>
680 12:32:51.901686 [ANA_INIT] PLL <<<<<<<<
681 12:32:51.901773 [ANA_INIT] MIDPI >>>>>>>>
682 12:32:51.905158 [ANA_INIT] MIDPI <<<<<<<<
683 12:32:51.908411 [ANA_INIT] DLL >>>>>>>>
684 12:32:51.908498 [ANA_INIT] flow end
685 12:32:51.914716 ============ LP4 DIFF to SE enter ============
686 12:32:51.918598 ============ LP4 DIFF to SE exit ============
687 12:32:51.921810 [ANA_INIT] <<<<<<<<<<<<<
688 12:32:51.924945 [Flow] Enable top DCM control >>>>>
689 12:32:51.928300 [Flow] Enable top DCM control <<<<<
690 12:32:51.928387 Enable DLL master slave shuffle
691 12:32:51.934814 ==============================================================
692 12:32:51.938063 Gating Mode config
693 12:32:51.941382 ==============================================================
694 12:32:51.944788 Config description:
695 12:32:51.954860 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:32:51.961561 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:32:51.964865 SELPH_MODE 0: By rank 1: By Phase
698 12:32:51.971755 ==============================================================
699 12:32:51.975066 GAT_TRACK_EN = 1
700 12:32:51.978292 RX_GATING_MODE = 2
701 12:32:51.978412 RX_GATING_TRACK_MODE = 2
702 12:32:51.982062 SELPH_MODE = 1
703 12:32:51.985329 PICG_EARLY_EN = 1
704 12:32:51.988570 VALID_LAT_VALUE = 1
705 12:32:51.994905 ==============================================================
706 12:32:51.998367 Enter into Gating configuration >>>>
707 12:32:52.002171 Exit from Gating configuration <<<<
708 12:32:52.005235 Enter into DVFS_PRE_config >>>>>
709 12:32:52.015624 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:32:52.018732 Exit from DVFS_PRE_config <<<<<
711 12:32:52.021882 Enter into PICG configuration >>>>
712 12:32:52.025175 Exit from PICG configuration <<<<
713 12:32:52.028333 [RX_INPUT] configuration >>>>>
714 12:32:52.031685 [RX_INPUT] configuration <<<<<
715 12:32:52.035077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:32:52.041854 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:32:52.048492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:32:52.051891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:32:52.058681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:32:52.065344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:32:52.068572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:32:52.071925 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:32:52.078767 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:32:52.082035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:32:52.085335 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:32:52.091918 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:32:52.095659 ===================================
728 12:32:52.095800 LPDDR4 DRAM CONFIGURATION
729 12:32:52.098752 ===================================
730 12:32:52.102163 EX_ROW_EN[0] = 0x0
731 12:32:52.102271 EX_ROW_EN[1] = 0x0
732 12:32:52.105526 LP4Y_EN = 0x0
733 12:32:52.105706 WORK_FSP = 0x0
734 12:32:52.108866 WL = 0x2
735 12:32:52.108980 RL = 0x2
736 12:32:52.112209 BL = 0x2
737 12:32:52.112317 RPST = 0x0
738 12:32:52.115252 RD_PRE = 0x0
739 12:32:52.118727 WR_PRE = 0x1
740 12:32:52.118840 WR_PST = 0x0
741 12:32:52.121944 DBI_WR = 0x0
742 12:32:52.122079 DBI_RD = 0x0
743 12:32:52.125600 OTF = 0x1
744 12:32:52.128767 ===================================
745 12:32:52.131922 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:32:52.135022 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:32:52.138867 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:32:52.142161 ===================================
749 12:32:52.145562 LPDDR4 DRAM CONFIGURATION
750 12:32:52.148872 ===================================
751 12:32:52.152216 EX_ROW_EN[0] = 0x10
752 12:32:52.152322 EX_ROW_EN[1] = 0x0
753 12:32:52.155620 LP4Y_EN = 0x0
754 12:32:52.155714 WORK_FSP = 0x0
755 12:32:52.158977 WL = 0x2
756 12:32:52.159087 RL = 0x2
757 12:32:52.162381 BL = 0x2
758 12:32:52.162472 RPST = 0x0
759 12:32:52.165618 RD_PRE = 0x0
760 12:32:52.165739 WR_PRE = 0x1
761 12:32:52.168884 WR_PST = 0x0
762 12:32:52.169014 DBI_WR = 0x0
763 12:32:52.172200 DBI_RD = 0x0
764 12:32:52.172306 OTF = 0x1
765 12:32:52.175581 ===================================
766 12:32:52.181711 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:32:52.186972 nWR fixed to 40
768 12:32:52.190007 [ModeRegInit_LP4] CH0 RK0
769 12:32:52.190093 [ModeRegInit_LP4] CH0 RK1
770 12:32:52.193942 [ModeRegInit_LP4] CH1 RK0
771 12:32:52.197212 [ModeRegInit_LP4] CH1 RK1
772 12:32:52.197296 match AC timing 13
773 12:32:52.203536 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:32:52.206730 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:32:52.210006 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:32:52.216628 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:32:52.219947 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:32:52.220041 [EMI DOE] emi_dcm 0
779 12:32:52.226958 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:32:52.227052 ==
781 12:32:52.230402 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:32:52.234024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:32:52.234111 ==
784 12:32:52.240301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:32:52.243996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:32:52.253932 [CA 0] Center 36 (6~67) winsize 62
787 12:32:52.257342 [CA 1] Center 36 (6~67) winsize 62
788 12:32:52.260793 [CA 2] Center 34 (4~65) winsize 62
789 12:32:52.264017 [CA 3] Center 34 (4~64) winsize 61
790 12:32:52.267407 [CA 4] Center 33 (3~63) winsize 61
791 12:32:52.270497 [CA 5] Center 32 (2~62) winsize 61
792 12:32:52.270582
793 12:32:52.273823 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:32:52.273909
795 12:32:52.277239 [CATrainingPosCal] consider 1 rank data
796 12:32:52.280576 u2DelayCellTimex100 = 270/100 ps
797 12:32:52.283981 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 12:32:52.287340 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 12:32:52.293983 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 12:32:52.297447 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 12:32:52.301205 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 12:32:52.304529 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 12:32:52.304616
804 12:32:52.307775 CA PerBit enable=1, Macro0, CA PI delay=32
805 12:32:52.307865
806 12:32:52.310906 [CBTSetCACLKResult] CA Dly = 32
807 12:32:52.310992 CS Dly: 5 (0~36)
808 12:32:52.314215 ==
809 12:32:52.314330 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:32:52.321015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:32:52.321131 ==
812 12:32:52.324508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:32:52.330890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:32:52.340628 [CA 0] Center 36 (6~67) winsize 62
815 12:32:52.343781 [CA 1] Center 36 (6~67) winsize 62
816 12:32:52.347548 [CA 2] Center 34 (4~65) winsize 62
817 12:32:52.350829 [CA 3] Center 33 (3~64) winsize 62
818 12:32:52.354014 [CA 4] Center 32 (2~63) winsize 62
819 12:32:52.357136 [CA 5] Center 32 (2~63) winsize 62
820 12:32:52.357253
821 12:32:52.360815 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 12:32:52.360923
823 12:32:52.364243 [CATrainingPosCal] consider 2 rank data
824 12:32:52.367016 u2DelayCellTimex100 = 270/100 ps
825 12:32:52.370392 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 12:32:52.373644 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 12:32:52.380379 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 12:32:52.383801 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 12:32:52.387100 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 12:32:52.390536 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 12:32:52.390609
832 12:32:52.393958 CA PerBit enable=1, Macro0, CA PI delay=32
833 12:32:52.394062
834 12:32:52.397409 [CBTSetCACLKResult] CA Dly = 32
835 12:32:52.397517 CS Dly: 5 (0~37)
836 12:32:52.397624
837 12:32:52.401266 ----->DramcWriteLeveling(PI) begin...
838 12:32:52.401384 ==
839 12:32:52.404985 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:32:52.408934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:32:52.409022 ==
842 12:32:52.412825 Write leveling (Byte 0): 34 => 34
843 12:32:52.416606 Write leveling (Byte 1): 31 => 31
844 12:32:52.419996 DramcWriteLeveling(PI) end<-----
845 12:32:52.420084
846 12:32:52.420153 ==
847 12:32:52.423188 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:32:52.426649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:32:52.426737 ==
850 12:32:52.429888 [Gating] SW mode calibration
851 12:32:52.437219 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:32:52.440486 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:32:52.447233 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:32:52.450471 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 12:32:52.453655 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 12:32:52.460403 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:32:52.464316 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:32:52.467238 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:32:52.473825 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:32:52.477254 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:32:52.480724 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:32:52.487615 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:32:52.491050 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:32:52.494658 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:32:52.501252 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:32:52.504659 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:32:52.507959 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:32:52.514579 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:32:52.517903 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:32:52.520858 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:32:52.524550 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 12:32:52.530930 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 12:32:52.534333 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:32:52.537732 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:32:52.544572 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:32:52.547705 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:32:52.550932 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:32:52.557319 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:32:52.561197 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
880 12:32:52.564313 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
881 12:32:52.570934 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:32:52.573976 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:32:52.577715 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:32:52.584370 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:32:52.587631 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:32:52.591059 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
887 12:32:52.597343 0 10 8 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
888 12:32:52.600754 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 12:32:52.604407 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:32:52.607753 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:32:52.614313 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:32:52.617567 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:32:52.621243 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:32:52.627525 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 12:32:52.631434 0 11 8 | B1->B0 | 2a2a 3f3f | 0 1 | (0 0) (0 0)
896 12:32:52.634429 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
897 12:32:52.641501 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:32:52.644618 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:32:52.647989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:32:52.654525 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:32:52.657743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:32:52.661051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 12:32:52.668078 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 12:32:52.671097 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:32:52.674949 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:32:52.681311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:32:52.684575 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:32:52.687760 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:32:52.694489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:32:52.697781 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:32:52.701132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:32:52.704510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:32:52.711182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:32:52.714714 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:32:52.717956 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:32:52.724698 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:32:52.728004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:32:52.731175 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 12:32:52.738052 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 12:32:52.741211 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 12:32:52.744373 Total UI for P1: 0, mck2ui 16
922 12:32:52.748208 best dqsien dly found for B0: ( 0, 14, 6)
923 12:32:52.751165 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 12:32:52.755250 Total UI for P1: 0, mck2ui 16
925 12:32:52.758628 best dqsien dly found for B1: ( 0, 14, 12)
926 12:32:52.761973 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 12:32:52.765300 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 12:32:52.765741
929 12:32:52.768316 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 12:32:52.772171 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 12:32:52.775245 [Gating] SW calibration Done
932 12:32:52.775780 ==
933 12:32:52.778287 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:32:52.785462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:32:52.785946 ==
936 12:32:52.786289 RX Vref Scan: 0
937 12:32:52.786611
938 12:32:52.788624 RX Vref 0 -> 0, step: 1
939 12:32:52.789053
940 12:32:52.791781 RX Delay -130 -> 252, step: 16
941 12:32:52.795473 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
942 12:32:52.798918 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 12:32:52.802352 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 12:32:52.805752 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 12:32:52.811862 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 12:32:52.815123 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 12:32:52.819025 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
948 12:32:52.821876 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
949 12:32:52.824830 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
950 12:32:52.831475 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
951 12:32:52.834929 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 12:32:52.838055 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
953 12:32:52.841802 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
954 12:32:52.844833 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
955 12:32:52.851664 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
956 12:32:52.854829 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 12:32:52.854927 ==
958 12:32:52.858704 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:32:52.862024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:32:52.862111 ==
961 12:32:52.865313 DQS Delay:
962 12:32:52.865398 DQS0 = 0, DQS1 = 0
963 12:32:52.865484 DQM Delay:
964 12:32:52.868453 DQM0 = 90, DQM1 = 84
965 12:32:52.868538 DQ Delay:
966 12:32:52.871801 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
967 12:32:52.875063 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
968 12:32:52.878227 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
969 12:32:52.881370 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
970 12:32:52.881455
971 12:32:52.881559
972 12:32:52.881639 ==
973 12:32:52.885246 Dram Type= 6, Freq= 0, CH_0, rank 0
974 12:32:52.891825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 12:32:52.891911 ==
976 12:32:52.891980
977 12:32:52.892054
978 12:32:52.892115 TX Vref Scan disable
979 12:32:52.894854 == TX Byte 0 ==
980 12:32:52.898624 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
981 12:32:52.905326 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
982 12:32:52.905411 == TX Byte 1 ==
983 12:32:52.908675 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
984 12:32:52.912064 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
985 12:32:52.915249 ==
986 12:32:52.918114 Dram Type= 6, Freq= 0, CH_0, rank 0
987 12:32:52.921473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 12:32:52.921565 ==
989 12:32:52.934811 TX Vref=22, minBit 8, minWin=27, winSum=447
990 12:32:52.938038 TX Vref=24, minBit 11, minWin=27, winSum=452
991 12:32:52.941266 TX Vref=26, minBit 9, minWin=27, winSum=453
992 12:32:52.944629 TX Vref=28, minBit 8, minWin=28, winSum=458
993 12:32:52.947858 TX Vref=30, minBit 5, minWin=28, winSum=458
994 12:32:52.951098 TX Vref=32, minBit 5, minWin=28, winSum=454
995 12:32:52.958002 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
996 12:32:52.958090
997 12:32:52.961183 Final TX Range 1 Vref 28
998 12:32:52.961268
999 12:32:52.961374 ==
1000 12:32:52.964843 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 12:32:52.968102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 12:32:52.968202 ==
1003 12:32:52.968269
1004 12:32:52.968331
1005 12:32:52.971295 TX Vref Scan disable
1006 12:32:52.974469 == TX Byte 0 ==
1007 12:32:52.977700 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1008 12:32:52.981137 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1009 12:32:52.984425 == TX Byte 1 ==
1010 12:32:52.988165 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1011 12:32:52.991386 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1012 12:32:52.991475
1013 12:32:52.994525 [DATLAT]
1014 12:32:52.994610 Freq=800, CH0 RK0
1015 12:32:52.994677
1016 12:32:52.997849 DATLAT Default: 0xa
1017 12:32:52.997934 0, 0xFFFF, sum = 0
1018 12:32:53.001540 1, 0xFFFF, sum = 0
1019 12:32:53.001656 2, 0xFFFF, sum = 0
1020 12:32:53.004611 3, 0xFFFF, sum = 0
1021 12:32:53.004747 4, 0xFFFF, sum = 0
1022 12:32:53.007966 5, 0xFFFF, sum = 0
1023 12:32:53.008083 6, 0xFFFF, sum = 0
1024 12:32:53.011486 7, 0xFFFF, sum = 0
1025 12:32:53.011579 8, 0xFFFF, sum = 0
1026 12:32:53.014707 9, 0x0, sum = 1
1027 12:32:53.014798 10, 0x0, sum = 2
1028 12:32:53.018211 11, 0x0, sum = 3
1029 12:32:53.018318 12, 0x0, sum = 4
1030 12:32:53.021579 best_step = 10
1031 12:32:53.021675
1032 12:32:53.021750 ==
1033 12:32:53.025049 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 12:32:53.028145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 12:32:53.028267 ==
1036 12:32:53.031548 RX Vref Scan: 1
1037 12:32:53.031662
1038 12:32:53.031752 Set Vref Range= 32 -> 127
1039 12:32:53.031837
1040 12:32:53.034833 RX Vref 32 -> 127, step: 1
1041 12:32:53.034958
1042 12:32:53.037968 RX Delay -79 -> 252, step: 8
1043 12:32:53.038093
1044 12:32:53.041375 Set Vref, RX VrefLevel [Byte0]: 32
1045 12:32:53.045079 [Byte1]: 32
1046 12:32:53.045512
1047 12:32:53.048321 Set Vref, RX VrefLevel [Byte0]: 33
1048 12:32:53.051731 [Byte1]: 33
1049 12:32:53.052165
1050 12:32:53.055590 Set Vref, RX VrefLevel [Byte0]: 34
1051 12:32:53.058647 [Byte1]: 34
1052 12:32:53.062465
1053 12:32:53.062896 Set Vref, RX VrefLevel [Byte0]: 35
1054 12:32:53.066276 [Byte1]: 35
1055 12:32:53.070517
1056 12:32:53.070963 Set Vref, RX VrefLevel [Byte0]: 36
1057 12:32:53.073678 [Byte1]: 36
1058 12:32:53.077776
1059 12:32:53.078205 Set Vref, RX VrefLevel [Byte0]: 37
1060 12:32:53.080991 [Byte1]: 37
1061 12:32:53.085647
1062 12:32:53.086215 Set Vref, RX VrefLevel [Byte0]: 38
1063 12:32:53.088807 [Byte1]: 38
1064 12:32:53.092700
1065 12:32:53.093125 Set Vref, RX VrefLevel [Byte0]: 39
1066 12:32:53.096302 [Byte1]: 39
1067 12:32:53.100714
1068 12:32:53.101156 Set Vref, RX VrefLevel [Byte0]: 40
1069 12:32:53.103934 [Byte1]: 40
1070 12:32:53.107734
1071 12:32:53.108187 Set Vref, RX VrefLevel [Byte0]: 41
1072 12:32:53.111592 [Byte1]: 41
1073 12:32:53.115397
1074 12:32:53.116001 Set Vref, RX VrefLevel [Byte0]: 42
1075 12:32:53.118613 [Byte1]: 42
1076 12:32:53.122813
1077 12:32:53.123514 Set Vref, RX VrefLevel [Byte0]: 43
1078 12:32:53.126280 [Byte1]: 43
1079 12:32:53.130432
1080 12:32:53.130982 Set Vref, RX VrefLevel [Byte0]: 44
1081 12:32:53.133854 [Byte1]: 44
1082 12:32:53.137690
1083 12:32:53.138220 Set Vref, RX VrefLevel [Byte0]: 45
1084 12:32:53.141715 [Byte1]: 45
1085 12:32:53.145621
1086 12:32:53.146235 Set Vref, RX VrefLevel [Byte0]: 46
1087 12:32:53.148947 [Byte1]: 46
1088 12:32:53.152958
1089 12:32:53.153537 Set Vref, RX VrefLevel [Byte0]: 47
1090 12:32:53.156377 [Byte1]: 47
1091 12:32:53.160929
1092 12:32:53.161520 Set Vref, RX VrefLevel [Byte0]: 48
1093 12:32:53.164229 [Byte1]: 48
1094 12:32:53.168012
1095 12:32:53.168609 Set Vref, RX VrefLevel [Byte0]: 49
1096 12:32:53.171822 [Byte1]: 49
1097 12:32:53.175418
1098 12:32:53.175973 Set Vref, RX VrefLevel [Byte0]: 50
1099 12:32:53.179120 [Byte1]: 50
1100 12:32:53.183163
1101 12:32:53.183745 Set Vref, RX VrefLevel [Byte0]: 51
1102 12:32:53.187013 [Byte1]: 51
1103 12:32:53.190842
1104 12:32:53.191322 Set Vref, RX VrefLevel [Byte0]: 52
1105 12:32:53.194089 [Byte1]: 52
1106 12:32:53.198529
1107 12:32:53.198958 Set Vref, RX VrefLevel [Byte0]: 53
1108 12:32:53.201624 [Byte1]: 53
1109 12:32:53.206094
1110 12:32:53.206518 Set Vref, RX VrefLevel [Byte0]: 54
1111 12:32:53.209330 [Byte1]: 54
1112 12:32:53.213749
1113 12:32:53.214308 Set Vref, RX VrefLevel [Byte0]: 55
1114 12:32:53.216875 [Byte1]: 55
1115 12:32:53.221464
1116 12:32:53.222007 Set Vref, RX VrefLevel [Byte0]: 56
1117 12:32:53.224127 [Byte1]: 56
1118 12:32:53.228751
1119 12:32:53.229150 Set Vref, RX VrefLevel [Byte0]: 57
1120 12:32:53.232221 [Byte1]: 57
1121 12:32:53.236214
1122 12:32:53.236636 Set Vref, RX VrefLevel [Byte0]: 58
1123 12:32:53.239579 [Byte1]: 58
1124 12:32:53.243486
1125 12:32:53.244108 Set Vref, RX VrefLevel [Byte0]: 59
1126 12:32:53.246696 [Byte1]: 59
1127 12:32:53.251601
1128 12:32:53.252078 Set Vref, RX VrefLevel [Byte0]: 60
1129 12:32:53.254186 [Byte1]: 60
1130 12:32:53.259074
1131 12:32:53.259811 Set Vref, RX VrefLevel [Byte0]: 61
1132 12:32:53.262387 [Byte1]: 61
1133 12:32:53.266506
1134 12:32:53.267101 Set Vref, RX VrefLevel [Byte0]: 62
1135 12:32:53.269641 [Byte1]: 62
1136 12:32:53.273702
1137 12:32:53.274123 Set Vref, RX VrefLevel [Byte0]: 63
1138 12:32:53.277509 [Byte1]: 63
1139 12:32:53.281839
1140 12:32:53.282299 Set Vref, RX VrefLevel [Byte0]: 64
1141 12:32:53.284971 [Byte1]: 64
1142 12:32:53.288835
1143 12:32:53.289256 Set Vref, RX VrefLevel [Byte0]: 65
1144 12:32:53.292028 [Byte1]: 65
1145 12:32:53.296599
1146 12:32:53.297018 Set Vref, RX VrefLevel [Byte0]: 66
1147 12:32:53.299835 [Byte1]: 66
1148 12:32:53.304242
1149 12:32:53.304658 Set Vref, RX VrefLevel [Byte0]: 67
1150 12:32:53.307561 [Byte1]: 67
1151 12:32:53.311759
1152 12:32:53.312177 Set Vref, RX VrefLevel [Byte0]: 68
1153 12:32:53.314867 [Byte1]: 68
1154 12:32:53.319383
1155 12:32:53.319930 Set Vref, RX VrefLevel [Byte0]: 69
1156 12:32:53.322561 [Byte1]: 69
1157 12:32:53.326798
1158 12:32:53.327218 Set Vref, RX VrefLevel [Byte0]: 70
1159 12:32:53.330116 [Byte1]: 70
1160 12:32:53.334036
1161 12:32:53.334475 Set Vref, RX VrefLevel [Byte0]: 71
1162 12:32:53.337396 [Byte1]: 71
1163 12:32:53.342165
1164 12:32:53.342583 Set Vref, RX VrefLevel [Byte0]: 72
1165 12:32:53.344808 [Byte1]: 72
1166 12:32:53.349415
1167 12:32:53.352611 Set Vref, RX VrefLevel [Byte0]: 73
1168 12:32:53.355953 [Byte1]: 73
1169 12:32:53.356670
1170 12:32:53.359275 Set Vref, RX VrefLevel [Byte0]: 74
1171 12:32:53.362643 [Byte1]: 74
1172 12:32:53.363087
1173 12:32:53.365911 Set Vref, RX VrefLevel [Byte0]: 75
1174 12:32:53.369071 [Byte1]: 75
1175 12:32:53.369438
1176 12:32:53.372357 Set Vref, RX VrefLevel [Byte0]: 76
1177 12:32:53.375567 [Byte1]: 76
1178 12:32:53.379486
1179 12:32:53.379675 Set Vref, RX VrefLevel [Byte0]: 77
1180 12:32:53.382696 [Byte1]: 77
1181 12:32:53.387003
1182 12:32:53.387206 Set Vref, RX VrefLevel [Byte0]: 78
1183 12:32:53.390193 [Byte1]: 78
1184 12:32:53.394109
1185 12:32:53.394259 Set Vref, RX VrefLevel [Byte0]: 79
1186 12:32:53.397567 [Byte1]: 79
1187 12:32:53.402046
1188 12:32:53.402141 Final RX Vref Byte 0 = 56 to rank0
1189 12:32:53.405354 Final RX Vref Byte 1 = 59 to rank0
1190 12:32:53.408447 Final RX Vref Byte 0 = 56 to rank1
1191 12:32:53.411767 Final RX Vref Byte 1 = 59 to rank1==
1192 12:32:53.415397 Dram Type= 6, Freq= 0, CH_0, rank 0
1193 12:32:53.418536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 12:32:53.422320 ==
1195 12:32:53.422415 DQS Delay:
1196 12:32:53.422494 DQS0 = 0, DQS1 = 0
1197 12:32:53.425665 DQM Delay:
1198 12:32:53.425760 DQM0 = 92, DQM1 = 86
1199 12:32:53.428788 DQ Delay:
1200 12:32:53.432012 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1201 12:32:53.432125 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1202 12:32:53.435095 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1203 12:32:53.441990 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1204 12:32:53.442097
1205 12:32:53.442189
1206 12:32:53.448634 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1207 12:32:53.452024 CH0 RK0: MR19=606, MR18=4D43
1208 12:32:53.458963 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1209 12:32:53.459484
1210 12:32:53.462332 ----->DramcWriteLeveling(PI) begin...
1211 12:32:53.462765 ==
1212 12:32:53.465645 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 12:32:53.469105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1214 12:32:53.469531 ==
1215 12:32:53.472408 Write leveling (Byte 0): 32 => 32
1216 12:32:53.516534 Write leveling (Byte 1): 31 => 31
1217 12:32:53.516696 DramcWriteLeveling(PI) end<-----
1218 12:32:53.516768
1219 12:32:53.516830 ==
1220 12:32:53.516889 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 12:32:53.517141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 12:32:53.517205 ==
1223 12:32:53.517264 [Gating] SW mode calibration
1224 12:32:53.517320 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1225 12:32:53.517377 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1226 12:32:53.517433 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1227 12:32:53.517668 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1228 12:32:53.517774 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1229 12:32:53.533867 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:32:53.533956 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:32:53.534023 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:32:53.534264 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:32:53.537641 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:32:53.540685 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:32:53.544183 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:32:53.550665 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:32:53.554012 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:32:53.557402 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:32:53.563910 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:32:53.567160 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:32:53.570539 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:32:53.573820 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:32:53.580576 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:32:53.583904 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1245 12:32:53.587198 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:32:53.593866 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:32:53.597557 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:32:53.600860 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:32:53.608144 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:32:53.611511 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:32:53.614899 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:32:53.621383 0 9 8 | B1->B0 | 2e2e 2d2d | 1 1 | (1 1) (0 0)
1253 12:32:53.624986 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 12:32:53.628114 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 12:32:53.634868 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 12:32:53.638208 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 12:32:53.641313 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 12:32:53.644992 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 12:32:53.652079 0 10 4 | B1->B0 | 3232 3333 | 0 0 | (0 0) (0 0)
1260 12:32:53.656715 0 10 8 | B1->B0 | 2e2e 2929 | 0 0 | (0 1) (0 1)
1261 12:32:53.659877 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:32:53.663882 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:32:53.667090 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 12:32:53.673863 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 12:32:53.677836 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 12:32:53.681328 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 12:32:53.684563 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1268 12:32:53.691472 0 11 8 | B1->B0 | 3f3f 3737 | 0 1 | (0 0) (0 0)
1269 12:32:53.694792 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:32:53.698120 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 12:32:53.704336 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 12:32:53.708009 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 12:32:53.711090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 12:32:53.718156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 12:32:53.721233 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 12:32:53.724562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1277 12:32:53.731440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:32:53.734592 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:32:53.737823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:32:53.744541 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:32:53.748310 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:32:53.751358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:32:53.754418 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:32:53.761791 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:32:53.764569 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:32:53.767771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 12:32:53.775004 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 12:32:53.778318 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 12:32:53.781696 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 12:32:53.788330 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 12:32:53.791646 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 12:32:53.795025 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1293 12:32:53.801761 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1294 12:32:53.802198 Total UI for P1: 0, mck2ui 16
1295 12:32:53.805022 best dqsien dly found for B0: ( 0, 14, 8)
1296 12:32:53.808312 Total UI for P1: 0, mck2ui 16
1297 12:32:53.811435 best dqsien dly found for B1: ( 0, 14, 8)
1298 12:32:53.815106 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1299 12:32:53.821324 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1300 12:32:53.821750
1301 12:32:53.825272 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1302 12:32:53.828355 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1303 12:32:53.831704 [Gating] SW calibration Done
1304 12:32:53.832158 ==
1305 12:32:53.834890 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 12:32:53.838128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 12:32:53.838562 ==
1308 12:32:53.838906 RX Vref Scan: 0
1309 12:32:53.839229
1310 12:32:53.841779 RX Vref 0 -> 0, step: 1
1311 12:32:53.842420
1312 12:32:53.844909 RX Delay -130 -> 252, step: 16
1313 12:32:53.848194 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1314 12:32:53.851920 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1315 12:32:53.858172 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1316 12:32:53.861874 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1317 12:32:53.864980 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1318 12:32:53.868351 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1319 12:32:53.871671 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1320 12:32:53.878389 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1321 12:32:53.881907 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1322 12:32:53.885109 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1323 12:32:53.888448 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1324 12:32:53.891719 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1325 12:32:53.898379 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1326 12:32:53.901831 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1327 12:32:53.905191 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1328 12:32:53.908484 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1329 12:32:53.908968 ==
1330 12:32:53.911905 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 12:32:53.914927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 12:32:53.918864 ==
1333 12:32:53.919291 DQS Delay:
1334 12:32:53.919764 DQS0 = 0, DQS1 = 0
1335 12:32:53.921998 DQM Delay:
1336 12:32:53.922646 DQM0 = 92, DQM1 = 82
1337 12:32:53.925220 DQ Delay:
1338 12:32:53.925759 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1339 12:32:53.928921 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1340 12:32:53.932223 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1341 12:32:53.935424 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1342 12:32:53.936133
1343 12:32:53.938835
1344 12:32:53.939428 ==
1345 12:32:53.942322 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 12:32:53.945372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 12:32:53.945852 ==
1348 12:32:53.946274
1349 12:32:53.946622
1350 12:32:53.948540 TX Vref Scan disable
1351 12:32:53.948913 == TX Byte 0 ==
1352 12:32:53.955297 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1353 12:32:53.958362 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1354 12:32:53.958818 == TX Byte 1 ==
1355 12:32:53.965246 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1356 12:32:53.968891 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1357 12:32:53.969326 ==
1358 12:32:53.971859 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 12:32:53.975067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 12:32:53.975535 ==
1361 12:32:53.988951 TX Vref=22, minBit 8, minWin=27, winSum=447
1362 12:32:53.992272 TX Vref=24, minBit 11, minWin=27, winSum=453
1363 12:32:53.995264 TX Vref=26, minBit 5, minWin=28, winSum=459
1364 12:32:53.998668 TX Vref=28, minBit 5, minWin=28, winSum=457
1365 12:32:54.002083 TX Vref=30, minBit 5, minWin=28, winSum=458
1366 12:32:54.008660 TX Vref=32, minBit 4, minWin=28, winSum=453
1367 12:32:54.012107 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 26
1368 12:32:54.012257
1369 12:32:54.015275 Final TX Range 1 Vref 26
1370 12:32:54.015426
1371 12:32:54.015526 ==
1372 12:32:54.018563 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 12:32:54.021996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 12:32:54.022125 ==
1375 12:32:54.025418
1376 12:32:54.025545
1377 12:32:54.025644 TX Vref Scan disable
1378 12:32:54.028433 == TX Byte 0 ==
1379 12:32:54.032296 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1380 12:32:54.035362 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1381 12:32:54.038588 == TX Byte 1 ==
1382 12:32:54.042071 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1383 12:32:54.045972 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1384 12:32:54.049333
1385 12:32:54.049746 [DATLAT]
1386 12:32:54.050069 Freq=800, CH0 RK1
1387 12:32:54.050376
1388 12:32:54.052543 DATLAT Default: 0xa
1389 12:32:54.052960 0, 0xFFFF, sum = 0
1390 12:32:54.055661 1, 0xFFFF, sum = 0
1391 12:32:54.056088 2, 0xFFFF, sum = 0
1392 12:32:54.058957 3, 0xFFFF, sum = 0
1393 12:32:54.059418 4, 0xFFFF, sum = 0
1394 12:32:54.062071 5, 0xFFFF, sum = 0
1395 12:32:54.062492 6, 0xFFFF, sum = 0
1396 12:32:54.065966 7, 0xFFFF, sum = 0
1397 12:32:54.069149 8, 0xFFFF, sum = 0
1398 12:32:54.069569 9, 0x0, sum = 1
1399 12:32:54.069902 10, 0x0, sum = 2
1400 12:32:54.072230 11, 0x0, sum = 3
1401 12:32:54.072655 12, 0x0, sum = 4
1402 12:32:54.075379 best_step = 10
1403 12:32:54.075802
1404 12:32:54.076127 ==
1405 12:32:54.079164 Dram Type= 6, Freq= 0, CH_0, rank 1
1406 12:32:54.082361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 12:32:54.082779 ==
1408 12:32:54.085598 RX Vref Scan: 0
1409 12:32:54.086013
1410 12:32:54.086335 RX Vref 0 -> 0, step: 1
1411 12:32:54.086641
1412 12:32:54.088982 RX Delay -95 -> 252, step: 8
1413 12:32:54.095778 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1414 12:32:54.099103 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1415 12:32:54.102865 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1416 12:32:54.105567 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1417 12:32:54.108976 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1418 12:32:54.112384 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1419 12:32:54.119249 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1420 12:32:54.122512 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1421 12:32:54.125811 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1422 12:32:54.129200 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1423 12:32:54.132599 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1424 12:32:54.138749 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1425 12:32:54.142495 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1426 12:32:54.145995 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1427 12:32:54.149119 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1428 12:32:54.155837 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1429 12:32:54.156255 ==
1430 12:32:54.159455 Dram Type= 6, Freq= 0, CH_0, rank 1
1431 12:32:54.162803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 12:32:54.163216 ==
1433 12:32:54.163601 DQS Delay:
1434 12:32:54.166075 DQS0 = 0, DQS1 = 0
1435 12:32:54.166794 DQM Delay:
1436 12:32:54.169707 DQM0 = 93, DQM1 = 83
1437 12:32:54.170485 DQ Delay:
1438 12:32:54.172864 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1439 12:32:54.176004 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1440 12:32:54.179787 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1441 12:32:54.182905 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1442 12:32:54.183483
1443 12:32:54.184045
1444 12:32:54.189834 [DQSOSCAuto] RK1, (LSB)MR18= 0x4516, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1445 12:32:54.193050 CH0 RK1: MR19=606, MR18=4516
1446 12:32:54.200067 CH0_RK1: MR19=0x606, MR18=0x4516, DQSOSC=392, MR23=63, INC=96, DEC=64
1447 12:32:54.202709 [RxdqsGatingPostProcess] freq 800
1448 12:32:54.206333 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1449 12:32:54.209310 Pre-setting of DQS Precalculation
1450 12:32:54.215935 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1451 12:32:54.216354 ==
1452 12:32:54.220044 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 12:32:54.223277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 12:32:54.223768 ==
1455 12:32:54.229894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1456 12:32:54.236037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1457 12:32:54.243790 [CA 0] Center 36 (6~67) winsize 62
1458 12:32:54.247407 [CA 1] Center 36 (6~67) winsize 62
1459 12:32:54.250486 [CA 2] Center 35 (4~66) winsize 63
1460 12:32:54.253825 [CA 3] Center 34 (4~65) winsize 62
1461 12:32:54.257666 [CA 4] Center 34 (4~65) winsize 62
1462 12:32:54.260768 [CA 5] Center 34 (4~65) winsize 62
1463 12:32:54.261193
1464 12:32:54.264051 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1465 12:32:54.264476
1466 12:32:54.267578 [CATrainingPosCal] consider 1 rank data
1467 12:32:54.269835 u2DelayCellTimex100 = 270/100 ps
1468 12:32:54.273708 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1469 12:32:54.276564 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1470 12:32:54.283562 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1471 12:32:54.286686 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 12:32:54.290238 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1473 12:32:54.293433 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 12:32:54.293516
1475 12:32:54.296487 CA PerBit enable=1, Macro0, CA PI delay=34
1476 12:32:54.296570
1477 12:32:54.300366 [CBTSetCACLKResult] CA Dly = 34
1478 12:32:54.300448 CS Dly: 6 (0~37)
1479 12:32:54.303633 ==
1480 12:32:54.303716 Dram Type= 6, Freq= 0, CH_1, rank 1
1481 12:32:54.310663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 12:32:54.310747 ==
1483 12:32:54.314796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1484 12:32:54.321503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1485 12:32:54.330234 [CA 0] Center 36 (6~67) winsize 62
1486 12:32:54.334162 [CA 1] Center 37 (6~68) winsize 63
1487 12:32:54.337607 [CA 2] Center 35 (5~66) winsize 62
1488 12:32:54.341678 [CA 3] Center 34 (4~65) winsize 62
1489 12:32:54.344990 [CA 4] Center 34 (4~65) winsize 62
1490 12:32:54.345073 [CA 5] Center 34 (4~65) winsize 62
1491 12:32:54.348130
1492 12:32:54.351894 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1493 12:32:54.351978
1494 12:32:54.355007 [CATrainingPosCal] consider 2 rank data
1495 12:32:54.358349 u2DelayCellTimex100 = 270/100 ps
1496 12:32:54.361560 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1497 12:32:54.364798 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1498 12:32:54.368051 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1499 12:32:54.371339 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1500 12:32:54.374807 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1501 12:32:54.378185 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 12:32:54.378294
1503 12:32:54.381348 CA PerBit enable=1, Macro0, CA PI delay=34
1504 12:32:54.381452
1505 12:32:54.385009 [CBTSetCACLKResult] CA Dly = 34
1506 12:32:54.388253 CS Dly: 6 (0~38)
1507 12:32:54.388342
1508 12:32:54.391864 ----->DramcWriteLeveling(PI) begin...
1509 12:32:54.391948 ==
1510 12:32:54.394923 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 12:32:54.398851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 12:32:54.398934 ==
1513 12:32:54.402075 Write leveling (Byte 0): 27 => 27
1514 12:32:54.405043 Write leveling (Byte 1): 28 => 28
1515 12:32:54.408457 DramcWriteLeveling(PI) end<-----
1516 12:32:54.408540
1517 12:32:54.408605 ==
1518 12:32:54.411827 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 12:32:54.415036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 12:32:54.415120 ==
1521 12:32:54.419116 [Gating] SW mode calibration
1522 12:32:54.425178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1523 12:32:54.431998 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1524 12:32:54.435493 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1525 12:32:54.438664 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1526 12:32:54.445434 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1527 12:32:54.448771 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:32:54.451935 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:32:54.458369 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:32:54.461974 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:32:54.465296 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:32:54.472213 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:32:54.475271 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:32:54.478575 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:32:54.485176 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:32:54.488471 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:32:54.492352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:32:54.495501 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:32:54.502287 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:32:54.505217 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1541 12:32:54.508883 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1542 12:32:54.515295 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:32:54.518684 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:32:54.522088 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:32:54.528908 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:32:54.532295 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:32:54.535626 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:32:54.542480 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:32:54.545684 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1550 12:32:54.549040 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1551 12:32:54.555566 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 12:32:54.558809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 12:32:54.562036 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 12:32:54.569020 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 12:32:54.572138 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 12:32:54.575294 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 12:32:54.578605 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1558 12:32:54.585672 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1559 12:32:54.588800 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:32:54.592126 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 12:32:54.598795 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 12:32:54.601930 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 12:32:54.605506 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 12:32:54.612426 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1565 12:32:54.615359 0 11 4 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
1566 12:32:54.619177 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1567 12:32:54.625619 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 12:32:54.628924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 12:32:54.632382 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 12:32:54.639063 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 12:32:54.642321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 12:32:54.645537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 12:32:54.652353 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1574 12:32:54.655563 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:32:54.658880 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:32:54.662331 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:32:54.668684 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:32:54.672374 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:32:54.675615 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:32:54.682303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:32:54.685585 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:32:54.688853 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:32:54.695576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:32:54.698910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:32:54.702281 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 12:32:54.708866 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 12:32:54.712571 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 12:32:54.715623 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1589 12:32:54.722709 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1590 12:32:54.725857 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 12:32:54.729521 Total UI for P1: 0, mck2ui 16
1592 12:32:54.732707 best dqsien dly found for B0: ( 0, 14, 2)
1593 12:32:54.735994 Total UI for P1: 0, mck2ui 16
1594 12:32:54.739549 best dqsien dly found for B1: ( 0, 14, 4)
1595 12:32:54.742821 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1596 12:32:54.746100 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1597 12:32:54.746206
1598 12:32:54.749270 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1599 12:32:54.752554 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1600 12:32:54.755793 [Gating] SW calibration Done
1601 12:32:54.755898 ==
1602 12:32:54.759192 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 12:32:54.762574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 12:32:54.762659 ==
1605 12:32:54.765914 RX Vref Scan: 0
1606 12:32:54.766011
1607 12:32:54.766106 RX Vref 0 -> 0, step: 1
1608 12:32:54.769294
1609 12:32:54.769403 RX Delay -130 -> 252, step: 16
1610 12:32:54.776232 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1611 12:32:54.779270 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1612 12:32:54.782457 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1613 12:32:54.785610 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1614 12:32:54.788914 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1615 12:32:54.792938 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1616 12:32:54.799480 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1617 12:32:54.802553 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1618 12:32:54.805845 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1619 12:32:54.809264 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1620 12:32:54.812703 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1621 12:32:54.819006 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1622 12:32:54.822837 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1623 12:32:54.825959 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1624 12:32:54.829071 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1625 12:32:54.835905 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1626 12:32:54.835991 ==
1627 12:32:54.839164 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 12:32:54.842937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 12:32:54.843063 ==
1630 12:32:54.843181 DQS Delay:
1631 12:32:54.846260 DQS0 = 0, DQS1 = 0
1632 12:32:54.846366 DQM Delay:
1633 12:32:54.849605 DQM0 = 96, DQM1 = 93
1634 12:32:54.849712 DQ Delay:
1635 12:32:54.852963 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1636 12:32:54.856244 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1637 12:32:54.859587 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1638 12:32:54.862949 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1639 12:32:54.863023
1640 12:32:54.863087
1641 12:32:54.863147 ==
1642 12:32:54.866218 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 12:32:54.869700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 12:32:54.869785 ==
1645 12:32:54.869852
1646 12:32:54.869913
1647 12:32:54.872979 TX Vref Scan disable
1648 12:32:54.876374 == TX Byte 0 ==
1649 12:32:54.879551 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1650 12:32:54.882734 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1651 12:32:54.885973 == TX Byte 1 ==
1652 12:32:54.889918 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1653 12:32:54.893240 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1654 12:32:54.893327 ==
1655 12:32:54.897226 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 12:32:54.899898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 12:32:54.899984 ==
1658 12:32:54.914593 TX Vref=22, minBit 3, minWin=26, winSum=435
1659 12:32:54.917955 TX Vref=24, minBit 2, minWin=26, winSum=437
1660 12:32:54.921051 TX Vref=26, minBit 3, minWin=26, winSum=442
1661 12:32:54.924378 TX Vref=28, minBit 3, minWin=26, winSum=444
1662 12:32:54.927529 TX Vref=30, minBit 0, minWin=27, winSum=449
1663 12:32:54.931496 TX Vref=32, minBit 2, minWin=27, winSum=446
1664 12:32:54.937850 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1665 12:32:54.937962
1666 12:32:54.940964 Final TX Range 1 Vref 30
1667 12:32:54.941069
1668 12:32:54.941162 ==
1669 12:32:54.944744 Dram Type= 6, Freq= 0, CH_1, rank 0
1670 12:32:54.947931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1671 12:32:54.948042 ==
1672 12:32:54.948140
1673 12:32:54.948253
1674 12:32:54.951469 TX Vref Scan disable
1675 12:32:54.954599 == TX Byte 0 ==
1676 12:32:54.958000 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1677 12:32:54.961433 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1678 12:32:54.964185 == TX Byte 1 ==
1679 12:32:54.968166 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1680 12:32:54.970859 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1681 12:32:54.970964
1682 12:32:54.974226 [DATLAT]
1683 12:32:54.974328 Freq=800, CH1 RK0
1684 12:32:54.974420
1685 12:32:54.977668 DATLAT Default: 0xa
1686 12:32:54.977739 0, 0xFFFF, sum = 0
1687 12:32:54.980990 1, 0xFFFF, sum = 0
1688 12:32:54.981063 2, 0xFFFF, sum = 0
1689 12:32:54.984279 3, 0xFFFF, sum = 0
1690 12:32:54.984348 4, 0xFFFF, sum = 0
1691 12:32:54.988014 5, 0xFFFF, sum = 0
1692 12:32:54.988083 6, 0xFFFF, sum = 0
1693 12:32:54.991183 7, 0xFFFF, sum = 0
1694 12:32:54.991284 8, 0xFFFF, sum = 0
1695 12:32:54.994381 9, 0x0, sum = 1
1696 12:32:54.994481 10, 0x0, sum = 2
1697 12:32:54.997592 11, 0x0, sum = 3
1698 12:32:54.997697 12, 0x0, sum = 4
1699 12:32:55.001059 best_step = 10
1700 12:32:55.001162
1701 12:32:55.001255 ==
1702 12:32:55.004302 Dram Type= 6, Freq= 0, CH_1, rank 0
1703 12:32:55.007619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1704 12:32:55.007701 ==
1705 12:32:55.011507 RX Vref Scan: 1
1706 12:32:55.011655
1707 12:32:55.011779 Set Vref Range= 32 -> 127
1708 12:32:55.011867
1709 12:32:55.014828 RX Vref 32 -> 127, step: 1
1710 12:32:55.014926
1711 12:32:55.017515 RX Delay -63 -> 252, step: 8
1712 12:32:55.017625
1713 12:32:55.021459 Set Vref, RX VrefLevel [Byte0]: 32
1714 12:32:55.024732 [Byte1]: 32
1715 12:32:55.024845
1716 12:32:55.028138 Set Vref, RX VrefLevel [Byte0]: 33
1717 12:32:55.031516 [Byte1]: 33
1718 12:32:55.031627
1719 12:32:55.034635 Set Vref, RX VrefLevel [Byte0]: 34
1720 12:32:55.037905 [Byte1]: 34
1721 12:32:55.041544
1722 12:32:55.041628 Set Vref, RX VrefLevel [Byte0]: 35
1723 12:32:55.044907 [Byte1]: 35
1724 12:32:55.049256
1725 12:32:55.052451 Set Vref, RX VrefLevel [Byte0]: 36
1726 12:32:55.052535 [Byte1]: 36
1727 12:32:55.056977
1728 12:32:55.057069 Set Vref, RX VrefLevel [Byte0]: 37
1729 12:32:55.060156 [Byte1]: 37
1730 12:32:55.064027
1731 12:32:55.064104 Set Vref, RX VrefLevel [Byte0]: 38
1732 12:32:55.067963 [Byte1]: 38
1733 12:32:55.072002
1734 12:32:55.072084 Set Vref, RX VrefLevel [Byte0]: 39
1735 12:32:55.075283 [Byte1]: 39
1736 12:32:55.079297
1737 12:32:55.079387 Set Vref, RX VrefLevel [Byte0]: 40
1738 12:32:55.082516 [Byte1]: 40
1739 12:32:55.086542
1740 12:32:55.086626 Set Vref, RX VrefLevel [Byte0]: 41
1741 12:32:55.089846 [Byte1]: 41
1742 12:32:55.094487
1743 12:32:55.094570 Set Vref, RX VrefLevel [Byte0]: 42
1744 12:32:55.097603 [Byte1]: 42
1745 12:32:55.101711
1746 12:32:55.101795 Set Vref, RX VrefLevel [Byte0]: 43
1747 12:32:55.105385 [Byte1]: 43
1748 12:32:55.109157
1749 12:32:55.109232 Set Vref, RX VrefLevel [Byte0]: 44
1750 12:32:55.112465 [Byte1]: 44
1751 12:32:55.116905
1752 12:32:55.116989 Set Vref, RX VrefLevel [Byte0]: 45
1753 12:32:55.120206 [Byte1]: 45
1754 12:32:55.124209
1755 12:32:55.124293 Set Vref, RX VrefLevel [Byte0]: 46
1756 12:32:55.127439 [Byte1]: 46
1757 12:32:55.131923
1758 12:32:55.132006 Set Vref, RX VrefLevel [Byte0]: 47
1759 12:32:55.135160 [Byte1]: 47
1760 12:32:55.139185
1761 12:32:55.139268 Set Vref, RX VrefLevel [Byte0]: 48
1762 12:32:55.142884 [Byte1]: 48
1763 12:32:55.146922
1764 12:32:55.147005 Set Vref, RX VrefLevel [Byte0]: 49
1765 12:32:55.150012 [Byte1]: 49
1766 12:32:55.154502
1767 12:32:55.154585 Set Vref, RX VrefLevel [Byte0]: 50
1768 12:32:55.157677 [Byte1]: 50
1769 12:32:55.161597
1770 12:32:55.161682 Set Vref, RX VrefLevel [Byte0]: 51
1771 12:32:55.164811 [Byte1]: 51
1772 12:32:55.169302
1773 12:32:55.169386 Set Vref, RX VrefLevel [Byte0]: 52
1774 12:32:55.172635 [Byte1]: 52
1775 12:32:55.176858
1776 12:32:55.176941 Set Vref, RX VrefLevel [Byte0]: 53
1777 12:32:55.180218 [Byte1]: 53
1778 12:32:55.184310
1779 12:32:55.184393 Set Vref, RX VrefLevel [Byte0]: 54
1780 12:32:55.187681 [Byte1]: 54
1781 12:32:55.191636
1782 12:32:55.191720 Set Vref, RX VrefLevel [Byte0]: 55
1783 12:32:55.194991 [Byte1]: 55
1784 12:32:55.199631
1785 12:32:55.199715 Set Vref, RX VrefLevel [Byte0]: 56
1786 12:32:55.202876 [Byte1]: 56
1787 12:32:55.206646
1788 12:32:55.206730 Set Vref, RX VrefLevel [Byte0]: 57
1789 12:32:55.210312 [Byte1]: 57
1790 12:32:55.214037
1791 12:32:55.214151 Set Vref, RX VrefLevel [Byte0]: 58
1792 12:32:55.217672 [Byte1]: 58
1793 12:32:55.222172
1794 12:32:55.222281 Set Vref, RX VrefLevel [Byte0]: 59
1795 12:32:55.224877 [Byte1]: 59
1796 12:32:55.229550
1797 12:32:55.229634 Set Vref, RX VrefLevel [Byte0]: 60
1798 12:32:55.232569 [Byte1]: 60
1799 12:32:55.236527
1800 12:32:55.236609 Set Vref, RX VrefLevel [Byte0]: 61
1801 12:32:55.239842 [Byte1]: 61
1802 12:32:55.244488
1803 12:32:55.244571 Set Vref, RX VrefLevel [Byte0]: 62
1804 12:32:55.247670 [Byte1]: 62
1805 12:32:55.252009
1806 12:32:55.252092 Set Vref, RX VrefLevel [Byte0]: 63
1807 12:32:55.255095 [Byte1]: 63
1808 12:32:55.259709
1809 12:32:55.259792 Set Vref, RX VrefLevel [Byte0]: 64
1810 12:32:55.262644 [Byte1]: 64
1811 12:32:55.266534
1812 12:32:55.266617 Set Vref, RX VrefLevel [Byte0]: 65
1813 12:32:55.270288 [Byte1]: 65
1814 12:32:55.274255
1815 12:32:55.274336 Set Vref, RX VrefLevel [Byte0]: 66
1816 12:32:55.277553 [Byte1]: 66
1817 12:32:55.281648
1818 12:32:55.281720 Set Vref, RX VrefLevel [Byte0]: 67
1819 12:32:55.284977 [Byte1]: 67
1820 12:32:55.289029
1821 12:32:55.289110 Set Vref, RX VrefLevel [Byte0]: 68
1822 12:32:55.292456 [Byte1]: 68
1823 12:32:55.296561
1824 12:32:55.296662 Set Vref, RX VrefLevel [Byte0]: 69
1825 12:32:55.299897 [Byte1]: 69
1826 12:32:55.304422
1827 12:32:55.304503 Set Vref, RX VrefLevel [Byte0]: 70
1828 12:32:55.307688 [Byte1]: 70
1829 12:32:55.311759
1830 12:32:55.311840 Set Vref, RX VrefLevel [Byte0]: 71
1831 12:32:55.314977 [Byte1]: 71
1832 12:32:55.319537
1833 12:32:55.319655 Set Vref, RX VrefLevel [Byte0]: 72
1834 12:32:55.322494 [Byte1]: 72
1835 12:32:55.326763
1836 12:32:55.326847 Final RX Vref Byte 0 = 58 to rank0
1837 12:32:55.330016 Final RX Vref Byte 1 = 57 to rank0
1838 12:32:55.333287 Final RX Vref Byte 0 = 58 to rank1
1839 12:32:55.336877 Final RX Vref Byte 1 = 57 to rank1==
1840 12:32:55.339879 Dram Type= 6, Freq= 0, CH_1, rank 0
1841 12:32:55.346510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 12:32:55.346594 ==
1843 12:32:55.346660 DQS Delay:
1844 12:32:55.346721 DQS0 = 0, DQS1 = 0
1845 12:32:55.349763 DQM Delay:
1846 12:32:55.349877 DQM0 = 95, DQM1 = 90
1847 12:32:55.353640 DQ Delay:
1848 12:32:55.356771 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1849 12:32:55.360463 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1850 12:32:55.363495 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1851 12:32:55.366717 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1852 12:32:55.366800
1853 12:32:55.366894
1854 12:32:55.373652 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1855 12:32:55.376810 CH1 RK0: MR19=606, MR18=2B47
1856 12:32:55.383480 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1857 12:32:55.383564
1858 12:32:55.386872 ----->DramcWriteLeveling(PI) begin...
1859 12:32:55.386956 ==
1860 12:32:55.390231 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 12:32:55.393591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 12:32:55.393691 ==
1863 12:32:55.397122 Write leveling (Byte 0): 27 => 27
1864 12:32:55.399859 Write leveling (Byte 1): 25 => 25
1865 12:32:55.403211 DramcWriteLeveling(PI) end<-----
1866 12:32:55.403292
1867 12:32:55.403434 ==
1868 12:32:55.406592 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 12:32:55.410361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 12:32:55.410476 ==
1871 12:32:55.413134 [Gating] SW mode calibration
1872 12:32:55.419860 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1873 12:32:55.426960 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1874 12:32:55.429999 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1875 12:32:55.433226 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1876 12:32:55.440232 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:32:55.443522 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:32:55.446542 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:32:55.453287 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:32:55.456739 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:32:55.460096 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:32:55.466609 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:32:55.470165 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:32:55.473471 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:32:55.479838 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:32:55.483128 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:32:55.486791 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:32:55.493494 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:32:55.496958 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:32:55.500212 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1891 12:32:55.506931 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:32:55.510271 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:32:55.513481 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:32:55.516821 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:32:55.523457 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:32:55.526658 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:32:55.529844 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:32:55.536959 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:32:55.540214 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1900 12:32:55.543312 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1901 12:32:55.549714 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 12:32:55.553525 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 12:32:55.556791 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 12:32:55.563583 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 12:32:55.566887 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 12:32:55.570270 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 12:32:55.576599 0 10 4 | B1->B0 | 2d2d 2f2f | 0 1 | (0 0) (1 0)
1908 12:32:55.580091 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1909 12:32:55.583263 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:32:55.590365 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:32:55.593580 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:32:55.596609 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:32:55.600422 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:32:55.607052 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1915 12:32:55.610367 0 11 4 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (0 0)
1916 12:32:55.613876 0 11 8 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
1917 12:32:55.619788 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 12:32:55.623228 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 12:32:55.626537 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 12:32:55.633082 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 12:32:55.636453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:32:55.639826 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 12:32:55.646831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1924 12:32:55.649854 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:32:55.653030 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:32:55.660105 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:32:55.663417 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:32:55.666688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:32:55.673395 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:32:55.676711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:32:55.680103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:32:55.683241 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:32:55.690251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:32:55.693464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:32:55.697215 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:32:55.703490 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:32:55.706792 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:32:55.710055 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:32:55.716831 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 12:32:55.716904 Total UI for P1: 0, mck2ui 16
1941 12:32:55.723518 best dqsien dly found for B0: ( 0, 14, 2)
1942 12:32:55.723592 Total UI for P1: 0, mck2ui 16
1943 12:32:55.730117 best dqsien dly found for B1: ( 0, 14, 2)
1944 12:32:55.733400 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1945 12:32:55.736849 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1946 12:32:55.736947
1947 12:32:55.740175 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1948 12:32:55.743561 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1949 12:32:55.747359 [Gating] SW calibration Done
1950 12:32:55.747453 ==
1951 12:32:55.750579 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 12:32:55.753737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 12:32:55.753828 ==
1954 12:32:55.756870 RX Vref Scan: 0
1955 12:32:55.756952
1956 12:32:55.757019 RX Vref 0 -> 0, step: 1
1957 12:32:55.757080
1958 12:32:55.760742 RX Delay -130 -> 252, step: 16
1959 12:32:55.763969 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1960 12:32:55.767201 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1961 12:32:55.773703 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1962 12:32:55.777739 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1963 12:32:55.780482 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1964 12:32:55.783784 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1965 12:32:55.787684 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1966 12:32:55.794160 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1967 12:32:55.797437 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1968 12:32:55.800656 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1969 12:32:55.803876 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1970 12:32:55.807494 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1971 12:32:55.813729 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1972 12:32:55.817154 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1973 12:32:55.820511 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1974 12:32:55.823825 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1975 12:32:55.823936 ==
1976 12:32:55.827807 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 12:32:55.834333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 12:32:55.834441 ==
1979 12:32:55.834545 DQS Delay:
1980 12:32:55.834650 DQS0 = 0, DQS1 = 0
1981 12:32:55.837555 DQM Delay:
1982 12:32:55.837665 DQM0 = 92, DQM1 = 89
1983 12:32:55.841047 DQ Delay:
1984 12:32:55.843821 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1985 12:32:55.847148 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1986 12:32:55.850564 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1987 12:32:55.853815 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1988 12:32:55.853969
1989 12:32:55.854062
1990 12:32:55.854182 ==
1991 12:32:55.857539 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 12:32:55.860661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 12:32:55.860806 ==
1994 12:32:55.860899
1995 12:32:55.861010
1996 12:32:55.863758 TX Vref Scan disable
1997 12:32:55.863856 == TX Byte 0 ==
1998 12:32:55.870902 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1999 12:32:55.874254 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2000 12:32:55.874358 == TX Byte 1 ==
2001 12:32:55.880795 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2002 12:32:55.884120 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2003 12:32:55.884218 ==
2004 12:32:55.887485 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 12:32:55.890498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 12:32:55.890576 ==
2007 12:32:55.904906 TX Vref=22, minBit 2, minWin=26, winSum=443
2008 12:32:55.908184 TX Vref=24, minBit 2, minWin=26, winSum=444
2009 12:32:55.912067 TX Vref=26, minBit 1, minWin=27, winSum=450
2010 12:32:55.915237 TX Vref=28, minBit 1, minWin=27, winSum=452
2011 12:32:55.918362 TX Vref=30, minBit 3, minWin=27, winSum=448
2012 12:32:55.921570 TX Vref=32, minBit 1, minWin=27, winSum=448
2013 12:32:55.928718 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 28
2014 12:32:55.928796
2015 12:32:55.931998 Final TX Range 1 Vref 28
2016 12:32:55.932094
2017 12:32:55.932164 ==
2018 12:32:55.935246 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 12:32:55.938660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 12:32:55.938742 ==
2021 12:32:55.938807
2022 12:32:55.938866
2023 12:32:55.941839 TX Vref Scan disable
2024 12:32:55.945101 == TX Byte 0 ==
2025 12:32:55.948432 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2026 12:32:55.951754 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2027 12:32:55.955126 == TX Byte 1 ==
2028 12:32:55.958590 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2029 12:32:55.961745 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2030 12:32:55.961830
2031 12:32:55.965601 [DATLAT]
2032 12:32:55.965694 Freq=800, CH1 RK1
2033 12:32:55.965762
2034 12:32:55.968674 DATLAT Default: 0xa
2035 12:32:55.968755 0, 0xFFFF, sum = 0
2036 12:32:55.971697 1, 0xFFFF, sum = 0
2037 12:32:55.971784 2, 0xFFFF, sum = 0
2038 12:32:55.975483 3, 0xFFFF, sum = 0
2039 12:32:55.975575 4, 0xFFFF, sum = 0
2040 12:32:55.978799 5, 0xFFFF, sum = 0
2041 12:32:55.978877 6, 0xFFFF, sum = 0
2042 12:32:55.982093 7, 0xFFFF, sum = 0
2043 12:32:55.982178 8, 0xFFFF, sum = 0
2044 12:32:55.985248 9, 0x0, sum = 1
2045 12:32:55.985335 10, 0x0, sum = 2
2046 12:32:55.988839 11, 0x0, sum = 3
2047 12:32:55.988934 12, 0x0, sum = 4
2048 12:32:55.992137 best_step = 10
2049 12:32:55.992221
2050 12:32:55.992301 ==
2051 12:32:55.995296 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 12:32:55.998593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 12:32:55.998687 ==
2054 12:32:56.001896 RX Vref Scan: 0
2055 12:32:56.001974
2056 12:32:56.002058 RX Vref 0 -> 0, step: 1
2057 12:32:56.002122
2058 12:32:56.005287 RX Delay -79 -> 252, step: 8
2059 12:32:56.011697 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2060 12:32:56.015554 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2061 12:32:56.018740 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2062 12:32:56.022015 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2063 12:32:56.025153 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2064 12:32:56.028532 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2065 12:32:56.035009 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2066 12:32:56.038312 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2067 12:32:56.041688 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2068 12:32:56.045505 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2069 12:32:56.048878 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2070 12:32:56.055554 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2071 12:32:56.058328 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2072 12:32:56.061656 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2073 12:32:56.065629 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2074 12:32:56.068820 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2075 12:32:56.068904 ==
2076 12:32:56.072000 Dram Type= 6, Freq= 0, CH_1, rank 1
2077 12:32:56.078435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2078 12:32:56.078549 ==
2079 12:32:56.078653 DQS Delay:
2080 12:32:56.082095 DQS0 = 0, DQS1 = 0
2081 12:32:56.082185 DQM Delay:
2082 12:32:56.082279 DQM0 = 97, DQM1 = 91
2083 12:32:56.085380 DQ Delay:
2084 12:32:56.088564 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2085 12:32:56.092405 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2086 12:32:56.095609 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2087 12:32:56.098681 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2088 12:32:56.098766
2089 12:32:56.098834
2090 12:32:56.105692 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2091 12:32:56.108943 CH1 RK1: MR19=606, MR18=4711
2092 12:32:56.115582 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2093 12:32:56.118861 [RxdqsGatingPostProcess] freq 800
2094 12:32:56.121996 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2095 12:32:56.125228 Pre-setting of DQS Precalculation
2096 12:32:56.132279 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2097 12:32:56.138711 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2098 12:32:56.145486 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2099 12:32:56.145596
2100 12:32:56.145693
2101 12:32:56.148769 [Calibration Summary] 1600 Mbps
2102 12:32:56.148873 CH 0, Rank 0
2103 12:32:56.151970 SW Impedance : PASS
2104 12:32:56.155424 DUTY Scan : NO K
2105 12:32:56.155526 ZQ Calibration : PASS
2106 12:32:56.158818 Jitter Meter : NO K
2107 12:32:56.162327 CBT Training : PASS
2108 12:32:56.162439 Write leveling : PASS
2109 12:32:56.165583 RX DQS gating : PASS
2110 12:32:56.168974 RX DQ/DQS(RDDQC) : PASS
2111 12:32:56.169086 TX DQ/DQS : PASS
2112 12:32:56.172452 RX DATLAT : PASS
2113 12:32:56.172554 RX DQ/DQS(Engine): PASS
2114 12:32:56.175169 TX OE : NO K
2115 12:32:56.175273 All Pass.
2116 12:32:56.175395
2117 12:32:56.178847 CH 0, Rank 1
2118 12:32:56.178951 SW Impedance : PASS
2119 12:32:56.181991 DUTY Scan : NO K
2120 12:32:56.185831 ZQ Calibration : PASS
2121 12:32:56.185916 Jitter Meter : NO K
2122 12:32:56.188830 CBT Training : PASS
2123 12:32:56.192206 Write leveling : PASS
2124 12:32:56.192290 RX DQS gating : PASS
2125 12:32:56.195362 RX DQ/DQS(RDDQC) : PASS
2126 12:32:56.199196 TX DQ/DQS : PASS
2127 12:32:56.199280 RX DATLAT : PASS
2128 12:32:56.202332 RX DQ/DQS(Engine): PASS
2129 12:32:56.205915 TX OE : NO K
2130 12:32:56.206037 All Pass.
2131 12:32:56.206135
2132 12:32:56.206227 CH 1, Rank 0
2133 12:32:56.209253 SW Impedance : PASS
2134 12:32:56.209325 DUTY Scan : NO K
2135 12:32:56.212514 ZQ Calibration : PASS
2136 12:32:56.215823 Jitter Meter : NO K
2137 12:32:56.215897 CBT Training : PASS
2138 12:32:56.219081 Write leveling : PASS
2139 12:32:56.222871 RX DQS gating : PASS
2140 12:32:56.222970 RX DQ/DQS(RDDQC) : PASS
2141 12:32:56.226149 TX DQ/DQS : PASS
2142 12:32:56.229153 RX DATLAT : PASS
2143 12:32:56.229256 RX DQ/DQS(Engine): PASS
2144 12:32:56.232432 TX OE : NO K
2145 12:32:56.232507 All Pass.
2146 12:32:56.232585
2147 12:32:56.236125 CH 1, Rank 1
2148 12:32:56.236209 SW Impedance : PASS
2149 12:32:56.239180 DUTY Scan : NO K
2150 12:32:56.242351 ZQ Calibration : PASS
2151 12:32:56.242467 Jitter Meter : NO K
2152 12:32:56.246216 CBT Training : PASS
2153 12:32:56.246329 Write leveling : PASS
2154 12:32:56.249655 RX DQS gating : PASS
2155 12:32:56.252822 RX DQ/DQS(RDDQC) : PASS
2156 12:32:56.252899 TX DQ/DQS : PASS
2157 12:32:56.256193 RX DATLAT : PASS
2158 12:32:56.259573 RX DQ/DQS(Engine): PASS
2159 12:32:56.259659 TX OE : NO K
2160 12:32:56.262921 All Pass.
2161 12:32:56.263006
2162 12:32:56.263072 DramC Write-DBI off
2163 12:32:56.266314 PER_BANK_REFRESH: Hybrid Mode
2164 12:32:56.266408 TX_TRACKING: ON
2165 12:32:56.269722 [GetDramInforAfterCalByMRR] Vendor 6.
2166 12:32:56.276245 [GetDramInforAfterCalByMRR] Revision 606.
2167 12:32:56.279709 [GetDramInforAfterCalByMRR] Revision 2 0.
2168 12:32:56.279793 MR0 0x3b3b
2169 12:32:56.279858 MR8 0x5151
2170 12:32:56.282915 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 12:32:56.282997
2172 12:32:56.286235 MR0 0x3b3b
2173 12:32:56.286312 MR8 0x5151
2174 12:32:56.289384 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 12:32:56.289457
2176 12:32:56.299164 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2177 12:32:56.302574 [FAST_K] Save calibration result to emmc
2178 12:32:56.305876 [FAST_K] Save calibration result to emmc
2179 12:32:56.309611 dram_init: config_dvfs: 1
2180 12:32:56.312761 dramc_set_vcore_voltage set vcore to 662500
2181 12:32:56.316460 Read voltage for 1200, 2
2182 12:32:56.316544 Vio18 = 0
2183 12:32:56.316610 Vcore = 662500
2184 12:32:56.319147 Vdram = 0
2185 12:32:56.319218 Vddq = 0
2186 12:32:56.319278 Vmddr = 0
2187 12:32:56.325917 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2188 12:32:56.329700 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2189 12:32:56.332946 MEM_TYPE=3, freq_sel=15
2190 12:32:56.336038 sv_algorithm_assistance_LP4_1600
2191 12:32:56.339380 ============ PULL DRAM RESETB DOWN ============
2192 12:32:56.343063 ========== PULL DRAM RESETB DOWN end =========
2193 12:32:56.349289 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2194 12:32:56.353289 ===================================
2195 12:32:56.353375 LPDDR4 DRAM CONFIGURATION
2196 12:32:56.356486 ===================================
2197 12:32:56.359651 EX_ROW_EN[0] = 0x0
2198 12:32:56.359737 EX_ROW_EN[1] = 0x0
2199 12:32:56.362983 LP4Y_EN = 0x0
2200 12:32:56.366321 WORK_FSP = 0x0
2201 12:32:56.366410 WL = 0x4
2202 12:32:56.369733 RL = 0x4
2203 12:32:56.369855 BL = 0x2
2204 12:32:56.372920 RPST = 0x0
2205 12:32:56.372995 RD_PRE = 0x0
2206 12:32:56.376267 WR_PRE = 0x1
2207 12:32:56.376346 WR_PST = 0x0
2208 12:32:56.379641 DBI_WR = 0x0
2209 12:32:56.379751 DBI_RD = 0x0
2210 12:32:56.382928 OTF = 0x1
2211 12:32:56.386296 ===================================
2212 12:32:56.389591 ===================================
2213 12:32:56.389703 ANA top config
2214 12:32:56.392936 ===================================
2215 12:32:56.396184 DLL_ASYNC_EN = 0
2216 12:32:56.399961 ALL_SLAVE_EN = 0
2217 12:32:56.400048 NEW_RANK_MODE = 1
2218 12:32:56.403126 DLL_IDLE_MODE = 1
2219 12:32:56.406260 LP45_APHY_COMB_EN = 1
2220 12:32:56.410067 TX_ODT_DIS = 1
2221 12:32:56.410153 NEW_8X_MODE = 1
2222 12:32:56.413244 ===================================
2223 12:32:56.416408 ===================================
2224 12:32:56.419476 data_rate = 2400
2225 12:32:56.423100 CKR = 1
2226 12:32:56.426503 DQ_P2S_RATIO = 8
2227 12:32:56.429882 ===================================
2228 12:32:56.433189 CA_P2S_RATIO = 8
2229 12:32:56.436352 DQ_CA_OPEN = 0
2230 12:32:56.436437 DQ_SEMI_OPEN = 0
2231 12:32:56.440228 CA_SEMI_OPEN = 0
2232 12:32:56.443343 CA_FULL_RATE = 0
2233 12:32:56.446690 DQ_CKDIV4_EN = 0
2234 12:32:56.449757 CA_CKDIV4_EN = 0
2235 12:32:56.453517 CA_PREDIV_EN = 0
2236 12:32:56.453602 PH8_DLY = 17
2237 12:32:56.456548 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2238 12:32:56.459887 DQ_AAMCK_DIV = 4
2239 12:32:56.463206 CA_AAMCK_DIV = 4
2240 12:32:56.466739 CA_ADMCK_DIV = 4
2241 12:32:56.470053 DQ_TRACK_CA_EN = 0
2242 12:32:56.470137 CA_PICK = 1200
2243 12:32:56.473433 CA_MCKIO = 1200
2244 12:32:56.476731 MCKIO_SEMI = 0
2245 12:32:56.480063 PLL_FREQ = 2366
2246 12:32:56.482816 DQ_UI_PI_RATIO = 32
2247 12:32:56.486130 CA_UI_PI_RATIO = 0
2248 12:32:56.489485 ===================================
2249 12:32:56.492865 ===================================
2250 12:32:56.492950 memory_type:LPDDR4
2251 12:32:56.496219 GP_NUM : 10
2252 12:32:56.499587 SRAM_EN : 1
2253 12:32:56.499671 MD32_EN : 0
2254 12:32:56.502874 ===================================
2255 12:32:56.506230 [ANA_INIT] >>>>>>>>>>>>>>
2256 12:32:56.509458 <<<<<< [CONFIGURE PHASE]: ANA_TX
2257 12:32:56.513190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2258 12:32:56.516373 ===================================
2259 12:32:56.519492 data_rate = 2400,PCW = 0X5b00
2260 12:32:56.522764 ===================================
2261 12:32:56.526521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2262 12:32:56.529703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 12:32:56.536439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 12:32:56.539568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2265 12:32:56.542783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2266 12:32:56.546567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2267 12:32:56.549738 [ANA_INIT] flow start
2268 12:32:56.552918 [ANA_INIT] PLL >>>>>>>>
2269 12:32:56.553003 [ANA_INIT] PLL <<<<<<<<
2270 12:32:56.556213 [ANA_INIT] MIDPI >>>>>>>>
2271 12:32:56.559468 [ANA_INIT] MIDPI <<<<<<<<
2272 12:32:56.563250 [ANA_INIT] DLL >>>>>>>>
2273 12:32:56.563333 [ANA_INIT] DLL <<<<<<<<
2274 12:32:56.566331 [ANA_INIT] flow end
2275 12:32:56.569691 ============ LP4 DIFF to SE enter ============
2276 12:32:56.572982 ============ LP4 DIFF to SE exit ============
2277 12:32:56.576461 [ANA_INIT] <<<<<<<<<<<<<
2278 12:32:56.579772 [Flow] Enable top DCM control >>>>>
2279 12:32:56.583182 [Flow] Enable top DCM control <<<<<
2280 12:32:56.586492 Enable DLL master slave shuffle
2281 12:32:56.593193 ==============================================================
2282 12:32:56.593278 Gating Mode config
2283 12:32:56.599836 ==============================================================
2284 12:32:56.599922 Config description:
2285 12:32:56.609883 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2286 12:32:56.616182 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2287 12:32:56.623057 SELPH_MODE 0: By rank 1: By Phase
2288 12:32:56.626209 ==============================================================
2289 12:32:56.629412 GAT_TRACK_EN = 1
2290 12:32:56.632758 RX_GATING_MODE = 2
2291 12:32:56.636540 RX_GATING_TRACK_MODE = 2
2292 12:32:56.639830 SELPH_MODE = 1
2293 12:32:56.643170 PICG_EARLY_EN = 1
2294 12:32:56.646380 VALID_LAT_VALUE = 1
2295 12:32:56.649584 ==============================================================
2296 12:32:56.653543 Enter into Gating configuration >>>>
2297 12:32:56.656751 Exit from Gating configuration <<<<
2298 12:32:56.659926 Enter into DVFS_PRE_config >>>>>
2299 12:32:56.673279 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2300 12:32:56.673396 Exit from DVFS_PRE_config <<<<<
2301 12:32:56.676587 Enter into PICG configuration >>>>
2302 12:32:56.680003 Exit from PICG configuration <<<<
2303 12:32:56.683222 [RX_INPUT] configuration >>>>>
2304 12:32:56.686593 [RX_INPUT] configuration <<<<<
2305 12:32:56.692894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2306 12:32:56.696202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2307 12:32:56.703007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 12:32:56.709612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 12:32:56.716171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 12:32:56.723161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 12:32:56.726289 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2312 12:32:56.729649 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2313 12:32:56.733306 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2314 12:32:56.739922 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2315 12:32:56.743156 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2316 12:32:56.746563 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2317 12:32:56.749696 ===================================
2318 12:32:56.753471 LPDDR4 DRAM CONFIGURATION
2319 12:32:56.756891 ===================================
2320 12:32:56.756980 EX_ROW_EN[0] = 0x0
2321 12:32:56.759946 EX_ROW_EN[1] = 0x0
2322 12:32:56.760019 LP4Y_EN = 0x0
2323 12:32:56.763165 WORK_FSP = 0x0
2324 12:32:56.763262 WL = 0x4
2325 12:32:56.766343 RL = 0x4
2326 12:32:56.766441 BL = 0x2
2327 12:32:56.770199 RPST = 0x0
2328 12:32:56.773356 RD_PRE = 0x0
2329 12:32:56.773462 WR_PRE = 0x1
2330 12:32:56.776520 WR_PST = 0x0
2331 12:32:56.776591 DBI_WR = 0x0
2332 12:32:56.779673 DBI_RD = 0x0
2333 12:32:56.779748 OTF = 0x1
2334 12:32:56.783633 ===================================
2335 12:32:56.786987 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2336 12:32:56.790371 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2337 12:32:56.796502 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2338 12:32:56.799863 ===================================
2339 12:32:56.803263 LPDDR4 DRAM CONFIGURATION
2340 12:32:56.806511 ===================================
2341 12:32:56.806595 EX_ROW_EN[0] = 0x10
2342 12:32:56.809835 EX_ROW_EN[1] = 0x0
2343 12:32:56.809947 LP4Y_EN = 0x0
2344 12:32:56.813170 WORK_FSP = 0x0
2345 12:32:56.813282 WL = 0x4
2346 12:32:56.816587 RL = 0x4
2347 12:32:56.816692 BL = 0x2
2348 12:32:56.819872 RPST = 0x0
2349 12:32:56.819974 RD_PRE = 0x0
2350 12:32:56.823001 WR_PRE = 0x1
2351 12:32:56.823107 WR_PST = 0x0
2352 12:32:56.826232 DBI_WR = 0x0
2353 12:32:56.826332 DBI_RD = 0x0
2354 12:32:56.830031 OTF = 0x1
2355 12:32:56.833291 ===================================
2356 12:32:56.840136 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2357 12:32:56.840221 ==
2358 12:32:56.843416 Dram Type= 6, Freq= 0, CH_0, rank 0
2359 12:32:56.846646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 12:32:56.846754 ==
2361 12:32:56.849983 [Duty_Offset_Calibration]
2362 12:32:56.850093 B0:2 B1:1 CA:1
2363 12:32:56.850186
2364 12:32:56.853400 [DutyScan_Calibration_Flow] k_type=0
2365 12:32:56.863597
2366 12:32:56.863682 ==CLK 0==
2367 12:32:56.867214 Final CLK duty delay cell = 0
2368 12:32:56.870426 [0] MAX Duty = 5187%(X100), DQS PI = 24
2369 12:32:56.873570 [0] MIN Duty = 4875%(X100), DQS PI = 0
2370 12:32:56.873670 [0] AVG Duty = 5031%(X100)
2371 12:32:56.873759
2372 12:32:56.877379 CH0 CLK Duty spec in!! Max-Min= 312%
2373 12:32:56.883715 [DutyScan_Calibration_Flow] ====Done====
2374 12:32:56.883796
2375 12:32:56.886852 [DutyScan_Calibration_Flow] k_type=1
2376 12:32:56.902231
2377 12:32:56.902312 ==DQS 0 ==
2378 12:32:56.905709 Final DQS duty delay cell = -4
2379 12:32:56.908913 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2380 12:32:56.912220 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2381 12:32:56.915474 [-4] AVG Duty = 4953%(X100)
2382 12:32:56.915574
2383 12:32:56.915638 ==DQS 1 ==
2384 12:32:56.918834 Final DQS duty delay cell = 0
2385 12:32:56.922218 [0] MAX Duty = 5156%(X100), DQS PI = 46
2386 12:32:56.925456 [0] MIN Duty = 5031%(X100), DQS PI = 32
2387 12:32:56.929305 [0] AVG Duty = 5093%(X100)
2388 12:32:56.929409
2389 12:32:56.932380 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2390 12:32:56.932449
2391 12:32:56.935606 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2392 12:32:56.938687 [DutyScan_Calibration_Flow] ====Done====
2393 12:32:56.938767
2394 12:32:56.942426 [DutyScan_Calibration_Flow] k_type=3
2395 12:32:56.959317
2396 12:32:56.959445 ==DQM 0 ==
2397 12:32:56.962724 Final DQM duty delay cell = 0
2398 12:32:56.965990 [0] MAX Duty = 5156%(X100), DQS PI = 30
2399 12:32:56.969221 [0] MIN Duty = 4875%(X100), DQS PI = 58
2400 12:32:56.972295 [0] AVG Duty = 5015%(X100)
2401 12:32:56.972378
2402 12:32:56.972449 ==DQM 1 ==
2403 12:32:56.975977 Final DQM duty delay cell = 0
2404 12:32:56.979133 [0] MAX Duty = 5124%(X100), DQS PI = 8
2405 12:32:56.982265 [0] MIN Duty = 5031%(X100), DQS PI = 16
2406 12:32:56.985555 [0] AVG Duty = 5077%(X100)
2407 12:32:56.985677
2408 12:32:56.989319 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2409 12:32:56.989435
2410 12:32:56.992384 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2411 12:32:56.995592 [DutyScan_Calibration_Flow] ====Done====
2412 12:32:56.995693
2413 12:32:56.998960 [DutyScan_Calibration_Flow] k_type=2
2414 12:32:57.015484
2415 12:32:57.015571 ==DQ 0 ==
2416 12:32:57.018850 Final DQ duty delay cell = 0
2417 12:32:57.022333 [0] MAX Duty = 5062%(X100), DQS PI = 32
2418 12:32:57.025735 [0] MIN Duty = 4906%(X100), DQS PI = 0
2419 12:32:57.025832 [0] AVG Duty = 4984%(X100)
2420 12:32:57.025922
2421 12:32:57.029109 ==DQ 1 ==
2422 12:32:57.032427 Final DQ duty delay cell = 0
2423 12:32:57.035606 [0] MAX Duty = 5093%(X100), DQS PI = 10
2424 12:32:57.038869 [0] MIN Duty = 4969%(X100), DQS PI = 14
2425 12:32:57.038943 [0] AVG Duty = 5031%(X100)
2426 12:32:57.039005
2427 12:32:57.042713 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2428 12:32:57.042793
2429 12:32:57.045807 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2430 12:32:57.052247 [DutyScan_Calibration_Flow] ====Done====
2431 12:32:57.052330 ==
2432 12:32:57.056072 Dram Type= 6, Freq= 0, CH_1, rank 0
2433 12:32:57.059296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2434 12:32:57.059412 ==
2435 12:32:57.062687 [Duty_Offset_Calibration]
2436 12:32:57.062769 B0:1 B1:0 CA:0
2437 12:32:57.062834
2438 12:32:57.066027 [DutyScan_Calibration_Flow] k_type=0
2439 12:32:57.074598
2440 12:32:57.074676 ==CLK 0==
2441 12:32:57.078355 Final CLK duty delay cell = -4
2442 12:32:57.081547 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2443 12:32:57.084857 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2444 12:32:57.087950 [-4] AVG Duty = 4969%(X100)
2445 12:32:57.088060
2446 12:32:57.091754 CH1 CLK Duty spec in!! Max-Min= 124%
2447 12:32:57.094741 [DutyScan_Calibration_Flow] ====Done====
2448 12:32:57.094848
2449 12:32:57.098389 [DutyScan_Calibration_Flow] k_type=1
2450 12:32:57.114558
2451 12:32:57.114642 ==DQS 0 ==
2452 12:32:57.117848 Final DQS duty delay cell = 0
2453 12:32:57.121217 [0] MAX Duty = 5094%(X100), DQS PI = 24
2454 12:32:57.124585 [0] MIN Duty = 4875%(X100), DQS PI = 0
2455 12:32:57.124679 [0] AVG Duty = 4984%(X100)
2456 12:32:57.127935
2457 12:32:57.128049 ==DQS 1 ==
2458 12:32:57.131185 Final DQS duty delay cell = 0
2459 12:32:57.134516 [0] MAX Duty = 5218%(X100), DQS PI = 20
2460 12:32:57.137955 [0] MIN Duty = 4969%(X100), DQS PI = 10
2461 12:32:57.138038 [0] AVG Duty = 5093%(X100)
2462 12:32:57.141153
2463 12:32:57.144339 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2464 12:32:57.144423
2465 12:32:57.147943 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2466 12:32:57.151236 [DutyScan_Calibration_Flow] ====Done====
2467 12:32:57.151342
2468 12:32:57.154235 [DutyScan_Calibration_Flow] k_type=3
2469 12:32:57.170951
2470 12:32:57.171067 ==DQM 0 ==
2471 12:32:57.174388 Final DQM duty delay cell = 0
2472 12:32:57.177745 [0] MAX Duty = 5156%(X100), DQS PI = 6
2473 12:32:57.181018 [0] MIN Duty = 5000%(X100), DQS PI = 62
2474 12:32:57.181093 [0] AVG Duty = 5078%(X100)
2475 12:32:57.185061
2476 12:32:57.185165 ==DQM 1 ==
2477 12:32:57.188165 Final DQM duty delay cell = 0
2478 12:32:57.191435 [0] MAX Duty = 5031%(X100), DQS PI = 14
2479 12:32:57.194388 [0] MIN Duty = 4907%(X100), DQS PI = 36
2480 12:32:57.194501 [0] AVG Duty = 4969%(X100)
2481 12:32:57.197440
2482 12:32:57.201267 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2483 12:32:57.201380
2484 12:32:57.204385 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2485 12:32:57.208262 [DutyScan_Calibration_Flow] ====Done====
2486 12:32:57.208346
2487 12:32:57.210850 [DutyScan_Calibration_Flow] k_type=2
2488 12:32:57.226914
2489 12:32:57.227054 ==DQ 0 ==
2490 12:32:57.230229 Final DQ duty delay cell = -4
2491 12:32:57.233722 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2492 12:32:57.236963 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2493 12:32:57.237072 [-4] AVG Duty = 5000%(X100)
2494 12:32:57.240289
2495 12:32:57.240397 ==DQ 1 ==
2496 12:32:57.243717 Final DQ duty delay cell = 0
2497 12:32:57.246989 [0] MAX Duty = 5125%(X100), DQS PI = 20
2498 12:32:57.250700 [0] MIN Duty = 4969%(X100), DQS PI = 10
2499 12:32:57.250809 [0] AVG Duty = 5047%(X100)
2500 12:32:57.250904
2501 12:32:57.256834 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2502 12:32:57.256917
2503 12:32:57.260588 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2504 12:32:57.263629 [DutyScan_Calibration_Flow] ====Done====
2505 12:32:57.266724 nWR fixed to 30
2506 12:32:57.266807 [ModeRegInit_LP4] CH0 RK0
2507 12:32:57.270653 [ModeRegInit_LP4] CH0 RK1
2508 12:32:57.273902 [ModeRegInit_LP4] CH1 RK0
2509 12:32:57.277119 [ModeRegInit_LP4] CH1 RK1
2510 12:32:57.277203 match AC timing 7
2511 12:32:57.280485 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2512 12:32:57.283778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2513 12:32:57.290270 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2514 12:32:57.297151 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2515 12:32:57.300495 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2516 12:32:57.300588 ==
2517 12:32:57.303685 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 12:32:57.306979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 12:32:57.307083 ==
2520 12:32:57.313435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2521 12:32:57.320312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2522 12:32:57.327518 [CA 0] Center 39 (8~70) winsize 63
2523 12:32:57.330828 [CA 1] Center 39 (8~70) winsize 63
2524 12:32:57.334202 [CA 2] Center 35 (5~66) winsize 62
2525 12:32:57.337495 [CA 3] Center 34 (4~65) winsize 62
2526 12:32:57.340736 [CA 4] Center 33 (3~64) winsize 62
2527 12:32:57.344163 [CA 5] Center 32 (3~62) winsize 60
2528 12:32:57.344246
2529 12:32:57.347613 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2530 12:32:57.347723
2531 12:32:57.350843 [CATrainingPosCal] consider 1 rank data
2532 12:32:57.354217 u2DelayCellTimex100 = 270/100 ps
2533 12:32:57.357559 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2534 12:32:57.360579 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2535 12:32:57.367414 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2536 12:32:57.370626 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2537 12:32:57.374279 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2538 12:32:57.377378 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2539 12:32:57.377509
2540 12:32:57.380722 CA PerBit enable=1, Macro0, CA PI delay=32
2541 12:32:57.380821
2542 12:32:57.383790 [CBTSetCACLKResult] CA Dly = 32
2543 12:32:57.383889 CS Dly: 6 (0~37)
2544 12:32:57.383981 ==
2545 12:32:57.387157 Dram Type= 6, Freq= 0, CH_0, rank 1
2546 12:32:57.393818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 12:32:57.393920 ==
2548 12:32:57.397593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2549 12:32:57.403829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2550 12:32:57.413140 [CA 0] Center 38 (8~69) winsize 62
2551 12:32:57.416351 [CA 1] Center 38 (8~69) winsize 62
2552 12:32:57.419515 [CA 2] Center 35 (5~66) winsize 62
2553 12:32:57.423269 [CA 3] Center 34 (4~65) winsize 62
2554 12:32:57.426676 [CA 4] Center 33 (3~64) winsize 62
2555 12:32:57.429960 [CA 5] Center 32 (3~62) winsize 60
2556 12:32:57.430059
2557 12:32:57.433269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2558 12:32:57.433370
2559 12:32:57.436461 [CATrainingPosCal] consider 2 rank data
2560 12:32:57.439870 u2DelayCellTimex100 = 270/100 ps
2561 12:32:57.443173 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2562 12:32:57.446488 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2563 12:32:57.453239 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2564 12:32:57.456591 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2565 12:32:57.459315 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2566 12:32:57.462746 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2567 12:32:57.462852
2568 12:32:57.466456 CA PerBit enable=1, Macro0, CA PI delay=32
2569 12:32:57.466553
2570 12:32:57.469718 [CBTSetCACLKResult] CA Dly = 32
2571 12:32:57.469816 CS Dly: 6 (0~38)
2572 12:32:57.469906
2573 12:32:57.472874 ----->DramcWriteLeveling(PI) begin...
2574 12:32:57.476485 ==
2575 12:32:57.476589 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 12:32:57.482877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 12:32:57.482980 ==
2578 12:32:57.486549 Write leveling (Byte 0): 32 => 32
2579 12:32:57.489721 Write leveling (Byte 1): 27 => 27
2580 12:32:57.489829 DramcWriteLeveling(PI) end<-----
2581 12:32:57.492882
2582 12:32:57.492959 ==
2583 12:32:57.496223 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 12:32:57.499630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 12:32:57.499741 ==
2586 12:32:57.503510 [Gating] SW mode calibration
2587 12:32:57.510085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2588 12:32:57.513273 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2589 12:32:57.520104 0 15 0 | B1->B0 | 2322 3232 | 1 0 | (0 0) (0 0)
2590 12:32:57.523095 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2591 12:32:57.526799 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 12:32:57.533192 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 12:32:57.536451 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 12:32:57.539847 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 12:32:57.546568 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2596 12:32:57.549998 0 15 28 | B1->B0 | 3333 2424 | 1 1 | (1 1) (1 1)
2597 12:32:57.553341 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2598 12:32:57.556578 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 12:32:57.563503 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 12:32:57.566865 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 12:32:57.570168 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 12:32:57.576802 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:32:57.580568 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2604 12:32:57.583581 1 0 28 | B1->B0 | 2525 4343 | 0 0 | (0 0) (0 0)
2605 12:32:57.590331 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2606 12:32:57.593449 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 12:32:57.596664 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 12:32:57.603741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 12:32:57.606416 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 12:32:57.609760 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 12:32:57.616503 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 12:32:57.620312 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2613 12:32:57.623532 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2614 12:32:57.630199 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:32:57.633395 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:32:57.636381 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:32:57.643466 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:32:57.646809 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:32:57.650217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:32:57.656893 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:32:57.660209 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:32:57.663638 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:32:57.667040 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:32:57.673644 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:32:57.676967 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:32:57.680339 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:32:57.686803 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:32:57.689945 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2629 12:32:57.693238 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2630 12:32:57.696980 Total UI for P1: 0, mck2ui 16
2631 12:32:57.700155 best dqsien dly found for B0: ( 1, 3, 28)
2632 12:32:57.706551 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 12:32:57.706654 Total UI for P1: 0, mck2ui 16
2634 12:32:57.713768 best dqsien dly found for B1: ( 1, 4, 0)
2635 12:32:57.716464 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2636 12:32:57.719761 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2637 12:32:57.719864
2638 12:32:57.723678 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2639 12:32:57.726851 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2640 12:32:57.730105 [Gating] SW calibration Done
2641 12:32:57.730211 ==
2642 12:32:57.733340 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 12:32:57.736532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 12:32:57.736630 ==
2645 12:32:57.739704 RX Vref Scan: 0
2646 12:32:57.739809
2647 12:32:57.739902 RX Vref 0 -> 0, step: 1
2648 12:32:57.739991
2649 12:32:57.743436 RX Delay -40 -> 252, step: 8
2650 12:32:57.746691 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2651 12:32:57.753334 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2652 12:32:57.756854 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2653 12:32:57.760232 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2654 12:32:57.763633 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2655 12:32:57.766379 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2656 12:32:57.773734 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2657 12:32:57.776436 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2658 12:32:57.779741 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2659 12:32:57.783323 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2660 12:32:57.786585 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2661 12:32:57.792919 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2662 12:32:57.796260 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2663 12:32:57.799555 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2664 12:32:57.803441 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2665 12:32:57.806460 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2666 12:32:57.806544 ==
2667 12:32:57.810159 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 12:32:57.816594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 12:32:57.816680 ==
2670 12:32:57.816748 DQS Delay:
2671 12:32:57.819707 DQS0 = 0, DQS1 = 0
2672 12:32:57.819792 DQM Delay:
2673 12:32:57.822951 DQM0 = 121, DQM1 = 112
2674 12:32:57.823061 DQ Delay:
2675 12:32:57.826153 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2676 12:32:57.829406 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2677 12:32:57.833264 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2678 12:32:57.836369 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2679 12:32:57.836489
2680 12:32:57.836568
2681 12:32:57.836632 ==
2682 12:32:57.839479 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 12:32:57.846546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 12:32:57.846632 ==
2685 12:32:57.846699
2686 12:32:57.846760
2687 12:32:57.846819 TX Vref Scan disable
2688 12:32:57.849696 == TX Byte 0 ==
2689 12:32:57.852794 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2690 12:32:57.856747 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2691 12:32:57.860244 == TX Byte 1 ==
2692 12:32:57.863519 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2693 12:32:57.866231 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2694 12:32:57.870246 ==
2695 12:32:57.870322 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 12:32:57.876765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 12:32:57.876867 ==
2698 12:32:57.888163 TX Vref=22, minBit 0, minWin=25, winSum=408
2699 12:32:57.891219 TX Vref=24, minBit 0, minWin=25, winSum=413
2700 12:32:57.894587 TX Vref=26, minBit 7, minWin=25, winSum=421
2701 12:32:57.897933 TX Vref=28, minBit 10, minWin=25, winSum=426
2702 12:32:57.901211 TX Vref=30, minBit 0, minWin=26, winSum=427
2703 12:32:57.904559 TX Vref=32, minBit 0, minWin=26, winSum=426
2704 12:32:57.911121 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
2705 12:32:57.911205
2706 12:32:57.914398 Final TX Range 1 Vref 30
2707 12:32:57.914482
2708 12:32:57.914548 ==
2709 12:32:57.918048 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 12:32:57.921379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 12:32:57.921484 ==
2712 12:32:57.921563
2713 12:32:57.921632
2714 12:32:57.924567 TX Vref Scan disable
2715 12:32:57.928440 == TX Byte 0 ==
2716 12:32:57.931601 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2717 12:32:57.934821 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2718 12:32:57.938115 == TX Byte 1 ==
2719 12:32:57.941307 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2720 12:32:57.944574 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2721 12:32:57.944658
2722 12:32:57.948137 [DATLAT]
2723 12:32:57.948262 Freq=1200, CH0 RK0
2724 12:32:57.948388
2725 12:32:57.951428 DATLAT Default: 0xd
2726 12:32:57.951512 0, 0xFFFF, sum = 0
2727 12:32:57.954971 1, 0xFFFF, sum = 0
2728 12:32:57.955053 2, 0xFFFF, sum = 0
2729 12:32:57.958170 3, 0xFFFF, sum = 0
2730 12:32:57.958243 4, 0xFFFF, sum = 0
2731 12:32:57.961470 5, 0xFFFF, sum = 0
2732 12:32:57.961591 6, 0xFFFF, sum = 0
2733 12:32:57.964899 7, 0xFFFF, sum = 0
2734 12:32:57.964992 8, 0xFFFF, sum = 0
2735 12:32:57.968217 9, 0xFFFF, sum = 0
2736 12:32:57.968290 10, 0xFFFF, sum = 0
2737 12:32:57.971551 11, 0xFFFF, sum = 0
2738 12:32:57.971623 12, 0x0, sum = 1
2739 12:32:57.974988 13, 0x0, sum = 2
2740 12:32:57.975074 14, 0x0, sum = 3
2741 12:32:57.978552 15, 0x0, sum = 4
2742 12:32:57.978638 best_step = 13
2743 12:32:57.978701
2744 12:32:57.978765 ==
2745 12:32:57.981924 Dram Type= 6, Freq= 0, CH_0, rank 0
2746 12:32:57.988584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2747 12:32:57.988684 ==
2748 12:32:57.988751 RX Vref Scan: 1
2749 12:32:57.988812
2750 12:32:57.991917 Set Vref Range= 32 -> 127
2751 12:32:57.991993
2752 12:32:57.995286 RX Vref 32 -> 127, step: 1
2753 12:32:57.995395
2754 12:32:57.995456 RX Delay -13 -> 252, step: 4
2755 12:32:57.998603
2756 12:32:57.998673 Set Vref, RX VrefLevel [Byte0]: 32
2757 12:32:58.001776 [Byte1]: 32
2758 12:32:58.005864
2759 12:32:58.005937 Set Vref, RX VrefLevel [Byte0]: 33
2760 12:32:58.009324 [Byte1]: 33
2761 12:32:58.013955
2762 12:32:58.014038 Set Vref, RX VrefLevel [Byte0]: 34
2763 12:32:58.017066 [Byte1]: 34
2764 12:32:58.021677
2765 12:32:58.021760 Set Vref, RX VrefLevel [Byte0]: 35
2766 12:32:58.025239 [Byte1]: 35
2767 12:32:58.029931
2768 12:32:58.030005 Set Vref, RX VrefLevel [Byte0]: 36
2769 12:32:58.033223 [Byte1]: 36
2770 12:32:58.037823
2771 12:32:58.037896 Set Vref, RX VrefLevel [Byte0]: 37
2772 12:32:58.040968 [Byte1]: 37
2773 12:32:58.045481
2774 12:32:58.045564 Set Vref, RX VrefLevel [Byte0]: 38
2775 12:32:58.048650 [Byte1]: 38
2776 12:32:58.053560
2777 12:32:58.053668 Set Vref, RX VrefLevel [Byte0]: 39
2778 12:32:58.056733 [Byte1]: 39
2779 12:32:58.061193
2780 12:32:58.061306 Set Vref, RX VrefLevel [Byte0]: 40
2781 12:32:58.064924 [Byte1]: 40
2782 12:32:58.069523
2783 12:32:58.069606 Set Vref, RX VrefLevel [Byte0]: 41
2784 12:32:58.072771 [Byte1]: 41
2785 12:32:58.077580
2786 12:32:58.077663 Set Vref, RX VrefLevel [Byte0]: 42
2787 12:32:58.080275 [Byte1]: 42
2788 12:32:58.084863
2789 12:32:58.084947 Set Vref, RX VrefLevel [Byte0]: 43
2790 12:32:58.088071 [Byte1]: 43
2791 12:32:58.092675
2792 12:32:58.092784 Set Vref, RX VrefLevel [Byte0]: 44
2793 12:32:58.095945 [Byte1]: 44
2794 12:32:58.100887
2795 12:32:58.100969 Set Vref, RX VrefLevel [Byte0]: 45
2796 12:32:58.103995 [Byte1]: 45
2797 12:32:58.108648
2798 12:32:58.108731 Set Vref, RX VrefLevel [Byte0]: 46
2799 12:32:58.112179 [Byte1]: 46
2800 12:32:58.116871
2801 12:32:58.116954 Set Vref, RX VrefLevel [Byte0]: 47
2802 12:32:58.120271 [Byte1]: 47
2803 12:32:58.124698
2804 12:32:58.124781 Set Vref, RX VrefLevel [Byte0]: 48
2805 12:32:58.127845 [Byte1]: 48
2806 12:32:58.132185
2807 12:32:58.132267 Set Vref, RX VrefLevel [Byte0]: 49
2808 12:32:58.135499 [Byte1]: 49
2809 12:32:58.140138
2810 12:32:58.140224 Set Vref, RX VrefLevel [Byte0]: 50
2811 12:32:58.143330 [Byte1]: 50
2812 12:32:58.148118
2813 12:32:58.148201 Set Vref, RX VrefLevel [Byte0]: 51
2814 12:32:58.151235 [Byte1]: 51
2815 12:32:58.156352
2816 12:32:58.156435 Set Vref, RX VrefLevel [Byte0]: 52
2817 12:32:58.159450 [Byte1]: 52
2818 12:32:58.163831
2819 12:32:58.163915 Set Vref, RX VrefLevel [Byte0]: 53
2820 12:32:58.167474 [Byte1]: 53
2821 12:32:58.171866
2822 12:32:58.171962 Set Vref, RX VrefLevel [Byte0]: 54
2823 12:32:58.175450 [Byte1]: 54
2824 12:32:58.179493
2825 12:32:58.179577 Set Vref, RX VrefLevel [Byte0]: 55
2826 12:32:58.182930 [Byte1]: 55
2827 12:32:58.187571
2828 12:32:58.187654 Set Vref, RX VrefLevel [Byte0]: 56
2829 12:32:58.190995 [Byte1]: 56
2830 12:32:58.195346
2831 12:32:58.195431 Set Vref, RX VrefLevel [Byte0]: 57
2832 12:32:58.198622 [Byte1]: 57
2833 12:32:58.203471
2834 12:32:58.203553 Set Vref, RX VrefLevel [Byte0]: 58
2835 12:32:58.206724 [Byte1]: 58
2836 12:32:58.211332
2837 12:32:58.211450 Set Vref, RX VrefLevel [Byte0]: 59
2838 12:32:58.214693 [Byte1]: 59
2839 12:32:58.219293
2840 12:32:58.219409 Set Vref, RX VrefLevel [Byte0]: 60
2841 12:32:58.222752 [Byte1]: 60
2842 12:32:58.227274
2843 12:32:58.227397 Set Vref, RX VrefLevel [Byte0]: 61
2844 12:32:58.230500 [Byte1]: 61
2845 12:32:58.234974
2846 12:32:58.235077 Set Vref, RX VrefLevel [Byte0]: 62
2847 12:32:58.238016 [Byte1]: 62
2848 12:32:58.242712
2849 12:32:58.242809 Set Vref, RX VrefLevel [Byte0]: 63
2850 12:32:58.246016 [Byte1]: 63
2851 12:32:58.250551
2852 12:32:58.250634 Set Vref, RX VrefLevel [Byte0]: 64
2853 12:32:58.253878 [Byte1]: 64
2854 12:32:58.258337
2855 12:32:58.258421 Set Vref, RX VrefLevel [Byte0]: 65
2856 12:32:58.262191 [Byte1]: 65
2857 12:32:58.266516
2858 12:32:58.266599 Set Vref, RX VrefLevel [Byte0]: 66
2859 12:32:58.269697 [Byte1]: 66
2860 12:32:58.274597
2861 12:32:58.274687 Set Vref, RX VrefLevel [Byte0]: 67
2862 12:32:58.277668 [Byte1]: 67
2863 12:32:58.281978
2864 12:32:58.282061 Set Vref, RX VrefLevel [Byte0]: 68
2865 12:32:58.285745 [Byte1]: 68
2866 12:32:58.290432
2867 12:32:58.290515 Set Vref, RX VrefLevel [Byte0]: 69
2868 12:32:58.293176 [Byte1]: 69
2869 12:32:58.297732
2870 12:32:58.297815 Set Vref, RX VrefLevel [Byte0]: 70
2871 12:32:58.301579 [Byte1]: 70
2872 12:32:58.305663
2873 12:32:58.305750 Set Vref, RX VrefLevel [Byte0]: 71
2874 12:32:58.309018 [Byte1]: 71
2875 12:32:58.313542
2876 12:32:58.313625 Set Vref, RX VrefLevel [Byte0]: 72
2877 12:32:58.316938 [Byte1]: 72
2878 12:32:58.321733
2879 12:32:58.321816 Final RX Vref Byte 0 = 55 to rank0
2880 12:32:58.325050 Final RX Vref Byte 1 = 55 to rank0
2881 12:32:58.328486 Final RX Vref Byte 0 = 55 to rank1
2882 12:32:58.331884 Final RX Vref Byte 1 = 55 to rank1==
2883 12:32:58.335057 Dram Type= 6, Freq= 0, CH_0, rank 0
2884 12:32:58.338696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 12:32:58.341663 ==
2886 12:32:58.341738 DQS Delay:
2887 12:32:58.341802 DQS0 = 0, DQS1 = 0
2888 12:32:58.344878 DQM Delay:
2889 12:32:58.344953 DQM0 = 120, DQM1 = 113
2890 12:32:58.348656 DQ Delay:
2891 12:32:58.351854 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2892 12:32:58.355242 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2893 12:32:58.358548 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2894 12:32:58.361898 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =124
2895 12:32:58.362010
2896 12:32:58.362134
2897 12:32:58.368262 [DQSOSCAuto] RK0, (LSB)MR18= 0x120c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2898 12:32:58.372013 CH0 RK0: MR19=404, MR18=120C
2899 12:32:58.378948 CH0_RK0: MR19=0x404, MR18=0x120C, DQSOSC=403, MR23=63, INC=40, DEC=26
2900 12:32:58.379056
2901 12:32:58.381811 ----->DramcWriteLeveling(PI) begin...
2902 12:32:58.381918 ==
2903 12:32:58.385060 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 12:32:58.388912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 12:32:58.389019 ==
2906 12:32:58.391986 Write leveling (Byte 0): 34 => 34
2907 12:32:58.395208 Write leveling (Byte 1): 28 => 28
2908 12:32:58.398648 DramcWriteLeveling(PI) end<-----
2909 12:32:58.398753
2910 12:32:58.398858 ==
2911 12:32:58.401993 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:32:58.408507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:32:58.408664 ==
2914 12:32:58.408767 [Gating] SW mode calibration
2915 12:32:58.418896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2916 12:32:58.422234 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2917 12:32:58.425594 0 15 0 | B1->B0 | 3131 2c2c | 1 0 | (1 1) (0 0)
2918 12:32:58.431785 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 12:32:58.435099 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 12:32:58.438431 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 12:32:58.445461 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 12:32:58.448579 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 12:32:58.452273 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2924 12:32:58.458746 0 15 28 | B1->B0 | 3131 2d2d | 0 0 | (1 0) (0 1)
2925 12:32:58.462195 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 12:32:58.465601 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 12:32:58.472137 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 12:32:58.475444 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 12:32:58.478554 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 12:32:58.485528 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 12:32:58.488743 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 12:32:58.492355 1 0 28 | B1->B0 | 3939 3938 | 1 1 | (0 0) (0 0)
2933 12:32:58.495438 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2934 12:32:58.502378 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 12:32:58.505815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 12:32:58.509045 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 12:32:58.515827 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 12:32:58.518461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 12:32:58.522393 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 12:32:58.528495 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2941 12:32:58.531921 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:32:58.535296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:32:58.541942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:32:58.545204 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:32:58.548952 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:32:58.555394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:32:58.559184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:32:58.562269 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:32:58.569010 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:32:58.572464 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:32:58.575845 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:32:58.582344 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:32:58.585697 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:32:58.588764 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:32:58.592334 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:32:58.598615 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2957 12:32:58.602364 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2958 12:32:58.605382 Total UI for P1: 0, mck2ui 16
2959 12:32:58.608534 best dqsien dly found for B1: ( 1, 3, 28)
2960 12:32:58.612160 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 12:32:58.615480 Total UI for P1: 0, mck2ui 16
2962 12:32:58.618784 best dqsien dly found for B0: ( 1, 3, 30)
2963 12:32:58.622105 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2964 12:32:58.625345 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2965 12:32:58.628753
2966 12:32:58.632204 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2967 12:32:58.635001 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2968 12:32:58.638366 [Gating] SW calibration Done
2969 12:32:58.638448 ==
2970 12:32:58.641637 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 12:32:58.645033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 12:32:58.645116 ==
2973 12:32:58.645181 RX Vref Scan: 0
2974 12:32:58.645242
2975 12:32:58.648358 RX Vref 0 -> 0, step: 1
2976 12:32:58.648525
2977 12:32:58.651561 RX Delay -40 -> 252, step: 8
2978 12:32:58.655397 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2979 12:32:58.658599 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2980 12:32:58.665107 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2981 12:32:58.668817 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2982 12:32:58.672182 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2983 12:32:58.675524 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2984 12:32:58.678300 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2985 12:32:58.685420 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2986 12:32:58.688636 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
2987 12:32:58.691848 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2988 12:32:58.695162 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2989 12:32:58.698345 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2990 12:32:58.705075 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2991 12:32:58.708838 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2992 12:32:58.712003 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2993 12:32:58.715034 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2994 12:32:58.715133 ==
2995 12:32:58.718467 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 12:32:58.722200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 12:32:58.725437 ==
2998 12:32:58.725556 DQS Delay:
2999 12:32:58.725708 DQS0 = 0, DQS1 = 0
3000 12:32:58.728656 DQM Delay:
3001 12:32:58.728771 DQM0 = 122, DQM1 = 114
3002 12:32:58.731856 DQ Delay:
3003 12:32:58.735210 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
3004 12:32:58.738497 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
3005 12:32:58.741882 DQ8 =107, DQ9 =103, DQ10 =115, DQ11 =107
3006 12:32:58.745308 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
3007 12:32:58.745418
3008 12:32:58.745513
3009 12:32:58.745605 ==
3010 12:32:58.748857 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 12:32:58.752199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 12:32:58.752302 ==
3013 12:32:58.752394
3014 12:32:58.752484
3015 12:32:58.755622 TX Vref Scan disable
3016 12:32:58.758819 == TX Byte 0 ==
3017 12:32:58.761910 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3018 12:32:58.765161 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3019 12:32:58.769016 == TX Byte 1 ==
3020 12:32:58.772274 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3021 12:32:58.775514 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3022 12:32:58.775620 ==
3023 12:32:58.778875 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 12:32:58.785456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 12:32:58.785564 ==
3026 12:32:58.795947 TX Vref=22, minBit 5, minWin=24, winSum=408
3027 12:32:58.799257 TX Vref=24, minBit 10, minWin=25, winSum=419
3028 12:32:58.803152 TX Vref=26, minBit 1, minWin=24, winSum=416
3029 12:32:58.806286 TX Vref=28, minBit 10, minWin=25, winSum=422
3030 12:32:58.809436 TX Vref=30, minBit 1, minWin=26, winSum=429
3031 12:32:58.816219 TX Vref=32, minBit 0, minWin=26, winSum=420
3032 12:32:58.819821 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3033 12:32:58.819929
3034 12:32:58.822872 Final TX Range 1 Vref 30
3035 12:32:58.822973
3036 12:32:58.823064 ==
3037 12:32:58.826182 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 12:32:58.829205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 12:32:58.829277 ==
3040 12:32:58.832970
3041 12:32:58.833072
3042 12:32:58.833166 TX Vref Scan disable
3043 12:32:58.836284 == TX Byte 0 ==
3044 12:32:58.839696 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3045 12:32:58.842981 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3046 12:32:58.846405 == TX Byte 1 ==
3047 12:32:58.849766 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3048 12:32:58.853057 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3049 12:32:58.856438
3050 12:32:58.856536 [DATLAT]
3051 12:32:58.856630 Freq=1200, CH0 RK1
3052 12:32:58.856722
3053 12:32:58.859782 DATLAT Default: 0xd
3054 12:32:58.859878 0, 0xFFFF, sum = 0
3055 12:32:58.863127 1, 0xFFFF, sum = 0
3056 12:32:58.863235 2, 0xFFFF, sum = 0
3057 12:32:58.866387 3, 0xFFFF, sum = 0
3058 12:32:58.866488 4, 0xFFFF, sum = 0
3059 12:32:58.869599 5, 0xFFFF, sum = 0
3060 12:32:58.869699 6, 0xFFFF, sum = 0
3061 12:32:58.872721 7, 0xFFFF, sum = 0
3062 12:32:58.876552 8, 0xFFFF, sum = 0
3063 12:32:58.876654 9, 0xFFFF, sum = 0
3064 12:32:58.879816 10, 0xFFFF, sum = 0
3065 12:32:58.879919 11, 0xFFFF, sum = 0
3066 12:32:58.882991 12, 0x0, sum = 1
3067 12:32:58.883091 13, 0x0, sum = 2
3068 12:32:58.886300 14, 0x0, sum = 3
3069 12:32:58.886403 15, 0x0, sum = 4
3070 12:32:58.886498 best_step = 13
3071 12:32:58.886592
3072 12:32:58.889758 ==
3073 12:32:58.893013 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 12:32:58.896257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 12:32:58.896361 ==
3076 12:32:58.896454 RX Vref Scan: 0
3077 12:32:58.896543
3078 12:32:58.899483 RX Vref 0 -> 0, step: 1
3079 12:32:58.899560
3080 12:32:58.902777 RX Delay -13 -> 252, step: 4
3081 12:32:58.906213 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3082 12:32:58.909488 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3083 12:32:58.916420 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3084 12:32:58.919522 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3085 12:32:58.923360 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3086 12:32:58.926269 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3087 12:32:58.929519 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3088 12:32:58.936387 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3089 12:32:58.939440 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3090 12:32:58.943095 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3091 12:32:58.946425 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3092 12:32:58.949875 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3093 12:32:58.956673 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3094 12:32:58.959508 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3095 12:32:58.962897 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3096 12:32:58.966343 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3097 12:32:58.966463 ==
3098 12:32:58.969638 Dram Type= 6, Freq= 0, CH_0, rank 1
3099 12:32:58.976574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 12:32:58.976699 ==
3101 12:32:58.976795 DQS Delay:
3102 12:32:58.976906 DQS0 = 0, DQS1 = 0
3103 12:32:58.979715 DQM Delay:
3104 12:32:58.979826 DQM0 = 120, DQM1 = 111
3105 12:32:58.982946 DQ Delay:
3106 12:32:58.986754 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3107 12:32:58.990132 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3108 12:32:58.993489 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3109 12:32:58.996732 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3110 12:32:58.996841
3111 12:32:58.996950
3112 12:32:59.006645 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3113 12:32:59.006758 CH0 RK1: MR19=403, MR18=10F1
3114 12:32:59.013510 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3115 12:32:59.016684 [RxdqsGatingPostProcess] freq 1200
3116 12:32:59.023264 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3117 12:32:59.026452 best DQS0 dly(2T, 0.5T) = (0, 11)
3118 12:32:59.029963 best DQS1 dly(2T, 0.5T) = (0, 12)
3119 12:32:59.030073 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3120 12:32:59.033204 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3121 12:32:59.036242 best DQS0 dly(2T, 0.5T) = (0, 11)
3122 12:32:59.039992 best DQS1 dly(2T, 0.5T) = (0, 11)
3123 12:32:59.043268 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3124 12:32:59.046387 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3125 12:32:59.050113 Pre-setting of DQS Precalculation
3126 12:32:59.056819 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3127 12:32:59.056904 ==
3128 12:32:59.060220 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 12:32:59.063497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 12:32:59.063582 ==
3131 12:32:59.070125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3132 12:32:59.073459 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3133 12:32:59.083173 [CA 0] Center 37 (7~68) winsize 62
3134 12:32:59.086155 [CA 1] Center 37 (7~68) winsize 62
3135 12:32:59.089361 [CA 2] Center 35 (5~65) winsize 61
3136 12:32:59.092516 [CA 3] Center 34 (4~64) winsize 61
3137 12:32:59.096371 [CA 4] Center 34 (4~64) winsize 61
3138 12:32:59.099783 [CA 5] Center 33 (4~63) winsize 60
3139 12:32:59.099867
3140 12:32:59.103145 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3141 12:32:59.103229
3142 12:32:59.106485 [CATrainingPosCal] consider 1 rank data
3143 12:32:59.109788 u2DelayCellTimex100 = 270/100 ps
3144 12:32:59.113207 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3145 12:32:59.116519 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3146 12:32:59.119803 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3147 12:32:59.126272 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 12:32:59.129659 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 12:32:59.132931 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3150 12:32:59.133036
3151 12:32:59.136655 CA PerBit enable=1, Macro0, CA PI delay=33
3152 12:32:59.136756
3153 12:32:59.139758 [CBTSetCACLKResult] CA Dly = 33
3154 12:32:59.139877 CS Dly: 8 (0~39)
3155 12:32:59.139979 ==
3156 12:32:59.142864 Dram Type= 6, Freq= 0, CH_1, rank 1
3157 12:32:59.149735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 12:32:59.149843 ==
3159 12:32:59.153505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3160 12:32:59.159735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3161 12:32:59.168357 [CA 0] Center 37 (7~68) winsize 62
3162 12:32:59.172103 [CA 1] Center 38 (7~69) winsize 63
3163 12:32:59.174819 [CA 2] Center 35 (5~65) winsize 61
3164 12:32:59.178866 [CA 3] Center 34 (4~65) winsize 62
3165 12:32:59.181698 [CA 4] Center 34 (4~65) winsize 62
3166 12:32:59.184967 [CA 5] Center 33 (4~63) winsize 60
3167 12:32:59.185074
3168 12:32:59.188251 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3169 12:32:59.188354
3170 12:32:59.192041 [CATrainingPosCal] consider 2 rank data
3171 12:32:59.195188 u2DelayCellTimex100 = 270/100 ps
3172 12:32:59.198397 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3173 12:32:59.202209 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3174 12:32:59.205397 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3175 12:32:59.212021 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 12:32:59.215176 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3177 12:32:59.218523 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3178 12:32:59.218633
3179 12:32:59.221887 CA PerBit enable=1, Macro0, CA PI delay=33
3180 12:32:59.221995
3181 12:32:59.225074 [CBTSetCACLKResult] CA Dly = 33
3182 12:32:59.225157 CS Dly: 9 (0~41)
3183 12:32:59.225220
3184 12:32:59.228333 ----->DramcWriteLeveling(PI) begin...
3185 12:32:59.228424 ==
3186 12:32:59.231716 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 12:32:59.238525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 12:32:59.238612 ==
3189 12:32:59.241732 Write leveling (Byte 0): 26 => 26
3190 12:32:59.245555 Write leveling (Byte 1): 30 => 30
3191 12:32:59.248554 DramcWriteLeveling(PI) end<-----
3192 12:32:59.248638
3193 12:32:59.248705 ==
3194 12:32:59.251651 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 12:32:59.255449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 12:32:59.255534 ==
3197 12:32:59.258479 [Gating] SW mode calibration
3198 12:32:59.265323 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3199 12:32:59.268393 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3200 12:32:59.275726 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 12:32:59.279035 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 12:32:59.282379 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 12:32:59.288922 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 12:32:59.292402 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 12:32:59.295007 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 12:32:59.301912 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
3207 12:32:59.305645 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 12:32:59.308706 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 12:32:59.315012 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 12:32:59.318362 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 12:32:59.322142 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 12:32:59.328763 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 12:32:59.331905 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3214 12:32:59.335295 1 0 24 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
3215 12:32:59.338602 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 12:32:59.345417 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 12:32:59.348743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 12:32:59.352193 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 12:32:59.358586 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 12:32:59.362258 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 12:32:59.365403 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 12:32:59.372349 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3223 12:32:59.375508 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:32:59.378832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:32:59.385394 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:32:59.388896 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:32:59.392178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:32:59.398786 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:32:59.402113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:32:59.405403 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:32:59.411870 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:32:59.415528 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:32:59.418653 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:32:59.425890 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:32:59.428882 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:32:59.432198 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:32:59.435447 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:32:59.442039 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3239 12:32:59.445542 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 12:32:59.448840 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 12:32:59.452031 Total UI for P1: 0, mck2ui 16
3242 12:32:59.455296 best dqsien dly found for B0: ( 1, 3, 26)
3243 12:32:59.458670 Total UI for P1: 0, mck2ui 16
3244 12:32:59.461922 best dqsien dly found for B1: ( 1, 3, 26)
3245 12:32:59.465679 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3246 12:32:59.468844 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3247 12:32:59.468927
3248 12:32:59.475169 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3249 12:32:59.478964 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3250 12:32:59.482107 [Gating] SW calibration Done
3251 12:32:59.482219 ==
3252 12:32:59.485299 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 12:32:59.488642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 12:32:59.488724 ==
3255 12:32:59.488787 RX Vref Scan: 0
3256 12:32:59.488848
3257 12:32:59.492049 RX Vref 0 -> 0, step: 1
3258 12:32:59.492138
3259 12:32:59.495279 RX Delay -40 -> 252, step: 8
3260 12:32:59.498657 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3261 12:32:59.502039 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3262 12:32:59.505380 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3263 12:32:59.511938 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3264 12:32:59.515746 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3265 12:32:59.519108 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3266 12:32:59.522416 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3267 12:32:59.525407 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3268 12:32:59.532283 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3269 12:32:59.535554 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3270 12:32:59.538716 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3271 12:32:59.542350 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3272 12:32:59.545751 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3273 12:32:59.552693 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3274 12:32:59.555784 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3275 12:32:59.559167 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3276 12:32:59.559248 ==
3277 12:32:59.562551 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 12:32:59.565907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 12:32:59.565989 ==
3280 12:32:59.569093 DQS Delay:
3281 12:32:59.569182 DQS0 = 0, DQS1 = 0
3282 12:32:59.572395 DQM Delay:
3283 12:32:59.572477 DQM0 = 119, DQM1 = 117
3284 12:32:59.572541 DQ Delay:
3285 12:32:59.579322 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3286 12:32:59.582501 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3287 12:32:59.585805 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =111
3288 12:32:59.588907 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3289 12:32:59.588990
3290 12:32:59.589054
3291 12:32:59.589115 ==
3292 12:32:59.592239 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 12:32:59.595600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 12:32:59.595682 ==
3295 12:32:59.595747
3296 12:32:59.595805
3297 12:32:59.599048 TX Vref Scan disable
3298 12:32:59.602344 == TX Byte 0 ==
3299 12:32:59.605713 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3300 12:32:59.609180 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3301 12:32:59.612422 == TX Byte 1 ==
3302 12:32:59.615730 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3303 12:32:59.618954 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3304 12:32:59.619037 ==
3305 12:32:59.622217 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 12:32:59.625566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 12:32:59.628869 ==
3308 12:32:59.639066 TX Vref=22, minBit 9, minWin=24, winSum=412
3309 12:32:59.642429 TX Vref=24, minBit 9, minWin=25, winSum=417
3310 12:32:59.645497 TX Vref=26, minBit 9, minWin=25, winSum=426
3311 12:32:59.649209 TX Vref=28, minBit 1, minWin=26, winSum=427
3312 12:32:59.652514 TX Vref=30, minBit 2, minWin=26, winSum=428
3313 12:32:59.655928 TX Vref=32, minBit 9, minWin=26, winSum=432
3314 12:32:59.662213 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3315 12:32:59.662331
3316 12:32:59.665622 Final TX Range 1 Vref 32
3317 12:32:59.665758
3318 12:32:59.665861 ==
3319 12:32:59.668969 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 12:32:59.672208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 12:32:59.672314 ==
3322 12:32:59.672381
3323 12:32:59.675554
3324 12:32:59.675629 TX Vref Scan disable
3325 12:32:59.678736 == TX Byte 0 ==
3326 12:32:59.682399 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3327 12:32:59.686060 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3328 12:32:59.689219 == TX Byte 1 ==
3329 12:32:59.692479 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3330 12:32:59.695456 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3331 12:32:59.695535
3332 12:32:59.699412 [DATLAT]
3333 12:32:59.699501 Freq=1200, CH1 RK0
3334 12:32:59.699566
3335 12:32:59.702143 DATLAT Default: 0xd
3336 12:32:59.702225 0, 0xFFFF, sum = 0
3337 12:32:59.705503 1, 0xFFFF, sum = 0
3338 12:32:59.705581 2, 0xFFFF, sum = 0
3339 12:32:59.708824 3, 0xFFFF, sum = 0
3340 12:32:59.708900 4, 0xFFFF, sum = 0
3341 12:32:59.712213 5, 0xFFFF, sum = 0
3342 12:32:59.712291 6, 0xFFFF, sum = 0
3343 12:32:59.715639 7, 0xFFFF, sum = 0
3344 12:32:59.715720 8, 0xFFFF, sum = 0
3345 12:32:59.719022 9, 0xFFFF, sum = 0
3346 12:32:59.722113 10, 0xFFFF, sum = 0
3347 12:32:59.722254 11, 0xFFFF, sum = 0
3348 12:32:59.725353 12, 0x0, sum = 1
3349 12:32:59.725438 13, 0x0, sum = 2
3350 12:32:59.725504 14, 0x0, sum = 3
3351 12:32:59.728748 15, 0x0, sum = 4
3352 12:32:59.728823 best_step = 13
3353 12:32:59.728927
3354 12:32:59.728986 ==
3355 12:32:59.732124 Dram Type= 6, Freq= 0, CH_1, rank 0
3356 12:32:59.739120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3357 12:32:59.739245 ==
3358 12:32:59.739358 RX Vref Scan: 1
3359 12:32:59.739435
3360 12:32:59.742237 Set Vref Range= 32 -> 127
3361 12:32:59.742312
3362 12:32:59.746284 RX Vref 32 -> 127, step: 1
3363 12:32:59.746362
3364 12:32:59.749450 RX Delay -5 -> 252, step: 4
3365 12:32:59.749533
3366 12:32:59.749638 Set Vref, RX VrefLevel [Byte0]: 32
3367 12:32:59.752714 [Byte1]: 32
3368 12:32:59.757164
3369 12:32:59.757298 Set Vref, RX VrefLevel [Byte0]: 33
3370 12:32:59.760475 [Byte1]: 33
3371 12:32:59.765088
3372 12:32:59.765173 Set Vref, RX VrefLevel [Byte0]: 34
3373 12:32:59.768493 [Byte1]: 34
3374 12:32:59.772582
3375 12:32:59.772664 Set Vref, RX VrefLevel [Byte0]: 35
3376 12:32:59.776382 [Byte1]: 35
3377 12:32:59.780465
3378 12:32:59.780547 Set Vref, RX VrefLevel [Byte0]: 36
3379 12:32:59.784320 [Byte1]: 36
3380 12:32:59.788731
3381 12:32:59.788812 Set Vref, RX VrefLevel [Byte0]: 37
3382 12:32:59.791693 [Byte1]: 37
3383 12:32:59.796080
3384 12:32:59.796191 Set Vref, RX VrefLevel [Byte0]: 38
3385 12:32:59.799849 [Byte1]: 38
3386 12:32:59.804199
3387 12:32:59.804279 Set Vref, RX VrefLevel [Byte0]: 39
3388 12:32:59.807626 [Byte1]: 39
3389 12:32:59.812235
3390 12:32:59.812306 Set Vref, RX VrefLevel [Byte0]: 40
3391 12:32:59.815601 [Byte1]: 40
3392 12:32:59.820348
3393 12:32:59.820417 Set Vref, RX VrefLevel [Byte0]: 41
3394 12:32:59.822929 [Byte1]: 41
3395 12:32:59.828127
3396 12:32:59.828200 Set Vref, RX VrefLevel [Byte0]: 42
3397 12:32:59.831483 [Byte1]: 42
3398 12:32:59.835527
3399 12:32:59.835603 Set Vref, RX VrefLevel [Byte0]: 43
3400 12:32:59.838828 [Byte1]: 43
3401 12:32:59.843320
3402 12:32:59.843431 Set Vref, RX VrefLevel [Byte0]: 44
3403 12:32:59.847395 [Byte1]: 44
3404 12:32:59.851583
3405 12:32:59.851656 Set Vref, RX VrefLevel [Byte0]: 45
3406 12:32:59.854844 [Byte1]: 45
3407 12:32:59.859449
3408 12:32:59.859525 Set Vref, RX VrefLevel [Byte0]: 46
3409 12:32:59.862728 [Byte1]: 46
3410 12:32:59.867097
3411 12:32:59.867178 Set Vref, RX VrefLevel [Byte0]: 47
3412 12:32:59.870301 [Byte1]: 47
3413 12:32:59.875038
3414 12:32:59.875147 Set Vref, RX VrefLevel [Byte0]: 48
3415 12:32:59.878307 [Byte1]: 48
3416 12:32:59.882836
3417 12:32:59.882940 Set Vref, RX VrefLevel [Byte0]: 49
3418 12:32:59.886188 [Byte1]: 49
3419 12:32:59.890934
3420 12:32:59.891035 Set Vref, RX VrefLevel [Byte0]: 50
3421 12:32:59.894150 [Byte1]: 50
3422 12:32:59.898606
3423 12:32:59.898683 Set Vref, RX VrefLevel [Byte0]: 51
3424 12:32:59.901592 [Byte1]: 51
3425 12:32:59.906496
3426 12:32:59.906576 Set Vref, RX VrefLevel [Byte0]: 52
3427 12:32:59.909605 [Byte1]: 52
3428 12:32:59.914151
3429 12:32:59.914238 Set Vref, RX VrefLevel [Byte0]: 53
3430 12:32:59.917349 [Byte1]: 53
3431 12:32:59.921943
3432 12:32:59.922029 Set Vref, RX VrefLevel [Byte0]: 54
3433 12:32:59.925174 [Byte1]: 54
3434 12:32:59.929666
3435 12:32:59.929745 Set Vref, RX VrefLevel [Byte0]: 55
3436 12:32:59.933026 [Byte1]: 55
3437 12:32:59.937862
3438 12:32:59.937937 Set Vref, RX VrefLevel [Byte0]: 56
3439 12:32:59.941213 [Byte1]: 56
3440 12:32:59.945831
3441 12:32:59.945907 Set Vref, RX VrefLevel [Byte0]: 57
3442 12:32:59.948572 [Byte1]: 57
3443 12:32:59.953581
3444 12:32:59.953661 Set Vref, RX VrefLevel [Byte0]: 58
3445 12:32:59.956510 [Byte1]: 58
3446 12:32:59.961406
3447 12:32:59.961487 Set Vref, RX VrefLevel [Byte0]: 59
3448 12:32:59.964714 [Byte1]: 59
3449 12:32:59.969188
3450 12:32:59.969273 Set Vref, RX VrefLevel [Byte0]: 60
3451 12:32:59.972243 [Byte1]: 60
3452 12:32:59.977296
3453 12:32:59.977395 Set Vref, RX VrefLevel [Byte0]: 61
3454 12:32:59.980033 [Byte1]: 61
3455 12:32:59.984976
3456 12:32:59.985065 Set Vref, RX VrefLevel [Byte0]: 62
3457 12:32:59.987769 [Byte1]: 62
3458 12:32:59.992460
3459 12:32:59.992547 Set Vref, RX VrefLevel [Byte0]: 63
3460 12:32:59.996014 [Byte1]: 63
3461 12:33:00.000657
3462 12:33:00.000748 Set Vref, RX VrefLevel [Byte0]: 64
3463 12:33:00.003835 [Byte1]: 64
3464 12:33:00.008488
3465 12:33:00.008584 Set Vref, RX VrefLevel [Byte0]: 65
3466 12:33:00.011690 [Byte1]: 65
3467 12:33:00.016043
3468 12:33:00.016133 Set Vref, RX VrefLevel [Byte0]: 66
3469 12:33:00.019738 [Byte1]: 66
3470 12:33:00.024227
3471 12:33:00.024313 Set Vref, RX VrefLevel [Byte0]: 67
3472 12:33:00.027331 [Byte1]: 67
3473 12:33:00.031875
3474 12:33:00.032014 Set Vref, RX VrefLevel [Byte0]: 68
3475 12:33:00.035149 [Byte1]: 68
3476 12:33:00.039786
3477 12:33:00.039906 Set Vref, RX VrefLevel [Byte0]: 69
3478 12:33:00.043075 [Byte1]: 69
3479 12:33:00.047794
3480 12:33:00.047898 Set Vref, RX VrefLevel [Byte0]: 70
3481 12:33:00.051042 [Byte1]: 70
3482 12:33:00.055702
3483 12:33:00.055809 Final RX Vref Byte 0 = 53 to rank0
3484 12:33:00.058936 Final RX Vref Byte 1 = 48 to rank0
3485 12:33:00.062229 Final RX Vref Byte 0 = 53 to rank1
3486 12:33:00.065414 Final RX Vref Byte 1 = 48 to rank1==
3487 12:33:00.068691 Dram Type= 6, Freq= 0, CH_1, rank 0
3488 12:33:00.075660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 12:33:00.075744 ==
3490 12:33:00.075824 DQS Delay:
3491 12:33:00.075892 DQS0 = 0, DQS1 = 0
3492 12:33:00.078907 DQM Delay:
3493 12:33:00.078991 DQM0 = 120, DQM1 = 116
3494 12:33:00.081935 DQ Delay:
3495 12:33:00.085208 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3496 12:33:00.089022 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3497 12:33:00.091733 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3498 12:33:00.095006 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3499 12:33:00.095137
3500 12:33:00.095232
3501 12:33:00.105261 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3502 12:33:00.105352 CH1 RK0: MR19=404, MR18=316
3503 12:33:00.111776 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3504 12:33:00.111862
3505 12:33:00.115523 ----->DramcWriteLeveling(PI) begin...
3506 12:33:00.115601 ==
3507 12:33:00.118617 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 12:33:00.122272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 12:33:00.125574 ==
3510 12:33:00.125661 Write leveling (Byte 0): 28 => 28
3511 12:33:00.128600 Write leveling (Byte 1): 29 => 29
3512 12:33:00.131636 DramcWriteLeveling(PI) end<-----
3513 12:33:00.131724
3514 12:33:00.131792 ==
3515 12:33:00.135423 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 12:33:00.141865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 12:33:00.141955 ==
3518 12:33:00.142025 [Gating] SW mode calibration
3519 12:33:00.152106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3520 12:33:00.155415 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3521 12:33:00.158859 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 12:33:00.165431 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 12:33:00.168815 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 12:33:00.172131 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 12:33:00.178451 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 12:33:00.182131 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3527 12:33:00.185508 0 15 24 | B1->B0 | 2626 3232 | 1 1 | (1 0) (1 0)
3528 12:33:00.191795 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 12:33:00.194960 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 12:33:00.198276 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 12:33:00.204914 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 12:33:00.208291 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 12:33:00.211738 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 12:33:00.218397 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3535 12:33:00.221565 1 0 24 | B1->B0 | 4141 2a2a | 1 1 | (0 0) (0 0)
3536 12:33:00.225149 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 12:33:00.231528 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 12:33:00.235339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 12:33:00.238473 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 12:33:00.244731 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 12:33:00.248508 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 12:33:00.251918 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3543 12:33:00.258594 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3544 12:33:00.261833 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3545 12:33:00.265298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:33:00.271898 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:33:00.275194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:33:00.278577 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 12:33:00.281624 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 12:33:00.288549 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 12:33:00.291731 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 12:33:00.294924 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 12:33:00.301549 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 12:33:00.304623 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 12:33:00.308041 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 12:33:00.314649 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 12:33:00.317903 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 12:33:00.321250 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3559 12:33:00.327841 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3560 12:33:00.331541 Total UI for P1: 0, mck2ui 16
3561 12:33:00.334698 best dqsien dly found for B1: ( 1, 3, 20)
3562 12:33:00.337773 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3563 12:33:00.341535 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 12:33:00.344721 Total UI for P1: 0, mck2ui 16
3565 12:33:00.348364 best dqsien dly found for B0: ( 1, 3, 26)
3566 12:33:00.351474 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3567 12:33:00.354550 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3568 12:33:00.354638
3569 12:33:00.361227 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3570 12:33:00.364583 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3571 12:33:00.364669 [Gating] SW calibration Done
3572 12:33:00.367905 ==
3573 12:33:00.371185 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 12:33:00.374546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 12:33:00.374631 ==
3576 12:33:00.374698 RX Vref Scan: 0
3577 12:33:00.374760
3578 12:33:00.377858 RX Vref 0 -> 0, step: 1
3579 12:33:00.377941
3580 12:33:00.381141 RX Delay -40 -> 252, step: 8
3581 12:33:00.384657 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3582 12:33:00.387852 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3583 12:33:00.394886 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3584 12:33:00.398013 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3585 12:33:00.401106 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3586 12:33:00.404306 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3587 12:33:00.407548 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3588 12:33:00.411337 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3589 12:33:00.417952 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3590 12:33:00.421286 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3591 12:33:00.424685 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3592 12:33:00.427375 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3593 12:33:00.434539 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3594 12:33:00.437594 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3595 12:33:00.441362 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3596 12:33:00.444513 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3597 12:33:00.444597 ==
3598 12:33:00.447500 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 12:33:00.451038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 12:33:00.454184 ==
3601 12:33:00.454269 DQS Delay:
3602 12:33:00.454335 DQS0 = 0, DQS1 = 0
3603 12:33:00.457395 DQM Delay:
3604 12:33:00.457478 DQM0 = 121, DQM1 = 118
3605 12:33:00.461177 DQ Delay:
3606 12:33:00.464213 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3607 12:33:00.467512 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3608 12:33:00.470838 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3609 12:33:00.474128 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127
3610 12:33:00.474210
3611 12:33:00.474274
3612 12:33:00.474334 ==
3613 12:33:00.477365 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 12:33:00.480731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 12:33:00.480807 ==
3616 12:33:00.480870
3617 12:33:00.483972
3618 12:33:00.484044 TX Vref Scan disable
3619 12:33:00.487283 == TX Byte 0 ==
3620 12:33:00.490626 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3621 12:33:00.493940 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3622 12:33:00.497197 == TX Byte 1 ==
3623 12:33:00.500906 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3624 12:33:00.503897 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3625 12:33:00.504008 ==
3626 12:33:00.507039 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 12:33:00.514137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 12:33:00.514221 ==
3629 12:33:00.524730 TX Vref=22, minBit 0, minWin=25, winSum=418
3630 12:33:00.528189 TX Vref=24, minBit 10, minWin=25, winSum=422
3631 12:33:00.531485 TX Vref=26, minBit 2, minWin=26, winSum=429
3632 12:33:00.534783 TX Vref=28, minBit 7, minWin=26, winSum=429
3633 12:33:00.537511 TX Vref=30, minBit 9, minWin=26, winSum=433
3634 12:33:00.544812 TX Vref=32, minBit 1, minWin=26, winSum=433
3635 12:33:00.547782 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3636 12:33:00.547868
3637 12:33:00.551481 Final TX Range 1 Vref 30
3638 12:33:00.551565
3639 12:33:00.551631 ==
3640 12:33:00.554576 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 12:33:00.557684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 12:33:00.557798 ==
3643 12:33:00.560750
3644 12:33:00.560832
3645 12:33:00.560945 TX Vref Scan disable
3646 12:33:00.564477 == TX Byte 0 ==
3647 12:33:00.567642 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3648 12:33:00.570699 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3649 12:33:00.574355 == TX Byte 1 ==
3650 12:33:00.577543 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3651 12:33:00.584235 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3652 12:33:00.584325
3653 12:33:00.584408 [DATLAT]
3654 12:33:00.584472 Freq=1200, CH1 RK1
3655 12:33:00.584532
3656 12:33:00.587653 DATLAT Default: 0xd
3657 12:33:00.587753 0, 0xFFFF, sum = 0
3658 12:33:00.590944 1, 0xFFFF, sum = 0
3659 12:33:00.594276 2, 0xFFFF, sum = 0
3660 12:33:00.594365 3, 0xFFFF, sum = 0
3661 12:33:00.597658 4, 0xFFFF, sum = 0
3662 12:33:00.597745 5, 0xFFFF, sum = 0
3663 12:33:00.600913 6, 0xFFFF, sum = 0
3664 12:33:00.600984 7, 0xFFFF, sum = 0
3665 12:33:00.604156 8, 0xFFFF, sum = 0
3666 12:33:00.604231 9, 0xFFFF, sum = 0
3667 12:33:00.607411 10, 0xFFFF, sum = 0
3668 12:33:00.607487 11, 0xFFFF, sum = 0
3669 12:33:00.610411 12, 0x0, sum = 1
3670 12:33:00.610489 13, 0x0, sum = 2
3671 12:33:00.614185 14, 0x0, sum = 3
3672 12:33:00.614263 15, 0x0, sum = 4
3673 12:33:00.617333 best_step = 13
3674 12:33:00.617437
3675 12:33:00.617534 ==
3676 12:33:00.620571 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 12:33:00.623642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 12:33:00.623732 ==
3679 12:33:00.623806 RX Vref Scan: 0
3680 12:33:00.623899
3681 12:33:00.627650 RX Vref 0 -> 0, step: 1
3682 12:33:00.627736
3683 12:33:00.630289 RX Delay -5 -> 252, step: 4
3684 12:33:00.633627 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3685 12:33:00.640948 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3686 12:33:00.643740 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3687 12:33:00.647132 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3688 12:33:00.650408 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3689 12:33:00.654118 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3690 12:33:00.660846 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3691 12:33:00.663992 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3692 12:33:00.667014 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3693 12:33:00.670738 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3694 12:33:00.673817 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3695 12:33:00.680192 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3696 12:33:00.683420 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3697 12:33:00.687181 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3698 12:33:00.690505 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3699 12:33:00.697217 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3700 12:33:00.697340 ==
3701 12:33:00.700560 Dram Type= 6, Freq= 0, CH_1, rank 1
3702 12:33:00.703240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3703 12:33:00.703401 ==
3704 12:33:00.703506 DQS Delay:
3705 12:33:00.707131 DQS0 = 0, DQS1 = 0
3706 12:33:00.707245 DQM Delay:
3707 12:33:00.710197 DQM0 = 119, DQM1 = 116
3708 12:33:00.710312 DQ Delay:
3709 12:33:00.713312 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3710 12:33:00.716511 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3711 12:33:00.719793 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3712 12:33:00.723256 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3713 12:33:00.723413
3714 12:33:00.723561
3715 12:33:00.733554 [DQSOSCAuto] RK1, (LSB)MR18= 0xfed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3716 12:33:00.737011 CH1 RK1: MR19=403, MR18=FED
3717 12:33:00.740340 CH1_RK1: MR19=0x403, MR18=0xFED, DQSOSC=404, MR23=63, INC=40, DEC=26
3718 12:33:00.743619 [RxdqsGatingPostProcess] freq 1200
3719 12:33:00.750538 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3720 12:33:00.753329 best DQS0 dly(2T, 0.5T) = (0, 11)
3721 12:33:00.756482 best DQS1 dly(2T, 0.5T) = (0, 11)
3722 12:33:00.759820 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3723 12:33:00.763489 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3724 12:33:00.766574 best DQS0 dly(2T, 0.5T) = (0, 11)
3725 12:33:00.770274 best DQS1 dly(2T, 0.5T) = (0, 11)
3726 12:33:00.773404 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3727 12:33:00.776800 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3728 12:33:00.776913 Pre-setting of DQS Precalculation
3729 12:33:00.783110 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3730 12:33:00.789645 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3731 12:33:00.796650 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3732 12:33:00.796741
3733 12:33:00.796808
3734 12:33:00.800037 [Calibration Summary] 2400 Mbps
3735 12:33:00.803356 CH 0, Rank 0
3736 12:33:00.803444 SW Impedance : PASS
3737 12:33:00.806157 DUTY Scan : NO K
3738 12:33:00.809549 ZQ Calibration : PASS
3739 12:33:00.809659 Jitter Meter : NO K
3740 12:33:00.812856 CBT Training : PASS
3741 12:33:00.816743 Write leveling : PASS
3742 12:33:00.816826 RX DQS gating : PASS
3743 12:33:00.819993 RX DQ/DQS(RDDQC) : PASS
3744 12:33:00.823184 TX DQ/DQS : PASS
3745 12:33:00.823334 RX DATLAT : PASS
3746 12:33:00.826456 RX DQ/DQS(Engine): PASS
3747 12:33:00.826547 TX OE : NO K
3748 12:33:00.829666 All Pass.
3749 12:33:00.829761
3750 12:33:00.829871 CH 0, Rank 1
3751 12:33:00.832899 SW Impedance : PASS
3752 12:33:00.833010 DUTY Scan : NO K
3753 12:33:00.836147 ZQ Calibration : PASS
3754 12:33:00.839580 Jitter Meter : NO K
3755 12:33:00.839661 CBT Training : PASS
3756 12:33:00.842926 Write leveling : PASS
3757 12:33:00.846374 RX DQS gating : PASS
3758 12:33:00.846455 RX DQ/DQS(RDDQC) : PASS
3759 12:33:00.849658 TX DQ/DQS : PASS
3760 12:33:00.853162 RX DATLAT : PASS
3761 12:33:00.853246 RX DQ/DQS(Engine): PASS
3762 12:33:00.856471 TX OE : NO K
3763 12:33:00.856553 All Pass.
3764 12:33:00.856636
3765 12:33:00.859215 CH 1, Rank 0
3766 12:33:00.859296 SW Impedance : PASS
3767 12:33:00.863157 DUTY Scan : NO K
3768 12:33:00.866499 ZQ Calibration : PASS
3769 12:33:00.866585 Jitter Meter : NO K
3770 12:33:00.869767 CBT Training : PASS
3771 12:33:00.872822 Write leveling : PASS
3772 12:33:00.872905 RX DQS gating : PASS
3773 12:33:00.875849 RX DQ/DQS(RDDQC) : PASS
3774 12:33:00.879666 TX DQ/DQS : PASS
3775 12:33:00.879749 RX DATLAT : PASS
3776 12:33:00.882856 RX DQ/DQS(Engine): PASS
3777 12:33:00.885956 TX OE : NO K
3778 12:33:00.886036 All Pass.
3779 12:33:00.886127
3780 12:33:00.886210 CH 1, Rank 1
3781 12:33:00.888973 SW Impedance : PASS
3782 12:33:00.892714 DUTY Scan : NO K
3783 12:33:00.892798 ZQ Calibration : PASS
3784 12:33:00.895792 Jitter Meter : NO K
3785 12:33:00.895879 CBT Training : PASS
3786 12:33:00.898922 Write leveling : PASS
3787 12:33:00.902776 RX DQS gating : PASS
3788 12:33:00.902855 RX DQ/DQS(RDDQC) : PASS
3789 12:33:00.906150 TX DQ/DQS : PASS
3790 12:33:00.909391 RX DATLAT : PASS
3791 12:33:00.909471 RX DQ/DQS(Engine): PASS
3792 12:33:00.912790 TX OE : NO K
3793 12:33:00.912868 All Pass.
3794 12:33:00.912950
3795 12:33:00.915388 DramC Write-DBI off
3796 12:33:00.919216 PER_BANK_REFRESH: Hybrid Mode
3797 12:33:00.919294 TX_TRACKING: ON
3798 12:33:00.928747 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3799 12:33:00.932627 [FAST_K] Save calibration result to emmc
3800 12:33:00.935724 dramc_set_vcore_voltage set vcore to 650000
3801 12:33:00.938988 Read voltage for 600, 5
3802 12:33:00.939096 Vio18 = 0
3803 12:33:00.939214 Vcore = 650000
3804 12:33:00.942195 Vdram = 0
3805 12:33:00.942273 Vddq = 0
3806 12:33:00.942357 Vmddr = 0
3807 12:33:00.948836 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3808 12:33:00.952260 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3809 12:33:00.955699 MEM_TYPE=3, freq_sel=19
3810 12:33:00.959125 sv_algorithm_assistance_LP4_1600
3811 12:33:00.962500 ============ PULL DRAM RESETB DOWN ============
3812 12:33:00.965863 ========== PULL DRAM RESETB DOWN end =========
3813 12:33:00.971961 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3814 12:33:00.975861 ===================================
3815 12:33:00.979014 LPDDR4 DRAM CONFIGURATION
3816 12:33:00.979093 ===================================
3817 12:33:00.982235 EX_ROW_EN[0] = 0x0
3818 12:33:00.985321 EX_ROW_EN[1] = 0x0
3819 12:33:00.985395 LP4Y_EN = 0x0
3820 12:33:00.989155 WORK_FSP = 0x0
3821 12:33:00.989237 WL = 0x2
3822 12:33:00.992154 RL = 0x2
3823 12:33:00.992234 BL = 0x2
3824 12:33:00.995281 RPST = 0x0
3825 12:33:00.995368 RD_PRE = 0x0
3826 12:33:00.998461 WR_PRE = 0x1
3827 12:33:00.998533 WR_PST = 0x0
3828 12:33:01.002288 DBI_WR = 0x0
3829 12:33:01.002399 DBI_RD = 0x0
3830 12:33:01.005489 OTF = 0x1
3831 12:33:01.008581 ===================================
3832 12:33:01.012417 ===================================
3833 12:33:01.012492 ANA top config
3834 12:33:01.015789 ===================================
3835 12:33:01.019126 DLL_ASYNC_EN = 0
3836 12:33:01.021853 ALL_SLAVE_EN = 1
3837 12:33:01.025696 NEW_RANK_MODE = 1
3838 12:33:01.025774 DLL_IDLE_MODE = 1
3839 12:33:01.028962 LP45_APHY_COMB_EN = 1
3840 12:33:01.032154 TX_ODT_DIS = 1
3841 12:33:01.035426 NEW_8X_MODE = 1
3842 12:33:01.038607 ===================================
3843 12:33:01.041711 ===================================
3844 12:33:01.045632 data_rate = 1200
3845 12:33:01.045707 CKR = 1
3846 12:33:01.048767 DQ_P2S_RATIO = 8
3847 12:33:01.052208 ===================================
3848 12:33:01.055525 CA_P2S_RATIO = 8
3849 12:33:01.058226 DQ_CA_OPEN = 0
3850 12:33:01.061655 DQ_SEMI_OPEN = 0
3851 12:33:01.064999 CA_SEMI_OPEN = 0
3852 12:33:01.065083 CA_FULL_RATE = 0
3853 12:33:01.068504 DQ_CKDIV4_EN = 1
3854 12:33:01.071870 CA_CKDIV4_EN = 1
3855 12:33:01.075169 CA_PREDIV_EN = 0
3856 12:33:01.078361 PH8_DLY = 0
3857 12:33:01.082257 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3858 12:33:01.082339 DQ_AAMCK_DIV = 4
3859 12:33:01.085579 CA_AAMCK_DIV = 4
3860 12:33:01.088747 CA_ADMCK_DIV = 4
3861 12:33:01.092055 DQ_TRACK_CA_EN = 0
3862 12:33:01.095140 CA_PICK = 600
3863 12:33:01.098865 CA_MCKIO = 600
3864 12:33:01.098963 MCKIO_SEMI = 0
3865 12:33:01.101984 PLL_FREQ = 2288
3866 12:33:01.104973 DQ_UI_PI_RATIO = 32
3867 12:33:01.108889 CA_UI_PI_RATIO = 0
3868 12:33:01.111946 ===================================
3869 12:33:01.114944 ===================================
3870 12:33:01.118768 memory_type:LPDDR4
3871 12:33:01.118843 GP_NUM : 10
3872 12:33:01.121453 SRAM_EN : 1
3873 12:33:01.124832 MD32_EN : 0
3874 12:33:01.128175 ===================================
3875 12:33:01.128254 [ANA_INIT] >>>>>>>>>>>>>>
3876 12:33:01.131428 <<<<<< [CONFIGURE PHASE]: ANA_TX
3877 12:33:01.135103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3878 12:33:01.138260 ===================================
3879 12:33:01.141515 data_rate = 1200,PCW = 0X5800
3880 12:33:01.145348 ===================================
3881 12:33:01.148403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3882 12:33:01.154767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3883 12:33:01.158185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 12:33:01.164938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3885 12:33:01.168337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3886 12:33:01.171615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3887 12:33:01.171695 [ANA_INIT] flow start
3888 12:33:01.174905 [ANA_INIT] PLL >>>>>>>>
3889 12:33:01.178219 [ANA_INIT] PLL <<<<<<<<
3890 12:33:01.181627 [ANA_INIT] MIDPI >>>>>>>>
3891 12:33:01.181708 [ANA_INIT] MIDPI <<<<<<<<
3892 12:33:01.184871 [ANA_INIT] DLL >>>>>>>>
3893 12:33:01.188181 [ANA_INIT] flow end
3894 12:33:01.191595 ============ LP4 DIFF to SE enter ============
3895 12:33:01.194952 ============ LP4 DIFF to SE exit ============
3896 12:33:01.198153 [ANA_INIT] <<<<<<<<<<<<<
3897 12:33:01.201397 [Flow] Enable top DCM control >>>>>
3898 12:33:01.204654 [Flow] Enable top DCM control <<<<<
3899 12:33:01.207647 Enable DLL master slave shuffle
3900 12:33:01.211304 ==============================================================
3901 12:33:01.214403 Gating Mode config
3902 12:33:01.217593 ==============================================================
3903 12:33:01.221230 Config description:
3904 12:33:01.230932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3905 12:33:01.237751 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3906 12:33:01.240902 SELPH_MODE 0: By rank 1: By Phase
3907 12:33:01.247741 ==============================================================
3908 12:33:01.250815 GAT_TRACK_EN = 1
3909 12:33:01.254520 RX_GATING_MODE = 2
3910 12:33:01.257528 RX_GATING_TRACK_MODE = 2
3911 12:33:01.260819 SELPH_MODE = 1
3912 12:33:01.264105 PICG_EARLY_EN = 1
3913 12:33:01.267439 VALID_LAT_VALUE = 1
3914 12:33:01.270614 ==============================================================
3915 12:33:01.273960 Enter into Gating configuration >>>>
3916 12:33:01.277391 Exit from Gating configuration <<<<
3917 12:33:01.280744 Enter into DVFS_PRE_config >>>>>
3918 12:33:01.290530 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3919 12:33:01.293913 Exit from DVFS_PRE_config <<<<<
3920 12:33:01.297182 Enter into PICG configuration >>>>
3921 12:33:01.300545 Exit from PICG configuration <<<<
3922 12:33:01.303862 [RX_INPUT] configuration >>>>>
3923 12:33:01.307238 [RX_INPUT] configuration <<<<<
3924 12:33:01.313903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3925 12:33:01.317542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3926 12:33:01.324410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 12:33:01.330547 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 12:33:01.337564 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3929 12:33:01.344264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3930 12:33:01.346990 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3931 12:33:01.350762 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3932 12:33:01.353790 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3933 12:33:01.360581 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3934 12:33:01.363716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3935 12:33:01.366750 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 12:33:01.370652 ===================================
3937 12:33:01.373985 LPDDR4 DRAM CONFIGURATION
3938 12:33:01.376810 ===================================
3939 12:33:01.376888 EX_ROW_EN[0] = 0x0
3940 12:33:01.380214 EX_ROW_EN[1] = 0x0
3941 12:33:01.383670 LP4Y_EN = 0x0
3942 12:33:01.383751 WORK_FSP = 0x0
3943 12:33:01.386981 WL = 0x2
3944 12:33:01.387060 RL = 0x2
3945 12:33:01.390442 BL = 0x2
3946 12:33:01.390540 RPST = 0x0
3947 12:33:01.393697 RD_PRE = 0x0
3948 12:33:01.393779 WR_PRE = 0x1
3949 12:33:01.396873 WR_PST = 0x0
3950 12:33:01.396982 DBI_WR = 0x0
3951 12:33:01.400132 DBI_RD = 0x0
3952 12:33:01.400211 OTF = 0x1
3953 12:33:01.403507 ===================================
3954 12:33:01.406845 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3955 12:33:01.413465 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3956 12:33:01.416828 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3957 12:33:01.420125 ===================================
3958 12:33:01.423817 LPDDR4 DRAM CONFIGURATION
3959 12:33:01.426829 ===================================
3960 12:33:01.426944 EX_ROW_EN[0] = 0x10
3961 12:33:01.430458 EX_ROW_EN[1] = 0x0
3962 12:33:01.430574 LP4Y_EN = 0x0
3963 12:33:01.433695 WORK_FSP = 0x0
3964 12:33:01.433796 WL = 0x2
3965 12:33:01.436790 RL = 0x2
3966 12:33:01.439932 BL = 0x2
3967 12:33:01.440031 RPST = 0x0
3968 12:33:01.443583 RD_PRE = 0x0
3969 12:33:01.443662 WR_PRE = 0x1
3970 12:33:01.447133 WR_PST = 0x0
3971 12:33:01.447258 DBI_WR = 0x0
3972 12:33:01.450449 DBI_RD = 0x0
3973 12:33:01.450549 OTF = 0x1
3974 12:33:01.453081 ===================================
3975 12:33:01.459826 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3976 12:33:01.463659 nWR fixed to 30
3977 12:33:01.467296 [ModeRegInit_LP4] CH0 RK0
3978 12:33:01.467442 [ModeRegInit_LP4] CH0 RK1
3979 12:33:01.470492 [ModeRegInit_LP4] CH1 RK0
3980 12:33:01.474133 [ModeRegInit_LP4] CH1 RK1
3981 12:33:01.474207 match AC timing 17
3982 12:33:01.480431 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3983 12:33:01.483648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3984 12:33:01.487049 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3985 12:33:01.493863 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3986 12:33:01.497235 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3987 12:33:01.497318 ==
3988 12:33:01.500569 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 12:33:01.503834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 12:33:01.503918 ==
3991 12:33:01.510521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3992 12:33:01.517102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3993 12:33:01.520423 [CA 0] Center 36 (5~67) winsize 63
3994 12:33:01.523885 [CA 1] Center 36 (5~67) winsize 63
3995 12:33:01.527210 [CA 2] Center 34 (3~65) winsize 63
3996 12:33:01.530941 [CA 3] Center 33 (3~64) winsize 62
3997 12:33:01.534011 [CA 4] Center 33 (2~64) winsize 63
3998 12:33:01.537056 [CA 5] Center 32 (2~63) winsize 62
3999 12:33:01.537156
4000 12:33:01.540862 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4001 12:33:01.540968
4002 12:33:01.544067 [CATrainingPosCal] consider 1 rank data
4003 12:33:01.547283 u2DelayCellTimex100 = 270/100 ps
4004 12:33:01.550345 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
4005 12:33:01.553533 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4006 12:33:01.556930 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4007 12:33:01.560276 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4008 12:33:01.563500 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4009 12:33:01.566883 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4010 12:33:01.570235
4011 12:33:01.573532 CA PerBit enable=1, Macro0, CA PI delay=32
4012 12:33:01.573607
4013 12:33:01.577194 [CBTSetCACLKResult] CA Dly = 32
4014 12:33:01.577327 CS Dly: 4 (0~35)
4015 12:33:01.577419 ==
4016 12:33:01.580588 Dram Type= 6, Freq= 0, CH_0, rank 1
4017 12:33:01.583728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 12:33:01.583804 ==
4019 12:33:01.590244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4020 12:33:01.596902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4021 12:33:01.600211 [CA 0] Center 36 (5~67) winsize 63
4022 12:33:01.603356 [CA 1] Center 36 (5~67) winsize 63
4023 12:33:01.606643 [CA 2] Center 34 (3~65) winsize 63
4024 12:33:01.610013 [CA 3] Center 33 (3~64) winsize 62
4025 12:33:01.613433 [CA 4] Center 33 (2~64) winsize 63
4026 12:33:01.616743 [CA 5] Center 32 (2~63) winsize 62
4027 12:33:01.616826
4028 12:33:01.620169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4029 12:33:01.620252
4030 12:33:01.623532 [CATrainingPosCal] consider 2 rank data
4031 12:33:01.626877 u2DelayCellTimex100 = 270/100 ps
4032 12:33:01.630219 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
4033 12:33:01.633683 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4034 12:33:01.636937 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4035 12:33:01.640125 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4036 12:33:01.646834 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4037 12:33:01.650056 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4038 12:33:01.650158
4039 12:33:01.653845 CA PerBit enable=1, Macro0, CA PI delay=32
4040 12:33:01.653943
4041 12:33:01.656935 [CBTSetCACLKResult] CA Dly = 32
4042 12:33:01.657009 CS Dly: 4 (0~35)
4043 12:33:01.657071
4044 12:33:01.660204 ----->DramcWriteLeveling(PI) begin...
4045 12:33:01.660307 ==
4046 12:33:01.663391 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 12:33:01.669914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 12:33:01.669999 ==
4049 12:33:01.673445 Write leveling (Byte 0): 33 => 33
4050 12:33:01.676676 Write leveling (Byte 1): 31 => 31
4051 12:33:01.676759 DramcWriteLeveling(PI) end<-----
4052 12:33:01.676825
4053 12:33:01.679920 ==
4054 12:33:01.683060 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 12:33:01.686263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 12:33:01.686375 ==
4057 12:33:01.689765 [Gating] SW mode calibration
4058 12:33:01.696178 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4059 12:33:01.700143 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4060 12:33:01.706571 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 12:33:01.709713 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 12:33:01.712904 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 12:33:01.719734 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4064 12:33:01.722943 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4065 12:33:01.726279 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 12:33:01.732533 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 12:33:01.735861 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 12:33:01.739184 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 12:33:01.745728 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 12:33:01.748773 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 12:33:01.752351 0 10 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
4072 12:33:01.758767 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4073 12:33:01.762384 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 12:33:01.765553 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 12:33:01.771885 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 12:33:01.775100 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 12:33:01.778480 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 12:33:01.785144 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 12:33:01.789033 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4080 12:33:01.792329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4081 12:33:01.798667 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:33:01.801841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:33:01.805064 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:33:01.811640 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 12:33:01.815373 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 12:33:01.818235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 12:33:01.825408 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 12:33:01.828696 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 12:33:01.832016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 12:33:01.838651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 12:33:01.842019 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 12:33:01.845291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 12:33:01.851768 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 12:33:01.854921 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4095 12:33:01.858028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4096 12:33:01.864902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4097 12:33:01.864988 Total UI for P1: 0, mck2ui 16
4098 12:33:01.871289 best dqsien dly found for B0: ( 0, 13, 10)
4099 12:33:01.875065 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 12:33:01.878263 Total UI for P1: 0, mck2ui 16
4101 12:33:01.881431 best dqsien dly found for B1: ( 0, 13, 16)
4102 12:33:01.884657 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4103 12:33:01.887914 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4104 12:33:01.887997
4105 12:33:01.891654 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4106 12:33:01.894903 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4107 12:33:01.898327 [Gating] SW calibration Done
4108 12:33:01.898410 ==
4109 12:33:01.901610 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 12:33:01.904822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 12:33:01.904934 ==
4112 12:33:01.907928 RX Vref Scan: 0
4113 12:33:01.908011
4114 12:33:01.911142 RX Vref 0 -> 0, step: 1
4115 12:33:01.911233
4116 12:33:01.914440 RX Delay -230 -> 252, step: 16
4117 12:33:01.918106 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4118 12:33:01.921302 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4119 12:33:01.924715 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4120 12:33:01.927991 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4121 12:33:01.934579 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4122 12:33:01.937950 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4123 12:33:01.941319 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4124 12:33:01.944585 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4125 12:33:01.948088 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4126 12:33:01.954809 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4127 12:33:01.957480 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4128 12:33:01.961251 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4129 12:33:01.964514 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4130 12:33:01.970810 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4131 12:33:01.973990 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4132 12:33:01.977863 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4133 12:33:01.978004 ==
4134 12:33:01.981071 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 12:33:01.984329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 12:33:01.987997 ==
4137 12:33:01.988081 DQS Delay:
4138 12:33:01.988149 DQS0 = 0, DQS1 = 0
4139 12:33:01.991252 DQM Delay:
4140 12:33:01.991322 DQM0 = 53, DQM1 = 47
4141 12:33:01.994492 DQ Delay:
4142 12:33:01.994586 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4143 12:33:01.997755 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4144 12:33:02.001180 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4145 12:33:02.003962 DQ12 =57, DQ13 =49, DQ14 =65, DQ15 =49
4146 12:33:02.007897
4147 12:33:02.007991
4148 12:33:02.008075 ==
4149 12:33:02.011168 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 12:33:02.014423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 12:33:02.014504 ==
4152 12:33:02.014585
4153 12:33:02.014661
4154 12:33:02.017959 TX Vref Scan disable
4155 12:33:02.018039 == TX Byte 0 ==
4156 12:33:02.024340 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4157 12:33:02.027832 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4158 12:33:02.027912 == TX Byte 1 ==
4159 12:33:02.034312 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4160 12:33:02.037666 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4161 12:33:02.037743 ==
4162 12:33:02.041060 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 12:33:02.044466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 12:33:02.044546 ==
4165 12:33:02.044636
4166 12:33:02.044717
4167 12:33:02.047879 TX Vref Scan disable
4168 12:33:02.051248 == TX Byte 0 ==
4169 12:33:02.054620 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4170 12:33:02.058096 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4171 12:33:02.060791 == TX Byte 1 ==
4172 12:33:02.064686 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4173 12:33:02.067865 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4174 12:33:02.067946
4175 12:33:02.071035 [DATLAT]
4176 12:33:02.071118 Freq=600, CH0 RK0
4177 12:33:02.071221
4178 12:33:02.074146 DATLAT Default: 0x9
4179 12:33:02.074221 0, 0xFFFF, sum = 0
4180 12:33:02.078037 1, 0xFFFF, sum = 0
4181 12:33:02.078116 2, 0xFFFF, sum = 0
4182 12:33:02.081194 3, 0xFFFF, sum = 0
4183 12:33:02.081280 4, 0xFFFF, sum = 0
4184 12:33:02.084332 5, 0xFFFF, sum = 0
4185 12:33:02.084409 6, 0xFFFF, sum = 0
4186 12:33:02.087599 7, 0xFFFF, sum = 0
4187 12:33:02.087676 8, 0x0, sum = 1
4188 12:33:02.091195 9, 0x0, sum = 2
4189 12:33:02.091271 10, 0x0, sum = 3
4190 12:33:02.094625 11, 0x0, sum = 4
4191 12:33:02.094702 best_step = 9
4192 12:33:02.094780
4193 12:33:02.094856 ==
4194 12:33:02.097758 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 12:33:02.100935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 12:33:02.104351 ==
4197 12:33:02.104424 RX Vref Scan: 1
4198 12:33:02.104505
4199 12:33:02.107699 RX Vref 0 -> 0, step: 1
4200 12:33:02.107774
4201 12:33:02.111061 RX Delay -163 -> 252, step: 8
4202 12:33:02.111132
4203 12:33:02.114481 Set Vref, RX VrefLevel [Byte0]: 55
4204 12:33:02.117678 [Byte1]: 55
4205 12:33:02.117755
4206 12:33:02.120895 Final RX Vref Byte 0 = 55 to rank0
4207 12:33:02.124137 Final RX Vref Byte 1 = 55 to rank0
4208 12:33:02.127421 Final RX Vref Byte 0 = 55 to rank1
4209 12:33:02.130677 Final RX Vref Byte 1 = 55 to rank1==
4210 12:33:02.133904 Dram Type= 6, Freq= 0, CH_0, rank 0
4211 12:33:02.137596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 12:33:02.137682 ==
4213 12:33:02.137778 DQS Delay:
4214 12:33:02.140805 DQS0 = 0, DQS1 = 0
4215 12:33:02.140886 DQM Delay:
4216 12:33:02.144265 DQM0 = 53, DQM1 = 46
4217 12:33:02.144342 DQ Delay:
4218 12:33:02.147523 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4219 12:33:02.150902 DQ4 =56, DQ5 =44, DQ6 =64, DQ7 =56
4220 12:33:02.153714 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4221 12:33:02.157029 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4222 12:33:02.157142
4223 12:33:02.157225
4224 12:33:02.167239 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4225 12:33:02.167399 CH0 RK0: MR19=808, MR18=6C5F
4226 12:33:02.173776 CH0_RK0: MR19=0x808, MR18=0x6C5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4227 12:33:02.173858
4228 12:33:02.177564 ----->DramcWriteLeveling(PI) begin...
4229 12:33:02.177652 ==
4230 12:33:02.180628 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 12:33:02.187591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 12:33:02.187676 ==
4233 12:33:02.190854 Write leveling (Byte 0): 35 => 35
4234 12:33:02.190930 Write leveling (Byte 1): 31 => 31
4235 12:33:02.194001 DramcWriteLeveling(PI) end<-----
4236 12:33:02.194085
4237 12:33:02.197199 ==
4238 12:33:02.197282 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 12:33:02.203594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 12:33:02.203671 ==
4241 12:33:02.207456 [Gating] SW mode calibration
4242 12:33:02.214155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4243 12:33:02.216825 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4244 12:33:02.223914 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 12:33:02.227271 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 12:33:02.230430 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 12:33:02.236980 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4248 12:33:02.240187 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
4249 12:33:02.243719 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 12:33:02.250302 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 12:33:02.253616 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 12:33:02.256994 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 12:33:02.263547 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 12:33:02.267029 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 12:33:02.270301 0 10 12 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
4256 12:33:02.276843 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4257 12:33:02.280081 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 12:33:02.283408 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 12:33:02.289865 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 12:33:02.293612 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 12:33:02.296783 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 12:33:02.299971 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 12:33:02.306973 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4264 12:33:02.310266 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4265 12:33:02.313391 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:33:02.320035 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:33:02.323389 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:33:02.326630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 12:33:02.333204 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 12:33:02.336950 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 12:33:02.340018 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 12:33:02.346696 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 12:33:02.349858 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 12:33:02.353698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 12:33:02.359778 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 12:33:02.363173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 12:33:02.366443 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 12:33:02.373360 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 12:33:02.376741 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4280 12:33:02.380021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 12:33:02.383263 Total UI for P1: 0, mck2ui 16
4282 12:33:02.386321 best dqsien dly found for B0: ( 0, 13, 12)
4283 12:33:02.390193 Total UI for P1: 0, mck2ui 16
4284 12:33:02.393373 best dqsien dly found for B1: ( 0, 13, 14)
4285 12:33:02.396511 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4286 12:33:02.399614 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4287 12:33:02.399696
4288 12:33:02.406620 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4289 12:33:02.409852 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4290 12:33:02.409935 [Gating] SW calibration Done
4291 12:33:02.413032 ==
4292 12:33:02.416201 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 12:33:02.419886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 12:33:02.419970 ==
4295 12:33:02.420036 RX Vref Scan: 0
4296 12:33:02.420097
4297 12:33:02.423212 RX Vref 0 -> 0, step: 1
4298 12:33:02.423295
4299 12:33:02.426551 RX Delay -230 -> 252, step: 16
4300 12:33:02.429768 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4301 12:33:02.433109 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4302 12:33:02.436522 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4303 12:33:02.443067 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4304 12:33:02.446167 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4305 12:33:02.449811 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4306 12:33:02.453054 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4307 12:33:02.456228 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4308 12:33:02.463247 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4309 12:33:02.466552 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4310 12:33:02.469793 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4311 12:33:02.473096 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4312 12:33:02.479821 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4313 12:33:02.483197 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4314 12:33:02.486453 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4315 12:33:02.489707 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4316 12:33:02.489789 ==
4317 12:33:02.492774 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 12:33:02.499597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 12:33:02.499708 ==
4320 12:33:02.499805 DQS Delay:
4321 12:33:02.502787 DQS0 = 0, DQS1 = 0
4322 12:33:02.502862 DQM Delay:
4323 12:33:02.502931 DQM0 = 58, DQM1 = 47
4324 12:33:02.506496 DQ Delay:
4325 12:33:02.509704 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4326 12:33:02.513021 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4327 12:33:02.516120 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4328 12:33:02.519511 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4329 12:33:02.519611
4330 12:33:02.519701
4331 12:33:02.519798 ==
4332 12:33:02.522689 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 12:33:02.526378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 12:33:02.526487 ==
4335 12:33:02.526587
4336 12:33:02.526689
4337 12:33:02.529677 TX Vref Scan disable
4338 12:33:02.529786 == TX Byte 0 ==
4339 12:33:02.536245 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4340 12:33:02.539637 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4341 12:33:02.539752 == TX Byte 1 ==
4342 12:33:02.546291 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4343 12:33:02.549529 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4344 12:33:02.549630 ==
4345 12:33:02.552556 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 12:33:02.555735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 12:33:02.555844 ==
4348 12:33:02.559107
4349 12:33:02.559211
4350 12:33:02.559304 TX Vref Scan disable
4351 12:33:02.563103 == TX Byte 0 ==
4352 12:33:02.566300 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4353 12:33:02.572738 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4354 12:33:02.572856 == TX Byte 1 ==
4355 12:33:02.576198 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4356 12:33:02.582803 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4357 12:33:02.582889
4358 12:33:02.582956 [DATLAT]
4359 12:33:02.583019 Freq=600, CH0 RK1
4360 12:33:02.583079
4361 12:33:02.586207 DATLAT Default: 0x9
4362 12:33:02.586291 0, 0xFFFF, sum = 0
4363 12:33:02.589572 1, 0xFFFF, sum = 0
4364 12:33:02.589657 2, 0xFFFF, sum = 0
4365 12:33:02.593028 3, 0xFFFF, sum = 0
4366 12:33:02.596049 4, 0xFFFF, sum = 0
4367 12:33:02.596134 5, 0xFFFF, sum = 0
4368 12:33:02.599846 6, 0xFFFF, sum = 0
4369 12:33:02.599959 7, 0xFFFF, sum = 0
4370 12:33:02.600044 8, 0x0, sum = 1
4371 12:33:02.602810 9, 0x0, sum = 2
4372 12:33:02.602923 10, 0x0, sum = 3
4373 12:33:02.606474 11, 0x0, sum = 4
4374 12:33:02.606555 best_step = 9
4375 12:33:02.606620
4376 12:33:02.606680 ==
4377 12:33:02.609630 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 12:33:02.616501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 12:33:02.616616 ==
4380 12:33:02.616720 RX Vref Scan: 0
4381 12:33:02.616816
4382 12:33:02.619642 RX Vref 0 -> 0, step: 1
4383 12:33:02.619747
4384 12:33:02.622727 RX Delay -163 -> 252, step: 8
4385 12:33:02.626444 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4386 12:33:02.632881 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4387 12:33:02.635919 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4388 12:33:02.639647 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4389 12:33:02.642909 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4390 12:33:02.646250 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4391 12:33:02.649611 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4392 12:33:02.656082 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4393 12:33:02.659233 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4394 12:33:02.662536 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4395 12:33:02.665790 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4396 12:33:02.672339 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4397 12:33:02.676072 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4398 12:33:02.679477 iDelay=197, Bit 13, Center 56 (-83 ~ 196) 280
4399 12:33:02.682254 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4400 12:33:02.685620 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4401 12:33:02.689063 ==
4402 12:33:02.692497 Dram Type= 6, Freq= 0, CH_0, rank 1
4403 12:33:02.695930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 12:33:02.696012 ==
4405 12:33:02.696076 DQS Delay:
4406 12:33:02.699248 DQS0 = 0, DQS1 = 0
4407 12:33:02.699373 DQM Delay:
4408 12:33:02.702500 DQM0 = 52, DQM1 = 47
4409 12:33:02.702582 DQ Delay:
4410 12:33:02.705699 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4411 12:33:02.708907 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4412 12:33:02.712628 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4413 12:33:02.715597 DQ12 =52, DQ13 =56, DQ14 =56, DQ15 =52
4414 12:33:02.715678
4415 12:33:02.715742
4416 12:33:02.722327 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
4417 12:33:02.725456 CH0 RK1: MR19=808, MR18=5F1F
4418 12:33:02.732472 CH0_RK1: MR19=0x808, MR18=0x5F1F, DQSOSC=391, MR23=63, INC=171, DEC=114
4419 12:33:02.735856 [RxdqsGatingPostProcess] freq 600
4420 12:33:02.742621 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4421 12:33:02.742703 Pre-setting of DQS Precalculation
4422 12:33:02.748963 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4423 12:33:02.749045 ==
4424 12:33:02.752344 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 12:33:02.755665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 12:33:02.755748 ==
4427 12:33:02.762249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 12:33:02.768720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4429 12:33:02.772018 [CA 0] Center 35 (5~66) winsize 62
4430 12:33:02.775445 [CA 1] Center 36 (5~67) winsize 63
4431 12:33:02.778934 [CA 2] Center 34 (4~65) winsize 62
4432 12:33:02.782521 [CA 3] Center 34 (4~65) winsize 62
4433 12:33:02.785310 [CA 4] Center 34 (4~65) winsize 62
4434 12:33:02.788629 [CA 5] Center 34 (4~65) winsize 62
4435 12:33:02.788712
4436 12:33:02.792031 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4437 12:33:02.792115
4438 12:33:02.795437 [CATrainingPosCal] consider 1 rank data
4439 12:33:02.798747 u2DelayCellTimex100 = 270/100 ps
4440 12:33:02.802091 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4441 12:33:02.805475 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4442 12:33:02.808930 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4443 12:33:02.811992 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4444 12:33:02.815282 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4445 12:33:02.818444 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4446 12:33:02.818528
4447 12:33:02.825418 CA PerBit enable=1, Macro0, CA PI delay=34
4448 12:33:02.825502
4449 12:33:02.825568 [CBTSetCACLKResult] CA Dly = 34
4450 12:33:02.828534 CS Dly: 6 (0~37)
4451 12:33:02.828618 ==
4452 12:33:02.832086 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 12:33:02.835203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 12:33:02.835312 ==
4455 12:33:02.842088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4456 12:33:02.849037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4457 12:33:02.852040 [CA 0] Center 36 (6~67) winsize 62
4458 12:33:02.855170 [CA 1] Center 36 (5~67) winsize 63
4459 12:33:02.858482 [CA 2] Center 34 (4~65) winsize 62
4460 12:33:02.862398 [CA 3] Center 34 (3~65) winsize 63
4461 12:33:02.865645 [CA 4] Center 35 (4~66) winsize 63
4462 12:33:02.868923 [CA 5] Center 34 (3~65) winsize 63
4463 12:33:02.869026
4464 12:33:02.872144 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4465 12:33:02.872260
4466 12:33:02.875396 [CATrainingPosCal] consider 2 rank data
4467 12:33:02.878489 u2DelayCellTimex100 = 270/100 ps
4468 12:33:02.881809 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4469 12:33:02.885152 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4470 12:33:02.888291 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4471 12:33:02.891637 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4472 12:33:02.895004 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4473 12:33:02.898403 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4474 12:33:02.898478
4475 12:33:02.905151 CA PerBit enable=1, Macro0, CA PI delay=34
4476 12:33:02.905254
4477 12:33:02.908455 [CBTSetCACLKResult] CA Dly = 34
4478 12:33:02.908557 CS Dly: 7 (0~39)
4479 12:33:02.908651
4480 12:33:02.911849 ----->DramcWriteLeveling(PI) begin...
4481 12:33:02.911923 ==
4482 12:33:02.915132 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 12:33:02.918425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 12:33:02.918524 ==
4485 12:33:02.921593 Write leveling (Byte 0): 29 => 29
4486 12:33:02.925571 Write leveling (Byte 1): 29 => 29
4487 12:33:02.928769 DramcWriteLeveling(PI) end<-----
4488 12:33:02.928867
4489 12:33:02.928958 ==
4490 12:33:02.931975 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 12:33:02.938253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 12:33:02.938357 ==
4493 12:33:02.938460 [Gating] SW mode calibration
4494 12:33:02.948455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4495 12:33:02.951611 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4496 12:33:02.955416 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 12:33:02.962248 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 12:33:02.965465 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 12:33:02.968732 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4500 12:33:02.975485 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 12:33:02.978806 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 12:33:02.981540 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 12:33:02.988475 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 12:33:02.991569 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 12:33:02.994872 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 12:33:03.001557 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 12:33:03.004914 0 10 12 | B1->B0 | 3636 3c3c | 0 0 | (0 0) (0 0)
4508 12:33:03.008225 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:33:03.014949 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 12:33:03.018149 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 12:33:03.021493 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 12:33:03.028503 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 12:33:03.031884 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 12:33:03.035105 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 12:33:03.041470 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4516 12:33:03.045196 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:33:03.048312 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:33:03.051571 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:33:03.058498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:33:03.061594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:33:03.064753 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 12:33:03.071533 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 12:33:03.074910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 12:33:03.078063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 12:33:03.084820 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 12:33:03.088336 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 12:33:03.091552 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 12:33:03.097825 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 12:33:03.101693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 12:33:03.105067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 12:33:03.111654 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4532 12:33:03.111755 Total UI for P1: 0, mck2ui 16
4533 12:33:03.118310 best dqsien dly found for B0: ( 0, 13, 10)
4534 12:33:03.121534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 12:33:03.124831 Total UI for P1: 0, mck2ui 16
4536 12:33:03.128083 best dqsien dly found for B1: ( 0, 13, 12)
4537 12:33:03.131360 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4538 12:33:03.134582 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4539 12:33:03.134651
4540 12:33:03.137885 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4541 12:33:03.141273 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4542 12:33:03.144970 [Gating] SW calibration Done
4543 12:33:03.145048 ==
4544 12:33:03.148154 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 12:33:03.151283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 12:33:03.154336 ==
4547 12:33:03.154456 RX Vref Scan: 0
4548 12:33:03.154586
4549 12:33:03.158092 RX Vref 0 -> 0, step: 1
4550 12:33:03.158188
4551 12:33:03.161339 RX Delay -230 -> 252, step: 16
4552 12:33:03.164626 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4553 12:33:03.167728 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4554 12:33:03.171443 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4555 12:33:03.177615 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4556 12:33:03.181362 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4557 12:33:03.184273 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4558 12:33:03.187608 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4559 12:33:03.190959 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4560 12:33:03.197580 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4561 12:33:03.200851 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4562 12:33:03.204625 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4563 12:33:03.207823 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4564 12:33:03.214294 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4565 12:33:03.217843 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4566 12:33:03.221235 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4567 12:33:03.224710 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4568 12:33:03.224809 ==
4569 12:33:03.227769 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 12:33:03.234512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 12:33:03.234638 ==
4572 12:33:03.234741 DQS Delay:
4573 12:33:03.237577 DQS0 = 0, DQS1 = 0
4574 12:33:03.237659 DQM Delay:
4575 12:33:03.237723 DQM0 = 51, DQM1 = 49
4576 12:33:03.241107 DQ Delay:
4577 12:33:03.244516 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4578 12:33:03.247912 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4579 12:33:03.251140 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4580 12:33:03.254297 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4581 12:33:03.254380
4582 12:33:03.254459
4583 12:33:03.254518 ==
4584 12:33:03.257332 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 12:33:03.261204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 12:33:03.261345 ==
4587 12:33:03.261471
4588 12:33:03.261588
4589 12:33:03.264290 TX Vref Scan disable
4590 12:33:03.264424 == TX Byte 0 ==
4591 12:33:03.270951 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4592 12:33:03.274089 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4593 12:33:03.274166 == TX Byte 1 ==
4594 12:33:03.280957 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4595 12:33:03.284040 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4596 12:33:03.284156 ==
4597 12:33:03.287221 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 12:33:03.290562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 12:33:03.290677 ==
4600 12:33:03.290761
4601 12:33:03.293953
4602 12:33:03.294038 TX Vref Scan disable
4603 12:33:03.297458 == TX Byte 0 ==
4604 12:33:03.300787 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4605 12:33:03.307414 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4606 12:33:03.307500 == TX Byte 1 ==
4607 12:33:03.310648 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4608 12:33:03.317503 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4609 12:33:03.317588
4610 12:33:03.317672 [DATLAT]
4611 12:33:03.317751 Freq=600, CH1 RK0
4612 12:33:03.317829
4613 12:33:03.320770 DATLAT Default: 0x9
4614 12:33:03.320868 0, 0xFFFF, sum = 0
4615 12:33:03.324118 1, 0xFFFF, sum = 0
4616 12:33:03.324208 2, 0xFFFF, sum = 0
4617 12:33:03.327508 3, 0xFFFF, sum = 0
4618 12:33:03.330715 4, 0xFFFF, sum = 0
4619 12:33:03.330801 5, 0xFFFF, sum = 0
4620 12:33:03.334135 6, 0xFFFF, sum = 0
4621 12:33:03.334226 7, 0xFFFF, sum = 0
4622 12:33:03.337301 8, 0x0, sum = 1
4623 12:33:03.337387 9, 0x0, sum = 2
4624 12:33:03.337473 10, 0x0, sum = 3
4625 12:33:03.340359 11, 0x0, sum = 4
4626 12:33:03.340445 best_step = 9
4627 12:33:03.340546
4628 12:33:03.340708 ==
4629 12:33:03.343761 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 12:33:03.350472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 12:33:03.350587 ==
4632 12:33:03.350672 RX Vref Scan: 1
4633 12:33:03.350782
4634 12:33:03.353863 RX Vref 0 -> 0, step: 1
4635 12:33:03.354007
4636 12:33:03.357192 RX Delay -147 -> 252, step: 8
4637 12:33:03.357309
4638 12:33:03.360636 Set Vref, RX VrefLevel [Byte0]: 53
4639 12:33:03.363871 [Byte1]: 48
4640 12:33:03.363999
4641 12:33:03.367125 Final RX Vref Byte 0 = 53 to rank0
4642 12:33:03.370411 Final RX Vref Byte 1 = 48 to rank0
4643 12:33:03.374155 Final RX Vref Byte 0 = 53 to rank1
4644 12:33:03.377227 Final RX Vref Byte 1 = 48 to rank1==
4645 12:33:03.380402 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 12:33:03.384140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 12:33:03.384245 ==
4648 12:33:03.387349 DQS Delay:
4649 12:33:03.387457 DQS0 = 0, DQS1 = 0
4650 12:33:03.387553 DQM Delay:
4651 12:33:03.391030 DQM0 = 48, DQM1 = 44
4652 12:33:03.391127 DQ Delay:
4653 12:33:03.393914 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4654 12:33:03.397302 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4655 12:33:03.400601 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4656 12:33:03.404104 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4657 12:33:03.404207
4658 12:33:03.404307
4659 12:33:03.414019 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4660 12:33:03.414126 CH1 RK0: MR19=808, MR18=4B70
4661 12:33:03.420521 CH1_RK0: MR19=0x808, MR18=0x4B70, DQSOSC=388, MR23=63, INC=174, DEC=116
4662 12:33:03.420636
4663 12:33:03.423653 ----->DramcWriteLeveling(PI) begin...
4664 12:33:03.427408 ==
4665 12:33:03.427515 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 12:33:03.434181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 12:33:03.434290 ==
4668 12:33:03.437553 Write leveling (Byte 0): 30 => 30
4669 12:33:03.440853 Write leveling (Byte 1): 29 => 29
4670 12:33:03.444102 DramcWriteLeveling(PI) end<-----
4671 12:33:03.444209
4672 12:33:03.444302 ==
4673 12:33:03.447388 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 12:33:03.450702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 12:33:03.450802 ==
4676 12:33:03.454196 [Gating] SW mode calibration
4677 12:33:03.460856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4678 12:33:03.464101 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4679 12:33:03.470706 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 12:33:03.474028 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 12:33:03.477197 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4682 12:33:03.483592 0 9 12 | B1->B0 | 3030 3030 | 1 0 | (0 0) (1 0)
4683 12:33:03.486842 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 12:33:03.490562 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 12:33:03.496910 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 12:33:03.500553 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 12:33:03.503808 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 12:33:03.510537 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 12:33:03.513819 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4690 12:33:03.517219 0 10 12 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
4691 12:33:03.523275 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 12:33:03.527148 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 12:33:03.529865 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 12:33:03.537047 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 12:33:03.540364 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 12:33:03.543501 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 12:33:03.550051 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4698 12:33:03.553435 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4699 12:33:03.556915 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:33:03.563511 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:33:03.566552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:33:03.569937 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:33:03.576470 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:33:03.580204 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:33:03.583229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 12:33:03.589640 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 12:33:03.593433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 12:33:03.596581 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 12:33:03.599624 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 12:33:03.606499 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 12:33:03.609804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 12:33:03.613182 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 12:33:03.619821 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4714 12:33:03.623182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4715 12:33:03.626617 Total UI for P1: 0, mck2ui 16
4716 12:33:03.629930 best dqsien dly found for B0: ( 0, 13, 10)
4717 12:33:03.633151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 12:33:03.636346 Total UI for P1: 0, mck2ui 16
4719 12:33:03.639537 best dqsien dly found for B1: ( 0, 13, 10)
4720 12:33:03.642780 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4721 12:33:03.649253 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4722 12:33:03.649343
4723 12:33:03.652487 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4724 12:33:03.655806 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4725 12:33:03.659205 [Gating] SW calibration Done
4726 12:33:03.659311 ==
4727 12:33:03.662682 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 12:33:03.665855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 12:33:03.665934 ==
4730 12:33:03.669316 RX Vref Scan: 0
4731 12:33:03.669390
4732 12:33:03.669488 RX Vref 0 -> 0, step: 1
4733 12:33:03.669592
4734 12:33:03.672622 RX Delay -230 -> 252, step: 16
4735 12:33:03.675891 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4736 12:33:03.682546 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4737 12:33:03.685740 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4738 12:33:03.689381 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4739 12:33:03.692860 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4740 12:33:03.695826 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4741 12:33:03.702581 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4742 12:33:03.705741 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4743 12:33:03.708894 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4744 12:33:03.712515 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4745 12:33:03.719496 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4746 12:33:03.722635 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4747 12:33:03.725993 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4748 12:33:03.729223 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4749 12:33:03.732609 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4750 12:33:03.739123 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4751 12:33:03.739195 ==
4752 12:33:03.742483 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 12:33:03.745866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 12:33:03.745944 ==
4755 12:33:03.746008 DQS Delay:
4756 12:33:03.748915 DQS0 = 0, DQS1 = 0
4757 12:33:03.749043 DQM Delay:
4758 12:33:03.752121 DQM0 = 53, DQM1 = 52
4759 12:33:03.752192 DQ Delay:
4760 12:33:03.755422 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4761 12:33:03.759195 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4762 12:33:03.762460 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4763 12:33:03.765791 DQ12 =65, DQ13 =65, DQ14 =57, DQ15 =65
4764 12:33:03.765878
4765 12:33:03.765938
4766 12:33:03.765995 ==
4767 12:33:03.768577 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 12:33:03.772486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 12:33:03.772569 ==
4770 12:33:03.775828
4771 12:33:03.775909
4772 12:33:03.775972 TX Vref Scan disable
4773 12:33:03.779146 == TX Byte 0 ==
4774 12:33:03.782426 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 12:33:03.785802 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 12:33:03.789126 == TX Byte 1 ==
4777 12:33:03.792445 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4778 12:33:03.795671 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4779 12:33:03.795745 ==
4780 12:33:03.798837 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 12:33:03.805727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 12:33:03.805811 ==
4783 12:33:03.805875
4784 12:33:03.805935
4785 12:33:03.805994 TX Vref Scan disable
4786 12:33:03.810100 == TX Byte 0 ==
4787 12:33:03.813184 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4788 12:33:03.820413 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4789 12:33:03.820497 == TX Byte 1 ==
4790 12:33:03.823476 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4791 12:33:03.830110 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4792 12:33:03.830193
4793 12:33:03.830258 [DATLAT]
4794 12:33:03.830319 Freq=600, CH1 RK1
4795 12:33:03.830378
4796 12:33:03.833488 DATLAT Default: 0x9
4797 12:33:03.833570 0, 0xFFFF, sum = 0
4798 12:33:03.836824 1, 0xFFFF, sum = 0
4799 12:33:03.836907 2, 0xFFFF, sum = 0
4800 12:33:03.840084 3, 0xFFFF, sum = 0
4801 12:33:03.843461 4, 0xFFFF, sum = 0
4802 12:33:03.843560 5, 0xFFFF, sum = 0
4803 12:33:03.846687 6, 0xFFFF, sum = 0
4804 12:33:03.846792 7, 0xFFFF, sum = 0
4805 12:33:03.846879 8, 0x0, sum = 1
4806 12:33:03.849977 9, 0x0, sum = 2
4807 12:33:03.850067 10, 0x0, sum = 3
4808 12:33:03.853111 11, 0x0, sum = 4
4809 12:33:03.853197 best_step = 9
4810 12:33:03.853265
4811 12:33:03.853328 ==
4812 12:33:03.856858 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 12:33:03.863285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 12:33:03.863416 ==
4815 12:33:03.863512 RX Vref Scan: 0
4816 12:33:03.863573
4817 12:33:03.866699 RX Vref 0 -> 0, step: 1
4818 12:33:03.866811
4819 12:33:03.870070 RX Delay -163 -> 252, step: 8
4820 12:33:03.873335 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4821 12:33:03.879956 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4822 12:33:03.883236 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4823 12:33:03.886694 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4824 12:33:03.890120 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4825 12:33:03.892825 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4826 12:33:03.899951 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4827 12:33:03.903475 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4828 12:33:03.906807 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4829 12:33:03.909899 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4830 12:33:03.912963 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4831 12:33:03.919865 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4832 12:33:03.923033 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4833 12:33:03.926177 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4834 12:33:03.929893 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4835 12:33:03.933112 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4836 12:33:03.936377 ==
4837 12:33:03.939595 Dram Type= 6, Freq= 0, CH_1, rank 1
4838 12:33:03.942980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4839 12:33:03.943087 ==
4840 12:33:03.943190 DQS Delay:
4841 12:33:03.946324 DQS0 = 0, DQS1 = 0
4842 12:33:03.946426 DQM Delay:
4843 12:33:03.949755 DQM0 = 49, DQM1 = 45
4844 12:33:03.949862 DQ Delay:
4845 12:33:03.953002 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4846 12:33:03.956201 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4847 12:33:03.959408 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4848 12:33:03.963211 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4849 12:33:03.963313
4850 12:33:03.963392
4851 12:33:03.969598 [DQSOSCAuto] RK1, (LSB)MR18= 0x661d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4852 12:33:03.972817 CH1 RK1: MR19=808, MR18=661D
4853 12:33:03.979524 CH1_RK1: MR19=0x808, MR18=0x661D, DQSOSC=390, MR23=63, INC=172, DEC=114
4854 12:33:03.982853 [RxdqsGatingPostProcess] freq 600
4855 12:33:03.989518 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4856 12:33:03.989625 Pre-setting of DQS Precalculation
4857 12:33:03.996497 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4858 12:33:04.002911 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4859 12:33:04.009672 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4860 12:33:04.009786
4861 12:33:04.009888
4862 12:33:04.012863 [Calibration Summary] 1200 Mbps
4863 12:33:04.012967 CH 0, Rank 0
4864 12:33:04.016484 SW Impedance : PASS
4865 12:33:04.019548 DUTY Scan : NO K
4866 12:33:04.019627 ZQ Calibration : PASS
4867 12:33:04.023296 Jitter Meter : NO K
4868 12:33:04.026406 CBT Training : PASS
4869 12:33:04.026509 Write leveling : PASS
4870 12:33:04.029567 RX DQS gating : PASS
4871 12:33:04.032504 RX DQ/DQS(RDDQC) : PASS
4872 12:33:04.032605 TX DQ/DQS : PASS
4873 12:33:04.036397 RX DATLAT : PASS
4874 12:33:04.039427 RX DQ/DQS(Engine): PASS
4875 12:33:04.039526 TX OE : NO K
4876 12:33:04.042565 All Pass.
4877 12:33:04.042675
4878 12:33:04.042768 CH 0, Rank 1
4879 12:33:04.045912 SW Impedance : PASS
4880 12:33:04.046012 DUTY Scan : NO K
4881 12:33:04.049401 ZQ Calibration : PASS
4882 12:33:04.052653 Jitter Meter : NO K
4883 12:33:04.052758 CBT Training : PASS
4884 12:33:04.056097 Write leveling : PASS
4885 12:33:04.059283 RX DQS gating : PASS
4886 12:33:04.059400 RX DQ/DQS(RDDQC) : PASS
4887 12:33:04.062560 TX DQ/DQS : PASS
4888 12:33:04.062658 RX DATLAT : PASS
4889 12:33:04.065843 RX DQ/DQS(Engine): PASS
4890 12:33:04.069057 TX OE : NO K
4891 12:33:04.069160 All Pass.
4892 12:33:04.069260
4893 12:33:04.069350 CH 1, Rank 0
4894 12:33:04.072863 SW Impedance : PASS
4895 12:33:04.075906 DUTY Scan : NO K
4896 12:33:04.075990 ZQ Calibration : PASS
4897 12:33:04.079146 Jitter Meter : NO K
4898 12:33:04.082546 CBT Training : PASS
4899 12:33:04.082621 Write leveling : PASS
4900 12:33:04.085895 RX DQS gating : PASS
4901 12:33:04.089215 RX DQ/DQS(RDDQC) : PASS
4902 12:33:04.089314 TX DQ/DQS : PASS
4903 12:33:04.092602 RX DATLAT : PASS
4904 12:33:04.095770 RX DQ/DQS(Engine): PASS
4905 12:33:04.095873 TX OE : NO K
4906 12:33:04.095970 All Pass.
4907 12:33:04.099150
4908 12:33:04.099249 CH 1, Rank 1
4909 12:33:04.102556 SW Impedance : PASS
4910 12:33:04.102654 DUTY Scan : NO K
4911 12:33:04.105893 ZQ Calibration : PASS
4912 12:33:04.109071 Jitter Meter : NO K
4913 12:33:04.109155 CBT Training : PASS
4914 12:33:04.112438 Write leveling : PASS
4915 12:33:04.115722 RX DQS gating : PASS
4916 12:33:04.115816 RX DQ/DQS(RDDQC) : PASS
4917 12:33:04.119003 TX DQ/DQS : PASS
4918 12:33:04.119088 RX DATLAT : PASS
4919 12:33:04.122422 RX DQ/DQS(Engine): PASS
4920 12:33:04.125761 TX OE : NO K
4921 12:33:04.125846 All Pass.
4922 12:33:04.125913
4923 12:33:04.128856 DramC Write-DBI off
4924 12:33:04.128941 PER_BANK_REFRESH: Hybrid Mode
4925 12:33:04.132607 TX_TRACKING: ON
4926 12:33:04.142283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4927 12:33:04.145449 [FAST_K] Save calibration result to emmc
4928 12:33:04.148651 dramc_set_vcore_voltage set vcore to 662500
4929 12:33:04.152437 Read voltage for 933, 3
4930 12:33:04.152526 Vio18 = 0
4931 12:33:04.152604 Vcore = 662500
4932 12:33:04.152712 Vdram = 0
4933 12:33:04.155777 Vddq = 0
4934 12:33:04.155861 Vmddr = 0
4935 12:33:04.161898 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4936 12:33:04.165707 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4937 12:33:04.168926 MEM_TYPE=3, freq_sel=17
4938 12:33:04.172296 sv_algorithm_assistance_LP4_1600
4939 12:33:04.175646 ============ PULL DRAM RESETB DOWN ============
4940 12:33:04.178682 ========== PULL DRAM RESETB DOWN end =========
4941 12:33:04.185281 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4942 12:33:04.188606 ===================================
4943 12:33:04.188694 LPDDR4 DRAM CONFIGURATION
4944 12:33:04.191960 ===================================
4945 12:33:04.195143 EX_ROW_EN[0] = 0x0
4946 12:33:04.198569 EX_ROW_EN[1] = 0x0
4947 12:33:04.198684 LP4Y_EN = 0x0
4948 12:33:04.201994 WORK_FSP = 0x0
4949 12:33:04.202094 WL = 0x3
4950 12:33:04.205319 RL = 0x3
4951 12:33:04.205406 BL = 0x2
4952 12:33:04.208742 RPST = 0x0
4953 12:33:04.208818 RD_PRE = 0x0
4954 12:33:04.212064 WR_PRE = 0x1
4955 12:33:04.212153 WR_PST = 0x0
4956 12:33:04.214767 DBI_WR = 0x0
4957 12:33:04.214870 DBI_RD = 0x0
4958 12:33:04.218219 OTF = 0x1
4959 12:33:04.221617 ===================================
4960 12:33:04.224875 ===================================
4961 12:33:04.224977 ANA top config
4962 12:33:04.228263 ===================================
4963 12:33:04.231558 DLL_ASYNC_EN = 0
4964 12:33:04.234741 ALL_SLAVE_EN = 1
4965 12:33:04.234846 NEW_RANK_MODE = 1
4966 12:33:04.238520 DLL_IDLE_MODE = 1
4967 12:33:04.241655 LP45_APHY_COMB_EN = 1
4968 12:33:04.244799 TX_ODT_DIS = 1
4969 12:33:04.247834 NEW_8X_MODE = 1
4970 12:33:04.251570 ===================================
4971 12:33:04.254757 ===================================
4972 12:33:04.257781 data_rate = 1866
4973 12:33:04.257904 CKR = 1
4974 12:33:04.261361 DQ_P2S_RATIO = 8
4975 12:33:04.264675 ===================================
4976 12:33:04.267986 CA_P2S_RATIO = 8
4977 12:33:04.271451 DQ_CA_OPEN = 0
4978 12:33:04.274598 DQ_SEMI_OPEN = 0
4979 12:33:04.274689 CA_SEMI_OPEN = 0
4980 12:33:04.277856 CA_FULL_RATE = 0
4981 12:33:04.281132 DQ_CKDIV4_EN = 1
4982 12:33:04.284715 CA_CKDIV4_EN = 1
4983 12:33:04.287894 CA_PREDIV_EN = 0
4984 12:33:04.291421 PH8_DLY = 0
4985 12:33:04.291508 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4986 12:33:04.294766 DQ_AAMCK_DIV = 4
4987 12:33:04.298113 CA_AAMCK_DIV = 4
4988 12:33:04.301435 CA_ADMCK_DIV = 4
4989 12:33:04.304241 DQ_TRACK_CA_EN = 0
4990 12:33:04.308143 CA_PICK = 933
4991 12:33:04.311532 CA_MCKIO = 933
4992 12:33:04.311632 MCKIO_SEMI = 0
4993 12:33:04.314732 PLL_FREQ = 3732
4994 12:33:04.317833 DQ_UI_PI_RATIO = 32
4995 12:33:04.321311 CA_UI_PI_RATIO = 0
4996 12:33:04.324574 ===================================
4997 12:33:04.327964 ===================================
4998 12:33:04.331255 memory_type:LPDDR4
4999 12:33:04.331371 GP_NUM : 10
5000 12:33:04.334633 SRAM_EN : 1
5001 12:33:04.337916 MD32_EN : 0
5002 12:33:04.341295 ===================================
5003 12:33:04.341369 [ANA_INIT] >>>>>>>>>>>>>>
5004 12:33:04.344442 <<<<<< [CONFIGURE PHASE]: ANA_TX
5005 12:33:04.347733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5006 12:33:04.351037 ===================================
5007 12:33:04.354825 data_rate = 1866,PCW = 0X8f00
5008 12:33:04.357950 ===================================
5009 12:33:04.361029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5010 12:33:04.367874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 12:33:04.371208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 12:33:04.377882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5013 12:33:04.380904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5014 12:33:04.384741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5015 12:33:04.384833 [ANA_INIT] flow start
5016 12:33:04.387930 [ANA_INIT] PLL >>>>>>>>
5017 12:33:04.391103 [ANA_INIT] PLL <<<<<<<<
5018 12:33:04.391215 [ANA_INIT] MIDPI >>>>>>>>
5019 12:33:04.394337 [ANA_INIT] MIDPI <<<<<<<<
5020 12:33:04.397614 [ANA_INIT] DLL >>>>>>>>
5021 12:33:04.397700 [ANA_INIT] flow end
5022 12:33:04.404205 ============ LP4 DIFF to SE enter ============
5023 12:33:04.407564 ============ LP4 DIFF to SE exit ============
5024 12:33:04.410883 [ANA_INIT] <<<<<<<<<<<<<
5025 12:33:04.414256 [Flow] Enable top DCM control >>>>>
5026 12:33:04.414341 [Flow] Enable top DCM control <<<<<
5027 12:33:04.417686 Enable DLL master slave shuffle
5028 12:33:04.424203 ==============================================================
5029 12:33:04.427570 Gating Mode config
5030 12:33:04.430879 ==============================================================
5031 12:33:04.434710 Config description:
5032 12:33:04.444613 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5033 12:33:04.451192 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5034 12:33:04.454411 SELPH_MODE 0: By rank 1: By Phase
5035 12:33:04.460847 ==============================================================
5036 12:33:04.463998 GAT_TRACK_EN = 1
5037 12:33:04.467751 RX_GATING_MODE = 2
5038 12:33:04.470910 RX_GATING_TRACK_MODE = 2
5039 12:33:04.471016 SELPH_MODE = 1
5040 12:33:04.474539 PICG_EARLY_EN = 1
5041 12:33:04.477207 VALID_LAT_VALUE = 1
5042 12:33:04.483963 ==============================================================
5043 12:33:04.487760 Enter into Gating configuration >>>>
5044 12:33:04.490917 Exit from Gating configuration <<<<
5045 12:33:04.494246 Enter into DVFS_PRE_config >>>>>
5046 12:33:04.504463 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5047 12:33:04.507811 Exit from DVFS_PRE_config <<<<<
5048 12:33:04.511147 Enter into PICG configuration >>>>
5049 12:33:04.513835 Exit from PICG configuration <<<<
5050 12:33:04.517231 [RX_INPUT] configuration >>>>>
5051 12:33:04.520546 [RX_INPUT] configuration <<<<<
5052 12:33:04.523763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5053 12:33:04.530433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5054 12:33:04.537619 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 12:33:04.543739 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 12:33:04.547737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5057 12:33:04.553838 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5058 12:33:04.557112 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5059 12:33:04.563975 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5060 12:33:04.567120 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5061 12:33:04.570355 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5062 12:33:04.574013 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5063 12:33:04.580971 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 12:33:04.584372 ===================================
5065 12:33:04.584458 LPDDR4 DRAM CONFIGURATION
5066 12:33:04.587753 ===================================
5067 12:33:04.591158 EX_ROW_EN[0] = 0x0
5068 12:33:04.593761 EX_ROW_EN[1] = 0x0
5069 12:33:04.593846 LP4Y_EN = 0x0
5070 12:33:04.597531 WORK_FSP = 0x0
5071 12:33:04.597616 WL = 0x3
5072 12:33:04.600868 RL = 0x3
5073 12:33:04.600953 BL = 0x2
5074 12:33:04.603802 RPST = 0x0
5075 12:33:04.603915 RD_PRE = 0x0
5076 12:33:04.606887 WR_PRE = 0x1
5077 12:33:04.607002 WR_PST = 0x0
5078 12:33:04.610600 DBI_WR = 0x0
5079 12:33:04.610713 DBI_RD = 0x0
5080 12:33:04.613864 OTF = 0x1
5081 12:33:04.617238 ===================================
5082 12:33:04.620485 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5083 12:33:04.623871 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5084 12:33:04.630457 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5085 12:33:04.633852 ===================================
5086 12:33:04.633979 LPDDR4 DRAM CONFIGURATION
5087 12:33:04.637203 ===================================
5088 12:33:04.640373 EX_ROW_EN[0] = 0x10
5089 12:33:04.643600 EX_ROW_EN[1] = 0x0
5090 12:33:04.643684 LP4Y_EN = 0x0
5091 12:33:04.646921 WORK_FSP = 0x0
5092 12:33:04.647005 WL = 0x3
5093 12:33:04.650216 RL = 0x3
5094 12:33:04.650301 BL = 0x2
5095 12:33:04.653517 RPST = 0x0
5096 12:33:04.653602 RD_PRE = 0x0
5097 12:33:04.657100 WR_PRE = 0x1
5098 12:33:04.657184 WR_PST = 0x0
5099 12:33:04.660407 DBI_WR = 0x0
5100 12:33:04.660491 DBI_RD = 0x0
5101 12:33:04.663629 OTF = 0x1
5102 12:33:04.666666 ===================================
5103 12:33:04.673199 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5104 12:33:04.676386 nWR fixed to 30
5105 12:33:04.680184 [ModeRegInit_LP4] CH0 RK0
5106 12:33:04.680266 [ModeRegInit_LP4] CH0 RK1
5107 12:33:04.683438 [ModeRegInit_LP4] CH1 RK0
5108 12:33:04.686506 [ModeRegInit_LP4] CH1 RK1
5109 12:33:04.686621 match AC timing 9
5110 12:33:04.693193 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5111 12:33:04.696690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5112 12:33:04.699859 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5113 12:33:04.706490 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5114 12:33:04.710067 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5115 12:33:04.710214 ==
5116 12:33:04.713265 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 12:33:04.716314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 12:33:04.716416 ==
5119 12:33:04.723152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 12:33:04.729886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5121 12:33:04.733054 [CA 0] Center 37 (6~68) winsize 63
5122 12:33:04.736557 [CA 1] Center 37 (6~68) winsize 63
5123 12:33:04.739893 [CA 2] Center 34 (4~65) winsize 62
5124 12:33:04.743228 [CA 3] Center 33 (3~64) winsize 62
5125 12:33:04.746644 [CA 4] Center 33 (3~64) winsize 62
5126 12:33:04.749387 [CA 5] Center 32 (2~62) winsize 61
5127 12:33:04.749469
5128 12:33:04.752890 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5129 12:33:04.752973
5130 12:33:04.756080 [CATrainingPosCal] consider 1 rank data
5131 12:33:04.759483 u2DelayCellTimex100 = 270/100 ps
5132 12:33:04.762816 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5133 12:33:04.766144 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5134 12:33:04.769867 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5135 12:33:04.772941 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5136 12:33:04.776153 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5137 12:33:04.779425 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5138 12:33:04.779509
5139 12:33:04.786443 CA PerBit enable=1, Macro0, CA PI delay=32
5140 12:33:04.786529
5141 12:33:04.786596 [CBTSetCACLKResult] CA Dly = 32
5142 12:33:04.789596 CS Dly: 5 (0~36)
5143 12:33:04.789680 ==
5144 12:33:04.792771 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 12:33:04.796077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 12:33:04.796200 ==
5147 12:33:04.802840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5148 12:33:04.809088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5149 12:33:04.812514 [CA 0] Center 37 (6~68) winsize 63
5150 12:33:04.816175 [CA 1] Center 37 (6~68) winsize 63
5151 12:33:04.819312 [CA 2] Center 34 (4~65) winsize 62
5152 12:33:04.822406 [CA 3] Center 34 (3~65) winsize 63
5153 12:33:04.826154 [CA 4] Center 33 (3~63) winsize 61
5154 12:33:04.829220 [CA 5] Center 32 (2~62) winsize 61
5155 12:33:04.829332
5156 12:33:04.832462 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5157 12:33:04.832573
5158 12:33:04.835746 [CATrainingPosCal] consider 2 rank data
5159 12:33:04.839154 u2DelayCellTimex100 = 270/100 ps
5160 12:33:04.842554 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5161 12:33:04.845769 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5162 12:33:04.849064 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5163 12:33:04.852498 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5164 12:33:04.855706 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5165 12:33:04.859697 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5166 12:33:04.862386
5167 12:33:04.865888 CA PerBit enable=1, Macro0, CA PI delay=32
5168 12:33:04.865971
5169 12:33:04.869198 [CBTSetCACLKResult] CA Dly = 32
5170 12:33:04.869281 CS Dly: 5 (0~37)
5171 12:33:04.869346
5172 12:33:04.872603 ----->DramcWriteLeveling(PI) begin...
5173 12:33:04.872686 ==
5174 12:33:04.875961 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 12:33:04.879060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 12:33:04.882727 ==
5177 12:33:04.882804 Write leveling (Byte 0): 31 => 31
5178 12:33:04.885688 Write leveling (Byte 1): 29 => 29
5179 12:33:04.888825 DramcWriteLeveling(PI) end<-----
5180 12:33:04.888917
5181 12:33:04.888981 ==
5182 12:33:04.892419 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 12:33:04.899172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 12:33:04.899273 ==
5185 12:33:04.899346 [Gating] SW mode calibration
5186 12:33:04.908933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5187 12:33:04.912448 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5188 12:33:04.919072 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5189 12:33:04.922445 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 12:33:04.925550 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 12:33:04.929283 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 12:33:04.935583 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 12:33:04.939231 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 12:33:04.942278 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5195 12:33:04.948956 0 14 28 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (1 0)
5196 12:33:04.952258 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5197 12:33:04.955827 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 12:33:04.962470 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 12:33:04.965752 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 12:33:04.969169 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 12:33:04.975292 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 12:33:04.978607 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5203 12:33:04.981946 0 15 28 | B1->B0 | 2525 3636 | 1 0 | (0 0) (0 0)
5204 12:33:04.988414 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5205 12:33:04.992208 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 12:33:04.995294 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 12:33:05.001694 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 12:33:05.005491 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 12:33:05.008551 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 12:33:05.015055 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5211 12:33:05.018384 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5212 12:33:05.021708 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:33:05.028592 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:33:05.031838 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:33:05.035543 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:33:05.041964 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:33:05.045118 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:33:05.048266 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:33:05.055389 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 12:33:05.058682 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 12:33:05.062060 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 12:33:05.065466 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 12:33:05.072297 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 12:33:05.075577 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 12:33:05.078982 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 12:33:05.085575 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5227 12:33:05.088920 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5228 12:33:05.092272 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5229 12:33:05.095648 Total UI for P1: 0, mck2ui 16
5230 12:33:05.098824 best dqsien dly found for B0: ( 1, 2, 26)
5231 12:33:05.105108 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 12:33:05.105202 Total UI for P1: 0, mck2ui 16
5233 12:33:05.111878 best dqsien dly found for B1: ( 1, 3, 0)
5234 12:33:05.114842 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5235 12:33:05.118473 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5236 12:33:05.118548
5237 12:33:05.121793 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5238 12:33:05.125138 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5239 12:33:05.128457 [Gating] SW calibration Done
5240 12:33:05.128533 ==
5241 12:33:05.131814 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 12:33:05.135193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 12:33:05.135319 ==
5244 12:33:05.138608 RX Vref Scan: 0
5245 12:33:05.138690
5246 12:33:05.138749 RX Vref 0 -> 0, step: 1
5247 12:33:05.138807
5248 12:33:05.141799 RX Delay -80 -> 252, step: 8
5249 12:33:05.145029 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5250 12:33:05.151412 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5251 12:33:05.154674 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5252 12:33:05.157967 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5253 12:33:05.161692 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5254 12:33:05.165045 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5255 12:33:05.168346 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5256 12:33:05.174828 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5257 12:33:05.178273 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5258 12:33:05.181600 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5259 12:33:05.185041 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5260 12:33:05.188310 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5261 12:33:05.191563 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5262 12:33:05.197970 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5263 12:33:05.201958 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5264 12:33:05.204654 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5265 12:33:05.204730 ==
5266 12:33:05.208478 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 12:33:05.211604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 12:33:05.211705 ==
5269 12:33:05.214738 DQS Delay:
5270 12:33:05.214809 DQS0 = 0, DQS1 = 0
5271 12:33:05.214877 DQM Delay:
5272 12:33:05.217927 DQM0 = 104, DQM1 = 94
5273 12:33:05.218023 DQ Delay:
5274 12:33:05.221776 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5275 12:33:05.224748 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5276 12:33:05.227827 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5277 12:33:05.231806 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5278 12:33:05.231906
5279 12:33:05.232011
5280 12:33:05.235229 ==
5281 12:33:05.237910 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 12:33:05.241848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 12:33:05.241951 ==
5284 12:33:05.242042
5285 12:33:05.242143
5286 12:33:05.244516 TX Vref Scan disable
5287 12:33:05.244625 == TX Byte 0 ==
5288 12:33:05.251523 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5289 12:33:05.254843 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5290 12:33:05.254942 == TX Byte 1 ==
5291 12:33:05.261346 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5292 12:33:05.264390 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5293 12:33:05.264503 ==
5294 12:33:05.268032 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 12:33:05.271421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 12:33:05.271524 ==
5297 12:33:05.271588
5298 12:33:05.271647
5299 12:33:05.274540 TX Vref Scan disable
5300 12:33:05.277857 == TX Byte 0 ==
5301 12:33:05.281268 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5302 12:33:05.284694 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5303 12:33:05.288062 == TX Byte 1 ==
5304 12:33:05.291249 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5305 12:33:05.294656 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5306 12:33:05.294732
5307 12:33:05.297804 [DATLAT]
5308 12:33:05.297885 Freq=933, CH0 RK0
5309 12:33:05.297948
5310 12:33:05.301152 DATLAT Default: 0xd
5311 12:33:05.301229 0, 0xFFFF, sum = 0
5312 12:33:05.304409 1, 0xFFFF, sum = 0
5313 12:33:05.304489 2, 0xFFFF, sum = 0
5314 12:33:05.307860 3, 0xFFFF, sum = 0
5315 12:33:05.307932 4, 0xFFFF, sum = 0
5316 12:33:05.311236 5, 0xFFFF, sum = 0
5317 12:33:05.311352 6, 0xFFFF, sum = 0
5318 12:33:05.314614 7, 0xFFFF, sum = 0
5319 12:33:05.314715 8, 0xFFFF, sum = 0
5320 12:33:05.317666 9, 0xFFFF, sum = 0
5321 12:33:05.317748 10, 0x0, sum = 1
5322 12:33:05.321291 11, 0x0, sum = 2
5323 12:33:05.321408 12, 0x0, sum = 3
5324 12:33:05.324370 13, 0x0, sum = 4
5325 12:33:05.324462 best_step = 11
5326 12:33:05.324528
5327 12:33:05.324588 ==
5328 12:33:05.328081 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 12:33:05.331203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 12:33:05.334226 ==
5331 12:33:05.334300 RX Vref Scan: 1
5332 12:33:05.334369
5333 12:33:05.337975 RX Vref 0 -> 0, step: 1
5334 12:33:05.338050
5335 12:33:05.341135 RX Delay -53 -> 252, step: 4
5336 12:33:05.341211
5337 12:33:05.344359 Set Vref, RX VrefLevel [Byte0]: 55
5338 12:33:05.344433 [Byte1]: 55
5339 12:33:05.349768
5340 12:33:05.349843 Final RX Vref Byte 0 = 55 to rank0
5341 12:33:05.352947 Final RX Vref Byte 1 = 55 to rank0
5342 12:33:05.356228 Final RX Vref Byte 0 = 55 to rank1
5343 12:33:05.359388 Final RX Vref Byte 1 = 55 to rank1==
5344 12:33:05.363274 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 12:33:05.369687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 12:33:05.369791 ==
5347 12:33:05.369892 DQS Delay:
5348 12:33:05.369982 DQS0 = 0, DQS1 = 0
5349 12:33:05.372969 DQM Delay:
5350 12:33:05.373058 DQM0 = 104, DQM1 = 98
5351 12:33:05.376258 DQ Delay:
5352 12:33:05.379291 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5353 12:33:05.382718 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5354 12:33:05.385935 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5355 12:33:05.389596 DQ12 =100, DQ13 =102, DQ14 =108, DQ15 =106
5356 12:33:05.389678
5357 12:33:05.389742
5358 12:33:05.396329 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5359 12:33:05.399462 CH0 RK0: MR19=505, MR18=332B
5360 12:33:05.406172 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5361 12:33:05.406256
5362 12:33:05.409449 ----->DramcWriteLeveling(PI) begin...
5363 12:33:05.409548 ==
5364 12:33:05.412875 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 12:33:05.416319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 12:33:05.416400 ==
5367 12:33:05.419624 Write leveling (Byte 0): 34 => 34
5368 12:33:05.422842 Write leveling (Byte 1): 29 => 29
5369 12:33:05.425943 DramcWriteLeveling(PI) end<-----
5370 12:33:05.426027
5371 12:33:05.426090 ==
5372 12:33:05.429196 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 12:33:05.436058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 12:33:05.436163 ==
5375 12:33:05.436255 [Gating] SW mode calibration
5376 12:33:05.446034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 12:33:05.449319 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 12:33:05.452846 0 14 0 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5379 12:33:05.459508 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 12:33:05.462700 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 12:33:05.465865 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 12:33:05.472522 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 12:33:05.475863 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 12:33:05.479397 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5385 12:33:05.485826 0 14 28 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
5386 12:33:05.489213 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5387 12:33:05.492602 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 12:33:05.499219 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 12:33:05.502591 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 12:33:05.505821 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 12:33:05.512538 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 12:33:05.515763 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5393 12:33:05.519134 0 15 28 | B1->B0 | 3636 3535 | 0 0 | (0 0) (0 0)
5394 12:33:05.525869 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5395 12:33:05.528654 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 12:33:05.531784 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 12:33:05.539033 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 12:33:05.542230 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 12:33:05.545324 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 12:33:05.552375 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 12:33:05.555498 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5402 12:33:05.558746 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:33:05.565196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:33:05.568790 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:33:05.571941 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:33:05.578394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:33:05.582208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:33:05.585493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:33:05.592024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:33:05.595225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 12:33:05.598694 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 12:33:05.601938 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 12:33:05.608553 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 12:33:05.611874 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 12:33:05.615198 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 12:33:05.621967 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 12:33:05.625411 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5418 12:33:05.628188 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5419 12:33:05.632027 Total UI for P1: 0, mck2ui 16
5420 12:33:05.635261 best dqsien dly found for B1: ( 1, 2, 28)
5421 12:33:05.641769 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 12:33:05.641884 Total UI for P1: 0, mck2ui 16
5423 12:33:05.648712 best dqsien dly found for B0: ( 1, 2, 30)
5424 12:33:05.651690 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5425 12:33:05.654892 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5426 12:33:05.654974
5427 12:33:05.658177 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5428 12:33:05.661513 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5429 12:33:05.665447 [Gating] SW calibration Done
5430 12:33:05.665546 ==
5431 12:33:05.668780 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 12:33:05.672086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 12:33:05.672174 ==
5434 12:33:05.675154 RX Vref Scan: 0
5435 12:33:05.675269
5436 12:33:05.675366 RX Vref 0 -> 0, step: 1
5437 12:33:05.675431
5438 12:33:05.678272 RX Delay -80 -> 252, step: 8
5439 12:33:05.681885 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5440 12:33:05.688583 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5441 12:33:05.691761 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5442 12:33:05.694939 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5443 12:33:05.697995 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5444 12:33:05.701360 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5445 12:33:05.708083 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5446 12:33:05.711423 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5447 12:33:05.714759 iDelay=208, Bit 8, Center 91 (8 ~ 175) 168
5448 12:33:05.717968 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5449 12:33:05.721346 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5450 12:33:05.724591 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5451 12:33:05.731528 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5452 12:33:05.734799 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5453 12:33:05.738159 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5454 12:33:05.740847 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5455 12:33:05.740959 ==
5456 12:33:05.744776 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 12:33:05.747920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 12:33:05.751110 ==
5459 12:33:05.751221 DQS Delay:
5460 12:33:05.751316 DQS0 = 0, DQS1 = 0
5461 12:33:05.754322 DQM Delay:
5462 12:33:05.754439 DQM0 = 105, DQM1 = 95
5463 12:33:05.758177 DQ Delay:
5464 12:33:05.761358 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5465 12:33:05.764636 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5466 12:33:05.767836 DQ8 =91, DQ9 =83, DQ10 =95, DQ11 =91
5467 12:33:05.771145 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5468 12:33:05.771250
5469 12:33:05.771354
5470 12:33:05.771456 ==
5471 12:33:05.774568 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 12:33:05.777860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 12:33:05.777974 ==
5474 12:33:05.778085
5475 12:33:05.778186
5476 12:33:05.781122 TX Vref Scan disable
5477 12:33:05.784236 == TX Byte 0 ==
5478 12:33:05.787915 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5479 12:33:05.791112 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5480 12:33:05.794311 == TX Byte 1 ==
5481 12:33:05.797955 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5482 12:33:05.801061 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5483 12:33:05.801148 ==
5484 12:33:05.804301 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 12:33:05.807512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 12:33:05.807599 ==
5487 12:33:05.810869
5488 12:33:05.810954
5489 12:33:05.811057 TX Vref Scan disable
5490 12:33:05.814287 == TX Byte 0 ==
5491 12:33:05.817636 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5492 12:33:05.824231 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5493 12:33:05.824317 == TX Byte 1 ==
5494 12:33:05.827591 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5495 12:33:05.834143 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5496 12:33:05.834230
5497 12:33:05.834315 [DATLAT]
5498 12:33:05.834415 Freq=933, CH0 RK1
5499 12:33:05.834514
5500 12:33:05.837593 DATLAT Default: 0xb
5501 12:33:05.837678 0, 0xFFFF, sum = 0
5502 12:33:05.840921 1, 0xFFFF, sum = 0
5503 12:33:05.841007 2, 0xFFFF, sum = 0
5504 12:33:05.844340 3, 0xFFFF, sum = 0
5505 12:33:05.847639 4, 0xFFFF, sum = 0
5506 12:33:05.847725 5, 0xFFFF, sum = 0
5507 12:33:05.850808 6, 0xFFFF, sum = 0
5508 12:33:05.850893 7, 0xFFFF, sum = 0
5509 12:33:05.853997 8, 0xFFFF, sum = 0
5510 12:33:05.854083 9, 0xFFFF, sum = 0
5511 12:33:05.857873 10, 0x0, sum = 1
5512 12:33:05.857961 11, 0x0, sum = 2
5513 12:33:05.861119 12, 0x0, sum = 3
5514 12:33:05.861206 13, 0x0, sum = 4
5515 12:33:05.861292 best_step = 11
5516 12:33:05.861373
5517 12:33:05.864318 ==
5518 12:33:05.867451 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 12:33:05.870908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 12:33:05.870994 ==
5521 12:33:05.871080 RX Vref Scan: 0
5522 12:33:05.871159
5523 12:33:05.874054 RX Vref 0 -> 0, step: 1
5524 12:33:05.874137
5525 12:33:05.877477 RX Delay -53 -> 252, step: 4
5526 12:33:05.880758 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5527 12:33:05.887874 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5528 12:33:05.891189 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5529 12:33:05.894371 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5530 12:33:05.897500 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5531 12:33:05.901281 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5532 12:33:05.907632 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5533 12:33:05.910706 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5534 12:33:05.914396 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5535 12:33:05.917651 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5536 12:33:05.920956 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5537 12:33:05.924180 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5538 12:33:05.930772 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5539 12:33:05.934157 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5540 12:33:05.937336 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5541 12:33:05.940710 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5542 12:33:05.940794 ==
5543 12:33:05.944198 Dram Type= 6, Freq= 0, CH_0, rank 1
5544 12:33:05.950926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 12:33:05.951034 ==
5546 12:33:05.951126 DQS Delay:
5547 12:33:05.954279 DQS0 = 0, DQS1 = 0
5548 12:33:05.954400 DQM Delay:
5549 12:33:05.954528 DQM0 = 104, DQM1 = 95
5550 12:33:05.957492 DQ Delay:
5551 12:33:05.960587 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5552 12:33:05.964300 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5553 12:33:05.967475 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =92
5554 12:33:05.970639 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5555 12:33:05.970721
5556 12:33:05.970785
5557 12:33:05.977817 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5558 12:33:05.981154 CH0 RK1: MR19=505, MR18=2A03
5559 12:33:05.987134 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5560 12:33:05.990457 [RxdqsGatingPostProcess] freq 933
5561 12:33:05.997172 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5562 12:33:06.000455 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 12:33:06.000537 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 12:33:06.004201 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 12:33:06.007273 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 12:33:06.010448 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 12:33:06.014209 best DQS1 dly(2T, 0.5T) = (0, 10)
5568 12:33:06.017348 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 12:33:06.020629 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5570 12:33:06.023803 Pre-setting of DQS Precalculation
5571 12:33:06.030351 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5572 12:33:06.030435 ==
5573 12:33:06.033666 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 12:33:06.036948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 12:33:06.037031 ==
5576 12:33:06.043761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 12:33:06.047151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5578 12:33:06.051173 [CA 0] Center 36 (6~67) winsize 62
5579 12:33:06.054626 [CA 1] Center 36 (6~67) winsize 62
5580 12:33:06.058151 [CA 2] Center 35 (5~65) winsize 61
5581 12:33:06.061417 [CA 3] Center 34 (4~64) winsize 61
5582 12:33:06.064580 [CA 4] Center 34 (4~64) winsize 61
5583 12:33:06.067776 [CA 5] Center 33 (3~64) winsize 62
5584 12:33:06.067859
5585 12:33:06.070922 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5586 12:33:06.071004
5587 12:33:06.074035 [CATrainingPosCal] consider 1 rank data
5588 12:33:06.077921 u2DelayCellTimex100 = 270/100 ps
5589 12:33:06.081042 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 12:33:06.087490 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5591 12:33:06.090788 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5592 12:33:06.094054 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5593 12:33:06.097391 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5594 12:33:06.100915 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5595 12:33:06.101075
5596 12:33:06.104226 CA PerBit enable=1, Macro0, CA PI delay=33
5597 12:33:06.104308
5598 12:33:06.107480 [CBTSetCACLKResult] CA Dly = 33
5599 12:33:06.110820 CS Dly: 7 (0~38)
5600 12:33:06.110912 ==
5601 12:33:06.113960 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 12:33:06.117242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 12:33:06.117325 ==
5604 12:33:06.123699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5605 12:33:06.126830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5606 12:33:06.131205 [CA 0] Center 36 (6~67) winsize 62
5607 12:33:06.134660 [CA 1] Center 37 (6~68) winsize 63
5608 12:33:06.137972 [CA 2] Center 35 (4~66) winsize 63
5609 12:33:06.141490 [CA 3] Center 34 (4~65) winsize 62
5610 12:33:06.144180 [CA 4] Center 34 (4~65) winsize 62
5611 12:33:06.147588 [CA 5] Center 33 (3~64) winsize 62
5612 12:33:06.147663
5613 12:33:06.150873 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5614 12:33:06.150946
5615 12:33:06.154317 [CATrainingPosCal] consider 2 rank data
5616 12:33:06.157746 u2DelayCellTimex100 = 270/100 ps
5617 12:33:06.161146 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5618 12:33:06.167667 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5619 12:33:06.170877 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5620 12:33:06.174079 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5621 12:33:06.177711 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5622 12:33:06.180984 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5623 12:33:06.181067
5624 12:33:06.184125 CA PerBit enable=1, Macro0, CA PI delay=33
5625 12:33:06.184205
5626 12:33:06.187757 [CBTSetCACLKResult] CA Dly = 33
5627 12:33:06.187836 CS Dly: 8 (0~40)
5628 12:33:06.187899
5629 12:33:06.191010 ----->DramcWriteLeveling(PI) begin...
5630 12:33:06.194186 ==
5631 12:33:06.197580 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 12:33:06.200966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 12:33:06.201046 ==
5634 12:33:06.204254 Write leveling (Byte 0): 26 => 26
5635 12:33:06.207617 Write leveling (Byte 1): 26 => 26
5636 12:33:06.210708 DramcWriteLeveling(PI) end<-----
5637 12:33:06.210810
5638 12:33:06.210918 ==
5639 12:33:06.214148 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 12:33:06.217342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 12:33:06.217422 ==
5642 12:33:06.221107 [Gating] SW mode calibration
5643 12:33:06.227558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5644 12:33:06.234603 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5645 12:33:06.237633 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 12:33:06.241017 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 12:33:06.247726 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 12:33:06.251094 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 12:33:06.254527 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 12:33:06.257365 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5651 12:33:06.264077 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5652 12:33:06.267501 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5653 12:33:06.270831 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 12:33:06.277229 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 12:33:06.280891 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 12:33:06.283822 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 12:33:06.290770 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 12:33:06.293904 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 12:33:06.297263 0 15 24 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
5660 12:33:06.304150 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5661 12:33:06.307483 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 12:33:06.310239 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 12:33:06.317542 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 12:33:06.320903 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 12:33:06.324170 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 12:33:06.330510 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 12:33:06.334173 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 12:33:06.337173 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:33:06.343890 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:33:06.347163 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:33:06.350177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:33:06.356976 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:33:06.360312 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:33:06.363638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:33:06.370264 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 12:33:06.373571 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 12:33:06.376936 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 12:33:06.383383 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 12:33:06.387319 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 12:33:06.390389 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 12:33:06.394317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 12:33:06.400711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5683 12:33:06.404095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5684 12:33:06.407131 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5685 12:33:06.410373 Total UI for P1: 0, mck2ui 16
5686 12:33:06.413802 best dqsien dly found for B0: ( 1, 2, 26)
5687 12:33:06.420189 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 12:33:06.420275 Total UI for P1: 0, mck2ui 16
5689 12:33:06.426720 best dqsien dly found for B1: ( 1, 2, 24)
5690 12:33:06.430070 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5691 12:33:06.433395 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5692 12:33:06.433472
5693 12:33:06.436648 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5694 12:33:06.440401 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5695 12:33:06.443411 [Gating] SW calibration Done
5696 12:33:06.443501 ==
5697 12:33:06.447126 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 12:33:06.450310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 12:33:06.450395 ==
5700 12:33:06.453460 RX Vref Scan: 0
5701 12:33:06.453544
5702 12:33:06.453611 RX Vref 0 -> 0, step: 1
5703 12:33:06.456679
5704 12:33:06.456767 RX Delay -80 -> 252, step: 8
5705 12:33:06.463212 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5706 12:33:06.466679 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5707 12:33:06.470137 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5708 12:33:06.473473 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5709 12:33:06.476743 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5710 12:33:06.480176 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5711 12:33:06.483483 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5712 12:33:06.489814 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5713 12:33:06.493519 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5714 12:33:06.496693 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5715 12:33:06.500017 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5716 12:33:06.503709 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5717 12:33:06.507083 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5718 12:33:06.513452 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5719 12:33:06.516682 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5720 12:33:06.519981 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5721 12:33:06.520096 ==
5722 12:33:06.523131 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 12:33:06.526465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 12:33:06.529892 ==
5725 12:33:06.530009 DQS Delay:
5726 12:33:06.530108 DQS0 = 0, DQS1 = 0
5727 12:33:06.533288 DQM Delay:
5728 12:33:06.533401 DQM0 = 102, DQM1 = 98
5729 12:33:06.536681 DQ Delay:
5730 12:33:06.539915 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5731 12:33:06.543299 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5732 12:33:06.546576 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5733 12:33:06.549759 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5734 12:33:06.549871
5735 12:33:06.549977
5736 12:33:06.550086 ==
5737 12:33:06.553308 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 12:33:06.556587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 12:33:06.556707 ==
5740 12:33:06.556816
5741 12:33:06.556922
5742 12:33:06.559692 TX Vref Scan disable
5743 12:33:06.562922 == TX Byte 0 ==
5744 12:33:06.566666 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5745 12:33:06.570172 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5746 12:33:06.570249 == TX Byte 1 ==
5747 12:33:06.576911 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5748 12:33:06.580182 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5749 12:33:06.580298 ==
5750 12:33:06.583573 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 12:33:06.586905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 12:33:06.587016 ==
5753 12:33:06.587115
5754 12:33:06.590183
5755 12:33:06.590297 TX Vref Scan disable
5756 12:33:06.593419 == TX Byte 0 ==
5757 12:33:06.596613 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5758 12:33:06.599747 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5759 12:33:06.603435 == TX Byte 1 ==
5760 12:33:06.606624 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5761 12:33:06.609715 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5762 12:33:06.609790
5763 12:33:06.612931 [DATLAT]
5764 12:33:06.613011 Freq=933, CH1 RK0
5765 12:33:06.613078
5766 12:33:06.616262 DATLAT Default: 0xd
5767 12:33:06.616364 0, 0xFFFF, sum = 0
5768 12:33:06.620076 1, 0xFFFF, sum = 0
5769 12:33:06.620151 2, 0xFFFF, sum = 0
5770 12:33:06.623160 3, 0xFFFF, sum = 0
5771 12:33:06.623263 4, 0xFFFF, sum = 0
5772 12:33:06.626463 5, 0xFFFF, sum = 0
5773 12:33:06.626558 6, 0xFFFF, sum = 0
5774 12:33:06.629612 7, 0xFFFF, sum = 0
5775 12:33:06.633102 8, 0xFFFF, sum = 0
5776 12:33:06.633206 9, 0xFFFF, sum = 0
5777 12:33:06.633300 10, 0x0, sum = 1
5778 12:33:06.636388 11, 0x0, sum = 2
5779 12:33:06.636463 12, 0x0, sum = 3
5780 12:33:06.639912 13, 0x0, sum = 4
5781 12:33:06.640014 best_step = 11
5782 12:33:06.640105
5783 12:33:06.640193 ==
5784 12:33:06.643193 Dram Type= 6, Freq= 0, CH_1, rank 0
5785 12:33:06.649766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 12:33:06.649873 ==
5787 12:33:06.649974 RX Vref Scan: 1
5788 12:33:06.650068
5789 12:33:06.653236 RX Vref 0 -> 0, step: 1
5790 12:33:06.653347
5791 12:33:06.656452 RX Delay -45 -> 252, step: 4
5792 12:33:06.656537
5793 12:33:06.659622 Set Vref, RX VrefLevel [Byte0]: 53
5794 12:33:06.663220 [Byte1]: 48
5795 12:33:06.663335
5796 12:33:06.666506 Final RX Vref Byte 0 = 53 to rank0
5797 12:33:06.669534 Final RX Vref Byte 1 = 48 to rank0
5798 12:33:06.673346 Final RX Vref Byte 0 = 53 to rank1
5799 12:33:06.676743 Final RX Vref Byte 1 = 48 to rank1==
5800 12:33:06.679970 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 12:33:06.682641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 12:33:06.682747 ==
5803 12:33:06.686667 DQS Delay:
5804 12:33:06.686769 DQS0 = 0, DQS1 = 0
5805 12:33:06.689976 DQM Delay:
5806 12:33:06.690087 DQM0 = 103, DQM1 = 98
5807 12:33:06.690183 DQ Delay:
5808 12:33:06.693230 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5809 12:33:06.696597 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5810 12:33:06.699788 DQ8 =86, DQ9 =88, DQ10 =100, DQ11 =94
5811 12:33:06.705983 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108
5812 12:33:06.706097
5813 12:33:06.706197
5814 12:33:06.712992 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5815 12:33:06.715974 CH1 RK0: MR19=505, MR18=1A31
5816 12:33:06.723173 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5817 12:33:06.723253
5818 12:33:06.726396 ----->DramcWriteLeveling(PI) begin...
5819 12:33:06.726483 ==
5820 12:33:06.729670 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 12:33:06.732709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 12:33:06.732796 ==
5823 12:33:06.736467 Write leveling (Byte 0): 25 => 25
5824 12:33:06.739819 Write leveling (Byte 1): 27 => 27
5825 12:33:06.742567 DramcWriteLeveling(PI) end<-----
5826 12:33:06.742655
5827 12:33:06.742726 ==
5828 12:33:06.745792 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 12:33:06.749109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 12:33:06.749224 ==
5831 12:33:06.752492 [Gating] SW mode calibration
5832 12:33:06.759177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5833 12:33:06.765897 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5834 12:33:06.769143 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 12:33:06.776001 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 12:33:06.779050 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 12:33:06.782887 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 12:33:06.786291 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 12:33:06.793089 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5840 12:33:06.795751 0 14 24 | B1->B0 | 2e2e 3131 | 0 0 | (0 1) (0 1)
5841 12:33:06.799108 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
5842 12:33:06.806327 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 12:33:06.809686 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 12:33:06.812702 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 12:33:06.819544 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 12:33:06.822658 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 12:33:06.825966 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 12:33:06.832523 0 15 24 | B1->B0 | 3535 2929 | 0 0 | (0 0) (0 0)
5849 12:33:06.835959 0 15 28 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
5850 12:33:06.839162 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 12:33:06.845980 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 12:33:06.849388 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 12:33:06.852692 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 12:33:06.858812 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 12:33:06.862343 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5856 12:33:06.865635 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5857 12:33:06.872205 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:33:06.876103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:33:06.879284 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:33:06.885566 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:33:06.888843 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:33:06.892158 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:33:06.895540 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:33:06.902540 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:33:06.905845 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 12:33:06.909200 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 12:33:06.915462 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 12:33:06.919170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 12:33:06.922449 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 12:33:06.928789 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 12:33:06.932541 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 12:33:06.935819 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5873 12:33:06.942177 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 12:33:06.945460 Total UI for P1: 0, mck2ui 16
5875 12:33:06.949114 best dqsien dly found for B0: ( 1, 2, 24)
5876 12:33:06.949214 Total UI for P1: 0, mck2ui 16
5877 12:33:06.955460 best dqsien dly found for B1: ( 1, 2, 24)
5878 12:33:06.958738 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5879 12:33:06.962129 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5880 12:33:06.962226
5881 12:33:06.965545 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5882 12:33:06.968956 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5883 12:33:06.972159 [Gating] SW calibration Done
5884 12:33:06.972296 ==
5885 12:33:06.975613 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 12:33:06.978868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 12:33:06.978992 ==
5888 12:33:06.982162 RX Vref Scan: 0
5889 12:33:06.982271
5890 12:33:06.982396 RX Vref 0 -> 0, step: 1
5891 12:33:06.982520
5892 12:33:06.985304 RX Delay -80 -> 252, step: 8
5893 12:33:06.992265 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5894 12:33:06.995506 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5895 12:33:06.998751 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5896 12:33:07.002061 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5897 12:33:07.005451 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5898 12:33:07.008821 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5899 12:33:07.012249 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5900 12:33:07.018718 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5901 12:33:07.022310 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5902 12:33:07.025424 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5903 12:33:07.028681 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5904 12:33:07.031770 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5905 12:33:07.035524 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5906 12:33:07.041825 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5907 12:33:07.045117 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5908 12:33:07.048562 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5909 12:33:07.048641 ==
5910 12:33:07.052259 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:33:07.055583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:33:07.055685 ==
5913 12:33:07.058880 DQS Delay:
5914 12:33:07.059000 DQS0 = 0, DQS1 = 0
5915 12:33:07.061970 DQM Delay:
5916 12:33:07.062073 DQM0 = 102, DQM1 = 98
5917 12:33:07.062166 DQ Delay:
5918 12:33:07.065234 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5919 12:33:07.068664 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5920 12:33:07.072139 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5921 12:33:07.078645 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5922 12:33:07.078734
5923 12:33:07.078802
5924 12:33:07.078864 ==
5925 12:33:07.081917 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 12:33:07.085214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 12:33:07.085298 ==
5928 12:33:07.085364
5929 12:33:07.085426
5930 12:33:07.088508 TX Vref Scan disable
5931 12:33:07.088591 == TX Byte 0 ==
5932 12:33:07.095318 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5933 12:33:07.098433 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5934 12:33:07.098516 == TX Byte 1 ==
5935 12:33:07.104936 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5936 12:33:07.108247 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5937 12:33:07.108331 ==
5938 12:33:07.111582 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 12:33:07.114959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 12:33:07.115070 ==
5941 12:33:07.115164
5942 12:33:07.115262
5943 12:33:07.118222 TX Vref Scan disable
5944 12:33:07.121459 == TX Byte 0 ==
5945 12:33:07.124728 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5946 12:33:07.128553 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5947 12:33:07.131543 == TX Byte 1 ==
5948 12:33:07.135436 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5949 12:33:07.138394 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5950 12:33:07.138470
5951 12:33:07.141541 [DATLAT]
5952 12:33:07.141650 Freq=933, CH1 RK1
5953 12:33:07.141742
5954 12:33:07.145258 DATLAT Default: 0xb
5955 12:33:07.145364 0, 0xFFFF, sum = 0
5956 12:33:07.148579 1, 0xFFFF, sum = 0
5957 12:33:07.148680 2, 0xFFFF, sum = 0
5958 12:33:07.151951 3, 0xFFFF, sum = 0
5959 12:33:07.152056 4, 0xFFFF, sum = 0
5960 12:33:07.155193 5, 0xFFFF, sum = 0
5961 12:33:07.155292 6, 0xFFFF, sum = 0
5962 12:33:07.158340 7, 0xFFFF, sum = 0
5963 12:33:07.158446 8, 0xFFFF, sum = 0
5964 12:33:07.161680 9, 0xFFFF, sum = 0
5965 12:33:07.161767 10, 0x0, sum = 1
5966 12:33:07.164892 11, 0x0, sum = 2
5967 12:33:07.164978 12, 0x0, sum = 3
5968 12:33:07.168793 13, 0x0, sum = 4
5969 12:33:07.168879 best_step = 11
5970 12:33:07.168946
5971 12:33:07.169008 ==
5972 12:33:07.171956 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 12:33:07.178735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 12:33:07.178820 ==
5975 12:33:07.178885 RX Vref Scan: 0
5976 12:33:07.178947
5977 12:33:07.181881 RX Vref 0 -> 0, step: 1
5978 12:33:07.181975
5979 12:33:07.185103 RX Delay -45 -> 252, step: 4
5980 12:33:07.188337 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5981 12:33:07.191875 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5982 12:33:07.198506 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5983 12:33:07.201784 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5984 12:33:07.205756 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5985 12:33:07.208245 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5986 12:33:07.211346 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5987 12:33:07.218288 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5988 12:33:07.221543 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5989 12:33:07.224843 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5990 12:33:07.228205 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5991 12:33:07.231568 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5992 12:33:07.234630 iDelay=203, Bit 12, Center 112 (27 ~ 198) 172
5993 12:33:07.241434 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5994 12:33:07.244512 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5995 12:33:07.248180 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5996 12:33:07.248289 ==
5997 12:33:07.251188 Dram Type= 6, Freq= 0, CH_1, rank 1
5998 12:33:07.254357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5999 12:33:07.257960 ==
6000 12:33:07.258041 DQS Delay:
6001 12:33:07.258163 DQS0 = 0, DQS1 = 0
6002 12:33:07.261280 DQM Delay:
6003 12:33:07.261380 DQM0 = 104, DQM1 = 100
6004 12:33:07.264658 DQ Delay:
6005 12:33:07.268028 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
6006 12:33:07.271203 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
6007 12:33:07.274453 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
6008 12:33:07.278213 DQ12 =112, DQ13 =104, DQ14 =106, DQ15 =110
6009 12:33:07.278301
6010 12:33:07.278384
6011 12:33:07.284694 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
6012 12:33:07.287882 CH1 RK1: MR19=504, MR18=2AFD
6013 12:33:07.294525 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
6014 12:33:07.297799 [RxdqsGatingPostProcess] freq 933
6015 12:33:07.304519 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6016 12:33:07.304607 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 12:33:07.307859 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 12:33:07.311599 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 12:33:07.314692 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 12:33:07.317901 best DQS0 dly(2T, 0.5T) = (0, 10)
6021 12:33:07.321210 best DQS1 dly(2T, 0.5T) = (0, 10)
6022 12:33:07.324572 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6023 12:33:07.327959 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6024 12:33:07.331205 Pre-setting of DQS Precalculation
6025 12:33:07.334530 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6026 12:33:07.344886 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6027 12:33:07.351166 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6028 12:33:07.351251
6029 12:33:07.351336
6030 12:33:07.354842 [Calibration Summary] 1866 Mbps
6031 12:33:07.354938 CH 0, Rank 0
6032 12:33:07.358117 SW Impedance : PASS
6033 12:33:07.358256 DUTY Scan : NO K
6034 12:33:07.361281 ZQ Calibration : PASS
6035 12:33:07.364488 Jitter Meter : NO K
6036 12:33:07.364610 CBT Training : PASS
6037 12:33:07.367825 Write leveling : PASS
6038 12:33:07.371138 RX DQS gating : PASS
6039 12:33:07.371254 RX DQ/DQS(RDDQC) : PASS
6040 12:33:07.374546 TX DQ/DQS : PASS
6041 12:33:07.377967 RX DATLAT : PASS
6042 12:33:07.378055 RX DQ/DQS(Engine): PASS
6043 12:33:07.381203 TX OE : NO K
6044 12:33:07.381290 All Pass.
6045 12:33:07.381359
6046 12:33:07.384411 CH 0, Rank 1
6047 12:33:07.384497 SW Impedance : PASS
6048 12:33:07.388235 DUTY Scan : NO K
6049 12:33:07.391177 ZQ Calibration : PASS
6050 12:33:07.391263 Jitter Meter : NO K
6051 12:33:07.394494 CBT Training : PASS
6052 12:33:07.394579 Write leveling : PASS
6053 12:33:07.397903 RX DQS gating : PASS
6054 12:33:07.401282 RX DQ/DQS(RDDQC) : PASS
6055 12:33:07.401367 TX DQ/DQS : PASS
6056 12:33:07.404542 RX DATLAT : PASS
6057 12:33:07.407794 RX DQ/DQS(Engine): PASS
6058 12:33:07.407880 TX OE : NO K
6059 12:33:07.411108 All Pass.
6060 12:33:07.411225
6061 12:33:07.411321 CH 1, Rank 0
6062 12:33:07.414419 SW Impedance : PASS
6063 12:33:07.414525 DUTY Scan : NO K
6064 12:33:07.417755 ZQ Calibration : PASS
6065 12:33:07.420834 Jitter Meter : NO K
6066 12:33:07.420922 CBT Training : PASS
6067 12:33:07.424197 Write leveling : PASS
6068 12:33:07.427981 RX DQS gating : PASS
6069 12:33:07.428067 RX DQ/DQS(RDDQC) : PASS
6070 12:33:07.431463 TX DQ/DQS : PASS
6071 12:33:07.434132 RX DATLAT : PASS
6072 12:33:07.434217 RX DQ/DQS(Engine): PASS
6073 12:33:07.437461 TX OE : NO K
6074 12:33:07.437554 All Pass.
6075 12:33:07.437643
6076 12:33:07.440839 CH 1, Rank 1
6077 12:33:07.440923 SW Impedance : PASS
6078 12:33:07.444131 DUTY Scan : NO K
6079 12:33:07.444215 ZQ Calibration : PASS
6080 12:33:07.447413 Jitter Meter : NO K
6081 12:33:07.450775 CBT Training : PASS
6082 12:33:07.450860 Write leveling : PASS
6083 12:33:07.453840 RX DQS gating : PASS
6084 12:33:07.457579 RX DQ/DQS(RDDQC) : PASS
6085 12:33:07.457697 TX DQ/DQS : PASS
6086 12:33:07.460639 RX DATLAT : PASS
6087 12:33:07.464280 RX DQ/DQS(Engine): PASS
6088 12:33:07.464362 TX OE : NO K
6089 12:33:07.467497 All Pass.
6090 12:33:07.467589
6091 12:33:07.467687 DramC Write-DBI off
6092 12:33:07.470740 PER_BANK_REFRESH: Hybrid Mode
6093 12:33:07.474514 TX_TRACKING: ON
6094 12:33:07.481122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6095 12:33:07.483814 [FAST_K] Save calibration result to emmc
6096 12:33:07.487078 dramc_set_vcore_voltage set vcore to 650000
6097 12:33:07.491078 Read voltage for 400, 6
6098 12:33:07.491187 Vio18 = 0
6099 12:33:07.494390 Vcore = 650000
6100 12:33:07.494493 Vdram = 0
6101 12:33:07.494591 Vddq = 0
6102 12:33:07.497494 Vmddr = 0
6103 12:33:07.500464 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6104 12:33:07.507312 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6105 12:33:07.507436 MEM_TYPE=3, freq_sel=20
6106 12:33:07.510728 sv_algorithm_assistance_LP4_800
6107 12:33:07.514113 ============ PULL DRAM RESETB DOWN ============
6108 12:33:07.520895 ========== PULL DRAM RESETB DOWN end =========
6109 12:33:07.524120 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6110 12:33:07.527249 ===================================
6111 12:33:07.530680 LPDDR4 DRAM CONFIGURATION
6112 12:33:07.534410 ===================================
6113 12:33:07.534494 EX_ROW_EN[0] = 0x0
6114 12:33:07.537143 EX_ROW_EN[1] = 0x0
6115 12:33:07.537253 LP4Y_EN = 0x0
6116 12:33:07.540502 WORK_FSP = 0x0
6117 12:33:07.543903 WL = 0x2
6118 12:33:07.543987 RL = 0x2
6119 12:33:07.547197 BL = 0x2
6120 12:33:07.547307 RPST = 0x0
6121 12:33:07.551097 RD_PRE = 0x0
6122 12:33:07.551181 WR_PRE = 0x1
6123 12:33:07.553854 WR_PST = 0x0
6124 12:33:07.553938 DBI_WR = 0x0
6125 12:33:07.557198 DBI_RD = 0x0
6126 12:33:07.557281 OTF = 0x1
6127 12:33:07.560973 ===================================
6128 12:33:07.564142 ===================================
6129 12:33:07.567192 ANA top config
6130 12:33:07.570863 ===================================
6131 12:33:07.570973 DLL_ASYNC_EN = 0
6132 12:33:07.573900 ALL_SLAVE_EN = 1
6133 12:33:07.577057 NEW_RANK_MODE = 1
6134 12:33:07.580240 DLL_IDLE_MODE = 1
6135 12:33:07.580350 LP45_APHY_COMB_EN = 1
6136 12:33:07.584134 TX_ODT_DIS = 1
6137 12:33:07.586883 NEW_8X_MODE = 1
6138 12:33:07.590748 ===================================
6139 12:33:07.593619 ===================================
6140 12:33:07.596925 data_rate = 800
6141 12:33:07.600171 CKR = 1
6142 12:33:07.603369 DQ_P2S_RATIO = 4
6143 12:33:07.607264 ===================================
6144 12:33:07.607380 CA_P2S_RATIO = 4
6145 12:33:07.610488 DQ_CA_OPEN = 0
6146 12:33:07.613180 DQ_SEMI_OPEN = 1
6147 12:33:07.616587 CA_SEMI_OPEN = 1
6148 12:33:07.619821 CA_FULL_RATE = 0
6149 12:33:07.623118 DQ_CKDIV4_EN = 0
6150 12:33:07.623222 CA_CKDIV4_EN = 1
6151 12:33:07.626514 CA_PREDIV_EN = 0
6152 12:33:07.629811 PH8_DLY = 0
6153 12:33:07.633586 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6154 12:33:07.636609 DQ_AAMCK_DIV = 0
6155 12:33:07.639855 CA_AAMCK_DIV = 0
6156 12:33:07.639958 CA_ADMCK_DIV = 4
6157 12:33:07.643251 DQ_TRACK_CA_EN = 0
6158 12:33:07.646589 CA_PICK = 800
6159 12:33:07.649960 CA_MCKIO = 400
6160 12:33:07.653181 MCKIO_SEMI = 400
6161 12:33:07.656617 PLL_FREQ = 3016
6162 12:33:07.660073 DQ_UI_PI_RATIO = 32
6163 12:33:07.663250 CA_UI_PI_RATIO = 32
6164 12:33:07.666439 ===================================
6165 12:33:07.670118 ===================================
6166 12:33:07.670220 memory_type:LPDDR4
6167 12:33:07.673256 GP_NUM : 10
6168 12:33:07.676424 SRAM_EN : 1
6169 12:33:07.676533 MD32_EN : 0
6170 12:33:07.679534 ===================================
6171 12:33:07.683169 [ANA_INIT] >>>>>>>>>>>>>>
6172 12:33:07.686342 <<<<<< [CONFIGURE PHASE]: ANA_TX
6173 12:33:07.689955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6174 12:33:07.693289 ===================================
6175 12:33:07.693391 data_rate = 800,PCW = 0X7400
6176 12:33:07.696692 ===================================
6177 12:33:07.703480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6178 12:33:07.706190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6179 12:33:07.719956 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6180 12:33:07.723209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6181 12:33:07.726399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6182 12:33:07.729810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6183 12:33:07.733182 [ANA_INIT] flow start
6184 12:33:07.733293 [ANA_INIT] PLL >>>>>>>>
6185 12:33:07.736504 [ANA_INIT] PLL <<<<<<<<
6186 12:33:07.739571 [ANA_INIT] MIDPI >>>>>>>>
6187 12:33:07.742897 [ANA_INIT] MIDPI <<<<<<<<
6188 12:33:07.743010 [ANA_INIT] DLL >>>>>>>>
6189 12:33:07.746018 [ANA_INIT] flow end
6190 12:33:07.749405 ============ LP4 DIFF to SE enter ============
6191 12:33:07.752688 ============ LP4 DIFF to SE exit ============
6192 12:33:07.755987 [ANA_INIT] <<<<<<<<<<<<<
6193 12:33:07.759178 [Flow] Enable top DCM control >>>>>
6194 12:33:07.762509 [Flow] Enable top DCM control <<<<<
6195 12:33:07.765857 Enable DLL master slave shuffle
6196 12:33:07.769262 ==============================================================
6197 12:33:07.772972 Gating Mode config
6198 12:33:07.779251 ==============================================================
6199 12:33:07.779365 Config description:
6200 12:33:07.789759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6201 12:33:07.796094 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6202 12:33:07.802628 SELPH_MODE 0: By rank 1: By Phase
6203 12:33:07.805943 ==============================================================
6204 12:33:07.809248 GAT_TRACK_EN = 0
6205 12:33:07.812962 RX_GATING_MODE = 2
6206 12:33:07.816355 RX_GATING_TRACK_MODE = 2
6207 12:33:07.819517 SELPH_MODE = 1
6208 12:33:07.822810 PICG_EARLY_EN = 1
6209 12:33:07.826219 VALID_LAT_VALUE = 1
6210 12:33:07.829564 ==============================================================
6211 12:33:07.833044 Enter into Gating configuration >>>>
6212 12:33:07.835750 Exit from Gating configuration <<<<
6213 12:33:07.839131 Enter into DVFS_PRE_config >>>>>
6214 12:33:07.852853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6215 12:33:07.856180 Exit from DVFS_PRE_config <<<<<
6216 12:33:07.856289 Enter into PICG configuration >>>>
6217 12:33:07.859586 Exit from PICG configuration <<<<
6218 12:33:07.862701 [RX_INPUT] configuration >>>>>
6219 12:33:07.865978 [RX_INPUT] configuration <<<<<
6220 12:33:07.872631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6221 12:33:07.875689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6222 12:33:07.882699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6223 12:33:07.889482 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6224 12:33:07.895762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6225 12:33:07.902580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6226 12:33:07.905715 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6227 12:33:07.909129 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6228 12:33:07.912497 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6229 12:33:07.919100 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6230 12:33:07.922377 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6231 12:33:07.925757 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 12:33:07.929624 ===================================
6233 12:33:07.932731 LPDDR4 DRAM CONFIGURATION
6234 12:33:07.935964 ===================================
6235 12:33:07.936069 EX_ROW_EN[0] = 0x0
6236 12:33:07.939433 EX_ROW_EN[1] = 0x0
6237 12:33:07.942800 LP4Y_EN = 0x0
6238 12:33:07.942905 WORK_FSP = 0x0
6239 12:33:07.946181 WL = 0x2
6240 12:33:07.946281 RL = 0x2
6241 12:33:07.949414 BL = 0x2
6242 12:33:07.949517 RPST = 0x0
6243 12:33:07.952587 RD_PRE = 0x0
6244 12:33:07.952696 WR_PRE = 0x1
6245 12:33:07.955766 WR_PST = 0x0
6246 12:33:07.955845 DBI_WR = 0x0
6247 12:33:07.959097 DBI_RD = 0x0
6248 12:33:07.959208 OTF = 0x1
6249 12:33:07.962557 ===================================
6250 12:33:07.965833 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6251 12:33:07.972496 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6252 12:33:07.975838 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6253 12:33:07.979186 ===================================
6254 12:33:07.982529 LPDDR4 DRAM CONFIGURATION
6255 12:33:07.985819 ===================================
6256 12:33:07.985904 EX_ROW_EN[0] = 0x10
6257 12:33:07.988997 EX_ROW_EN[1] = 0x0
6258 12:33:07.989082 LP4Y_EN = 0x0
6259 12:33:07.992647 WORK_FSP = 0x0
6260 12:33:07.992732 WL = 0x2
6261 12:33:07.995879 RL = 0x2
6262 12:33:07.995967 BL = 0x2
6263 12:33:07.999205 RPST = 0x0
6264 12:33:08.002264 RD_PRE = 0x0
6265 12:33:08.002348 WR_PRE = 0x1
6266 12:33:08.005569 WR_PST = 0x0
6267 12:33:08.005653 DBI_WR = 0x0
6268 12:33:08.009340 DBI_RD = 0x0
6269 12:33:08.009425 OTF = 0x1
6270 12:33:08.012555 ===================================
6271 12:33:08.019069 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6272 12:33:08.022789 nWR fixed to 30
6273 12:33:08.026132 [ModeRegInit_LP4] CH0 RK0
6274 12:33:08.026217 [ModeRegInit_LP4] CH0 RK1
6275 12:33:08.029476 [ModeRegInit_LP4] CH1 RK0
6276 12:33:08.032647 [ModeRegInit_LP4] CH1 RK1
6277 12:33:08.032753 match AC timing 19
6278 12:33:08.039174 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6279 12:33:08.042578 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6280 12:33:08.045886 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6281 12:33:08.052709 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6282 12:33:08.055869 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6283 12:33:08.055945 ==
6284 12:33:08.059611 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 12:33:08.062780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 12:33:08.062862 ==
6287 12:33:08.069417 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6288 12:33:08.075888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6289 12:33:08.079234 [CA 0] Center 36 (8~64) winsize 57
6290 12:33:08.082558 [CA 1] Center 36 (8~64) winsize 57
6291 12:33:08.085952 [CA 2] Center 36 (8~64) winsize 57
6292 12:33:08.086053 [CA 3] Center 36 (8~64) winsize 57
6293 12:33:08.089259 [CA 4] Center 36 (8~64) winsize 57
6294 12:33:08.092484 [CA 5] Center 36 (8~64) winsize 57
6295 12:33:08.092575
6296 12:33:08.099218 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6297 12:33:08.099303
6298 12:33:08.102854 [CATrainingPosCal] consider 1 rank data
6299 12:33:08.102939 u2DelayCellTimex100 = 270/100 ps
6300 12:33:08.109221 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:33:08.112420 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:33:08.115606 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:33:08.119345 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 12:33:08.122657 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 12:33:08.125968 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 12:33:08.126054
6307 12:33:08.129225 CA PerBit enable=1, Macro0, CA PI delay=36
6308 12:33:08.129311
6309 12:33:08.132514 [CBTSetCACLKResult] CA Dly = 36
6310 12:33:08.135889 CS Dly: 1 (0~32)
6311 12:33:08.135975 ==
6312 12:33:08.139182 Dram Type= 6, Freq= 0, CH_0, rank 1
6313 12:33:08.142294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 12:33:08.142380 ==
6315 12:33:08.148984 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6316 12:33:08.152385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6317 12:33:08.155793 [CA 0] Center 36 (8~64) winsize 57
6318 12:33:08.159111 [CA 1] Center 36 (8~64) winsize 57
6319 12:33:08.162367 [CA 2] Center 36 (8~64) winsize 57
6320 12:33:08.165618 [CA 3] Center 36 (8~64) winsize 57
6321 12:33:08.168887 [CA 4] Center 36 (8~64) winsize 57
6322 12:33:08.172591 [CA 5] Center 36 (8~64) winsize 57
6323 12:33:08.172702
6324 12:33:08.175925 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6325 12:33:08.176011
6326 12:33:08.179157 [CATrainingPosCal] consider 2 rank data
6327 12:33:08.182511 u2DelayCellTimex100 = 270/100 ps
6328 12:33:08.185954 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 12:33:08.189295 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 12:33:08.192709 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 12:33:08.198976 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 12:33:08.202293 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 12:33:08.205931 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 12:33:08.206016
6335 12:33:08.208963 CA PerBit enable=1, Macro0, CA PI delay=36
6336 12:33:08.209049
6337 12:33:08.212326 [CBTSetCACLKResult] CA Dly = 36
6338 12:33:08.212411 CS Dly: 1 (0~32)
6339 12:33:08.212478
6340 12:33:08.215387 ----->DramcWriteLeveling(PI) begin...
6341 12:33:08.215474 ==
6342 12:33:08.219103 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 12:33:08.225435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 12:33:08.225521 ==
6345 12:33:08.228706 Write leveling (Byte 0): 40 => 8
6346 12:33:08.232100 Write leveling (Byte 1): 40 => 8
6347 12:33:08.232178 DramcWriteLeveling(PI) end<-----
6348 12:33:08.232241
6349 12:33:08.235464 ==
6350 12:33:08.238786 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 12:33:08.242070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 12:33:08.242150 ==
6353 12:33:08.245299 [Gating] SW mode calibration
6354 12:33:08.252513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6355 12:33:08.255190 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6356 12:33:08.262000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6357 12:33:08.265350 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6358 12:33:08.269193 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 12:33:08.275403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 12:33:08.278657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 12:33:08.282476 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 12:33:08.289178 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 12:33:08.292492 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 12:33:08.295688 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6365 12:33:08.298960 Total UI for P1: 0, mck2ui 16
6366 12:33:08.302164 best dqsien dly found for B0: ( 0, 14, 24)
6367 12:33:08.305531 Total UI for P1: 0, mck2ui 16
6368 12:33:08.308931 best dqsien dly found for B1: ( 0, 14, 24)
6369 12:33:08.311986 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6370 12:33:08.315144 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6371 12:33:08.315245
6372 12:33:08.322201 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6373 12:33:08.325469 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6374 12:33:08.325551 [Gating] SW calibration Done
6375 12:33:08.328599 ==
6376 12:33:08.328721 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 12:33:08.335501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 12:33:08.335584 ==
6379 12:33:08.335649 RX Vref Scan: 0
6380 12:33:08.335709
6381 12:33:08.338792 RX Vref 0 -> 0, step: 1
6382 12:33:08.338873
6383 12:33:08.342279 RX Delay -410 -> 252, step: 16
6384 12:33:08.344934 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6385 12:33:08.348326 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6386 12:33:08.355288 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6387 12:33:08.358550 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6388 12:33:08.361782 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6389 12:33:08.365195 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6390 12:33:08.371857 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6391 12:33:08.375152 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6392 12:33:08.378068 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6393 12:33:08.381422 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6394 12:33:08.388322 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6395 12:33:08.391743 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6396 12:33:08.394942 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6397 12:33:08.401598 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6398 12:33:08.404342 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6399 12:33:08.407619 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6400 12:33:08.407700 ==
6401 12:33:08.411299 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 12:33:08.414534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:33:08.417466 ==
6404 12:33:08.417606 DQS Delay:
6405 12:33:08.417733 DQS0 = 27, DQS1 = 35
6406 12:33:08.421175 DQM Delay:
6407 12:33:08.421259 DQM0 = 10, DQM1 = 11
6408 12:33:08.424424 DQ Delay:
6409 12:33:08.424508 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6410 12:33:08.427556 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6411 12:33:08.430780 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6412 12:33:08.434510 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6413 12:33:08.434631
6414 12:33:08.434717
6415 12:33:08.437657 ==
6416 12:33:08.440734 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 12:33:08.444153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:33:08.444254 ==
6419 12:33:08.444338
6420 12:33:08.444417
6421 12:33:08.447531 TX Vref Scan disable
6422 12:33:08.447640 == TX Byte 0 ==
6423 12:33:08.450910 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 12:33:08.457469 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 12:33:08.457552 == TX Byte 1 ==
6426 12:33:08.460658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 12:33:08.467016 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 12:33:08.467116 ==
6429 12:33:08.470535 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 12:33:08.473846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 12:33:08.473930 ==
6432 12:33:08.473996
6433 12:33:08.474058
6434 12:33:08.477183 TX Vref Scan disable
6435 12:33:08.477267 == TX Byte 0 ==
6436 12:33:08.480391 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 12:33:08.487318 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 12:33:08.487414 == TX Byte 1 ==
6439 12:33:08.490399 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6440 12:33:08.497416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6441 12:33:08.497500
6442 12:33:08.497566 [DATLAT]
6443 12:33:08.497627 Freq=400, CH0 RK0
6444 12:33:08.497687
6445 12:33:08.500735 DATLAT Default: 0xf
6446 12:33:08.504211 0, 0xFFFF, sum = 0
6447 12:33:08.504298 1, 0xFFFF, sum = 0
6448 12:33:08.506902 2, 0xFFFF, sum = 0
6449 12:33:08.506987 3, 0xFFFF, sum = 0
6450 12:33:08.510293 4, 0xFFFF, sum = 0
6451 12:33:08.510379 5, 0xFFFF, sum = 0
6452 12:33:08.513527 6, 0xFFFF, sum = 0
6453 12:33:08.513612 7, 0xFFFF, sum = 0
6454 12:33:08.516844 8, 0xFFFF, sum = 0
6455 12:33:08.516930 9, 0xFFFF, sum = 0
6456 12:33:08.520517 10, 0xFFFF, sum = 0
6457 12:33:08.520603 11, 0xFFFF, sum = 0
6458 12:33:08.523671 12, 0xFFFF, sum = 0
6459 12:33:08.523757 13, 0x0, sum = 1
6460 12:33:08.527314 14, 0x0, sum = 2
6461 12:33:08.527409 15, 0x0, sum = 3
6462 12:33:08.530440 16, 0x0, sum = 4
6463 12:33:08.530526 best_step = 14
6464 12:33:08.530592
6465 12:33:08.530655 ==
6466 12:33:08.533560 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 12:33:08.536673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 12:33:08.540406 ==
6469 12:33:08.540490 RX Vref Scan: 1
6470 12:33:08.540558
6471 12:33:08.543688 RX Vref 0 -> 0, step: 1
6472 12:33:08.543797
6473 12:33:08.546815 RX Delay -311 -> 252, step: 8
6474 12:33:08.546913
6475 12:33:08.550031 Set Vref, RX VrefLevel [Byte0]: 55
6476 12:33:08.553380 [Byte1]: 55
6477 12:33:08.553464
6478 12:33:08.556889 Final RX Vref Byte 0 = 55 to rank0
6479 12:33:08.560223 Final RX Vref Byte 1 = 55 to rank0
6480 12:33:08.563580 Final RX Vref Byte 0 = 55 to rank1
6481 12:33:08.566736 Final RX Vref Byte 1 = 55 to rank1==
6482 12:33:08.570037 Dram Type= 6, Freq= 0, CH_0, rank 0
6483 12:33:08.573311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 12:33:08.573409 ==
6485 12:33:08.576718 DQS Delay:
6486 12:33:08.576802 DQS0 = 28, DQS1 = 36
6487 12:33:08.580125 DQM Delay:
6488 12:33:08.580211 DQM0 = 11, DQM1 = 13
6489 12:33:08.580278 DQ Delay:
6490 12:33:08.583660 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6491 12:33:08.586827 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6492 12:33:08.590010 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6493 12:33:08.593258 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6494 12:33:08.593375
6495 12:33:08.593473
6496 12:33:08.603091 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6497 12:33:08.603205 CH0 RK0: MR19=C0C, MR18=CAB7
6498 12:33:08.609852 CH0_RK0: MR19=0xC0C, MR18=0xCAB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6499 12:33:08.609937 ==
6500 12:33:08.613899 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 12:33:08.620466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 12:33:08.620552 ==
6503 12:33:08.623673 [Gating] SW mode calibration
6504 12:33:08.629907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6505 12:33:08.633125 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6506 12:33:08.639917 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 12:33:08.643207 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 12:33:08.646809 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 12:33:08.653134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 12:33:08.656414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 12:33:08.659865 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 12:33:08.663278 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 12:33:08.669853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 12:33:08.673284 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 12:33:08.676561 Total UI for P1: 0, mck2ui 16
6516 12:33:08.679882 best dqsien dly found for B0: ( 0, 14, 24)
6517 12:33:08.683141 Total UI for P1: 0, mck2ui 16
6518 12:33:08.686632 best dqsien dly found for B1: ( 0, 14, 24)
6519 12:33:08.690121 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6520 12:33:08.693443 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6521 12:33:08.693530
6522 12:33:08.696763 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6523 12:33:08.703082 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6524 12:33:08.703171 [Gating] SW calibration Done
6525 12:33:08.703278 ==
6526 12:33:08.706263 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 12:33:08.713114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 12:33:08.713200 ==
6529 12:33:08.713286 RX Vref Scan: 0
6530 12:33:08.713366
6531 12:33:08.716503 RX Vref 0 -> 0, step: 1
6532 12:33:08.716588
6533 12:33:08.719716 RX Delay -410 -> 252, step: 16
6534 12:33:08.723123 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6535 12:33:08.726434 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6536 12:33:08.732892 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6537 12:33:08.735967 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6538 12:33:08.739252 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6539 12:33:08.742926 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6540 12:33:08.749298 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6541 12:33:08.752925 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6542 12:33:08.756112 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6543 12:33:08.759253 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6544 12:33:08.766174 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6545 12:33:08.769623 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6546 12:33:08.772836 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6547 12:33:08.776213 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6548 12:33:08.782836 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6549 12:33:08.786177 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6550 12:33:08.786292 ==
6551 12:33:08.788967 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:33:08.792402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:33:08.792513 ==
6554 12:33:08.795766 DQS Delay:
6555 12:33:08.795850 DQS0 = 19, DQS1 = 35
6556 12:33:08.799264 DQM Delay:
6557 12:33:08.799404 DQM0 = 5, DQM1 = 10
6558 12:33:08.799508 DQ Delay:
6559 12:33:08.802692 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6560 12:33:08.806039 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6561 12:33:08.809340 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6562 12:33:08.812616 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6563 12:33:08.812689
6564 12:33:08.812759
6565 12:33:08.812857 ==
6566 12:33:08.815782 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 12:33:08.819007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 12:33:08.822778 ==
6569 12:33:08.822882
6570 12:33:08.822975
6571 12:33:08.823127 TX Vref Scan disable
6572 12:33:08.825580 == TX Byte 0 ==
6573 12:33:08.829500 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6574 12:33:08.832247 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6575 12:33:08.835762 == TX Byte 1 ==
6576 12:33:08.838948 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6577 12:33:08.842685 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6578 12:33:08.842769 ==
6579 12:33:08.845794 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 12:33:08.848793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 12:33:08.852838 ==
6582 12:33:08.852921
6583 12:33:08.852986
6584 12:33:08.853047 TX Vref Scan disable
6585 12:33:08.856119 == TX Byte 0 ==
6586 12:33:08.859340 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6587 12:33:08.862713 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6588 12:33:08.865845 == TX Byte 1 ==
6589 12:33:08.869508 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6590 12:33:08.872227 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6591 12:33:08.872303
6592 12:33:08.872368 [DATLAT]
6593 12:33:08.875522 Freq=400, CH0 RK1
6594 12:33:08.875594
6595 12:33:08.878684 DATLAT Default: 0xe
6596 12:33:08.878763 0, 0xFFFF, sum = 0
6597 12:33:08.882233 1, 0xFFFF, sum = 0
6598 12:33:08.882309 2, 0xFFFF, sum = 0
6599 12:33:08.885450 3, 0xFFFF, sum = 0
6600 12:33:08.885536 4, 0xFFFF, sum = 0
6601 12:33:08.888902 5, 0xFFFF, sum = 0
6602 12:33:08.888979 6, 0xFFFF, sum = 0
6603 12:33:08.892720 7, 0xFFFF, sum = 0
6604 12:33:08.892817 8, 0xFFFF, sum = 0
6605 12:33:08.895389 9, 0xFFFF, sum = 0
6606 12:33:08.895462 10, 0xFFFF, sum = 0
6607 12:33:08.898604 11, 0xFFFF, sum = 0
6608 12:33:08.898687 12, 0xFFFF, sum = 0
6609 12:33:08.901995 13, 0x0, sum = 1
6610 12:33:08.902072 14, 0x0, sum = 2
6611 12:33:08.905542 15, 0x0, sum = 3
6612 12:33:08.905613 16, 0x0, sum = 4
6613 12:33:08.908771 best_step = 14
6614 12:33:08.908855
6615 12:33:08.908922 ==
6616 12:33:08.912116 Dram Type= 6, Freq= 0, CH_0, rank 1
6617 12:33:08.915425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 12:33:08.915509 ==
6619 12:33:08.918574 RX Vref Scan: 0
6620 12:33:08.918648
6621 12:33:08.918715 RX Vref 0 -> 0, step: 1
6622 12:33:08.918779
6623 12:33:08.922278 RX Delay -311 -> 252, step: 8
6624 12:33:08.929744 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6625 12:33:08.933345 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6626 12:33:08.936616 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6627 12:33:08.939827 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6628 12:33:08.947013 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6629 12:33:08.950232 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6630 12:33:08.953378 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6631 12:33:08.956584 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6632 12:33:08.963481 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6633 12:33:08.966607 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6634 12:33:08.969922 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6635 12:33:08.973673 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6636 12:33:08.980139 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6637 12:33:08.983607 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6638 12:33:08.986907 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6639 12:33:08.993555 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6640 12:33:08.993980 ==
6641 12:33:08.996776 Dram Type= 6, Freq= 0, CH_0, rank 1
6642 12:33:09.000156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 12:33:09.000578 ==
6644 12:33:09.000912 DQS Delay:
6645 12:33:09.003439 DQS0 = 24, DQS1 = 32
6646 12:33:09.003859 DQM Delay:
6647 12:33:09.006970 DQM0 = 9, DQM1 = 10
6648 12:33:09.007441 DQ Delay:
6649 12:33:09.010111 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6650 12:33:09.013631 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6651 12:33:09.017127 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6652 12:33:09.020329 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6653 12:33:09.020747
6654 12:33:09.021077
6655 12:33:09.027030 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6656 12:33:09.030092 CH0 RK1: MR19=C0C, MR18=BB5C
6657 12:33:09.036908 CH0_RK1: MR19=0xC0C, MR18=0xBB5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6658 12:33:09.040023 [RxdqsGatingPostProcess] freq 400
6659 12:33:09.043481 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6660 12:33:09.046857 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 12:33:09.050117 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 12:33:09.053592 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 12:33:09.056764 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 12:33:09.059829 best DQS0 dly(2T, 0.5T) = (0, 10)
6665 12:33:09.063581 best DQS1 dly(2T, 0.5T) = (0, 10)
6666 12:33:09.066579 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6667 12:33:09.070319 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6668 12:33:09.073321 Pre-setting of DQS Precalculation
6669 12:33:09.076531 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6670 12:33:09.076954 ==
6671 12:33:09.080150 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 12:33:09.086520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 12:33:09.086945 ==
6674 12:33:09.089885 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6675 12:33:09.096602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6676 12:33:09.100067 [CA 0] Center 36 (8~64) winsize 57
6677 12:33:09.103166 [CA 1] Center 36 (8~64) winsize 57
6678 12:33:09.106611 [CA 2] Center 36 (8~64) winsize 57
6679 12:33:09.110053 [CA 3] Center 36 (8~64) winsize 57
6680 12:33:09.113282 [CA 4] Center 36 (8~64) winsize 57
6681 12:33:09.116648 [CA 5] Center 36 (8~64) winsize 57
6682 12:33:09.117220
6683 12:33:09.119936 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6684 12:33:09.120313
6685 12:33:09.123264 [CATrainingPosCal] consider 1 rank data
6686 12:33:09.126655 u2DelayCellTimex100 = 270/100 ps
6687 12:33:09.130118 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:33:09.133350 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:33:09.136567 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:33:09.139545 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 12:33:09.143221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 12:33:09.146378 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 12:33:09.149766
6694 12:33:09.153028 CA PerBit enable=1, Macro0, CA PI delay=36
6695 12:33:09.153597
6696 12:33:09.156372 [CBTSetCACLKResult] CA Dly = 36
6697 12:33:09.156897 CS Dly: 1 (0~32)
6698 12:33:09.157399 ==
6699 12:33:09.159806 Dram Type= 6, Freq= 0, CH_1, rank 1
6700 12:33:09.163064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 12:33:09.163542 ==
6702 12:33:09.169690 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6703 12:33:09.176401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6704 12:33:09.179518 [CA 0] Center 36 (8~64) winsize 57
6705 12:33:09.183443 [CA 1] Center 36 (8~64) winsize 57
6706 12:33:09.186547 [CA 2] Center 36 (8~64) winsize 57
6707 12:33:09.189744 [CA 3] Center 36 (8~64) winsize 57
6708 12:33:09.192893 [CA 4] Center 36 (8~64) winsize 57
6709 12:33:09.193340 [CA 5] Center 36 (8~64) winsize 57
6710 12:33:09.196222
6711 12:33:09.199523 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6712 12:33:09.200016
6713 12:33:09.202815 [CATrainingPosCal] consider 2 rank data
6714 12:33:09.206145 u2DelayCellTimex100 = 270/100 ps
6715 12:33:09.209287 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 12:33:09.213304 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 12:33:09.215871 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 12:33:09.219371 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 12:33:09.222751 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 12:33:09.225929 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 12:33:09.226350
6722 12:33:09.229346 CA PerBit enable=1, Macro0, CA PI delay=36
6723 12:33:09.229719
6724 12:33:09.232786 [CBTSetCACLKResult] CA Dly = 36
6725 12:33:09.236448 CS Dly: 1 (0~32)
6726 12:33:09.237040
6727 12:33:09.239525 ----->DramcWriteLeveling(PI) begin...
6728 12:33:09.240097 ==
6729 12:33:09.243046 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 12:33:09.246130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 12:33:09.246732 ==
6732 12:33:09.249210 Write leveling (Byte 0): 40 => 8
6733 12:33:09.252963 Write leveling (Byte 1): 40 => 8
6734 12:33:09.256106 DramcWriteLeveling(PI) end<-----
6735 12:33:09.256514
6736 12:33:09.256844 ==
6737 12:33:09.259172 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 12:33:09.262463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 12:33:09.262894 ==
6740 12:33:09.265885 [Gating] SW mode calibration
6741 12:33:09.272879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6742 12:33:09.279268 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6743 12:33:09.282363 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6744 12:33:09.289115 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6745 12:33:09.292290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 12:33:09.296030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 12:33:09.299101 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 12:33:09.305961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 12:33:09.309384 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 12:33:09.312846 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 12:33:09.319302 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6752 12:33:09.322476 Total UI for P1: 0, mck2ui 16
6753 12:33:09.325725 best dqsien dly found for B0: ( 0, 14, 24)
6754 12:33:09.328889 Total UI for P1: 0, mck2ui 16
6755 12:33:09.332234 best dqsien dly found for B1: ( 0, 14, 24)
6756 12:33:09.335612 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6757 12:33:09.339238 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6758 12:33:09.339880
6759 12:33:09.342484 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6760 12:33:09.345731 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6761 12:33:09.349223 [Gating] SW calibration Done
6762 12:33:09.349671 ==
6763 12:33:09.352452 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 12:33:09.355563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 12:33:09.355990 ==
6766 12:33:09.358848 RX Vref Scan: 0
6767 12:33:09.359269
6768 12:33:09.361868 RX Vref 0 -> 0, step: 1
6769 12:33:09.362293
6770 12:33:09.362625 RX Delay -410 -> 252, step: 16
6771 12:33:09.368903 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6772 12:33:09.372305 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6773 12:33:09.375435 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6774 12:33:09.378681 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6775 12:33:09.385781 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6776 12:33:09.388882 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6777 12:33:09.391975 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6778 12:33:09.395760 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6779 12:33:09.401871 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6780 12:33:09.405685 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6781 12:33:09.409047 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6782 12:33:09.412403 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6783 12:33:09.418931 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6784 12:33:09.422460 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6785 12:33:09.425619 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6786 12:33:09.428615 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6787 12:33:09.431964 ==
6788 12:33:09.435277 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 12:33:09.438611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:33:09.439209 ==
6791 12:33:09.439692 DQS Delay:
6792 12:33:09.442204 DQS0 = 35, DQS1 = 35
6793 12:33:09.442781 DQM Delay:
6794 12:33:09.445366 DQM0 = 18, DQM1 = 13
6795 12:33:09.446037 DQ Delay:
6796 12:33:09.448631 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6797 12:33:09.451939 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6798 12:33:09.455200 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6799 12:33:09.458527 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6800 12:33:09.459164
6801 12:33:09.459750
6802 12:33:09.460265 ==
6803 12:33:09.461788 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 12:33:09.465175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:33:09.465809 ==
6806 12:33:09.466392
6807 12:33:09.466928
6808 12:33:09.468992 TX Vref Scan disable
6809 12:33:09.469555 == TX Byte 0 ==
6810 12:33:09.475481 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 12:33:09.478906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 12:33:09.479504 == TX Byte 1 ==
6813 12:33:09.485304 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 12:33:09.488675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 12:33:09.489141 ==
6816 12:33:09.492373 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 12:33:09.495389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 12:33:09.495782 ==
6819 12:33:09.496111
6820 12:33:09.496420
6821 12:33:09.498648 TX Vref Scan disable
6822 12:33:09.499079 == TX Byte 0 ==
6823 12:33:09.505118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 12:33:09.508837 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 12:33:09.509272 == TX Byte 1 ==
6826 12:33:09.515261 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 12:33:09.518605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 12:33:09.519130
6829 12:33:09.519710 [DATLAT]
6830 12:33:09.521873 Freq=400, CH1 RK0
6831 12:33:09.522427
6832 12:33:09.522905 DATLAT Default: 0xf
6833 12:33:09.525275 0, 0xFFFF, sum = 0
6834 12:33:09.525930 1, 0xFFFF, sum = 0
6835 12:33:09.528505 2, 0xFFFF, sum = 0
6836 12:33:09.529073 3, 0xFFFF, sum = 0
6837 12:33:09.531722 4, 0xFFFF, sum = 0
6838 12:33:09.532409 5, 0xFFFF, sum = 0
6839 12:33:09.534904 6, 0xFFFF, sum = 0
6840 12:33:09.538164 7, 0xFFFF, sum = 0
6841 12:33:09.538822 8, 0xFFFF, sum = 0
6842 12:33:09.541580 9, 0xFFFF, sum = 0
6843 12:33:09.542200 10, 0xFFFF, sum = 0
6844 12:33:09.544967 11, 0xFFFF, sum = 0
6845 12:33:09.545540 12, 0xFFFF, sum = 0
6846 12:33:09.548284 13, 0x0, sum = 1
6847 12:33:09.548834 14, 0x0, sum = 2
6848 12:33:09.551685 15, 0x0, sum = 3
6849 12:33:09.552241 16, 0x0, sum = 4
6850 12:33:09.552728 best_step = 14
6851 12:33:09.553204
6852 12:33:09.555696 ==
6853 12:33:09.556218 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 12:33:09.562134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 12:33:09.562637 ==
6856 12:33:09.563135 RX Vref Scan: 1
6857 12:33:09.563669
6858 12:33:09.565411 RX Vref 0 -> 0, step: 1
6859 12:33:09.566001
6860 12:33:09.568475 RX Delay -311 -> 252, step: 8
6861 12:33:09.568585
6862 12:33:09.571260 Set Vref, RX VrefLevel [Byte0]: 53
6863 12:33:09.575181 [Byte1]: 48
6864 12:33:09.578544
6865 12:33:09.578626 Final RX Vref Byte 0 = 53 to rank0
6866 12:33:09.581596 Final RX Vref Byte 1 = 48 to rank0
6867 12:33:09.585306 Final RX Vref Byte 0 = 53 to rank1
6868 12:33:09.588474 Final RX Vref Byte 1 = 48 to rank1==
6869 12:33:09.591757 Dram Type= 6, Freq= 0, CH_1, rank 0
6870 12:33:09.597997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 12:33:09.598121 ==
6872 12:33:09.598252 DQS Delay:
6873 12:33:09.601799 DQS0 = 28, DQS1 = 32
6874 12:33:09.601924 DQM Delay:
6875 12:33:09.602034 DQM0 = 9, DQM1 = 11
6876 12:33:09.604884 DQ Delay:
6877 12:33:09.608040 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6878 12:33:09.608195 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6879 12:33:09.611258 DQ8 =0, DQ9 =4, DQ10 =8, DQ11 =4
6880 12:33:09.615034 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6881 12:33:09.615222
6882 12:33:09.615397
6883 12:33:09.624756 [DQSOSCAuto] RK0, (LSB)MR18= 0x92ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6884 12:33:09.628186 CH1 RK0: MR19=C0C, MR18=92CA
6885 12:33:09.634948 CH1_RK0: MR19=0xC0C, MR18=0x92CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6886 12:33:09.635285 ==
6887 12:33:09.638089 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 12:33:09.641440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 12:33:09.641855 ==
6890 12:33:09.644682 [Gating] SW mode calibration
6891 12:33:09.651892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6892 12:33:09.655242 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6893 12:33:09.661426 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6894 12:33:09.664719 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6895 12:33:09.668657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 12:33:09.674569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 12:33:09.677892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 12:33:09.681782 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 12:33:09.688379 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 12:33:09.691481 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 12:33:09.694653 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6902 12:33:09.697919 Total UI for P1: 0, mck2ui 16
6903 12:33:09.701537 best dqsien dly found for B0: ( 0, 14, 24)
6904 12:33:09.704745 Total UI for P1: 0, mck2ui 16
6905 12:33:09.708571 best dqsien dly found for B1: ( 0, 14, 24)
6906 12:33:09.711686 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6907 12:33:09.714678 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6908 12:33:09.715223
6909 12:33:09.721562 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6910 12:33:09.724588 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6911 12:33:09.725137 [Gating] SW calibration Done
6912 12:33:09.728266 ==
6913 12:33:09.731692 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 12:33:09.734957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 12:33:09.735555 ==
6916 12:33:09.736066 RX Vref Scan: 0
6917 12:33:09.736539
6918 12:33:09.738263 RX Vref 0 -> 0, step: 1
6919 12:33:09.738796
6920 12:33:09.741611 RX Delay -410 -> 252, step: 16
6921 12:33:09.744745 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6922 12:33:09.748407 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6923 12:33:09.754905 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6924 12:33:09.758306 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6925 12:33:09.761707 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6926 12:33:09.765075 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6927 12:33:09.771750 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6928 12:33:09.775141 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6929 12:33:09.778309 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6930 12:33:09.781605 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6931 12:33:09.788318 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6932 12:33:09.791587 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6933 12:33:09.794814 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6934 12:33:09.798063 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6935 12:33:09.804508 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6936 12:33:09.808211 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6937 12:33:09.808737 ==
6938 12:33:09.811283 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:33:09.814874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:33:09.815534 ==
6941 12:33:09.818100 DQS Delay:
6942 12:33:09.818749 DQS0 = 35, DQS1 = 35
6943 12:33:09.821145 DQM Delay:
6944 12:33:09.821805 DQM0 = 18, DQM1 = 13
6945 12:33:09.822418 DQ Delay:
6946 12:33:09.824893 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6947 12:33:09.827957 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6948 12:33:09.831065 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6949 12:33:09.834734 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6950 12:33:09.835251
6951 12:33:09.835684
6952 12:33:09.836222 ==
6953 12:33:09.837798 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 12:33:09.844618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 12:33:09.845215 ==
6956 12:33:09.845739
6957 12:33:09.846225
6958 12:33:09.846723 TX Vref Scan disable
6959 12:33:09.847999 == TX Byte 0 ==
6960 12:33:09.851126 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6961 12:33:09.854530 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6962 12:33:09.857236 == TX Byte 1 ==
6963 12:33:09.861045 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6964 12:33:09.864403 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6965 12:33:09.864515 ==
6966 12:33:09.867701 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 12:33:09.873897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 12:33:09.874018 ==
6969 12:33:09.874121
6970 12:33:09.874222
6971 12:33:09.874318 TX Vref Scan disable
6972 12:33:09.877770 == TX Byte 0 ==
6973 12:33:09.881161 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6974 12:33:09.883907 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6975 12:33:09.887187 == TX Byte 1 ==
6976 12:33:09.891160 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6977 12:33:09.893860 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6978 12:33:09.893969
6979 12:33:09.897248 [DATLAT]
6980 12:33:09.897359 Freq=400, CH1 RK1
6981 12:33:09.897458
6982 12:33:09.900521 DATLAT Default: 0xe
6983 12:33:09.900624 0, 0xFFFF, sum = 0
6984 12:33:09.903779 1, 0xFFFF, sum = 0
6985 12:33:09.903884 2, 0xFFFF, sum = 0
6986 12:33:09.907302 3, 0xFFFF, sum = 0
6987 12:33:09.907414 4, 0xFFFF, sum = 0
6988 12:33:09.910682 5, 0xFFFF, sum = 0
6989 12:33:09.910782 6, 0xFFFF, sum = 0
6990 12:33:09.913868 7, 0xFFFF, sum = 0
6991 12:33:09.913969 8, 0xFFFF, sum = 0
6992 12:33:09.917604 9, 0xFFFF, sum = 0
6993 12:33:09.920689 10, 0xFFFF, sum = 0
6994 12:33:09.920788 11, 0xFFFF, sum = 0
6995 12:33:09.923860 12, 0xFFFF, sum = 0
6996 12:33:09.923946 13, 0x0, sum = 1
6997 12:33:09.927515 14, 0x0, sum = 2
6998 12:33:09.927601 15, 0x0, sum = 3
6999 12:33:09.927668 16, 0x0, sum = 4
7000 12:33:09.930741 best_step = 14
7001 12:33:09.930851
7002 12:33:09.930948 ==
7003 12:33:09.933984 Dram Type= 6, Freq= 0, CH_1, rank 1
7004 12:33:09.937237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7005 12:33:09.937351 ==
7006 12:33:09.940407 RX Vref Scan: 0
7007 12:33:09.940491
7008 12:33:09.943496 RX Vref 0 -> 0, step: 1
7009 12:33:09.943599
7010 12:33:09.943695 RX Delay -311 -> 252, step: 8
7011 12:33:09.952631 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
7012 12:33:09.955382 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
7013 12:33:09.959301 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7014 12:33:09.962539 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
7015 12:33:09.969023 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7016 12:33:09.972350 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
7017 12:33:09.975919 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7018 12:33:09.978456 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7019 12:33:09.985329 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7020 12:33:09.988666 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7021 12:33:09.991943 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
7022 12:33:09.995285 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7023 12:33:10.002038 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7024 12:33:10.005430 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7025 12:33:10.008673 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7026 12:33:10.015178 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7027 12:33:10.015260 ==
7028 12:33:10.018448 Dram Type= 6, Freq= 0, CH_1, rank 1
7029 12:33:10.022332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7030 12:33:10.022415 ==
7031 12:33:10.022480 DQS Delay:
7032 12:33:10.025473 DQS0 = 28, DQS1 = 32
7033 12:33:10.025556 DQM Delay:
7034 12:33:10.028680 DQM0 = 11, DQM1 = 11
7035 12:33:10.028762 DQ Delay:
7036 12:33:10.031851 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7037 12:33:10.035069 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7038 12:33:10.038846 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7039 12:33:10.041889 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7040 12:33:10.041972
7041 12:33:10.042044
7042 12:33:10.048280 [DQSOSCAuto] RK1, (LSB)MR18= 0xc152, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7043 12:33:10.051939 CH1 RK1: MR19=C0C, MR18=C152
7044 12:33:10.058659 CH1_RK1: MR19=0xC0C, MR18=0xC152, DQSOSC=385, MR23=63, INC=398, DEC=265
7045 12:33:10.061891 [RxdqsGatingPostProcess] freq 400
7046 12:33:10.065207 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7047 12:33:10.068581 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 12:33:10.071889 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 12:33:10.075119 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 12:33:10.078503 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 12:33:10.081765 best DQS0 dly(2T, 0.5T) = (0, 10)
7052 12:33:10.084958 best DQS1 dly(2T, 0.5T) = (0, 10)
7053 12:33:10.088310 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7054 12:33:10.091761 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7055 12:33:10.094887 Pre-setting of DQS Precalculation
7056 12:33:10.098276 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7057 12:33:10.108301 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7058 12:33:10.114956 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7059 12:33:10.115036
7060 12:33:10.115121
7061 12:33:10.118268 [Calibration Summary] 800 Mbps
7062 12:33:10.118354 CH 0, Rank 0
7063 12:33:10.121538 SW Impedance : PASS
7064 12:33:10.121629 DUTY Scan : NO K
7065 12:33:10.124824 ZQ Calibration : PASS
7066 12:33:10.128478 Jitter Meter : NO K
7067 12:33:10.128562 CBT Training : PASS
7068 12:33:10.131637 Write leveling : PASS
7069 12:33:10.134829 RX DQS gating : PASS
7070 12:33:10.134917 RX DQ/DQS(RDDQC) : PASS
7071 12:33:10.138002 TX DQ/DQS : PASS
7072 12:33:10.141882 RX DATLAT : PASS
7073 12:33:10.141970 RX DQ/DQS(Engine): PASS
7074 12:33:10.145068 TX OE : NO K
7075 12:33:10.145143 All Pass.
7076 12:33:10.145207
7077 12:33:10.148196 CH 0, Rank 1
7078 12:33:10.148270 SW Impedance : PASS
7079 12:33:10.151398 DUTY Scan : NO K
7080 12:33:10.154637 ZQ Calibration : PASS
7081 12:33:10.154716 Jitter Meter : NO K
7082 12:33:10.158449 CBT Training : PASS
7083 12:33:10.158533 Write leveling : NO K
7084 12:33:10.161234 RX DQS gating : PASS
7085 12:33:10.164591 RX DQ/DQS(RDDQC) : PASS
7086 12:33:10.164676 TX DQ/DQS : PASS
7087 12:33:10.167992 RX DATLAT : PASS
7088 12:33:10.171221 RX DQ/DQS(Engine): PASS
7089 12:33:10.171293 TX OE : NO K
7090 12:33:10.174420 All Pass.
7091 12:33:10.174494
7092 12:33:10.174566 CH 1, Rank 0
7093 12:33:10.178400 SW Impedance : PASS
7094 12:33:10.178492 DUTY Scan : NO K
7095 12:33:10.181651 ZQ Calibration : PASS
7096 12:33:10.184936 Jitter Meter : NO K
7097 12:33:10.185017 CBT Training : PASS
7098 12:33:10.188224 Write leveling : PASS
7099 12:33:10.191546 RX DQS gating : PASS
7100 12:33:10.191637 RX DQ/DQS(RDDQC) : PASS
7101 12:33:10.194866 TX DQ/DQS : PASS
7102 12:33:10.194954 RX DATLAT : PASS
7103 12:33:10.198193 RX DQ/DQS(Engine): PASS
7104 12:33:10.201453 TX OE : NO K
7105 12:33:10.201546 All Pass.
7106 12:33:10.201619
7107 12:33:10.201681 CH 1, Rank 1
7108 12:33:10.204828 SW Impedance : PASS
7109 12:33:10.208190 DUTY Scan : NO K
7110 12:33:10.208266 ZQ Calibration : PASS
7111 12:33:10.211369 Jitter Meter : NO K
7112 12:33:10.214748 CBT Training : PASS
7113 12:33:10.214822 Write leveling : NO K
7114 12:33:10.218184 RX DQS gating : PASS
7115 12:33:10.221465 RX DQ/DQS(RDDQC) : PASS
7116 12:33:10.221547 TX DQ/DQS : PASS
7117 12:33:10.224692 RX DATLAT : PASS
7118 12:33:10.228056 RX DQ/DQS(Engine): PASS
7119 12:33:10.228135 TX OE : NO K
7120 12:33:10.231450 All Pass.
7121 12:33:10.231531
7122 12:33:10.231601 DramC Write-DBI off
7123 12:33:10.234583 PER_BANK_REFRESH: Hybrid Mode
7124 12:33:10.234654 TX_TRACKING: ON
7125 12:33:10.244574 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7126 12:33:10.248270 [FAST_K] Save calibration result to emmc
7127 12:33:10.251448 dramc_set_vcore_voltage set vcore to 725000
7128 12:33:10.254655 Read voltage for 1600, 0
7129 12:33:10.254741 Vio18 = 0
7130 12:33:10.258373 Vcore = 725000
7131 12:33:10.258461 Vdram = 0
7132 12:33:10.258557 Vddq = 0
7133 12:33:10.258639 Vmddr = 0
7134 12:33:10.264600 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7135 12:33:10.271188 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7136 12:33:10.271271 MEM_TYPE=3, freq_sel=13
7137 12:33:10.274457 sv_algorithm_assistance_LP4_3733
7138 12:33:10.277750 ============ PULL DRAM RESETB DOWN ============
7139 12:33:10.284437 ========== PULL DRAM RESETB DOWN end =========
7140 12:33:10.288280 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7141 12:33:10.291069 ===================================
7142 12:33:10.294933 LPDDR4 DRAM CONFIGURATION
7143 12:33:10.297687 ===================================
7144 12:33:10.297757 EX_ROW_EN[0] = 0x0
7145 12:33:10.300998 EX_ROW_EN[1] = 0x0
7146 12:33:10.304865 LP4Y_EN = 0x0
7147 12:33:10.304936 WORK_FSP = 0x1
7148 12:33:10.308269 WL = 0x5
7149 12:33:10.308339 RL = 0x5
7150 12:33:10.311578 BL = 0x2
7151 12:33:10.311645 RPST = 0x0
7152 12:33:10.314847 RD_PRE = 0x0
7153 12:33:10.314916 WR_PRE = 0x1
7154 12:33:10.318191 WR_PST = 0x1
7155 12:33:10.318259 DBI_WR = 0x0
7156 12:33:10.321512 DBI_RD = 0x0
7157 12:33:10.321577 OTF = 0x1
7158 12:33:10.324961 ===================================
7159 12:33:10.328268 ===================================
7160 12:33:10.331407 ANA top config
7161 12:33:10.334759 ===================================
7162 12:33:10.334830 DLL_ASYNC_EN = 0
7163 12:33:10.338005 ALL_SLAVE_EN = 0
7164 12:33:10.341329 NEW_RANK_MODE = 1
7165 12:33:10.344440 DLL_IDLE_MODE = 1
7166 12:33:10.347436 LP45_APHY_COMB_EN = 1
7167 12:33:10.347511 TX_ODT_DIS = 0
7168 12:33:10.351215 NEW_8X_MODE = 1
7169 12:33:10.354285 ===================================
7170 12:33:10.357522 ===================================
7171 12:33:10.361319 data_rate = 3200
7172 12:33:10.364490 CKR = 1
7173 12:33:10.367731 DQ_P2S_RATIO = 8
7174 12:33:10.370904 ===================================
7175 12:33:10.371002 CA_P2S_RATIO = 8
7176 12:33:10.374011 DQ_CA_OPEN = 0
7177 12:33:10.377839 DQ_SEMI_OPEN = 0
7178 12:33:10.381274 CA_SEMI_OPEN = 0
7179 12:33:10.384334 CA_FULL_RATE = 0
7180 12:33:10.387529 DQ_CKDIV4_EN = 0
7181 12:33:10.387984 CA_CKDIV4_EN = 0
7182 12:33:10.390917 CA_PREDIV_EN = 0
7183 12:33:10.394666 PH8_DLY = 12
7184 12:33:10.397870 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7185 12:33:10.401214 DQ_AAMCK_DIV = 4
7186 12:33:10.404583 CA_AAMCK_DIV = 4
7187 12:33:10.405016 CA_ADMCK_DIV = 4
7188 12:33:10.407290 DQ_TRACK_CA_EN = 0
7189 12:33:10.411116 CA_PICK = 1600
7190 12:33:10.414454 CA_MCKIO = 1600
7191 12:33:10.417992 MCKIO_SEMI = 0
7192 12:33:10.420605 PLL_FREQ = 3068
7193 12:33:10.424220 DQ_UI_PI_RATIO = 32
7194 12:33:10.427550 CA_UI_PI_RATIO = 0
7195 12:33:10.430891 ===================================
7196 12:33:10.431277 ===================================
7197 12:33:10.434130 memory_type:LPDDR4
7198 12:33:10.437796 GP_NUM : 10
7199 12:33:10.438227 SRAM_EN : 1
7200 12:33:10.441028 MD32_EN : 0
7201 12:33:10.443749 ===================================
7202 12:33:10.447832 [ANA_INIT] >>>>>>>>>>>>>>
7203 12:33:10.450992 <<<<<< [CONFIGURE PHASE]: ANA_TX
7204 12:33:10.454061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7205 12:33:10.457110 ===================================
7206 12:33:10.457532 data_rate = 3200,PCW = 0X7600
7207 12:33:10.460727 ===================================
7208 12:33:10.464014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7209 12:33:10.471047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7210 12:33:10.477270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7211 12:33:10.480618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7212 12:33:10.484098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7213 12:33:10.487222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7214 12:33:10.490635 [ANA_INIT] flow start
7215 12:33:10.494100 [ANA_INIT] PLL >>>>>>>>
7216 12:33:10.494559 [ANA_INIT] PLL <<<<<<<<
7217 12:33:10.497451 [ANA_INIT] MIDPI >>>>>>>>
7218 12:33:10.501111 [ANA_INIT] MIDPI <<<<<<<<
7219 12:33:10.501562 [ANA_INIT] DLL >>>>>>>>
7220 12:33:10.504359 [ANA_INIT] DLL <<<<<<<<
7221 12:33:10.507209 [ANA_INIT] flow end
7222 12:33:10.510663 ============ LP4 DIFF to SE enter ============
7223 12:33:10.514379 ============ LP4 DIFF to SE exit ============
7224 12:33:10.517876 [ANA_INIT] <<<<<<<<<<<<<
7225 12:33:10.521103 [Flow] Enable top DCM control >>>>>
7226 12:33:10.523961 [Flow] Enable top DCM control <<<<<
7227 12:33:10.527279 Enable DLL master slave shuffle
7228 12:33:10.530011 ==============================================================
7229 12:33:10.533385 Gating Mode config
7230 12:33:10.540162 ==============================================================
7231 12:33:10.540246 Config description:
7232 12:33:10.550130 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7233 12:33:10.557022 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7234 12:33:10.560360 SELPH_MODE 0: By rank 1: By Phase
7235 12:33:10.566795 ==============================================================
7236 12:33:10.570379 GAT_TRACK_EN = 1
7237 12:33:10.573436 RX_GATING_MODE = 2
7238 12:33:10.576699 RX_GATING_TRACK_MODE = 2
7239 12:33:10.580546 SELPH_MODE = 1
7240 12:33:10.583601 PICG_EARLY_EN = 1
7241 12:33:10.586743 VALID_LAT_VALUE = 1
7242 12:33:10.589780 ==============================================================
7243 12:33:10.593532 Enter into Gating configuration >>>>
7244 12:33:10.596961 Exit from Gating configuration <<<<
7245 12:33:10.600834 Enter into DVFS_PRE_config >>>>>
7246 12:33:10.610090 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7247 12:33:10.613340 Exit from DVFS_PRE_config <<<<<
7248 12:33:10.616788 Enter into PICG configuration >>>>
7249 12:33:10.619963 Exit from PICG configuration <<<<
7250 12:33:10.623230 [RX_INPUT] configuration >>>>>
7251 12:33:10.626547 [RX_INPUT] configuration <<<<<
7252 12:33:10.633123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7253 12:33:10.636568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7254 12:33:10.643260 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7255 12:33:10.649820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7256 12:33:10.656384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7257 12:33:10.663442 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7258 12:33:10.666881 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7259 12:33:10.670302 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7260 12:33:10.673453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7261 12:33:10.679534 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7262 12:33:10.683176 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7263 12:33:10.686345 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 12:33:10.690026 ===================================
7265 12:33:10.693219 LPDDR4 DRAM CONFIGURATION
7266 12:33:10.696784 ===================================
7267 12:33:10.697336 EX_ROW_EN[0] = 0x0
7268 12:33:10.699948 EX_ROW_EN[1] = 0x0
7269 12:33:10.703023 LP4Y_EN = 0x0
7270 12:33:10.703471 WORK_FSP = 0x1
7271 12:33:10.706453 WL = 0x5
7272 12:33:10.706890 RL = 0x5
7273 12:33:10.709750 BL = 0x2
7274 12:33:10.710189 RPST = 0x0
7275 12:33:10.712927 RD_PRE = 0x0
7276 12:33:10.713352 WR_PRE = 0x1
7277 12:33:10.716680 WR_PST = 0x1
7278 12:33:10.717100 DBI_WR = 0x0
7279 12:33:10.719997 DBI_RD = 0x0
7280 12:33:10.720455 OTF = 0x1
7281 12:33:10.723142 ===================================
7282 12:33:10.726359 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7283 12:33:10.732574 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7284 12:33:10.736025 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7285 12:33:10.739556 ===================================
7286 12:33:10.742947 LPDDR4 DRAM CONFIGURATION
7287 12:33:10.746292 ===================================
7288 12:33:10.746379 EX_ROW_EN[0] = 0x10
7289 12:33:10.749663 EX_ROW_EN[1] = 0x0
7290 12:33:10.749745 LP4Y_EN = 0x0
7291 12:33:10.752883 WORK_FSP = 0x1
7292 12:33:10.752965 WL = 0x5
7293 12:33:10.756101 RL = 0x5
7294 12:33:10.759545 BL = 0x2
7295 12:33:10.759627 RPST = 0x0
7296 12:33:10.762699 RD_PRE = 0x0
7297 12:33:10.762781 WR_PRE = 0x1
7298 12:33:10.765775 WR_PST = 0x1
7299 12:33:10.765857 DBI_WR = 0x0
7300 12:33:10.769221 DBI_RD = 0x0
7301 12:33:10.769303 OTF = 0x1
7302 12:33:10.772583 ===================================
7303 12:33:10.779122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7304 12:33:10.779205 ==
7305 12:33:10.782425 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 12:33:10.785663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7307 12:33:10.785746 ==
7308 12:33:10.788772 [Duty_Offset_Calibration]
7309 12:33:10.792723 B0:2 B1:1 CA:1
7310 12:33:10.792806
7311 12:33:10.795812 [DutyScan_Calibration_Flow] k_type=0
7312 12:33:10.803981
7313 12:33:10.804063 ==CLK 0==
7314 12:33:10.807785 Final CLK duty delay cell = 0
7315 12:33:10.810815 [0] MAX Duty = 5187%(X100), DQS PI = 22
7316 12:33:10.814175 [0] MIN Duty = 4876%(X100), DQS PI = 0
7317 12:33:10.814258 [0] AVG Duty = 5031%(X100)
7318 12:33:10.814324
7319 12:33:10.817504 CH0 CLK Duty spec in!! Max-Min= 311%
7320 12:33:10.824859 [DutyScan_Calibration_Flow] ====Done====
7321 12:33:10.824947
7322 12:33:10.827860 [DutyScan_Calibration_Flow] k_type=1
7323 12:33:10.843311
7324 12:33:10.843433 ==DQS 0 ==
7325 12:33:10.846856 Final DQS duty delay cell = -4
7326 12:33:10.850070 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7327 12:33:10.853395 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7328 12:33:10.856789 [-4] AVG Duty = 4906%(X100)
7329 12:33:10.856885
7330 12:33:10.856961 ==DQS 1 ==
7331 12:33:10.860083 Final DQS duty delay cell = 0
7332 12:33:10.863288 [0] MAX Duty = 5187%(X100), DQS PI = 20
7333 12:33:10.866877 [0] MIN Duty = 5031%(X100), DQS PI = 52
7334 12:33:10.870011 [0] AVG Duty = 5109%(X100)
7335 12:33:10.870134
7336 12:33:10.873466 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7337 12:33:10.873603
7338 12:33:10.876801 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7339 12:33:10.880093 [DutyScan_Calibration_Flow] ====Done====
7340 12:33:10.880247
7341 12:33:10.883564 [DutyScan_Calibration_Flow] k_type=3
7342 12:33:10.899941
7343 12:33:10.900264 ==DQM 0 ==
7344 12:33:10.903859 Final DQM duty delay cell = 0
7345 12:33:10.906951 [0] MAX Duty = 5218%(X100), DQS PI = 32
7346 12:33:10.910095 [0] MIN Duty = 4907%(X100), DQS PI = 56
7347 12:33:10.913790 [0] AVG Duty = 5062%(X100)
7348 12:33:10.914216
7349 12:33:10.914549 ==DQM 1 ==
7350 12:33:10.917049 Final DQM duty delay cell = -4
7351 12:33:10.920215 [-4] MAX Duty = 4969%(X100), DQS PI = 0
7352 12:33:10.923465 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7353 12:33:10.926776 [-4] AVG Duty = 4906%(X100)
7354 12:33:10.927192
7355 12:33:10.930168 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7356 12:33:10.930581
7357 12:33:10.933497 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7358 12:33:10.936699 [DutyScan_Calibration_Flow] ====Done====
7359 12:33:10.937106
7360 12:33:10.940304 [DutyScan_Calibration_Flow] k_type=2
7361 12:33:10.958031
7362 12:33:10.958574 ==DQ 0 ==
7363 12:33:10.960818 Final DQ duty delay cell = 0
7364 12:33:10.964082 [0] MAX Duty = 5062%(X100), DQS PI = 26
7365 12:33:10.967433 [0] MIN Duty = 4907%(X100), DQS PI = 0
7366 12:33:10.967836 [0] AVG Duty = 4984%(X100)
7367 12:33:10.971106
7368 12:33:10.971593 ==DQ 1 ==
7369 12:33:10.974444 Final DQ duty delay cell = 0
7370 12:33:10.977618 [0] MAX Duty = 5156%(X100), DQS PI = 22
7371 12:33:10.980832 [0] MIN Duty = 4938%(X100), DQS PI = 34
7372 12:33:10.981277 [0] AVG Duty = 5047%(X100)
7373 12:33:10.984322
7374 12:33:10.987638 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7375 12:33:10.988071
7376 12:33:10.990805 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7377 12:33:10.993964 [DutyScan_Calibration_Flow] ====Done====
7378 12:33:10.994454 ==
7379 12:33:10.997658 Dram Type= 6, Freq= 0, CH_1, rank 0
7380 12:33:11.000997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7381 12:33:11.001418 ==
7382 12:33:11.004218 [Duty_Offset_Calibration]
7383 12:33:11.004649 B0:1 B1:0 CA:0
7384 12:33:11.004985
7385 12:33:11.007439 [DutyScan_Calibration_Flow] k_type=0
7386 12:33:11.017206
7387 12:33:11.017679 ==CLK 0==
7388 12:33:11.020461 Final CLK duty delay cell = -4
7389 12:33:11.023640 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7390 12:33:11.026925 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7391 12:33:11.030001 [-4] AVG Duty = 4937%(X100)
7392 12:33:11.030400
7393 12:33:11.033509 CH1 CLK Duty spec in!! Max-Min= 125%
7394 12:33:11.036952 [DutyScan_Calibration_Flow] ====Done====
7395 12:33:11.037370
7396 12:33:11.040140 [DutyScan_Calibration_Flow] k_type=1
7397 12:33:11.056521
7398 12:33:11.057030 ==DQS 0 ==
7399 12:33:11.059781 Final DQS duty delay cell = 0
7400 12:33:11.063195 [0] MAX Duty = 5094%(X100), DQS PI = 18
7401 12:33:11.065870 [0] MIN Duty = 4875%(X100), DQS PI = 0
7402 12:33:11.069443 [0] AVG Duty = 4984%(X100)
7403 12:33:11.069862
7404 12:33:11.070183 ==DQS 1 ==
7405 12:33:11.072901 Final DQS duty delay cell = -4
7406 12:33:11.075989 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7407 12:33:11.079193 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7408 12:33:11.082918 [-4] AVG Duty = 4875%(X100)
7409 12:33:11.083361
7410 12:33:11.085743 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7411 12:33:11.086340
7412 12:33:11.089267 CH1 DQS 1 Duty spec in!! Max-Min= 250%
7413 12:33:11.092710 [DutyScan_Calibration_Flow] ====Done====
7414 12:33:11.093130
7415 12:33:11.095931 [DutyScan_Calibration_Flow] k_type=3
7416 12:33:11.113330
7417 12:33:11.113748 ==DQM 0 ==
7418 12:33:11.116843 Final DQM duty delay cell = 0
7419 12:33:11.120010 [0] MAX Duty = 5218%(X100), DQS PI = 18
7420 12:33:11.123797 [0] MIN Duty = 4969%(X100), DQS PI = 48
7421 12:33:11.124218 [0] AVG Duty = 5093%(X100)
7422 12:33:11.127136
7423 12:33:11.127597 ==DQM 1 ==
7424 12:33:11.130202 Final DQM duty delay cell = 0
7425 12:33:11.133991 [0] MAX Duty = 5093%(X100), DQS PI = 18
7426 12:33:11.137351 [0] MIN Duty = 4907%(X100), DQS PI = 52
7427 12:33:11.137772 [0] AVG Duty = 5000%(X100)
7428 12:33:11.140656
7429 12:33:11.143520 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7430 12:33:11.143638
7431 12:33:11.146642 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7432 12:33:11.149998 [DutyScan_Calibration_Flow] ====Done====
7433 12:33:11.150080
7434 12:33:11.153215 [DutyScan_Calibration_Flow] k_type=2
7435 12:33:11.169771
7436 12:33:11.169857 ==DQ 0 ==
7437 12:33:11.172992 Final DQ duty delay cell = -4
7438 12:33:11.175721 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7439 12:33:11.179008 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7440 12:33:11.182369 [-4] AVG Duty = 4968%(X100)
7441 12:33:11.182450
7442 12:33:11.182515 ==DQ 1 ==
7443 12:33:11.186098 Final DQ duty delay cell = 0
7444 12:33:11.189145 [0] MAX Duty = 5124%(X100), DQS PI = 16
7445 12:33:11.192408 [0] MIN Duty = 4938%(X100), DQS PI = 10
7446 12:33:11.195821 [0] AVG Duty = 5031%(X100)
7447 12:33:11.195902
7448 12:33:11.199393 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7449 12:33:11.199475
7450 12:33:11.202714 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7451 12:33:11.206001 [DutyScan_Calibration_Flow] ====Done====
7452 12:33:11.209177 nWR fixed to 30
7453 12:33:11.212383 [ModeRegInit_LP4] CH0 RK0
7454 12:33:11.212465 [ModeRegInit_LP4] CH0 RK1
7455 12:33:11.215568 [ModeRegInit_LP4] CH1 RK0
7456 12:33:11.219455 [ModeRegInit_LP4] CH1 RK1
7457 12:33:11.219536 match AC timing 5
7458 12:33:11.225571 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7459 12:33:11.229475 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7460 12:33:11.232798 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7461 12:33:11.239173 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7462 12:33:11.242382 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7463 12:33:11.242464 [MiockJmeterHQA]
7464 12:33:11.242527
7465 12:33:11.245726 [DramcMiockJmeter] u1RxGatingPI = 0
7466 12:33:11.248886 0 : 4252, 4027
7467 12:33:11.248995 4 : 4362, 4137
7468 12:33:11.252217 8 : 4252, 4027
7469 12:33:11.252300 12 : 4253, 4026
7470 12:33:11.252365 16 : 4252, 4027
7471 12:33:11.255569 20 : 4253, 4026
7472 12:33:11.255652 24 : 4255, 4030
7473 12:33:11.258916 28 : 4252, 4027
7474 12:33:11.258998 32 : 4363, 4137
7475 12:33:11.262321 36 : 4363, 4138
7476 12:33:11.262404 40 : 4253, 4026
7477 12:33:11.265408 44 : 4252, 4027
7478 12:33:11.265491 48 : 4252, 4026
7479 12:33:11.265588 52 : 4365, 4140
7480 12:33:11.268765 56 : 4252, 4027
7481 12:33:11.268847 60 : 4363, 4137
7482 12:33:11.272281 64 : 4253, 4029
7483 12:33:11.272363 68 : 4250, 4026
7484 12:33:11.275556 72 : 4250, 4026
7485 12:33:11.275645 76 : 4252, 4030
7486 12:33:11.278862 80 : 4250, 4027
7487 12:33:11.278958 84 : 4250, 4025
7488 12:33:11.279033 88 : 4363, 124
7489 12:33:11.282338 92 : 4361, 0
7490 12:33:11.282433 96 : 4252, 0
7491 12:33:11.282508 100 : 4250, 0
7492 12:33:11.285640 104 : 4252, 0
7493 12:33:11.285743 108 : 4250, 0
7494 12:33:11.288928 112 : 4360, 0
7495 12:33:11.289076 116 : 4361, 0
7496 12:33:11.289204 120 : 4250, 0
7497 12:33:11.292123 124 : 4250, 0
7498 12:33:11.292235 128 : 4250, 0
7499 12:33:11.295277 132 : 4363, 0
7500 12:33:11.295419 136 : 4253, 0
7501 12:33:11.295517 140 : 4249, 0
7502 12:33:11.299048 144 : 4250, 0
7503 12:33:11.299228 148 : 4250, 0
7504 12:33:11.302427 152 : 4249, 0
7505 12:33:11.302563 156 : 4252, 0
7506 12:33:11.302671 160 : 4252, 0
7507 12:33:11.305780 164 : 4360, 0
7508 12:33:11.305933 168 : 4361, 0
7509 12:33:11.306054 172 : 4250, 0
7510 12:33:11.309201 176 : 4360, 0
7511 12:33:11.309376 180 : 4360, 0
7512 12:33:11.311915 184 : 4250, 0
7513 12:33:11.312090 188 : 4250, 0
7514 12:33:11.312229 192 : 4250, 0
7515 12:33:11.315617 196 : 4252, 0
7516 12:33:11.315823 200 : 4363, 0
7517 12:33:11.318791 204 : 4250, 1427
7518 12:33:11.318874 208 : 4250, 4000
7519 12:33:11.321953 212 : 4250, 4027
7520 12:33:11.322036 216 : 4250, 4027
7521 12:33:11.325034 220 : 4249, 4027
7522 12:33:11.325127 224 : 4250, 4026
7523 12:33:11.328801 228 : 4253, 4029
7524 12:33:11.328884 232 : 4252, 4030
7525 12:33:11.328949 236 : 4249, 4027
7526 12:33:11.331867 240 : 4360, 4137
7527 12:33:11.331950 244 : 4363, 4137
7528 12:33:11.334968 248 : 4250, 4027
7529 12:33:11.335051 252 : 4363, 4140
7530 12:33:11.338913 256 : 4250, 4027
7531 12:33:11.338996 260 : 4250, 4026
7532 12:33:11.342040 264 : 4253, 4029
7533 12:33:11.342122 268 : 4252, 4030
7534 12:33:11.345205 272 : 4249, 4027
7535 12:33:11.345288 276 : 4252, 4029
7536 12:33:11.348717 280 : 4250, 4027
7537 12:33:11.348825 284 : 4252, 4030
7538 12:33:11.348905 288 : 4250, 4027
7539 12:33:11.351948 292 : 4360, 4137
7540 12:33:11.352031 296 : 4361, 4137
7541 12:33:11.355132 300 : 4250, 4027
7542 12:33:11.355221 304 : 4363, 4140
7543 12:33:11.358479 308 : 4250, 3968
7544 12:33:11.358574 312 : 4250, 1963
7545 12:33:11.358649
7546 12:33:11.361656 MIOCK jitter meter ch=0
7547 12:33:11.361750
7548 12:33:11.365054 1T = (312-88) = 224 dly cells
7549 12:33:11.371843 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7550 12:33:11.371956 ==
7551 12:33:11.375466 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 12:33:11.378780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 12:33:11.378958 ==
7554 12:33:11.385088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 12:33:11.388477 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 12:33:11.391913 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 12:33:11.398420 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 12:33:11.407452 [CA 0] Center 43 (12~74) winsize 63
7559 12:33:11.410883 [CA 1] Center 43 (13~74) winsize 62
7560 12:33:11.414223 [CA 2] Center 38 (9~68) winsize 60
7561 12:33:11.417555 [CA 3] Center 38 (8~68) winsize 61
7562 12:33:11.420976 [CA 4] Center 37 (7~67) winsize 61
7563 12:33:11.424070 [CA 5] Center 36 (7~65) winsize 59
7564 12:33:11.424568
7565 12:33:11.427180 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7566 12:33:11.427655
7567 12:33:11.430698 [CATrainingPosCal] consider 1 rank data
7568 12:33:11.434091 u2DelayCellTimex100 = 290/100 ps
7569 12:33:11.437342 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7570 12:33:11.444279 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7571 12:33:11.447243 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7572 12:33:11.450578 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7573 12:33:11.453758 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7574 12:33:11.457853 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7575 12:33:11.458493
7576 12:33:11.460332 CA PerBit enable=1, Macro0, CA PI delay=36
7577 12:33:11.460742
7578 12:33:11.463647 [CBTSetCACLKResult] CA Dly = 36
7579 12:33:11.464277 CS Dly: 9 (0~40)
7580 12:33:11.470203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 12:33:11.473401 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 12:33:11.473484 ==
7583 12:33:11.476720 Dram Type= 6, Freq= 0, CH_0, rank 1
7584 12:33:11.479823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 12:33:11.479933 ==
7586 12:33:11.486705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7587 12:33:11.490092 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7588 12:33:11.496803 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7589 12:33:11.500194 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7590 12:33:11.510098 [CA 0] Center 42 (12~73) winsize 62
7591 12:33:11.513231 [CA 1] Center 42 (12~73) winsize 62
7592 12:33:11.516689 [CA 2] Center 38 (8~68) winsize 61
7593 12:33:11.520124 [CA 3] Center 37 (8~67) winsize 60
7594 12:33:11.523468 [CA 4] Center 36 (6~66) winsize 61
7595 12:33:11.526706 [CA 5] Center 35 (5~65) winsize 61
7596 12:33:11.526777
7597 12:33:11.529946 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7598 12:33:11.530052
7599 12:33:11.533831 [CATrainingPosCal] consider 2 rank data
7600 12:33:11.536941 u2DelayCellTimex100 = 290/100 ps
7601 12:33:11.540059 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7602 12:33:11.547172 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7603 12:33:11.550206 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7604 12:33:11.553414 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7605 12:33:11.556720 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7606 12:33:11.559845 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7607 12:33:11.559960
7608 12:33:11.563247 CA PerBit enable=1, Macro0, CA PI delay=36
7609 12:33:11.563320
7610 12:33:11.566590 [CBTSetCACLKResult] CA Dly = 36
7611 12:33:11.569901 CS Dly: 10 (0~42)
7612 12:33:11.573271 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7613 12:33:11.576616 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7614 12:33:11.576693
7615 12:33:11.579912 ----->DramcWriteLeveling(PI) begin...
7616 12:33:11.579994 ==
7617 12:33:11.583261 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 12:33:11.586498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 12:33:11.589968 ==
7620 12:33:11.590049 Write leveling (Byte 0): 35 => 35
7621 12:33:11.593149 Write leveling (Byte 1): 29 => 29
7622 12:33:11.596692 DramcWriteLeveling(PI) end<-----
7623 12:33:11.596784
7624 12:33:11.596861 ==
7625 12:33:11.600108 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 12:33:11.606490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 12:33:11.606581 ==
7628 12:33:11.609836 [Gating] SW mode calibration
7629 12:33:11.616582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7630 12:33:11.619794 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7631 12:33:11.626709 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:33:11.630082 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7633 12:33:11.632795 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7634 12:33:11.639808 1 4 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7635 12:33:11.642884 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7636 12:33:11.646086 1 4 20 | B1->B0 | 3333 3535 | 1 0 | (1 1) (0 0)
7637 12:33:11.652988 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 12:33:11.656158 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 12:33:11.659226 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 12:33:11.663061 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 12:33:11.669706 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7642 12:33:11.672717 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7643 12:33:11.676046 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7644 12:33:11.682809 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7645 12:33:11.686403 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7646 12:33:11.689853 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7647 12:33:11.696509 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7648 12:33:11.699278 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7649 12:33:11.702927 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7650 12:33:11.709535 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7651 12:33:11.712802 1 6 16 | B1->B0 | 2626 4645 | 0 1 | (0 0) (0 0)
7652 12:33:11.716074 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7653 12:33:11.722766 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 12:33:11.726330 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 12:33:11.729445 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 12:33:11.736402 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 12:33:11.739538 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 12:33:11.742820 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7659 12:33:11.749313 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7660 12:33:11.752452 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7661 12:33:11.755710 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 12:33:11.762244 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 12:33:11.766062 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 12:33:11.769200 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 12:33:11.775701 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 12:33:11.778838 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 12:33:11.782661 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 12:33:11.789287 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:33:11.792561 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:33:11.795348 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:33:11.799218 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:33:11.805397 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:33:11.808829 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7674 12:33:11.812090 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7675 12:33:11.818685 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7676 12:33:11.822189 Total UI for P1: 0, mck2ui 16
7677 12:33:11.825557 best dqsien dly found for B0: ( 1, 9, 10)
7678 12:33:11.828822 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 12:33:11.832162 Total UI for P1: 0, mck2ui 16
7680 12:33:11.835369 best dqsien dly found for B1: ( 1, 9, 16)
7681 12:33:11.845454 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7682 12:33:11.845561 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7683 12:33:11.845630
7684 12:33:11.845879 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7685 12:33:11.852269 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7686 12:33:11.852365 [Gating] SW calibration Done
7687 12:33:11.852465 ==
7688 12:33:11.855418 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 12:33:11.861967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 12:33:11.862101 ==
7691 12:33:11.862172 RX Vref Scan: 0
7692 12:33:11.862234
7693 12:33:11.865265 RX Vref 0 -> 0, step: 1
7694 12:33:11.865349
7695 12:33:11.868442 RX Delay 0 -> 252, step: 8
7696 12:33:11.872321 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7697 12:33:11.875529 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7698 12:33:11.878754 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7699 12:33:11.881915 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7700 12:33:11.888453 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7701 12:33:11.891871 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7702 12:33:11.895235 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7703 12:33:11.898707 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7704 12:33:11.902051 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7705 12:33:11.908694 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7706 12:33:11.912153 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7707 12:33:11.915534 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7708 12:33:11.918886 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7709 12:33:11.922110 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7710 12:33:11.928871 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7711 12:33:11.931669 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7712 12:33:11.931781 ==
7713 12:33:11.935027 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 12:33:11.938402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 12:33:11.938508 ==
7716 12:33:11.941792 DQS Delay:
7717 12:33:11.941905 DQS0 = 0, DQS1 = 0
7718 12:33:11.942001 DQM Delay:
7719 12:33:11.945242 DQM0 = 137, DQM1 = 130
7720 12:33:11.945329 DQ Delay:
7721 12:33:11.948551 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7722 12:33:11.951686 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7723 12:33:11.955442 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7724 12:33:11.961957 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7725 12:33:11.962062
7726 12:33:11.962155
7727 12:33:11.962244 ==
7728 12:33:11.965247 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 12:33:11.968535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 12:33:11.968634 ==
7731 12:33:11.968704
7732 12:33:11.968768
7733 12:33:11.971776 TX Vref Scan disable
7734 12:33:11.971882 == TX Byte 0 ==
7735 12:33:11.978252 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7736 12:33:11.981858 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7737 12:33:11.981975 == TX Byte 1 ==
7738 12:33:11.988654 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7739 12:33:11.991958 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7740 12:33:11.992038 ==
7741 12:33:11.995260 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 12:33:11.998676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 12:33:11.998758 ==
7744 12:33:12.011321
7745 12:33:12.014640 TX Vref early break, caculate TX vref
7746 12:33:12.018058 TX Vref=16, minBit 7, minWin=22, winSum=378
7747 12:33:12.021461 TX Vref=18, minBit 1, minWin=23, winSum=387
7748 12:33:12.024590 TX Vref=20, minBit 0, minWin=24, winSum=399
7749 12:33:12.027914 TX Vref=22, minBit 0, minWin=25, winSum=412
7750 12:33:12.031243 TX Vref=24, minBit 1, minWin=25, winSum=421
7751 12:33:12.038179 TX Vref=26, minBit 6, minWin=25, winSum=428
7752 12:33:12.041433 TX Vref=28, minBit 6, minWin=24, winSum=420
7753 12:33:12.044585 TX Vref=30, minBit 6, minWin=24, winSum=410
7754 12:33:12.047845 TX Vref=32, minBit 0, minWin=24, winSum=400
7755 12:33:12.099503 [TxChooseVref] Worse bit 6, Min win 25, Win sum 428, Final Vref 26
7756 12:33:12.099693
7757 12:33:12.099794 Final TX Range 0 Vref 26
7758 12:33:12.099886
7759 12:33:12.099975 ==
7760 12:33:12.100071 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 12:33:12.100162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 12:33:12.100250 ==
7763 12:33:12.100336
7764 12:33:12.100421
7765 12:33:12.100505 TX Vref Scan disable
7766 12:33:12.100594 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7767 12:33:12.100680 == TX Byte 0 ==
7768 12:33:12.100765 u2DelayCellOfst[0]=10 cells (3 PI)
7769 12:33:12.100849 u2DelayCellOfst[1]=13 cells (4 PI)
7770 12:33:12.100933 u2DelayCellOfst[2]=10 cells (3 PI)
7771 12:33:12.101017 u2DelayCellOfst[3]=10 cells (3 PI)
7772 12:33:12.101101 u2DelayCellOfst[4]=6 cells (2 PI)
7773 12:33:12.101189 u2DelayCellOfst[5]=0 cells (0 PI)
7774 12:33:12.101274 u2DelayCellOfst[6]=16 cells (5 PI)
7775 12:33:12.101374 u2DelayCellOfst[7]=13 cells (4 PI)
7776 12:33:12.104621 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7777 12:33:12.107975 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7778 12:33:12.108086 == TX Byte 1 ==
7779 12:33:12.110733 u2DelayCellOfst[8]=0 cells (0 PI)
7780 12:33:12.113914 u2DelayCellOfst[9]=3 cells (1 PI)
7781 12:33:12.117705 u2DelayCellOfst[10]=6 cells (2 PI)
7782 12:33:12.121032 u2DelayCellOfst[11]=3 cells (1 PI)
7783 12:33:12.123892 u2DelayCellOfst[12]=10 cells (3 PI)
7784 12:33:12.127207 u2DelayCellOfst[13]=13 cells (4 PI)
7785 12:33:12.130514 u2DelayCellOfst[14]=13 cells (4 PI)
7786 12:33:12.133876 u2DelayCellOfst[15]=10 cells (3 PI)
7787 12:33:12.137274 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7788 12:33:12.140687 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7789 12:33:12.144154 DramC Write-DBI on
7790 12:33:12.144295 ==
7791 12:33:12.147954 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 12:33:12.150777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 12:33:12.150998 ==
7794 12:33:12.151204
7795 12:33:12.151408
7796 12:33:12.154119 TX Vref Scan disable
7797 12:33:12.157438 == TX Byte 0 ==
7798 12:33:12.160887 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7799 12:33:12.163973 == TX Byte 1 ==
7800 12:33:12.167374 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7801 12:33:12.167560 DramC Write-DBI off
7802 12:33:12.167706
7803 12:33:12.171144 [DATLAT]
7804 12:33:12.171401 Freq=1600, CH0 RK0
7805 12:33:12.171568
7806 12:33:12.174243 DATLAT Default: 0xf
7807 12:33:12.174469 0, 0xFFFF, sum = 0
7808 12:33:12.177338 1, 0xFFFF, sum = 0
7809 12:33:12.177596 2, 0xFFFF, sum = 0
7810 12:33:12.180609 3, 0xFFFF, sum = 0
7811 12:33:12.180871 4, 0xFFFF, sum = 0
7812 12:33:12.184063 5, 0xFFFF, sum = 0
7813 12:33:12.184274 6, 0xFFFF, sum = 0
7814 12:33:12.187265 7, 0xFFFF, sum = 0
7815 12:33:12.191086 8, 0xFFFF, sum = 0
7816 12:33:12.191277 9, 0xFFFF, sum = 0
7817 12:33:12.194223 10, 0xFFFF, sum = 0
7818 12:33:12.194430 11, 0xFFFF, sum = 0
7819 12:33:12.197056 12, 0xFFFF, sum = 0
7820 12:33:12.197261 13, 0xFFFF, sum = 0
7821 12:33:12.201019 14, 0x0, sum = 1
7822 12:33:12.201214 15, 0x0, sum = 2
7823 12:33:12.204149 16, 0x0, sum = 3
7824 12:33:12.204342 17, 0x0, sum = 4
7825 12:33:12.204535 best_step = 15
7826 12:33:12.207484
7827 12:33:12.207673 ==
7828 12:33:12.210808 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 12:33:12.214282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 12:33:12.214508 ==
7831 12:33:12.214734 RX Vref Scan: 1
7832 12:33:12.214947
7833 12:33:12.217720 Set Vref Range= 24 -> 127
7834 12:33:12.217944
7835 12:33:12.221022 RX Vref 24 -> 127, step: 1
7836 12:33:12.221291
7837 12:33:12.224169 RX Delay 27 -> 252, step: 4
7838 12:33:12.224449
7839 12:33:12.227517 Set Vref, RX VrefLevel [Byte0]: 24
7840 12:33:12.230703 [Byte1]: 24
7841 12:33:12.230982
7842 12:33:12.233828 Set Vref, RX VrefLevel [Byte0]: 25
7843 12:33:12.237295 [Byte1]: 25
7844 12:33:12.237544
7845 12:33:12.240794 Set Vref, RX VrefLevel [Byte0]: 26
7846 12:33:12.244028 [Byte1]: 26
7847 12:33:12.247433
7848 12:33:12.247752 Set Vref, RX VrefLevel [Byte0]: 27
7849 12:33:12.250936 [Byte1]: 27
7850 12:33:12.254922
7851 12:33:12.255269 Set Vref, RX VrefLevel [Byte0]: 28
7852 12:33:12.258250 [Byte1]: 28
7853 12:33:12.262739
7854 12:33:12.263010 Set Vref, RX VrefLevel [Byte0]: 29
7855 12:33:12.265302 [Byte1]: 29
7856 12:33:12.269939
7857 12:33:12.270121 Set Vref, RX VrefLevel [Byte0]: 30
7858 12:33:12.273053 [Byte1]: 30
7859 12:33:12.277482
7860 12:33:12.277676 Set Vref, RX VrefLevel [Byte0]: 31
7861 12:33:12.280605 [Byte1]: 31
7862 12:33:12.285089
7863 12:33:12.285225 Set Vref, RX VrefLevel [Byte0]: 32
7864 12:33:12.288200 [Byte1]: 32
7865 12:33:12.292238
7866 12:33:12.292341 Set Vref, RX VrefLevel [Byte0]: 33
7867 12:33:12.295579 [Byte1]: 33
7868 12:33:12.300046
7869 12:33:12.300143 Set Vref, RX VrefLevel [Byte0]: 34
7870 12:33:12.303285 [Byte1]: 34
7871 12:33:12.307153
7872 12:33:12.307275 Set Vref, RX VrefLevel [Byte0]: 35
7873 12:33:12.310907 [Byte1]: 35
7874 12:33:12.315226
7875 12:33:12.315364 Set Vref, RX VrefLevel [Byte0]: 36
7876 12:33:12.318028 [Byte1]: 36
7877 12:33:12.322797
7878 12:33:12.322889 Set Vref, RX VrefLevel [Byte0]: 37
7879 12:33:12.325511 [Byte1]: 37
7880 12:33:12.330178
7881 12:33:12.330279 Set Vref, RX VrefLevel [Byte0]: 38
7882 12:33:12.333704 [Byte1]: 38
7883 12:33:12.337424
7884 12:33:12.337536 Set Vref, RX VrefLevel [Byte0]: 39
7885 12:33:12.340930 [Byte1]: 39
7886 12:33:12.344894
7887 12:33:12.345005 Set Vref, RX VrefLevel [Byte0]: 40
7888 12:33:12.348164 [Byte1]: 40
7889 12:33:12.352934
7890 12:33:12.353018 Set Vref, RX VrefLevel [Byte0]: 41
7891 12:33:12.355673 [Byte1]: 41
7892 12:33:12.360244
7893 12:33:12.360329 Set Vref, RX VrefLevel [Byte0]: 42
7894 12:33:12.363548 [Byte1]: 42
7895 12:33:12.367575
7896 12:33:12.367659 Set Vref, RX VrefLevel [Byte0]: 43
7897 12:33:12.371012 [Byte1]: 43
7898 12:33:12.374924
7899 12:33:12.375008 Set Vref, RX VrefLevel [Byte0]: 44
7900 12:33:12.378153 [Byte1]: 44
7901 12:33:12.382645
7902 12:33:12.382729 Set Vref, RX VrefLevel [Byte0]: 45
7903 12:33:12.385728 [Byte1]: 45
7904 12:33:12.390084
7905 12:33:12.390211 Set Vref, RX VrefLevel [Byte0]: 46
7906 12:33:12.393827 [Byte1]: 46
7907 12:33:12.397686
7908 12:33:12.397802 Set Vref, RX VrefLevel [Byte0]: 47
7909 12:33:12.401037 [Byte1]: 47
7910 12:33:12.405486
7911 12:33:12.405599 Set Vref, RX VrefLevel [Byte0]: 48
7912 12:33:12.408620 [Byte1]: 48
7913 12:33:12.412657
7914 12:33:12.412735 Set Vref, RX VrefLevel [Byte0]: 49
7915 12:33:12.416468 [Byte1]: 49
7916 12:33:12.420308
7917 12:33:12.420418 Set Vref, RX VrefLevel [Byte0]: 50
7918 12:33:12.423510 [Byte1]: 50
7919 12:33:12.427698
7920 12:33:12.427809 Set Vref, RX VrefLevel [Byte0]: 51
7921 12:33:12.431697 [Byte1]: 51
7922 12:33:12.435663
7923 12:33:12.435771 Set Vref, RX VrefLevel [Byte0]: 52
7924 12:33:12.438994 [Byte1]: 52
7925 12:33:12.442846
7926 12:33:12.442959 Set Vref, RX VrefLevel [Byte0]: 53
7927 12:33:12.446241 [Byte1]: 53
7928 12:33:12.450867
7929 12:33:12.450945 Set Vref, RX VrefLevel [Byte0]: 54
7930 12:33:12.454123 [Byte1]: 54
7931 12:33:12.458128
7932 12:33:12.458219 Set Vref, RX VrefLevel [Byte0]: 55
7933 12:33:12.461561 [Byte1]: 55
7934 12:33:12.465539
7935 12:33:12.465625 Set Vref, RX VrefLevel [Byte0]: 56
7936 12:33:12.468703 [Byte1]: 56
7937 12:33:12.473457
7938 12:33:12.473568 Set Vref, RX VrefLevel [Byte0]: 57
7939 12:33:12.476292 [Byte1]: 57
7940 12:33:12.480841
7941 12:33:12.480925 Set Vref, RX VrefLevel [Byte0]: 58
7942 12:33:12.483940 [Byte1]: 58
7943 12:33:12.488347
7944 12:33:12.488455 Set Vref, RX VrefLevel [Byte0]: 59
7945 12:33:12.491521 [Byte1]: 59
7946 12:33:12.495821
7947 12:33:12.495912 Set Vref, RX VrefLevel [Byte0]: 60
7948 12:33:12.498998 [Byte1]: 60
7949 12:33:12.503473
7950 12:33:12.503580 Set Vref, RX VrefLevel [Byte0]: 61
7951 12:33:12.506364 [Byte1]: 61
7952 12:33:12.510851
7953 12:33:12.510957 Set Vref, RX VrefLevel [Byte0]: 62
7954 12:33:12.514097 [Byte1]: 62
7955 12:33:12.518641
7956 12:33:12.518753 Set Vref, RX VrefLevel [Byte0]: 63
7957 12:33:12.521863 [Byte1]: 63
7958 12:33:12.525716
7959 12:33:12.525825 Set Vref, RX VrefLevel [Byte0]: 64
7960 12:33:12.528830 [Byte1]: 64
7961 12:33:12.533363
7962 12:33:12.533481 Set Vref, RX VrefLevel [Byte0]: 65
7963 12:33:12.536774 [Byte1]: 65
7964 12:33:12.540838
7965 12:33:12.540942 Set Vref, RX VrefLevel [Byte0]: 66
7966 12:33:12.544105 [Byte1]: 66
7967 12:33:12.548423
7968 12:33:12.548535 Set Vref, RX VrefLevel [Byte0]: 67
7969 12:33:12.551794 [Byte1]: 67
7970 12:33:12.555861
7971 12:33:12.555964 Set Vref, RX VrefLevel [Byte0]: 68
7972 12:33:12.559166 [Byte1]: 68
7973 12:33:12.563322
7974 12:33:12.563417 Set Vref, RX VrefLevel [Byte0]: 69
7975 12:33:12.566675 [Byte1]: 69
7976 12:33:12.570739
7977 12:33:12.570822 Set Vref, RX VrefLevel [Byte0]: 70
7978 12:33:12.574614 [Byte1]: 70
7979 12:33:12.578471
7980 12:33:12.578555 Set Vref, RX VrefLevel [Byte0]: 71
7981 12:33:12.581779 [Byte1]: 71
7982 12:33:12.585844
7983 12:33:12.585927 Set Vref, RX VrefLevel [Byte0]: 72
7984 12:33:12.589730 [Byte1]: 72
7985 12:33:12.593582
7986 12:33:12.593665 Set Vref, RX VrefLevel [Byte0]: 73
7987 12:33:12.596886 [Byte1]: 73
7988 12:33:12.600902
7989 12:33:12.601017 Final RX Vref Byte 0 = 56 to rank0
7990 12:33:12.604613 Final RX Vref Byte 1 = 64 to rank0
7991 12:33:12.607763 Final RX Vref Byte 0 = 56 to rank1
7992 12:33:12.611006 Final RX Vref Byte 1 = 64 to rank1==
7993 12:33:12.614089 Dram Type= 6, Freq= 0, CH_0, rank 0
7994 12:33:12.621063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 12:33:12.621177 ==
7996 12:33:12.621280 DQS Delay:
7997 12:33:12.624145 DQS0 = 0, DQS1 = 0
7998 12:33:12.624232 DQM Delay:
7999 12:33:12.624333 DQM0 = 133, DQM1 = 128
8000 12:33:12.627435 DQ Delay:
8001 12:33:12.630508 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
8002 12:33:12.634470 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8003 12:33:12.637613 DQ8 =118, DQ9 =118, DQ10 =130, DQ11 =120
8004 12:33:12.640811 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
8005 12:33:12.640919
8006 12:33:12.641015
8007 12:33:12.641080
8008 12:33:12.644257 [DramC_TX_OE_Calibration] TA2
8009 12:33:12.647738 Original DQ_B0 (3 6) =30, OEN = 27
8010 12:33:12.650921 Original DQ_B1 (3 6) =30, OEN = 27
8011 12:33:12.654092 24, 0x0, End_B0=24 End_B1=24
8012 12:33:12.654168 25, 0x0, End_B0=25 End_B1=25
8013 12:33:12.657286 26, 0x0, End_B0=26 End_B1=26
8014 12:33:12.660637 27, 0x0, End_B0=27 End_B1=27
8015 12:33:12.664129 28, 0x0, End_B0=28 End_B1=28
8016 12:33:12.667439 29, 0x0, End_B0=29 End_B1=29
8017 12:33:12.667515 30, 0x0, End_B0=30 End_B1=30
8018 12:33:12.670860 31, 0x4545, End_B0=30 End_B1=30
8019 12:33:12.674234 Byte0 end_step=30 best_step=27
8020 12:33:12.677528 Byte1 end_step=30 best_step=27
8021 12:33:12.680789 Byte0 TX OE(2T, 0.5T) = (3, 3)
8022 12:33:12.684154 Byte1 TX OE(2T, 0.5T) = (3, 3)
8023 12:33:12.684258
8024 12:33:12.684359
8025 12:33:12.690422 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8026 12:33:12.693713 CH0 RK0: MR19=303, MR18=2622
8027 12:33:12.700271 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
8028 12:33:12.700352
8029 12:33:12.703482 ----->DramcWriteLeveling(PI) begin...
8030 12:33:12.703561 ==
8031 12:33:12.706880 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 12:33:12.710227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 12:33:12.710329 ==
8034 12:33:12.713874 Write leveling (Byte 0): 36 => 36
8035 12:33:12.717098 Write leveling (Byte 1): 26 => 26
8036 12:33:12.720304 DramcWriteLeveling(PI) end<-----
8037 12:33:12.720405
8038 12:33:12.720496 ==
8039 12:33:12.723399 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 12:33:12.727204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 12:33:12.727312 ==
8042 12:33:12.730457 [Gating] SW mode calibration
8043 12:33:12.736824 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8044 12:33:12.743393 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8045 12:33:12.746984 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8046 12:33:12.753659 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 12:33:12.757036 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 12:33:12.760235 1 4 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8049 12:33:12.766805 1 4 16 | B1->B0 | 3030 3535 | 0 0 | (0 0) (1 1)
8050 12:33:12.770258 1 4 20 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
8051 12:33:12.773614 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8052 12:33:12.777037 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
8053 12:33:12.783771 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 12:33:12.786962 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8055 12:33:12.790332 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
8056 12:33:12.797012 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
8057 12:33:12.800367 1 5 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
8058 12:33:12.803189 1 5 20 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8059 12:33:12.809983 1 5 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8060 12:33:12.813407 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8061 12:33:12.816685 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8062 12:33:12.823708 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8063 12:33:12.827019 1 6 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8064 12:33:12.830209 1 6 12 | B1->B0 | 2727 3535 | 0 0 | (0 0) (0 0)
8065 12:33:12.837034 1 6 16 | B1->B0 | 4242 4645 | 0 1 | (0 0) (0 0)
8066 12:33:12.840340 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 12:33:12.843565 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 12:33:12.850132 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 12:33:12.853766 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 12:33:12.856895 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 12:33:12.863684 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 12:33:12.866962 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8073 12:33:12.870243 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8074 12:33:12.873541 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 12:33:12.880310 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 12:33:12.883706 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 12:33:12.887065 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 12:33:12.893098 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 12:33:12.896470 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 12:33:12.900416 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 12:33:12.906828 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 12:33:12.910130 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 12:33:12.913405 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 12:33:12.920271 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 12:33:12.923473 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 12:33:12.926832 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 12:33:12.933432 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 12:33:12.936483 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8089 12:33:12.939645 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8090 12:33:12.942867 Total UI for P1: 0, mck2ui 16
8091 12:33:12.946627 best dqsien dly found for B1: ( 1, 9, 12)
8092 12:33:12.953010 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 12:33:12.953099 Total UI for P1: 0, mck2ui 16
8094 12:33:12.959759 best dqsien dly found for B0: ( 1, 9, 14)
8095 12:33:12.962959 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8096 12:33:12.966628 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8097 12:33:12.966718
8098 12:33:12.969979 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8099 12:33:12.973356 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8100 12:33:12.976575 [Gating] SW calibration Done
8101 12:33:12.976681 ==
8102 12:33:12.979899 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 12:33:12.983361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 12:33:12.983477 ==
8105 12:33:12.986892 RX Vref Scan: 0
8106 12:33:12.987001
8107 12:33:12.987096 RX Vref 0 -> 0, step: 1
8108 12:33:12.987185
8109 12:33:12.989658 RX Delay 0 -> 252, step: 8
8110 12:33:12.993583 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8111 12:33:13.000117 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8112 12:33:13.003413 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8113 12:33:13.006715 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8114 12:33:13.009934 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8115 12:33:13.013160 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8116 12:33:13.020043 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8117 12:33:13.023301 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8118 12:33:13.026670 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8119 12:33:13.029917 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8120 12:33:13.033241 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8121 12:33:13.039430 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8122 12:33:13.042701 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8123 12:33:13.046566 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8124 12:33:13.049718 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8125 12:33:13.052842 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8126 12:33:13.056572 ==
8127 12:33:13.056647 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 12:33:13.062943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 12:33:13.063026 ==
8130 12:33:13.063091 DQS Delay:
8131 12:33:13.066153 DQS0 = 0, DQS1 = 0
8132 12:33:13.066235 DQM Delay:
8133 12:33:13.069466 DQM0 = 137, DQM1 = 131
8134 12:33:13.069548 DQ Delay:
8135 12:33:13.072644 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8136 12:33:13.076254 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8137 12:33:13.079452 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8138 12:33:13.082584 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8139 12:33:13.082694
8140 12:33:13.082789
8141 12:33:13.082880 ==
8142 12:33:13.085942 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 12:33:13.092738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 12:33:13.092825 ==
8145 12:33:13.092893
8146 12:33:13.092956
8147 12:33:13.093016 TX Vref Scan disable
8148 12:33:13.096111 == TX Byte 0 ==
8149 12:33:13.099489 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8150 12:33:13.106283 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8151 12:33:13.106369 == TX Byte 1 ==
8152 12:33:13.109503 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8153 12:33:13.112789 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8154 12:33:13.116212 ==
8155 12:33:13.119516 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 12:33:13.122799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 12:33:13.122885 ==
8158 12:33:13.137590
8159 12:33:13.140889 TX Vref early break, caculate TX vref
8160 12:33:13.144216 TX Vref=16, minBit 3, minWin=22, winSum=382
8161 12:33:13.147570 TX Vref=18, minBit 1, minWin=23, winSum=393
8162 12:33:13.150839 TX Vref=20, minBit 1, minWin=23, winSum=401
8163 12:33:13.154641 TX Vref=22, minBit 1, minWin=24, winSum=410
8164 12:33:13.157863 TX Vref=24, minBit 1, minWin=25, winSum=420
8165 12:33:13.164345 TX Vref=26, minBit 1, minWin=25, winSum=424
8166 12:33:13.167895 TX Vref=28, minBit 1, minWin=25, winSum=424
8167 12:33:13.171166 TX Vref=30, minBit 0, minWin=25, winSum=417
8168 12:33:13.174431 TX Vref=32, minBit 3, minWin=24, winSum=408
8169 12:33:13.177705 TX Vref=34, minBit 1, minWin=24, winSum=406
8170 12:33:13.180835 TX Vref=36, minBit 0, minWin=23, winSum=391
8171 12:33:13.187712 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8172 12:33:13.187824
8173 12:33:13.190879 Final TX Range 0 Vref 26
8174 12:33:13.190965
8175 12:33:13.191033 ==
8176 12:33:13.194259 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 12:33:13.197710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 12:33:13.197796 ==
8179 12:33:13.197863
8180 12:33:13.197925
8181 12:33:13.201136 TX Vref Scan disable
8182 12:33:13.207077 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8183 12:33:13.207182 == TX Byte 0 ==
8184 12:33:13.211065 u2DelayCellOfst[0]=13 cells (4 PI)
8185 12:33:13.214305 u2DelayCellOfst[1]=13 cells (4 PI)
8186 12:33:13.217535 u2DelayCellOfst[2]=10 cells (3 PI)
8187 12:33:13.220843 u2DelayCellOfst[3]=6 cells (2 PI)
8188 12:33:13.224115 u2DelayCellOfst[4]=6 cells (2 PI)
8189 12:33:13.227612 u2DelayCellOfst[5]=0 cells (0 PI)
8190 12:33:13.230933 u2DelayCellOfst[6]=13 cells (4 PI)
8191 12:33:13.234284 u2DelayCellOfst[7]=13 cells (4 PI)
8192 12:33:13.237512 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8193 12:33:13.240739 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8194 12:33:13.244161 == TX Byte 1 ==
8195 12:33:13.247356 u2DelayCellOfst[8]=3 cells (1 PI)
8196 12:33:13.247472 u2DelayCellOfst[9]=0 cells (0 PI)
8197 12:33:13.250593 u2DelayCellOfst[10]=6 cells (2 PI)
8198 12:33:13.253830 u2DelayCellOfst[11]=3 cells (1 PI)
8199 12:33:13.257129 u2DelayCellOfst[12]=10 cells (3 PI)
8200 12:33:13.260452 u2DelayCellOfst[13]=13 cells (4 PI)
8201 12:33:13.264338 u2DelayCellOfst[14]=13 cells (4 PI)
8202 12:33:13.267349 u2DelayCellOfst[15]=10 cells (3 PI)
8203 12:33:13.270616 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8204 12:33:13.277440 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8205 12:33:13.277549 DramC Write-DBI on
8206 12:33:13.277649 ==
8207 12:33:13.280759 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 12:33:13.287209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 12:33:13.287313 ==
8210 12:33:13.287449
8211 12:33:13.287545
8212 12:33:13.287640 TX Vref Scan disable
8213 12:33:13.290976 == TX Byte 0 ==
8214 12:33:13.294606 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8215 12:33:13.297948 == TX Byte 1 ==
8216 12:33:13.301182 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8217 12:33:13.304709 DramC Write-DBI off
8218 12:33:13.304822
8219 12:33:13.304921 [DATLAT]
8220 12:33:13.304986 Freq=1600, CH0 RK1
8221 12:33:13.305051
8222 12:33:13.307393 DATLAT Default: 0xf
8223 12:33:13.307530 0, 0xFFFF, sum = 0
8224 12:33:13.310774 1, 0xFFFF, sum = 0
8225 12:33:13.310925 2, 0xFFFF, sum = 0
8226 12:33:13.314112 3, 0xFFFF, sum = 0
8227 12:33:13.317789 4, 0xFFFF, sum = 0
8228 12:33:13.317931 5, 0xFFFF, sum = 0
8229 12:33:13.321165 6, 0xFFFF, sum = 0
8230 12:33:13.321268 7, 0xFFFF, sum = 0
8231 12:33:13.324569 8, 0xFFFF, sum = 0
8232 12:33:13.324667 9, 0xFFFF, sum = 0
8233 12:33:13.327812 10, 0xFFFF, sum = 0
8234 12:33:13.327897 11, 0xFFFF, sum = 0
8235 12:33:13.331079 12, 0xFFFF, sum = 0
8236 12:33:13.331204 13, 0xFFFF, sum = 0
8237 12:33:13.334527 14, 0x0, sum = 1
8238 12:33:13.334609 15, 0x0, sum = 2
8239 12:33:13.338039 16, 0x0, sum = 3
8240 12:33:13.338112 17, 0x0, sum = 4
8241 12:33:13.341225 best_step = 15
8242 12:33:13.341303
8243 12:33:13.341366 ==
8244 12:33:13.344461 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 12:33:13.347241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 12:33:13.347313 ==
8247 12:33:13.350794 RX Vref Scan: 0
8248 12:33:13.350876
8249 12:33:13.350941 RX Vref 0 -> 0, step: 1
8250 12:33:13.351002
8251 12:33:13.354057 RX Delay 19 -> 252, step: 4
8252 12:33:13.357544 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8253 12:33:13.364184 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8254 12:33:13.367296 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8255 12:33:13.370432 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8256 12:33:13.373708 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8257 12:33:13.377637 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8258 12:33:13.383983 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8259 12:33:13.387296 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8260 12:33:13.390493 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8261 12:33:13.393701 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8262 12:33:13.397510 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8263 12:33:13.404208 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8264 12:33:13.407511 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8265 12:33:13.410932 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8266 12:33:13.414158 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8267 12:33:13.417599 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8268 12:33:13.420862 ==
8269 12:33:13.424016 Dram Type= 6, Freq= 0, CH_0, rank 1
8270 12:33:13.427111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 12:33:13.427197 ==
8272 12:33:13.427264 DQS Delay:
8273 12:33:13.430282 DQS0 = 0, DQS1 = 0
8274 12:33:13.430365 DQM Delay:
8275 12:33:13.433553 DQM0 = 133, DQM1 = 127
8276 12:33:13.433637 DQ Delay:
8277 12:33:13.436933 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8278 12:33:13.440369 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140
8279 12:33:13.443752 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8280 12:33:13.447021 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8281 12:33:13.447106
8282 12:33:13.447172
8283 12:33:13.447233
8284 12:33:13.450206 [DramC_TX_OE_Calibration] TA2
8285 12:33:13.453659 Original DQ_B0 (3 6) =30, OEN = 27
8286 12:33:13.457057 Original DQ_B1 (3 6) =30, OEN = 27
8287 12:33:13.460436 24, 0x0, End_B0=24 End_B1=24
8288 12:33:13.463783 25, 0x0, End_B0=25 End_B1=25
8289 12:33:13.463868 26, 0x0, End_B0=26 End_B1=26
8290 12:33:13.467002 27, 0x0, End_B0=27 End_B1=27
8291 12:33:13.470477 28, 0x0, End_B0=28 End_B1=28
8292 12:33:13.473781 29, 0x0, End_B0=29 End_B1=29
8293 12:33:13.476981 30, 0x0, End_B0=30 End_B1=30
8294 12:33:13.477067 31, 0x4141, End_B0=30 End_B1=30
8295 12:33:13.480130 Byte0 end_step=30 best_step=27
8296 12:33:13.483337 Byte1 end_step=30 best_step=27
8297 12:33:13.487235 Byte0 TX OE(2T, 0.5T) = (3, 3)
8298 12:33:13.490567 Byte1 TX OE(2T, 0.5T) = (3, 3)
8299 12:33:13.490678
8300 12:33:13.490793
8301 12:33:13.496846 [DQSOSCAuto] RK1, (LSB)MR18= 0x230a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8302 12:33:13.500090 CH0 RK1: MR19=303, MR18=230A
8303 12:33:13.506995 CH0_RK1: MR19=0x303, MR18=0x230A, DQSOSC=392, MR23=63, INC=24, DEC=16
8304 12:33:13.510439 [RxdqsGatingPostProcess] freq 1600
8305 12:33:13.513637 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8306 12:33:13.516869 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 12:33:13.520205 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 12:33:13.523716 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 12:33:13.526995 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 12:33:13.530254 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 12:33:13.533423 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 12:33:13.536526 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 12:33:13.540292 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 12:33:13.543608 Pre-setting of DQS Precalculation
8315 12:33:13.546270 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8316 12:33:13.546356 ==
8317 12:33:13.549670 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 12:33:13.556931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 12:33:13.557019 ==
8320 12:33:13.559685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 12:33:13.566949 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 12:33:13.570095 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 12:33:13.576203 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 12:33:13.584007 [CA 0] Center 42 (13~72) winsize 60
8325 12:33:13.587170 [CA 1] Center 42 (13~72) winsize 60
8326 12:33:13.590342 [CA 2] Center 39 (10~68) winsize 59
8327 12:33:13.594175 [CA 3] Center 38 (9~67) winsize 59
8328 12:33:13.597140 [CA 4] Center 38 (9~68) winsize 60
8329 12:33:13.600314 [CA 5] Center 37 (8~67) winsize 60
8330 12:33:13.600409
8331 12:33:13.603583 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8332 12:33:13.603668
8333 12:33:13.607511 [CATrainingPosCal] consider 1 rank data
8334 12:33:13.610777 u2DelayCellTimex100 = 290/100 ps
8335 12:33:13.617460 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8336 12:33:13.620821 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8337 12:33:13.624186 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8338 12:33:13.627574 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8339 12:33:13.630244 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8340 12:33:13.633730 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8341 12:33:13.633858
8342 12:33:13.636940 CA PerBit enable=1, Macro0, CA PI delay=37
8343 12:33:13.637047
8344 12:33:13.640249 [CBTSetCACLKResult] CA Dly = 37
8345 12:33:13.643561 CS Dly: 11 (0~42)
8346 12:33:13.647253 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 12:33:13.650410 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 12:33:13.650485 ==
8349 12:33:13.653857 Dram Type= 6, Freq= 0, CH_1, rank 1
8350 12:33:13.657026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 12:33:13.660451 ==
8352 12:33:13.663814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8353 12:33:13.667157 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8354 12:33:13.673828 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8355 12:33:13.680239 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8356 12:33:13.687436 [CA 0] Center 42 (12~72) winsize 61
8357 12:33:13.690701 [CA 1] Center 41 (12~71) winsize 60
8358 12:33:13.693946 [CA 2] Center 38 (9~68) winsize 60
8359 12:33:13.697472 [CA 3] Center 37 (8~67) winsize 60
8360 12:33:13.700600 [CA 4] Center 38 (8~68) winsize 61
8361 12:33:13.704339 [CA 5] Center 37 (8~66) winsize 59
8362 12:33:13.704440
8363 12:33:13.707165 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8364 12:33:13.707267
8365 12:33:13.710287 [CATrainingPosCal] consider 2 rank data
8366 12:33:13.713514 u2DelayCellTimex100 = 290/100 ps
8367 12:33:13.720589 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8368 12:33:13.723832 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8369 12:33:13.727332 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8370 12:33:13.730721 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8371 12:33:13.733939 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8372 12:33:13.737263 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8373 12:33:13.737365
8374 12:33:13.740531 CA PerBit enable=1, Macro0, CA PI delay=37
8375 12:33:13.740631
8376 12:33:13.743796 [CBTSetCACLKResult] CA Dly = 37
8377 12:33:13.747126 CS Dly: 12 (0~44)
8378 12:33:13.750305 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8379 12:33:13.753665 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8380 12:33:13.753772
8381 12:33:13.756607 ----->DramcWriteLeveling(PI) begin...
8382 12:33:13.756712 ==
8383 12:33:13.760410 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 12:33:13.767028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 12:33:13.767137 ==
8386 12:33:13.770420 Write leveling (Byte 0): 25 => 25
8387 12:33:13.770531 Write leveling (Byte 1): 28 => 28
8388 12:33:13.773900 DramcWriteLeveling(PI) end<-----
8389 12:33:13.774006
8390 12:33:13.774098 ==
8391 12:33:13.777128 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 12:33:13.783226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 12:33:13.783337 ==
8394 12:33:13.786569 [Gating] SW mode calibration
8395 12:33:13.793177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8396 12:33:13.797025 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8397 12:33:13.803517 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 12:33:13.806809 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 12:33:13.809944 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8400 12:33:13.817076 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8401 12:33:13.820335 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 12:33:13.823586 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 12:33:13.829793 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 12:33:13.833236 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 12:33:13.836687 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 12:33:13.843264 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 12:33:13.846662 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8408 12:33:13.849906 1 5 12 | B1->B0 | 2626 2323 | 1 0 | (1 0) (1 0)
8409 12:33:13.853246 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 12:33:13.860376 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 12:33:13.863566 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 12:33:13.866818 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 12:33:13.873543 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 12:33:13.877146 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 12:33:13.880305 1 6 8 | B1->B0 | 2626 4343 | 0 0 | (1 1) (0 0)
8416 12:33:13.886917 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8417 12:33:13.890254 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 12:33:13.893629 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 12:33:13.900340 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 12:33:13.903630 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 12:33:13.906845 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 12:33:13.913629 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 12:33:13.916926 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8424 12:33:13.920314 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8425 12:33:13.927023 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8426 12:33:13.930428 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 12:33:13.934124 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 12:33:13.937308 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 12:33:13.943981 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 12:33:13.947267 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 12:33:13.950496 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 12:33:13.956966 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 12:33:13.960313 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 12:33:13.963477 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 12:33:13.970656 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 12:33:13.973600 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 12:33:13.976824 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 12:33:13.983520 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 12:33:13.986842 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8440 12:33:13.989891 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8441 12:33:13.996818 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 12:33:14.000143 Total UI for P1: 0, mck2ui 16
8443 12:33:14.003490 best dqsien dly found for B0: ( 1, 9, 10)
8444 12:33:14.003912 Total UI for P1: 0, mck2ui 16
8445 12:33:14.009726 best dqsien dly found for B1: ( 1, 9, 10)
8446 12:33:14.012987 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8447 12:33:14.016763 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8448 12:33:14.017421
8449 12:33:14.019673 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8450 12:33:14.023730 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8451 12:33:14.026983 [Gating] SW calibration Done
8452 12:33:14.027558 ==
8453 12:33:14.030109 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 12:33:14.033051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 12:33:14.033542 ==
8456 12:33:14.036801 RX Vref Scan: 0
8457 12:33:14.037270
8458 12:33:14.037605 RX Vref 0 -> 0, step: 1
8459 12:33:14.039921
8460 12:33:14.040344 RX Delay 0 -> 252, step: 8
8461 12:33:14.043186 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8462 12:33:14.049932 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8463 12:33:14.053198 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8464 12:33:14.056544 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8465 12:33:14.059906 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8466 12:33:14.063182 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8467 12:33:14.069822 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8468 12:33:14.073645 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8469 12:33:14.076995 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8470 12:33:14.080070 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8471 12:33:14.083103 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8472 12:33:14.090365 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8473 12:33:14.093563 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8474 12:33:14.096989 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8475 12:33:14.100542 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8476 12:33:14.103283 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8477 12:33:14.103753 ==
8478 12:33:14.106525 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 12:33:14.113225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 12:33:14.113650 ==
8481 12:33:14.113981 DQS Delay:
8482 12:33:14.116967 DQS0 = 0, DQS1 = 0
8483 12:33:14.117388 DQM Delay:
8484 12:33:14.117722 DQM0 = 136, DQM1 = 133
8485 12:33:14.120212 DQ Delay:
8486 12:33:14.123140 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8487 12:33:14.127023 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8488 12:33:14.129885 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8489 12:33:14.132910 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8490 12:33:14.133331
8491 12:33:14.133664
8492 12:33:14.133971 ==
8493 12:33:14.136181 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 12:33:14.142887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 12:33:14.143311 ==
8496 12:33:14.143706
8497 12:33:14.144020
8498 12:33:14.144318 TX Vref Scan disable
8499 12:33:14.146712 == TX Byte 0 ==
8500 12:33:14.149820 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 12:33:14.156248 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8502 12:33:14.156334 == TX Byte 1 ==
8503 12:33:14.159483 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8504 12:33:14.166031 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8505 12:33:14.166113 ==
8506 12:33:14.169255 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 12:33:14.172509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 12:33:14.172591 ==
8509 12:33:14.184737
8510 12:33:14.188584 TX Vref early break, caculate TX vref
8511 12:33:14.191812 TX Vref=16, minBit 1, minWin=22, winSum=371
8512 12:33:14.195040 TX Vref=18, minBit 1, minWin=23, winSum=382
8513 12:33:14.198442 TX Vref=20, minBit 0, minWin=24, winSum=396
8514 12:33:14.201687 TX Vref=22, minBit 1, minWin=24, winSum=403
8515 12:33:14.204989 TX Vref=24, minBit 0, minWin=25, winSum=413
8516 12:33:14.211740 TX Vref=26, minBit 0, minWin=25, winSum=420
8517 12:33:14.214608 TX Vref=28, minBit 2, minWin=25, winSum=426
8518 12:33:14.217854 TX Vref=30, minBit 0, minWin=25, winSum=420
8519 12:33:14.221631 TX Vref=32, minBit 2, minWin=24, winSum=410
8520 12:33:14.225000 TX Vref=34, minBit 0, minWin=24, winSum=398
8521 12:33:14.231930 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 28
8522 12:33:14.232278
8523 12:33:14.234771 Final TX Range 0 Vref 28
8524 12:33:14.234853
8525 12:33:14.234918 ==
8526 12:33:14.237893 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 12:33:14.241249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 12:33:14.241332 ==
8529 12:33:14.241396
8530 12:33:14.241456
8531 12:33:14.244430 TX Vref Scan disable
8532 12:33:14.251478 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8533 12:33:14.251566 == TX Byte 0 ==
8534 12:33:14.254580 u2DelayCellOfst[0]=16 cells (5 PI)
8535 12:33:14.257876 u2DelayCellOfst[1]=10 cells (3 PI)
8536 12:33:14.261172 u2DelayCellOfst[2]=0 cells (0 PI)
8537 12:33:14.264429 u2DelayCellOfst[3]=6 cells (2 PI)
8538 12:33:14.267725 u2DelayCellOfst[4]=10 cells (3 PI)
8539 12:33:14.271144 u2DelayCellOfst[5]=20 cells (6 PI)
8540 12:33:14.274130 u2DelayCellOfst[6]=16 cells (5 PI)
8541 12:33:14.277555 u2DelayCellOfst[7]=3 cells (1 PI)
8542 12:33:14.280773 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8543 12:33:14.284147 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8544 12:33:14.287511 == TX Byte 1 ==
8545 12:33:14.287593 u2DelayCellOfst[8]=0 cells (0 PI)
8546 12:33:14.290688 u2DelayCellOfst[9]=3 cells (1 PI)
8547 12:33:14.293899 u2DelayCellOfst[10]=13 cells (4 PI)
8548 12:33:14.297189 u2DelayCellOfst[11]=6 cells (2 PI)
8549 12:33:14.300860 u2DelayCellOfst[12]=13 cells (4 PI)
8550 12:33:14.304285 u2DelayCellOfst[13]=20 cells (6 PI)
8551 12:33:14.307555 u2DelayCellOfst[14]=20 cells (6 PI)
8552 12:33:14.310972 u2DelayCellOfst[15]=20 cells (6 PI)
8553 12:33:14.314382 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8554 12:33:14.320311 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8555 12:33:14.320407 DramC Write-DBI on
8556 12:33:14.320481 ==
8557 12:33:14.324319 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 12:33:14.330706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 12:33:14.330820 ==
8560 12:33:14.330909
8561 12:33:14.330992
8562 12:33:14.331071 TX Vref Scan disable
8563 12:33:14.334454 == TX Byte 0 ==
8564 12:33:14.337551 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8565 12:33:14.340807 == TX Byte 1 ==
8566 12:33:14.344557 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8567 12:33:14.347739 DramC Write-DBI off
8568 12:33:14.347891
8569 12:33:14.348011 [DATLAT]
8570 12:33:14.348123 Freq=1600, CH1 RK0
8571 12:33:14.348231
8572 12:33:14.350938 DATLAT Default: 0xf
8573 12:33:14.351132 0, 0xFFFF, sum = 0
8574 12:33:14.354008 1, 0xFFFF, sum = 0
8575 12:33:14.357808 2, 0xFFFF, sum = 0
8576 12:33:14.358021 3, 0xFFFF, sum = 0
8577 12:33:14.361099 4, 0xFFFF, sum = 0
8578 12:33:14.361372 5, 0xFFFF, sum = 0
8579 12:33:14.364361 6, 0xFFFF, sum = 0
8580 12:33:14.364711 7, 0xFFFF, sum = 0
8581 12:33:14.367575 8, 0xFFFF, sum = 0
8582 12:33:14.367905 9, 0xFFFF, sum = 0
8583 12:33:14.370990 10, 0xFFFF, sum = 0
8584 12:33:14.371449 11, 0xFFFF, sum = 0
8585 12:33:14.374401 12, 0xFFFF, sum = 0
8586 12:33:14.374889 13, 0xFFFF, sum = 0
8587 12:33:14.377738 14, 0x0, sum = 1
8588 12:33:14.378267 15, 0x0, sum = 2
8589 12:33:14.380972 16, 0x0, sum = 3
8590 12:33:14.381408 17, 0x0, sum = 4
8591 12:33:14.384208 best_step = 15
8592 12:33:14.384681
8593 12:33:14.385079 ==
8594 12:33:14.387619 Dram Type= 6, Freq= 0, CH_1, rank 0
8595 12:33:14.390905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8596 12:33:14.391555 ==
8597 12:33:14.394054 RX Vref Scan: 1
8598 12:33:14.394481
8599 12:33:14.394821 Set Vref Range= 24 -> 127
8600 12:33:14.395139
8601 12:33:14.397907 RX Vref 24 -> 127, step: 1
8602 12:33:14.398334
8603 12:33:14.400605 RX Delay 27 -> 252, step: 4
8604 12:33:14.401067
8605 12:33:14.404468 Set Vref, RX VrefLevel [Byte0]: 24
8606 12:33:14.407542 [Byte1]: 24
8607 12:33:14.408120
8608 12:33:14.410842 Set Vref, RX VrefLevel [Byte0]: 25
8609 12:33:14.414127 [Byte1]: 25
8610 12:33:14.414498
8611 12:33:14.417522 Set Vref, RX VrefLevel [Byte0]: 26
8612 12:33:14.420330 [Byte1]: 26
8613 12:33:14.424488
8614 12:33:14.425060 Set Vref, RX VrefLevel [Byte0]: 27
8615 12:33:14.427933 [Byte1]: 27
8616 12:33:14.432378
8617 12:33:14.432969 Set Vref, RX VrefLevel [Byte0]: 28
8618 12:33:14.435758 [Byte1]: 28
8619 12:33:14.439988
8620 12:33:14.440448 Set Vref, RX VrefLevel [Byte0]: 29
8621 12:33:14.443099 [Byte1]: 29
8622 12:33:14.447018
8623 12:33:14.447586 Set Vref, RX VrefLevel [Byte0]: 30
8624 12:33:14.450809 [Byte1]: 30
8625 12:33:14.454792
8626 12:33:14.455217 Set Vref, RX VrefLevel [Byte0]: 31
8627 12:33:14.458045 [Byte1]: 31
8628 12:33:14.462493
8629 12:33:14.463086 Set Vref, RX VrefLevel [Byte0]: 32
8630 12:33:14.465583 [Byte1]: 32
8631 12:33:14.470224
8632 12:33:14.470651 Set Vref, RX VrefLevel [Byte0]: 33
8633 12:33:14.473314 [Byte1]: 33
8634 12:33:14.477800
8635 12:33:14.478239 Set Vref, RX VrefLevel [Byte0]: 34
8636 12:33:14.481109 [Byte1]: 34
8637 12:33:14.484841
8638 12:33:14.485268 Set Vref, RX VrefLevel [Byte0]: 35
8639 12:33:14.488269 [Byte1]: 35
8640 12:33:14.492743
8641 12:33:14.493168 Set Vref, RX VrefLevel [Byte0]: 36
8642 12:33:14.496105 [Byte1]: 36
8643 12:33:14.499851
8644 12:33:14.500321 Set Vref, RX VrefLevel [Byte0]: 37
8645 12:33:14.503738 [Byte1]: 37
8646 12:33:14.507665
8647 12:33:14.508178 Set Vref, RX VrefLevel [Byte0]: 38
8648 12:33:14.510803 [Byte1]: 38
8649 12:33:14.515307
8650 12:33:14.515866 Set Vref, RX VrefLevel [Byte0]: 39
8651 12:33:14.518169 [Byte1]: 39
8652 12:33:14.522694
8653 12:33:14.523201 Set Vref, RX VrefLevel [Byte0]: 40
8654 12:33:14.525916 [Byte1]: 40
8655 12:33:14.530423
8656 12:33:14.530996 Set Vref, RX VrefLevel [Byte0]: 41
8657 12:33:14.533740 [Byte1]: 41
8658 12:33:14.537725
8659 12:33:14.538234 Set Vref, RX VrefLevel [Byte0]: 42
8660 12:33:14.540898 [Byte1]: 42
8661 12:33:14.545292
8662 12:33:14.545812 Set Vref, RX VrefLevel [Byte0]: 43
8663 12:33:14.548776 [Byte1]: 43
8664 12:33:14.552819
8665 12:33:14.553333 Set Vref, RX VrefLevel [Byte0]: 44
8666 12:33:14.555823 [Byte1]: 44
8667 12:33:14.560511
8668 12:33:14.561296 Set Vref, RX VrefLevel [Byte0]: 45
8669 12:33:14.563704 [Byte1]: 45
8670 12:33:14.567507
8671 12:33:14.568007 Set Vref, RX VrefLevel [Byte0]: 46
8672 12:33:14.571199 [Byte1]: 46
8673 12:33:14.575168
8674 12:33:14.575758 Set Vref, RX VrefLevel [Byte0]: 47
8675 12:33:14.578970 [Byte1]: 47
8676 12:33:14.582597
8677 12:33:14.583151 Set Vref, RX VrefLevel [Byte0]: 48
8678 12:33:14.586536 [Byte1]: 48
8679 12:33:14.590132
8680 12:33:14.591041 Set Vref, RX VrefLevel [Byte0]: 49
8681 12:33:14.593602 [Byte1]: 49
8682 12:33:14.598175
8683 12:33:14.598758 Set Vref, RX VrefLevel [Byte0]: 50
8684 12:33:14.601207 [Byte1]: 50
8685 12:33:14.605572
8686 12:33:14.605907 Set Vref, RX VrefLevel [Byte0]: 51
8687 12:33:14.608327 [Byte1]: 51
8688 12:33:14.612890
8689 12:33:14.613091 Set Vref, RX VrefLevel [Byte0]: 52
8690 12:33:14.616056 [Byte1]: 52
8691 12:33:14.620437
8692 12:33:14.620578 Set Vref, RX VrefLevel [Byte0]: 53
8693 12:33:14.623622 [Byte1]: 53
8694 12:33:14.628029
8695 12:33:14.628153 Set Vref, RX VrefLevel [Byte0]: 54
8696 12:33:14.631153 [Byte1]: 54
8697 12:33:14.635122
8698 12:33:14.635211 Set Vref, RX VrefLevel [Byte0]: 55
8699 12:33:14.638488 [Byte1]: 55
8700 12:33:14.643033
8701 12:33:14.643115 Set Vref, RX VrefLevel [Byte0]: 56
8702 12:33:14.646269 [Byte1]: 56
8703 12:33:14.650118
8704 12:33:14.650200 Set Vref, RX VrefLevel [Byte0]: 57
8705 12:33:14.653833 [Byte1]: 57
8706 12:33:14.658108
8707 12:33:14.658183 Set Vref, RX VrefLevel [Byte0]: 58
8708 12:33:14.661225 [Byte1]: 58
8709 12:33:14.665501
8710 12:33:14.665580 Set Vref, RX VrefLevel [Byte0]: 59
8711 12:33:14.668429 [Byte1]: 59
8712 12:33:14.672897
8713 12:33:14.672970 Set Vref, RX VrefLevel [Byte0]: 60
8714 12:33:14.676477 [Byte1]: 60
8715 12:33:14.680749
8716 12:33:14.680828 Set Vref, RX VrefLevel [Byte0]: 61
8717 12:33:14.683963 [Byte1]: 61
8718 12:33:14.688309
8719 12:33:14.688388 Set Vref, RX VrefLevel [Byte0]: 62
8720 12:33:14.691275 [Byte1]: 62
8721 12:33:14.695552
8722 12:33:14.695642 Set Vref, RX VrefLevel [Byte0]: 63
8723 12:33:14.698831 [Byte1]: 63
8724 12:33:14.702807
8725 12:33:14.702894 Set Vref, RX VrefLevel [Byte0]: 64
8726 12:33:14.706146 [Byte1]: 64
8727 12:33:14.710566
8728 12:33:14.710646 Set Vref, RX VrefLevel [Byte0]: 65
8729 12:33:14.713789 [Byte1]: 65
8730 12:33:14.718279
8731 12:33:14.718363 Set Vref, RX VrefLevel [Byte0]: 66
8732 12:33:14.721536 [Byte1]: 66
8733 12:33:14.725947
8734 12:33:14.726030 Set Vref, RX VrefLevel [Byte0]: 67
8735 12:33:14.729213 [Byte1]: 67
8736 12:33:14.733430
8737 12:33:14.733509 Set Vref, RX VrefLevel [Byte0]: 68
8738 12:33:14.736695 [Byte1]: 68
8739 12:33:14.740538
8740 12:33:14.740615 Set Vref, RX VrefLevel [Byte0]: 69
8741 12:33:14.743809 [Byte1]: 69
8742 12:33:14.748374
8743 12:33:14.748449 Set Vref, RX VrefLevel [Byte0]: 70
8744 12:33:14.751533 [Byte1]: 70
8745 12:33:14.756044
8746 12:33:14.756126 Set Vref, RX VrefLevel [Byte0]: 71
8747 12:33:14.759297 [Byte1]: 71
8748 12:33:14.763090
8749 12:33:14.763188 Set Vref, RX VrefLevel [Byte0]: 72
8750 12:33:14.766773 [Byte1]: 72
8751 12:33:14.770942
8752 12:33:14.771113 Set Vref, RX VrefLevel [Byte0]: 73
8753 12:33:14.773870 [Byte1]: 73
8754 12:33:14.778286
8755 12:33:14.778427 Final RX Vref Byte 0 = 57 to rank0
8756 12:33:14.781393 Final RX Vref Byte 1 = 57 to rank0
8757 12:33:14.784989 Final RX Vref Byte 0 = 57 to rank1
8758 12:33:14.787976 Final RX Vref Byte 1 = 57 to rank1==
8759 12:33:14.791792 Dram Type= 6, Freq= 0, CH_1, rank 0
8760 12:33:14.797965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 12:33:14.798114 ==
8762 12:33:14.798288 DQS Delay:
8763 12:33:14.801683 DQS0 = 0, DQS1 = 0
8764 12:33:14.801816 DQM Delay:
8765 12:33:14.801948 DQM0 = 134, DQM1 = 131
8766 12:33:14.804884 DQ Delay:
8767 12:33:14.808119 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8768 12:33:14.811547 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8769 12:33:14.814581 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8770 12:33:14.817690 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8771 12:33:14.817786
8772 12:33:14.817856
8773 12:33:14.817935
8774 12:33:14.820984 [DramC_TX_OE_Calibration] TA2
8775 12:33:14.824228 Original DQ_B0 (3 6) =30, OEN = 27
8776 12:33:14.827928 Original DQ_B1 (3 6) =30, OEN = 27
8777 12:33:14.831220 24, 0x0, End_B0=24 End_B1=24
8778 12:33:14.831300 25, 0x0, End_B0=25 End_B1=25
8779 12:33:14.834567 26, 0x0, End_B0=26 End_B1=26
8780 12:33:14.837614 27, 0x0, End_B0=27 End_B1=27
8781 12:33:14.841263 28, 0x0, End_B0=28 End_B1=28
8782 12:33:14.844502 29, 0x0, End_B0=29 End_B1=29
8783 12:33:14.844579 30, 0x0, End_B0=30 End_B1=30
8784 12:33:14.847900 31, 0x4141, End_B0=30 End_B1=30
8785 12:33:14.851150 Byte0 end_step=30 best_step=27
8786 12:33:14.854323 Byte1 end_step=30 best_step=27
8787 12:33:14.857735 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 12:33:14.860776 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 12:33:14.860851
8790 12:33:14.860921
8791 12:33:14.867322 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8792 12:33:14.871024 CH1 RK0: MR19=303, MR18=1623
8793 12:33:14.877747 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8794 12:33:14.877825
8795 12:33:14.880786 ----->DramcWriteLeveling(PI) begin...
8796 12:33:14.880870 ==
8797 12:33:14.883869 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 12:33:14.887605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 12:33:14.887684 ==
8800 12:33:14.890539 Write leveling (Byte 0): 25 => 25
8801 12:33:14.894150 Write leveling (Byte 1): 29 => 29
8802 12:33:14.897143 DramcWriteLeveling(PI) end<-----
8803 12:33:14.897225
8804 12:33:14.897289 ==
8805 12:33:14.900370 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 12:33:14.904236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 12:33:14.907027 ==
8808 12:33:14.907102 [Gating] SW mode calibration
8809 12:33:14.914004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8810 12:33:14.920387 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8811 12:33:14.923654 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 12:33:14.930139 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 12:33:14.934010 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8814 12:33:14.937190 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8815 12:33:14.943652 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 12:33:14.946683 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 12:33:14.950470 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 12:33:14.956965 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 12:33:14.960414 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 12:33:14.963556 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8821 12:33:14.970502 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8822 12:33:14.973830 1 5 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
8823 12:33:14.976920 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 12:33:14.983667 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 12:33:14.987006 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 12:33:14.990466 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 12:33:14.993675 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 12:33:15.000264 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 12:33:15.003366 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8830 12:33:15.007169 1 6 12 | B1->B0 | 4646 3b3b | 0 1 | (0 0) (1 1)
8831 12:33:15.013208 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 12:33:15.017222 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 12:33:15.020195 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 12:33:15.026648 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 12:33:15.029920 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 12:33:15.033265 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8837 12:33:15.040382 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8838 12:33:15.043539 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8839 12:33:15.046867 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8840 12:33:15.053305 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 12:33:15.056490 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 12:33:15.059833 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 12:33:15.066386 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 12:33:15.069798 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 12:33:15.073158 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 12:33:15.079583 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 12:33:15.083177 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 12:33:15.086280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 12:33:15.093049 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 12:33:15.096423 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 12:33:15.099648 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 12:33:15.106331 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8853 12:33:15.109491 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8854 12:33:15.112714 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8855 12:33:15.116382 Total UI for P1: 0, mck2ui 16
8856 12:33:15.119445 best dqsien dly found for B1: ( 1, 9, 6)
8857 12:33:15.126176 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 12:33:15.126300 Total UI for P1: 0, mck2ui 16
8859 12:33:15.129415 best dqsien dly found for B0: ( 1, 9, 12)
8860 12:33:15.135927 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8861 12:33:15.139710 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8862 12:33:15.139819
8863 12:33:15.142912 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8864 12:33:15.146215 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8865 12:33:15.149387 [Gating] SW calibration Done
8866 12:33:15.149488 ==
8867 12:33:15.152640 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 12:33:15.155952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 12:33:15.156056 ==
8870 12:33:15.159133 RX Vref Scan: 0
8871 12:33:15.159243
8872 12:33:15.159387 RX Vref 0 -> 0, step: 1
8873 12:33:15.159454
8874 12:33:15.162869 RX Delay 0 -> 252, step: 8
8875 12:33:15.166238 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8876 12:33:15.169496 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8877 12:33:15.175749 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8878 12:33:15.179090 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8879 12:33:15.182300 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8880 12:33:15.186163 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8881 12:33:15.189305 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8882 12:33:15.196127 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8883 12:33:15.199117 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8884 12:33:15.202989 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8885 12:33:15.206124 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8886 12:33:15.209111 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8887 12:33:15.216210 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8888 12:33:15.219369 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8889 12:33:15.222471 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8890 12:33:15.226157 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8891 12:33:15.226242 ==
8892 12:33:15.229158 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 12:33:15.236218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 12:33:15.236305 ==
8895 12:33:15.236370 DQS Delay:
8896 12:33:15.239474 DQS0 = 0, DQS1 = 0
8897 12:33:15.239557 DQM Delay:
8898 12:33:15.239622 DQM0 = 135, DQM1 = 133
8899 12:33:15.242661 DQ Delay:
8900 12:33:15.245741 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8901 12:33:15.249611 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8902 12:33:15.252945 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8903 12:33:15.256064 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8904 12:33:15.256149
8905 12:33:15.256215
8906 12:33:15.256276 ==
8907 12:33:15.259347 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 12:33:15.262689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 12:33:15.265845 ==
8910 12:33:15.265930
8911 12:33:15.265995
8912 12:33:15.266057 TX Vref Scan disable
8913 12:33:15.269779 == TX Byte 0 ==
8914 12:33:15.272904 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8915 12:33:15.275964 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8916 12:33:15.279109 == TX Byte 1 ==
8917 12:33:15.282950 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8918 12:33:15.286200 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8919 12:33:15.286305 ==
8920 12:33:15.289508 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 12:33:15.295836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 12:33:15.295947 ==
8923 12:33:15.307720
8924 12:33:15.311513 TX Vref early break, caculate TX vref
8925 12:33:15.314534 TX Vref=16, minBit 0, minWin=23, winSum=381
8926 12:33:15.317560 TX Vref=18, minBit 0, minWin=23, winSum=389
8927 12:33:15.321170 TX Vref=20, minBit 0, minWin=24, winSum=399
8928 12:33:15.324254 TX Vref=22, minBit 13, minWin=24, winSum=407
8929 12:33:15.327991 TX Vref=24, minBit 0, minWin=25, winSum=416
8930 12:33:15.334266 TX Vref=26, minBit 0, minWin=24, winSum=418
8931 12:33:15.337923 TX Vref=28, minBit 15, minWin=25, winSum=426
8932 12:33:15.341129 TX Vref=30, minBit 6, minWin=25, winSum=421
8933 12:33:15.344340 TX Vref=32, minBit 1, minWin=25, winSum=413
8934 12:33:15.347506 TX Vref=34, minBit 0, minWin=24, winSum=400
8935 12:33:15.354805 [TxChooseVref] Worse bit 15, Min win 25, Win sum 426, Final Vref 28
8936 12:33:15.354922
8937 12:33:15.357233 Final TX Range 0 Vref 28
8938 12:33:15.357316
8939 12:33:15.357411 ==
8940 12:33:15.361218 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 12:33:15.364406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 12:33:15.364491 ==
8943 12:33:15.364567
8944 12:33:15.364636
8945 12:33:15.367613 TX Vref Scan disable
8946 12:33:15.374193 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8947 12:33:15.374308 == TX Byte 0 ==
8948 12:33:15.377497 u2DelayCellOfst[0]=16 cells (5 PI)
8949 12:33:15.380595 u2DelayCellOfst[1]=13 cells (4 PI)
8950 12:33:15.383795 u2DelayCellOfst[2]=0 cells (0 PI)
8951 12:33:15.387636 u2DelayCellOfst[3]=6 cells (2 PI)
8952 12:33:15.390906 u2DelayCellOfst[4]=10 cells (3 PI)
8953 12:33:15.394220 u2DelayCellOfst[5]=16 cells (5 PI)
8954 12:33:15.397369 u2DelayCellOfst[6]=20 cells (6 PI)
8955 12:33:15.400632 u2DelayCellOfst[7]=6 cells (2 PI)
8956 12:33:15.403770 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8957 12:33:15.407482 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8958 12:33:15.410615 == TX Byte 1 ==
8959 12:33:15.414333 u2DelayCellOfst[8]=0 cells (0 PI)
8960 12:33:15.414418 u2DelayCellOfst[9]=3 cells (1 PI)
8961 12:33:15.417404 u2DelayCellOfst[10]=10 cells (3 PI)
8962 12:33:15.420551 u2DelayCellOfst[11]=6 cells (2 PI)
8963 12:33:15.423697 u2DelayCellOfst[12]=16 cells (5 PI)
8964 12:33:15.427339 u2DelayCellOfst[13]=16 cells (5 PI)
8965 12:33:15.430485 u2DelayCellOfst[14]=16 cells (5 PI)
8966 12:33:15.434095 u2DelayCellOfst[15]=16 cells (5 PI)
8967 12:33:15.437189 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8968 12:33:15.443948 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8969 12:33:15.444029 DramC Write-DBI on
8970 12:33:15.444094 ==
8971 12:33:15.447147 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 12:33:15.451031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 12:33:15.454086 ==
8974 12:33:15.454191
8975 12:33:15.454283
8976 12:33:15.454377 TX Vref Scan disable
8977 12:33:15.457330 == TX Byte 0 ==
8978 12:33:15.461121 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8979 12:33:15.464478 == TX Byte 1 ==
8980 12:33:15.467725 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8981 12:33:15.470995 DramC Write-DBI off
8982 12:33:15.471077
8983 12:33:15.471141 [DATLAT]
8984 12:33:15.471201 Freq=1600, CH1 RK1
8985 12:33:15.471259
8986 12:33:15.474192 DATLAT Default: 0xf
8987 12:33:15.474273 0, 0xFFFF, sum = 0
8988 12:33:15.477511 1, 0xFFFF, sum = 0
8989 12:33:15.477594 2, 0xFFFF, sum = 0
8990 12:33:15.480644 3, 0xFFFF, sum = 0
8991 12:33:15.483805 4, 0xFFFF, sum = 0
8992 12:33:15.483889 5, 0xFFFF, sum = 0
8993 12:33:15.487479 6, 0xFFFF, sum = 0
8994 12:33:15.487562 7, 0xFFFF, sum = 0
8995 12:33:15.490696 8, 0xFFFF, sum = 0
8996 12:33:15.490779 9, 0xFFFF, sum = 0
8997 12:33:15.493904 10, 0xFFFF, sum = 0
8998 12:33:15.493987 11, 0xFFFF, sum = 0
8999 12:33:15.497296 12, 0xFFFF, sum = 0
9000 12:33:15.497381 13, 0xFFFF, sum = 0
9001 12:33:15.500589 14, 0x0, sum = 1
9002 12:33:15.500673 15, 0x0, sum = 2
9003 12:33:15.503866 16, 0x0, sum = 3
9004 12:33:15.503949 17, 0x0, sum = 4
9005 12:33:15.507748 best_step = 15
9006 12:33:15.507874
9007 12:33:15.507940 ==
9008 12:33:15.510786 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 12:33:15.513858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 12:33:15.513942 ==
9011 12:33:15.514008 RX Vref Scan: 0
9012 12:33:15.517645
9013 12:33:15.517727 RX Vref 0 -> 0, step: 1
9014 12:33:15.517792
9015 12:33:15.520492 RX Delay 19 -> 252, step: 4
9016 12:33:15.523645 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9017 12:33:15.530335 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9018 12:33:15.533982 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9019 12:33:15.537148 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9020 12:33:15.540709 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9021 12:33:15.543856 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9022 12:33:15.547609 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9023 12:33:15.553784 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9024 12:33:15.556886 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9025 12:33:15.560653 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9026 12:33:15.563864 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9027 12:33:15.567076 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9028 12:33:15.573506 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9029 12:33:15.576789 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9030 12:33:15.580659 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9031 12:33:15.583854 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9032 12:33:15.583938 ==
9033 12:33:15.587034 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 12:33:15.593710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 12:33:15.593795 ==
9036 12:33:15.593861 DQS Delay:
9037 12:33:15.596913 DQS0 = 0, DQS1 = 0
9038 12:33:15.596996 DQM Delay:
9039 12:33:15.600117 DQM0 = 134, DQM1 = 130
9040 12:33:15.600204 DQ Delay:
9041 12:33:15.603243 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9042 12:33:15.607167 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9043 12:33:15.609825 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9044 12:33:15.613782 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9045 12:33:15.613866
9046 12:33:15.613961
9047 12:33:15.614021
9048 12:33:15.617092 [DramC_TX_OE_Calibration] TA2
9049 12:33:15.620212 Original DQ_B0 (3 6) =30, OEN = 27
9050 12:33:15.623158 Original DQ_B1 (3 6) =30, OEN = 27
9051 12:33:15.626379 24, 0x0, End_B0=24 End_B1=24
9052 12:33:15.630011 25, 0x0, End_B0=25 End_B1=25
9053 12:33:15.630128 26, 0x0, End_B0=26 End_B1=26
9054 12:33:15.633080 27, 0x0, End_B0=27 End_B1=27
9055 12:33:15.636850 28, 0x0, End_B0=28 End_B1=28
9056 12:33:15.639668 29, 0x0, End_B0=29 End_B1=29
9057 12:33:15.639748 30, 0x0, End_B0=30 End_B1=30
9058 12:33:15.643559 31, 0x4141, End_B0=30 End_B1=30
9059 12:33:15.646689 Byte0 end_step=30 best_step=27
9060 12:33:15.650044 Byte1 end_step=30 best_step=27
9061 12:33:15.653093 Byte0 TX OE(2T, 0.5T) = (3, 3)
9062 12:33:15.656731 Byte1 TX OE(2T, 0.5T) = (3, 3)
9063 12:33:15.656808
9064 12:33:15.656871
9065 12:33:15.663160 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9066 12:33:15.666717 CH1 RK1: MR19=303, MR18=2207
9067 12:33:15.673641 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9068 12:33:15.676896 [RxdqsGatingPostProcess] freq 1600
9069 12:33:15.680248 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9070 12:33:15.683505 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 12:33:15.686886 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 12:33:15.690042 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 12:33:15.693213 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 12:33:15.696867 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 12:33:15.700122 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 12:33:15.703392 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 12:33:15.706624 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 12:33:15.709933 Pre-setting of DQS Precalculation
9079 12:33:15.713294 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9080 12:33:15.720443 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9081 12:33:15.726762 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 12:33:15.730068
9083 12:33:15.730152
9084 12:33:15.730219 [Calibration Summary] 3200 Mbps
9085 12:33:15.733234 CH 0, Rank 0
9086 12:33:15.733319 SW Impedance : PASS
9087 12:33:15.736873 DUTY Scan : NO K
9088 12:33:15.739772 ZQ Calibration : PASS
9089 12:33:15.739856 Jitter Meter : NO K
9090 12:33:15.743345 CBT Training : PASS
9091 12:33:15.747242 Write leveling : PASS
9092 12:33:15.747337 RX DQS gating : PASS
9093 12:33:15.750113 RX DQ/DQS(RDDQC) : PASS
9094 12:33:15.753139 TX DQ/DQS : PASS
9095 12:33:15.753239 RX DATLAT : PASS
9096 12:33:15.756746 RX DQ/DQS(Engine): PASS
9097 12:33:15.759819 TX OE : PASS
9098 12:33:15.759919 All Pass.
9099 12:33:15.760021
9100 12:33:15.760084 CH 0, Rank 1
9101 12:33:15.763561 SW Impedance : PASS
9102 12:33:15.766572 DUTY Scan : NO K
9103 12:33:15.766656 ZQ Calibration : PASS
9104 12:33:15.770038 Jitter Meter : NO K
9105 12:33:15.770122 CBT Training : PASS
9106 12:33:15.773672 Write leveling : PASS
9107 12:33:15.776678 RX DQS gating : PASS
9108 12:33:15.776761 RX DQ/DQS(RDDQC) : PASS
9109 12:33:15.779790 TX DQ/DQS : PASS
9110 12:33:15.783095 RX DATLAT : PASS
9111 12:33:15.783175 RX DQ/DQS(Engine): PASS
9112 12:33:15.786344 TX OE : PASS
9113 12:33:15.786420 All Pass.
9114 12:33:15.786483
9115 12:33:15.789699 CH 1, Rank 0
9116 12:33:15.789772 SW Impedance : PASS
9117 12:33:15.793443 DUTY Scan : NO K
9118 12:33:15.796549 ZQ Calibration : PASS
9119 12:33:15.796628 Jitter Meter : NO K
9120 12:33:15.800077 CBT Training : PASS
9121 12:33:15.803032 Write leveling : PASS
9122 12:33:15.803137 RX DQS gating : PASS
9123 12:33:15.806213 RX DQ/DQS(RDDQC) : PASS
9124 12:33:15.809519 TX DQ/DQS : PASS
9125 12:33:15.809595 RX DATLAT : PASS
9126 12:33:15.812707 RX DQ/DQS(Engine): PASS
9127 12:33:15.816075 TX OE : PASS
9128 12:33:15.816148 All Pass.
9129 12:33:15.816219
9130 12:33:15.816286 CH 1, Rank 1
9131 12:33:15.819821 SW Impedance : PASS
9132 12:33:15.823159 DUTY Scan : NO K
9133 12:33:15.823228 ZQ Calibration : PASS
9134 12:33:15.826429 Jitter Meter : NO K
9135 12:33:15.829602 CBT Training : PASS
9136 12:33:15.829672 Write leveling : PASS
9137 12:33:15.832846 RX DQS gating : PASS
9138 12:33:15.832974 RX DQ/DQS(RDDQC) : PASS
9139 12:33:15.836073 TX DQ/DQS : PASS
9140 12:33:15.839316 RX DATLAT : PASS
9141 12:33:15.839404 RX DQ/DQS(Engine): PASS
9142 12:33:15.842549 TX OE : PASS
9143 12:33:15.842624 All Pass.
9144 12:33:15.842687
9145 12:33:15.846587 DramC Write-DBI on
9146 12:33:15.849487 PER_BANK_REFRESH: Hybrid Mode
9147 12:33:15.849560 TX_TRACKING: ON
9148 12:33:15.859763 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9149 12:33:15.866371 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9150 12:33:15.873115 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 12:33:15.879604 [FAST_K] Save calibration result to emmc
9152 12:33:15.879758 sync common calibartion params.
9153 12:33:15.882665 sync cbt_mode0:1, 1:1
9154 12:33:15.886423 dram_init: ddr_geometry: 2
9155 12:33:15.886602 dram_init: ddr_geometry: 2
9156 12:33:15.889664 dram_init: ddr_geometry: 2
9157 12:33:15.892887 0:dram_rank_size:100000000
9158 12:33:15.896241 1:dram_rank_size:100000000
9159 12:33:15.899380 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9160 12:33:15.902630 DFS_SHUFFLE_HW_MODE: ON
9161 12:33:15.906450 dramc_set_vcore_voltage set vcore to 725000
9162 12:33:15.909405 Read voltage for 1600, 0
9163 12:33:15.909490 Vio18 = 0
9164 12:33:15.909557 Vcore = 725000
9165 12:33:15.912920 Vdram = 0
9166 12:33:15.913004 Vddq = 0
9167 12:33:15.913071 Vmddr = 0
9168 12:33:15.916105 switch to 3200 Mbps bootup
9169 12:33:15.919345 [DramcRunTimeConfig]
9170 12:33:15.919429 PHYPLL
9171 12:33:15.919496 DPM_CONTROL_AFTERK: ON
9172 12:33:15.922662 PER_BANK_REFRESH: ON
9173 12:33:15.926015 REFRESH_OVERHEAD_REDUCTION: ON
9174 12:33:15.926105 CMD_PICG_NEW_MODE: OFF
9175 12:33:15.929160 XRTWTW_NEW_MODE: ON
9176 12:33:15.933153 XRTRTR_NEW_MODE: ON
9177 12:33:15.933237 TX_TRACKING: ON
9178 12:33:15.936313 RDSEL_TRACKING: OFF
9179 12:33:15.936397 DQS Precalculation for DVFS: ON
9180 12:33:15.939510 RX_TRACKING: OFF
9181 12:33:15.939594 HW_GATING DBG: ON
9182 12:33:15.942797 ZQCS_ENABLE_LP4: ON
9183 12:33:15.942881 RX_PICG_NEW_MODE: ON
9184 12:33:15.945994 TX_PICG_NEW_MODE: ON
9185 12:33:15.949280 ENABLE_RX_DCM_DPHY: ON
9186 12:33:15.953007 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9187 12:33:15.953091 DUMMY_READ_FOR_TRACKING: OFF
9188 12:33:15.956073 !!! SPM_CONTROL_AFTERK: OFF
9189 12:33:15.959555 !!! SPM could not control APHY
9190 12:33:15.962706 IMPEDANCE_TRACKING: ON
9191 12:33:15.962790 TEMP_SENSOR: ON
9192 12:33:15.965863 HW_SAVE_FOR_SR: OFF
9193 12:33:15.965947 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9194 12:33:15.972937 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9195 12:33:15.973021 Read ODT Tracking: ON
9196 12:33:15.975895 Refresh Rate DeBounce: ON
9197 12:33:15.975977 DFS_NO_QUEUE_FLUSH: ON
9198 12:33:15.979553 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9199 12:33:15.982620 ENABLE_DFS_RUNTIME_MRW: OFF
9200 12:33:15.985633 DDR_RESERVE_NEW_MODE: ON
9201 12:33:15.985716 MR_CBT_SWITCH_FREQ: ON
9202 12:33:15.989254 =========================
9203 12:33:16.008469 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9204 12:33:16.012286 dram_init: ddr_geometry: 2
9205 12:33:16.030409 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9206 12:33:16.033805 dram_init: dram init end (result: 0)
9207 12:33:16.040128 DRAM-K: Full calibration passed in 24460 msecs
9208 12:33:16.043453 MRC: failed to locate region type 0.
9209 12:33:16.043535 DRAM rank0 size:0x100000000,
9210 12:33:16.046706 DRAM rank1 size=0x100000000
9211 12:33:16.056953 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9212 12:33:16.063444 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9213 12:33:16.069916 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9214 12:33:16.076614 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9215 12:33:16.080297 DRAM rank0 size:0x100000000,
9216 12:33:16.083319 DRAM rank1 size=0x100000000
9217 12:33:16.083426 CBMEM:
9218 12:33:16.086970 IMD: root @ 0xfffff000 254 entries.
9219 12:33:16.090000 IMD: root @ 0xffffec00 62 entries.
9220 12:33:16.093513 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9221 12:33:16.096526 WARNING: RO_VPD is uninitialized or empty.
9222 12:33:16.103206 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9223 12:33:16.110389 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9224 12:33:16.122788 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9225 12:33:16.134666 BS: romstage times (exec / console): total (unknown) / 23993 ms
9226 12:33:16.134775
9227 12:33:16.134869
9228 12:33:16.144368 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9229 12:33:16.147784 ARM64: Exception handlers installed.
9230 12:33:16.150925 ARM64: Testing exception
9231 12:33:16.154211 ARM64: Done test exception
9232 12:33:16.154321 Enumerating buses...
9233 12:33:16.157628 Show all devs... Before device enumeration.
9234 12:33:16.160830 Root Device: enabled 1
9235 12:33:16.164083 CPU_CLUSTER: 0: enabled 1
9236 12:33:16.164168 CPU: 00: enabled 1
9237 12:33:16.167862 Compare with tree...
9238 12:33:16.167940 Root Device: enabled 1
9239 12:33:16.171194 CPU_CLUSTER: 0: enabled 1
9240 12:33:16.174248 CPU: 00: enabled 1
9241 12:33:16.174331 Root Device scanning...
9242 12:33:16.177788 scan_static_bus for Root Device
9243 12:33:16.180698 CPU_CLUSTER: 0 enabled
9244 12:33:16.184352 scan_static_bus for Root Device done
9245 12:33:16.187263 scan_bus: bus Root Device finished in 8 msecs
9246 12:33:16.187410 done
9247 12:33:16.194159 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9248 12:33:16.197206 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9249 12:33:16.204076 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9250 12:33:16.207719 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9251 12:33:16.210666 Allocating resources...
9252 12:33:16.213932 Reading resources...
9253 12:33:16.217096 Root Device read_resources bus 0 link: 0
9254 12:33:16.217169 DRAM rank0 size:0x100000000,
9255 12:33:16.220447 DRAM rank1 size=0x100000000
9256 12:33:16.223740 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9257 12:33:16.227581 CPU: 00 missing read_resources
9258 12:33:16.230799 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9259 12:33:16.237345 Root Device read_resources bus 0 link: 0 done
9260 12:33:16.237427 Done reading resources.
9261 12:33:16.243789 Show resources in subtree (Root Device)...After reading.
9262 12:33:16.247607 Root Device child on link 0 CPU_CLUSTER: 0
9263 12:33:16.250855 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 12:33:16.260741 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 12:33:16.260940 CPU: 00
9266 12:33:16.264105 Root Device assign_resources, bus 0 link: 0
9267 12:33:16.267462 CPU_CLUSTER: 0 missing set_resources
9268 12:33:16.270430 Root Device assign_resources, bus 0 link: 0 done
9269 12:33:16.273741 Done setting resources.
9270 12:33:16.280896 Show resources in subtree (Root Device)...After assigning values.
9271 12:33:16.284032 Root Device child on link 0 CPU_CLUSTER: 0
9272 12:33:16.287663 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 12:33:16.297141 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 12:33:16.297283 CPU: 00
9275 12:33:16.300774 Done allocating resources.
9276 12:33:16.303911 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9277 12:33:16.307452 Enabling resources...
9278 12:33:16.307625 done.
9279 12:33:16.314071 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9280 12:33:16.314326 Initializing devices...
9281 12:33:16.317127 Root Device init
9282 12:33:16.317463 init hardware done!
9283 12:33:16.320748 0x00000018: ctrlr->caps
9284 12:33:16.323882 52.000 MHz: ctrlr->f_max
9285 12:33:16.324214 0.400 MHz: ctrlr->f_min
9286 12:33:16.327395 0x40ff8080: ctrlr->voltages
9287 12:33:16.327764 sclk: 390625
9288 12:33:16.330705 Bus Width = 1
9289 12:33:16.331201 sclk: 390625
9290 12:33:16.333935 Bus Width = 1
9291 12:33:16.334508 Early init status = 3
9292 12:33:16.340800 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9293 12:33:16.344011 in-header: 03 fc 00 00 01 00 00 00
9294 12:33:16.344446 in-data: 00
9295 12:33:16.350758 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9296 12:33:16.353938 in-header: 03 fd 00 00 00 00 00 00
9297 12:33:16.357025 in-data:
9298 12:33:16.360395 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9299 12:33:16.364239 in-header: 03 fc 00 00 01 00 00 00
9300 12:33:16.367302 in-data: 00
9301 12:33:16.370706 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9302 12:33:16.375020 in-header: 03 fd 00 00 00 00 00 00
9303 12:33:16.378217 in-data:
9304 12:33:16.381450 [SSUSB] Setting up USB HOST controller...
9305 12:33:16.384785 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9306 12:33:16.388468 [SSUSB] phy power-on done.
9307 12:33:16.391732 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9308 12:33:16.398039 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9309 12:33:16.401590 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9310 12:33:16.408435 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9311 12:33:16.415084 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9312 12:33:16.421137 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9313 12:33:16.427904 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9314 12:33:16.434783 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9315 12:33:16.437915 SPM: binary array size = 0x9dc
9316 12:33:16.441251 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9317 12:33:16.448199 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9318 12:33:16.454423 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9319 12:33:16.458218 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9320 12:33:16.464604 configure_display: Starting display init
9321 12:33:16.498118 anx7625_power_on_init: Init interface.
9322 12:33:16.501159 anx7625_disable_pd_protocol: Disabled PD feature.
9323 12:33:16.504277 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9324 12:33:16.532266 anx7625_start_dp_work: Secure OCM version=00
9325 12:33:16.535274 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9326 12:33:16.550578 sp_tx_get_edid_block: EDID Block = 1
9327 12:33:16.652926 Extracted contents:
9328 12:33:16.656238 header: 00 ff ff ff ff ff ff 00
9329 12:33:16.659997 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9330 12:33:16.663378 version: 01 04
9331 12:33:16.666519 basic params: 95 1f 11 78 0a
9332 12:33:16.669540 chroma info: 76 90 94 55 54 90 27 21 50 54
9333 12:33:16.673212 established: 00 00 00
9334 12:33:16.679766 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9335 12:33:16.683073 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9336 12:33:16.689660 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 12:33:16.696171 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9338 12:33:16.702622 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9339 12:33:16.705882 extensions: 00
9340 12:33:16.705988 checksum: fb
9341 12:33:16.706091
9342 12:33:16.709113 Manufacturer: IVO Model 57d Serial Number 0
9343 12:33:16.712885 Made week 0 of 2020
9344 12:33:16.712988 EDID version: 1.4
9345 12:33:16.715870 Digital display
9346 12:33:16.719607 6 bits per primary color channel
9347 12:33:16.719690 DisplayPort interface
9348 12:33:16.722482 Maximum image size: 31 cm x 17 cm
9349 12:33:16.725713 Gamma: 220%
9350 12:33:16.725784 Check DPMS levels
9351 12:33:16.729572 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9352 12:33:16.732693 First detailed timing is preferred timing
9353 12:33:16.735736 Established timings supported:
9354 12:33:16.739301 Standard timings supported:
9355 12:33:16.739412 Detailed timings
9356 12:33:16.746264 Hex of detail: 383680a07038204018303c0035ae10000019
9357 12:33:16.749199 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9358 12:33:16.756153 0780 0798 07c8 0820 hborder 0
9359 12:33:16.759188 0438 043b 0447 0458 vborder 0
9360 12:33:16.762363 -hsync -vsync
9361 12:33:16.762449 Did detailed timing
9362 12:33:16.766164 Hex of detail: 000000000000000000000000000000000000
9363 12:33:16.769349 Manufacturer-specified data, tag 0
9364 12:33:16.775779 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9365 12:33:16.775852 ASCII string: InfoVision
9366 12:33:16.782527 Hex of detail: 000000fe00523134304e574635205248200a
9367 12:33:16.785803 ASCII string: R140NWF5 RH
9368 12:33:16.785886 Checksum
9369 12:33:16.789150 Checksum: 0xfb (valid)
9370 12:33:16.792262 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9371 12:33:16.795702 DSI data_rate: 832800000 bps
9372 12:33:16.802231 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9373 12:33:16.805506 anx7625_parse_edid: pixelclock(138800).
9374 12:33:16.808634 hactive(1920), hsync(48), hfp(24), hbp(88)
9375 12:33:16.812538 vactive(1080), vsync(12), vfp(3), vbp(17)
9376 12:33:16.815151 anx7625_dsi_config: config dsi.
9377 12:33:16.821878 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9378 12:33:16.835203 anx7625_dsi_config: success to config DSI
9379 12:33:16.838508 anx7625_dp_start: MIPI phy setup OK.
9380 12:33:16.841595 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9381 12:33:16.845129 mtk_ddp_mode_set invalid vrefresh 60
9382 12:33:16.848569 main_disp_path_setup
9383 12:33:16.848668 ovl_layer_smi_id_en
9384 12:33:16.851564 ovl_layer_smi_id_en
9385 12:33:16.851672 ccorr_config
9386 12:33:16.851764 aal_config
9387 12:33:16.855273 gamma_config
9388 12:33:16.855418 postmask_config
9389 12:33:16.858333 dither_config
9390 12:33:16.861969 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9391 12:33:16.868285 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9392 12:33:16.871542 Root Device init finished in 551 msecs
9393 12:33:16.874747 CPU_CLUSTER: 0 init
9394 12:33:16.881867 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9395 12:33:16.884991 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9396 12:33:16.888085 APU_MBOX 0x190000b0 = 0x10001
9397 12:33:16.891399 APU_MBOX 0x190001b0 = 0x10001
9398 12:33:16.895155 APU_MBOX 0x190005b0 = 0x10001
9399 12:33:16.898436 APU_MBOX 0x190006b0 = 0x10001
9400 12:33:16.901614 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9401 12:33:16.914585 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9402 12:33:16.926877 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9403 12:33:16.933475 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9404 12:33:16.944937 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9405 12:33:16.953938 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9406 12:33:16.957099 CPU_CLUSTER: 0 init finished in 81 msecs
9407 12:33:16.960671 Devices initialized
9408 12:33:16.963874 Show all devs... After init.
9409 12:33:16.963954 Root Device: enabled 1
9410 12:33:16.966916 CPU_CLUSTER: 0: enabled 1
9411 12:33:16.970458 CPU: 00: enabled 1
9412 12:33:16.973332 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9413 12:33:16.977049 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9414 12:33:16.980229 ELOG: NV offset 0x57f000 size 0x1000
9415 12:33:16.986710 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9416 12:33:16.993642 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9417 12:33:16.996775 ELOG: Event(17) added with size 13 at 2023-06-06 12:33:05 UTC
9418 12:33:16.999963 out: cmd=0x121: 03 db 21 01 00 00 00 00
9419 12:33:17.004369 in-header: 03 d3 00 00 2c 00 00 00
9420 12:33:17.017438 in-data: 8c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9421 12:33:17.024086 ELOG: Event(A1) added with size 10 at 2023-06-06 12:33:05 UTC
9422 12:33:17.031260 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9423 12:33:17.034222 ELOG: Event(A0) added with size 9 at 2023-06-06 12:33:05 UTC
9424 12:33:17.040884 elog_add_boot_reason: Logged dev mode boot
9425 12:33:17.044159 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9426 12:33:17.047320 Finalize devices...
9427 12:33:17.047427 Devices finalized
9428 12:33:17.053901 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9429 12:33:17.057872 Writing coreboot table at 0xffe64000
9430 12:33:17.060951 0. 000000000010a000-0000000000113fff: RAMSTAGE
9431 12:33:17.063965 1. 0000000040000000-00000000400fffff: RAM
9432 12:33:17.067541 2. 0000000040100000-000000004032afff: RAMSTAGE
9433 12:33:17.074114 3. 000000004032b000-00000000545fffff: RAM
9434 12:33:17.077110 4. 0000000054600000-000000005465ffff: BL31
9435 12:33:17.080712 5. 0000000054660000-00000000ffe63fff: RAM
9436 12:33:17.083969 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9437 12:33:17.090409 7. 0000000100000000-000000023fffffff: RAM
9438 12:33:17.090508 Passing 5 GPIOs to payload:
9439 12:33:17.097427 NAME | PORT | POLARITY | VALUE
9440 12:33:17.100625 EC in RW | 0x000000aa | low | undefined
9441 12:33:17.107251 EC interrupt | 0x00000005 | low | undefined
9442 12:33:17.110635 TPM interrupt | 0x000000ab | high | undefined
9443 12:33:17.113855 SD card detect | 0x00000011 | high | undefined
9444 12:33:17.120735 speaker enable | 0x00000093 | high | undefined
9445 12:33:17.124192 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9446 12:33:17.127446 in-header: 03 f9 00 00 02 00 00 00
9447 12:33:17.127636 in-data: 02 00
9448 12:33:17.130831 ADC[4]: Raw value=904726 ID=7
9449 12:33:17.133995 ADC[3]: Raw value=213441 ID=1
9450 12:33:17.134214 RAM Code: 0x71
9451 12:33:17.137227 ADC[6]: Raw value=75701 ID=0
9452 12:33:17.140168 ADC[5]: Raw value=213072 ID=1
9453 12:33:17.140457 SKU Code: 0x1
9454 12:33:17.146790 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9455 12:33:17.149897 coreboot table: 964 bytes.
9456 12:33:17.153746 IMD ROOT 0. 0xfffff000 0x00001000
9457 12:33:17.157093 IMD SMALL 1. 0xffffe000 0x00001000
9458 12:33:17.160243 RO MCACHE 2. 0xffffc000 0x00001104
9459 12:33:17.163534 CONSOLE 3. 0xfff7c000 0x00080000
9460 12:33:17.166602 FMAP 4. 0xfff7b000 0x00000452
9461 12:33:17.170370 TIME STAMP 5. 0xfff7a000 0x00000910
9462 12:33:17.173337 VBOOT WORK 6. 0xfff66000 0x00014000
9463 12:33:17.177015 RAMOOPS 7. 0xffe66000 0x00100000
9464 12:33:17.180164 COREBOOT 8. 0xffe64000 0x00002000
9465 12:33:17.180240 IMD small region:
9466 12:33:17.183096 IMD ROOT 0. 0xffffec00 0x00000400
9467 12:33:17.186760 VPD 1. 0xffffeba0 0x0000004c
9468 12:33:17.189853 MMC STATUS 2. 0xffffeb80 0x00000004
9469 12:33:17.196812 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9470 12:33:17.196904 Probing TPM: done!
9471 12:33:17.203419 Connected to device vid:did:rid of 1ae0:0028:00
9472 12:33:17.213830 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9473 12:33:17.217186 Initialized TPM device CR50 revision 0
9474 12:33:17.217294 Checking cr50 for pending updates
9475 12:33:17.223744 Reading cr50 TPM mode
9476 12:33:17.232271 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9477 12:33:17.238749 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9478 12:33:17.278696 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9479 12:33:17.282328 Checking segment from ROM address 0x40100000
9480 12:33:17.285367 Checking segment from ROM address 0x4010001c
9481 12:33:17.292128 Loading segment from ROM address 0x40100000
9482 12:33:17.292221 code (compression=0)
9483 12:33:17.298952 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9484 12:33:17.309157 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9485 12:33:17.309287 it's not compressed!
9486 12:33:17.315830 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9487 12:33:17.318971 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9488 12:33:17.339076 Loading segment from ROM address 0x4010001c
9489 12:33:17.339194 Entry Point 0x80000000
9490 12:33:17.342874 Loaded segments
9491 12:33:17.346060 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9492 12:33:17.353035 Jumping to boot code at 0x80000000(0xffe64000)
9493 12:33:17.359130 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9494 12:33:17.366051 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9495 12:33:17.373841 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9496 12:33:17.376970 Checking segment from ROM address 0x40100000
9497 12:33:17.380265 Checking segment from ROM address 0x4010001c
9498 12:33:17.387109 Loading segment from ROM address 0x40100000
9499 12:33:17.387218 code (compression=1)
9500 12:33:17.393782 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9501 12:33:17.404167 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9502 12:33:17.404286 using LZMA
9503 12:33:17.412273 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9504 12:33:17.418638 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9505 12:33:17.422259 Loading segment from ROM address 0x4010001c
9506 12:33:17.422366 Entry Point 0x54601000
9507 12:33:17.425391 Loaded segments
9508 12:33:17.428649 NOTICE: MT8192 bl31_setup
9509 12:33:17.435817 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9510 12:33:17.438974 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9511 12:33:17.442290 WARNING: region 0:
9512 12:33:17.445511 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 12:33:17.445613 WARNING: region 1:
9514 12:33:17.452084 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9515 12:33:17.455846 WARNING: region 2:
9516 12:33:17.458950 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9517 12:33:17.462658 WARNING: region 3:
9518 12:33:17.465577 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 12:33:17.469161 WARNING: region 4:
9520 12:33:17.475528 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 12:33:17.475638 WARNING: region 5:
9522 12:33:17.479302 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 12:33:17.482657 WARNING: region 6:
9524 12:33:17.485840 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 12:33:17.489160 WARNING: region 7:
9526 12:33:17.492228 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 12:33:17.499188 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9528 12:33:17.502776 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9529 12:33:17.505979 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9530 12:33:17.512676 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9531 12:33:17.515754 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9532 12:33:17.519275 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9533 12:33:17.525699 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9534 12:33:17.529040 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9535 12:33:17.532551 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9536 12:33:17.539509 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9537 12:33:17.542818 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9538 12:33:17.549359 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9539 12:33:17.552758 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9540 12:33:17.556103 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9541 12:33:17.562853 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9542 12:33:17.565877 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9543 12:33:17.569664 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9544 12:33:17.575828 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9545 12:33:17.579364 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9546 12:33:17.582641 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9547 12:33:17.589132 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9548 12:33:17.593003 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9549 12:33:17.599403 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9550 12:33:17.602623 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9551 12:33:17.605840 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9552 12:33:17.612773 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9553 12:33:17.616245 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9554 12:33:17.622998 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9555 12:33:17.625924 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9556 12:33:17.629805 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9557 12:33:17.636060 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9558 12:33:17.639637 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9559 12:33:17.642711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9560 12:33:17.649844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9561 12:33:17.653108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9562 12:33:17.656342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9563 12:33:17.659638 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9564 12:33:17.665962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9565 12:33:17.669735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9566 12:33:17.672722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9567 12:33:17.676572 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9568 12:33:17.683199 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9569 12:33:17.686322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9570 12:33:17.689592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9571 12:33:17.692817 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9572 12:33:17.699469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9573 12:33:17.703200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9574 12:33:17.706386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9575 12:33:17.712771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9576 12:33:17.716591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9577 12:33:17.719708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9578 12:33:17.726399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9579 12:33:17.729948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9580 12:33:17.736500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9581 12:33:17.739618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9582 12:33:17.742758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9583 12:33:17.749706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9584 12:33:17.753285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9585 12:33:17.759840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9586 12:33:17.763116 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9587 12:33:17.769689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9588 12:33:17.773120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9589 12:33:17.779827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9590 12:33:17.783514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9591 12:33:17.786541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9592 12:33:17.793237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9593 12:33:17.796593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9594 12:33:17.803031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9595 12:33:17.806233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9596 12:33:17.813427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9597 12:33:17.816612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9598 12:33:17.819768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9599 12:33:17.826748 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9600 12:33:17.829895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9601 12:33:17.836619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9602 12:33:17.839696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9603 12:33:17.846264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9604 12:33:17.850119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9605 12:33:17.853409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9606 12:33:17.859552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9607 12:33:17.863235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9608 12:33:17.869848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9609 12:33:17.873211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9610 12:33:17.879640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9611 12:33:17.883510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9612 12:33:17.886717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9613 12:33:17.893499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9614 12:33:17.896625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9615 12:33:17.903296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9616 12:33:17.906601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9617 12:33:17.910439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9618 12:33:17.916992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9619 12:33:17.920322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9620 12:33:17.926486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9621 12:33:17.930384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9622 12:33:17.936695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9623 12:33:17.940447 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9624 12:33:17.943350 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9625 12:33:17.947045 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9626 12:33:17.953587 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9627 12:33:17.956534 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9628 12:33:17.959945 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9629 12:33:17.966853 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9630 12:33:17.970074 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9631 12:33:17.976508 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9632 12:33:17.979703 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9633 12:33:17.983610 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9634 12:33:17.990123 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9635 12:33:17.993221 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9636 12:33:17.999862 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9637 12:33:18.003405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9638 12:33:18.006394 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9639 12:33:18.013082 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9640 12:33:18.016904 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9641 12:33:18.023429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9642 12:33:18.026681 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9643 12:33:18.030428 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9644 12:33:18.033722 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9645 12:33:18.040186 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9646 12:33:18.043300 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9647 12:33:18.046637 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9648 12:33:18.050240 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9649 12:33:18.057158 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9650 12:33:18.060124 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9651 12:33:18.063265 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9652 12:33:18.070258 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9653 12:33:18.073829 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9654 12:33:18.076995 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9655 12:33:18.083534 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9656 12:33:18.086750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9657 12:33:18.093450 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9658 12:33:18.096762 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9659 12:33:18.100445 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9660 12:33:18.106754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9661 12:33:18.110339 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9662 12:33:18.117272 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9663 12:33:18.120285 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9664 12:33:18.123982 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9665 12:33:18.130521 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9666 12:33:18.133596 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9667 12:33:18.136904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9668 12:33:18.143383 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9669 12:33:18.147059 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9670 12:33:18.153490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9671 12:33:18.157107 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9672 12:33:18.160102 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9673 12:33:18.166818 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9674 12:33:18.169997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9675 12:33:18.176985 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9676 12:33:18.180163 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9677 12:33:18.183260 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9678 12:33:18.190393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9679 12:33:18.193682 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9680 12:33:18.196998 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9681 12:33:18.204010 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9682 12:33:18.207293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9683 12:33:18.213764 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9684 12:33:18.216789 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9685 12:33:18.220339 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9686 12:33:18.227154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9687 12:33:18.230227 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9688 12:33:18.236673 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9689 12:33:18.240613 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9690 12:33:18.243859 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9691 12:33:18.250216 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9692 12:33:18.253530 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9693 12:33:18.256814 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9694 12:33:18.263762 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9695 12:33:18.266705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9696 12:33:18.273463 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9697 12:33:18.277103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9698 12:33:18.280600 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9699 12:33:18.286645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9700 12:33:18.289855 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9701 12:33:18.297110 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9702 12:33:18.300369 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9703 12:33:18.303089 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9704 12:33:18.310192 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9705 12:33:18.313347 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9706 12:33:18.316698 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9707 12:33:18.323483 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9708 12:33:18.326585 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9709 12:33:18.333706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9710 12:33:18.336755 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9711 12:33:18.339864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9712 12:33:18.346248 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9713 12:33:18.350059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9714 12:33:18.356516 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9715 12:33:18.359826 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9716 12:33:18.366365 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9717 12:33:18.369870 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9718 12:33:18.373058 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9719 12:33:18.379705 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9720 12:33:18.382884 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9721 12:33:18.389583 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9722 12:33:18.392892 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9723 12:33:18.399074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9724 12:33:18.402414 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9725 12:33:18.406242 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9726 12:33:18.412752 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9727 12:33:18.416026 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9728 12:33:18.422524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9729 12:33:18.425515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9730 12:33:18.429469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9731 12:33:18.435937 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9732 12:33:18.439011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9733 12:33:18.445517 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9734 12:33:18.449122 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9735 12:33:18.455375 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9736 12:33:18.459206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9737 12:33:18.462462 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9738 12:33:18.468955 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9739 12:33:18.472264 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9740 12:33:18.479085 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9741 12:33:18.482245 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9742 12:33:18.485260 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9743 12:33:18.492137 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9744 12:33:18.495827 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9745 12:33:18.502203 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9746 12:33:18.505237 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9747 12:33:18.512394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9748 12:33:18.515563 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9749 12:33:18.518689 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9750 12:33:18.525229 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9751 12:33:18.528884 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9752 12:33:18.535295 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9753 12:33:18.538599 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9754 12:33:18.542460 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9755 12:33:18.548617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9756 12:33:18.552476 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9757 12:33:18.555346 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9758 12:33:18.559082 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9759 12:33:18.565635 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9760 12:33:18.568978 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9761 12:33:18.572292 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9762 12:33:18.578502 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9763 12:33:18.582391 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9764 12:33:18.585700 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9765 12:33:18.591928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9766 12:33:18.595501 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9767 12:33:18.602018 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9768 12:33:18.605255 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9769 12:33:18.608346 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9770 12:33:18.615243 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9771 12:33:18.618483 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9772 12:33:18.621621 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9773 12:33:18.628734 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9774 12:33:18.631888 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9775 12:33:18.635042 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9776 12:33:18.641642 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9777 12:33:18.644923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9778 12:33:18.651510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9779 12:33:18.655172 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9780 12:33:18.658227 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9781 12:33:18.664966 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9782 12:33:18.668624 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9783 12:33:18.671614 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9784 12:33:18.678579 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9785 12:33:18.681696 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9786 12:33:18.684807 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9787 12:33:18.691289 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9788 12:33:18.695208 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9789 12:33:18.701316 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9790 12:33:18.705049 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9791 12:33:18.708162 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9792 12:33:18.715121 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9793 12:33:18.718336 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9794 12:33:18.721445 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9795 12:33:18.728361 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9796 12:33:18.731732 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9797 12:33:18.734924 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9798 12:33:18.737983 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9799 12:33:18.744510 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9800 12:33:18.747780 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9801 12:33:18.751783 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9802 12:33:18.754440 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9803 12:33:18.761576 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9804 12:33:18.764574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9805 12:33:18.767995 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9806 12:33:18.771613 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9807 12:33:18.778220 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9808 12:33:18.781322 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9809 12:33:18.784522 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9810 12:33:18.791563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9811 12:33:18.794873 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9812 12:33:18.801303 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9813 12:33:18.804536 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9814 12:33:18.807632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9815 12:33:18.814576 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9816 12:33:18.817596 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9817 12:33:18.824381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9818 12:33:18.827678 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9819 12:33:18.831272 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9820 12:33:18.838129 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9821 12:33:18.841282 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9822 12:33:18.847778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9823 12:33:18.850948 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9824 12:33:18.854177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9825 12:33:18.861307 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9826 12:33:18.864577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9827 12:33:18.870930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9828 12:33:18.874634 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9829 12:33:18.881215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9830 12:33:18.884282 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9831 12:33:18.887285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9832 12:33:18.894074 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9833 12:33:18.897344 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9834 12:33:18.904623 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9835 12:33:18.907831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9836 12:33:18.911136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9837 12:33:18.917468 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9838 12:33:18.921128 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9839 12:33:18.927454 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9840 12:33:18.930768 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9841 12:33:18.934467 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9842 12:33:18.940741 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9843 12:33:18.944480 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9844 12:33:18.950850 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9845 12:33:18.954182 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9846 12:33:18.957395 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9847 12:33:18.963968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9848 12:33:18.967805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9849 12:33:18.974127 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9850 12:33:18.977319 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9851 12:33:18.981177 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9852 12:33:18.987229 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9853 12:33:18.990809 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9854 12:33:18.997581 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9855 12:33:19.001089 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9856 12:33:19.004043 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9857 12:33:19.010423 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9858 12:33:19.013739 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9859 12:33:19.020631 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9860 12:33:19.023817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9861 12:33:19.030371 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9862 12:33:19.034066 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9863 12:33:19.037304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9864 12:33:19.043721 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9865 12:33:19.047288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9866 12:33:19.050320 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9867 12:33:19.057356 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9868 12:33:19.060749 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9869 12:33:19.067309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9870 12:33:19.070665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9871 12:33:19.077245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9872 12:33:19.080386 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9873 12:33:19.083647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9874 12:33:19.090813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9875 12:33:19.094076 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9876 12:33:19.100734 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9877 12:33:19.103866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9878 12:33:19.107513 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9879 12:33:19.114164 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9880 12:33:19.117496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9881 12:33:19.120636 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9882 12:33:19.127144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9883 12:33:19.130450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9884 12:33:19.137480 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9885 12:33:19.140556 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9886 12:33:19.147448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9887 12:33:19.150628 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9888 12:33:19.157549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9889 12:33:19.160406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9890 12:33:19.163604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9891 12:33:19.170707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9892 12:33:19.173907 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9893 12:33:19.180523 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9894 12:33:19.183728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9895 12:33:19.190141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9896 12:33:19.193427 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9897 12:33:19.197200 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9898 12:33:19.203662 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9899 12:33:19.206754 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9900 12:33:19.213412 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9901 12:33:19.217015 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9902 12:33:19.223791 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9903 12:33:19.226939 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9904 12:33:19.230015 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9905 12:33:19.236555 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9906 12:33:19.240527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9907 12:33:19.247195 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9908 12:33:19.250113 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9909 12:33:19.256844 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9910 12:33:19.260456 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9911 12:33:19.266510 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9912 12:33:19.270153 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9913 12:33:19.273510 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9914 12:33:19.279913 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9915 12:33:19.283131 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9916 12:33:19.290230 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9917 12:33:19.293427 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9918 12:33:19.299756 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9919 12:33:19.303090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9920 12:33:19.306395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9921 12:33:19.313452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9922 12:33:19.316497 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9923 12:33:19.323253 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9924 12:33:19.326266 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9925 12:33:19.333100 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9926 12:33:19.336377 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9927 12:33:19.340152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9928 12:33:19.346505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9929 12:33:19.349759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9930 12:33:19.356331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9931 12:33:19.360097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9932 12:33:19.363221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9933 12:33:19.370006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9934 12:33:19.373145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9935 12:33:19.379814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9936 12:33:19.383071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9937 12:33:19.389648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9938 12:33:19.392890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9939 12:33:19.399941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9940 12:33:19.403147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9941 12:33:19.409669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9942 12:33:19.412957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9943 12:33:19.419907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9944 12:33:19.423220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9945 12:33:19.430005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9946 12:33:19.433273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9947 12:33:19.439701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9948 12:33:19.443301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9949 12:33:19.449621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9950 12:33:19.452860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9951 12:33:19.459805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9952 12:33:19.463044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9953 12:33:19.469430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9954 12:33:19.473248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9955 12:33:19.479772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9956 12:33:19.482960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9957 12:33:19.489368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9958 12:33:19.492632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9959 12:33:19.499595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9960 12:33:19.502989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9961 12:33:19.506202 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9962 12:33:19.509947 INFO: [APUAPC] vio 0
9963 12:33:19.513206 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9964 12:33:19.519715 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9965 12:33:19.523362 INFO: [APUAPC] D0_APC_0: 0x400510
9966 12:33:19.526715 INFO: [APUAPC] D0_APC_1: 0x0
9967 12:33:19.530067 INFO: [APUAPC] D0_APC_2: 0x1540
9968 12:33:19.530149 INFO: [APUAPC] D0_APC_3: 0x0
9969 12:33:19.533131 INFO: [APUAPC] D1_APC_0: 0xffffffff
9970 12:33:19.536878 INFO: [APUAPC] D1_APC_1: 0xffffffff
9971 12:33:19.540208 INFO: [APUAPC] D1_APC_2: 0x3fffff
9972 12:33:19.543235 INFO: [APUAPC] D1_APC_3: 0x0
9973 12:33:19.546927 INFO: [APUAPC] D2_APC_0: 0xffffffff
9974 12:33:19.549906 INFO: [APUAPC] D2_APC_1: 0xffffffff
9975 12:33:19.553104 INFO: [APUAPC] D2_APC_2: 0x3fffff
9976 12:33:19.557036 INFO: [APUAPC] D2_APC_3: 0x0
9977 12:33:19.560358 INFO: [APUAPC] D3_APC_0: 0xffffffff
9978 12:33:19.563501 INFO: [APUAPC] D3_APC_1: 0xffffffff
9979 12:33:19.566691 INFO: [APUAPC] D3_APC_2: 0x3fffff
9980 12:33:19.570137 INFO: [APUAPC] D3_APC_3: 0x0
9981 12:33:19.573365 INFO: [APUAPC] D4_APC_0: 0xffffffff
9982 12:33:19.576449 INFO: [APUAPC] D4_APC_1: 0xffffffff
9983 12:33:19.580245 INFO: [APUAPC] D4_APC_2: 0x3fffff
9984 12:33:19.583151 INFO: [APUAPC] D4_APC_3: 0x0
9985 12:33:19.586656 INFO: [APUAPC] D5_APC_0: 0xffffffff
9986 12:33:19.590254 INFO: [APUAPC] D5_APC_1: 0xffffffff
9987 12:33:19.593430 INFO: [APUAPC] D5_APC_2: 0x3fffff
9988 12:33:19.596692 INFO: [APUAPC] D5_APC_3: 0x0
9989 12:33:19.599908 INFO: [APUAPC] D6_APC_0: 0xffffffff
9990 12:33:19.602991 INFO: [APUAPC] D6_APC_1: 0xffffffff
9991 12:33:19.606965 INFO: [APUAPC] D6_APC_2: 0x3fffff
9992 12:33:19.610120 INFO: [APUAPC] D6_APC_3: 0x0
9993 12:33:19.613205 INFO: [APUAPC] D7_APC_0: 0xffffffff
9994 12:33:19.616480 INFO: [APUAPC] D7_APC_1: 0xffffffff
9995 12:33:19.619770 INFO: [APUAPC] D7_APC_2: 0x3fffff
9996 12:33:19.622929 INFO: [APUAPC] D7_APC_3: 0x0
9997 12:33:19.626594 INFO: [APUAPC] D8_APC_0: 0xffffffff
9998 12:33:19.629832 INFO: [APUAPC] D8_APC_1: 0xffffffff
9999 12:33:19.633119 INFO: [APUAPC] D8_APC_2: 0x3fffff
10000 12:33:19.636581 INFO: [APUAPC] D8_APC_3: 0x0
10001 12:33:19.639575 INFO: [APUAPC] D9_APC_0: 0xffffffff
10002 12:33:19.643182 INFO: [APUAPC] D9_APC_1: 0xffffffff
10003 12:33:19.646728 INFO: [APUAPC] D9_APC_2: 0x3fffff
10004 12:33:19.649878 INFO: [APUAPC] D9_APC_3: 0x0
10005 12:33:19.653439 INFO: [APUAPC] D10_APC_0: 0xffffffff
10006 12:33:19.656470 INFO: [APUAPC] D10_APC_1: 0xffffffff
10007 12:33:19.659666 INFO: [APUAPC] D10_APC_2: 0x3fffff
10008 12:33:19.662890 INFO: [APUAPC] D10_APC_3: 0x0
10009 12:33:19.666156 INFO: [APUAPC] D11_APC_0: 0xffffffff
10010 12:33:19.669420 INFO: [APUAPC] D11_APC_1: 0xffffffff
10011 12:33:19.673271 INFO: [APUAPC] D11_APC_2: 0x3fffff
10012 12:33:19.676564 INFO: [APUAPC] D11_APC_3: 0x0
10013 12:33:19.679801 INFO: [APUAPC] D12_APC_0: 0xffffffff
10014 12:33:19.683036 INFO: [APUAPC] D12_APC_1: 0xffffffff
10015 12:33:19.686543 INFO: [APUAPC] D12_APC_2: 0x3fffff
10016 12:33:19.689581 INFO: [APUAPC] D12_APC_3: 0x0
10017 12:33:19.693139 INFO: [APUAPC] D13_APC_0: 0xffffffff
10018 12:33:19.696185 INFO: [APUAPC] D13_APC_1: 0xffffffff
10019 12:33:19.699761 INFO: [APUAPC] D13_APC_2: 0x3fffff
10020 12:33:19.702920 INFO: [APUAPC] D13_APC_3: 0x0
10021 12:33:19.706025 INFO: [APUAPC] D14_APC_0: 0xffffffff
10022 12:33:19.709907 INFO: [APUAPC] D14_APC_1: 0xffffffff
10023 12:33:19.713286 INFO: [APUAPC] D14_APC_2: 0x3fffff
10024 12:33:19.716369 INFO: [APUAPC] D14_APC_3: 0x0
10025 12:33:19.719564 INFO: [APUAPC] D15_APC_0: 0xffffffff
10026 12:33:19.722769 INFO: [APUAPC] D15_APC_1: 0xffffffff
10027 12:33:19.725986 INFO: [APUAPC] D15_APC_2: 0x3fffff
10028 12:33:19.729785 INFO: [APUAPC] D15_APC_3: 0x0
10029 12:33:19.732852 INFO: [APUAPC] APC_CON: 0x4
10030 12:33:19.732964 INFO: [NOCDAPC] D0_APC_0: 0x0
10031 12:33:19.736120 INFO: [NOCDAPC] D0_APC_1: 0x0
10032 12:33:19.739444 INFO: [NOCDAPC] D1_APC_0: 0x0
10033 12:33:19.742764 INFO: [NOCDAPC] D1_APC_1: 0xfff
10034 12:33:19.745910 INFO: [NOCDAPC] D2_APC_0: 0x0
10035 12:33:19.749195 INFO: [NOCDAPC] D2_APC_1: 0xfff
10036 12:33:19.752747 INFO: [NOCDAPC] D3_APC_0: 0x0
10037 12:33:19.756268 INFO: [NOCDAPC] D3_APC_1: 0xfff
10038 12:33:19.759241 INFO: [NOCDAPC] D4_APC_0: 0x0
10039 12:33:19.762754 INFO: [NOCDAPC] D4_APC_1: 0xfff
10040 12:33:19.762854 INFO: [NOCDAPC] D5_APC_0: 0x0
10041 12:33:19.765820 INFO: [NOCDAPC] D5_APC_1: 0xfff
10042 12:33:19.769560 INFO: [NOCDAPC] D6_APC_0: 0x0
10043 12:33:19.772627 INFO: [NOCDAPC] D6_APC_1: 0xfff
10044 12:33:19.776018 INFO: [NOCDAPC] D7_APC_0: 0x0
10045 12:33:19.779269 INFO: [NOCDAPC] D7_APC_1: 0xfff
10046 12:33:19.782450 INFO: [NOCDAPC] D8_APC_0: 0x0
10047 12:33:19.786418 INFO: [NOCDAPC] D8_APC_1: 0xfff
10048 12:33:19.789602 INFO: [NOCDAPC] D9_APC_0: 0x0
10049 12:33:19.792821 INFO: [NOCDAPC] D9_APC_1: 0xfff
10050 12:33:19.796078 INFO: [NOCDAPC] D10_APC_0: 0x0
10051 12:33:19.796152 INFO: [NOCDAPC] D10_APC_1: 0xfff
10052 12:33:19.799163 INFO: [NOCDAPC] D11_APC_0: 0x0
10053 12:33:19.802923 INFO: [NOCDAPC] D11_APC_1: 0xfff
10054 12:33:19.806034 INFO: [NOCDAPC] D12_APC_0: 0x0
10055 12:33:19.809208 INFO: [NOCDAPC] D12_APC_1: 0xfff
10056 12:33:19.812422 INFO: [NOCDAPC] D13_APC_0: 0x0
10057 12:33:19.815699 INFO: [NOCDAPC] D13_APC_1: 0xfff
10058 12:33:19.818972 INFO: [NOCDAPC] D14_APC_0: 0x0
10059 12:33:19.822816 INFO: [NOCDAPC] D14_APC_1: 0xfff
10060 12:33:19.826037 INFO: [NOCDAPC] D15_APC_0: 0x0
10061 12:33:19.829459 INFO: [NOCDAPC] D15_APC_1: 0xfff
10062 12:33:19.832696 INFO: [NOCDAPC] APC_CON: 0x4
10063 12:33:19.835792 INFO: [APUAPC] set_apusys_apc done
10064 12:33:19.839134 INFO: [DEVAPC] devapc_init done
10065 12:33:19.842366 INFO: GICv3 without legacy support detected.
10066 12:33:19.846165 INFO: ARM GICv3 driver initialized in EL3
10067 12:33:19.849410 INFO: Maximum SPI INTID supported: 639
10068 12:33:19.852826 INFO: BL31: Initializing runtime services
10069 12:33:19.858974 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10070 12:33:19.862113 INFO: SPM: enable CPC mode
10071 12:33:19.868880 INFO: mcdi ready for mcusys-off-idle and system suspend
10072 12:33:19.872697 INFO: BL31: Preparing for EL3 exit to normal world
10073 12:33:19.875599 INFO: Entry point address = 0x80000000
10074 12:33:19.878842 INFO: SPSR = 0x8
10075 12:33:19.883920
10076 12:33:19.884002
10077 12:33:19.884066
10078 12:33:19.887173 Starting depthcharge on Spherion...
10079 12:33:19.887256
10080 12:33:19.887321 Wipe memory regions:
10081 12:33:19.887424
10082 12:33:19.888051 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10083 12:33:19.888150 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10084 12:33:19.888232 Setting prompt string to ['asurada:']
10085 12:33:19.888312 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10086 12:33:19.890266 [0x00000040000000, 0x00000054600000)
10087 12:33:20.012554
10088 12:33:20.012712 [0x00000054660000, 0x00000080000000)
10089 12:33:20.273196
10090 12:33:20.273356 [0x000000821a7280, 0x000000ffe64000)
10091 12:33:21.017847
10092 12:33:21.018052 [0x00000100000000, 0x00000240000000)
10093 12:33:22.908406
10094 12:33:22.911308 Initializing XHCI USB controller at 0x11200000.
10095 12:33:23.949270
10096 12:33:23.953096 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10097 12:33:23.953188
10098 12:33:23.953255
10099 12:33:23.953316
10100 12:33:23.953598 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 12:33:24.053936 asurada: tftpboot 192.168.201.1 10605812/tftp-deploy-xnewfqnq/kernel/image.itb 10605812/tftp-deploy-xnewfqnq/kernel/cmdline
10103 12:33:24.054132 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 12:33:24.054277 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10105 12:33:24.057926 tftpboot 192.168.201.1 10605812/tftp-deploy-xnewfqnq/kernel/image.ittp-deploy-xnewfqnq/kernel/cmdline
10106 12:33:24.058011
10107 12:33:24.058077 Waiting for link
10108 12:33:24.218782
10109 12:33:24.218942 R8152: Initializing
10110 12:33:24.219017
10111 12:33:24.221789 Version 9 (ocp_data = 6010)
10112 12:33:24.221874
10113 12:33:24.224938 R8152: Done initializing
10114 12:33:24.225022
10115 12:33:24.225089 Adding net device
10116 12:33:26.097815
10117 12:33:26.097974 done.
10118 12:33:26.098041
10119 12:33:26.098103 MAC: 00:e0:4c:78:7a:aa
10120 12:33:26.098162
10121 12:33:26.101073 Sending DHCP discover... done.
10122 12:33:26.101157
10123 12:33:26.104599 Waiting for reply... done.
10124 12:33:26.104683
10125 12:33:26.107530 Sending DHCP request... done.
10126 12:33:26.107612
10127 12:33:26.107678 Waiting for reply... done.
10128 12:33:26.107739
10129 12:33:26.111279 My ip is 192.168.201.12
10130 12:33:26.111406
10131 12:33:26.114438 The DHCP server ip is 192.168.201.1
10132 12:33:26.114556
10133 12:33:26.117727 TFTP server IP predefined by user: 192.168.201.1
10134 12:33:26.117827
10135 12:33:26.124263 Bootfile predefined by user: 10605812/tftp-deploy-xnewfqnq/kernel/image.itb
10136 12:33:26.124347
10137 12:33:26.127522 Sending tftp read request... done.
10138 12:33:26.127605
10139 12:33:26.130819 Waiting for the transfer...
10140 12:33:26.130902
10141 12:33:26.400773 00000000 ################################################################
10142 12:33:26.400936
10143 12:33:26.662024 00080000 ################################################################
10144 12:33:26.662181
10145 12:33:26.924570 00100000 ################################################################
10146 12:33:26.924710
10147 12:33:27.181886 00180000 ################################################################
10148 12:33:27.182029
10149 12:33:27.449920 00200000 ################################################################
10150 12:33:27.450061
10151 12:33:27.729553 00280000 ################################################################
10152 12:33:27.729708
10153 12:33:27.991248 00300000 ################################################################
10154 12:33:27.991429
10155 12:33:28.249011 00380000 ################################################################
10156 12:33:28.249163
10157 12:33:28.501747 00400000 ################################################################
10158 12:33:28.501896
10159 12:33:28.754639 00480000 ################################################################
10160 12:33:28.754792
10161 12:33:29.004717 00500000 ################################################################
10162 12:33:29.004869
10163 12:33:29.260369 00580000 ################################################################
10164 12:33:29.260524
10165 12:33:29.517777 00600000 ################################################################
10166 12:33:29.517933
10167 12:33:29.785775 00680000 ################################################################
10168 12:33:29.785924
10169 12:33:30.033109 00700000 ################################################################
10170 12:33:30.033275
10171 12:33:30.272086 00780000 ################################################################
10172 12:33:30.272252
10173 12:33:30.524887 00800000 ################################################################
10174 12:33:30.525083
10175 12:33:30.764031 00880000 ################################################################
10176 12:33:30.764181
10177 12:33:31.003990 00900000 ################################################################
10178 12:33:31.004164
10179 12:33:31.244096 00980000 ################################################################
10180 12:33:31.244247
10181 12:33:31.484130 00a00000 ################################################################
10182 12:33:31.484312
10183 12:33:31.728082 00a80000 ################################################################
10184 12:33:31.728233
10185 12:33:31.975370 00b00000 ################################################################
10186 12:33:31.975511
10187 12:33:32.217320 00b80000 ################################################################
10188 12:33:32.217469
10189 12:33:32.460238 00c00000 ################################################################
10190 12:33:32.460422
10191 12:33:32.704800 00c80000 ################################################################
10192 12:33:32.704981
10193 12:33:32.951490 00d00000 ################################################################
10194 12:33:32.951637
10195 12:33:33.197398 00d80000 ################################################################
10196 12:33:33.197588
10197 12:33:33.453002 00e00000 ################################################################
10198 12:33:33.453193
10199 12:33:33.695675 00e80000 ################################################################
10200 12:33:33.695838
10201 12:33:33.940275 00f00000 ################################################################
10202 12:33:33.940461
10203 12:33:34.189984 00f80000 ################################################################
10204 12:33:34.190158
10205 12:33:34.450423 01000000 ################################################################
10206 12:33:34.450599
10207 12:33:34.710248 01080000 ################################################################
10208 12:33:34.710475
10209 12:33:34.950138 01100000 ################################################################
10210 12:33:34.950315
10211 12:33:35.192584 01180000 ################################################################
10212 12:33:35.192789
10213 12:33:35.438854 01200000 ################################################################
10214 12:33:35.438998
10215 12:33:35.692954 01280000 ################################################################
10216 12:33:35.693094
10217 12:33:35.935099 01300000 ################################################################
10218 12:33:35.935241
10219 12:33:36.177284 01380000 ################################################################
10220 12:33:36.177418
10221 12:33:36.423137 01400000 ################################################################
10222 12:33:36.423291
10223 12:33:36.677809 01480000 ################################################################
10224 12:33:36.677966
10225 12:33:36.918632 01500000 ################################################################
10226 12:33:36.918789
10227 12:33:37.167012 01580000 ################################################################
10228 12:33:37.167187
10229 12:33:37.411599 01600000 ################################################################
10230 12:33:37.411764
10231 12:33:37.655064 01680000 ################################################################
10232 12:33:37.655243
10233 12:33:37.903677 01700000 ################################################################
10234 12:33:37.903838
10235 12:33:38.147709 01780000 ################################################################
10236 12:33:38.147890
10237 12:33:38.388570 01800000 ################################################################
10238 12:33:38.388720
10239 12:33:38.633014 01880000 ################################################################
10240 12:33:38.633191
10241 12:33:38.872283 01900000 ################################################################
10242 12:33:38.872460
10243 12:33:39.123470 01980000 ################################################################
10244 12:33:39.123620
10245 12:33:39.371136 01a00000 ############################################################### done.
10246 12:33:39.371311
10247 12:33:39.374433 The bootfile was 27778038 bytes long.
10248 12:33:39.374539
10249 12:33:39.378120 Sending tftp read request... done.
10250 12:33:39.378267
10251 12:33:39.378378 Waiting for the transfer...
10252 12:33:39.378541
10253 12:33:39.381378 00000000 # done.
10254 12:33:39.381482
10255 12:33:39.387936 Command line loaded dynamically from TFTP file: 10605812/tftp-deploy-xnewfqnq/kernel/cmdline
10256 12:33:39.388019
10257 12:33:39.407879 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10258 12:33:39.407999
10259 12:33:39.410994 Loading FIT.
10260 12:33:39.411093
10261 12:33:39.411188 Image ramdisk-1 has 17642329 bytes.
10262 12:33:39.414671
10263 12:33:39.414778 Image fdt-1 has 46924 bytes.
10264 12:33:39.414877
10265 12:33:39.417794 Image kernel-1 has 10086749 bytes.
10266 12:33:39.417896
10267 12:33:39.427670 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 12:33:39.427773
10269 12:33:39.444476 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 12:33:39.444602
10271 12:33:39.451063 Choosing best match conf-1 for compat google,spherion-rev2.
10272 12:33:39.454168
10273 12:33:39.459354 Connected to device vid:did:rid of 1ae0:0028:00
10274 12:33:39.467271
10275 12:33:39.471282 tpm_get_response: command 0x17b, return code 0x0
10276 12:33:39.471820
10277 12:33:39.474470 ec_init: CrosEC protocol v3 supported (256, 248)
10278 12:33:39.478392
10279 12:33:39.481821 tpm_cleanup: add release locality here.
10280 12:33:39.482437
10281 12:33:39.482823 Shutting down all USB controllers.
10282 12:33:39.483378
10283 12:33:39.484838 Removing current net device
10284 12:33:39.485356
10285 12:33:39.491681 Exiting depthcharge with code 4 at timestamp: 48887148
10286 12:33:39.492342
10287 12:33:39.494657 LZMA decompressing kernel-1 to 0x821a6718
10288 12:33:39.495114
10289 12:33:39.498691 LZMA decompressing kernel-1 to 0x40000000
10290 12:33:40.764440
10291 12:33:40.764737 jumping to kernel
10292 12:33:40.765528 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10293 12:33:40.765782 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10294 12:33:40.766002 Setting prompt string to ['Linux version [0-9]']
10295 12:33:40.766269 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 12:33:40.766507 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 12:33:40.846497
10298 12:33:40.849410 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 12:33:40.853894 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10300 12:33:40.854362 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 12:33:40.854801 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10302 12:33:40.855195 Using line separator: #'\n'#
10303 12:33:40.855716 No login prompt set.
10304 12:33:40.856057 Parsing kernel messages
10305 12:33:40.856356 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10306 12:33:40.856877 [login-action] Waiting for messages, (timeout 00:04:04)
10307 12:33:40.872779 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10308 12:33:40.876522 [ 0.000000] random: crng init done
10309 12:33:40.879888 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10310 12:33:40.883199 [ 0.000000] efi: UEFI not found.
10311 12:33:40.893125 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10312 12:33:40.899444 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10313 12:33:40.909514 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10314 12:33:40.919610 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10315 12:33:40.925979 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10316 12:33:40.929244 [ 0.000000] printk: bootconsole [mtk8250] enabled
10317 12:33:40.937887 [ 0.000000] NUMA: No NUMA configuration found
10318 12:33:40.944531 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10319 12:33:40.951354 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10320 12:33:40.951800 [ 0.000000] Zone ranges:
10321 12:33:40.958077 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10322 12:33:40.960921 [ 0.000000] DMA32 empty
10323 12:33:40.967378 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10324 12:33:40.970581 [ 0.000000] Movable zone start for each node
10325 12:33:40.973929 [ 0.000000] Early memory node ranges
10326 12:33:40.980418 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10327 12:33:40.987145 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10328 12:33:40.994297 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10329 12:33:41.000981 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10330 12:33:41.007361 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10331 12:33:41.013866 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10332 12:33:41.070778 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10333 12:33:41.077728 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10334 12:33:41.084329 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10335 12:33:41.087512 [ 0.000000] psci: probing for conduit method from DT.
10336 12:33:41.093798 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10337 12:33:41.097084 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10338 12:33:41.103718 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10339 12:33:41.107083 [ 0.000000] psci: SMC Calling Convention v1.2
10340 12:33:41.113564 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10341 12:33:41.116806 [ 0.000000] Detected VIPT I-cache on CPU0
10342 12:33:41.123492 [ 0.000000] CPU features: detected: GIC system register CPU interface
10343 12:33:41.130050 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10344 12:33:41.136859 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10345 12:33:41.143412 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10346 12:33:41.150376 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10347 12:33:41.156928 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10348 12:33:41.163764 [ 0.000000] alternatives: applying boot alternatives
10349 12:33:41.166722 [ 0.000000] Fallback order for Node 0: 0
10350 12:33:41.176924 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10351 12:33:41.177519 [ 0.000000] Policy zone: Normal
10352 12:33:41.199864 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10353 12:33:41.209938 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10354 12:33:41.220365 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10355 12:33:41.229915 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10356 12:33:41.236441 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10357 12:33:41.240241 <6>[ 0.000000] software IO TLB: area num 8.
10358 12:33:41.296693 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10359 12:33:41.445483 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10360 12:33:41.452433 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10361 12:33:41.458878 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10362 12:33:41.461813 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10363 12:33:41.469193 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10364 12:33:41.475559 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10365 12:33:41.478655 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10366 12:33:41.488617 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10367 12:33:41.495168 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10368 12:33:41.501524 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10369 12:33:41.508385 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10370 12:33:41.511344 <6>[ 0.000000] GICv3: 608 SPIs implemented
10371 12:33:41.515102 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10372 12:33:41.521578 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10373 12:33:41.524864 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10374 12:33:41.531366 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10375 12:33:41.545167 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10376 12:33:41.555012 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10377 12:33:41.564877 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10378 12:33:41.572538 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10379 12:33:41.585606 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10380 12:33:41.591955 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10381 12:33:41.598653 <6>[ 0.009173] Console: colour dummy device 80x25
10382 12:33:41.608814 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10383 12:33:41.611815 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10384 12:33:41.618738 <6>[ 0.029216] LSM: Security Framework initializing
10385 12:33:41.625273 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 12:33:41.635573 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 12:33:41.642046 <6>[ 0.051405] cblist_init_generic: Setting adjustable number of callback queues.
10388 12:33:41.648581 <6>[ 0.058873] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 12:33:41.655015 <6>[ 0.065212] cblist_init_generic: Setting shift to 3 and lim to 1.
10390 12:33:41.661569 <6>[ 0.071620] rcu: Hierarchical SRCU implementation.
10391 12:33:41.664783 <6>[ 0.076634] rcu: Max phase no-delay instances is 1000.
10392 12:33:41.673265 <6>[ 0.083648] EFI services will not be available.
10393 12:33:41.676292 <6>[ 0.088618] smp: Bringing up secondary CPUs ...
10394 12:33:41.685744 <6>[ 0.093669] Detected VIPT I-cache on CPU1
10395 12:33:41.692061 <6>[ 0.093739] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10396 12:33:41.698685 <6>[ 0.093772] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10397 12:33:41.701938 <6>[ 0.094107] Detected VIPT I-cache on CPU2
10398 12:33:41.712046 <6>[ 0.094156] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10399 12:33:41.718093 <6>[ 0.094172] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10400 12:33:41.721873 <6>[ 0.094431] Detected VIPT I-cache on CPU3
10401 12:33:41.728562 <6>[ 0.094478] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10402 12:33:41.735274 <6>[ 0.094492] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10403 12:33:41.741624 <6>[ 0.094799] CPU features: detected: Spectre-v4
10404 12:33:41.745000 <6>[ 0.094806] CPU features: detected: Spectre-BHB
10405 12:33:41.748211 <6>[ 0.094813] Detected PIPT I-cache on CPU4
10406 12:33:41.754774 <6>[ 0.094873] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10407 12:33:41.761970 <6>[ 0.094889] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10408 12:33:41.768456 <6>[ 0.095187] Detected PIPT I-cache on CPU5
10409 12:33:41.774266 <6>[ 0.095251] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10410 12:33:41.781497 <6>[ 0.095267] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10411 12:33:41.784332 <6>[ 0.095538] Detected PIPT I-cache on CPU6
10412 12:33:41.794391 <6>[ 0.095599] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10413 12:33:41.800846 <6>[ 0.095615] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10414 12:33:41.804134 <6>[ 0.095909] Detected PIPT I-cache on CPU7
10415 12:33:41.810688 <6>[ 0.095979] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10416 12:33:41.817664 <6>[ 0.095995] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10417 12:33:41.820507 <6>[ 0.096042] smp: Brought up 1 node, 8 CPUs
10418 12:33:41.827076 <6>[ 0.237512] SMP: Total of 8 processors activated.
10419 12:33:41.830899 <6>[ 0.242433] CPU features: detected: 32-bit EL0 Support
10420 12:33:41.840393 <6>[ 0.247797] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10421 12:33:41.847168 <6>[ 0.256596] CPU features: detected: Common not Private translations
10422 12:33:41.854093 <6>[ 0.263072] CPU features: detected: CRC32 instructions
10423 12:33:41.860310 <6>[ 0.268423] CPU features: detected: RCpc load-acquire (LDAPR)
10424 12:33:41.863576 <6>[ 0.274387] CPU features: detected: LSE atomic instructions
10425 12:33:41.870456 <6>[ 0.280204] CPU features: detected: Privileged Access Never
10426 12:33:41.876843 <6>[ 0.286001] CPU features: detected: RAS Extension Support
10427 12:33:41.883293 <6>[ 0.291645] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10428 12:33:41.887045 <6>[ 0.298913] CPU: All CPU(s) started at EL2
10429 12:33:41.893296 <6>[ 0.303229] alternatives: applying system-wide alternatives
10430 12:33:41.903205 <6>[ 0.313936] devtmpfs: initialized
10431 12:33:41.919245 <6>[ 0.322916] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10432 12:33:41.925829 <6>[ 0.332877] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10433 12:33:41.932388 <6>[ 0.341102] pinctrl core: initialized pinctrl subsystem
10434 12:33:41.935315 <6>[ 0.347883] DMI not present or invalid.
10435 12:33:41.942346 <6>[ 0.352292] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10436 12:33:41.952020 <6>[ 0.359178] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10437 12:33:41.958932 <6>[ 0.366762] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10438 12:33:41.968485 <6>[ 0.374986] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10439 12:33:41.971810 <6>[ 0.383229] audit: initializing netlink subsys (disabled)
10440 12:33:41.982251 <5>[ 0.388926] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10441 12:33:41.988188 <6>[ 0.389730] thermal_sys: Registered thermal governor 'step_wise'
10442 12:33:41.995110 <6>[ 0.396891] thermal_sys: Registered thermal governor 'power_allocator'
10443 12:33:41.998821 <6>[ 0.403151] cpuidle: using governor menu
10444 12:33:42.005040 <6>[ 0.414107] NET: Registered PF_QIPCRTR protocol family
10445 12:33:42.011546 <6>[ 0.419636] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10446 12:33:42.017939 <6>[ 0.426740] ASID allocator initialised with 32768 entries
10447 12:33:42.021134 <6>[ 0.433354] Serial: AMBA PL011 UART driver
10448 12:33:42.031879 <4>[ 0.442393] Trying to register duplicate clock ID: 134
10449 12:33:42.088866 <6>[ 0.502406] KASLR enabled
10450 12:33:42.103144 <6>[ 0.510220] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10451 12:33:42.109280 <6>[ 0.517233] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10452 12:33:42.116612 <6>[ 0.523723] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10453 12:33:42.122900 <6>[ 0.530726] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10454 12:33:42.129453 <6>[ 0.537213] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10455 12:33:42.135870 <6>[ 0.544218] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10456 12:33:42.142878 <6>[ 0.550704] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10457 12:33:42.149447 <6>[ 0.557706] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10458 12:33:42.152837 <6>[ 0.565236] ACPI: Interpreter disabled.
10459 12:33:42.161112 <6>[ 0.571738] iommu: Default domain type: Translated
10460 12:33:42.167809 <6>[ 0.576854] iommu: DMA domain TLB invalidation policy: strict mode
10461 12:33:42.171099 <5>[ 0.583516] SCSI subsystem initialized
10462 12:33:42.177711 <6>[ 0.587675] usbcore: registered new interface driver usbfs
10463 12:33:42.184669 <6>[ 0.593409] usbcore: registered new interface driver hub
10464 12:33:42.187716 <6>[ 0.598957] usbcore: registered new device driver usb
10465 12:33:42.194923 <6>[ 0.605107] pps_core: LinuxPPS API ver. 1 registered
10466 12:33:42.204766 <6>[ 0.610299] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10467 12:33:42.207959 <6>[ 0.619636] PTP clock support registered
10468 12:33:42.210983 <6>[ 0.623877] EDAC MC: Ver: 3.0.0
10469 12:33:42.218468 <6>[ 0.629090] FPGA manager framework
10470 12:33:42.225514 <6>[ 0.632776] Advanced Linux Sound Architecture Driver Initialized.
10471 12:33:42.228702 <6>[ 0.639547] vgaarb: loaded
10472 12:33:42.235370 <6>[ 0.642731] clocksource: Switched to clocksource arch_sys_counter
10473 12:33:42.238603 <5>[ 0.649181] VFS: Disk quotas dquot_6.6.0
10474 12:33:42.244813 <6>[ 0.653364] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10475 12:33:42.248274 <6>[ 0.660556] pnp: PnP ACPI: disabled
10476 12:33:42.256505 <6>[ 0.667233] NET: Registered PF_INET protocol family
10477 12:33:42.266867 <6>[ 0.672824] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10478 12:33:42.277563 <6>[ 0.685114] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10479 12:33:42.287187 <6>[ 0.693927] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10480 12:33:42.294219 <6>[ 0.701897] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10481 12:33:42.300571 <6>[ 0.710593] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10482 12:33:42.312568 <6>[ 0.720336] TCP: Hash tables configured (established 65536 bind 65536)
10483 12:33:42.319513 <6>[ 0.727195] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 12:33:42.326249 <6>[ 0.734393] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 12:33:42.332545 <6>[ 0.742103] NET: Registered PF_UNIX/PF_LOCAL protocol family
10486 12:33:42.339219 <6>[ 0.748207] RPC: Registered named UNIX socket transport module.
10487 12:33:42.342383 <6>[ 0.754358] RPC: Registered udp transport module.
10488 12:33:42.349544 <6>[ 0.759291] RPC: Registered tcp transport module.
10489 12:33:42.355723 <6>[ 0.764225] RPC: Registered tcp NFSv4.1 backchannel transport module.
10490 12:33:42.359308 <6>[ 0.770886] PCI: CLS 0 bytes, default 64
10491 12:33:42.362437 <6>[ 0.775282] Unpacking initramfs...
10492 12:33:42.387464 <6>[ 0.794846] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10493 12:33:42.397187 <6>[ 0.803510] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10494 12:33:42.400898 <6>[ 0.812379] kvm [1]: IPA Size Limit: 40 bits
10495 12:33:42.407463 <6>[ 0.816905] kvm [1]: GICv3: no GICV resource entry
10496 12:33:42.410908 <6>[ 0.821927] kvm [1]: disabling GICv2 emulation
10497 12:33:42.417218 <6>[ 0.826616] kvm [1]: GIC system register CPU interface enabled
10498 12:33:42.420453 <6>[ 0.832778] kvm [1]: vgic interrupt IRQ18
10499 12:33:42.427440 <6>[ 0.837130] kvm [1]: VHE mode initialized successfully
10500 12:33:42.433706 <5>[ 0.843525] Initialise system trusted keyrings
10501 12:33:42.440179 <6>[ 0.848349] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10502 12:33:42.447320 <6>[ 0.858397] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10503 12:33:42.453941 <5>[ 0.864811] NFS: Registering the id_resolver key type
10504 12:33:42.457345 <5>[ 0.870109] Key type id_resolver registered
10505 12:33:42.464194 <5>[ 0.874524] Key type id_legacy registered
10506 12:33:42.470814 <6>[ 0.878808] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10507 12:33:42.477469 <6>[ 0.885730] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10508 12:33:42.483911 <6>[ 0.893444] 9p: Installing v9fs 9p2000 file system support
10509 12:33:42.520346 <5>[ 0.931064] Key type asymmetric registered
10510 12:33:42.523636 <5>[ 0.935393] Asymmetric key parser 'x509' registered
10511 12:33:42.533157 <6>[ 0.940531] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10512 12:33:42.537128 <6>[ 0.948146] io scheduler mq-deadline registered
10513 12:33:42.540330 <6>[ 0.952922] io scheduler kyber registered
10514 12:33:42.559130 <6>[ 0.970068] EINJ: ACPI disabled.
10515 12:33:42.591791 <4>[ 0.996044] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 12:33:42.601448 <4>[ 1.006655] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 12:33:42.616621 <6>[ 1.027583] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10518 12:33:42.624522 <6>[ 1.035461] printk: console [ttyS0] disabled
10519 12:33:42.652174 <6>[ 1.060103] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10520 12:33:42.659395 <6>[ 1.069576] printk: console [ttyS0] enabled
10521 12:33:42.662621 <6>[ 1.069576] printk: console [ttyS0] enabled
10522 12:33:42.669222 <6>[ 1.078473] printk: bootconsole [mtk8250] disabled
10523 12:33:42.672299 <6>[ 1.078473] printk: bootconsole [mtk8250] disabled
10524 12:33:42.679208 <6>[ 1.089537] SuperH (H)SCI(F) driver initialized
10525 12:33:42.682359 <6>[ 1.094833] msm_serial: driver initialized
10526 12:33:42.696490 <6>[ 1.103792] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10527 12:33:42.706501 <6>[ 1.112338] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10528 12:33:42.713035 <6>[ 1.120880] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10529 12:33:42.723041 <6>[ 1.129507] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10530 12:33:42.729410 <6>[ 1.138214] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10531 12:33:42.739687 <6>[ 1.146927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10532 12:33:42.749218 <6>[ 1.155468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10533 12:33:42.756284 <6>[ 1.164263] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10534 12:33:42.766026 <6>[ 1.172808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10535 12:33:42.777812 <6>[ 1.188487] loop: module loaded
10536 12:33:42.784224 <6>[ 1.194487] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10537 12:33:42.806957 <4>[ 1.217875] mtk-pmic-keys: Failed to locate of_node [id: -1]
10538 12:33:42.814033 <6>[ 1.224608] megasas: 07.719.03.00-rc1
10539 12:33:42.823185 <6>[ 1.234285] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10540 12:33:42.831632 <6>[ 1.242117] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10541 12:33:42.848291 <6>[ 1.258883] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10542 12:33:42.905314 <6>[ 1.309279] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10543 12:33:43.088438 <6>[ 1.499307] Freeing initrd memory: 17224K
10544 12:33:43.098702 <6>[ 1.509429] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10545 12:33:43.109714 <6>[ 1.520327] tun: Universal TUN/TAP device driver, 1.6
10546 12:33:43.112911 <6>[ 1.526412] thunder_xcv, ver 1.0
10547 12:33:43.116512 <6>[ 1.529914] thunder_bgx, ver 1.0
10548 12:33:43.119442 <6>[ 1.533410] nicpf, ver 1.0
10549 12:33:43.130500 <6>[ 1.537441] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10550 12:33:43.133588 <6>[ 1.544917] hns3: Copyright (c) 2017 Huawei Corporation.
10551 12:33:43.137063 <6>[ 1.550503] hclge is initializing
10552 12:33:43.143694 <6>[ 1.554081] e1000: Intel(R) PRO/1000 Network Driver
10553 12:33:43.149731 <6>[ 1.559211] e1000: Copyright (c) 1999-2006 Intel Corporation.
10554 12:33:43.153707 <6>[ 1.565223] e1000e: Intel(R) PRO/1000 Network Driver
10555 12:33:43.159997 <6>[ 1.570438] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10556 12:33:43.166375 <6>[ 1.576625] igb: Intel(R) Gigabit Ethernet Network Driver
10557 12:33:43.173683 <6>[ 1.582275] igb: Copyright (c) 2007-2014 Intel Corporation.
10558 12:33:43.180077 <6>[ 1.588112] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10559 12:33:43.186598 <6>[ 1.594629] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10560 12:33:43.189856 <6>[ 1.601091] sky2: driver version 1.30
10561 12:33:43.196362 <6>[ 1.606135] VFIO - User Level meta-driver version: 0.3
10562 12:33:43.203628 <6>[ 1.614435] usbcore: registered new interface driver usb-storage
10563 12:33:43.210576 <6>[ 1.620879] usbcore: registered new device driver onboard-usb-hub
10564 12:33:43.219670 <6>[ 1.630021] mt6397-rtc mt6359-rtc: registered as rtc0
10565 12:33:43.229071 <6>[ 1.635489] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:33:31 UTC (1686054811)
10566 12:33:43.231964 <6>[ 1.645074] i2c_dev: i2c /dev entries driver
10567 12:33:43.249065 <6>[ 1.656927] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10568 12:33:43.256152 <6>[ 1.667161] sdhci: Secure Digital Host Controller Interface driver
10569 12:33:43.262901 <6>[ 1.673599] sdhci: Copyright(c) Pierre Ossman
10570 12:33:43.269426 <6>[ 1.679028] Synopsys Designware Multimedia Card Interface Driver
10571 12:33:43.272730 <6>[ 1.685636] mmc0: CQHCI version 5.10
10572 12:33:43.279435 <6>[ 1.686216] sdhci-pltfm: SDHCI platform and OF driver helper
10573 12:33:43.286377 <6>[ 1.697628] ledtrig-cpu: registered to indicate activity on CPUs
10574 12:33:43.296804 <6>[ 1.704793] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10575 12:33:43.300116 <6>[ 1.712192] usbcore: registered new interface driver usbhid
10576 12:33:43.307319 <6>[ 1.718024] usbhid: USB HID core driver
10577 12:33:43.313753 <6>[ 1.722278] spi_master spi0: will run message pump with realtime priority
10578 12:33:43.357114 <6>[ 1.761134] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10579 12:33:43.372624 <6>[ 1.777090] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10580 12:33:43.380101 <6>[ 1.790644] mmc0: Command Queue Engine enabled
10581 12:33:43.386681 <6>[ 1.795391] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10582 12:33:43.393626 <6>[ 1.802303] cros-ec-spi spi0.0: Chrome EC device registered
10583 12:33:43.396578 <6>[ 1.802644] mmcblk0: mmc0:0001 DA4128 116 GiB
10584 12:33:43.405931 <6>[ 1.817303] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10585 12:33:43.413672 <6>[ 1.824458] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10586 12:33:43.420164 <6>[ 1.830354] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10587 12:33:43.426581 <6>[ 1.836225] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10588 12:33:43.445085 <6>[ 1.852929] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10589 12:33:43.453689 <6>[ 1.864390] NET: Registered PF_PACKET protocol family
10590 12:33:43.456762 <6>[ 1.869861] 9pnet: Installing 9P2000 support
10591 12:33:43.463554 <5>[ 1.874459] Key type dns_resolver registered
10592 12:33:43.466478 <6>[ 1.879561] registered taskstats version 1
10593 12:33:43.473355 <5>[ 1.883966] Loading compiled-in X.509 certificates
10594 12:33:43.507437 <4>[ 1.911891] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 12:33:43.517273 <4>[ 1.922590] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10596 12:33:43.527628 <3>[ 1.935216] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10597 12:33:43.539770 <6>[ 1.950594] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10598 12:33:43.546060 <6>[ 1.957346] xhci-mtk 11200000.usb: xHCI Host Controller
10599 12:33:43.552701 <6>[ 1.962865] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10600 12:33:43.562875 <6>[ 1.970729] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10601 12:33:43.569744 <6>[ 1.980151] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10602 12:33:43.576768 <6>[ 1.986345] xhci-mtk 11200000.usb: xHCI Host Controller
10603 12:33:43.583091 <6>[ 1.991844] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10604 12:33:43.589765 <6>[ 1.999502] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10605 12:33:43.596302 <6>[ 2.007405] hub 1-0:1.0: USB hub found
10606 12:33:43.599494 <6>[ 2.011439] hub 1-0:1.0: 1 port detected
10607 12:33:43.606417 <6>[ 2.015789] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10608 12:33:43.613478 <6>[ 2.024615] hub 2-0:1.0: USB hub found
10609 12:33:43.616700 <6>[ 2.028650] hub 2-0:1.0: 1 port detected
10610 12:33:43.625255 <6>[ 2.035997] mtk-msdc 11f70000.mmc: Got CD GPIO
10611 12:33:43.641657 <6>[ 2.049332] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10612 12:33:43.648136 <6>[ 2.057375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10613 12:33:43.658224 <4>[ 2.065351] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10614 12:33:43.667979 <6>[ 2.075024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10615 12:33:43.674527 <6>[ 2.083106] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10616 12:33:43.681255 <6>[ 2.091139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10617 12:33:43.691304 <6>[ 2.099056] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10618 12:33:43.698282 <6>[ 2.106877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10619 12:33:43.708089 <6>[ 2.114702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10620 12:33:43.718395 <6>[ 2.125409] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10621 12:33:43.724916 <6>[ 2.133778] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10622 12:33:43.734757 <6>[ 2.142132] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10623 12:33:43.741620 <6>[ 2.150477] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10624 12:33:43.751463 <6>[ 2.158823] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10625 12:33:43.758484 <6>[ 2.167166] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10626 12:33:43.768254 <6>[ 2.175510] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10627 12:33:43.774997 <6>[ 2.183852] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10628 12:33:43.784828 <6>[ 2.192196] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10629 12:33:43.791884 <6>[ 2.200539] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10630 12:33:43.801721 <6>[ 2.208882] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10631 12:33:43.808101 <6>[ 2.217226] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10632 12:33:43.818477 <6>[ 2.225569] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10633 12:33:43.824674 <6>[ 2.233912] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10634 12:33:43.835039 <6>[ 2.242257] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10635 12:33:43.841479 <6>[ 2.251186] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10636 12:33:43.848395 <6>[ 2.258652] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10637 12:33:43.855118 <6>[ 2.265721] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10638 12:33:43.862240 <6>[ 2.272865] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10639 12:33:43.872723 <6>[ 2.280201] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10640 12:33:43.878961 <6>[ 2.287118] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10641 12:33:43.889023 <6>[ 2.296265] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10642 12:33:43.899047 <6>[ 2.305392] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10643 12:33:43.908858 <6>[ 2.314694] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10644 12:33:43.919056 <6>[ 2.324169] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10645 12:33:43.925580 <6>[ 2.333644] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10646 12:33:43.935321 <6>[ 2.342771] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10647 12:33:43.945565 <6>[ 2.352246] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10648 12:33:43.955335 <6>[ 2.361373] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10649 12:33:43.965337 <6>[ 2.370675] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10650 12:33:43.975174 <6>[ 2.380841] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10651 12:33:43.985026 <6>[ 2.392074] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10652 12:33:43.991526 <6>[ 2.401889] Trying to probe devices needed for running init ...
10653 12:33:44.010948 <6>[ 2.419026] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10654 12:33:44.038724 <6>[ 2.449578] hub 2-1:1.0: USB hub found
10655 12:33:44.041997 <6>[ 2.453982] hub 2-1:1.0: 3 ports detected
10656 12:33:44.163688 <6>[ 2.571046] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10657 12:33:44.317551 <6>[ 2.728649] hub 1-1:1.0: USB hub found
10658 12:33:44.320512 <6>[ 2.733133] hub 1-1:1.0: 4 ports detected
10659 12:33:44.399493 <6>[ 2.807260] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10660 12:33:44.642531 <6>[ 3.050976] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10661 12:33:44.774153 <6>[ 3.185536] hub 1-1.4:1.0: USB hub found
10662 12:33:44.777395 <6>[ 3.190078] hub 1-1.4:1.0: 2 ports detected
10663 12:33:45.075290 <6>[ 3.482975] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10664 12:33:45.259105 <6>[ 3.666977] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10665 12:33:56.283940 <6>[ 14.699632] ALSA device list:
10666 12:33:56.290531 <6>[ 14.702883] No soundcards found.
10667 12:33:56.302596 <6>[ 14.715294] Freeing unused kernel memory: 8384K
10668 12:33:56.306280 <6>[ 14.720222] Run /init as init process
10669 12:33:56.317307 Loading, please wait...
10670 12:33:56.336068 Starting version 247.3-7+deb11u2
10671 12:33:56.650977 <6>[ 15.060518] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10672 12:33:56.663136 <6>[ 15.075534] remoteproc remoteproc0: scp is available
10673 12:33:56.672880 <4>[ 15.081229] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10674 12:33:56.679876 <6>[ 15.091098] remoteproc remoteproc0: powering up scp
10675 12:33:56.689487 <4>[ 15.096294] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10676 12:33:56.696340 <3>[ 15.096903] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 12:33:56.702483 <3>[ 15.107486] remoteproc remoteproc0: request_firmware failed: -2
10678 12:33:56.709392 <3>[ 15.114291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 12:33:56.719624 <6>[ 15.122297] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10680 12:33:56.725935 <6>[ 15.124058] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10681 12:33:56.736222 <3>[ 15.128585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 12:33:56.742316 <3>[ 15.128691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 12:33:56.745918 <6>[ 15.129125] mc: Linux media interface: v0.10
10684 12:33:56.756200 <6>[ 15.136260] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10685 12:33:56.762225 <3>[ 15.143845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 12:33:56.772641 <3>[ 15.143856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:33:56.779356 <3>[ 15.143867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 12:33:56.788987 <3>[ 15.143874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:33:56.796061 <3>[ 15.143931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 12:33:56.802808 <6>[ 15.144679] videodev: Linux video capture interface: v2.00
10691 12:33:56.809879 <4>[ 15.145249] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10692 12:33:56.816155 <4>[ 15.145372] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10693 12:33:56.823202 <6>[ 15.147070] usbcore: registered new interface driver r8152
10694 12:33:56.830286 <6>[ 15.152687] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10695 12:33:56.839939 <3>[ 15.160158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 12:33:56.846688 <3>[ 15.160170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 12:33:56.857113 <3>[ 15.160181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 12:33:56.863728 <3>[ 15.160257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 12:33:56.873539 <4>[ 15.184730] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10700 12:33:56.876631 <4>[ 15.184730] Fallback method does not support PEC.
10701 12:33:56.886966 <3>[ 15.189622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 12:33:56.893292 <3>[ 15.214423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 12:33:56.903091 <3>[ 15.219659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 12:33:56.909800 <3>[ 15.219671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 12:33:56.919800 <3>[ 15.219680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 12:33:56.926585 <3>[ 15.248747] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 12:33:56.932927 <6>[ 15.257022] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10708 12:33:56.943001 <3>[ 15.258410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 12:33:56.952977 <6>[ 15.273579] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10710 12:33:56.959822 <6>[ 15.296676] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10711 12:33:56.969311 <6>[ 15.304684] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10712 12:33:56.975921 <4>[ 15.308722] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10713 12:33:56.986111 <4>[ 15.308732] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10714 12:33:56.992793 <6>[ 15.311747] pci_bus 0000:00: root bus resource [bus 00-ff]
10715 12:33:56.999193 <6>[ 15.320108] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10716 12:33:57.009448 <6>[ 15.327846] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10717 12:33:57.016320 <6>[ 15.327853] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10718 12:33:57.022538 <6>[ 15.360916] Bluetooth: Core ver 2.22
10719 12:33:57.025996 <6>[ 15.361023] usbcore: registered new interface driver cdc_ether
10720 12:33:57.032293 <6>[ 15.369320] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10721 12:33:57.039305 <6>[ 15.369486] r8152 2-1.3:1.0 eth0: v1.12.13
10722 12:33:57.045875 <6>[ 15.369708] usbcore: registered new interface driver r8153_ecm
10723 12:33:57.049155 <6>[ 15.376279] NET: Registered PF_BLUETOOTH protocol family
10724 12:33:57.055457 <6>[ 15.378362] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10725 12:33:57.062098 <6>[ 15.386292] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10726 12:33:57.068757 <6>[ 15.387269] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10727 12:33:57.082198 <6>[ 15.388769] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10728 12:33:57.088614 <6>[ 15.388917] usbcore: registered new interface driver uvcvideo
10729 12:33:57.095309 <6>[ 15.395297] Bluetooth: HCI device and connection manager initialized
10730 12:33:57.101760 <6>[ 15.395322] Bluetooth: HCI socket layer initialized
10731 12:33:57.105604 <6>[ 15.403487] pci 0000:00:00.0: supports D1 D2
10732 12:33:57.111946 <6>[ 15.409252] Bluetooth: L2CAP socket layer initialized
10733 12:33:57.118394 <6>[ 15.418176] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10734 12:33:57.125373 <6>[ 15.420217] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10735 12:33:57.131506 <6>[ 15.420446] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10736 12:33:57.138008 <6>[ 15.425339] Bluetooth: SCO socket layer initialized
10737 12:33:57.144857 <6>[ 15.435351] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10738 12:33:57.148111 <6>[ 15.474155] usbcore: registered new interface driver btusb
10739 12:33:57.158322 <4>[ 15.474861] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10740 12:33:57.164958 <3>[ 15.474870] Bluetooth: hci0: Failed to load firmware file (-2)
10741 12:33:57.171098 <3>[ 15.474873] Bluetooth: hci0: Failed to set up firmware (-2)
10742 12:33:57.180891 <4>[ 15.474876] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10743 12:33:57.187755 <6>[ 15.481004] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10744 12:33:57.197599 <6>[ 15.607078] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10745 12:33:57.204532 <6>[ 15.614576] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10746 12:33:57.207679 <6>[ 15.622168] pci 0000:01:00.0: supports D1 D2
10747 12:33:57.217328 <6>[ 15.626692] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 12:33:57.233720 <6>[ 15.642775] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10749 12:33:57.240266 <6>[ 15.649680] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10750 12:33:57.246907 <6>[ 15.657774] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10751 12:33:57.256938 <6>[ 15.665781] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10752 12:33:57.263371 <6>[ 15.673790] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10753 12:33:57.273335 <6>[ 15.681797] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10754 12:33:57.276279 <6>[ 15.689804] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 12:33:57.286632 <6>[ 15.695026] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 12:33:57.292993 <6>[ 15.703153] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 12:33:57.299646 <6>[ 15.710356] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10758 12:33:57.306326 <6>[ 15.717101] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10759 12:33:57.322888 <5>[ 15.732617] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10760 12:33:57.342544 <5>[ 15.751795] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10761 12:33:57.349252 <4>[ 15.758714] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 12:33:57.355944 <6>[ 15.767605] cfg80211: failed to load regulatory.db
10763 12:33:57.399059 <6>[ 15.808017] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 12:33:57.405521 <6>[ 15.815548] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 12:33:57.429688 <6>[ 15.842221] mt7921e 0000:01:00.0: ASIC revision: 79610010
10766 12:33:57.536516 <4>[ 15.942615] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 12:33:57.554386 Begin: Loading essential drivers ... done.
10768 12:33:57.557681 Begin: Running /scripts/init-premount ... done.
10769 12:33:57.563773 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10770 12:33:57.573806 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10771 12:33:57.577005 Device /sys/class/net/enx00e04c787aaa found
10772 12:33:57.577082 done.
10773 12:33:57.609882 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10774 12:33:57.654899 <4>[ 16.061117] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 12:33:57.774713 <4>[ 16.180763] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 12:33:57.890811 <4>[ 16.296804] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 12:33:58.006377 <4>[ 16.412652] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 12:33:58.122525 <4>[ 16.528637] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 12:33:58.238411 <4>[ 16.644544] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:33:58.354321 <4>[ 16.760474] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 12:33:58.470101 <4>[ 16.876443] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 12:33:58.586511 <4>[ 16.992521] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 12:33:58.607817 <6>[ 17.020733] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10784 12:33:58.693085 <3>[ 17.106201] mt7921e 0000:01:00.0: hardware init failed
10785 12:33:58.722735 IP-Config: no response after 2 secs - giving up
10786 12:33:58.761116 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10787 12:33:58.764782 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10788 12:33:58.771509 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10789 12:33:58.778153 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10790 12:33:58.784483 host : mt8192-asurada-spherion-r0-cbg-0
10791 12:33:58.791657 domain : lava-rack
10792 12:33:58.794720 rootserver: 192.168.201.1 rootpath:
10793 12:33:58.798331 filename :
10794 12:33:58.822149 done.
10795 12:33:58.825331 Begin: Running /scripts/nfs-bottom ... done.
10796 12:33:58.844456 Begin: Running /scripts/init-bottom ... done.
10797 12:33:59.913142 <6>[ 18.325863] NET: Registered PF_INET6 protocol family
10798 12:33:59.920111 <6>[ 18.332845] Segment Routing with IPv6
10799 12:33:59.923244 <6>[ 18.336839] In-situ OAM (IOAM) with IPv6
10800 12:34:00.025613 <30>[ 18.418813] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10801 12:34:00.028732 <30>[ 18.442646] systemd[1]: Detected architecture arm64.
10802 12:34:00.046767
10803 12:34:00.050052 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10804 12:34:00.050156
10805 12:34:00.067370 <30>[ 18.480546] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10806 12:34:00.533100 <30>[ 18.943055] systemd[1]: Queued start job for default target Graphical Interface.
10807 12:34:00.555075 <30>[ 18.968109] systemd[1]: Created slice system-getty.slice.
10808 12:34:00.561247 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10809 12:34:00.578456 <30>[ 18.991635] systemd[1]: Created slice system-modprobe.slice.
10810 12:34:00.585365 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10811 12:34:00.602352 <30>[ 19.015550] systemd[1]: Created slice system-serial\x2dgetty.slice.
10812 12:34:00.612367 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10813 12:34:00.626931 <30>[ 19.040058] systemd[1]: Created slice User and Session Slice.
10814 12:34:00.633529 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10815 12:34:00.653847 <30>[ 19.063563] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10816 12:34:00.663369 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10817 12:34:00.681549 <30>[ 19.091539] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10818 12:34:00.688481 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10819 12:34:00.708814 <30>[ 19.115144] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10820 12:34:00.715515 <30>[ 19.127177] systemd[1]: Reached target Local Encrypted Volumes.
10821 12:34:00.721901 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10822 12:34:00.738367 <30>[ 19.151371] systemd[1]: Reached target Paths.
10823 12:34:00.742008 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10824 12:34:00.758120 <30>[ 19.171054] systemd[1]: Reached target Remote File Systems.
10825 12:34:00.765086 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10826 12:34:00.778244 <30>[ 19.191037] systemd[1]: Reached target Slices.
10827 12:34:00.781482 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10828 12:34:00.797944 <30>[ 19.211061] systemd[1]: Reached target Swap.
10829 12:34:00.801042 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10830 12:34:00.821707 <30>[ 19.231342] systemd[1]: Listening on initctl Compatibility Named Pipe.
10831 12:34:00.828321 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10832 12:34:00.834789 <30>[ 19.246545] systemd[1]: Listening on Journal Audit Socket.
10833 12:34:00.841289 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10834 12:34:00.854937 <30>[ 19.267870] systemd[1]: Listening on Journal Socket (/dev/log).
10835 12:34:00.861718 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10836 12:34:00.878797 <30>[ 19.291744] systemd[1]: Listening on Journal Socket.
10837 12:34:00.885146 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10838 12:34:00.899058 <30>[ 19.312151] systemd[1]: Listening on Network Service Netlink Socket.
10839 12:34:00.909387 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10840 12:34:00.923915 <30>[ 19.337002] systemd[1]: Listening on udev Control Socket.
10841 12:34:00.930674 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10842 12:34:00.946278 <30>[ 19.359293] systemd[1]: Listening on udev Kernel Socket.
10843 12:34:00.952602 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10844 12:34:00.982209 <30>[ 19.395288] systemd[1]: Mounting Huge Pages File System...
10845 12:34:00.988899 Mounting [0;1;39mHuge Pages File System[0m...
10846 12:34:01.004747 <30>[ 19.417600] systemd[1]: Mounting POSIX Message Queue File System...
10847 12:34:01.011085 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10848 12:34:01.028106 <30>[ 19.441405] systemd[1]: Mounting Kernel Debug File System...
10849 12:34:01.035129 Mounting [0;1;39mKernel Debug File System[0m...
10850 12:34:01.053584 <30>[ 19.463321] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10851 12:34:01.097700 <30>[ 19.507418] systemd[1]: Starting Create list of static device nodes for the current kernel...
10852 12:34:01.103929 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10853 12:34:01.124248 <30>[ 19.537642] systemd[1]: Starting Load Kernel Module configfs...
10854 12:34:01.131345 Starting [0;1;39mLoad Kernel Module configfs[0m...
10855 12:34:01.148669 <30>[ 19.561587] systemd[1]: Starting Load Kernel Module drm...
10856 12:34:01.154747 Starting [0;1;39mLoad Kernel Module drm[0m...
10857 12:34:01.172138 <30>[ 19.585501] systemd[1]: Starting Load Kernel Module fuse...
10858 12:34:01.179110 Starting [0;1;39mLoad Kernel Module fuse[0m...
10859 12:34:01.207233 <6>[ 19.620059] fuse: init (API version 7.37)
10860 12:34:01.216921 <30>[ 19.620662] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10861 12:34:01.225868 <30>[ 19.638597] systemd[1]: Starting Journal Service...
10862 12:34:01.229078 Starting [0;1;39mJournal Service[0m...
10863 12:34:01.253132 <30>[ 19.665805] systemd[1]: Starting Load Kernel Modules...
10864 12:34:01.259169 Starting [0;1;39mLoad Kernel Modules[0m...
10865 12:34:01.281027 <30>[ 19.690753] systemd[1]: Starting Remount Root and Kernel File Systems...
10866 12:34:01.287193 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10867 12:34:01.305572 <30>[ 19.718521] systemd[1]: Starting Coldplug All udev Devices...
10868 12:34:01.312158 Starting [0;1;39mColdplug All udev Devices[0m...
10869 12:34:01.328675 <30>[ 19.741967] systemd[1]: Mounted Huge Pages File System.
10870 12:34:01.335225 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10871 12:34:01.350465 <30>[ 19.763613] systemd[1]: Mounted POSIX Message Queue File System.
10872 12:34:01.357136 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10873 12:34:01.376986 <3>[ 19.786875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 12:34:01.383641 <30>[ 19.787322] systemd[1]: Mounted Kernel Debug File System.
10875 12:34:01.390733 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10876 12:34:01.405775 <3>[ 19.815603] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 12:34:01.416036 <30>[ 19.825659] systemd[1]: Finished Create list of static device nodes for the current kernel.
10878 12:34:01.425966 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10879 12:34:01.439228 <30>[ 19.851990] systemd[1]: modprobe@configfs.service: Succeeded.
10880 12:34:01.446254 <30>[ 19.858673] systemd[1]: Finished Load Kernel Module configfs.
10881 12:34:01.455937 <3>[ 19.862451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 12:34:01.462476 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10883 12:34:01.478587 <30>[ 19.891960] systemd[1]: modprobe@drm.service: Succeeded.
10884 12:34:01.488613 <3>[ 19.897006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 12:34:01.495537 <30>[ 19.898218] systemd[1]: Finished Load Kernel Module drm.
10886 12:34:01.498665 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10887 12:34:01.514676 <30>[ 19.927936] systemd[1]: modprobe@fuse.service: Succeeded.
10888 12:34:01.524412 <3>[ 19.929984] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:34:01.531274 <30>[ 19.934272] systemd[1]: Finished Load Kernel Module fuse.
10890 12:34:01.534454 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10891 12:34:01.551761 <30>[ 19.964288] systemd[1]: Finished Load Kernel Modules.
10892 12:34:01.561354 <3>[ 19.965310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:34:01.567518 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10894 12:34:01.583313 <30>[ 19.996299] systemd[1]: Finished Remount Root and Kernel File Systems.
10895 12:34:01.593096 <3>[ 20.000792] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 12:34:01.600061 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10897 12:34:01.623294 <3>[ 20.032718] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 12:34:01.642051 <30>[ 20.054710] systemd[1]: Mounting FUSE Control File System...
10899 12:34:01.649247 Mounting [0;1;39mFUSE Control File System[0m...
10900 12:34:01.665212 <30>[ 20.077894] systemd[1]: Mounting Kernel Configuration File System...
10901 12:34:01.671542 Mounting [0;1;39mKernel Configuration File System[0m...
10902 12:34:01.696573 <30>[ 20.106409] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10903 12:34:01.706503 <30>[ 20.115409] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10904 12:34:01.714783 <30>[ 20.128286] systemd[1]: Starting Load/Save Random Seed...
10905 12:34:01.721636 Starting [0;1;39mLoad/Save Random Seed[0m...
10906 12:34:01.737643 <30>[ 20.150629] systemd[1]: Starting Apply Kernel Variables...
10907 12:34:01.743767 Starting [0;1;39mApply Kernel Variables[0m...
10908 12:34:01.790962 <30>[ 20.203719] systemd[1]: Starting Create System Users...
10909 12:34:01.797283 Starting [0;1;39mCreate System Users[0m...
10910 12:34:01.816059 <30>[ 20.228832] systemd[1]: Started Journal Service.
10911 12:34:01.822258 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10912 12:34:01.836730 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10913 12:34:01.843752 <4>[ 20.254842] power_supply_show_property: 3 callbacks suppressed
10914 12:34:01.853644 <3>[ 20.254860] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 12:34:01.867086 <4>[ 20.269999] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10916 12:34:01.876765 <3>[ 20.284891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 12:34:01.883922 <3>[ 20.285641] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10918 12:34:01.890052 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10919 12:34:01.905339 <3>[ 20.315047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 12:34:01.915865 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10921 12:34:01.937061 See 'systemctl status systemd-ud<3>[ 20.345273] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:34:01.940227 ev-trigger.service' for details.
10923 12:34:01.955152 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10924 12:34:01.965588 <3>[ 20.374650] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:34:01.971980 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10926 12:34:01.994070 [[0;32m OK [0m] Finished [0;1;39mCreate Sys<3>[ 20.403902] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:34:01.997755 tem Users[0m.
10928 12:34:02.025278 <3>[ 20.434996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 12:34:02.042735 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10930 12:34:02.056460 <3>[ 20.466210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:34:02.065252 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10932 12:34:02.086057 <3>[ 20.496011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 12:34:02.115548 <3>[ 20.525146] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:34:02.121981 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10935 12:34:02.142321 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10936 12:34:02.158692 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10937 12:34:02.168881 <46>[ 20.577530] systemd-journald[292]: Received client request to flush runtime journal.
10938 12:34:02.209912 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10939 12:34:03.538751 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10940 12:34:03.586868 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10941 12:34:03.606123 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10942 12:34:03.633064 Starting [0;1;39mNetwork Service[0m...
10943 12:34:03.938982 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10944 12:34:03.994039 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10945 12:34:04.016749 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10946 12:34:04.192197 <6>[ 22.605685] remoteproc remoteproc0: powering up scp
10947 12:34:04.220486 <4>[ 22.630605] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10948 12:34:04.226854 <3>[ 22.640490] remoteproc remoteproc0: request_firmware failed: -2
10949 12:34:04.237059 <3>[ 22.646673] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10950 12:34:04.345969 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10951 12:34:04.369947 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10952 12:34:04.390327 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10953 12:34:04.452680 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10954 12:34:04.469468 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10955 12:34:04.506250 Starting [0;1;39mNetwork Name Resolution[0m...
10956 12:34:04.528623 Starting [0;1;39mNetwork Time Synchronization[0m...
10957 12:34:04.544525 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10958 12:34:04.567191 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10959 12:34:04.599210 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10960 12:34:04.618165 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10961 12:34:04.757686 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10962 12:34:04.773954 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10963 12:34:04.792872 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 12:34:04.805810 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10965 12:34:04.825570 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10966 12:34:04.974165 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10967 12:34:05.006385 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10968 12:34:05.027058 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10969 12:34:05.051488 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 12:34:05.065471 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 12:34:05.097905 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 12:34:05.110224 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10973 12:34:05.130403 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10974 12:34:05.174657 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10975 12:34:05.207817 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10976 12:34:05.278793 Starting [0;1;39mUser Login Management[0m...
10977 12:34:05.294550 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10978 12:34:05.310802 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10979 12:34:05.329451 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10980 12:34:05.362715 Starting [0;1;39mPermit User Sessions[0m...
10981 12:34:05.488211 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10982 12:34:05.530953 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10983 12:34:05.549104 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10984 12:34:05.566215 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10985 12:34:05.591192 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10986 12:34:05.608870 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10987 12:34:05.627285 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10988 12:34:05.641973 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10989 12:34:05.694491 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10990 12:34:05.759482 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10991 12:34:05.823958
10992 12:34:05.824088
10993 12:34:05.827131 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10994 12:34:05.827239
10995 12:34:05.830291 debian-bullseye-arm64 login: root (automatic login)
10996 12:34:05.830373
10997 12:34:05.830437
10998 12:34:06.131744 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
10999 12:34:06.131897
11000 12:34:06.138030 The programs included with the Debian GNU/Linux system are free software;
11001 12:34:06.144735 the exact distribution terms for each program are described in the
11002 12:34:06.148274 individual files in /usr/share/doc/*/copyright.
11003 12:34:06.148356
11004 12:34:06.154431 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11005 12:34:06.154514 permitted by applicable law.
11006 12:34:06.872364 Matched prompt #10: / #
11008 12:34:06.872654 Setting prompt string to ['/ #']
11009 12:34:06.872748 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11011 12:34:06.872950 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11012 12:34:06.873035 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11013 12:34:06.873104 Setting prompt string to ['/ #']
11014 12:34:06.873164 Forcing a shell prompt, looking for ['/ #']
11016 12:34:06.923411 / #
11017 12:34:06.923529 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11018 12:34:06.923639 Waiting using forced prompt support (timeout 00:02:30)
11019 12:34:06.928173
11020 12:34:06.928441 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11021 12:34:06.928536 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11023 12:34:07.028892 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0'
11024 12:34:07.033762 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605812/extract-nfsrootfs-idcg0eg0'
11026 12:34:07.134294 / # export NFS_SERVER_IP='192.168.201.1'
11027 12:34:07.139834 export NFS_SERVER_IP='192.168.201.1'
11028 12:34:07.140118 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 12:34:07.140217 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11030 12:34:07.140313 end: 2 depthcharge-action (duration 00:01:22) [common]
11031 12:34:07.140402 start: 3 lava-test-retry (timeout 00:07:54) [common]
11032 12:34:07.140488 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
11033 12:34:07.140562 Using namespace: common
11035 12:34:07.240892 / # #
11036 12:34:07.241027 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11037 12:34:07.246063 #
11038 12:34:07.246325 Using /lava-10605812
11040 12:34:07.346666 / # export SHELL=/bin/bash
11041 12:34:07.351947 export SHELL=/bin/bash
11043 12:34:07.452473 / # . /lava-10605812/environment
11044 12:34:07.457352 . /lava-10605812/environment
11046 12:34:07.562646 / # /lava-10605812/bin/lava-test-runner /lava-10605812/0
11047 12:34:07.563280 Test shell timeout: 10s (minimum of the action and connection timeout)
11048 12:34:07.569238 /lava-10605812/bin/lava-test-runner /lava-10605812/0
11049 12:34:07.782610 + export TESTRUN_ID=0_timesync-off
11050 12:34:07.785792 + TESTRUN_ID=0_timesync-off
11051 12:34:07.788914 + cd /lava-10605812/0/tests/0_timesync-off
11052 12:34:07.792692 ++ cat uuid
11053 12:34:07.792790 + UUID=10605812_1.6.2.3.1
11054 12:34:07.795788 + set +x
11055 12:34:07.798898 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605812_1.6.2.3.1>
11056 12:34:07.799172 Received signal: <STARTRUN> 0_timesync-off 10605812_1.6.2.3.1
11057 12:34:07.799246 Starting test lava.0_timesync-off (10605812_1.6.2.3.1)
11058 12:34:07.799342 Skipping test definition patterns.
11059 12:34:07.802760 + systemctl stop systemd-timesyncd
11060 12:34:07.821808 + set +x
11061 12:34:07.825579 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605812_1.6.2.3.1>
11062 12:34:07.825833 Received signal: <ENDRUN> 0_timesync-off 10605812_1.6.2.3.1
11063 12:34:07.825915 Ending use of test pattern.
11064 12:34:07.825976 Ending test lava.0_timesync-off (10605812_1.6.2.3.1), duration 0.03
11066 12:34:07.867128 + export TESTRUN_ID=1_kselftest-tpm2
11067 12:34:07.869991 + TESTRUN_ID=1_kselftest-tpm2
11068 12:34:07.876920 + cd /lava-10605812/0/tests/1_kselftest-tpm2
11069 12:34:07.877032 ++ cat uuid
11070 12:34:07.880033 + UUID=10605812_1.6.2.3.5
11071 12:34:07.880129 + set +x
11072 12:34:07.883156 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10605812_1.6.2.3.5>
11073 12:34:07.883412 Received signal: <STARTRUN> 1_kselftest-tpm2 10605812_1.6.2.3.5
11074 12:34:07.883519 Starting test lava.1_kselftest-tpm2 (10605812_1.6.2.3.5)
11075 12:34:07.883599 Skipping test definition patterns.
11076 12:34:07.887007 + cd ./automated/linux/kselftest/
11077 12:34:07.913003 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11078 12:34:07.923474 INFO: install_deps skipped
11079 12:34:08.022094 --2023-06-06 12:33:56-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11080 12:34:08.040696 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11081 12:34:08.188530 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11082 12:34:08.336484 HTTP request sent, awaiting response... 200 OK
11083 12:34:08.339657 Length: 2699740 (2.6M) [application/octet-stream]
11084 12:34:08.342752 Saving to: 'kselftest.tar.xz'
11085 12:34:08.342835
11086 12:34:08.342902
11087 12:34:08.631100 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11088 12:34:08.925938 kselftest.tar.xz 1%[ ] 47.81K 165KB/s
11089 12:34:09.271864 kselftest.tar.xz 8%[> ] 217.50K 374KB/s
11090 12:34:09.580354 kselftest.tar.xz 31%[=====> ] 828.37K 897KB/s
11091 12:34:09.684410 kselftest.tar.xz 73%[=============> ] 1.89M 1.53MB/s
11092 12:34:09.690573 kselftest.tar.xz 100%[===================>] 2.57M 1.93MB/s in 1.3s
11093 12:34:09.690658
11094 12:34:09.923651 2023-06-06 12:33:58 (1.93 MB/s) - 'kselftest.tar.xz' saved [2699740/2699740]
11095 12:34:09.923804
11096 12:34:14.327505 skiplist:
11097 12:34:14.330725 ========================================
11098 12:34:14.333754 ========================================
11099 12:34:14.370136 tpm2:test_smoke.sh
11100 12:34:14.373119 tpm2:test_space.sh
11101 12:34:14.384180 ============== Tests to run ===============
11102 12:34:14.384263 tpm2:test_smoke.sh
11103 12:34:14.387828 tpm2:test_space.sh
11104 12:34:14.391088 ===========End Tests to run ===============
11105 12:34:14.476217 <12>[ 32.890359] kselftest: Running tests in tpm2
11106 12:34:14.485224 TAP version 13
11107 12:34:14.497075 1..2
11108 12:34:14.525429 # selftests: tpm2: test_smoke.sh
11109 12:34:15.676320 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11110 12:34:15.679369 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11111 12:34:15.686245 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11112 12:34:15.689475 # Traceback (most recent call last):
11113 12:34:15.699256 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11114 12:34:15.699369 # if self.tpm:
11115 12:34:15.706259 # AttributeError: 'Client' object has no attribute 'tpm'
11116 12:34:15.713264 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11117 12:34:15.716104 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11118 12:34:15.719512 # Traceback (most recent call last):
11119 12:34:15.729500 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11120 12:34:15.733091 # if self.tpm:
11121 12:34:15.736485 # AttributeError: 'Client' object has no attribute 'tpm'
11122 12:34:15.743316 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11123 12:34:15.749877 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11124 12:34:15.752938 # Traceback (most recent call last):
11125 12:34:15.762983 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11126 12:34:15.763465 # if self.tpm:
11127 12:34:15.769851 # AttributeError: 'Client' object has no attribute 'tpm'
11128 12:34:15.773158 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11129 12:34:15.779568 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11130 12:34:15.783278 # Traceback (most recent call last):
11131 12:34:15.792978 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11132 12:34:15.796722 # if self.tpm:
11133 12:34:15.799672 # AttributeError: 'Client' object has no attribute 'tpm'
11134 12:34:15.803025 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11135 12:34:15.809574 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11136 12:34:15.813389 # Traceback (most recent call last):
11137 12:34:15.823538 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11138 12:34:15.826494 # if self.tpm:
11139 12:34:15.829789 # AttributeError: 'Client' object has no attribute 'tpm'
11140 12:34:15.836217 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11141 12:34:15.842698 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11142 12:34:15.846292 # Traceback (most recent call last):
11143 12:34:15.853151 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11144 12:34:15.856679 # if self.tpm:
11145 12:34:15.859701 # AttributeError: 'Client' object has no attribute 'tpm'
11146 12:34:15.866828 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11147 12:34:15.872910 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11148 12:34:15.876520 # Traceback (most recent call last):
11149 12:34:15.886202 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11150 12:34:15.886706 # if self.tpm:
11151 12:34:15.893297 # AttributeError: 'Client' object has no attribute 'tpm'
11152 12:34:15.900180 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11153 12:34:15.903268 # Exception ignored in: <function Client.__del__ at 0xffffa3ea6d30>
11154 12:34:15.906598 # Traceback (most recent call last):
11155 12:34:15.916518 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11156 12:34:15.919588 # if self.tpm:
11157 12:34:15.922823 # AttributeError: 'Client' object has no attribute 'tpm'
11158 12:34:15.926582 #
11159 12:34:15.929617 # ======================================================================
11160 12:34:15.936304 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11161 12:34:15.943263 # ----------------------------------------------------------------------
11162 12:34:15.947018 # Traceback (most recent call last):
11163 12:34:15.956284 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11164 12:34:15.959869 # self.root_key = self.client.create_root_key()
11165 12:34:15.970205 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11166 12:34:15.976714 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11167 12:34:15.986304 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11168 12:34:15.989818 # raise ProtocolError(cc, rc)
11169 12:34:15.996570 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11170 12:34:15.996997 #
11171 12:34:16.003127 # ======================================================================
11172 12:34:16.006741 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11173 12:34:16.012903 # ----------------------------------------------------------------------
11174 12:34:16.016599 # Traceback (most recent call last):
11175 12:34:16.026579 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11176 12:34:16.029808 # self.client = tpm2.Client()
11177 12:34:16.039852 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11178 12:34:16.046315 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11179 12:34:16.049834 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11180 12:34:16.050352 #
11181 12:34:16.056646 # ======================================================================
11182 12:34:16.062748 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11183 12:34:16.069948 # ----------------------------------------------------------------------
11184 12:34:16.073124 # Traceback (most recent call last):
11185 12:34:16.082862 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11186 12:34:16.083571 # self.client = tpm2.Client()
11187 12:34:16.092713 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11188 12:34:16.099809 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11189 12:34:16.106387 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11190 12:34:16.106864 #
11191 12:34:16.112598 # ======================================================================
11192 12:34:16.115779 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11193 12:34:16.122455 # ----------------------------------------------------------------------
11194 12:34:16.126174 # Traceback (most recent call last):
11195 12:34:16.136232 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11196 12:34:16.139264 # self.client = tpm2.Client()
11197 12:34:16.149156 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11198 12:34:16.152908 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11199 12:34:16.159317 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11200 12:34:16.159929 #
11201 12:34:16.166047 # ======================================================================
11202 12:34:16.172397 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11203 12:34:16.175670 # ----------------------------------------------------------------------
11204 12:34:16.179422 # Traceback (most recent call last):
11205 12:34:16.192692 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11206 12:34:16.193275 # self.client = tpm2.Client()
11207 12:34:16.202157 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11208 12:34:16.209077 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11209 12:34:16.212250 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11210 12:34:16.215512 #
11211 12:34:16.222173 # ======================================================================
11212 12:34:16.226186 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11213 12:34:16.232603 # ----------------------------------------------------------------------
11214 12:34:16.235685 # Traceback (most recent call last):
11215 12:34:16.245855 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11216 12:34:16.248786 # self.client = tpm2.Client()
11217 12:34:16.258858 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11218 12:34:16.262062 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11219 12:34:16.269564 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11220 12:34:16.270124 #
11221 12:34:16.274794 # ======================================================================
11222 12:34:16.278176 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11223 12:34:16.285186 # ----------------------------------------------------------------------
11224 12:34:16.289037 # Traceback (most recent call last):
11225 12:34:16.301035 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11226 12:34:16.301624 # self.client = tpm2.Client()
11227 12:34:16.314190 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11228 12:34:16.318094 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11229 12:34:16.322289 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11230 12:34:16.322825 #
11231 12:34:16.329475 # ======================================================================
11232 12:34:16.333079 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11233 12:34:16.339799 # ----------------------------------------------------------------------
11234 12:34:16.342938 # Traceback (most recent call last):
11235 12:34:16.353425 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11236 12:34:16.356730 # self.client = tpm2.Client()
11237 12:34:16.367011 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11238 12:34:16.373223 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11239 12:34:16.376433 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11240 12:34:16.376936 #
11241 12:34:16.382768 # ======================================================================
11242 12:34:16.389934 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11243 12:34:16.396187 # ----------------------------------------------------------------------
11244 12:34:16.399593 # Traceback (most recent call last):
11245 12:34:16.410120 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11246 12:34:16.412963 # self.client = tpm2.Client()
11247 12:34:16.422817 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11248 12:34:16.426411 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11249 12:34:16.432853 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11250 12:34:16.433444 #
11251 12:34:16.439421 # ----------------------------------------------------------------------
11252 12:34:16.443033 # Ran 9 tests in 0.028s
11253 12:34:16.443725 #
11254 12:34:16.444108 # FAILED (errors=9)
11255 12:34:16.446243 # test_async (tpm2_tests.AsyncTest) ... ok
11256 12:34:16.453515 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11257 12:34:16.454098 #
11258 12:34:16.459412 # ----------------------------------------------------------------------
11259 12:34:16.463474 # Ran 2 tests in 0.033s
11260 12:34:16.464150 #
11261 12:34:16.464539 # OK
11262 12:34:16.466373 ok 1 selftests: tpm2: test_smoke.sh
11263 12:34:16.469206 # selftests: tpm2: test_space.sh
11264 12:34:16.472527 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11265 12:34:16.476037 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11266 12:34:16.482396 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11267 12:34:16.486344 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11268 12:34:16.486874 #
11269 12:34:16.492596 # ======================================================================
11270 12:34:16.499413 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11271 12:34:16.506456 # ----------------------------------------------------------------------
11272 12:34:16.509515 # Traceback (most recent call last):
11273 12:34:16.519129 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11274 12:34:16.522406 # root1 = space1.create_root_key()
11275 12:34:16.532419 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11276 12:34:16.538817 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11277 12:34:16.549243 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11278 12:34:16.552960 # raise ProtocolError(cc, rc)
11279 12:34:16.559006 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11280 12:34:16.559483 #
11281 12:34:16.565685 # ======================================================================
11282 12:34:16.569412 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11283 12:34:16.575781 # ----------------------------------------------------------------------
11284 12:34:16.579428 # Traceback (most recent call last):
11285 12:34:16.589010 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11286 12:34:16.592345 # space1.create_root_key()
11287 12:34:16.602467 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11288 12:34:16.608912 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11289 12:34:16.618860 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11290 12:34:16.622724 # raise ProtocolError(cc, rc)
11291 12:34:16.625816 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11292 12:34:16.629505 #
11293 12:34:16.632381 # ======================================================================
11294 12:34:16.639162 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11295 12:34:16.645734 # ----------------------------------------------------------------------
11296 12:34:16.649259 # Traceback (most recent call last):
11297 12:34:16.659278 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11298 12:34:16.662479 # root1 = space1.create_root_key()
11299 12:34:16.672352 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11300 12:34:16.679226 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11301 12:34:16.688940 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11302 12:34:16.692533 # raise ProtocolError(cc, rc)
11303 12:34:16.695683 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11304 12:34:16.699344 #
11305 12:34:16.702445 # ======================================================================
11306 12:34:16.709254 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11307 12:34:16.716128 # ----------------------------------------------------------------------
11308 12:34:16.719233 # Traceback (most recent call last):
11309 12:34:16.729227 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11310 12:34:16.733134 # root1 = space1.create_root_key()
11311 12:34:16.742665 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11312 12:34:16.749253 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11313 12:34:16.759355 # File "/lava-10605812/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11314 12:34:16.762136 # raise ProtocolError(cc, rc)
11315 12:34:16.768962 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11316 12:34:16.769049 #
11317 12:34:16.775847 # ----------------------------------------------------------------------
11318 12:34:16.778962 # Ran 4 tests in 0.074s
11319 12:34:16.779047 #
11320 12:34:16.779132 # FAILED (errors=4)
11321 12:34:16.782646 not ok 2 selftests: tpm2: test_space.sh # exit=1
11322 12:34:16.790010 tpm2_test_smoke_sh pass
11323 12:34:16.792897 tpm2_test_space_sh fail
11324 12:34:16.808996 + ../../utils/send-to-lava.sh ./output/result.txt
11325 12:34:16.882529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11326 12:34:16.882870 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11328 12:34:16.918284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11329 12:34:16.918544 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11331 12:34:16.921447 + set +x
11332 12:34:16.924384 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10605812_1.6.2.3.5>
11333 12:34:16.924641 Received signal: <ENDRUN> 1_kselftest-tpm2 10605812_1.6.2.3.5
11334 12:34:16.924724 Ending use of test pattern.
11335 12:34:16.924800 Ending test lava.1_kselftest-tpm2 (10605812_1.6.2.3.5), duration 9.04
11337 12:34:16.927909 <LAVA_TEST_RUNNER EXIT>
11338 12:34:16.928164 ok: lava_test_shell seems to have completed
11339 12:34:16.928283 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11340 12:34:16.928385 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11341 12:34:16.928487 end: 3 lava-test-retry (duration 00:00:10) [common]
11342 12:34:16.928588 start: 4 finalize (timeout 00:07:44) [common]
11343 12:34:16.928693 start: 4.1 power-off (timeout 00:00:30) [common]
11344 12:34:16.928860 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11345 12:34:17.004874 >> Command sent successfully.
11346 12:34:17.008534 Returned 0 in 0 seconds
11347 12:34:17.109050 end: 4.1 power-off (duration 00:00:00) [common]
11349 12:34:17.109423 start: 4.2 read-feedback (timeout 00:07:44) [common]
11350 12:34:17.109703 Listened to connection for namespace 'common' for up to 1s
11351 12:34:18.110669 Finalising connection for namespace 'common'
11352 12:34:18.110869 Disconnecting from shell: Finalise
11353 12:34:18.110977 / #
11354 12:34:18.211617 end: 4.2 read-feedback (duration 00:00:01) [common]
11355 12:34:18.212266 end: 4 finalize (duration 00:00:01) [common]
11356 12:34:18.212858 Cleaning after the job
11357 12:34:18.213429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/ramdisk
11358 12:34:18.218490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/kernel
11359 12:34:18.227230 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/dtb
11360 12:34:18.227411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/nfsrootfs
11361 12:34:18.295706 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605812/tftp-deploy-xnewfqnq/modules
11362 12:34:18.301129 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605812
11363 12:34:18.814120 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605812
11364 12:34:18.814304 Job finished correctly