Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 12:28:42.443669 lava-dispatcher, installed at version: 2023.05.1
2 12:28:42.443870 start: 0 validate
3 12:28:42.444001 Start time: 2023-06-06 12:28:42.443994+00:00 (UTC)
4 12:28:42.444123 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:28:42.444254 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:28:42.732642 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:28:42.732879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:28:43.023953 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:28:43.024638 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:28:43.317624 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:28:43.317943 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:28:43.613175 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:28:43.613391 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:28:43.897828 validate duration: 1.45
16 12:28:43.898082 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:28:43.898180 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:28:43.898269 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:28:43.898396 Not decompressing ramdisk as can be used compressed.
20 12:28:43.898481 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 12:28:43.898549 saving as /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/ramdisk/initrd.cpio.gz
22 12:28:43.898611 total size: 4665273 (4MB)
23 12:28:43.900308 progress 0% (0MB)
24 12:28:43.901608 progress 5% (0MB)
25 12:28:43.902813 progress 10% (0MB)
26 12:28:43.904024 progress 15% (0MB)
27 12:28:43.905266 progress 20% (0MB)
28 12:28:43.906482 progress 25% (1MB)
29 12:28:43.907691 progress 30% (1MB)
30 12:28:43.908937 progress 35% (1MB)
31 12:28:43.910145 progress 40% (1MB)
32 12:28:43.911548 progress 45% (2MB)
33 12:28:43.912753 progress 50% (2MB)
34 12:28:43.914007 progress 55% (2MB)
35 12:28:43.915200 progress 60% (2MB)
36 12:28:43.916394 progress 65% (2MB)
37 12:28:43.917629 progress 70% (3MB)
38 12:28:43.918870 progress 75% (3MB)
39 12:28:43.920074 progress 80% (3MB)
40 12:28:43.921473 progress 85% (3MB)
41 12:28:43.922690 progress 90% (4MB)
42 12:28:43.923891 progress 95% (4MB)
43 12:28:43.925145 progress 100% (4MB)
44 12:28:43.925296 4MB downloaded in 0.03s (166.76MB/s)
45 12:28:43.925449 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:28:43.925690 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:28:43.925776 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:28:43.925861 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:28:43.926018 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:28:43.926096 saving as /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/kernel/Image
52 12:28:43.926160 total size: 45746688 (43MB)
53 12:28:43.926220 No compression specified
54 12:28:43.927325 progress 0% (0MB)
55 12:28:43.938886 progress 5% (2MB)
56 12:28:43.950342 progress 10% (4MB)
57 12:28:43.961980 progress 15% (6MB)
58 12:28:43.973716 progress 20% (8MB)
59 12:28:43.985219 progress 25% (10MB)
60 12:28:43.996650 progress 30% (13MB)
61 12:28:44.008161 progress 35% (15MB)
62 12:28:44.020217 progress 40% (17MB)
63 12:28:44.032100 progress 45% (19MB)
64 12:28:44.044590 progress 50% (21MB)
65 12:28:44.056626 progress 55% (24MB)
66 12:28:44.068546 progress 60% (26MB)
67 12:28:44.080234 progress 65% (28MB)
68 12:28:44.091965 progress 70% (30MB)
69 12:28:44.103941 progress 75% (32MB)
70 12:28:44.115760 progress 80% (34MB)
71 12:28:44.128164 progress 85% (37MB)
72 12:28:44.140399 progress 90% (39MB)
73 12:28:44.151890 progress 95% (41MB)
74 12:28:44.163396 progress 100% (43MB)
75 12:28:44.163553 43MB downloaded in 0.24s (183.78MB/s)
76 12:28:44.163708 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:28:44.163940 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:28:44.164028 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:28:44.164113 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:28:44.164255 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:28:44.164326 saving as /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/dtb/mt8192-asurada-spherion-r0.dtb
83 12:28:44.164391 total size: 46924 (0MB)
84 12:28:44.164451 No compression specified
85 12:28:44.165614 progress 69% (0MB)
86 12:28:44.165884 progress 100% (0MB)
87 12:28:44.166035 0MB downloaded in 0.00s (27.26MB/s)
88 12:28:44.166156 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:28:44.166378 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:28:44.166464 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:28:44.166547 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:28:44.166657 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 12:28:44.166725 saving as /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/nfsrootfs/full.rootfs.tar
95 12:28:44.166786 total size: 89386020 (85MB)
96 12:28:44.166846 Using unxz to decompress xz
97 12:28:44.171067 progress 0% (0MB)
98 12:28:44.383600 progress 5% (4MB)
99 12:28:44.600914 progress 10% (8MB)
100 12:28:44.853278 progress 15% (12MB)
101 12:28:45.050116 progress 20% (17MB)
102 12:28:45.144710 progress 25% (21MB)
103 12:28:45.397316 progress 30% (25MB)
104 12:28:45.680912 progress 35% (29MB)
105 12:28:45.946153 progress 40% (34MB)
106 12:28:46.205558 progress 45% (38MB)
107 12:28:46.453461 progress 50% (42MB)
108 12:28:46.715791 progress 55% (46MB)
109 12:28:46.966202 progress 60% (51MB)
110 12:28:47.232534 progress 65% (55MB)
111 12:28:47.526286 progress 70% (59MB)
112 12:28:47.828012 progress 75% (63MB)
113 12:28:48.124756 progress 80% (68MB)
114 12:28:48.377972 progress 85% (72MB)
115 12:28:48.607814 progress 90% (76MB)
116 12:28:48.866505 progress 95% (81MB)
117 12:28:49.136771 progress 100% (85MB)
118 12:28:49.143213 85MB downloaded in 4.98s (17.13MB/s)
119 12:28:49.143556 end: 1.4.1 http-download (duration 00:00:05) [common]
121 12:28:49.143966 end: 1.4 download-retry (duration 00:00:05) [common]
122 12:28:49.144091 start: 1.5 download-retry (timeout 00:09:55) [common]
123 12:28:49.144214 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 12:28:49.144397 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:28:49.144498 saving as /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/modules/modules.tar
126 12:28:49.144593 total size: 8539116 (8MB)
127 12:28:49.144693 Using unxz to decompress xz
128 12:28:49.148769 progress 0% (0MB)
129 12:28:49.170541 progress 5% (0MB)
130 12:28:49.195615 progress 10% (0MB)
131 12:28:49.218868 progress 15% (1MB)
132 12:28:49.245865 progress 20% (1MB)
133 12:28:49.271525 progress 25% (2MB)
134 12:28:49.296271 progress 30% (2MB)
135 12:28:49.322496 progress 35% (2MB)
136 12:28:49.347486 progress 40% (3MB)
137 12:28:49.371780 progress 45% (3MB)
138 12:28:49.396920 progress 50% (4MB)
139 12:28:49.420626 progress 55% (4MB)
140 12:28:49.445673 progress 60% (4MB)
141 12:28:49.471316 progress 65% (5MB)
142 12:28:49.496922 progress 70% (5MB)
143 12:28:49.523437 progress 75% (6MB)
144 12:28:49.553838 progress 80% (6MB)
145 12:28:49.576787 progress 85% (6MB)
146 12:28:49.600704 progress 90% (7MB)
147 12:28:49.624753 progress 95% (7MB)
148 12:28:49.650607 progress 100% (8MB)
149 12:28:49.656554 8MB downloaded in 0.51s (15.91MB/s)
150 12:28:49.656924 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:28:49.657246 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:28:49.657358 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 12:28:49.657478 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 12:28:51.337236 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj
156 12:28:51.337434 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:28:51.337537 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 12:28:51.337710 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb
159 12:28:51.337840 makedir: /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin
160 12:28:51.337947 makedir: /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/tests
161 12:28:51.338051 makedir: /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/results
162 12:28:51.338155 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-add-keys
163 12:28:51.338310 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-add-sources
164 12:28:51.338471 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-background-process-start
165 12:28:51.338603 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-background-process-stop
166 12:28:51.338730 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-common-functions
167 12:28:51.338855 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-echo-ipv4
168 12:28:51.338978 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-install-packages
169 12:28:51.339101 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-installed-packages
170 12:28:51.339233 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-os-build
171 12:28:51.339359 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-probe-channel
172 12:28:51.339482 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-probe-ip
173 12:28:51.339609 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-target-ip
174 12:28:51.339733 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-target-mac
175 12:28:51.339864 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-target-storage
176 12:28:51.339989 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-case
177 12:28:51.340114 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-event
178 12:28:51.340237 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-feedback
179 12:28:51.340365 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-raise
180 12:28:51.340493 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-reference
181 12:28:51.340617 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-runner
182 12:28:51.340756 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-set
183 12:28:51.340939 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-test-shell
184 12:28:51.341064 Updating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-install-packages (oe)
185 12:28:51.341216 Updating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/bin/lava-installed-packages (oe)
186 12:28:51.341344 Creating /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/environment
187 12:28:51.341444 LAVA metadata
188 12:28:51.341517 - LAVA_JOB_ID=10605793
189 12:28:51.341583 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:28:51.341686 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 12:28:51.341755 skipped lava-vland-overlay
192 12:28:51.341831 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:28:51.341912 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 12:28:51.341975 skipped lava-multinode-overlay
195 12:28:51.342049 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:28:51.342135 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 12:28:51.342214 Loading test definitions
198 12:28:51.342306 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 12:28:51.342379 Using /lava-10605793 at stage 0
200 12:28:51.342679 uuid=10605793_1.6.2.3.1 testdef=None
201 12:28:51.342771 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:28:51.342858 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 12:28:51.343348 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:28:51.343577 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 12:28:51.344183 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:28:51.344416 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 12:28:51.345053 runner path: /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/0/tests/0_lc-compliance test_uuid 10605793_1.6.2.3.1
210 12:28:51.345208 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:28:51.345420 Creating lava-test-runner.conf files
213 12:28:51.345486 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605793/lava-overlay-a04z14lb/lava-10605793/0 for stage 0
214 12:28:51.345576 - 0_lc-compliance
215 12:28:51.345673 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 12:28:51.345760 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 12:28:51.351661 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 12:28:51.351769 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 12:28:51.351857 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 12:28:51.351944 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 12:28:51.352032 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 12:28:51.468942 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 12:28:51.469324 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 12:28:51.469529 extracting modules file /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj
225 12:28:51.733354 extracting modules file /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605793/extract-overlay-ramdisk-cqrn9tmm/ramdisk
226 12:28:51.949865 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 12:28:51.950069 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 12:28:51.950200 [common] Applying overlay to NFS
229 12:28:51.950305 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605793/compress-overlay-eztc4d89/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj
230 12:28:51.960297 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 12:28:51.960458 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 12:28:51.960591 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 12:28:51.960718 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 12:28:51.960849 Building ramdisk /var/lib/lava/dispatcher/tmp/10605793/extract-overlay-ramdisk-cqrn9tmm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605793/extract-overlay-ramdisk-cqrn9tmm/ramdisk
235 12:28:52.226267 >> 117807 blocks
236 12:28:54.283222 rename /var/lib/lava/dispatcher/tmp/10605793/extract-overlay-ramdisk-cqrn9tmm/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/ramdisk/ramdisk.cpio.gz
237 12:28:54.283696 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 12:28:54.283850 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 12:28:54.283985 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 12:28:54.284131 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/kernel/Image'
241 12:29:06.577678 Returned 0 in 12 seconds
242 12:29:06.678258 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/kernel/image.itb
243 12:29:06.980885 output: FIT description: Kernel Image image with one or more FDT blobs
244 12:29:06.981239 output: Created: Tue Jun 6 13:29:06 2023
245 12:29:06.981327 output: Image 0 (kernel-1)
246 12:29:06.981396 output: Description:
247 12:29:06.981464 output: Created: Tue Jun 6 13:29:06 2023
248 12:29:06.981525 output: Type: Kernel Image
249 12:29:06.981588 output: Compression: lzma compressed
250 12:29:06.981650 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
251 12:29:06.981713 output: Architecture: AArch64
252 12:29:06.981774 output: OS: Linux
253 12:29:06.981835 output: Load Address: 0x00000000
254 12:29:06.981897 output: Entry Point: 0x00000000
255 12:29:06.981959 output: Hash algo: crc32
256 12:29:06.982016 output: Hash value: a26c3f91
257 12:29:06.982073 output: Image 1 (fdt-1)
258 12:29:06.982129 output: Description: mt8192-asurada-spherion-r0
259 12:29:06.982204 output: Created: Tue Jun 6 13:29:06 2023
260 12:29:06.982266 output: Type: Flat Device Tree
261 12:29:06.982323 output: Compression: uncompressed
262 12:29:06.982380 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 12:29:06.982437 output: Architecture: AArch64
264 12:29:06.982494 output: Hash algo: crc32
265 12:29:06.982553 output: Hash value: 1df858fa
266 12:29:06.982612 output: Image 2 (ramdisk-1)
267 12:29:06.982670 output: Description: unavailable
268 12:29:06.982727 output: Created: Tue Jun 6 13:29:06 2023
269 12:29:06.982783 output: Type: RAMDisk Image
270 12:29:06.982840 output: Compression: Unknown Compression
271 12:29:06.982896 output: Data Size: 17646135 Bytes = 17232.55 KiB = 16.83 MiB
272 12:29:06.982953 output: Architecture: AArch64
273 12:29:06.983009 output: OS: Linux
274 12:29:06.983066 output: Load Address: unavailable
275 12:29:06.983122 output: Entry Point: unavailable
276 12:29:06.983178 output: Hash algo: crc32
277 12:29:06.983234 output: Hash value: 2c28258a
278 12:29:06.983291 output: Default Configuration: 'conf-1'
279 12:29:06.983346 output: Configuration 0 (conf-1)
280 12:29:06.983403 output: Description: mt8192-asurada-spherion-r0
281 12:29:06.983463 output: Kernel: kernel-1
282 12:29:06.983520 output: Init Ramdisk: ramdisk-1
283 12:29:06.983575 output: FDT: fdt-1
284 12:29:06.983631 output: Loadables: kernel-1
285 12:29:06.983692 output:
286 12:29:06.983893 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 12:29:06.983999 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 12:29:06.984108 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 12:29:06.984209 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 12:29:06.984289 No LXC device requested
291 12:29:06.984371 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 12:29:06.984461 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 12:29:06.984547 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 12:29:06.984624 Checking files for TFTP limit of 4294967296 bytes.
295 12:29:06.985123 end: 1 tftp-deploy (duration 00:00:23) [common]
296 12:29:06.985229 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 12:29:06.985327 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 12:29:06.985466 substitutions:
299 12:29:06.985539 - {DTB}: 10605793/tftp-deploy-se3bmgto/dtb/mt8192-asurada-spherion-r0.dtb
300 12:29:06.985607 - {INITRD}: 10605793/tftp-deploy-se3bmgto/ramdisk/ramdisk.cpio.gz
301 12:29:06.985671 - {KERNEL}: 10605793/tftp-deploy-se3bmgto/kernel/Image
302 12:29:06.985733 - {LAVA_MAC}: None
303 12:29:06.985793 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj
304 12:29:06.985852 - {NFS_SERVER_IP}: 192.168.201.1
305 12:29:06.985911 - {PRESEED_CONFIG}: None
306 12:29:06.985968 - {PRESEED_LOCAL}: None
307 12:29:06.986026 - {RAMDISK}: 10605793/tftp-deploy-se3bmgto/ramdisk/ramdisk.cpio.gz
308 12:29:06.986084 - {ROOT_PART}: None
309 12:29:06.986141 - {ROOT}: None
310 12:29:06.986199 - {SERVER_IP}: 192.168.201.1
311 12:29:06.986255 - {TEE}: None
312 12:29:06.986312 Parsed boot commands:
313 12:29:06.986369 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 12:29:06.986563 Parsed boot commands: tftpboot 192.168.201.1 10605793/tftp-deploy-se3bmgto/kernel/image.itb 10605793/tftp-deploy-se3bmgto/kernel/cmdline
315 12:29:06.986657 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 12:29:06.986752 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 12:29:06.986846 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 12:29:06.986936 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 12:29:06.987010 Not connected, no need to disconnect.
320 12:29:06.987088 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 12:29:06.987172 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 12:29:06.987245 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
323 12:29:06.990541 Setting prompt string to ['lava-test: # ']
324 12:29:06.990920 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 12:29:06.991032 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 12:29:06.991134 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 12:29:06.991232 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 12:29:06.991436 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 12:29:12.125632 >> Command sent successfully.
330 12:29:12.127981 Returned 0 in 5 seconds
331 12:29:12.228385 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 12:29:12.228943 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 12:29:12.229079 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 12:29:12.229195 Setting prompt string to 'Starting depthcharge on Spherion...'
336 12:29:12.229298 Changing prompt to 'Starting depthcharge on Spherion...'
337 12:29:12.229372 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 12:29:12.229765 [Enter `^Ec?' for help]
339 12:29:12.401588
340 12:29:12.401750
341 12:29:12.401825 F0: 102B 0000
342 12:29:12.401896
343 12:29:12.405342 F3: 1001 0000 [0200]
344 12:29:12.405427
345 12:29:12.405539 F3: 1001 0000
346 12:29:12.405621
347 12:29:12.405721 F7: 102D 0000
348 12:29:12.405820
349 12:29:12.408626 F1: 0000 0000
350 12:29:12.408727
351 12:29:12.408860 V0: 0000 0000 [0001]
352 12:29:12.408959
353 12:29:12.411679 00: 0007 8000
354 12:29:12.411855
355 12:29:12.411956 01: 0000 0000
356 12:29:12.412074
357 12:29:12.415340 BP: 0C00 0209 [0000]
358 12:29:12.415459
359 12:29:12.415566 G0: 1182 0000
360 12:29:12.415676
361 12:29:12.418487 EC: 0000 0021 [4000]
362 12:29:12.418601
363 12:29:12.418712 S7: 0000 0000 [0000]
364 12:29:12.418850
365 12:29:12.421753 CC: 0000 0000 [0001]
366 12:29:12.421851
367 12:29:12.421957 T0: 0000 0040 [010F]
368 12:29:12.422061
369 12:29:12.425250 Jump to BL
370 12:29:12.425339
371 12:29:12.449085
372 12:29:12.449174
373 12:29:12.449260
374 12:29:12.456111 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 12:29:12.459853 ARM64: Exception handlers installed.
376 12:29:12.463719 ARM64: Testing exception
377 12:29:12.467304 ARM64: Done test exception
378 12:29:12.473716 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 12:29:12.484205 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 12:29:12.490642 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 12:29:12.500950 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 12:29:12.507107 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 12:29:12.513890 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 12:29:12.525517 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 12:29:12.532463 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 12:29:12.551485 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 12:29:12.554855 WDT: Last reset was cold boot
388 12:29:12.558247 SPI1(PAD0) initialized at 2873684 Hz
389 12:29:12.561687 SPI5(PAD0) initialized at 992727 Hz
390 12:29:12.564907 VBOOT: Loading verstage.
391 12:29:12.571609 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 12:29:12.575027 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 12:29:12.578466 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 12:29:12.581448 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 12:29:12.589137 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 12:29:12.595575 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 12:29:12.606849 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 12:29:12.606962
399 12:29:12.607060
400 12:29:12.616569 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 12:29:12.620027 ARM64: Exception handlers installed.
402 12:29:12.622913 ARM64: Testing exception
403 12:29:12.623024 ARM64: Done test exception
404 12:29:12.629882 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 12:29:12.633372 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 12:29:12.647474 Probing TPM: . done!
407 12:29:12.647622 TPM ready after 0 ms
408 12:29:12.654106 Connected to device vid:did:rid of 1ae0:0028:00
409 12:29:12.661388 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 12:29:12.719258 Initialized TPM device CR50 revision 0
411 12:29:12.731599 tlcl_send_startup: Startup return code is 0
412 12:29:12.731769 TPM: setup succeeded
413 12:29:12.742976 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 12:29:12.751591 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 12:29:12.758864 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 12:29:12.771110 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 12:29:12.774522 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 12:29:12.781837 in-header: 03 07 00 00 08 00 00 00
419 12:29:12.785406 in-data: aa e4 47 04 13 02 00 00
420 12:29:12.788884 Chrome EC: UHEPI supported
421 12:29:12.796011 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 12:29:12.799699 in-header: 03 ad 00 00 08 00 00 00
423 12:29:12.803569 in-data: 00 20 20 08 00 00 00 00
424 12:29:12.803666 Phase 1
425 12:29:12.807067 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 12:29:12.814557 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 12:29:12.818443 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 12:29:12.821727 Recovery requested (1009000e)
429 12:29:12.831767 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 12:29:12.836596 tlcl_extend: response is 0
431 12:29:12.841593 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 12:29:12.852828 tlcl_extend: response is 0
433 12:29:12.859965 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 12:29:12.880346 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 12:29:12.887093 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 12:29:12.887219
437 12:29:12.887289
438 12:29:12.896675 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 12:29:12.900428 ARM64: Exception handlers installed.
440 12:29:12.900526 ARM64: Testing exception
441 12:29:12.903693 ARM64: Done test exception
442 12:29:12.925807 pmic_efuse_setting: Set efuses in 11 msecs
443 12:29:12.929235 pmwrap_interface_init: Select PMIF_VLD_RDY
444 12:29:12.935889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 12:29:12.939406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 12:29:12.942902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 12:29:12.949206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 12:29:12.952750 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 12:29:12.959757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 12:29:12.963907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 12:29:12.967155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 12:29:12.974995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 12:29:12.978379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 12:29:12.982276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 12:29:12.985805 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 12:29:12.992657 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 12:29:12.998990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 12:29:13.002610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 12:29:13.009126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 12:29:13.016477 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 12:29:13.020466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 12:29:13.027216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 12:29:13.030873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 12:29:13.037725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 12:29:13.041037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 12:29:13.048017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 12:29:13.054716 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 12:29:13.057974 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 12:29:13.064512 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 12:29:13.071286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 12:29:13.074460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 12:29:13.077921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 12:29:13.084347 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 12:29:13.087542 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 12:29:13.094491 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 12:29:13.097752 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 12:29:13.104503 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 12:29:13.107691 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 12:29:13.114222 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 12:29:13.121187 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 12:29:13.124543 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 12:29:13.127537 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 12:29:13.134371 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 12:29:13.137795 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 12:29:13.141579 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 12:29:13.144891 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 12:29:13.151926 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 12:29:13.154848 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 12:29:13.158241 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 12:29:13.164904 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 12:29:13.168306 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 12:29:13.171578 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 12:29:13.174915 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 12:29:13.181628 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 12:29:13.188101 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 12:29:13.198315 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 12:29:13.201356 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 12:29:13.208346 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 12:29:13.218306 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 12:29:13.221734 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 12:29:13.228729 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 12:29:13.232095 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 12:29:13.239251 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 12:29:13.242950 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 12:29:13.250482 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 12:29:13.253851 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 12:29:13.263086 [RTC]rtc_get_frequency_meter,154: input=15, output=772
508 12:29:13.272352 [RTC]rtc_get_frequency_meter,154: input=23, output=958
509 12:29:13.282120 [RTC]rtc_get_frequency_meter,154: input=19, output=865
510 12:29:13.291343 [RTC]rtc_get_frequency_meter,154: input=17, output=819
511 12:29:13.300432 [RTC]rtc_get_frequency_meter,154: input=16, output=794
512 12:29:13.303870 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 12:29:13.310358 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 12:29:13.314063 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
515 12:29:13.317351 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 12:29:13.320592 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
517 12:29:13.323835 ADC[4]: Raw value=902507 ID=7
518 12:29:13.327201 ADC[3]: Raw value=213179 ID=1
519 12:29:13.330802 RAM Code: 0x71
520 12:29:13.333772 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 12:29:13.337057 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 12:29:13.347760 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 12:29:13.355278 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 12:29:13.358776 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 12:29:13.362726 in-header: 03 07 00 00 08 00 00 00
526 12:29:13.362830 in-data: aa e4 47 04 13 02 00 00
527 12:29:13.366603 Chrome EC: UHEPI supported
528 12:29:13.373808 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 12:29:13.376781 in-header: 03 ed 00 00 08 00 00 00
530 12:29:13.380035 in-data: 80 20 60 08 00 00 00 00
531 12:29:13.383436 MRC: failed to locate region type 0.
532 12:29:13.390261 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 12:29:13.393519 DRAM-K: Running full calibration
534 12:29:13.400025 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 12:29:13.400153 header.status = 0x0
536 12:29:13.403436 header.version = 0x6 (expected: 0x6)
537 12:29:13.406762 header.size = 0xd00 (expected: 0xd00)
538 12:29:13.410095 header.flags = 0x0
539 12:29:13.416173 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 12:29:13.432884 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
541 12:29:13.439254 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 12:29:13.442674 dram_init: ddr_geometry: 2
543 12:29:13.445841 [EMI] MDL number = 2
544 12:29:13.445994 [EMI] Get MDL freq = 0
545 12:29:13.449207 dram_init: ddr_type: 0
546 12:29:13.449314 is_discrete_lpddr4: 1
547 12:29:13.452645 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 12:29:13.452732
549 12:29:13.452824
550 12:29:13.455571 [Bian_co] ETT version 0.0.0.1
551 12:29:13.462312 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 12:29:13.462443
553 12:29:13.465705 dramc_set_vcore_voltage set vcore to 650000
554 12:29:13.469246 Read voltage for 800, 4
555 12:29:13.469336 Vio18 = 0
556 12:29:13.469417 Vcore = 650000
557 12:29:13.472434 Vdram = 0
558 12:29:13.472604 Vddq = 0
559 12:29:13.472706 Vmddr = 0
560 12:29:13.475648 dram_init: config_dvfs: 1
561 12:29:13.479153 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 12:29:13.485815 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 12:29:13.489252 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
564 12:29:13.492502 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
565 12:29:13.495910 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 12:29:13.499265 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 12:29:13.502473 MEM_TYPE=3, freq_sel=18
568 12:29:13.505948 sv_algorithm_assistance_LP4_1600
569 12:29:13.509308 ============ PULL DRAM RESETB DOWN ============
570 12:29:13.515607 ========== PULL DRAM RESETB DOWN end =========
571 12:29:13.519003 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 12:29:13.522419 ===================================
573 12:29:13.526017 LPDDR4 DRAM CONFIGURATION
574 12:29:13.529127 ===================================
575 12:29:13.529224 EX_ROW_EN[0] = 0x0
576 12:29:13.532536 EX_ROW_EN[1] = 0x0
577 12:29:13.532628 LP4Y_EN = 0x0
578 12:29:13.535941 WORK_FSP = 0x0
579 12:29:13.536028 WL = 0x2
580 12:29:13.539350 RL = 0x2
581 12:29:13.539435 BL = 0x2
582 12:29:13.542237 RPST = 0x0
583 12:29:13.542324 RD_PRE = 0x0
584 12:29:13.545613 WR_PRE = 0x1
585 12:29:13.545724 WR_PST = 0x0
586 12:29:13.549313 DBI_WR = 0x0
587 12:29:13.549441 DBI_RD = 0x0
588 12:29:13.552663 OTF = 0x1
589 12:29:13.555689 ===================================
590 12:29:13.559047 ===================================
591 12:29:13.559142 ANA top config
592 12:29:13.562295 ===================================
593 12:29:13.565653 DLL_ASYNC_EN = 0
594 12:29:13.569094 ALL_SLAVE_EN = 1
595 12:29:13.572506 NEW_RANK_MODE = 1
596 12:29:13.572613 DLL_IDLE_MODE = 1
597 12:29:13.575775 LP45_APHY_COMB_EN = 1
598 12:29:13.578781 TX_ODT_DIS = 1
599 12:29:13.582169 NEW_8X_MODE = 1
600 12:29:13.585639 ===================================
601 12:29:13.589000 ===================================
602 12:29:13.592404 data_rate = 1600
603 12:29:13.595522 CKR = 1
604 12:29:13.595611 DQ_P2S_RATIO = 8
605 12:29:13.598870 ===================================
606 12:29:13.602405 CA_P2S_RATIO = 8
607 12:29:13.605326 DQ_CA_OPEN = 0
608 12:29:13.609108 DQ_SEMI_OPEN = 0
609 12:29:13.612223 CA_SEMI_OPEN = 0
610 12:29:13.612329 CA_FULL_RATE = 0
611 12:29:13.615335 DQ_CKDIV4_EN = 1
612 12:29:13.618768 CA_CKDIV4_EN = 1
613 12:29:13.622236 CA_PREDIV_EN = 0
614 12:29:13.625583 PH8_DLY = 0
615 12:29:13.628847 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 12:29:13.628941 DQ_AAMCK_DIV = 4
617 12:29:13.632033 CA_AAMCK_DIV = 4
618 12:29:13.635691 CA_ADMCK_DIV = 4
619 12:29:13.638643 DQ_TRACK_CA_EN = 0
620 12:29:13.641984 CA_PICK = 800
621 12:29:13.645299 CA_MCKIO = 800
622 12:29:13.648696 MCKIO_SEMI = 0
623 12:29:13.648840 PLL_FREQ = 3068
624 12:29:13.652049 DQ_UI_PI_RATIO = 32
625 12:29:13.655414 CA_UI_PI_RATIO = 0
626 12:29:13.658873 ===================================
627 12:29:13.661878 ===================================
628 12:29:13.665654 memory_type:LPDDR4
629 12:29:13.665753 GP_NUM : 10
630 12:29:13.668639 SRAM_EN : 1
631 12:29:13.672161 MD32_EN : 0
632 12:29:13.675609 ===================================
633 12:29:13.675744 [ANA_INIT] >>>>>>>>>>>>>>
634 12:29:13.679497 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 12:29:13.683285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 12:29:13.686754 ===================================
637 12:29:13.690721 data_rate = 1600,PCW = 0X7600
638 12:29:13.690837 ===================================
639 12:29:13.694503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 12:29:13.701676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 12:29:13.705559 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 12:29:13.712822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 12:29:13.715752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 12:29:13.719303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 12:29:13.719411 [ANA_INIT] flow start
646 12:29:13.722578 [ANA_INIT] PLL >>>>>>>>
647 12:29:13.726023 [ANA_INIT] PLL <<<<<<<<
648 12:29:13.726124 [ANA_INIT] MIDPI >>>>>>>>
649 12:29:13.729426 [ANA_INIT] MIDPI <<<<<<<<
650 12:29:13.732486 [ANA_INIT] DLL >>>>>>>>
651 12:29:13.732584 [ANA_INIT] flow end
652 12:29:13.739129 ============ LP4 DIFF to SE enter ============
653 12:29:13.742516 ============ LP4 DIFF to SE exit ============
654 12:29:13.745883 [ANA_INIT] <<<<<<<<<<<<<
655 12:29:13.745982 [Flow] Enable top DCM control >>>>>
656 12:29:13.749382 [Flow] Enable top DCM control <<<<<
657 12:29:13.752381 Enable DLL master slave shuffle
658 12:29:13.759216 ==============================================================
659 12:29:13.762570 Gating Mode config
660 12:29:13.766023 ==============================================================
661 12:29:13.769350 Config description:
662 12:29:13.779211 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 12:29:13.785457 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 12:29:13.789186 SELPH_MODE 0: By rank 1: By Phase
665 12:29:13.795496 ==============================================================
666 12:29:13.798896 GAT_TRACK_EN = 1
667 12:29:13.802335 RX_GATING_MODE = 2
668 12:29:13.805673 RX_GATING_TRACK_MODE = 2
669 12:29:13.805777 SELPH_MODE = 1
670 12:29:13.809023 PICG_EARLY_EN = 1
671 12:29:13.812510 VALID_LAT_VALUE = 1
672 12:29:13.818923 ==============================================================
673 12:29:13.822217 Enter into Gating configuration >>>>
674 12:29:13.825474 Exit from Gating configuration <<<<
675 12:29:13.828815 Enter into DVFS_PRE_config >>>>>
676 12:29:13.839139 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 12:29:13.842474 Exit from DVFS_PRE_config <<<<<
678 12:29:13.845917 Enter into PICG configuration >>>>
679 12:29:13.848729 Exit from PICG configuration <<<<
680 12:29:13.852228 [RX_INPUT] configuration >>>>>
681 12:29:13.855602 [RX_INPUT] configuration <<<<<
682 12:29:13.858615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 12:29:13.865288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 12:29:13.872006 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 12:29:13.878833 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 12:29:13.885287 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 12:29:13.888623 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 12:29:13.892374 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 12:29:13.899189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 12:29:13.902650 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 12:29:13.906558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 12:29:13.909815 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 12:29:13.913381 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 12:29:13.916435 ===================================
695 12:29:13.920331 LPDDR4 DRAM CONFIGURATION
696 12:29:13.923631 ===================================
697 12:29:13.927289 EX_ROW_EN[0] = 0x0
698 12:29:13.927428 EX_ROW_EN[1] = 0x0
699 12:29:13.931262 LP4Y_EN = 0x0
700 12:29:13.931364 WORK_FSP = 0x0
701 12:29:13.934546 WL = 0x2
702 12:29:13.934643 RL = 0x2
703 12:29:13.937909 BL = 0x2
704 12:29:13.938005 RPST = 0x0
705 12:29:13.938077 RD_PRE = 0x0
706 12:29:13.941970 WR_PRE = 0x1
707 12:29:13.942074 WR_PST = 0x0
708 12:29:13.945227 DBI_WR = 0x0
709 12:29:13.945332 DBI_RD = 0x0
710 12:29:13.949050 OTF = 0x1
711 12:29:13.952728 ===================================
712 12:29:13.956635 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 12:29:13.960234 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 12:29:13.963678 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 12:29:13.966901 ===================================
716 12:29:13.970943 LPDDR4 DRAM CONFIGURATION
717 12:29:13.974301 ===================================
718 12:29:13.974436 EX_ROW_EN[0] = 0x10
719 12:29:13.978149 EX_ROW_EN[1] = 0x0
720 12:29:13.978279 LP4Y_EN = 0x0
721 12:29:13.981720 WORK_FSP = 0x0
722 12:29:13.981862 WL = 0x2
723 12:29:13.985224 RL = 0x2
724 12:29:13.985351 BL = 0x2
725 12:29:13.989186 RPST = 0x0
726 12:29:13.989313 RD_PRE = 0x0
727 12:29:13.992523 WR_PRE = 0x1
728 12:29:13.992638 WR_PST = 0x0
729 12:29:13.992736 DBI_WR = 0x0
730 12:29:13.996191 DBI_RD = 0x0
731 12:29:13.996304 OTF = 0x1
732 12:29:14.000101 ===================================
733 12:29:14.007464 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 12:29:14.010811 nWR fixed to 40
735 12:29:14.014729 [ModeRegInit_LP4] CH0 RK0
736 12:29:14.014851 [ModeRegInit_LP4] CH0 RK1
737 12:29:14.018176 [ModeRegInit_LP4] CH1 RK0
738 12:29:14.022175 [ModeRegInit_LP4] CH1 RK1
739 12:29:14.022288 match AC timing 13
740 12:29:14.025647 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 12:29:14.029453 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 12:29:14.036642 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 12:29:14.040505 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 12:29:14.044323 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 12:29:14.044436 [EMI DOE] emi_dcm 0
746 12:29:14.051717 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 12:29:14.051848 ==
748 12:29:14.055578 Dram Type= 6, Freq= 0, CH_0, rank 0
749 12:29:14.059068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 12:29:14.059192 ==
751 12:29:14.062913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 12:29:14.069815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 12:29:14.079023 [CA 0] Center 38 (7~69) winsize 63
754 12:29:14.082736 [CA 1] Center 38 (7~69) winsize 63
755 12:29:14.086186 [CA 2] Center 35 (5~66) winsize 62
756 12:29:14.090211 [CA 3] Center 35 (5~66) winsize 62
757 12:29:14.093673 [CA 4] Center 34 (4~65) winsize 62
758 12:29:14.097570 [CA 5] Center 33 (3~64) winsize 62
759 12:29:14.097683
760 12:29:14.101354 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 12:29:14.101460
762 12:29:14.105212 [CATrainingPosCal] consider 1 rank data
763 12:29:14.105338 u2DelayCellTimex100 = 270/100 ps
764 12:29:14.109072 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
765 12:29:14.112591 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
766 12:29:14.116411 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 12:29:14.120196 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 12:29:14.123628 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
769 12:29:14.127643 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 12:29:14.127780
771 12:29:14.131146 CA PerBit enable=1, Macro0, CA PI delay=33
772 12:29:14.131269
773 12:29:14.134995 [CBTSetCACLKResult] CA Dly = 33
774 12:29:14.138427 CS Dly: 5 (0~36)
775 12:29:14.138538 ==
776 12:29:14.142299 Dram Type= 6, Freq= 0, CH_0, rank 1
777 12:29:14.146033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 12:29:14.146144 ==
779 12:29:14.149573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 12:29:14.157034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 12:29:14.165495 [CA 0] Center 38 (7~69) winsize 63
782 12:29:14.169482 [CA 1] Center 38 (8~69) winsize 62
783 12:29:14.172497 [CA 2] Center 36 (6~66) winsize 61
784 12:29:14.176392 [CA 3] Center 35 (5~66) winsize 62
785 12:29:14.179723 [CA 4] Center 35 (4~66) winsize 63
786 12:29:14.183485 [CA 5] Center 34 (4~65) winsize 62
787 12:29:14.183630
788 12:29:14.187389 [CmdBusTrainingLP45] Vref(ca) range 1: 32
789 12:29:14.187511
790 12:29:14.190894 [CATrainingPosCal] consider 2 rank data
791 12:29:14.190984 u2DelayCellTimex100 = 270/100 ps
792 12:29:14.194858 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
793 12:29:14.198351 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
794 12:29:14.202161 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
795 12:29:14.208630 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
796 12:29:14.211966 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
797 12:29:14.215289 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
798 12:29:14.215388
799 12:29:14.218695 CA PerBit enable=1, Macro0, CA PI delay=34
800 12:29:14.218825
801 12:29:14.222082 [CBTSetCACLKResult] CA Dly = 34
802 12:29:14.222184 CS Dly: 6 (0~38)
803 12:29:14.222256
804 12:29:14.225464 ----->DramcWriteLeveling(PI) begin...
805 12:29:14.225559 ==
806 12:29:14.228946 Dram Type= 6, Freq= 0, CH_0, rank 0
807 12:29:14.235325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 12:29:14.235437 ==
809 12:29:14.238684 Write leveling (Byte 0): 30 => 30
810 12:29:14.242085 Write leveling (Byte 1): 30 => 30
811 12:29:14.245019 DramcWriteLeveling(PI) end<-----
812 12:29:14.245115
813 12:29:14.245195 ==
814 12:29:14.248313 Dram Type= 6, Freq= 0, CH_0, rank 0
815 12:29:14.251755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 12:29:14.251860 ==
817 12:29:14.255414 [Gating] SW mode calibration
818 12:29:14.262675 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 12:29:14.266381 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 12:29:14.269415 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
821 12:29:14.276266 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
822 12:29:14.279551 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:29:14.283028 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:29:14.290310 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:29:14.293603 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:29:14.297086 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:29:14.300442 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:29:14.306705 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:29:14.310032 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:29:14.313389 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:29:14.320066 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:29:14.323384 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:29:14.326602 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 12:29:14.333459 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 12:29:14.336464 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 12:29:14.339841 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 12:29:14.346607 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
838 12:29:14.349652 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
839 12:29:14.352998 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:29:14.359728 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:29:14.363021 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:29:14.366181 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:29:14.372886 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:29:14.376541 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:29:14.379431 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
846 12:29:14.386027 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
847 12:29:14.389621 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
848 12:29:14.392920 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 12:29:14.399450 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 12:29:14.402795 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 12:29:14.406266 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 12:29:14.412870 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
853 12:29:14.416313 0 10 4 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
854 12:29:14.419274 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
855 12:29:14.426096 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:29:14.429283 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:29:14.432735 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:29:14.439168 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:29:14.442644 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:29:14.446086 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:29:14.452909 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
862 12:29:14.455834 0 11 8 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
863 12:29:14.459325 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
864 12:29:14.462740 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 12:29:14.469217 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 12:29:14.472652 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 12:29:14.475943 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 12:29:14.482531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 12:29:14.485649 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 12:29:14.488821 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
871 12:29:14.495738 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 12:29:14.498805 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 12:29:14.502167 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 12:29:14.509148 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 12:29:14.512529 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 12:29:14.515900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 12:29:14.522637 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 12:29:14.525554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 12:29:14.528984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 12:29:14.535548 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 12:29:14.539033 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 12:29:14.542463 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 12:29:14.548843 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 12:29:14.552074 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 12:29:14.555448 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
886 12:29:14.562403 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
887 12:29:14.562594 Total UI for P1: 0, mck2ui 16
888 12:29:14.568595 best dqsien dly found for B0: ( 0, 14, 4)
889 12:29:14.571897 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 12:29:14.575309 Total UI for P1: 0, mck2ui 16
891 12:29:14.578687 best dqsien dly found for B1: ( 0, 14, 8)
892 12:29:14.582036 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
893 12:29:14.585383 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
894 12:29:14.585476
895 12:29:14.588740 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
896 12:29:14.591916 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
897 12:29:14.595326 [Gating] SW calibration Done
898 12:29:14.595424 ==
899 12:29:14.598484 Dram Type= 6, Freq= 0, CH_0, rank 0
900 12:29:14.601750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 12:29:14.601852 ==
902 12:29:14.605405 RX Vref Scan: 0
903 12:29:14.605530
904 12:29:14.608391 RX Vref 0 -> 0, step: 1
905 12:29:14.608508
906 12:29:14.611854 RX Delay -130 -> 252, step: 16
907 12:29:14.615259 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
908 12:29:14.618477 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
909 12:29:14.621814 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
910 12:29:14.625283 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
911 12:29:14.631621 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
912 12:29:14.634930 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
913 12:29:14.638166 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
914 12:29:14.641606 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
915 12:29:14.645093 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
916 12:29:14.651599 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
917 12:29:14.654971 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
918 12:29:14.658364 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
919 12:29:14.661769 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
920 12:29:14.664731 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
921 12:29:14.671608 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
922 12:29:14.674993 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
923 12:29:14.675144 ==
924 12:29:14.678455 Dram Type= 6, Freq= 0, CH_0, rank 0
925 12:29:14.681373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 12:29:14.681513 ==
927 12:29:14.684772 DQS Delay:
928 12:29:14.684907 DQS0 = 0, DQS1 = 0
929 12:29:14.685015 DQM Delay:
930 12:29:14.687974 DQM0 = 91, DQM1 = 80
931 12:29:14.688097 DQ Delay:
932 12:29:14.691326 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
933 12:29:14.694631 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
934 12:29:14.697832 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
935 12:29:14.701018 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
936 12:29:14.701131
937 12:29:14.701230
938 12:29:14.701326 ==
939 12:29:14.704454 Dram Type= 6, Freq= 0, CH_0, rank 0
940 12:29:14.711200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 12:29:14.711354 ==
942 12:29:14.711460
943 12:29:14.711560
944 12:29:14.711655 TX Vref Scan disable
945 12:29:14.714907 == TX Byte 0 ==
946 12:29:14.718435 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
947 12:29:14.725059 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
948 12:29:14.725208 == TX Byte 1 ==
949 12:29:14.728491 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 12:29:14.735138 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 12:29:14.735286 ==
952 12:29:14.738520 Dram Type= 6, Freq= 0, CH_0, rank 0
953 12:29:14.741403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 12:29:14.741484 ==
955 12:29:14.753873 TX Vref=22, minBit 8, minWin=26, winSum=439
956 12:29:14.757261 TX Vref=24, minBit 6, minWin=27, winSum=443
957 12:29:14.760690 TX Vref=26, minBit 8, minWin=27, winSum=449
958 12:29:14.764160 TX Vref=28, minBit 12, minWin=27, winSum=452
959 12:29:14.767212 TX Vref=30, minBit 5, minWin=28, winSum=456
960 12:29:14.773879 TX Vref=32, minBit 9, minWin=27, winSum=453
961 12:29:14.777251 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
962 12:29:14.777383
963 12:29:14.780572 Final TX Range 1 Vref 30
964 12:29:14.780681
965 12:29:14.780755 ==
966 12:29:14.783885 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:29:14.787263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:29:14.787404 ==
969 12:29:14.790491
970 12:29:14.790615
971 12:29:14.790715 TX Vref Scan disable
972 12:29:14.793930 == TX Byte 0 ==
973 12:29:14.797406 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
974 12:29:14.803623 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
975 12:29:14.803771 == TX Byte 1 ==
976 12:29:14.807392 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 12:29:14.813734 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 12:29:14.813890
979 12:29:14.814006 [DATLAT]
980 12:29:14.814105 Freq=800, CH0 RK0
981 12:29:14.814201
982 12:29:14.816846 DATLAT Default: 0xa
983 12:29:14.816951 0, 0xFFFF, sum = 0
984 12:29:14.820327 1, 0xFFFF, sum = 0
985 12:29:14.823809 2, 0xFFFF, sum = 0
986 12:29:14.823939 3, 0xFFFF, sum = 0
987 12:29:14.826959 4, 0xFFFF, sum = 0
988 12:29:14.827076 5, 0xFFFF, sum = 0
989 12:29:14.830375 6, 0xFFFF, sum = 0
990 12:29:14.830469 7, 0xFFFF, sum = 0
991 12:29:14.833828 8, 0xFFFF, sum = 0
992 12:29:14.833954 9, 0x0, sum = 1
993 12:29:14.837197 10, 0x0, sum = 2
994 12:29:14.837310 11, 0x0, sum = 3
995 12:29:14.837409 12, 0x0, sum = 4
996 12:29:14.840200 best_step = 10
997 12:29:14.840308
998 12:29:14.840404 ==
999 12:29:14.843943 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:29:14.846778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:29:14.846895 ==
1002 12:29:14.850256 RX Vref Scan: 1
1003 12:29:14.850376
1004 12:29:14.853740 Set Vref Range= 32 -> 127
1005 12:29:14.853856
1006 12:29:14.853960 RX Vref 32 -> 127, step: 1
1007 12:29:14.854059
1008 12:29:14.856691 RX Delay -95 -> 252, step: 8
1009 12:29:14.856816
1010 12:29:14.860174 Set Vref, RX VrefLevel [Byte0]: 32
1011 12:29:14.863441 [Byte1]: 32
1012 12:29:14.866717
1013 12:29:14.866841 Set Vref, RX VrefLevel [Byte0]: 33
1014 12:29:14.869706 [Byte1]: 33
1015 12:29:14.874083
1016 12:29:14.874181 Set Vref, RX VrefLevel [Byte0]: 34
1017 12:29:14.877616 [Byte1]: 34
1018 12:29:14.881910
1019 12:29:14.882005 Set Vref, RX VrefLevel [Byte0]: 35
1020 12:29:14.885278 [Byte1]: 35
1021 12:29:14.889566
1022 12:29:14.889686 Set Vref, RX VrefLevel [Byte0]: 36
1023 12:29:14.892957 [Byte1]: 36
1024 12:29:14.897219
1025 12:29:14.897352 Set Vref, RX VrefLevel [Byte0]: 37
1026 12:29:14.900187 [Byte1]: 37
1027 12:29:14.904919
1028 12:29:14.905009 Set Vref, RX VrefLevel [Byte0]: 38
1029 12:29:14.908252 [Byte1]: 38
1030 12:29:14.912286
1031 12:29:14.912407 Set Vref, RX VrefLevel [Byte0]: 39
1032 12:29:14.915674 [Byte1]: 39
1033 12:29:14.919817
1034 12:29:14.919940 Set Vref, RX VrefLevel [Byte0]: 40
1035 12:29:14.923503 [Byte1]: 40
1036 12:29:14.927790
1037 12:29:14.927912 Set Vref, RX VrefLevel [Byte0]: 41
1038 12:29:14.931099 [Byte1]: 41
1039 12:29:14.934989
1040 12:29:14.935121 Set Vref, RX VrefLevel [Byte0]: 42
1041 12:29:14.938441 [Byte1]: 42
1042 12:29:14.942805
1043 12:29:14.942928 Set Vref, RX VrefLevel [Byte0]: 43
1044 12:29:14.946287 [Byte1]: 43
1045 12:29:14.950539
1046 12:29:14.950669 Set Vref, RX VrefLevel [Byte0]: 44
1047 12:29:14.953624 [Byte1]: 44
1048 12:29:14.957950
1049 12:29:14.958056 Set Vref, RX VrefLevel [Byte0]: 45
1050 12:29:14.961410 [Byte1]: 45
1051 12:29:14.965344
1052 12:29:14.965439 Set Vref, RX VrefLevel [Byte0]: 46
1053 12:29:14.968512 [Byte1]: 46
1054 12:29:14.973009
1055 12:29:14.973110 Set Vref, RX VrefLevel [Byte0]: 47
1056 12:29:14.976246 [Byte1]: 47
1057 12:29:14.980836
1058 12:29:14.980963 Set Vref, RX VrefLevel [Byte0]: 48
1059 12:29:14.983706 [Byte1]: 48
1060 12:29:14.988452
1061 12:29:14.988585 Set Vref, RX VrefLevel [Byte0]: 49
1062 12:29:14.991292 [Byte1]: 49
1063 12:29:14.995712
1064 12:29:14.995822 Set Vref, RX VrefLevel [Byte0]: 50
1065 12:29:14.999075 [Byte1]: 50
1066 12:29:15.003303
1067 12:29:15.003430 Set Vref, RX VrefLevel [Byte0]: 51
1068 12:29:15.006641 [Byte1]: 51
1069 12:29:15.011083
1070 12:29:15.011208 Set Vref, RX VrefLevel [Byte0]: 52
1071 12:29:15.014547 [Byte1]: 52
1072 12:29:15.018471
1073 12:29:15.018592 Set Vref, RX VrefLevel [Byte0]: 53
1074 12:29:15.021746 [Byte1]: 53
1075 12:29:15.026232
1076 12:29:15.026351 Set Vref, RX VrefLevel [Byte0]: 54
1077 12:29:15.029525 [Byte1]: 54
1078 12:29:15.033752
1079 12:29:15.033845 Set Vref, RX VrefLevel [Byte0]: 55
1080 12:29:15.036906 [Byte1]: 55
1081 12:29:15.041441
1082 12:29:15.041556 Set Vref, RX VrefLevel [Byte0]: 56
1083 12:29:15.044922 [Byte1]: 56
1084 12:29:15.049358
1085 12:29:15.049480 Set Vref, RX VrefLevel [Byte0]: 57
1086 12:29:15.052599 [Byte1]: 57
1087 12:29:15.056456
1088 12:29:15.056555 Set Vref, RX VrefLevel [Byte0]: 58
1089 12:29:15.059817 [Byte1]: 58
1090 12:29:15.064256
1091 12:29:15.064358 Set Vref, RX VrefLevel [Byte0]: 59
1092 12:29:15.067663 [Byte1]: 59
1093 12:29:15.071912
1094 12:29:15.072035 Set Vref, RX VrefLevel [Byte0]: 60
1095 12:29:15.075270 [Byte1]: 60
1096 12:29:15.079592
1097 12:29:15.079720 Set Vref, RX VrefLevel [Byte0]: 61
1098 12:29:15.082609 [Byte1]: 61
1099 12:29:15.086975
1100 12:29:15.087071 Set Vref, RX VrefLevel [Byte0]: 62
1101 12:29:15.090295 [Byte1]: 62
1102 12:29:15.094513
1103 12:29:15.094615 Set Vref, RX VrefLevel [Byte0]: 63
1104 12:29:15.098043 [Byte1]: 63
1105 12:29:15.102396
1106 12:29:15.102495 Set Vref, RX VrefLevel [Byte0]: 64
1107 12:29:15.105743 [Byte1]: 64
1108 12:29:15.109481
1109 12:29:15.109626 Set Vref, RX VrefLevel [Byte0]: 65
1110 12:29:15.112858 [Byte1]: 65
1111 12:29:15.117324
1112 12:29:15.117419 Set Vref, RX VrefLevel [Byte0]: 66
1113 12:29:15.120649 [Byte1]: 66
1114 12:29:15.125061
1115 12:29:15.125156 Set Vref, RX VrefLevel [Byte0]: 67
1116 12:29:15.128270 [Byte1]: 67
1117 12:29:15.132596
1118 12:29:15.132717 Set Vref, RX VrefLevel [Byte0]: 68
1119 12:29:15.135726 [Byte1]: 68
1120 12:29:15.140078
1121 12:29:15.140208 Set Vref, RX VrefLevel [Byte0]: 69
1122 12:29:15.143418 [Byte1]: 69
1123 12:29:15.148091
1124 12:29:15.148192 Set Vref, RX VrefLevel [Byte0]: 70
1125 12:29:15.151235 [Byte1]: 70
1126 12:29:15.155600
1127 12:29:15.155700 Set Vref, RX VrefLevel [Byte0]: 71
1128 12:29:15.158929 [Byte1]: 71
1129 12:29:15.162813
1130 12:29:15.162908 Set Vref, RX VrefLevel [Byte0]: 72
1131 12:29:15.166230 [Byte1]: 72
1132 12:29:15.170626
1133 12:29:15.170726 Set Vref, RX VrefLevel [Byte0]: 73
1134 12:29:15.173973 [Byte1]: 73
1135 12:29:15.178206
1136 12:29:15.181619 Set Vref, RX VrefLevel [Byte0]: 74
1137 12:29:15.184533 [Byte1]: 74
1138 12:29:15.184660
1139 12:29:15.187901 Set Vref, RX VrefLevel [Byte0]: 75
1140 12:29:15.191458 [Byte1]: 75
1141 12:29:15.191571
1142 12:29:15.194809 Set Vref, RX VrefLevel [Byte0]: 76
1143 12:29:15.198110 [Byte1]: 76
1144 12:29:15.198233
1145 12:29:15.201208 Set Vref, RX VrefLevel [Byte0]: 77
1146 12:29:15.204659 [Byte1]: 77
1147 12:29:15.208372
1148 12:29:15.208500 Final RX Vref Byte 0 = 62 to rank0
1149 12:29:15.211801 Final RX Vref Byte 1 = 56 to rank0
1150 12:29:15.215117 Final RX Vref Byte 0 = 62 to rank1
1151 12:29:15.218370 Final RX Vref Byte 1 = 56 to rank1==
1152 12:29:15.221884 Dram Type= 6, Freq= 0, CH_0, rank 0
1153 12:29:15.228270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 12:29:15.228400 ==
1155 12:29:15.228474 DQS Delay:
1156 12:29:15.228538 DQS0 = 0, DQS1 = 0
1157 12:29:15.232087 DQM Delay:
1158 12:29:15.232196 DQM0 = 93, DQM1 = 81
1159 12:29:15.234957 DQ Delay:
1160 12:29:15.238423 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1161 12:29:15.241725 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1162 12:29:15.245023 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
1163 12:29:15.248334 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1164 12:29:15.248435
1165 12:29:15.248503
1166 12:29:15.255262 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1167 12:29:15.258321 CH0 RK0: MR19=606, MR18=3D39
1168 12:29:15.265258 CH0_RK0: MR19=0x606, MR18=0x3D39, DQSOSC=394, MR23=63, INC=95, DEC=63
1169 12:29:15.265378
1170 12:29:15.268644 ----->DramcWriteLeveling(PI) begin...
1171 12:29:15.268804 ==
1172 12:29:15.271614 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 12:29:15.274993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1174 12:29:15.275125 ==
1175 12:29:15.278546 Write leveling (Byte 0): 30 => 30
1176 12:29:15.281663 Write leveling (Byte 1): 29 => 29
1177 12:29:15.285142 DramcWriteLeveling(PI) end<-----
1178 12:29:15.285253
1179 12:29:15.285344 ==
1180 12:29:15.288141 Dram Type= 6, Freq= 0, CH_0, rank 1
1181 12:29:15.291643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1182 12:29:15.291750 ==
1183 12:29:15.295038 [Gating] SW mode calibration
1184 12:29:15.301391 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1185 12:29:15.308129 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1186 12:29:15.311489 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1187 12:29:15.318138 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1188 12:29:15.321428 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1189 12:29:15.324870 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:29:15.368738 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:29:15.369144 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:29:15.369313 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:29:15.369481 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:29:15.369595 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:29:15.369658 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:29:15.369734 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:29:15.369797 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 12:29:15.369857 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 12:29:15.369928 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 12:29:15.412937 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:29:15.413351 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:29:15.413632 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1203 12:29:15.413740 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1204 12:29:15.413840 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1205 12:29:15.413944 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:29:15.414050 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:29:15.414142 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:29:15.414236 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:29:15.414325 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:29:15.450036 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:29:15.450484 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:29:15.450751 0 9 8 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
1213 12:29:15.450863 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 12:29:15.450963 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 12:29:15.451069 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 12:29:15.451167 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 12:29:15.454283 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 12:29:15.454361 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 12:29:15.457643 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1220 12:29:15.460586 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1221 12:29:15.467538 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:29:15.470703 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:29:15.474109 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:29:15.477746 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:29:15.483779 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:29:15.487197 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:29:15.490545 0 11 4 | B1->B0 | 2929 3636 | 1 0 | (0 0) (1 1)
1228 12:29:15.497491 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1229 12:29:15.500463 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 12:29:15.503883 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 12:29:15.511161 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 12:29:15.514632 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 12:29:15.518117 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 12:29:15.521427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 12:29:15.528140 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1236 12:29:15.531488 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 12:29:15.534910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 12:29:15.541796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 12:29:15.545188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 12:29:15.548580 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 12:29:15.555163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 12:29:15.558442 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 12:29:15.561851 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 12:29:15.568263 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 12:29:15.571650 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 12:29:15.574993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 12:29:15.578644 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 12:29:15.585158 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 12:29:15.588623 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 12:29:15.591855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 12:29:15.598231 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1252 12:29:15.601710 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:29:15.605123 Total UI for P1: 0, mck2ui 16
1254 12:29:15.608156 best dqsien dly found for B0: ( 0, 14, 4)
1255 12:29:15.611554 Total UI for P1: 0, mck2ui 16
1256 12:29:15.614966 best dqsien dly found for B1: ( 0, 14, 6)
1257 12:29:15.618021 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1258 12:29:15.621490 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1259 12:29:15.621584
1260 12:29:15.625128 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1261 12:29:15.628068 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1262 12:29:15.631352 [Gating] SW calibration Done
1263 12:29:15.631452 ==
1264 12:29:15.635161 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 12:29:15.638122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 12:29:15.641479 ==
1267 12:29:15.641582 RX Vref Scan: 0
1268 12:29:15.641679
1269 12:29:15.644867 RX Vref 0 -> 0, step: 1
1270 12:29:15.644952
1271 12:29:15.648028 RX Delay -130 -> 252, step: 16
1272 12:29:15.651464 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1273 12:29:15.654847 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1274 12:29:15.658127 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1275 12:29:15.661460 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1276 12:29:15.668139 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1277 12:29:15.671191 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1278 12:29:15.674593 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1279 12:29:15.678087 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1280 12:29:15.681485 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1281 12:29:15.687864 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1282 12:29:15.691061 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1283 12:29:15.694552 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1284 12:29:15.697848 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1285 12:29:15.704257 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1286 12:29:15.707683 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1287 12:29:15.711220 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1288 12:29:15.711353 ==
1289 12:29:15.714437 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 12:29:15.717873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 12:29:15.717972 ==
1292 12:29:15.721251 DQS Delay:
1293 12:29:15.721346 DQS0 = 0, DQS1 = 0
1294 12:29:15.724194 DQM Delay:
1295 12:29:15.724284 DQM0 = 90, DQM1 = 81
1296 12:29:15.724353 DQ Delay:
1297 12:29:15.727512 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1298 12:29:15.730858 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1299 12:29:15.734153 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1300 12:29:15.737879 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1301 12:29:15.737982
1302 12:29:15.738052
1303 12:29:15.738115 ==
1304 12:29:15.740753 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 12:29:15.747661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 12:29:15.747804 ==
1307 12:29:15.747899
1308 12:29:15.747965
1309 12:29:15.748026 TX Vref Scan disable
1310 12:29:15.751339 == TX Byte 0 ==
1311 12:29:15.754775 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1312 12:29:15.761491 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1313 12:29:15.761613 == TX Byte 1 ==
1314 12:29:15.764930 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1315 12:29:15.768193 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1316 12:29:15.771584 ==
1317 12:29:15.774963 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 12:29:15.777925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 12:29:15.778049 ==
1320 12:29:15.790440 TX Vref=22, minBit 3, minWin=27, winSum=444
1321 12:29:15.793950 TX Vref=24, minBit 8, minWin=27, winSum=446
1322 12:29:15.797105 TX Vref=26, minBit 8, minWin=27, winSum=451
1323 12:29:15.800360 TX Vref=28, minBit 4, minWin=28, winSum=454
1324 12:29:15.804046 TX Vref=30, minBit 8, minWin=27, winSum=456
1325 12:29:15.807019 TX Vref=32, minBit 8, minWin=27, winSum=454
1326 12:29:15.813842 [TxChooseVref] Worse bit 4, Min win 28, Win sum 454, Final Vref 28
1327 12:29:15.813998
1328 12:29:15.817260 Final TX Range 1 Vref 28
1329 12:29:15.817387
1330 12:29:15.817514 ==
1331 12:29:15.820580 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 12:29:15.823574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 12:29:15.823696 ==
1334 12:29:15.823797
1335 12:29:15.826923
1336 12:29:15.827037 TX Vref Scan disable
1337 12:29:15.830391 == TX Byte 0 ==
1338 12:29:15.833605 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1339 12:29:15.837033 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1340 12:29:15.840388 == TX Byte 1 ==
1341 12:29:15.843705 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1342 12:29:15.850030 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1343 12:29:15.850177
1344 12:29:15.850283 [DATLAT]
1345 12:29:15.850397 Freq=800, CH0 RK1
1346 12:29:15.850493
1347 12:29:15.853531 DATLAT Default: 0xa
1348 12:29:15.853641 0, 0xFFFF, sum = 0
1349 12:29:15.856930 1, 0xFFFF, sum = 0
1350 12:29:15.857050 2, 0xFFFF, sum = 0
1351 12:29:15.860264 3, 0xFFFF, sum = 0
1352 12:29:15.863633 4, 0xFFFF, sum = 0
1353 12:29:15.863763 5, 0xFFFF, sum = 0
1354 12:29:15.867015 6, 0xFFFF, sum = 0
1355 12:29:15.867133 7, 0xFFFF, sum = 0
1356 12:29:15.870444 8, 0xFFFF, sum = 0
1357 12:29:15.870568 9, 0x0, sum = 1
1358 12:29:15.870677 10, 0x0, sum = 2
1359 12:29:15.873403 11, 0x0, sum = 3
1360 12:29:15.873537 12, 0x0, sum = 4
1361 12:29:15.876657 best_step = 10
1362 12:29:15.876781
1363 12:29:15.876886 ==
1364 12:29:15.880105 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 12:29:15.883532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 12:29:15.883650 ==
1367 12:29:15.887032 RX Vref Scan: 0
1368 12:29:15.887149
1369 12:29:15.887246 RX Vref 0 -> 0, step: 1
1370 12:29:15.887344
1371 12:29:15.889945 RX Delay -95 -> 252, step: 8
1372 12:29:15.896752 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1373 12:29:15.900590 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1374 12:29:15.903646 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1375 12:29:15.906643 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1376 12:29:15.910162 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1377 12:29:15.916660 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1378 12:29:15.920187 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1379 12:29:15.923577 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1380 12:29:15.926833 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1381 12:29:15.929803 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1382 12:29:15.936478 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1383 12:29:15.939976 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1384 12:29:15.943307 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1385 12:29:15.946531 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1386 12:29:15.953315 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1387 12:29:15.956710 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1388 12:29:15.956833 ==
1389 12:29:15.959977 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 12:29:15.963336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 12:29:15.963450 ==
1392 12:29:15.966751 DQS Delay:
1393 12:29:15.966860 DQS0 = 0, DQS1 = 0
1394 12:29:15.966955 DQM Delay:
1395 12:29:15.969939 DQM0 = 91, DQM1 = 82
1396 12:29:15.970047 DQ Delay:
1397 12:29:15.973349 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1398 12:29:15.976671 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1399 12:29:15.980133 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1400 12:29:15.983068 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1401 12:29:15.983180
1402 12:29:15.983276
1403 12:29:15.993397 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
1404 12:29:15.993540 CH0 RK1: MR19=606, MR18=3D18
1405 12:29:15.999764 CH0_RK1: MR19=0x606, MR18=0x3D18, DQSOSC=394, MR23=63, INC=95, DEC=63
1406 12:29:16.003115 [RxdqsGatingPostProcess] freq 800
1407 12:29:16.009865 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1408 12:29:16.013096 Pre-setting of DQS Precalculation
1409 12:29:16.016610 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1410 12:29:16.016744 ==
1411 12:29:16.019729 Dram Type= 6, Freq= 0, CH_1, rank 0
1412 12:29:16.026852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 12:29:16.026965 ==
1414 12:29:16.029716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1415 12:29:16.036227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1416 12:29:16.045432 [CA 0] Center 36 (6~67) winsize 62
1417 12:29:16.049022 [CA 1] Center 36 (6~67) winsize 62
1418 12:29:16.052355 [CA 2] Center 34 (4~65) winsize 62
1419 12:29:16.055372 [CA 3] Center 34 (4~65) winsize 62
1420 12:29:16.058832 [CA 4] Center 34 (4~65) winsize 62
1421 12:29:16.062097 [CA 5] Center 33 (3~64) winsize 62
1422 12:29:16.062182
1423 12:29:16.065720 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1424 12:29:16.065837
1425 12:29:16.068699 [CATrainingPosCal] consider 1 rank data
1426 12:29:16.072043 u2DelayCellTimex100 = 270/100 ps
1427 12:29:16.075284 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1428 12:29:16.081799 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1429 12:29:16.085397 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 12:29:16.088675 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1431 12:29:16.091714 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1432 12:29:16.095136 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1433 12:29:16.095230
1434 12:29:16.098497 CA PerBit enable=1, Macro0, CA PI delay=33
1435 12:29:16.098605
1436 12:29:16.102002 [CBTSetCACLKResult] CA Dly = 33
1437 12:29:16.102097 CS Dly: 5 (0~36)
1438 12:29:16.105384 ==
1439 12:29:16.108312 Dram Type= 6, Freq= 0, CH_1, rank 1
1440 12:29:16.111656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 12:29:16.111752 ==
1442 12:29:16.114923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 12:29:16.121743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 12:29:16.131727 [CA 0] Center 36 (6~67) winsize 62
1445 12:29:16.135035 [CA 1] Center 37 (6~68) winsize 63
1446 12:29:16.138553 [CA 2] Center 35 (5~66) winsize 62
1447 12:29:16.141926 [CA 3] Center 34 (4~65) winsize 62
1448 12:29:16.145172 [CA 4] Center 35 (5~65) winsize 61
1449 12:29:16.148560 [CA 5] Center 34 (4~65) winsize 62
1450 12:29:16.148646
1451 12:29:16.151841 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1452 12:29:16.151947
1453 12:29:16.155097 [CATrainingPosCal] consider 2 rank data
1454 12:29:16.158346 u2DelayCellTimex100 = 270/100 ps
1455 12:29:16.161735 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 12:29:16.164671 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 12:29:16.172251 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1458 12:29:16.175656 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 12:29:16.179398 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1460 12:29:16.183120 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1461 12:29:16.183226
1462 12:29:16.186604 CA PerBit enable=1, Macro0, CA PI delay=34
1463 12:29:16.186702
1464 12:29:16.186790 [CBTSetCACLKResult] CA Dly = 34
1465 12:29:16.190101 CS Dly: 6 (0~38)
1466 12:29:16.190194
1467 12:29:16.194102 ----->DramcWriteLeveling(PI) begin...
1468 12:29:16.194198 ==
1469 12:29:16.197540 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 12:29:16.201448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 12:29:16.201551 ==
1472 12:29:16.204911 Write leveling (Byte 0): 28 => 28
1473 12:29:16.208611 Write leveling (Byte 1): 28 => 28
1474 12:29:16.208744 DramcWriteLeveling(PI) end<-----
1475 12:29:16.208890
1476 12:29:16.212108 ==
1477 12:29:16.215498 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 12:29:16.218849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 12:29:16.218947 ==
1480 12:29:16.221815 [Gating] SW mode calibration
1481 12:29:16.228572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1482 12:29:16.231793 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1483 12:29:16.238315 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1484 12:29:16.241749 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1485 12:29:16.245237 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:29:16.251845 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:29:16.255099 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:29:16.258391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:29:16.264809 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:29:16.268301 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:29:16.271733 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:29:16.278471 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:29:16.281663 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:29:16.285005 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:29:16.291601 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 12:29:16.295126 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:29:16.298023 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:29:16.304504 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:29:16.307968 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1500 12:29:16.311849 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1501 12:29:16.318069 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:29:16.321221 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:29:16.324635 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:29:16.331492 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:29:16.334823 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:29:16.338108 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:29:16.341307 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:29:16.347937 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1509 12:29:16.351410 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1510 12:29:16.354587 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 12:29:16.361372 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 12:29:16.364602 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 12:29:16.367666 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 12:29:16.374625 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 12:29:16.377763 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1516 12:29:16.381147 0 10 4 | B1->B0 | 2828 2a2a | 1 1 | (0 1) (1 1)
1517 12:29:16.387697 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:29:16.391028 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:29:16.394357 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:29:16.401258 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:29:16.404650 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:29:16.407572 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:29:16.414554 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1524 12:29:16.417852 0 11 4 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
1525 12:29:16.421232 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1526 12:29:16.427778 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 12:29:16.430729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 12:29:16.434039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 12:29:16.440968 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 12:29:16.444274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 12:29:16.447356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 12:29:16.454080 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1533 12:29:16.457479 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 12:29:16.460449 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 12:29:16.467543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 12:29:16.470655 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 12:29:16.474071 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 12:29:16.480753 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 12:29:16.484075 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 12:29:16.487023 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 12:29:16.494040 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 12:29:16.497382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 12:29:16.500384 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 12:29:16.503897 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 12:29:16.510210 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 12:29:16.513691 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 12:29:16.517008 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 12:29:16.523718 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1549 12:29:16.527012 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1550 12:29:16.530307 Total UI for P1: 0, mck2ui 16
1551 12:29:16.533751 best dqsien dly found for B0: ( 0, 14, 4)
1552 12:29:16.537067 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:29:16.540368 Total UI for P1: 0, mck2ui 16
1554 12:29:16.543835 best dqsien dly found for B1: ( 0, 14, 8)
1555 12:29:16.547219 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1556 12:29:16.550176 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1557 12:29:16.553394
1558 12:29:16.556853 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1559 12:29:16.560477 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1560 12:29:16.563782 [Gating] SW calibration Done
1561 12:29:16.563921 ==
1562 12:29:16.566700 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 12:29:16.570522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 12:29:16.570619 ==
1565 12:29:16.570687 RX Vref Scan: 0
1566 12:29:16.570750
1567 12:29:16.573388 RX Vref 0 -> 0, step: 1
1568 12:29:16.573477
1569 12:29:16.576850 RX Delay -130 -> 252, step: 16
1570 12:29:16.580263 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1571 12:29:16.583212 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1572 12:29:16.589875 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1573 12:29:16.593222 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1574 12:29:16.596587 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1575 12:29:16.599779 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1576 12:29:16.603617 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1577 12:29:16.610011 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1578 12:29:16.613433 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1579 12:29:16.616286 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1580 12:29:16.619563 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1581 12:29:16.622918 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1582 12:29:16.629694 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1583 12:29:16.632972 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1584 12:29:16.636373 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1585 12:29:16.639754 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1586 12:29:16.639851 ==
1587 12:29:16.642911 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 12:29:16.649814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 12:29:16.649928 ==
1590 12:29:16.650009 DQS Delay:
1591 12:29:16.653275 DQS0 = 0, DQS1 = 0
1592 12:29:16.653366 DQM Delay:
1593 12:29:16.653434 DQM0 = 87, DQM1 = 80
1594 12:29:16.656305 DQ Delay:
1595 12:29:16.659675 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1596 12:29:16.663005 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1597 12:29:16.666115 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1598 12:29:16.669303 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1599 12:29:16.669401
1600 12:29:16.669502
1601 12:29:16.669595 ==
1602 12:29:16.672904 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 12:29:16.676375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 12:29:16.676497 ==
1605 12:29:16.676596
1606 12:29:16.676688
1607 12:29:16.679323 TX Vref Scan disable
1608 12:29:16.682698 == TX Byte 0 ==
1609 12:29:16.686274 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 12:29:16.689145 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 12:29:16.692587 == TX Byte 1 ==
1612 12:29:16.695860 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1613 12:29:16.699177 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1614 12:29:16.699275 ==
1615 12:29:16.702451 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 12:29:16.705750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 12:29:16.709230 ==
1618 12:29:16.720324 TX Vref=22, minBit 10, minWin=27, winSum=450
1619 12:29:16.723779 TX Vref=24, minBit 15, minWin=27, winSum=456
1620 12:29:16.726719 TX Vref=26, minBit 15, minWin=27, winSum=457
1621 12:29:16.730119 TX Vref=28, minBit 15, minWin=27, winSum=456
1622 12:29:16.733467 TX Vref=30, minBit 15, minWin=27, winSum=458
1623 12:29:16.740435 TX Vref=32, minBit 8, minWin=28, winSum=458
1624 12:29:16.743397 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1625 12:29:16.743501
1626 12:29:16.746694 Final TX Range 1 Vref 32
1627 12:29:16.746786
1628 12:29:16.746854 ==
1629 12:29:16.750200 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 12:29:16.753590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 12:29:16.753682 ==
1632 12:29:16.757091
1633 12:29:16.757183
1634 12:29:16.757251 TX Vref Scan disable
1635 12:29:16.760498 == TX Byte 0 ==
1636 12:29:16.763898 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1637 12:29:16.770590 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1638 12:29:16.770707 == TX Byte 1 ==
1639 12:29:16.773463 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1640 12:29:16.780019 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1641 12:29:16.780132
1642 12:29:16.780201 [DATLAT]
1643 12:29:16.780265 Freq=800, CH1 RK0
1644 12:29:16.780327
1645 12:29:16.783662 DATLAT Default: 0xa
1646 12:29:16.783754 0, 0xFFFF, sum = 0
1647 12:29:16.786907 1, 0xFFFF, sum = 0
1648 12:29:16.790308 2, 0xFFFF, sum = 0
1649 12:29:16.790400 3, 0xFFFF, sum = 0
1650 12:29:16.793277 4, 0xFFFF, sum = 0
1651 12:29:16.793368 5, 0xFFFF, sum = 0
1652 12:29:16.796675 6, 0xFFFF, sum = 0
1653 12:29:16.796777 7, 0xFFFF, sum = 0
1654 12:29:16.800066 8, 0xFFFF, sum = 0
1655 12:29:16.800157 9, 0x0, sum = 1
1656 12:29:16.803286 10, 0x0, sum = 2
1657 12:29:16.803379 11, 0x0, sum = 3
1658 12:29:16.803450 12, 0x0, sum = 4
1659 12:29:16.806635 best_step = 10
1660 12:29:16.806738
1661 12:29:16.806820 ==
1662 12:29:16.810305 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 12:29:16.813281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 12:29:16.813390 ==
1665 12:29:16.816627 RX Vref Scan: 1
1666 12:29:16.816755
1667 12:29:16.820033 Set Vref Range= 32 -> 127
1668 12:29:16.820119
1669 12:29:16.820233 RX Vref 32 -> 127, step: 1
1670 12:29:16.820327
1671 12:29:16.823435 RX Delay -95 -> 252, step: 8
1672 12:29:16.823559
1673 12:29:16.826809 Set Vref, RX VrefLevel [Byte0]: 32
1674 12:29:16.830248 [Byte1]: 32
1675 12:29:16.830338
1676 12:29:16.833274 Set Vref, RX VrefLevel [Byte0]: 33
1677 12:29:16.836563 [Byte1]: 33
1678 12:29:16.840783
1679 12:29:16.840894 Set Vref, RX VrefLevel [Byte0]: 34
1680 12:29:16.844198 [Byte1]: 34
1681 12:29:16.848579
1682 12:29:16.848698 Set Vref, RX VrefLevel [Byte0]: 35
1683 12:29:16.851807 [Byte1]: 35
1684 12:29:16.855791
1685 12:29:16.855880 Set Vref, RX VrefLevel [Byte0]: 36
1686 12:29:16.859093 [Byte1]: 36
1687 12:29:16.863625
1688 12:29:16.863749 Set Vref, RX VrefLevel [Byte0]: 37
1689 12:29:16.866831 [Byte1]: 37
1690 12:29:16.871088
1691 12:29:16.871272 Set Vref, RX VrefLevel [Byte0]: 38
1692 12:29:16.874509 [Byte1]: 38
1693 12:29:16.878926
1694 12:29:16.879025 Set Vref, RX VrefLevel [Byte0]: 39
1695 12:29:16.882217 [Byte1]: 39
1696 12:29:16.886318
1697 12:29:16.886473 Set Vref, RX VrefLevel [Byte0]: 40
1698 12:29:16.889892 [Byte1]: 40
1699 12:29:16.893911
1700 12:29:16.894025 Set Vref, RX VrefLevel [Byte0]: 41
1701 12:29:16.897320 [Byte1]: 41
1702 12:29:16.901565
1703 12:29:16.901677 Set Vref, RX VrefLevel [Byte0]: 42
1704 12:29:16.904971 [Byte1]: 42
1705 12:29:16.909235
1706 12:29:16.909349 Set Vref, RX VrefLevel [Byte0]: 43
1707 12:29:16.912494 [Byte1]: 43
1708 12:29:16.916911
1709 12:29:16.917043 Set Vref, RX VrefLevel [Byte0]: 44
1710 12:29:16.919890 [Byte1]: 44
1711 12:29:16.924298
1712 12:29:16.924413 Set Vref, RX VrefLevel [Byte0]: 45
1713 12:29:16.927832 [Byte1]: 45
1714 12:29:16.931696
1715 12:29:16.931809 Set Vref, RX VrefLevel [Byte0]: 46
1716 12:29:16.935166 [Byte1]: 46
1717 12:29:16.939460
1718 12:29:16.939613 Set Vref, RX VrefLevel [Byte0]: 47
1719 12:29:16.942826 [Byte1]: 47
1720 12:29:16.946994
1721 12:29:16.947114 Set Vref, RX VrefLevel [Byte0]: 48
1722 12:29:16.950437 [Byte1]: 48
1723 12:29:16.954635
1724 12:29:16.954752 Set Vref, RX VrefLevel [Byte0]: 49
1725 12:29:16.958078 [Byte1]: 49
1726 12:29:16.962460
1727 12:29:16.962561 Set Vref, RX VrefLevel [Byte0]: 50
1728 12:29:16.965431 [Byte1]: 50
1729 12:29:16.969838
1730 12:29:16.969958 Set Vref, RX VrefLevel [Byte0]: 51
1731 12:29:16.973141 [Byte1]: 51
1732 12:29:16.977356
1733 12:29:16.977457 Set Vref, RX VrefLevel [Byte0]: 52
1734 12:29:16.980936 [Byte1]: 52
1735 12:29:16.985280
1736 12:29:16.985367 Set Vref, RX VrefLevel [Byte0]: 53
1737 12:29:16.988350 [Byte1]: 53
1738 12:29:16.992558
1739 12:29:16.992688 Set Vref, RX VrefLevel [Byte0]: 54
1740 12:29:16.996214 [Byte1]: 54
1741 12:29:17.000261
1742 12:29:17.000376 Set Vref, RX VrefLevel [Byte0]: 55
1743 12:29:17.003422 [Byte1]: 55
1744 12:29:17.007726
1745 12:29:17.007856 Set Vref, RX VrefLevel [Byte0]: 56
1746 12:29:17.011397 [Byte1]: 56
1747 12:29:17.015567
1748 12:29:17.015679 Set Vref, RX VrefLevel [Byte0]: 57
1749 12:29:17.018569 [Byte1]: 57
1750 12:29:17.022971
1751 12:29:17.023087 Set Vref, RX VrefLevel [Byte0]: 58
1752 12:29:17.026469 [Byte1]: 58
1753 12:29:17.030912
1754 12:29:17.031028 Set Vref, RX VrefLevel [Byte0]: 59
1755 12:29:17.033814 [Byte1]: 59
1756 12:29:17.038198
1757 12:29:17.038315 Set Vref, RX VrefLevel [Byte0]: 60
1758 12:29:17.041675 [Byte1]: 60
1759 12:29:17.046049
1760 12:29:17.046163 Set Vref, RX VrefLevel [Byte0]: 61
1761 12:29:17.049440 [Byte1]: 61
1762 12:29:17.053641
1763 12:29:17.053736 Set Vref, RX VrefLevel [Byte0]: 62
1764 12:29:17.056579 [Byte1]: 62
1765 12:29:17.061008
1766 12:29:17.061105 Set Vref, RX VrefLevel [Byte0]: 63
1767 12:29:17.064599 [Byte1]: 63
1768 12:29:17.068495
1769 12:29:17.068590 Set Vref, RX VrefLevel [Byte0]: 64
1770 12:29:17.071907 [Byte1]: 64
1771 12:29:17.076297
1772 12:29:17.076398 Set Vref, RX VrefLevel [Byte0]: 65
1773 12:29:17.079585 [Byte1]: 65
1774 12:29:17.083900
1775 12:29:17.083991 Set Vref, RX VrefLevel [Byte0]: 66
1776 12:29:17.086850 [Byte1]: 66
1777 12:29:17.091279
1778 12:29:17.091368 Set Vref, RX VrefLevel [Byte0]: 67
1779 12:29:17.094607 [Byte1]: 67
1780 12:29:17.099166
1781 12:29:17.099261 Set Vref, RX VrefLevel [Byte0]: 68
1782 12:29:17.102403 [Byte1]: 68
1783 12:29:17.106582
1784 12:29:17.106673 Set Vref, RX VrefLevel [Byte0]: 69
1785 12:29:17.109746 [Byte1]: 69
1786 12:29:17.114033
1787 12:29:17.114121 Set Vref, RX VrefLevel [Byte0]: 70
1788 12:29:17.117307 [Byte1]: 70
1789 12:29:17.121552
1790 12:29:17.121646 Set Vref, RX VrefLevel [Byte0]: 71
1791 12:29:17.125038 [Byte1]: 71
1792 12:29:17.129599
1793 12:29:17.129691 Set Vref, RX VrefLevel [Byte0]: 72
1794 12:29:17.132539 [Byte1]: 72
1795 12:29:17.136879
1796 12:29:17.136985 Set Vref, RX VrefLevel [Byte0]: 73
1797 12:29:17.140315 [Byte1]: 73
1798 12:29:17.144724
1799 12:29:17.144855 Set Vref, RX VrefLevel [Byte0]: 74
1800 12:29:17.148100 [Byte1]: 74
1801 12:29:17.152012
1802 12:29:17.152097 Set Vref, RX VrefLevel [Byte0]: 75
1803 12:29:17.155398 [Byte1]: 75
1804 12:29:17.159791
1805 12:29:17.159878 Set Vref, RX VrefLevel [Byte0]: 76
1806 12:29:17.163020 [Byte1]: 76
1807 12:29:17.167625
1808 12:29:17.167757 Set Vref, RX VrefLevel [Byte0]: 77
1809 12:29:17.170526 [Byte1]: 77
1810 12:29:17.175106
1811 12:29:17.175200 Set Vref, RX VrefLevel [Byte0]: 78
1812 12:29:17.178516 [Byte1]: 78
1813 12:29:17.182743
1814 12:29:17.182828 Final RX Vref Byte 0 = 51 to rank0
1815 12:29:17.186088 Final RX Vref Byte 1 = 62 to rank0
1816 12:29:17.189042 Final RX Vref Byte 0 = 51 to rank1
1817 12:29:17.192452 Final RX Vref Byte 1 = 62 to rank1==
1818 12:29:17.195713 Dram Type= 6, Freq= 0, CH_1, rank 0
1819 12:29:17.202399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 12:29:17.202517 ==
1821 12:29:17.202590 DQS Delay:
1822 12:29:17.202653 DQS0 = 0, DQS1 = 0
1823 12:29:17.206043 DQM Delay:
1824 12:29:17.206134 DQM0 = 91, DQM1 = 82
1825 12:29:17.209240 DQ Delay:
1826 12:29:17.212427 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1827 12:29:17.215593 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1828 12:29:17.219082 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1829 12:29:17.222418 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1830 12:29:17.222512
1831 12:29:17.222581
1832 12:29:17.228946 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1833 12:29:17.232468 CH1 RK0: MR19=606, MR18=2D4A
1834 12:29:17.238919 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1835 12:29:17.239035
1836 12:29:17.242381 ----->DramcWriteLeveling(PI) begin...
1837 12:29:17.242472 ==
1838 12:29:17.245772 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 12:29:17.249205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 12:29:17.249300 ==
1841 12:29:17.252137 Write leveling (Byte 0): 27 => 27
1842 12:29:17.255553 Write leveling (Byte 1): 31 => 31
1843 12:29:17.258791 DramcWriteLeveling(PI) end<-----
1844 12:29:17.258902
1845 12:29:17.258986 ==
1846 12:29:17.262387 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 12:29:17.265356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 12:29:17.265448 ==
1849 12:29:17.268651 [Gating] SW mode calibration
1850 12:29:17.275514 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1851 12:29:17.282322 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1852 12:29:17.285694 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1853 12:29:17.292010 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1854 12:29:17.295351 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1855 12:29:17.298696 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:29:17.305534 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:29:17.308689 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:29:17.311994 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:29:17.315311 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:29:17.321986 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:29:17.325069 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:29:17.328650 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:29:17.335433 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:29:17.338462 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:29:17.341810 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:29:17.348631 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:29:17.351592 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:29:17.355059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1869 12:29:17.361704 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1870 12:29:17.365084 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:29:17.368503 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:29:17.375081 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:29:17.378137 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:29:17.381673 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:29:17.388393 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:29:17.391349 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:29:17.394691 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1878 12:29:17.401660 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1879 12:29:17.404672 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 12:29:17.408236 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 12:29:17.414825 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 12:29:17.418036 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 12:29:17.421250 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 12:29:17.428190 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1885 12:29:17.431269 0 10 4 | B1->B0 | 2f2f 3131 | 1 0 | (0 1) (0 1)
1886 12:29:17.434767 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:29:17.441018 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:29:17.444443 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:29:17.447808 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:29:17.454229 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:29:17.457685 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:29:17.461003 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:29:17.468061 0 11 4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
1894 12:29:17.471073 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1895 12:29:17.474448 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 12:29:17.477647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 12:29:17.484579 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 12:29:17.487571 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 12:29:17.491015 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 12:29:17.497698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 12:29:17.501029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1902 12:29:17.504462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 12:29:17.511285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 12:29:17.514196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 12:29:17.517634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 12:29:17.524031 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 12:29:17.527661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 12:29:17.530941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 12:29:17.537375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 12:29:17.540707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 12:29:17.544170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 12:29:17.551055 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:29:17.554040 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:29:17.557541 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:29:17.564179 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:29:17.567545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:29:17.570784 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 12:29:17.574222 Total UI for P1: 0, mck2ui 16
1919 12:29:17.577710 best dqsien dly found for B0: ( 0, 14, 2)
1920 12:29:17.580853 Total UI for P1: 0, mck2ui 16
1921 12:29:17.584294 best dqsien dly found for B1: ( 0, 14, 2)
1922 12:29:17.587208 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1923 12:29:17.590744 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1924 12:29:17.590870
1925 12:29:17.594112 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1926 12:29:17.600851 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1927 12:29:17.600984 [Gating] SW calibration Done
1928 12:29:17.601084 ==
1929 12:29:17.603737 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 12:29:17.610510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 12:29:17.610622 ==
1932 12:29:17.610694 RX Vref Scan: 0
1933 12:29:17.610759
1934 12:29:17.614056 RX Vref 0 -> 0, step: 1
1935 12:29:17.614146
1936 12:29:17.617535 RX Delay -130 -> 252, step: 16
1937 12:29:17.620540 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1938 12:29:17.623839 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1939 12:29:17.627018 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1940 12:29:17.633734 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1941 12:29:17.637428 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1942 12:29:17.640617 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1943 12:29:17.643893 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1944 12:29:17.647114 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1945 12:29:17.653880 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1946 12:29:17.656885 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1947 12:29:17.660289 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1948 12:29:17.663692 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1949 12:29:17.667076 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1950 12:29:17.673686 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1951 12:29:17.677007 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1952 12:29:17.680356 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1953 12:29:17.680483 ==
1954 12:29:17.683604 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 12:29:17.686984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 12:29:17.687124 ==
1957 12:29:17.690369 DQS Delay:
1958 12:29:17.690494 DQS0 = 0, DQS1 = 0
1959 12:29:17.693805 DQM Delay:
1960 12:29:17.693895 DQM0 = 91, DQM1 = 87
1961 12:29:17.694005 DQ Delay:
1962 12:29:17.697162 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1963 12:29:17.700127 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1964 12:29:17.703782 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1965 12:29:17.706810 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1966 12:29:17.706945
1967 12:29:17.710302
1968 12:29:17.710417 ==
1969 12:29:17.713652 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 12:29:17.717144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 12:29:17.717240 ==
1972 12:29:17.717311
1973 12:29:17.717374
1974 12:29:17.720081 TX Vref Scan disable
1975 12:29:17.720195 == TX Byte 0 ==
1976 12:29:17.727056 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 12:29:17.729975 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 12:29:17.730090 == TX Byte 1 ==
1979 12:29:17.736702 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1980 12:29:17.740426 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1981 12:29:17.740551 ==
1982 12:29:17.743270 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 12:29:17.746716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 12:29:17.746829 ==
1985 12:29:17.760416 TX Vref=22, minBit 13, minWin=27, winSum=453
1986 12:29:17.763766 TX Vref=24, minBit 8, minWin=27, winSum=454
1987 12:29:17.767210 TX Vref=26, minBit 13, minWin=27, winSum=454
1988 12:29:17.770253 TX Vref=28, minBit 13, minWin=27, winSum=457
1989 12:29:17.773649 TX Vref=30, minBit 13, minWin=27, winSum=457
1990 12:29:17.780195 TX Vref=32, minBit 8, minWin=28, winSum=459
1991 12:29:17.783594 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
1992 12:29:17.783699
1993 12:29:17.786878 Final TX Range 1 Vref 32
1994 12:29:17.786998
1995 12:29:17.787133 ==
1996 12:29:17.790173 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 12:29:17.793587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 12:29:17.797158 ==
1999 12:29:17.797288
2000 12:29:17.797383
2001 12:29:17.797475 TX Vref Scan disable
2002 12:29:17.800570 == TX Byte 0 ==
2003 12:29:17.804061 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2004 12:29:17.810524 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2005 12:29:17.810665 == TX Byte 1 ==
2006 12:29:17.813913 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2007 12:29:17.820859 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2008 12:29:17.820977
2009 12:29:17.821049 [DATLAT]
2010 12:29:17.821115 Freq=800, CH1 RK1
2011 12:29:17.821178
2012 12:29:17.823803 DATLAT Default: 0xa
2013 12:29:17.823878 0, 0xFFFF, sum = 0
2014 12:29:17.827230 1, 0xFFFF, sum = 0
2015 12:29:17.830627 2, 0xFFFF, sum = 0
2016 12:29:17.830751 3, 0xFFFF, sum = 0
2017 12:29:17.833648 4, 0xFFFF, sum = 0
2018 12:29:17.833741 5, 0xFFFF, sum = 0
2019 12:29:17.837009 6, 0xFFFF, sum = 0
2020 12:29:17.837130 7, 0xFFFF, sum = 0
2021 12:29:17.840330 8, 0xFFFF, sum = 0
2022 12:29:17.840453 9, 0x0, sum = 1
2023 12:29:17.843542 10, 0x0, sum = 2
2024 12:29:17.843659 11, 0x0, sum = 3
2025 12:29:17.843761 12, 0x0, sum = 4
2026 12:29:17.847124 best_step = 10
2027 12:29:17.847248
2028 12:29:17.847347 ==
2029 12:29:17.850270 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 12:29:17.853566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 12:29:17.853683 ==
2032 12:29:17.856713 RX Vref Scan: 0
2033 12:29:17.856825
2034 12:29:17.860319 RX Vref 0 -> 0, step: 1
2035 12:29:17.860440
2036 12:29:17.860539 RX Delay -79 -> 252, step: 8
2037 12:29:17.867520 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2038 12:29:17.870651 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2039 12:29:17.873998 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2040 12:29:17.877433 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2041 12:29:17.880741 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2042 12:29:17.887346 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2043 12:29:17.890712 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2044 12:29:17.893947 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2045 12:29:17.897328 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2046 12:29:17.900328 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2047 12:29:17.907101 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2048 12:29:17.910487 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2049 12:29:17.913587 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2050 12:29:17.917059 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2051 12:29:17.920380 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2052 12:29:17.926703 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2053 12:29:17.926820 ==
2054 12:29:17.930202 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 12:29:17.933611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 12:29:17.933704 ==
2057 12:29:17.933775 DQS Delay:
2058 12:29:17.937037 DQS0 = 0, DQS1 = 0
2059 12:29:17.937118 DQM Delay:
2060 12:29:17.940028 DQM0 = 91, DQM1 = 84
2061 12:29:17.940105 DQ Delay:
2062 12:29:17.943380 DQ0 =92, DQ1 =88, DQ2 =80, DQ3 =88
2063 12:29:17.946616 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2064 12:29:17.949927 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2065 12:29:17.953163 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2066 12:29:17.953289
2067 12:29:17.953388
2068 12:29:17.963180 [DQSOSCAuto] RK1, (LSB)MR18= 0x390f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2069 12:29:17.963322 CH1 RK1: MR19=606, MR18=390F
2070 12:29:17.969994 CH1_RK1: MR19=0x606, MR18=0x390F, DQSOSC=395, MR23=63, INC=94, DEC=63
2071 12:29:17.973362 [RxdqsGatingPostProcess] freq 800
2072 12:29:17.979737 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2073 12:29:17.983069 Pre-setting of DQS Precalculation
2074 12:29:17.986314 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2075 12:29:17.993408 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2076 12:29:18.003028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2077 12:29:18.003199
2078 12:29:18.003303
2079 12:29:18.006579 [Calibration Summary] 1600 Mbps
2080 12:29:18.006673 CH 0, Rank 0
2081 12:29:18.010095 SW Impedance : PASS
2082 12:29:18.010189 DUTY Scan : NO K
2083 12:29:18.013008 ZQ Calibration : PASS
2084 12:29:18.016620 Jitter Meter : NO K
2085 12:29:18.016742 CBT Training : PASS
2086 12:29:18.019496 Write leveling : PASS
2087 12:29:18.019611 RX DQS gating : PASS
2088 12:29:18.023005 RX DQ/DQS(RDDQC) : PASS
2089 12:29:18.026566 TX DQ/DQS : PASS
2090 12:29:18.026680 RX DATLAT : PASS
2091 12:29:18.029493 RX DQ/DQS(Engine): PASS
2092 12:29:18.032896 TX OE : NO K
2093 12:29:18.033027 All Pass.
2094 12:29:18.033122
2095 12:29:18.033214 CH 0, Rank 1
2096 12:29:18.036391 SW Impedance : PASS
2097 12:29:18.039893 DUTY Scan : NO K
2098 12:29:18.040060 ZQ Calibration : PASS
2099 12:29:18.043271 Jitter Meter : NO K
2100 12:29:18.046331 CBT Training : PASS
2101 12:29:18.046439 Write leveling : PASS
2102 12:29:18.049739 RX DQS gating : PASS
2103 12:29:18.052977 RX DQ/DQS(RDDQC) : PASS
2104 12:29:18.053077 TX DQ/DQS : PASS
2105 12:29:18.056423 RX DATLAT : PASS
2106 12:29:18.059372 RX DQ/DQS(Engine): PASS
2107 12:29:18.059466 TX OE : NO K
2108 12:29:18.059535 All Pass.
2109 12:29:18.062854
2110 12:29:18.062969 CH 1, Rank 0
2111 12:29:18.066279 SW Impedance : PASS
2112 12:29:18.066381 DUTY Scan : NO K
2113 12:29:18.069376 ZQ Calibration : PASS
2114 12:29:18.072914 Jitter Meter : NO K
2115 12:29:18.073009 CBT Training : PASS
2116 12:29:18.076337 Write leveling : PASS
2117 12:29:18.076431 RX DQS gating : PASS
2118 12:29:18.079593 RX DQ/DQS(RDDQC) : PASS
2119 12:29:18.082905 TX DQ/DQS : PASS
2120 12:29:18.082995 RX DATLAT : PASS
2121 12:29:18.086229 RX DQ/DQS(Engine): PASS
2122 12:29:18.089474 TX OE : NO K
2123 12:29:18.089582 All Pass.
2124 12:29:18.089687
2125 12:29:18.089788 CH 1, Rank 1
2126 12:29:18.092997 SW Impedance : PASS
2127 12:29:18.096412 DUTY Scan : NO K
2128 12:29:18.096519 ZQ Calibration : PASS
2129 12:29:18.099750 Jitter Meter : NO K
2130 12:29:18.103102 CBT Training : PASS
2131 12:29:18.103216 Write leveling : PASS
2132 12:29:18.106029 RX DQS gating : PASS
2133 12:29:18.109378 RX DQ/DQS(RDDQC) : PASS
2134 12:29:18.109496 TX DQ/DQS : PASS
2135 12:29:18.112754 RX DATLAT : PASS
2136 12:29:18.112890 RX DQ/DQS(Engine): PASS
2137 12:29:18.116331 TX OE : NO K
2138 12:29:18.116446 All Pass.
2139 12:29:18.116542
2140 12:29:18.119572 DramC Write-DBI off
2141 12:29:18.122731 PER_BANK_REFRESH: Hybrid Mode
2142 12:29:18.122850 TX_TRACKING: ON
2143 12:29:18.126120 [GetDramInforAfterCalByMRR] Vendor 6.
2144 12:29:18.129553 [GetDramInforAfterCalByMRR] Revision 606.
2145 12:29:18.132936 [GetDramInforAfterCalByMRR] Revision 2 0.
2146 12:29:18.136369 MR0 0x3b3b
2147 12:29:18.136466 MR8 0x5151
2148 12:29:18.139730 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2149 12:29:18.139820
2150 12:29:18.142716 MR0 0x3b3b
2151 12:29:18.142831 MR8 0x5151
2152 12:29:18.146085 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2153 12:29:18.146196
2154 12:29:18.156218 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2155 12:29:18.159651 [FAST_K] Save calibration result to emmc
2156 12:29:18.162701 [FAST_K] Save calibration result to emmc
2157 12:29:18.166002 dram_init: config_dvfs: 1
2158 12:29:18.169313 dramc_set_vcore_voltage set vcore to 662500
2159 12:29:18.169412 Read voltage for 1200, 2
2160 12:29:18.172596 Vio18 = 0
2161 12:29:18.172713 Vcore = 662500
2162 12:29:18.172853 Vdram = 0
2163 12:29:18.176155 Vddq = 0
2164 12:29:18.176245 Vmddr = 0
2165 12:29:18.182467 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2166 12:29:18.185793 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2167 12:29:18.189029 MEM_TYPE=3, freq_sel=15
2168 12:29:18.192379 sv_algorithm_assistance_LP4_1600
2169 12:29:18.195564 ============ PULL DRAM RESETB DOWN ============
2170 12:29:18.199241 ========== PULL DRAM RESETB DOWN end =========
2171 12:29:18.205609 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2172 12:29:18.208941 ===================================
2173 12:29:18.209039 LPDDR4 DRAM CONFIGURATION
2174 12:29:18.212336 ===================================
2175 12:29:18.215795 EX_ROW_EN[0] = 0x0
2176 12:29:18.218821 EX_ROW_EN[1] = 0x0
2177 12:29:18.218932 LP4Y_EN = 0x0
2178 12:29:18.222181 WORK_FSP = 0x0
2179 12:29:18.222289 WL = 0x4
2180 12:29:18.225610 RL = 0x4
2181 12:29:18.225692 BL = 0x2
2182 12:29:18.228953 RPST = 0x0
2183 12:29:18.229037 RD_PRE = 0x0
2184 12:29:18.232389 WR_PRE = 0x1
2185 12:29:18.232497 WR_PST = 0x0
2186 12:29:18.235854 DBI_WR = 0x0
2187 12:29:18.235945 DBI_RD = 0x0
2188 12:29:18.239174 OTF = 0x1
2189 12:29:18.242015 ===================================
2190 12:29:18.245406 ===================================
2191 12:29:18.245510 ANA top config
2192 12:29:18.248856 ===================================
2193 12:29:18.252287 DLL_ASYNC_EN = 0
2194 12:29:18.255818 ALL_SLAVE_EN = 0
2195 12:29:18.255913 NEW_RANK_MODE = 1
2196 12:29:18.258653 DLL_IDLE_MODE = 1
2197 12:29:18.262412 LP45_APHY_COMB_EN = 1
2198 12:29:18.265427 TX_ODT_DIS = 1
2199 12:29:18.268932 NEW_8X_MODE = 1
2200 12:29:18.272303 ===================================
2201 12:29:18.272396 ===================================
2202 12:29:18.275438 data_rate = 2400
2203 12:29:18.278592 CKR = 1
2204 12:29:18.282320 DQ_P2S_RATIO = 8
2205 12:29:18.285670 ===================================
2206 12:29:18.288756 CA_P2S_RATIO = 8
2207 12:29:18.292015 DQ_CA_OPEN = 0
2208 12:29:18.295268 DQ_SEMI_OPEN = 0
2209 12:29:18.295366 CA_SEMI_OPEN = 0
2210 12:29:18.298579 CA_FULL_RATE = 0
2211 12:29:18.301825 DQ_CKDIV4_EN = 0
2212 12:29:18.305113 CA_CKDIV4_EN = 0
2213 12:29:18.308555 CA_PREDIV_EN = 0
2214 12:29:18.311901 PH8_DLY = 17
2215 12:29:18.311995 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2216 12:29:18.315418 DQ_AAMCK_DIV = 4
2217 12:29:18.318805 CA_AAMCK_DIV = 4
2218 12:29:18.321800 CA_ADMCK_DIV = 4
2219 12:29:18.325172 DQ_TRACK_CA_EN = 0
2220 12:29:18.328581 CA_PICK = 1200
2221 12:29:18.331872 CA_MCKIO = 1200
2222 12:29:18.331990 MCKIO_SEMI = 0
2223 12:29:18.335507 PLL_FREQ = 2366
2224 12:29:18.338465 DQ_UI_PI_RATIO = 32
2225 12:29:18.341789 CA_UI_PI_RATIO = 0
2226 12:29:18.345212 ===================================
2227 12:29:18.348284 ===================================
2228 12:29:18.351597 memory_type:LPDDR4
2229 12:29:18.351721 GP_NUM : 10
2230 12:29:18.355036 SRAM_EN : 1
2231 12:29:18.358496 MD32_EN : 0
2232 12:29:18.358605 ===================================
2233 12:29:18.361939 [ANA_INIT] >>>>>>>>>>>>>>
2234 12:29:18.365274 <<<<<< [CONFIGURE PHASE]: ANA_TX
2235 12:29:18.368611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2236 12:29:18.371621 ===================================
2237 12:29:18.375119 data_rate = 2400,PCW = 0X5b00
2238 12:29:18.378459 ===================================
2239 12:29:18.382047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2240 12:29:18.388456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2241 12:29:18.392126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2242 12:29:18.398050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2243 12:29:18.401531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2244 12:29:18.404654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2245 12:29:18.404799 [ANA_INIT] flow start
2246 12:29:18.407973 [ANA_INIT] PLL >>>>>>>>
2247 12:29:18.411361 [ANA_INIT] PLL <<<<<<<<
2248 12:29:18.411483 [ANA_INIT] MIDPI >>>>>>>>
2249 12:29:18.414631 [ANA_INIT] MIDPI <<<<<<<<
2250 12:29:18.418036 [ANA_INIT] DLL >>>>>>>>
2251 12:29:18.421559 [ANA_INIT] DLL <<<<<<<<
2252 12:29:18.421682 [ANA_INIT] flow end
2253 12:29:18.424948 ============ LP4 DIFF to SE enter ============
2254 12:29:18.431194 ============ LP4 DIFF to SE exit ============
2255 12:29:18.431322 [ANA_INIT] <<<<<<<<<<<<<
2256 12:29:18.434614 [Flow] Enable top DCM control >>>>>
2257 12:29:18.438306 [Flow] Enable top DCM control <<<<<
2258 12:29:18.441331 Enable DLL master slave shuffle
2259 12:29:18.448176 ==============================================================
2260 12:29:18.448320 Gating Mode config
2261 12:29:18.454616 ==============================================================
2262 12:29:18.458029 Config description:
2263 12:29:18.467757 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2264 12:29:18.474585 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2265 12:29:18.477623 SELPH_MODE 0: By rank 1: By Phase
2266 12:29:18.484598 ==============================================================
2267 12:29:18.487784 GAT_TRACK_EN = 1
2268 12:29:18.487893 RX_GATING_MODE = 2
2269 12:29:18.490969 RX_GATING_TRACK_MODE = 2
2270 12:29:18.494348 SELPH_MODE = 1
2271 12:29:18.497652 PICG_EARLY_EN = 1
2272 12:29:18.500759 VALID_LAT_VALUE = 1
2273 12:29:18.507548 ==============================================================
2274 12:29:18.510986 Enter into Gating configuration >>>>
2275 12:29:18.514206 Exit from Gating configuration <<<<
2276 12:29:18.517442 Enter into DVFS_PRE_config >>>>>
2277 12:29:18.527638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2278 12:29:18.531048 Exit from DVFS_PRE_config <<<<<
2279 12:29:18.533921 Enter into PICG configuration >>>>
2280 12:29:18.537228 Exit from PICG configuration <<<<
2281 12:29:18.540659 [RX_INPUT] configuration >>>>>
2282 12:29:18.544088 [RX_INPUT] configuration <<<<<
2283 12:29:18.547056 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2284 12:29:18.553909 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2285 12:29:18.560406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2286 12:29:18.567281 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2287 12:29:18.570630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 12:29:18.576892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 12:29:18.580364 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2290 12:29:18.586787 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2291 12:29:18.590121 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2292 12:29:18.593518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2293 12:29:18.596726 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2294 12:29:18.603527 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2295 12:29:18.606710 ===================================
2296 12:29:18.606811 LPDDR4 DRAM CONFIGURATION
2297 12:29:18.610466 ===================================
2298 12:29:18.613576 EX_ROW_EN[0] = 0x0
2299 12:29:18.616748 EX_ROW_EN[1] = 0x0
2300 12:29:18.616851 LP4Y_EN = 0x0
2301 12:29:18.620348 WORK_FSP = 0x0
2302 12:29:18.620444 WL = 0x4
2303 12:29:18.623523 RL = 0x4
2304 12:29:18.623614 BL = 0x2
2305 12:29:18.626952 RPST = 0x0
2306 12:29:18.627047 RD_PRE = 0x0
2307 12:29:18.629946 WR_PRE = 0x1
2308 12:29:18.630036 WR_PST = 0x0
2309 12:29:18.633286 DBI_WR = 0x0
2310 12:29:18.633379 DBI_RD = 0x0
2311 12:29:18.636568 OTF = 0x1
2312 12:29:18.639959 ===================================
2313 12:29:18.643267 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2314 12:29:18.646719 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2315 12:29:18.653204 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 12:29:18.656557 ===================================
2317 12:29:18.656661 LPDDR4 DRAM CONFIGURATION
2318 12:29:18.659907 ===================================
2319 12:29:18.662886 EX_ROW_EN[0] = 0x10
2320 12:29:18.666394 EX_ROW_EN[1] = 0x0
2321 12:29:18.666492 LP4Y_EN = 0x0
2322 12:29:18.669402 WORK_FSP = 0x0
2323 12:29:18.669492 WL = 0x4
2324 12:29:18.672733 RL = 0x4
2325 12:29:18.672834 BL = 0x2
2326 12:29:18.676048 RPST = 0x0
2327 12:29:18.676142 RD_PRE = 0x0
2328 12:29:18.679465 WR_PRE = 0x1
2329 12:29:18.679560 WR_PST = 0x0
2330 12:29:18.682782 DBI_WR = 0x0
2331 12:29:18.682875 DBI_RD = 0x0
2332 12:29:18.686276 OTF = 0x1
2333 12:29:18.689640 ===================================
2334 12:29:18.696040 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2335 12:29:18.696162 ==
2336 12:29:18.699202 Dram Type= 6, Freq= 0, CH_0, rank 0
2337 12:29:18.702635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2338 12:29:18.702728 ==
2339 12:29:18.705944 [Duty_Offset_Calibration]
2340 12:29:18.706031 B0:2 B1:0 CA:1
2341 12:29:18.706096
2342 12:29:18.709298 [DutyScan_Calibration_Flow] k_type=0
2343 12:29:18.719352
2344 12:29:18.719488 ==CLK 0==
2345 12:29:18.722667 Final CLK duty delay cell = -4
2346 12:29:18.725519 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2347 12:29:18.729214 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2348 12:29:18.732189 [-4] AVG Duty = 4953%(X100)
2349 12:29:18.732297
2350 12:29:18.735882 CH0 CLK Duty spec in!! Max-Min= 156%
2351 12:29:18.738801 [DutyScan_Calibration_Flow] ====Done====
2352 12:29:18.738888
2353 12:29:18.742249 [DutyScan_Calibration_Flow] k_type=1
2354 12:29:18.757762
2355 12:29:18.757914 ==DQS 0 ==
2356 12:29:18.761120 Final DQS duty delay cell = 0
2357 12:29:18.764586 [0] MAX Duty = 5187%(X100), DQS PI = 30
2358 12:29:18.768172 [0] MIN Duty = 4938%(X100), DQS PI = 0
2359 12:29:18.771020 [0] AVG Duty = 5062%(X100)
2360 12:29:18.771100
2361 12:29:18.771165 ==DQS 1 ==
2362 12:29:18.774626 Final DQS duty delay cell = -4
2363 12:29:18.778024 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2364 12:29:18.781430 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2365 12:29:18.784376 [-4] AVG Duty = 5031%(X100)
2366 12:29:18.784492
2367 12:29:18.787830 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2368 12:29:18.787923
2369 12:29:18.791294 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2370 12:29:18.794302 [DutyScan_Calibration_Flow] ====Done====
2371 12:29:18.794389
2372 12:29:18.797735 [DutyScan_Calibration_Flow] k_type=3
2373 12:29:18.814005
2374 12:29:18.814169 ==DQM 0 ==
2375 12:29:18.817166 Final DQM duty delay cell = 0
2376 12:29:18.820401 [0] MAX Duty = 5062%(X100), DQS PI = 24
2377 12:29:18.824077 [0] MIN Duty = 4844%(X100), DQS PI = 0
2378 12:29:18.824172 [0] AVG Duty = 4953%(X100)
2379 12:29:18.827252
2380 12:29:18.827342 ==DQM 1 ==
2381 12:29:18.830543 Final DQM duty delay cell = -4
2382 12:29:18.833855 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2383 12:29:18.837405 [-4] MIN Duty = 4813%(X100), DQS PI = 10
2384 12:29:18.840539 [-4] AVG Duty = 4906%(X100)
2385 12:29:18.840627
2386 12:29:18.843815 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2387 12:29:18.843908
2388 12:29:18.847304 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2389 12:29:18.850497 [DutyScan_Calibration_Flow] ====Done====
2390 12:29:18.850635
2391 12:29:18.853754 [DutyScan_Calibration_Flow] k_type=2
2392 12:29:18.870652
2393 12:29:18.870804 ==DQ 0 ==
2394 12:29:18.873993 Final DQ duty delay cell = -4
2395 12:29:18.877354 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2396 12:29:18.880812 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2397 12:29:18.884155 [-4] AVG Duty = 4968%(X100)
2398 12:29:18.884272
2399 12:29:18.884366 ==DQ 1 ==
2400 12:29:18.887626 Final DQ duty delay cell = 4
2401 12:29:18.890670 [4] MAX Duty = 5093%(X100), DQS PI = 4
2402 12:29:18.894045 [4] MIN Duty = 5031%(X100), DQS PI = 0
2403 12:29:18.894128 [4] AVG Duty = 5062%(X100)
2404 12:29:18.897437
2405 12:29:18.900961 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2406 12:29:18.901045
2407 12:29:18.904303 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2408 12:29:18.907531 [DutyScan_Calibration_Flow] ====Done====
2409 12:29:18.907640 ==
2410 12:29:18.911009 Dram Type= 6, Freq= 0, CH_1, rank 0
2411 12:29:18.914006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2412 12:29:18.914113 ==
2413 12:29:18.917542 [Duty_Offset_Calibration]
2414 12:29:18.917624 B0:0 B1:-1 CA:2
2415 12:29:18.917690
2416 12:29:18.920641 [DutyScan_Calibration_Flow] k_type=0
2417 12:29:18.930725
2418 12:29:18.930874 ==CLK 0==
2419 12:29:18.934356 Final CLK duty delay cell = 0
2420 12:29:18.937522 [0] MAX Duty = 5156%(X100), DQS PI = 16
2421 12:29:18.940703 [0] MIN Duty = 4938%(X100), DQS PI = 44
2422 12:29:18.944398 [0] AVG Duty = 5047%(X100)
2423 12:29:18.944491
2424 12:29:18.947561 CH1 CLK Duty spec in!! Max-Min= 218%
2425 12:29:18.950780 [DutyScan_Calibration_Flow] ====Done====
2426 12:29:18.950870
2427 12:29:18.954134 [DutyScan_Calibration_Flow] k_type=1
2428 12:29:18.970305
2429 12:29:18.970452 ==DQS 0 ==
2430 12:29:18.973677 Final DQS duty delay cell = 0
2431 12:29:18.976788 [0] MAX Duty = 5093%(X100), DQS PI = 24
2432 12:29:18.980234 [0] MIN Duty = 4969%(X100), DQS PI = 0
2433 12:29:18.980323 [0] AVG Duty = 5031%(X100)
2434 12:29:18.983639
2435 12:29:18.983717 ==DQS 1 ==
2436 12:29:18.987016 Final DQS duty delay cell = 0
2437 12:29:18.990212 [0] MAX Duty = 5156%(X100), DQS PI = 0
2438 12:29:18.993214 [0] MIN Duty = 4875%(X100), DQS PI = 34
2439 12:29:18.996691 [0] AVG Duty = 5015%(X100)
2440 12:29:18.996797
2441 12:29:19.000231 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2442 12:29:19.000308
2443 12:29:19.003186 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2444 12:29:19.006539 [DutyScan_Calibration_Flow] ====Done====
2445 12:29:19.006619
2446 12:29:19.009978 [DutyScan_Calibration_Flow] k_type=3
2447 12:29:19.027379
2448 12:29:19.027561 ==DQM 0 ==
2449 12:29:19.030941 Final DQM duty delay cell = 4
2450 12:29:19.034005 [4] MAX Duty = 5093%(X100), DQS PI = 20
2451 12:29:19.037628 [4] MIN Duty = 4938%(X100), DQS PI = 44
2452 12:29:19.040939 [4] AVG Duty = 5015%(X100)
2453 12:29:19.041025
2454 12:29:19.041091 ==DQM 1 ==
2455 12:29:19.044241 Final DQM duty delay cell = 0
2456 12:29:19.047334 [0] MAX Duty = 5249%(X100), DQS PI = 0
2457 12:29:19.050588 [0] MIN Duty = 4907%(X100), DQS PI = 36
2458 12:29:19.054260 [0] AVG Duty = 5078%(X100)
2459 12:29:19.054384
2460 12:29:19.057316 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2461 12:29:19.057405
2462 12:29:19.060501 CH1 DQM 1 Duty spec in!! Max-Min= 342%
2463 12:29:19.064330 [DutyScan_Calibration_Flow] ====Done====
2464 12:29:19.064418
2465 12:29:19.067278 [DutyScan_Calibration_Flow] k_type=2
2466 12:29:19.083872
2467 12:29:19.084029 ==DQ 0 ==
2468 12:29:19.087318 Final DQ duty delay cell = 0
2469 12:29:19.090630 [0] MAX Duty = 5062%(X100), DQS PI = 18
2470 12:29:19.094301 [0] MIN Duty = 4938%(X100), DQS PI = 46
2471 12:29:19.094399 [0] AVG Duty = 5000%(X100)
2472 12:29:19.094467
2473 12:29:19.097338 ==DQ 1 ==
2474 12:29:19.100708 Final DQ duty delay cell = 0
2475 12:29:19.103869 [0] MAX Duty = 5031%(X100), DQS PI = 2
2476 12:29:19.107244 [0] MIN Duty = 4813%(X100), DQS PI = 34
2477 12:29:19.107334 [0] AVG Duty = 4922%(X100)
2478 12:29:19.107402
2479 12:29:19.110682 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2480 12:29:19.113913
2481 12:29:19.117209 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2482 12:29:19.120621 [DutyScan_Calibration_Flow] ====Done====
2483 12:29:19.123913 nWR fixed to 30
2484 12:29:19.124004 [ModeRegInit_LP4] CH0 RK0
2485 12:29:19.127298 [ModeRegInit_LP4] CH0 RK1
2486 12:29:19.130750 [ModeRegInit_LP4] CH1 RK0
2487 12:29:19.130841 [ModeRegInit_LP4] CH1 RK1
2488 12:29:19.133750 match AC timing 7
2489 12:29:19.137170 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2490 12:29:19.140514 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2491 12:29:19.147182 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2492 12:29:19.150290 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2493 12:29:19.157444 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2494 12:29:19.157564 ==
2495 12:29:19.160642 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 12:29:19.164050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 12:29:19.164146 ==
2498 12:29:19.170436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 12:29:19.173864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2500 12:29:19.184057 [CA 0] Center 38 (7~69) winsize 63
2501 12:29:19.187543 [CA 1] Center 38 (8~69) winsize 62
2502 12:29:19.190377 [CA 2] Center 35 (5~66) winsize 62
2503 12:29:19.193765 [CA 3] Center 34 (4~65) winsize 62
2504 12:29:19.197035 [CA 4] Center 34 (4~65) winsize 62
2505 12:29:19.200544 [CA 5] Center 33 (3~63) winsize 61
2506 12:29:19.200644
2507 12:29:19.204056 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 12:29:19.204163
2509 12:29:19.207535 [CATrainingPosCal] consider 1 rank data
2510 12:29:19.210519 u2DelayCellTimex100 = 270/100 ps
2511 12:29:19.213871 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2512 12:29:19.217312 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2513 12:29:19.223937 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 12:29:19.227455 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2515 12:29:19.230169 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2516 12:29:19.233596 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2517 12:29:19.233713
2518 12:29:19.237152 CA PerBit enable=1, Macro0, CA PI delay=33
2519 12:29:19.237294
2520 12:29:19.240527 [CBTSetCACLKResult] CA Dly = 33
2521 12:29:19.240639 CS Dly: 6 (0~37)
2522 12:29:19.243460 ==
2523 12:29:19.246835 Dram Type= 6, Freq= 0, CH_0, rank 1
2524 12:29:19.250179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 12:29:19.250281 ==
2526 12:29:19.253676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 12:29:19.260094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2528 12:29:19.269715 [CA 0] Center 39 (8~70) winsize 63
2529 12:29:19.272852 [CA 1] Center 38 (8~69) winsize 62
2530 12:29:19.276466 [CA 2] Center 35 (5~66) winsize 62
2531 12:29:19.279680 [CA 3] Center 35 (5~66) winsize 62
2532 12:29:19.283180 [CA 4] Center 34 (4~65) winsize 62
2533 12:29:19.286126 [CA 5] Center 34 (4~64) winsize 61
2534 12:29:19.286232
2535 12:29:19.289633 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2536 12:29:19.289739
2537 12:29:19.293034 [CATrainingPosCal] consider 2 rank data
2538 12:29:19.296102 u2DelayCellTimex100 = 270/100 ps
2539 12:29:19.299427 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2540 12:29:19.302767 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2541 12:29:19.309554 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 12:29:19.313059 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2543 12:29:19.316418 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2544 12:29:19.319385 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2545 12:29:19.319486
2546 12:29:19.323064 CA PerBit enable=1, Macro0, CA PI delay=33
2547 12:29:19.323159
2548 12:29:19.326363 [CBTSetCACLKResult] CA Dly = 33
2549 12:29:19.326458 CS Dly: 7 (0~39)
2550 12:29:19.326529
2551 12:29:19.329763 ----->DramcWriteLeveling(PI) begin...
2552 12:29:19.332760 ==
2553 12:29:19.336270 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 12:29:19.339637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 12:29:19.339737 ==
2556 12:29:19.342696 Write leveling (Byte 0): 35 => 35
2557 12:29:19.346166 Write leveling (Byte 1): 32 => 32
2558 12:29:19.349503 DramcWriteLeveling(PI) end<-----
2559 12:29:19.349600
2560 12:29:19.349678 ==
2561 12:29:19.352754 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 12:29:19.356202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 12:29:19.356299 ==
2564 12:29:19.359431 [Gating] SW mode calibration
2565 12:29:19.366054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2566 12:29:19.372476 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2567 12:29:19.376056 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2568 12:29:19.379246 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2569 12:29:19.382862 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 12:29:19.389349 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 12:29:19.392775 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 12:29:19.395685 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 12:29:19.402169 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2574 12:29:19.405893 0 15 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
2575 12:29:19.408884 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2576 12:29:19.415836 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 12:29:19.419357 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 12:29:19.422365 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 12:29:19.429001 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 12:29:19.432404 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 12:29:19.435767 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2582 12:29:19.442252 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2583 12:29:19.445673 1 1 0 | B1->B0 | 3535 4646 | 1 0 | (1 1) (0 0)
2584 12:29:19.449034 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2585 12:29:19.455798 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 12:29:19.458878 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 12:29:19.462189 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 12:29:19.468917 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 12:29:19.472493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2590 12:29:19.475566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2591 12:29:19.482454 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2592 12:29:19.485686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 12:29:19.488865 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 12:29:19.495720 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 12:29:19.499137 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 12:29:19.502027 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 12:29:19.508866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 12:29:19.512195 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 12:29:19.515575 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 12:29:19.522036 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 12:29:19.525524 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 12:29:19.528461 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 12:29:19.532211 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:29:19.538643 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:29:19.542015 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:29:19.548365 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2607 12:29:19.551682 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2608 12:29:19.555149 Total UI for P1: 0, mck2ui 16
2609 12:29:19.558400 best dqsien dly found for B0: ( 1, 3, 28)
2610 12:29:19.561840 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 12:29:19.565210 Total UI for P1: 0, mck2ui 16
2612 12:29:19.568155 best dqsien dly found for B1: ( 1, 3, 30)
2613 12:29:19.571621 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2614 12:29:19.574998 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2615 12:29:19.575098
2616 12:29:19.578184 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2617 12:29:19.584925 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2618 12:29:19.585043 [Gating] SW calibration Done
2619 12:29:19.585116 ==
2620 12:29:19.588081 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 12:29:19.594725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 12:29:19.594841 ==
2623 12:29:19.594913 RX Vref Scan: 0
2624 12:29:19.594978
2625 12:29:19.597992 RX Vref 0 -> 0, step: 1
2626 12:29:19.598082
2627 12:29:19.601633 RX Delay -40 -> 252, step: 8
2628 12:29:19.605055 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2629 12:29:19.608425 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2630 12:29:19.611736 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2631 12:29:19.615051 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2632 12:29:19.621563 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2633 12:29:19.625091 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2634 12:29:19.628573 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2635 12:29:19.631484 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2636 12:29:19.634776 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2637 12:29:19.641357 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2638 12:29:19.644738 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2639 12:29:19.648197 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2640 12:29:19.651549 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2641 12:29:19.655048 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2642 12:29:19.661373 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2643 12:29:19.664590 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2644 12:29:19.664693 ==
2645 12:29:19.668024 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:29:19.671373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:29:19.671466 ==
2648 12:29:19.674726 DQS Delay:
2649 12:29:19.674817 DQS0 = 0, DQS1 = 0
2650 12:29:19.674888 DQM Delay:
2651 12:29:19.678163 DQM0 = 123, DQM1 = 110
2652 12:29:19.678255 DQ Delay:
2653 12:29:19.681500 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2654 12:29:19.684805 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2655 12:29:19.691328 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2656 12:29:19.694434 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2657 12:29:19.694528
2658 12:29:19.694596
2659 12:29:19.694663 ==
2660 12:29:19.698088 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 12:29:19.701395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 12:29:19.701490 ==
2663 12:29:19.701578
2664 12:29:19.701663
2665 12:29:19.704582 TX Vref Scan disable
2666 12:29:19.708181 == TX Byte 0 ==
2667 12:29:19.711339 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2668 12:29:19.714865 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2669 12:29:19.718136 == TX Byte 1 ==
2670 12:29:19.721147 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2671 12:29:19.724614 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2672 12:29:19.724700 ==
2673 12:29:19.728032 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 12:29:19.730968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 12:29:19.734425 ==
2676 12:29:19.744510 TX Vref=22, minBit 0, minWin=24, winSum=401
2677 12:29:19.747437 TX Vref=24, minBit 0, minWin=24, winSum=403
2678 12:29:19.750915 TX Vref=26, minBit 1, minWin=24, winSum=413
2679 12:29:19.754392 TX Vref=28, minBit 7, minWin=24, winSum=415
2680 12:29:19.757431 TX Vref=30, minBit 3, minWin=25, winSum=414
2681 12:29:19.760932 TX Vref=32, minBit 0, minWin=25, winSum=415
2682 12:29:19.767527 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 32
2683 12:29:19.767621
2684 12:29:19.770980 Final TX Range 1 Vref 32
2685 12:29:19.771069
2686 12:29:19.771138 ==
2687 12:29:19.774395 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 12:29:19.777844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 12:29:19.777933 ==
2690 12:29:19.778002
2691 12:29:19.780778
2692 12:29:19.780865 TX Vref Scan disable
2693 12:29:19.784214 == TX Byte 0 ==
2694 12:29:19.787495 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2695 12:29:19.790960 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2696 12:29:19.793840 == TX Byte 1 ==
2697 12:29:19.797173 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2698 12:29:19.800658 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2699 12:29:19.803837
2700 12:29:19.803924 [DATLAT]
2701 12:29:19.803993 Freq=1200, CH0 RK0
2702 12:29:19.804058
2703 12:29:19.807504 DATLAT Default: 0xd
2704 12:29:19.807589 0, 0xFFFF, sum = 0
2705 12:29:19.810714 1, 0xFFFF, sum = 0
2706 12:29:19.810802 2, 0xFFFF, sum = 0
2707 12:29:19.814079 3, 0xFFFF, sum = 0
2708 12:29:19.817210 4, 0xFFFF, sum = 0
2709 12:29:19.817296 5, 0xFFFF, sum = 0
2710 12:29:19.820932 6, 0xFFFF, sum = 0
2711 12:29:19.821019 7, 0xFFFF, sum = 0
2712 12:29:19.824203 8, 0xFFFF, sum = 0
2713 12:29:19.824290 9, 0xFFFF, sum = 0
2714 12:29:19.827209 10, 0xFFFF, sum = 0
2715 12:29:19.827296 11, 0xFFFF, sum = 0
2716 12:29:19.830698 12, 0x0, sum = 1
2717 12:29:19.830784 13, 0x0, sum = 2
2718 12:29:19.833667 14, 0x0, sum = 3
2719 12:29:19.833756 15, 0x0, sum = 4
2720 12:29:19.837125 best_step = 13
2721 12:29:19.837210
2722 12:29:19.837277 ==
2723 12:29:19.840587 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 12:29:19.843792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 12:29:19.843878 ==
2726 12:29:19.843978 RX Vref Scan: 1
2727 12:29:19.844041
2728 12:29:19.847073 Set Vref Range= 32 -> 127
2729 12:29:19.847169
2730 12:29:19.850607 RX Vref 32 -> 127, step: 1
2731 12:29:19.850692
2732 12:29:19.853572 RX Delay -13 -> 252, step: 4
2733 12:29:19.853658
2734 12:29:19.856989 Set Vref, RX VrefLevel [Byte0]: 32
2735 12:29:19.860468 [Byte1]: 32
2736 12:29:19.860545
2737 12:29:19.863411 Set Vref, RX VrefLevel [Byte0]: 33
2738 12:29:19.866842 [Byte1]: 33
2739 12:29:19.870680
2740 12:29:19.870772 Set Vref, RX VrefLevel [Byte0]: 34
2741 12:29:19.873782 [Byte1]: 34
2742 12:29:19.878236
2743 12:29:19.878317 Set Vref, RX VrefLevel [Byte0]: 35
2744 12:29:19.881520 [Byte1]: 35
2745 12:29:19.885942
2746 12:29:19.886021 Set Vref, RX VrefLevel [Byte0]: 36
2747 12:29:19.889371 [Byte1]: 36
2748 12:29:19.894136
2749 12:29:19.894215 Set Vref, RX VrefLevel [Byte0]: 37
2750 12:29:19.897101 [Byte1]: 37
2751 12:29:19.901987
2752 12:29:19.902063 Set Vref, RX VrefLevel [Byte0]: 38
2753 12:29:19.905304 [Byte1]: 38
2754 12:29:19.909919
2755 12:29:19.909994 Set Vref, RX VrefLevel [Byte0]: 39
2756 12:29:19.913057 [Byte1]: 39
2757 12:29:19.917471
2758 12:29:19.917556 Set Vref, RX VrefLevel [Byte0]: 40
2759 12:29:19.921146 [Byte1]: 40
2760 12:29:19.925593
2761 12:29:19.925707 Set Vref, RX VrefLevel [Byte0]: 41
2762 12:29:19.929184 [Byte1]: 41
2763 12:29:19.933353
2764 12:29:19.933439 Set Vref, RX VrefLevel [Byte0]: 42
2765 12:29:19.936742 [Byte1]: 42
2766 12:29:19.941275
2767 12:29:19.941374 Set Vref, RX VrefLevel [Byte0]: 43
2768 12:29:19.944618 [Byte1]: 43
2769 12:29:19.949329
2770 12:29:19.949414 Set Vref, RX VrefLevel [Byte0]: 44
2771 12:29:19.952644 [Byte1]: 44
2772 12:29:19.957173
2773 12:29:19.957259 Set Vref, RX VrefLevel [Byte0]: 45
2774 12:29:19.960694 [Byte1]: 45
2775 12:29:19.965018
2776 12:29:19.965142 Set Vref, RX VrefLevel [Byte0]: 46
2777 12:29:19.968324 [Byte1]: 46
2778 12:29:19.973044
2779 12:29:19.973130 Set Vref, RX VrefLevel [Byte0]: 47
2780 12:29:19.976250 [Byte1]: 47
2781 12:29:19.980642
2782 12:29:19.980733 Set Vref, RX VrefLevel [Byte0]: 48
2783 12:29:19.984031 [Byte1]: 48
2784 12:29:19.988579
2785 12:29:19.988665 Set Vref, RX VrefLevel [Byte0]: 49
2786 12:29:19.991908 [Byte1]: 49
2787 12:29:19.996694
2788 12:29:19.996798 Set Vref, RX VrefLevel [Byte0]: 50
2789 12:29:20.000080 [Byte1]: 50
2790 12:29:20.004629
2791 12:29:20.004713 Set Vref, RX VrefLevel [Byte0]: 51
2792 12:29:20.007958 [Byte1]: 51
2793 12:29:20.012174
2794 12:29:20.012259 Set Vref, RX VrefLevel [Byte0]: 52
2795 12:29:20.015636 [Byte1]: 52
2796 12:29:20.020204
2797 12:29:20.020306 Set Vref, RX VrefLevel [Byte0]: 53
2798 12:29:20.023788 [Byte1]: 53
2799 12:29:20.028269
2800 12:29:20.028404 Set Vref, RX VrefLevel [Byte0]: 54
2801 12:29:20.031421 [Byte1]: 54
2802 12:29:20.036019
2803 12:29:20.036131 Set Vref, RX VrefLevel [Byte0]: 55
2804 12:29:20.039366 [Byte1]: 55
2805 12:29:20.043800
2806 12:29:20.043912 Set Vref, RX VrefLevel [Byte0]: 56
2807 12:29:20.047165 [Byte1]: 56
2808 12:29:20.051704
2809 12:29:20.051792 Set Vref, RX VrefLevel [Byte0]: 57
2810 12:29:20.055304 [Byte1]: 57
2811 12:29:20.059726
2812 12:29:20.059836 Set Vref, RX VrefLevel [Byte0]: 58
2813 12:29:20.063181 [Byte1]: 58
2814 12:29:20.067552
2815 12:29:20.067674 Set Vref, RX VrefLevel [Byte0]: 59
2816 12:29:20.070919 [Byte1]: 59
2817 12:29:20.075325
2818 12:29:20.075440 Set Vref, RX VrefLevel [Byte0]: 60
2819 12:29:20.078756 [Byte1]: 60
2820 12:29:20.083095
2821 12:29:20.083206 Set Vref, RX VrefLevel [Byte0]: 61
2822 12:29:20.086593 [Byte1]: 61
2823 12:29:20.091051
2824 12:29:20.091136 Set Vref, RX VrefLevel [Byte0]: 62
2825 12:29:20.094479 [Byte1]: 62
2826 12:29:20.099135
2827 12:29:20.099261 Set Vref, RX VrefLevel [Byte0]: 63
2828 12:29:20.102691 [Byte1]: 63
2829 12:29:20.107303
2830 12:29:20.107436 Set Vref, RX VrefLevel [Byte0]: 64
2831 12:29:20.110373 [Byte1]: 64
2832 12:29:20.114962
2833 12:29:20.118290 Set Vref, RX VrefLevel [Byte0]: 65
2834 12:29:20.118423 [Byte1]: 65
2835 12:29:20.123095
2836 12:29:20.123218 Set Vref, RX VrefLevel [Byte0]: 66
2837 12:29:20.126270 [Byte1]: 66
2838 12:29:20.130929
2839 12:29:20.131054 Set Vref, RX VrefLevel [Byte0]: 67
2840 12:29:20.134163 [Byte1]: 67
2841 12:29:20.138675
2842 12:29:20.138789 Set Vref, RX VrefLevel [Byte0]: 68
2843 12:29:20.141845 [Byte1]: 68
2844 12:29:20.146377
2845 12:29:20.146491 Set Vref, RX VrefLevel [Byte0]: 69
2846 12:29:20.149805 [Byte1]: 69
2847 12:29:20.154541
2848 12:29:20.154674 Final RX Vref Byte 0 = 61 to rank0
2849 12:29:20.157800 Final RX Vref Byte 1 = 49 to rank0
2850 12:29:20.161264 Final RX Vref Byte 0 = 61 to rank1
2851 12:29:20.164686 Final RX Vref Byte 1 = 49 to rank1==
2852 12:29:20.167662 Dram Type= 6, Freq= 0, CH_0, rank 0
2853 12:29:20.174638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 12:29:20.174748 ==
2855 12:29:20.174847 DQS Delay:
2856 12:29:20.174972 DQS0 = 0, DQS1 = 0
2857 12:29:20.177837 DQM Delay:
2858 12:29:20.177946 DQM0 = 122, DQM1 = 109
2859 12:29:20.180752 DQ Delay:
2860 12:29:20.184090 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2861 12:29:20.187504 DQ4 =126, DQ5 =116, DQ6 =128, DQ7 =128
2862 12:29:20.190953 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2863 12:29:20.193961 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2864 12:29:20.194047
2865 12:29:20.194115
2866 12:29:20.204379 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2867 12:29:20.204493 CH0 RK0: MR19=404, MR18=B08
2868 12:29:20.210720 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2869 12:29:20.210841
2870 12:29:20.214154 ----->DramcWriteLeveling(PI) begin...
2871 12:29:20.214246 ==
2872 12:29:20.217467 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 12:29:20.220695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 12:29:20.224161 ==
2875 12:29:20.224305 Write leveling (Byte 0): 34 => 34
2876 12:29:20.227098 Write leveling (Byte 1): 31 => 31
2877 12:29:20.230677 DramcWriteLeveling(PI) end<-----
2878 12:29:20.230791
2879 12:29:20.230890 ==
2880 12:29:20.234235 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 12:29:20.240467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 12:29:20.240580 ==
2883 12:29:20.244249 [Gating] SW mode calibration
2884 12:29:20.250540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2885 12:29:20.253650 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2886 12:29:20.260376 0 15 0 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
2887 12:29:20.263615 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 12:29:20.267100 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 12:29:20.273548 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 12:29:20.276955 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 12:29:20.280482 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 12:29:20.287265 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 12:29:20.290556 0 15 28 | B1->B0 | 2c2c 2d2d | 0 0 | (1 0) (1 0)
2894 12:29:20.293582 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2895 12:29:20.297070 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 12:29:20.303510 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 12:29:20.306792 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 12:29:20.310277 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 12:29:20.316735 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 12:29:20.320240 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2901 12:29:20.323598 1 0 28 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
2902 12:29:20.330105 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 12:29:20.333375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 12:29:20.336793 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 12:29:20.343484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 12:29:20.346729 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 12:29:20.349855 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 12:29:20.356439 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 12:29:20.359859 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2910 12:29:20.363162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 12:29:20.369979 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 12:29:20.373365 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 12:29:20.376936 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 12:29:20.383134 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 12:29:20.386640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 12:29:20.389998 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:29:20.396794 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:29:20.399670 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:29:20.403086 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:29:20.409594 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:29:20.413258 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:29:20.416291 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:29:20.423220 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:29:20.426168 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2925 12:29:20.429800 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2926 12:29:20.436142 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2927 12:29:20.436259 Total UI for P1: 0, mck2ui 16
2928 12:29:20.439673 best dqsien dly found for B1: ( 1, 3, 28)
2929 12:29:20.446212 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 12:29:20.449334 Total UI for P1: 0, mck2ui 16
2931 12:29:20.453039 best dqsien dly found for B0: ( 1, 3, 28)
2932 12:29:20.456292 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2933 12:29:20.459891 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2934 12:29:20.459981
2935 12:29:20.462530 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2936 12:29:20.466150 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2937 12:29:20.469246 [Gating] SW calibration Done
2938 12:29:20.469354 ==
2939 12:29:20.472733 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 12:29:20.476168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 12:29:20.476283 ==
2942 12:29:20.479115 RX Vref Scan: 0
2943 12:29:20.479219
2944 12:29:20.482490 RX Vref 0 -> 0, step: 1
2945 12:29:20.482581
2946 12:29:20.482652 RX Delay -40 -> 252, step: 8
2947 12:29:20.489373 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2948 12:29:20.492763 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2949 12:29:20.496006 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2950 12:29:20.499384 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2951 12:29:20.502922 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2952 12:29:20.509250 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2953 12:29:20.512658 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2954 12:29:20.515801 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2955 12:29:20.519292 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2956 12:29:20.522275 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2957 12:29:20.529192 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2958 12:29:20.532457 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2959 12:29:20.535477 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2960 12:29:20.538849 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2961 12:29:20.545761 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2962 12:29:20.548616 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2963 12:29:20.548733 ==
2964 12:29:20.551921 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 12:29:20.555260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 12:29:20.555380 ==
2967 12:29:20.555480 DQS Delay:
2968 12:29:20.558610 DQS0 = 0, DQS1 = 0
2969 12:29:20.558699 DQM Delay:
2970 12:29:20.562299 DQM0 = 120, DQM1 = 108
2971 12:29:20.562389 DQ Delay:
2972 12:29:20.565624 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2973 12:29:20.568760 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2974 12:29:20.571973 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2975 12:29:20.575242 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2976 12:29:20.578767
2977 12:29:20.578881
2978 12:29:20.578973 ==
2979 12:29:20.582201 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 12:29:20.585582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 12:29:20.585696 ==
2982 12:29:20.585798
2983 12:29:20.585892
2984 12:29:20.588406 TX Vref Scan disable
2985 12:29:20.588509 == TX Byte 0 ==
2986 12:29:20.595278 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2987 12:29:20.598564 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2988 12:29:20.598672 == TX Byte 1 ==
2989 12:29:20.605478 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2990 12:29:20.608342 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2991 12:29:20.608474 ==
2992 12:29:20.611743 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 12:29:20.615178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 12:29:20.615287 ==
2995 12:29:20.627818 TX Vref=22, minBit 0, minWin=24, winSum=410
2996 12:29:20.631227 TX Vref=24, minBit 4, minWin=24, winSum=415
2997 12:29:20.634461 TX Vref=26, minBit 7, minWin=24, winSum=417
2998 12:29:20.637874 TX Vref=28, minBit 2, minWin=25, winSum=422
2999 12:29:20.641403 TX Vref=30, minBit 5, minWin=25, winSum=425
3000 12:29:20.647796 TX Vref=32, minBit 1, minWin=25, winSum=420
3001 12:29:20.650752 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
3002 12:29:20.650870
3003 12:29:20.654182 Final TX Range 1 Vref 30
3004 12:29:20.654271
3005 12:29:20.654341 ==
3006 12:29:20.657596 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 12:29:20.660762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 12:29:20.663936 ==
3009 12:29:20.664027
3010 12:29:20.664096
3011 12:29:20.664198 TX Vref Scan disable
3012 12:29:20.667606 == TX Byte 0 ==
3013 12:29:20.670886 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3014 12:29:20.677372 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3015 12:29:20.677493 == TX Byte 1 ==
3016 12:29:20.680986 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3017 12:29:20.687550 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3018 12:29:20.687671
3019 12:29:20.687770 [DATLAT]
3020 12:29:20.687864 Freq=1200, CH0 RK1
3021 12:29:20.687957
3022 12:29:20.690812 DATLAT Default: 0xd
3023 12:29:20.690935 0, 0xFFFF, sum = 0
3024 12:29:20.694239 1, 0xFFFF, sum = 0
3025 12:29:20.694356 2, 0xFFFF, sum = 0
3026 12:29:20.697660 3, 0xFFFF, sum = 0
3027 12:29:20.700577 4, 0xFFFF, sum = 0
3028 12:29:20.700689 5, 0xFFFF, sum = 0
3029 12:29:20.703964 6, 0xFFFF, sum = 0
3030 12:29:20.704087 7, 0xFFFF, sum = 0
3031 12:29:20.707369 8, 0xFFFF, sum = 0
3032 12:29:20.707491 9, 0xFFFF, sum = 0
3033 12:29:20.710914 10, 0xFFFF, sum = 0
3034 12:29:20.711028 11, 0xFFFF, sum = 0
3035 12:29:20.714046 12, 0x0, sum = 1
3036 12:29:20.714136 13, 0x0, sum = 2
3037 12:29:20.717411 14, 0x0, sum = 3
3038 12:29:20.717528 15, 0x0, sum = 4
3039 12:29:20.717638 best_step = 13
3040 12:29:20.720797
3041 12:29:20.720884 ==
3042 12:29:20.724146 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 12:29:20.727599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 12:29:20.727720 ==
3045 12:29:20.727825 RX Vref Scan: 0
3046 12:29:20.727925
3047 12:29:20.730601 RX Vref 0 -> 0, step: 1
3048 12:29:20.730710
3049 12:29:20.734028 RX Delay -21 -> 252, step: 4
3050 12:29:20.737395 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3051 12:29:20.744021 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3052 12:29:20.747509 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3053 12:29:20.750470 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3054 12:29:20.753827 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3055 12:29:20.757213 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3056 12:29:20.763871 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3057 12:29:20.767210 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3058 12:29:20.770406 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3059 12:29:20.773484 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3060 12:29:20.776707 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3061 12:29:20.783568 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3062 12:29:20.787099 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3063 12:29:20.790302 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3064 12:29:20.793530 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3065 12:29:20.800271 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3066 12:29:20.800394 ==
3067 12:29:20.803664 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 12:29:20.807090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 12:29:20.807206 ==
3070 12:29:20.807320 DQS Delay:
3071 12:29:20.810297 DQS0 = 0, DQS1 = 0
3072 12:29:20.810427 DQM Delay:
3073 12:29:20.813635 DQM0 = 119, DQM1 = 107
3074 12:29:20.813738 DQ Delay:
3075 12:29:20.816628 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3076 12:29:20.820194 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3077 12:29:20.823517 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3078 12:29:20.826859 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3079 12:29:20.826964
3080 12:29:20.827057
3081 12:29:20.836714 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3082 12:29:20.836858 CH0 RK1: MR19=403, MR18=DF5
3083 12:29:20.843392 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3084 12:29:20.846756 [RxdqsGatingPostProcess] freq 1200
3085 12:29:20.853563 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3086 12:29:20.856615 best DQS0 dly(2T, 0.5T) = (0, 11)
3087 12:29:20.859979 best DQS1 dly(2T, 0.5T) = (0, 11)
3088 12:29:20.863438 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3089 12:29:20.866820 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3090 12:29:20.869824 best DQS0 dly(2T, 0.5T) = (0, 11)
3091 12:29:20.873231 best DQS1 dly(2T, 0.5T) = (0, 11)
3092 12:29:20.876536 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3093 12:29:20.879645 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3094 12:29:20.879772 Pre-setting of DQS Precalculation
3095 12:29:20.886603 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3096 12:29:20.886737 ==
3097 12:29:20.889749 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 12:29:20.893316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 12:29:20.893444 ==
3100 12:29:20.899846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 12:29:20.906307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3102 12:29:20.913747 [CA 0] Center 37 (7~68) winsize 62
3103 12:29:20.917232 [CA 1] Center 37 (7~68) winsize 62
3104 12:29:20.920203 [CA 2] Center 35 (5~65) winsize 61
3105 12:29:20.923591 [CA 3] Center 34 (4~65) winsize 62
3106 12:29:20.927087 [CA 4] Center 34 (4~64) winsize 61
3107 12:29:20.930445 [CA 5] Center 33 (3~64) winsize 62
3108 12:29:20.930557
3109 12:29:20.933633 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3110 12:29:20.933741
3111 12:29:20.937123 [CATrainingPosCal] consider 1 rank data
3112 12:29:20.940029 u2DelayCellTimex100 = 270/100 ps
3113 12:29:20.943433 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3114 12:29:20.950033 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3115 12:29:20.952938 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3116 12:29:20.956450 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3117 12:29:20.959939 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 12:29:20.962883 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3119 12:29:20.962965
3120 12:29:20.966416 CA PerBit enable=1, Macro0, CA PI delay=33
3121 12:29:20.966522
3122 12:29:20.969754 [CBTSetCACLKResult] CA Dly = 33
3123 12:29:20.973217 CS Dly: 5 (0~36)
3124 12:29:20.973303 ==
3125 12:29:20.976186 Dram Type= 6, Freq= 0, CH_1, rank 1
3126 12:29:20.979604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 12:29:20.979689 ==
3128 12:29:20.986499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3129 12:29:20.989782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3130 12:29:20.999188 [CA 0] Center 38 (8~68) winsize 61
3131 12:29:21.002733 [CA 1] Center 38 (7~69) winsize 63
3132 12:29:21.006303 [CA 2] Center 35 (5~66) winsize 62
3133 12:29:21.009431 [CA 3] Center 35 (5~65) winsize 61
3134 12:29:21.012856 [CA 4] Center 35 (5~65) winsize 61
3135 12:29:21.015748 [CA 5] Center 34 (4~64) winsize 61
3136 12:29:21.015851
3137 12:29:21.019101 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3138 12:29:21.019215
3139 12:29:21.022500 [CATrainingPosCal] consider 2 rank data
3140 12:29:21.025957 u2DelayCellTimex100 = 270/100 ps
3141 12:29:21.028939 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3142 12:29:21.035702 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3143 12:29:21.039178 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3144 12:29:21.042101 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3145 12:29:21.045528 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3146 12:29:21.049082 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3147 12:29:21.049194
3148 12:29:21.052317 CA PerBit enable=1, Macro0, CA PI delay=34
3149 12:29:21.052425
3150 12:29:21.055780 [CBTSetCACLKResult] CA Dly = 34
3151 12:29:21.055888 CS Dly: 6 (0~39)
3152 12:29:21.059287
3153 12:29:21.062212 ----->DramcWriteLeveling(PI) begin...
3154 12:29:21.062321 ==
3155 12:29:21.065657 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 12:29:21.069088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 12:29:21.069201 ==
3158 12:29:21.072462 Write leveling (Byte 0): 25 => 25
3159 12:29:21.075839 Write leveling (Byte 1): 28 => 28
3160 12:29:21.078768 DramcWriteLeveling(PI) end<-----
3161 12:29:21.078887
3162 12:29:21.078987 ==
3163 12:29:21.082187 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 12:29:21.085563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 12:29:21.085648 ==
3166 12:29:21.088851 [Gating] SW mode calibration
3167 12:29:21.095559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3168 12:29:21.102102 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3169 12:29:21.105704 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 12:29:21.109044 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 12:29:21.115544 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 12:29:21.118987 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 12:29:21.122315 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 12:29:21.125691 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 12:29:21.132199 0 15 24 | B1->B0 | 2f2f 2c2c | 1 1 | (1 1) (1 0)
3176 12:29:21.135589 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 12:29:21.138844 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 12:29:21.145693 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 12:29:21.149190 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 12:29:21.152022 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 12:29:21.158738 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 12:29:21.162114 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3183 12:29:21.165654 1 0 24 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (1 1)
3184 12:29:21.172031 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 12:29:21.175487 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 12:29:21.178939 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 12:29:21.185733 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 12:29:21.189075 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 12:29:21.192406 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 12:29:21.199214 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3191 12:29:21.202379 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3192 12:29:21.205577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3193 12:29:21.212082 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 12:29:21.215366 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 12:29:21.218879 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 12:29:21.225249 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 12:29:21.229020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 12:29:21.232008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:29:21.235439 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 12:29:21.242343 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:29:21.245630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:29:21.248592 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:29:21.255490 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:29:21.258839 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:29:21.262320 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:29:21.269231 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3207 12:29:21.272139 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3208 12:29:21.275565 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3209 12:29:21.278996 Total UI for P1: 0, mck2ui 16
3210 12:29:21.282299 best dqsien dly found for B0: ( 1, 3, 22)
3211 12:29:21.289036 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 12:29:21.289130 Total UI for P1: 0, mck2ui 16
3213 12:29:21.295470 best dqsien dly found for B1: ( 1, 3, 26)
3214 12:29:21.298720 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3215 12:29:21.301956 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3216 12:29:21.302062
3217 12:29:21.305408 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3218 12:29:21.308691 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3219 12:29:21.312067 [Gating] SW calibration Done
3220 12:29:21.312159 ==
3221 12:29:21.315692 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 12:29:21.318815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 12:29:21.318906 ==
3224 12:29:21.322029 RX Vref Scan: 0
3225 12:29:21.322122
3226 12:29:21.322193 RX Vref 0 -> 0, step: 1
3227 12:29:21.322259
3228 12:29:21.325247 RX Delay -40 -> 252, step: 8
3229 12:29:21.328644 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3230 12:29:21.335308 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3231 12:29:21.338682 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3232 12:29:21.342008 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3233 12:29:21.345452 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3234 12:29:21.348626 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3235 12:29:21.355020 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3236 12:29:21.358516 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3237 12:29:21.361902 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3238 12:29:21.365310 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3239 12:29:21.368246 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3240 12:29:21.375222 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3241 12:29:21.378242 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3242 12:29:21.381794 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3243 12:29:21.385102 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3244 12:29:21.388136 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3245 12:29:21.391541 ==
3246 12:29:21.394937 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 12:29:21.398325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 12:29:21.398413 ==
3249 12:29:21.398493 DQS Delay:
3250 12:29:21.401554 DQS0 = 0, DQS1 = 0
3251 12:29:21.401642 DQM Delay:
3252 12:29:21.404991 DQM0 = 120, DQM1 = 112
3253 12:29:21.405067 DQ Delay:
3254 12:29:21.408373 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3255 12:29:21.411345 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3256 12:29:21.414714 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3257 12:29:21.418268 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3258 12:29:21.418352
3259 12:29:21.418418
3260 12:29:21.418485 ==
3261 12:29:21.421673 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 12:29:21.428078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 12:29:21.428200 ==
3264 12:29:21.428306
3265 12:29:21.428398
3266 12:29:21.428491 TX Vref Scan disable
3267 12:29:21.431354 == TX Byte 0 ==
3268 12:29:21.434872 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3269 12:29:21.438315 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3270 12:29:21.441538 == TX Byte 1 ==
3271 12:29:21.444996 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3272 12:29:21.451391 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3273 12:29:21.451479 ==
3274 12:29:21.454738 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 12:29:21.458086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 12:29:21.458166 ==
3277 12:29:21.469230 TX Vref=22, minBit 1, minWin=24, winSum=406
3278 12:29:21.472614 TX Vref=24, minBit 10, minWin=24, winSum=406
3279 12:29:21.475593 TX Vref=26, minBit 9, minWin=25, winSum=417
3280 12:29:21.479180 TX Vref=28, minBit 10, minWin=25, winSum=421
3281 12:29:21.482554 TX Vref=30, minBit 10, minWin=25, winSum=424
3282 12:29:21.489181 TX Vref=32, minBit 1, minWin=26, winSum=424
3283 12:29:21.492484 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3284 12:29:21.492588
3285 12:29:21.495936 Final TX Range 1 Vref 32
3286 12:29:21.496026
3287 12:29:21.496094 ==
3288 12:29:21.499003 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 12:29:21.505680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 12:29:21.505780 ==
3291 12:29:21.505847
3292 12:29:21.505910
3293 12:29:21.505970 TX Vref Scan disable
3294 12:29:21.509556 == TX Byte 0 ==
3295 12:29:21.512882 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3296 12:29:21.519307 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3297 12:29:21.519405 == TX Byte 1 ==
3298 12:29:21.522520 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3299 12:29:21.529459 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3300 12:29:21.529591
3301 12:29:21.529689 [DATLAT]
3302 12:29:21.529781 Freq=1200, CH1 RK0
3303 12:29:21.529937
3304 12:29:21.532347 DATLAT Default: 0xd
3305 12:29:21.532447 0, 0xFFFF, sum = 0
3306 12:29:21.535614 1, 0xFFFF, sum = 0
3307 12:29:21.539197 2, 0xFFFF, sum = 0
3308 12:29:21.539287 3, 0xFFFF, sum = 0
3309 12:29:21.542676 4, 0xFFFF, sum = 0
3310 12:29:21.542830 5, 0xFFFF, sum = 0
3311 12:29:21.545891 6, 0xFFFF, sum = 0
3312 12:29:21.545982 7, 0xFFFF, sum = 0
3313 12:29:21.548957 8, 0xFFFF, sum = 0
3314 12:29:21.549046 9, 0xFFFF, sum = 0
3315 12:29:21.552379 10, 0xFFFF, sum = 0
3316 12:29:21.552476 11, 0xFFFF, sum = 0
3317 12:29:21.555694 12, 0x0, sum = 1
3318 12:29:21.555784 13, 0x0, sum = 2
3319 12:29:21.559160 14, 0x0, sum = 3
3320 12:29:21.559279 15, 0x0, sum = 4
3321 12:29:21.562205 best_step = 13
3322 12:29:21.562337
3323 12:29:21.562404 ==
3324 12:29:21.565656 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 12:29:21.569187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 12:29:21.569276 ==
3327 12:29:21.569343 RX Vref Scan: 1
3328 12:29:21.569404
3329 12:29:21.572356 Set Vref Range= 32 -> 127
3330 12:29:21.572486
3331 12:29:21.575681 RX Vref 32 -> 127, step: 1
3332 12:29:21.575766
3333 12:29:21.579075 RX Delay -13 -> 252, step: 4
3334 12:29:21.579160
3335 12:29:21.582098 Set Vref, RX VrefLevel [Byte0]: 32
3336 12:29:21.585532 [Byte1]: 32
3337 12:29:21.585623
3338 12:29:21.589020 Set Vref, RX VrefLevel [Byte0]: 33
3339 12:29:21.592367 [Byte1]: 33
3340 12:29:21.595773
3341 12:29:21.595872 Set Vref, RX VrefLevel [Byte0]: 34
3342 12:29:21.599231 [Byte1]: 34
3343 12:29:21.603583
3344 12:29:21.603672 Set Vref, RX VrefLevel [Byte0]: 35
3345 12:29:21.606973 [Byte1]: 35
3346 12:29:21.611587
3347 12:29:21.611679 Set Vref, RX VrefLevel [Byte0]: 36
3348 12:29:21.614945 [Byte1]: 36
3349 12:29:21.619413
3350 12:29:21.619502 Set Vref, RX VrefLevel [Byte0]: 37
3351 12:29:21.622857 [Byte1]: 37
3352 12:29:21.627248
3353 12:29:21.627341 Set Vref, RX VrefLevel [Byte0]: 38
3354 12:29:21.630562 [Byte1]: 38
3355 12:29:21.635059
3356 12:29:21.635153 Set Vref, RX VrefLevel [Byte0]: 39
3357 12:29:21.638379 [Byte1]: 39
3358 12:29:21.642933
3359 12:29:21.643026 Set Vref, RX VrefLevel [Byte0]: 40
3360 12:29:21.646382 [Byte1]: 40
3361 12:29:21.650884
3362 12:29:21.650980 Set Vref, RX VrefLevel [Byte0]: 41
3363 12:29:21.654336 [Byte1]: 41
3364 12:29:21.658653
3365 12:29:21.658746 Set Vref, RX VrefLevel [Byte0]: 42
3366 12:29:21.661920 [Byte1]: 42
3367 12:29:21.666844
3368 12:29:21.666942 Set Vref, RX VrefLevel [Byte0]: 43
3369 12:29:21.669749 [Byte1]: 43
3370 12:29:21.674572
3371 12:29:21.674661 Set Vref, RX VrefLevel [Byte0]: 44
3372 12:29:21.677768 [Byte1]: 44
3373 12:29:21.682721
3374 12:29:21.682820 Set Vref, RX VrefLevel [Byte0]: 45
3375 12:29:21.685732 [Byte1]: 45
3376 12:29:21.690355
3377 12:29:21.690448 Set Vref, RX VrefLevel [Byte0]: 46
3378 12:29:21.693800 [Byte1]: 46
3379 12:29:21.698044
3380 12:29:21.698139 Set Vref, RX VrefLevel [Byte0]: 47
3381 12:29:21.701773 [Byte1]: 47
3382 12:29:21.706246
3383 12:29:21.706365 Set Vref, RX VrefLevel [Byte0]: 48
3384 12:29:21.709329 [Byte1]: 48
3385 12:29:21.713835
3386 12:29:21.713945 Set Vref, RX VrefLevel [Byte0]: 49
3387 12:29:21.717172 [Byte1]: 49
3388 12:29:21.722020
3389 12:29:21.722144 Set Vref, RX VrefLevel [Byte0]: 50
3390 12:29:21.725435 [Byte1]: 50
3391 12:29:21.729756
3392 12:29:21.729883 Set Vref, RX VrefLevel [Byte0]: 51
3393 12:29:21.733199 [Byte1]: 51
3394 12:29:21.737993
3395 12:29:21.738111 Set Vref, RX VrefLevel [Byte0]: 52
3396 12:29:21.741081 [Byte1]: 52
3397 12:29:21.745623
3398 12:29:21.745742 Set Vref, RX VrefLevel [Byte0]: 53
3399 12:29:21.748761 [Byte1]: 53
3400 12:29:21.753559
3401 12:29:21.753674 Set Vref, RX VrefLevel [Byte0]: 54
3402 12:29:21.756633 [Byte1]: 54
3403 12:29:21.761307
3404 12:29:21.761422 Set Vref, RX VrefLevel [Byte0]: 55
3405 12:29:21.764571 [Byte1]: 55
3406 12:29:21.769070
3407 12:29:21.772495 Set Vref, RX VrefLevel [Byte0]: 56
3408 12:29:21.775530 [Byte1]: 56
3409 12:29:21.775645
3410 12:29:21.778902 Set Vref, RX VrefLevel [Byte0]: 57
3411 12:29:21.782035 [Byte1]: 57
3412 12:29:21.782161
3413 12:29:21.785468 Set Vref, RX VrefLevel [Byte0]: 58
3414 12:29:21.788870 [Byte1]: 58
3415 12:29:21.792698
3416 12:29:21.792815 Set Vref, RX VrefLevel [Byte0]: 59
3417 12:29:21.796188 [Byte1]: 59
3418 12:29:21.801108
3419 12:29:21.801200 Set Vref, RX VrefLevel [Byte0]: 60
3420 12:29:21.803963 [Byte1]: 60
3421 12:29:21.808863
3422 12:29:21.808990 Set Vref, RX VrefLevel [Byte0]: 61
3423 12:29:21.811873 [Byte1]: 61
3424 12:29:21.816567
3425 12:29:21.816679 Set Vref, RX VrefLevel [Byte0]: 62
3426 12:29:21.819820 [Byte1]: 62
3427 12:29:21.824604
3428 12:29:21.824722 Set Vref, RX VrefLevel [Byte0]: 63
3429 12:29:21.827608 [Byte1]: 63
3430 12:29:21.832498
3431 12:29:21.832619 Set Vref, RX VrefLevel [Byte0]: 64
3432 12:29:21.835494 [Byte1]: 64
3433 12:29:21.840449
3434 12:29:21.840562 Set Vref, RX VrefLevel [Byte0]: 65
3435 12:29:21.843716 [Byte1]: 65
3436 12:29:21.848416
3437 12:29:21.848532 Set Vref, RX VrefLevel [Byte0]: 66
3438 12:29:21.851516 [Byte1]: 66
3439 12:29:21.855878
3440 12:29:21.855995 Set Vref, RX VrefLevel [Byte0]: 67
3441 12:29:21.859560 [Byte1]: 67
3442 12:29:21.863783
3443 12:29:21.863899 Final RX Vref Byte 0 = 52 to rank0
3444 12:29:21.867247 Final RX Vref Byte 1 = 50 to rank0
3445 12:29:21.870359 Final RX Vref Byte 0 = 52 to rank1
3446 12:29:21.873736 Final RX Vref Byte 1 = 50 to rank1==
3447 12:29:21.877125 Dram Type= 6, Freq= 0, CH_1, rank 0
3448 12:29:21.883912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 12:29:21.884035 ==
3450 12:29:21.884136 DQS Delay:
3451 12:29:21.884209 DQS0 = 0, DQS1 = 0
3452 12:29:21.887237 DQM Delay:
3453 12:29:21.887354 DQM0 = 119, DQM1 = 111
3454 12:29:21.890230 DQ Delay:
3455 12:29:21.893674 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =120
3456 12:29:21.897237 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3457 12:29:21.900578 DQ8 =102, DQ9 =98, DQ10 =114, DQ11 =104
3458 12:29:21.904003 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3459 12:29:21.904083
3460 12:29:21.904167
3461 12:29:21.910308 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3462 12:29:21.913743 CH1 RK0: MR19=404, MR18=417
3463 12:29:21.920212 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3464 12:29:21.920336
3465 12:29:21.923853 ----->DramcWriteLeveling(PI) begin...
3466 12:29:21.923963 ==
3467 12:29:21.927159 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 12:29:21.930129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 12:29:21.933570 ==
3470 12:29:21.933662 Write leveling (Byte 0): 25 => 25
3471 12:29:21.937108 Write leveling (Byte 1): 30 => 30
3472 12:29:21.940033 DramcWriteLeveling(PI) end<-----
3473 12:29:21.940120
3474 12:29:21.940224 ==
3475 12:29:21.943474 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 12:29:21.950392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 12:29:21.950507 ==
3478 12:29:21.950605 [Gating] SW mode calibration
3479 12:29:21.960286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3480 12:29:21.963788 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3481 12:29:21.966904 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 12:29:21.973438 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 12:29:21.976843 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 12:29:21.979937 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 12:29:21.986840 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 12:29:21.990122 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 12:29:21.993590 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)
3488 12:29:22.000144 0 15 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
3489 12:29:22.003540 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 12:29:22.006842 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 12:29:22.013587 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 12:29:22.016602 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 12:29:22.020077 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 12:29:22.027139 1 0 20 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3495 12:29:22.030362 1 0 24 | B1->B0 | 3535 2424 | 0 0 | (1 1) (0 0)
3496 12:29:22.033709 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
3497 12:29:22.040312 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 12:29:22.043716 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 12:29:22.047139 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 12:29:22.053422 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 12:29:22.056735 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 12:29:22.060233 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 12:29:22.066538 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3504 12:29:22.070032 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3505 12:29:22.073400 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 12:29:22.079848 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 12:29:22.083137 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 12:29:22.086230 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 12:29:22.093193 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 12:29:22.096161 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 12:29:22.099645 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 12:29:22.106379 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 12:29:22.109363 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 12:29:22.112790 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 12:29:22.119548 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:29:22.122544 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 12:29:22.125953 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:29:22.132490 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 12:29:22.136033 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3520 12:29:22.139479 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3521 12:29:22.142789 Total UI for P1: 0, mck2ui 16
3522 12:29:22.145844 best dqsien dly found for B0: ( 1, 3, 24)
3523 12:29:22.149331 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 12:29:22.152283 Total UI for P1: 0, mck2ui 16
3525 12:29:22.155842 best dqsien dly found for B1: ( 1, 3, 26)
3526 12:29:22.162474 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3527 12:29:22.165875 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3528 12:29:22.165988
3529 12:29:22.168872 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3530 12:29:22.172240 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3531 12:29:22.175547 [Gating] SW calibration Done
3532 12:29:22.175652 ==
3533 12:29:22.179120 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 12:29:22.182352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 12:29:22.182467 ==
3536 12:29:22.185324 RX Vref Scan: 0
3537 12:29:22.185429
3538 12:29:22.185548 RX Vref 0 -> 0, step: 1
3539 12:29:22.185655
3540 12:29:22.188769 RX Delay -40 -> 252, step: 8
3541 12:29:22.192153 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3542 12:29:22.198777 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3543 12:29:22.202183 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3544 12:29:22.205621 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3545 12:29:22.208535 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3546 12:29:22.212029 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3547 12:29:22.218481 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3548 12:29:22.221791 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3549 12:29:22.225153 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3550 12:29:22.228384 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3551 12:29:22.231793 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3552 12:29:22.238497 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3553 12:29:22.241952 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3554 12:29:22.244897 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3555 12:29:22.248360 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3556 12:29:22.251803 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3557 12:29:22.254757 ==
3558 12:29:22.258232 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 12:29:22.261704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 12:29:22.261796 ==
3561 12:29:22.261863 DQS Delay:
3562 12:29:22.264935 DQS0 = 0, DQS1 = 0
3563 12:29:22.265047 DQM Delay:
3564 12:29:22.268328 DQM0 = 121, DQM1 = 112
3565 12:29:22.268433 DQ Delay:
3566 12:29:22.271756 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3567 12:29:22.274631 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3568 12:29:22.278169 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =103
3569 12:29:22.281442 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3570 12:29:22.281531
3571 12:29:22.281603
3572 12:29:22.281719 ==
3573 12:29:22.284641 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 12:29:22.291184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 12:29:22.291289 ==
3576 12:29:22.291382
3577 12:29:22.291481
3578 12:29:22.291569 TX Vref Scan disable
3579 12:29:22.294744 == TX Byte 0 ==
3580 12:29:22.298076 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3581 12:29:22.304445 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3582 12:29:22.304552 == TX Byte 1 ==
3583 12:29:22.308044 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3584 12:29:22.314717 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3585 12:29:22.314834 ==
3586 12:29:22.318044 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 12:29:22.321033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 12:29:22.321109 ==
3589 12:29:22.332952 TX Vref=22, minBit 1, minWin=25, winSum=418
3590 12:29:22.336436 TX Vref=24, minBit 3, minWin=25, winSum=424
3591 12:29:22.339283 TX Vref=26, minBit 3, minWin=25, winSum=428
3592 12:29:22.343021 TX Vref=28, minBit 3, minWin=26, winSum=429
3593 12:29:22.346018 TX Vref=30, minBit 9, minWin=26, winSum=432
3594 12:29:22.352928 TX Vref=32, minBit 1, minWin=26, winSum=427
3595 12:29:22.355854 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3596 12:29:22.355962
3597 12:29:22.359384 Final TX Range 1 Vref 30
3598 12:29:22.359460
3599 12:29:22.359523 ==
3600 12:29:22.362755 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 12:29:22.366077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 12:29:22.369115 ==
3603 12:29:22.369196
3604 12:29:22.369262
3605 12:29:22.369323 TX Vref Scan disable
3606 12:29:22.372452 == TX Byte 0 ==
3607 12:29:22.375860 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3608 12:29:22.382812 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3609 12:29:22.382930 == TX Byte 1 ==
3610 12:29:22.385765 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3611 12:29:22.392478 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3612 12:29:22.392593
3613 12:29:22.392706 [DATLAT]
3614 12:29:22.392806 Freq=1200, CH1 RK1
3615 12:29:22.392891
3616 12:29:22.395766 DATLAT Default: 0xd
3617 12:29:22.395875 0, 0xFFFF, sum = 0
3618 12:29:22.399088 1, 0xFFFF, sum = 0
3619 12:29:22.402633 2, 0xFFFF, sum = 0
3620 12:29:22.402742 3, 0xFFFF, sum = 0
3621 12:29:22.405925 4, 0xFFFF, sum = 0
3622 12:29:22.406002 5, 0xFFFF, sum = 0
3623 12:29:22.409236 6, 0xFFFF, sum = 0
3624 12:29:22.409324 7, 0xFFFF, sum = 0
3625 12:29:22.412344 8, 0xFFFF, sum = 0
3626 12:29:22.412433 9, 0xFFFF, sum = 0
3627 12:29:22.415613 10, 0xFFFF, sum = 0
3628 12:29:22.415701 11, 0xFFFF, sum = 0
3629 12:29:22.418947 12, 0x0, sum = 1
3630 12:29:22.419035 13, 0x0, sum = 2
3631 12:29:22.422368 14, 0x0, sum = 3
3632 12:29:22.422456 15, 0x0, sum = 4
3633 12:29:22.425766 best_step = 13
3634 12:29:22.425853
3635 12:29:22.425921 ==
3636 12:29:22.429005 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 12:29:22.431962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 12:29:22.432050 ==
3639 12:29:22.432119 RX Vref Scan: 0
3640 12:29:22.435540
3641 12:29:22.435625 RX Vref 0 -> 0, step: 1
3642 12:29:22.435694
3643 12:29:22.438951 RX Delay -13 -> 252, step: 4
3644 12:29:22.445214 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3645 12:29:22.448604 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3646 12:29:22.452006 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3647 12:29:22.455473 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3648 12:29:22.458501 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3649 12:29:22.465397 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3650 12:29:22.468699 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3651 12:29:22.472054 iDelay=195, Bit 7, Center 118 (59 ~ 178) 120
3652 12:29:22.474988 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3653 12:29:22.478461 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3654 12:29:22.484872 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3655 12:29:22.488205 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3656 12:29:22.491638 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3657 12:29:22.494992 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3658 12:29:22.498360 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3659 12:29:22.504961 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3660 12:29:22.505050 ==
3661 12:29:22.508093 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 12:29:22.511304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 12:29:22.511393 ==
3664 12:29:22.511468 DQS Delay:
3665 12:29:22.514694 DQS0 = 0, DQS1 = 0
3666 12:29:22.514788 DQM Delay:
3667 12:29:22.517943 DQM0 = 119, DQM1 = 113
3668 12:29:22.518046 DQ Delay:
3669 12:29:22.521445 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3670 12:29:22.524399 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =118
3671 12:29:22.527975 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3672 12:29:22.531338 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3673 12:29:22.534580
3674 12:29:22.534663
3675 12:29:22.540972 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3676 12:29:22.544479 CH1 RK1: MR19=403, MR18=7EB
3677 12:29:22.550987 CH1_RK1: MR19=0x403, MR18=0x7EB, DQSOSC=407, MR23=63, INC=39, DEC=26
3678 12:29:22.554580 [RxdqsGatingPostProcess] freq 1200
3679 12:29:22.557497 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3680 12:29:22.561163 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 12:29:22.564591 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 12:29:22.568018 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 12:29:22.570870 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 12:29:22.574269 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 12:29:22.577544 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 12:29:22.580826 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 12:29:22.584242 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 12:29:22.587569 Pre-setting of DQS Precalculation
3689 12:29:22.591036 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3690 12:29:22.597443 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3691 12:29:22.607497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3692 12:29:22.607586
3693 12:29:22.607657
3694 12:29:22.610705 [Calibration Summary] 2400 Mbps
3695 12:29:22.610777 CH 0, Rank 0
3696 12:29:22.613870 SW Impedance : PASS
3697 12:29:22.613947 DUTY Scan : NO K
3698 12:29:22.617073 ZQ Calibration : PASS
3699 12:29:22.620652 Jitter Meter : NO K
3700 12:29:22.620741 CBT Training : PASS
3701 12:29:22.623727 Write leveling : PASS
3702 12:29:22.623814 RX DQS gating : PASS
3703 12:29:22.627374 RX DQ/DQS(RDDQC) : PASS
3704 12:29:22.630403 TX DQ/DQS : PASS
3705 12:29:22.630532 RX DATLAT : PASS
3706 12:29:22.633704 RX DQ/DQS(Engine): PASS
3707 12:29:22.637033 TX OE : NO K
3708 12:29:22.637132 All Pass.
3709 12:29:22.637227
3710 12:29:22.637288 CH 0, Rank 1
3711 12:29:22.640791 SW Impedance : PASS
3712 12:29:22.643779 DUTY Scan : NO K
3713 12:29:22.643880 ZQ Calibration : PASS
3714 12:29:22.647228 Jitter Meter : NO K
3715 12:29:22.650283 CBT Training : PASS
3716 12:29:22.650399 Write leveling : PASS
3717 12:29:22.653687 RX DQS gating : PASS
3718 12:29:22.657463 RX DQ/DQS(RDDQC) : PASS
3719 12:29:22.657548 TX DQ/DQS : PASS
3720 12:29:22.660481 RX DATLAT : PASS
3721 12:29:22.664022 RX DQ/DQS(Engine): PASS
3722 12:29:22.664107 TX OE : NO K
3723 12:29:22.664174 All Pass.
3724 12:29:22.667021
3725 12:29:22.667163 CH 1, Rank 0
3726 12:29:22.670491 SW Impedance : PASS
3727 12:29:22.670578 DUTY Scan : NO K
3728 12:29:22.673885 ZQ Calibration : PASS
3729 12:29:22.673970 Jitter Meter : NO K
3730 12:29:22.677347 CBT Training : PASS
3731 12:29:22.680615 Write leveling : PASS
3732 12:29:22.680701 RX DQS gating : PASS
3733 12:29:22.683701 RX DQ/DQS(RDDQC) : PASS
3734 12:29:22.687187 TX DQ/DQS : PASS
3735 12:29:22.687275 RX DATLAT : PASS
3736 12:29:22.690156 RX DQ/DQS(Engine): PASS
3737 12:29:22.693539 TX OE : NO K
3738 12:29:22.693624 All Pass.
3739 12:29:22.693691
3740 12:29:22.693828 CH 1, Rank 1
3741 12:29:22.697012 SW Impedance : PASS
3742 12:29:22.700363 DUTY Scan : NO K
3743 12:29:22.700469 ZQ Calibration : PASS
3744 12:29:22.703379 Jitter Meter : NO K
3745 12:29:22.706772 CBT Training : PASS
3746 12:29:22.706848 Write leveling : PASS
3747 12:29:22.710046 RX DQS gating : PASS
3748 12:29:22.713509 RX DQ/DQS(RDDQC) : PASS
3749 12:29:22.713589 TX DQ/DQS : PASS
3750 12:29:22.716717 RX DATLAT : PASS
3751 12:29:22.719928 RX DQ/DQS(Engine): PASS
3752 12:29:22.720014 TX OE : NO K
3753 12:29:22.723454 All Pass.
3754 12:29:22.723568
3755 12:29:22.723665 DramC Write-DBI off
3756 12:29:22.726651 PER_BANK_REFRESH: Hybrid Mode
3757 12:29:22.726763 TX_TRACKING: ON
3758 12:29:22.736332 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3759 12:29:22.739908 [FAST_K] Save calibration result to emmc
3760 12:29:22.742958 dramc_set_vcore_voltage set vcore to 650000
3761 12:29:22.746646 Read voltage for 600, 5
3762 12:29:22.746761 Vio18 = 0
3763 12:29:22.749636 Vcore = 650000
3764 12:29:22.749739 Vdram = 0
3765 12:29:22.749832 Vddq = 0
3766 12:29:22.753093 Vmddr = 0
3767 12:29:22.756030 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3768 12:29:22.762825 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3769 12:29:22.762913 MEM_TYPE=3, freq_sel=19
3770 12:29:22.766307 sv_algorithm_assistance_LP4_1600
3771 12:29:22.772572 ============ PULL DRAM RESETB DOWN ============
3772 12:29:22.776041 ========== PULL DRAM RESETB DOWN end =========
3773 12:29:22.779485 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3774 12:29:22.782376 ===================================
3775 12:29:22.785633 LPDDR4 DRAM CONFIGURATION
3776 12:29:22.789152 ===================================
3777 12:29:22.792608 EX_ROW_EN[0] = 0x0
3778 12:29:22.792693 EX_ROW_EN[1] = 0x0
3779 12:29:22.795578 LP4Y_EN = 0x0
3780 12:29:22.795693 WORK_FSP = 0x0
3781 12:29:22.799130 WL = 0x2
3782 12:29:22.799244 RL = 0x2
3783 12:29:22.802601 BL = 0x2
3784 12:29:22.802705 RPST = 0x0
3785 12:29:22.805618 RD_PRE = 0x0
3786 12:29:22.805705 WR_PRE = 0x1
3787 12:29:22.808958 WR_PST = 0x0
3788 12:29:22.809071 DBI_WR = 0x0
3789 12:29:22.812415 DBI_RD = 0x0
3790 12:29:22.812523 OTF = 0x1
3791 12:29:22.815648 ===================================
3792 12:29:22.819036 ===================================
3793 12:29:22.822346 ANA top config
3794 12:29:22.825586 ===================================
3795 12:29:22.829131 DLL_ASYNC_EN = 0
3796 12:29:22.829211 ALL_SLAVE_EN = 1
3797 12:29:22.832447 NEW_RANK_MODE = 1
3798 12:29:22.835506 DLL_IDLE_MODE = 1
3799 12:29:22.838605 LP45_APHY_COMB_EN = 1
3800 12:29:22.838706 TX_ODT_DIS = 1
3801 12:29:22.842242 NEW_8X_MODE = 1
3802 12:29:22.845360 ===================================
3803 12:29:22.848932 ===================================
3804 12:29:22.851994 data_rate = 1200
3805 12:29:22.855386 CKR = 1
3806 12:29:22.858788 DQ_P2S_RATIO = 8
3807 12:29:22.862041 ===================================
3808 12:29:22.864989 CA_P2S_RATIO = 8
3809 12:29:22.865115 DQ_CA_OPEN = 0
3810 12:29:22.868372 DQ_SEMI_OPEN = 0
3811 12:29:22.871916 CA_SEMI_OPEN = 0
3812 12:29:22.875303 CA_FULL_RATE = 0
3813 12:29:22.878247 DQ_CKDIV4_EN = 1
3814 12:29:22.881825 CA_CKDIV4_EN = 1
3815 12:29:22.881937 CA_PREDIV_EN = 0
3816 12:29:22.884820 PH8_DLY = 0
3817 12:29:22.888069 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3818 12:29:22.891486 DQ_AAMCK_DIV = 4
3819 12:29:22.894906 CA_AAMCK_DIV = 4
3820 12:29:22.898494 CA_ADMCK_DIV = 4
3821 12:29:22.898583 DQ_TRACK_CA_EN = 0
3822 12:29:22.901549 CA_PICK = 600
3823 12:29:22.905017 CA_MCKIO = 600
3824 12:29:22.908000 MCKIO_SEMI = 0
3825 12:29:22.911397 PLL_FREQ = 2288
3826 12:29:22.914847 DQ_UI_PI_RATIO = 32
3827 12:29:22.918175 CA_UI_PI_RATIO = 0
3828 12:29:22.921112 ===================================
3829 12:29:22.924545 ===================================
3830 12:29:22.924633 memory_type:LPDDR4
3831 12:29:22.927914 GP_NUM : 10
3832 12:29:22.931229 SRAM_EN : 1
3833 12:29:22.931316 MD32_EN : 0
3834 12:29:22.934394 ===================================
3835 12:29:22.937681 [ANA_INIT] >>>>>>>>>>>>>>
3836 12:29:22.941462 <<<<<< [CONFIGURE PHASE]: ANA_TX
3837 12:29:22.944657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3838 12:29:22.947757 ===================================
3839 12:29:22.951026 data_rate = 1200,PCW = 0X5800
3840 12:29:22.954165 ===================================
3841 12:29:22.957679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3842 12:29:22.961005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 12:29:22.967749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 12:29:22.974028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3845 12:29:22.977490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3846 12:29:22.980497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3847 12:29:22.980575 [ANA_INIT] flow start
3848 12:29:22.983927 [ANA_INIT] PLL >>>>>>>>
3849 12:29:22.987397 [ANA_INIT] PLL <<<<<<<<
3850 12:29:22.987487 [ANA_INIT] MIDPI >>>>>>>>
3851 12:29:22.990328 [ANA_INIT] MIDPI <<<<<<<<
3852 12:29:22.993926 [ANA_INIT] DLL >>>>>>>>
3853 12:29:22.994007 [ANA_INIT] flow end
3854 12:29:23.000511 ============ LP4 DIFF to SE enter ============
3855 12:29:23.003500 ============ LP4 DIFF to SE exit ============
3856 12:29:23.006839 [ANA_INIT] <<<<<<<<<<<<<
3857 12:29:23.010323 [Flow] Enable top DCM control >>>>>
3858 12:29:23.013738 [Flow] Enable top DCM control <<<<<
3859 12:29:23.013813 Enable DLL master slave shuffle
3860 12:29:23.020019 ==============================================================
3861 12:29:23.023452 Gating Mode config
3862 12:29:23.026922 ==============================================================
3863 12:29:23.030379 Config description:
3864 12:29:23.039898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3865 12:29:23.046881 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3866 12:29:23.050175 SELPH_MODE 0: By rank 1: By Phase
3867 12:29:23.056356 ==============================================================
3868 12:29:23.059565 GAT_TRACK_EN = 1
3869 12:29:23.063069 RX_GATING_MODE = 2
3870 12:29:23.066312 RX_GATING_TRACK_MODE = 2
3871 12:29:23.069840 SELPH_MODE = 1
3872 12:29:23.069928 PICG_EARLY_EN = 1
3873 12:29:23.073330 VALID_LAT_VALUE = 1
3874 12:29:23.079803 ==============================================================
3875 12:29:23.083237 Enter into Gating configuration >>>>
3876 12:29:23.086688 Exit from Gating configuration <<<<
3877 12:29:23.089604 Enter into DVFS_PRE_config >>>>>
3878 12:29:23.099779 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3879 12:29:23.102786 Exit from DVFS_PRE_config <<<<<
3880 12:29:23.106152 Enter into PICG configuration >>>>
3881 12:29:23.109631 Exit from PICG configuration <<<<
3882 12:29:23.112507 [RX_INPUT] configuration >>>>>
3883 12:29:23.116020 [RX_INPUT] configuration <<<<<
3884 12:29:23.119473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3885 12:29:23.126227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3886 12:29:23.132505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 12:29:23.139099 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 12:29:23.145894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 12:29:23.152532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 12:29:23.155766 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3891 12:29:23.159160 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3892 12:29:23.162350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3893 12:29:23.168709 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3894 12:29:23.171938 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3895 12:29:23.175622 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 12:29:23.179014 ===================================
3897 12:29:23.182012 LPDDR4 DRAM CONFIGURATION
3898 12:29:23.185487 ===================================
3899 12:29:23.185576 EX_ROW_EN[0] = 0x0
3900 12:29:23.188884 EX_ROW_EN[1] = 0x0
3901 12:29:23.191806 LP4Y_EN = 0x0
3902 12:29:23.191893 WORK_FSP = 0x0
3903 12:29:23.195266 WL = 0x2
3904 12:29:23.195382 RL = 0x2
3905 12:29:23.198585 BL = 0x2
3906 12:29:23.198672 RPST = 0x0
3907 12:29:23.201953 RD_PRE = 0x0
3908 12:29:23.202039 WR_PRE = 0x1
3909 12:29:23.204986 WR_PST = 0x0
3910 12:29:23.205101 DBI_WR = 0x0
3911 12:29:23.208480 DBI_RD = 0x0
3912 12:29:23.208566 OTF = 0x1
3913 12:29:23.211416 ===================================
3914 12:29:23.214812 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3915 12:29:23.221748 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3916 12:29:23.224693 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 12:29:23.228022 ===================================
3918 12:29:23.231369 LPDDR4 DRAM CONFIGURATION
3919 12:29:23.234848 ===================================
3920 12:29:23.234932 EX_ROW_EN[0] = 0x10
3921 12:29:23.237842 EX_ROW_EN[1] = 0x0
3922 12:29:23.241294 LP4Y_EN = 0x0
3923 12:29:23.241397 WORK_FSP = 0x0
3924 12:29:23.244955 WL = 0x2
3925 12:29:23.245058 RL = 0x2
3926 12:29:23.247942 BL = 0x2
3927 12:29:23.248052 RPST = 0x0
3928 12:29:23.251284 RD_PRE = 0x0
3929 12:29:23.251396 WR_PRE = 0x1
3930 12:29:23.254638 WR_PST = 0x0
3931 12:29:23.254727 DBI_WR = 0x0
3932 12:29:23.257390 DBI_RD = 0x0
3933 12:29:23.257503 OTF = 0x1
3934 12:29:23.260884 ===================================
3935 12:29:23.267473 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3936 12:29:23.272405 nWR fixed to 30
3937 12:29:23.275566 [ModeRegInit_LP4] CH0 RK0
3938 12:29:23.275675 [ModeRegInit_LP4] CH0 RK1
3939 12:29:23.278706 [ModeRegInit_LP4] CH1 RK0
3940 12:29:23.282261 [ModeRegInit_LP4] CH1 RK1
3941 12:29:23.282386 match AC timing 17
3942 12:29:23.288502 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3943 12:29:23.292080 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3944 12:29:23.295482 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3945 12:29:23.301745 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3946 12:29:23.305034 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3947 12:29:23.305165 ==
3948 12:29:23.308388 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 12:29:23.311819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 12:29:23.314717 ==
3951 12:29:23.318153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 12:29:23.324985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3953 12:29:23.327933 [CA 0] Center 36 (5~67) winsize 63
3954 12:29:23.331408 [CA 1] Center 36 (6~67) winsize 62
3955 12:29:23.334626 [CA 2] Center 34 (4~65) winsize 62
3956 12:29:23.338014 [CA 3] Center 34 (3~65) winsize 63
3957 12:29:23.341570 [CA 4] Center 33 (3~64) winsize 62
3958 12:29:23.344475 [CA 5] Center 33 (2~64) winsize 63
3959 12:29:23.344590
3960 12:29:23.347898 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3961 12:29:23.347986
3962 12:29:23.351213 [CATrainingPosCal] consider 1 rank data
3963 12:29:23.354550 u2DelayCellTimex100 = 270/100 ps
3964 12:29:23.357962 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3965 12:29:23.361315 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3966 12:29:23.364418 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 12:29:23.371206 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3968 12:29:23.374473 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 12:29:23.377666 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3970 12:29:23.377780
3971 12:29:23.380841 CA PerBit enable=1, Macro0, CA PI delay=33
3972 12:29:23.380951
3973 12:29:23.384522 [CBTSetCACLKResult] CA Dly = 33
3974 12:29:23.384636 CS Dly: 5 (0~36)
3975 12:29:23.384746 ==
3976 12:29:23.387563 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 12:29:23.394417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 12:29:23.394538 ==
3979 12:29:23.397402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 12:29:23.404278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3981 12:29:23.407648 [CA 0] Center 36 (6~67) winsize 62
3982 12:29:23.410956 [CA 1] Center 36 (6~67) winsize 62
3983 12:29:23.414329 [CA 2] Center 35 (5~65) winsize 61
3984 12:29:23.417297 [CA 3] Center 34 (4~65) winsize 62
3985 12:29:23.420807 [CA 4] Center 34 (3~65) winsize 63
3986 12:29:23.424363 [CA 5] Center 33 (3~64) winsize 62
3987 12:29:23.424454
3988 12:29:23.427211 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3989 12:29:23.427326
3990 12:29:23.430670 [CATrainingPosCal] consider 2 rank data
3991 12:29:23.434118 u2DelayCellTimex100 = 270/100 ps
3992 12:29:23.440374 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 12:29:23.443794 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3994 12:29:23.447113 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3995 12:29:23.450542 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 12:29:23.453843 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 12:29:23.456694 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 12:29:23.456795
3999 12:29:23.460183 CA PerBit enable=1, Macro0, CA PI delay=33
4000 12:29:23.460261
4001 12:29:23.463637 [CBTSetCACLKResult] CA Dly = 33
4002 12:29:23.466543 CS Dly: 5 (0~37)
4003 12:29:23.466637
4004 12:29:23.469829 ----->DramcWriteLeveling(PI) begin...
4005 12:29:23.469936 ==
4006 12:29:23.473591 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 12:29:23.476799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 12:29:23.476897 ==
4009 12:29:23.480156 Write leveling (Byte 0): 36 => 36
4010 12:29:23.483275 Write leveling (Byte 1): 31 => 31
4011 12:29:23.486385 DramcWriteLeveling(PI) end<-----
4012 12:29:23.486475
4013 12:29:23.486543 ==
4014 12:29:23.489725 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 12:29:23.492985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 12:29:23.493069 ==
4017 12:29:23.496463 [Gating] SW mode calibration
4018 12:29:23.503238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4019 12:29:23.509641 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4020 12:29:23.512929 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 12:29:23.516347 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 12:29:23.522775 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 12:29:23.526184 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
4024 12:29:23.529614 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
4025 12:29:23.536095 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 12:29:23.539563 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 12:29:23.542973 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 12:29:23.549249 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 12:29:23.552621 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 12:29:23.555929 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 12:29:23.562684 0 10 12 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)
4032 12:29:23.566015 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4033 12:29:23.568996 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 12:29:23.575667 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 12:29:23.578973 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 12:29:23.582250 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 12:29:23.589178 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 12:29:23.592311 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 12:29:23.595351 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 12:29:23.602268 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4041 12:29:23.605532 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 12:29:23.608552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 12:29:23.615377 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 12:29:23.618671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:29:23.622059 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:29:23.628454 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:29:23.631803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:29:23.635220 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:29:23.641999 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:29:23.645334 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:29:23.648628 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:29:23.655125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:29:23.658463 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:29:23.661587 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:29:23.668539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4056 12:29:23.671512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4057 12:29:23.674769 Total UI for P1: 0, mck2ui 16
4058 12:29:23.678109 best dqsien dly found for B0: ( 0, 13, 12)
4059 12:29:23.681533 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:29:23.684795 Total UI for P1: 0, mck2ui 16
4061 12:29:23.688083 best dqsien dly found for B1: ( 0, 13, 18)
4062 12:29:23.691308 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4063 12:29:23.694587 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4064 12:29:23.697906
4065 12:29:23.701412 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4066 12:29:23.704701 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4067 12:29:23.707991 [Gating] SW calibration Done
4068 12:29:23.708110 ==
4069 12:29:23.711239 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 12:29:23.714656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 12:29:23.714744 ==
4072 12:29:23.714812 RX Vref Scan: 0
4073 12:29:23.717635
4074 12:29:23.717720 RX Vref 0 -> 0, step: 1
4075 12:29:23.717849
4076 12:29:23.720956 RX Delay -230 -> 252, step: 16
4077 12:29:23.724339 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4078 12:29:23.731212 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4079 12:29:23.734213 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4080 12:29:23.737553 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4081 12:29:23.740910 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4082 12:29:23.747271 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4083 12:29:23.750489 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4084 12:29:23.754054 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4085 12:29:23.757499 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4086 12:29:23.760415 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4087 12:29:23.767259 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4088 12:29:23.770614 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4089 12:29:23.773869 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4090 12:29:23.776855 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4091 12:29:23.783830 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4092 12:29:23.786836 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4093 12:29:23.786946 ==
4094 12:29:23.790193 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 12:29:23.793392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 12:29:23.793500 ==
4097 12:29:23.796786 DQS Delay:
4098 12:29:23.796910 DQS0 = 0, DQS1 = 0
4099 12:29:23.800506 DQM Delay:
4100 12:29:23.800610 DQM0 = 53, DQM1 = 42
4101 12:29:23.800705 DQ Delay:
4102 12:29:23.803798 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4103 12:29:23.806963 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4104 12:29:23.810207 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4105 12:29:23.813431 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4106 12:29:23.813588
4107 12:29:23.813683
4108 12:29:23.813773 ==
4109 12:29:23.816729 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 12:29:23.823519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 12:29:23.823635 ==
4112 12:29:23.823732
4113 12:29:23.823823
4114 12:29:23.823899 TX Vref Scan disable
4115 12:29:23.827313 == TX Byte 0 ==
4116 12:29:23.830724 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4117 12:29:23.837135 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4118 12:29:23.837252 == TX Byte 1 ==
4119 12:29:23.840534 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4120 12:29:23.847448 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4121 12:29:23.847556 ==
4122 12:29:23.850500 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 12:29:23.853943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 12:29:23.854048 ==
4125 12:29:23.854140
4126 12:29:23.854246
4127 12:29:23.857227 TX Vref Scan disable
4128 12:29:23.860635 == TX Byte 0 ==
4129 12:29:23.863588 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4130 12:29:23.866974 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4131 12:29:23.870310 == TX Byte 1 ==
4132 12:29:23.873684 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 12:29:23.877142 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 12:29:23.877251
4135 12:29:23.877347 [DATLAT]
4136 12:29:23.880176 Freq=600, CH0 RK0
4137 12:29:23.880291
4138 12:29:23.883624 DATLAT Default: 0x9
4139 12:29:23.883737 0, 0xFFFF, sum = 0
4140 12:29:23.887052 1, 0xFFFF, sum = 0
4141 12:29:23.887168 2, 0xFFFF, sum = 0
4142 12:29:23.890574 3, 0xFFFF, sum = 0
4143 12:29:23.890683 4, 0xFFFF, sum = 0
4144 12:29:23.893540 5, 0xFFFF, sum = 0
4145 12:29:23.893645 6, 0xFFFF, sum = 0
4146 12:29:23.896996 7, 0xFFFF, sum = 0
4147 12:29:23.897111 8, 0x0, sum = 1
4148 12:29:23.900254 9, 0x0, sum = 2
4149 12:29:23.900373 10, 0x0, sum = 3
4150 12:29:23.903312 11, 0x0, sum = 4
4151 12:29:23.903426 best_step = 9
4152 12:29:23.903518
4153 12:29:23.903614 ==
4154 12:29:23.906834 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 12:29:23.910133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 12:29:23.910255 ==
4157 12:29:23.913278 RX Vref Scan: 1
4158 12:29:23.913381
4159 12:29:23.916812 RX Vref 0 -> 0, step: 1
4160 12:29:23.916915
4161 12:29:23.917007 RX Delay -179 -> 252, step: 8
4162 12:29:23.919843
4163 12:29:23.919949 Set Vref, RX VrefLevel [Byte0]: 61
4164 12:29:23.922955 [Byte1]: 49
4165 12:29:23.928273
4166 12:29:23.928392 Final RX Vref Byte 0 = 61 to rank0
4167 12:29:23.931516 Final RX Vref Byte 1 = 49 to rank0
4168 12:29:23.934432 Final RX Vref Byte 0 = 61 to rank1
4169 12:29:23.937782 Final RX Vref Byte 1 = 49 to rank1==
4170 12:29:23.941181 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 12:29:23.948155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 12:29:23.948262 ==
4173 12:29:23.948365 DQS Delay:
4174 12:29:23.948460 DQS0 = 0, DQS1 = 0
4175 12:29:23.951116 DQM Delay:
4176 12:29:23.951221 DQM0 = 48, DQM1 = 37
4177 12:29:23.954525 DQ Delay:
4178 12:29:23.957479 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4179 12:29:23.960723 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4180 12:29:23.964026 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4181 12:29:23.967476 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4182 12:29:23.967574
4183 12:29:23.967665
4184 12:29:23.974207 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4185 12:29:23.977134 CH0 RK0: MR19=808, MR18=5B56
4186 12:29:23.983902 CH0_RK0: MR19=0x808, MR18=0x5B56, DQSOSC=392, MR23=63, INC=170, DEC=113
4187 12:29:23.984007
4188 12:29:23.986957 ----->DramcWriteLeveling(PI) begin...
4189 12:29:23.987064 ==
4190 12:29:23.990307 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 12:29:23.993792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 12:29:23.993897 ==
4193 12:29:23.997273 Write leveling (Byte 0): 33 => 33
4194 12:29:24.000304 Write leveling (Byte 1): 33 => 33
4195 12:29:24.003688 DramcWriteLeveling(PI) end<-----
4196 12:29:24.003792
4197 12:29:24.003886 ==
4198 12:29:24.006958 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 12:29:24.010195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 12:29:24.013689 ==
4201 12:29:24.013786 [Gating] SW mode calibration
4202 12:29:24.023691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4203 12:29:24.027142 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4204 12:29:24.030249 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 12:29:24.036614 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 12:29:24.040100 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 12:29:24.043587 0 9 12 | B1->B0 | 3131 3030 | 1 1 | (1 0) (1 1)
4208 12:29:24.050003 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4209 12:29:24.053462 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 12:29:24.056886 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 12:29:24.063123 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 12:29:24.066611 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 12:29:24.069928 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 12:29:24.076246 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 12:29:24.079542 0 10 12 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
4216 12:29:24.082864 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
4217 12:29:24.089720 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 12:29:24.093187 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 12:29:24.096205 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 12:29:24.102984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 12:29:24.106345 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 12:29:24.109699 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 12:29:24.116354 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4224 12:29:24.119315 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4225 12:29:24.122585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 12:29:24.129324 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 12:29:24.132514 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:29:24.136096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 12:29:24.142439 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 12:29:24.145796 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 12:29:24.149340 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 12:29:24.155666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 12:29:24.159267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 12:29:24.162150 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 12:29:24.168836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:29:24.172171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 12:29:24.175437 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 12:29:24.181849 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:29:24.185221 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4240 12:29:24.188571 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 12:29:24.191611 Total UI for P1: 0, mck2ui 16
4242 12:29:24.195072 best dqsien dly found for B0: ( 0, 13, 12)
4243 12:29:24.198515 Total UI for P1: 0, mck2ui 16
4244 12:29:24.201495 best dqsien dly found for B1: ( 0, 13, 12)
4245 12:29:24.204967 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4246 12:29:24.208446 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4247 12:29:24.211398
4248 12:29:24.214665 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4249 12:29:24.218316 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4250 12:29:24.221316 [Gating] SW calibration Done
4251 12:29:24.221396 ==
4252 12:29:24.224678 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 12:29:24.228034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 12:29:24.228141 ==
4255 12:29:24.228237 RX Vref Scan: 0
4256 12:29:24.231196
4257 12:29:24.231311 RX Vref 0 -> 0, step: 1
4258 12:29:24.231418
4259 12:29:24.234415 RX Delay -230 -> 252, step: 16
4260 12:29:24.237956 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4261 12:29:24.244411 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4262 12:29:24.247941 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4263 12:29:24.251114 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4264 12:29:24.254517 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4265 12:29:24.260860 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4266 12:29:24.264354 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4267 12:29:24.267683 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4268 12:29:24.271092 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4269 12:29:24.274410 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4270 12:29:24.280805 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4271 12:29:24.284047 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4272 12:29:24.287272 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4273 12:29:24.290564 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4274 12:29:24.297493 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4275 12:29:24.300472 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4276 12:29:24.300563 ==
4277 12:29:24.303929 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 12:29:24.307341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 12:29:24.307426 ==
4280 12:29:24.310793 DQS Delay:
4281 12:29:24.310876 DQS0 = 0, DQS1 = 0
4282 12:29:24.313681 DQM Delay:
4283 12:29:24.313791 DQM0 = 49, DQM1 = 42
4284 12:29:24.313887 DQ Delay:
4285 12:29:24.317139 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4286 12:29:24.320348 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4287 12:29:24.323744 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4288 12:29:24.327119 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4289 12:29:24.327203
4290 12:29:24.327271
4291 12:29:24.330075 ==
4292 12:29:24.330169 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 12:29:24.336685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 12:29:24.336812 ==
4295 12:29:24.336893
4296 12:29:24.336959
4297 12:29:24.340022 TX Vref Scan disable
4298 12:29:24.340110 == TX Byte 0 ==
4299 12:29:24.346534 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4300 12:29:24.350240 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4301 12:29:24.350331 == TX Byte 1 ==
4302 12:29:24.356597 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4303 12:29:24.359722 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4304 12:29:24.359847 ==
4305 12:29:24.363489 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 12:29:24.366469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 12:29:24.366559 ==
4308 12:29:24.366633
4309 12:29:24.366697
4310 12:29:24.369819 TX Vref Scan disable
4311 12:29:24.373236 == TX Byte 0 ==
4312 12:29:24.376496 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4313 12:29:24.379724 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4314 12:29:24.383217 == TX Byte 1 ==
4315 12:29:24.386601 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4316 12:29:24.389795 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4317 12:29:24.389913
4318 12:29:24.393122 [DATLAT]
4319 12:29:24.393231 Freq=600, CH0 RK1
4320 12:29:24.393328
4321 12:29:24.396161 DATLAT Default: 0x9
4322 12:29:24.396274 0, 0xFFFF, sum = 0
4323 12:29:24.399472 1, 0xFFFF, sum = 0
4324 12:29:24.399563 2, 0xFFFF, sum = 0
4325 12:29:24.402799 3, 0xFFFF, sum = 0
4326 12:29:24.402915 4, 0xFFFF, sum = 0
4327 12:29:24.406224 5, 0xFFFF, sum = 0
4328 12:29:24.406346 6, 0xFFFF, sum = 0
4329 12:29:24.409594 7, 0xFFFF, sum = 0
4330 12:29:24.409705 8, 0x0, sum = 1
4331 12:29:24.412989 9, 0x0, sum = 2
4332 12:29:24.413097 10, 0x0, sum = 3
4333 12:29:24.416162 11, 0x0, sum = 4
4334 12:29:24.416270 best_step = 9
4335 12:29:24.416363
4336 12:29:24.416454 ==
4337 12:29:24.419182 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 12:29:24.425874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 12:29:24.425960 ==
4340 12:29:24.426027 RX Vref Scan: 0
4341 12:29:24.426090
4342 12:29:24.429302 RX Vref 0 -> 0, step: 1
4343 12:29:24.429418
4344 12:29:24.432308 RX Delay -179 -> 252, step: 8
4345 12:29:24.435645 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4346 12:29:24.442423 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4347 12:29:24.445841 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4348 12:29:24.449168 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4349 12:29:24.452273 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4350 12:29:24.455804 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4351 12:29:24.462520 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4352 12:29:24.465731 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4353 12:29:24.468740 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4354 12:29:24.472148 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4355 12:29:24.475605 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4356 12:29:24.482359 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4357 12:29:24.485819 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4358 12:29:24.488717 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4359 12:29:24.492088 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4360 12:29:24.498721 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4361 12:29:24.498838 ==
4362 12:29:24.502287 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 12:29:24.505360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 12:29:24.505474 ==
4365 12:29:24.505573 DQS Delay:
4366 12:29:24.508699 DQS0 = 0, DQS1 = 0
4367 12:29:24.508816 DQM Delay:
4368 12:29:24.512284 DQM0 = 49, DQM1 = 41
4369 12:29:24.512397 DQ Delay:
4370 12:29:24.515139 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4371 12:29:24.518707 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4372 12:29:24.522203 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4373 12:29:24.525420 DQ12 =44, DQ13 =48, DQ14 =52, DQ15 =52
4374 12:29:24.525531
4375 12:29:24.525611
4376 12:29:24.531582 [DQSOSCAuto] RK1, (LSB)MR18= 0x6734, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4377 12:29:24.534971 CH0 RK1: MR19=808, MR18=6734
4378 12:29:24.541898 CH0_RK1: MR19=0x808, MR18=0x6734, DQSOSC=390, MR23=63, INC=172, DEC=114
4379 12:29:24.545258 [RxdqsGatingPostProcess] freq 600
4380 12:29:24.551520 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 12:29:24.555159 Pre-setting of DQS Precalculation
4382 12:29:24.558255 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 12:29:24.558335 ==
4384 12:29:24.561518 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 12:29:24.565005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 12:29:24.565105 ==
4387 12:29:24.571338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 12:29:24.578211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4389 12:29:24.581479 [CA 0] Center 35 (5~66) winsize 62
4390 12:29:24.584773 [CA 1] Center 35 (5~66) winsize 62
4391 12:29:24.588024 [CA 2] Center 34 (4~65) winsize 62
4392 12:29:24.591356 [CA 3] Center 33 (3~64) winsize 62
4393 12:29:24.594785 [CA 4] Center 34 (3~65) winsize 63
4394 12:29:24.598146 [CA 5] Center 33 (3~64) winsize 62
4395 12:29:24.598254
4396 12:29:24.601388 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4397 12:29:24.601502
4398 12:29:24.604341 [CATrainingPosCal] consider 1 rank data
4399 12:29:24.607839 u2DelayCellTimex100 = 270/100 ps
4400 12:29:24.611264 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 12:29:24.614592 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 12:29:24.617543 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 12:29:24.620953 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 12:29:24.627899 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4405 12:29:24.630846 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 12:29:24.630960
4407 12:29:24.634297 CA PerBit enable=1, Macro0, CA PI delay=33
4408 12:29:24.634392
4409 12:29:24.637641 [CBTSetCACLKResult] CA Dly = 33
4410 12:29:24.637729 CS Dly: 4 (0~35)
4411 12:29:24.637804 ==
4412 12:29:24.640944 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 12:29:24.647396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 12:29:24.647520 ==
4415 12:29:24.650720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 12:29:24.657544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4417 12:29:24.660477 [CA 0] Center 35 (5~66) winsize 62
4418 12:29:24.664176 [CA 1] Center 35 (5~66) winsize 62
4419 12:29:24.667348 [CA 2] Center 34 (4~65) winsize 62
4420 12:29:24.670522 [CA 3] Center 34 (4~65) winsize 62
4421 12:29:24.673680 [CA 4] Center 34 (4~65) winsize 62
4422 12:29:24.677274 [CA 5] Center 33 (3~64) winsize 62
4423 12:29:24.677391
4424 12:29:24.680340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4425 12:29:24.680444
4426 12:29:24.683902 [CATrainingPosCal] consider 2 rank data
4427 12:29:24.687126 u2DelayCellTimex100 = 270/100 ps
4428 12:29:24.690582 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 12:29:24.697339 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 12:29:24.700143 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 12:29:24.703929 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4432 12:29:24.706893 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 12:29:24.710298 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 12:29:24.710406
4435 12:29:24.713794 CA PerBit enable=1, Macro0, CA PI delay=33
4436 12:29:24.713873
4437 12:29:24.716646 [CBTSetCACLKResult] CA Dly = 33
4438 12:29:24.720159 CS Dly: 4 (0~36)
4439 12:29:24.720258
4440 12:29:24.723549 ----->DramcWriteLeveling(PI) begin...
4441 12:29:24.723652 ==
4442 12:29:24.726525 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 12:29:24.730049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 12:29:24.730121 ==
4445 12:29:24.733476 Write leveling (Byte 0): 29 => 29
4446 12:29:24.736326 Write leveling (Byte 1): 30 => 30
4447 12:29:24.739651 DramcWriteLeveling(PI) end<-----
4448 12:29:24.739745
4449 12:29:24.739816 ==
4450 12:29:24.743077 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 12:29:24.746549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 12:29:24.746636 ==
4453 12:29:24.749829 [Gating] SW mode calibration
4454 12:29:24.756232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 12:29:24.762655 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 12:29:24.765960 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 12:29:24.769406 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 12:29:24.775811 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4459 12:29:24.779385 0 9 12 | B1->B0 | 2d2d 2b2b | 1 1 | (1 0) (1 0)
4460 12:29:24.782505 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 12:29:24.789364 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 12:29:24.792680 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 12:29:24.795793 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 12:29:24.802447 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 12:29:24.805821 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 12:29:24.809076 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4467 12:29:24.815578 0 10 12 | B1->B0 | 3838 3d3d | 1 1 | (0 0) (1 1)
4468 12:29:24.818614 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 12:29:24.821995 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 12:29:24.828699 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 12:29:24.832159 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 12:29:24.835154 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 12:29:24.842107 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 12:29:24.845477 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4475 12:29:24.848438 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4476 12:29:24.855170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:29:24.858641 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:29:24.861610 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:29:24.868143 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:29:24.871571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:29:24.874909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:29:24.881550 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:29:24.884720 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:29:24.888286 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:29:24.894869 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:29:24.897918 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:29:24.901657 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:29:24.907968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:29:24.911504 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:29:24.914827 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4491 12:29:24.921178 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 12:29:24.924617 Total UI for P1: 0, mck2ui 16
4493 12:29:24.927972 best dqsien dly found for B0: ( 0, 13, 8)
4494 12:29:24.928061 Total UI for P1: 0, mck2ui 16
4495 12:29:24.934492 best dqsien dly found for B1: ( 0, 13, 10)
4496 12:29:24.937840 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4497 12:29:24.940785 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4498 12:29:24.940913
4499 12:29:24.944029 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4500 12:29:24.947404 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4501 12:29:24.950802 [Gating] SW calibration Done
4502 12:29:24.950887 ==
4503 12:29:24.954269 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 12:29:24.957615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 12:29:24.957716 ==
4506 12:29:24.960961 RX Vref Scan: 0
4507 12:29:24.961047
4508 12:29:24.963859 RX Vref 0 -> 0, step: 1
4509 12:29:24.963930
4510 12:29:24.963994 RX Delay -230 -> 252, step: 16
4511 12:29:24.970821 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4512 12:29:24.973655 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4513 12:29:24.977168 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4514 12:29:24.980638 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4515 12:29:24.987195 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4516 12:29:24.990411 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4517 12:29:24.993583 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4518 12:29:24.997052 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4519 12:29:25.000289 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4520 12:29:25.006669 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4521 12:29:25.009881 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4522 12:29:25.013265 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4523 12:29:25.019913 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4524 12:29:25.023325 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4525 12:29:25.026875 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4526 12:29:25.029804 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4527 12:29:25.029892 ==
4528 12:29:25.033146 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 12:29:25.040042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 12:29:25.040146 ==
4531 12:29:25.040216 DQS Delay:
4532 12:29:25.040285 DQS0 = 0, DQS1 = 0
4533 12:29:25.043438 DQM Delay:
4534 12:29:25.043560 DQM0 = 51, DQM1 = 41
4535 12:29:25.046502 DQ Delay:
4536 12:29:25.049721 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4537 12:29:25.053303 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4538 12:29:25.053388 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4539 12:29:25.059748 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4540 12:29:25.059836
4541 12:29:25.059903
4542 12:29:25.059965 ==
4543 12:29:25.063419 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 12:29:25.066481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 12:29:25.066567 ==
4546 12:29:25.066633
4547 12:29:25.066693
4548 12:29:25.069953 TX Vref Scan disable
4549 12:29:25.070027 == TX Byte 0 ==
4550 12:29:25.076246 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4551 12:29:25.079661 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4552 12:29:25.079772 == TX Byte 1 ==
4553 12:29:25.086098 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4554 12:29:25.089579 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4555 12:29:25.089659 ==
4556 12:29:25.092933 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 12:29:25.096221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 12:29:25.096300 ==
4559 12:29:25.099350
4560 12:29:25.099447
4561 12:29:25.099551 TX Vref Scan disable
4562 12:29:25.102967 == TX Byte 0 ==
4563 12:29:25.106391 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4564 12:29:25.112753 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4565 12:29:25.112905 == TX Byte 1 ==
4566 12:29:25.115884 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 12:29:25.122758 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 12:29:25.122840
4569 12:29:25.122907 [DATLAT]
4570 12:29:25.122976 Freq=600, CH1 RK0
4571 12:29:25.123055
4572 12:29:25.125989 DATLAT Default: 0x9
4573 12:29:25.129430 0, 0xFFFF, sum = 0
4574 12:29:25.129512 1, 0xFFFF, sum = 0
4575 12:29:25.132342 2, 0xFFFF, sum = 0
4576 12:29:25.132453 3, 0xFFFF, sum = 0
4577 12:29:25.135665 4, 0xFFFF, sum = 0
4578 12:29:25.135764 5, 0xFFFF, sum = 0
4579 12:29:25.139077 6, 0xFFFF, sum = 0
4580 12:29:25.139179 7, 0xFFFF, sum = 0
4581 12:29:25.142548 8, 0x0, sum = 1
4582 12:29:25.142629 9, 0x0, sum = 2
4583 12:29:25.145640 10, 0x0, sum = 3
4584 12:29:25.145728 11, 0x0, sum = 4
4585 12:29:25.145834 best_step = 9
4586 12:29:25.145896
4587 12:29:25.149122 ==
4588 12:29:25.152426 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 12:29:25.155653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 12:29:25.155753 ==
4591 12:29:25.155819 RX Vref Scan: 1
4592 12:29:25.155895
4593 12:29:25.158987 RX Vref 0 -> 0, step: 1
4594 12:29:25.159070
4595 12:29:25.162151 RX Delay -179 -> 252, step: 8
4596 12:29:25.162243
4597 12:29:25.165446 Set Vref, RX VrefLevel [Byte0]: 52
4598 12:29:25.168621 [Byte1]: 50
4599 12:29:25.168707
4600 12:29:25.172195 Final RX Vref Byte 0 = 52 to rank0
4601 12:29:25.175538 Final RX Vref Byte 1 = 50 to rank0
4602 12:29:25.178552 Final RX Vref Byte 0 = 52 to rank1
4603 12:29:25.182048 Final RX Vref Byte 1 = 50 to rank1==
4604 12:29:25.185449 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 12:29:25.188410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 12:29:25.191942 ==
4607 12:29:25.192021 DQS Delay:
4608 12:29:25.192101 DQS0 = 0, DQS1 = 0
4609 12:29:25.195362 DQM Delay:
4610 12:29:25.195463 DQM0 = 49, DQM1 = 40
4611 12:29:25.198259 DQ Delay:
4612 12:29:25.198387 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4613 12:29:25.201833 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4614 12:29:25.205033 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =36
4615 12:29:25.208504 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4616 12:29:25.211798
4617 12:29:25.211886
4618 12:29:25.218195 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4619 12:29:25.221370 CH1 RK0: MR19=808, MR18=496F
4620 12:29:25.228052 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4621 12:29:25.228209
4622 12:29:25.231428 ----->DramcWriteLeveling(PI) begin...
4623 12:29:25.231548 ==
4624 12:29:25.234774 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 12:29:25.237772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 12:29:25.237895 ==
4627 12:29:25.241378 Write leveling (Byte 0): 28 => 28
4628 12:29:25.244777 Write leveling (Byte 1): 28 => 28
4629 12:29:25.247854 DramcWriteLeveling(PI) end<-----
4630 12:29:25.247970
4631 12:29:25.248069 ==
4632 12:29:25.250938 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 12:29:25.254469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 12:29:25.254558 ==
4635 12:29:25.257875 [Gating] SW mode calibration
4636 12:29:25.264264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4637 12:29:25.271018 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4638 12:29:25.274504 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4639 12:29:25.280971 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 12:29:25.283958 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4641 12:29:25.287532 0 9 12 | B1->B0 | 2929 3333 | 0 1 | (1 1) (1 0)
4642 12:29:25.294079 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 12:29:25.297553 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 12:29:25.300582 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 12:29:25.307374 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 12:29:25.310647 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 12:29:25.313911 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 12:29:25.320730 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4649 12:29:25.324151 0 10 12 | B1->B0 | 4242 2f2f | 0 1 | (0 0) (0 0)
4650 12:29:25.327205 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 12:29:25.333656 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 12:29:25.336933 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 12:29:25.340536 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 12:29:25.347163 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 12:29:25.350159 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 12:29:25.353729 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 12:29:25.357209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4658 12:29:25.363473 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:29:25.366965 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:29:25.373571 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:29:25.376496 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 12:29:25.380125 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 12:29:25.386715 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 12:29:25.389754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:29:25.393281 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:29:25.396337 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:29:25.403450 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 12:29:25.406445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 12:29:25.409946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:29:25.416415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:29:25.419576 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:29:25.423192 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:29:25.429691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:29:25.432980 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 12:29:25.436256 Total UI for P1: 0, mck2ui 16
4676 12:29:25.439583 best dqsien dly found for B0: ( 0, 13, 14)
4677 12:29:25.442835 Total UI for P1: 0, mck2ui 16
4678 12:29:25.446070 best dqsien dly found for B1: ( 0, 13, 14)
4679 12:29:25.449350 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4680 12:29:25.452800 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4681 12:29:25.452914
4682 12:29:25.456202 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4683 12:29:25.462716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4684 12:29:25.462806 [Gating] SW calibration Done
4685 12:29:25.462896 ==
4686 12:29:25.466179 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 12:29:25.472691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 12:29:25.472791 ==
4689 12:29:25.472877 RX Vref Scan: 0
4690 12:29:25.472966
4691 12:29:25.476279 RX Vref 0 -> 0, step: 1
4692 12:29:25.476357
4693 12:29:25.479177 RX Delay -230 -> 252, step: 16
4694 12:29:25.482654 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4695 12:29:25.486181 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4696 12:29:25.489170 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4697 12:29:25.495711 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4698 12:29:25.499353 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4699 12:29:25.502276 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4700 12:29:25.505805 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4701 12:29:25.512431 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4702 12:29:25.515834 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4703 12:29:25.519234 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4704 12:29:25.522293 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4705 12:29:25.525582 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4706 12:29:25.532482 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4707 12:29:25.535546 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4708 12:29:25.539218 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4709 12:29:25.542308 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4710 12:29:25.545499 ==
4711 12:29:25.548901 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 12:29:25.552152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 12:29:25.552272 ==
4714 12:29:25.552384 DQS Delay:
4715 12:29:25.555384 DQS0 = 0, DQS1 = 0
4716 12:29:25.555470 DQM Delay:
4717 12:29:25.558845 DQM0 = 52, DQM1 = 46
4718 12:29:25.558934 DQ Delay:
4719 12:29:25.561943 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4720 12:29:25.565385 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4721 12:29:25.568820 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4722 12:29:25.571752 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4723 12:29:25.571859
4724 12:29:25.571960
4725 12:29:25.572055 ==
4726 12:29:25.575352 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 12:29:25.578315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 12:29:25.578390 ==
4729 12:29:25.578456
4730 12:29:25.578517
4731 12:29:25.581793 TX Vref Scan disable
4732 12:29:25.585360 == TX Byte 0 ==
4733 12:29:25.588281 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4734 12:29:25.591777 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4735 12:29:25.594805 == TX Byte 1 ==
4736 12:29:25.598196 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4737 12:29:25.601782 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4738 12:29:25.601931 ==
4739 12:29:25.604883 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 12:29:25.611388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 12:29:25.611512 ==
4742 12:29:25.611616
4743 12:29:25.611716
4744 12:29:25.611807 TX Vref Scan disable
4745 12:29:25.615840 == TX Byte 0 ==
4746 12:29:25.619315 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4747 12:29:25.625701 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4748 12:29:25.625783 == TX Byte 1 ==
4749 12:29:25.629698 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4750 12:29:25.635428 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4751 12:29:25.635539
4752 12:29:25.635634 [DATLAT]
4753 12:29:25.635726 Freq=600, CH1 RK1
4754 12:29:25.635820
4755 12:29:25.638818 DATLAT Default: 0x9
4756 12:29:25.642332 0, 0xFFFF, sum = 0
4757 12:29:25.642427 1, 0xFFFF, sum = 0
4758 12:29:25.645452 2, 0xFFFF, sum = 0
4759 12:29:25.645532 3, 0xFFFF, sum = 0
4760 12:29:25.648695 4, 0xFFFF, sum = 0
4761 12:29:25.648806 5, 0xFFFF, sum = 0
4762 12:29:25.652192 6, 0xFFFF, sum = 0
4763 12:29:25.652302 7, 0xFFFF, sum = 0
4764 12:29:25.655559 8, 0x0, sum = 1
4765 12:29:25.655638 9, 0x0, sum = 2
4766 12:29:25.658828 10, 0x0, sum = 3
4767 12:29:25.658914 11, 0x0, sum = 4
4768 12:29:25.658980 best_step = 9
4769 12:29:25.659044
4770 12:29:25.662011 ==
4771 12:29:25.665423 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 12:29:25.668493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 12:29:25.668599 ==
4774 12:29:25.668697 RX Vref Scan: 0
4775 12:29:25.668803
4776 12:29:25.671975 RX Vref 0 -> 0, step: 1
4777 12:29:25.672094
4778 12:29:25.674942 RX Delay -163 -> 252, step: 8
4779 12:29:25.682006 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4780 12:29:25.685116 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4781 12:29:25.688478 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4782 12:29:25.691508 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4783 12:29:25.694963 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4784 12:29:25.701701 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4785 12:29:25.704690 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4786 12:29:25.708205 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4787 12:29:25.711237 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4788 12:29:25.714763 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4789 12:29:25.721212 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4790 12:29:25.724312 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4791 12:29:25.727789 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4792 12:29:25.731279 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4793 12:29:25.737859 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4794 12:29:25.740707 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4795 12:29:25.740841 ==
4796 12:29:25.744020 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 12:29:25.747622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 12:29:25.747732 ==
4799 12:29:25.751013 DQS Delay:
4800 12:29:25.751095 DQS0 = 0, DQS1 = 0
4801 12:29:25.751163 DQM Delay:
4802 12:29:25.754313 DQM0 = 49, DQM1 = 43
4803 12:29:25.754389 DQ Delay:
4804 12:29:25.757634 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4805 12:29:25.760710 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4806 12:29:25.764130 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4807 12:29:25.767224 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4808 12:29:25.767326
4809 12:29:25.767396
4810 12:29:25.777256 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4811 12:29:25.777412 CH1 RK1: MR19=808, MR18=5B21
4812 12:29:25.784308 CH1_RK1: MR19=0x808, MR18=0x5B21, DQSOSC=392, MR23=63, INC=170, DEC=113
4813 12:29:25.787378 [RxdqsGatingPostProcess] freq 600
4814 12:29:25.793716 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4815 12:29:25.797226 Pre-setting of DQS Precalculation
4816 12:29:25.800697 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4817 12:29:25.810331 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4818 12:29:25.816730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4819 12:29:25.816889
4820 12:29:25.816961
4821 12:29:25.820198 [Calibration Summary] 1200 Mbps
4822 12:29:25.820328 CH 0, Rank 0
4823 12:29:25.823527 SW Impedance : PASS
4824 12:29:25.823647 DUTY Scan : NO K
4825 12:29:25.827057 ZQ Calibration : PASS
4826 12:29:25.829986 Jitter Meter : NO K
4827 12:29:25.830100 CBT Training : PASS
4828 12:29:25.833565 Write leveling : PASS
4829 12:29:25.836633 RX DQS gating : PASS
4830 12:29:25.836752 RX DQ/DQS(RDDQC) : PASS
4831 12:29:25.840079 TX DQ/DQS : PASS
4832 12:29:25.843048 RX DATLAT : PASS
4833 12:29:25.843170 RX DQ/DQS(Engine): PASS
4834 12:29:25.846627 TX OE : NO K
4835 12:29:25.846715 All Pass.
4836 12:29:25.846781
4837 12:29:25.850137 CH 0, Rank 1
4838 12:29:25.850220 SW Impedance : PASS
4839 12:29:25.853449 DUTY Scan : NO K
4840 12:29:25.856488 ZQ Calibration : PASS
4841 12:29:25.856608 Jitter Meter : NO K
4842 12:29:25.859725 CBT Training : PASS
4843 12:29:25.859829 Write leveling : PASS
4844 12:29:25.863443 RX DQS gating : PASS
4845 12:29:25.866600 RX DQ/DQS(RDDQC) : PASS
4846 12:29:25.866727 TX DQ/DQS : PASS
4847 12:29:25.869908 RX DATLAT : PASS
4848 12:29:25.873024 RX DQ/DQS(Engine): PASS
4849 12:29:25.873152 TX OE : NO K
4850 12:29:25.876593 All Pass.
4851 12:29:25.876707
4852 12:29:25.876814 CH 1, Rank 0
4853 12:29:25.879829 SW Impedance : PASS
4854 12:29:25.879942 DUTY Scan : NO K
4855 12:29:25.883083 ZQ Calibration : PASS
4856 12:29:25.886466 Jitter Meter : NO K
4857 12:29:25.886575 CBT Training : PASS
4858 12:29:25.889427 Write leveling : PASS
4859 12:29:25.893034 RX DQS gating : PASS
4860 12:29:25.893137 RX DQ/DQS(RDDQC) : PASS
4861 12:29:25.896495 TX DQ/DQS : PASS
4862 12:29:25.899517 RX DATLAT : PASS
4863 12:29:25.899619 RX DQ/DQS(Engine): PASS
4864 12:29:25.903086 TX OE : NO K
4865 12:29:25.903188 All Pass.
4866 12:29:25.903294
4867 12:29:25.906186 CH 1, Rank 1
4868 12:29:25.906273 SW Impedance : PASS
4869 12:29:25.909233 DUTY Scan : NO K
4870 12:29:25.912685 ZQ Calibration : PASS
4871 12:29:25.912808 Jitter Meter : NO K
4872 12:29:25.916196 CBT Training : PASS
4873 12:29:25.919267 Write leveling : PASS
4874 12:29:25.919389 RX DQS gating : PASS
4875 12:29:25.922692 RX DQ/DQS(RDDQC) : PASS
4876 12:29:25.922793 TX DQ/DQS : PASS
4877 12:29:25.926213 RX DATLAT : PASS
4878 12:29:25.929222 RX DQ/DQS(Engine): PASS
4879 12:29:25.929350 TX OE : NO K
4880 12:29:25.932829 All Pass.
4881 12:29:25.932935
4882 12:29:25.933028 DramC Write-DBI off
4883 12:29:25.935801 PER_BANK_REFRESH: Hybrid Mode
4884 12:29:25.939320 TX_TRACKING: ON
4885 12:29:25.945876 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4886 12:29:25.949341 [FAST_K] Save calibration result to emmc
4887 12:29:25.955678 dramc_set_vcore_voltage set vcore to 662500
4888 12:29:25.955760 Read voltage for 933, 3
4889 12:29:25.955826 Vio18 = 0
4890 12:29:25.958964 Vcore = 662500
4891 12:29:25.959066 Vdram = 0
4892 12:29:25.959163 Vddq = 0
4893 12:29:25.962189 Vmddr = 0
4894 12:29:25.965871 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4895 12:29:25.972263 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4896 12:29:25.972341 MEM_TYPE=3, freq_sel=17
4897 12:29:25.975525 sv_algorithm_assistance_LP4_1600
4898 12:29:25.982078 ============ PULL DRAM RESETB DOWN ============
4899 12:29:25.985691 ========== PULL DRAM RESETB DOWN end =========
4900 12:29:25.988949 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4901 12:29:25.992107 ===================================
4902 12:29:25.995528 LPDDR4 DRAM CONFIGURATION
4903 12:29:25.998989 ===================================
4904 12:29:26.001922 EX_ROW_EN[0] = 0x0
4905 12:29:26.002034 EX_ROW_EN[1] = 0x0
4906 12:29:26.005489 LP4Y_EN = 0x0
4907 12:29:26.005576 WORK_FSP = 0x0
4908 12:29:26.008491 WL = 0x3
4909 12:29:26.008590 RL = 0x3
4910 12:29:26.012005 BL = 0x2
4911 12:29:26.012083 RPST = 0x0
4912 12:29:26.015012 RD_PRE = 0x0
4913 12:29:26.015090 WR_PRE = 0x1
4914 12:29:26.018588 WR_PST = 0x0
4915 12:29:26.018665 DBI_WR = 0x0
4916 12:29:26.021624 DBI_RD = 0x0
4917 12:29:26.021696 OTF = 0x1
4918 12:29:26.025130 ===================================
4919 12:29:26.028636 ===================================
4920 12:29:26.031660 ANA top config
4921 12:29:26.035220 ===================================
4922 12:29:26.038218 DLL_ASYNC_EN = 0
4923 12:29:26.038295 ALL_SLAVE_EN = 1
4924 12:29:26.041784 NEW_RANK_MODE = 1
4925 12:29:26.044757 DLL_IDLE_MODE = 1
4926 12:29:26.048135 LP45_APHY_COMB_EN = 1
4927 12:29:26.051571 TX_ODT_DIS = 1
4928 12:29:26.051643 NEW_8X_MODE = 1
4929 12:29:26.054610 ===================================
4930 12:29:26.058177 ===================================
4931 12:29:26.061286 data_rate = 1866
4932 12:29:26.064659 CKR = 1
4933 12:29:26.068215 DQ_P2S_RATIO = 8
4934 12:29:26.071503 ===================================
4935 12:29:26.074722 CA_P2S_RATIO = 8
4936 12:29:26.078003 DQ_CA_OPEN = 0
4937 12:29:26.078088 DQ_SEMI_OPEN = 0
4938 12:29:26.080978 CA_SEMI_OPEN = 0
4939 12:29:26.084434 CA_FULL_RATE = 0
4940 12:29:26.087695 DQ_CKDIV4_EN = 1
4941 12:29:26.090964 CA_CKDIV4_EN = 1
4942 12:29:26.094518 CA_PREDIV_EN = 0
4943 12:29:26.094603 PH8_DLY = 0
4944 12:29:26.097881 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4945 12:29:26.101026 DQ_AAMCK_DIV = 4
4946 12:29:26.104226 CA_AAMCK_DIV = 4
4947 12:29:26.107726 CA_ADMCK_DIV = 4
4948 12:29:26.110700 DQ_TRACK_CA_EN = 0
4949 12:29:26.114247 CA_PICK = 933
4950 12:29:26.114351 CA_MCKIO = 933
4951 12:29:26.117209 MCKIO_SEMI = 0
4952 12:29:26.120788 PLL_FREQ = 3732
4953 12:29:26.123815 DQ_UI_PI_RATIO = 32
4954 12:29:26.127354 CA_UI_PI_RATIO = 0
4955 12:29:26.130389 ===================================
4956 12:29:26.133839 ===================================
4957 12:29:26.137316 memory_type:LPDDR4
4958 12:29:26.137396 GP_NUM : 10
4959 12:29:26.140424 SRAM_EN : 1
4960 12:29:26.140541 MD32_EN : 0
4961 12:29:26.143851 ===================================
4962 12:29:26.146813 [ANA_INIT] >>>>>>>>>>>>>>
4963 12:29:26.150433 <<<<<< [CONFIGURE PHASE]: ANA_TX
4964 12:29:26.153458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4965 12:29:26.156991 ===================================
4966 12:29:26.160115 data_rate = 1866,PCW = 0X8f00
4967 12:29:26.163714 ===================================
4968 12:29:26.166687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4969 12:29:26.173152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 12:29:26.176499 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 12:29:26.183403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4972 12:29:26.186660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4973 12:29:26.189961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4974 12:29:26.190081 [ANA_INIT] flow start
4975 12:29:26.193096 [ANA_INIT] PLL >>>>>>>>
4976 12:29:26.196497 [ANA_INIT] PLL <<<<<<<<
4977 12:29:26.199537 [ANA_INIT] MIDPI >>>>>>>>
4978 12:29:26.199647 [ANA_INIT] MIDPI <<<<<<<<
4979 12:29:26.202830 [ANA_INIT] DLL >>>>>>>>
4980 12:29:26.206412 [ANA_INIT] flow end
4981 12:29:26.209247 ============ LP4 DIFF to SE enter ============
4982 12:29:26.212988 ============ LP4 DIFF to SE exit ============
4983 12:29:26.216014 [ANA_INIT] <<<<<<<<<<<<<
4984 12:29:26.219528 [Flow] Enable top DCM control >>>>>
4985 12:29:26.222964 [Flow] Enable top DCM control <<<<<
4986 12:29:26.225993 Enable DLL master slave shuffle
4987 12:29:26.229382 ==============================================================
4988 12:29:26.232959 Gating Mode config
4989 12:29:26.239554 ==============================================================
4990 12:29:26.239677 Config description:
4991 12:29:26.249450 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4992 12:29:26.255668 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4993 12:29:26.259169 SELPH_MODE 0: By rank 1: By Phase
4994 12:29:26.265560 ==============================================================
4995 12:29:26.269092 GAT_TRACK_EN = 1
4996 12:29:26.272438 RX_GATING_MODE = 2
4997 12:29:26.275831 RX_GATING_TRACK_MODE = 2
4998 12:29:26.278822 SELPH_MODE = 1
4999 12:29:26.282314 PICG_EARLY_EN = 1
5000 12:29:26.285711 VALID_LAT_VALUE = 1
5001 12:29:26.288618 ==============================================================
5002 12:29:26.291972 Enter into Gating configuration >>>>
5003 12:29:26.295338 Exit from Gating configuration <<<<
5004 12:29:26.298557 Enter into DVFS_PRE_config >>>>>
5005 12:29:26.312080 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5006 12:29:26.312205 Exit from DVFS_PRE_config <<<<<
5007 12:29:26.315374 Enter into PICG configuration >>>>
5008 12:29:26.318552 Exit from PICG configuration <<<<
5009 12:29:26.321900 [RX_INPUT] configuration >>>>>
5010 12:29:26.325428 [RX_INPUT] configuration <<<<<
5011 12:29:26.331887 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5012 12:29:26.335353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5013 12:29:26.341874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5014 12:29:26.348376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5015 12:29:26.354712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 12:29:26.361274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 12:29:26.364724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5018 12:29:26.368213 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5019 12:29:26.371208 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5020 12:29:26.378097 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5021 12:29:26.381106 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5022 12:29:26.384544 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 12:29:26.387976 ===================================
5024 12:29:26.391420 LPDDR4 DRAM CONFIGURATION
5025 12:29:26.394483 ===================================
5026 12:29:26.397972 EX_ROW_EN[0] = 0x0
5027 12:29:26.398084 EX_ROW_EN[1] = 0x0
5028 12:29:26.401317 LP4Y_EN = 0x0
5029 12:29:26.401420 WORK_FSP = 0x0
5030 12:29:26.404263 WL = 0x3
5031 12:29:26.404367 RL = 0x3
5032 12:29:26.407509 BL = 0x2
5033 12:29:26.407610 RPST = 0x0
5034 12:29:26.411193 RD_PRE = 0x0
5035 12:29:26.411294 WR_PRE = 0x1
5036 12:29:26.414580 WR_PST = 0x0
5037 12:29:26.414679 DBI_WR = 0x0
5038 12:29:26.417675 DBI_RD = 0x0
5039 12:29:26.421066 OTF = 0x1
5040 12:29:26.424300 ===================================
5041 12:29:26.427533 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5042 12:29:26.430759 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5043 12:29:26.434279 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 12:29:26.437298 ===================================
5045 12:29:26.440905 LPDDR4 DRAM CONFIGURATION
5046 12:29:26.444366 ===================================
5047 12:29:26.447328 EX_ROW_EN[0] = 0x10
5048 12:29:26.447421 EX_ROW_EN[1] = 0x0
5049 12:29:26.450933 LP4Y_EN = 0x0
5050 12:29:26.451049 WORK_FSP = 0x0
5051 12:29:26.453958 WL = 0x3
5052 12:29:26.454060 RL = 0x3
5053 12:29:26.457433 BL = 0x2
5054 12:29:26.457540 RPST = 0x0
5055 12:29:26.460886 RD_PRE = 0x0
5056 12:29:26.460965 WR_PRE = 0x1
5057 12:29:26.463866 WR_PST = 0x0
5058 12:29:26.463939 DBI_WR = 0x0
5059 12:29:26.467466 DBI_RD = 0x0
5060 12:29:26.470456 OTF = 0x1
5061 12:29:26.473936 ===================================
5062 12:29:26.476811 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5063 12:29:26.482127 nWR fixed to 30
5064 12:29:26.485650 [ModeRegInit_LP4] CH0 RK0
5065 12:29:26.485758 [ModeRegInit_LP4] CH0 RK1
5066 12:29:26.488582 [ModeRegInit_LP4] CH1 RK0
5067 12:29:26.491902 [ModeRegInit_LP4] CH1 RK1
5068 12:29:26.492033 match AC timing 9
5069 12:29:26.498381 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5070 12:29:26.501832 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5071 12:29:26.505233 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5072 12:29:26.511570 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5073 12:29:26.514977 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5074 12:29:26.515053 ==
5075 12:29:26.518411 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 12:29:26.521633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 12:29:26.524913 ==
5078 12:29:26.528209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 12:29:26.534837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 12:29:26.538092 [CA 0] Center 38 (7~69) winsize 63
5081 12:29:26.541104 [CA 1] Center 38 (8~69) winsize 62
5082 12:29:26.544664 [CA 2] Center 35 (5~65) winsize 61
5083 12:29:26.547668 [CA 3] Center 35 (5~66) winsize 62
5084 12:29:26.551338 [CA 4] Center 34 (4~65) winsize 62
5085 12:29:26.554363 [CA 5] Center 33 (3~64) winsize 62
5086 12:29:26.554447
5087 12:29:26.557904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 12:29:26.558001
5089 12:29:26.560871 [CATrainingPosCal] consider 1 rank data
5090 12:29:26.564315 u2DelayCellTimex100 = 270/100 ps
5091 12:29:26.567407 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5092 12:29:26.570940 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5093 12:29:26.573955 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5094 12:29:26.581061 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5095 12:29:26.583848 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5096 12:29:26.587125 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5097 12:29:26.587228
5098 12:29:26.590629 CA PerBit enable=1, Macro0, CA PI delay=33
5099 12:29:26.590725
5100 12:29:26.594111 [CBTSetCACLKResult] CA Dly = 33
5101 12:29:26.594196 CS Dly: 7 (0~38)
5102 12:29:26.597548 ==
5103 12:29:26.597633 Dram Type= 6, Freq= 0, CH_0, rank 1
5104 12:29:26.603910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 12:29:26.603995 ==
5106 12:29:26.607042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 12:29:26.613930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5108 12:29:26.617166 [CA 0] Center 38 (7~69) winsize 63
5109 12:29:26.620440 [CA 1] Center 38 (8~69) winsize 62
5110 12:29:26.624230 [CA 2] Center 36 (6~66) winsize 61
5111 12:29:26.626988 [CA 3] Center 35 (5~66) winsize 62
5112 12:29:26.630658 [CA 4] Center 34 (4~65) winsize 62
5113 12:29:26.633964 [CA 5] Center 34 (4~65) winsize 62
5114 12:29:26.634070
5115 12:29:26.636906 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5116 12:29:26.637006
5117 12:29:26.640395 [CATrainingPosCal] consider 2 rank data
5118 12:29:26.643662 u2DelayCellTimex100 = 270/100 ps
5119 12:29:26.649980 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5120 12:29:26.653468 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5121 12:29:26.656499 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5122 12:29:26.660062 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5123 12:29:26.663514 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5124 12:29:26.666601 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5125 12:29:26.666673
5126 12:29:26.670087 CA PerBit enable=1, Macro0, CA PI delay=34
5127 12:29:26.670160
5128 12:29:26.673107 [CBTSetCACLKResult] CA Dly = 34
5129 12:29:26.676641 CS Dly: 7 (0~39)
5130 12:29:26.676756
5131 12:29:26.679693 ----->DramcWriteLeveling(PI) begin...
5132 12:29:26.679795 ==
5133 12:29:26.683241 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 12:29:26.686794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 12:29:26.686893 ==
5136 12:29:26.690157 Write leveling (Byte 0): 33 => 33
5137 12:29:26.693019 Write leveling (Byte 1): 30 => 30
5138 12:29:26.696633 DramcWriteLeveling(PI) end<-----
5139 12:29:26.696707
5140 12:29:26.696793 ==
5141 12:29:26.699712 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 12:29:26.703210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 12:29:26.703286 ==
5144 12:29:26.706099 [Gating] SW mode calibration
5145 12:29:26.713126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5146 12:29:26.719533 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5147 12:29:26.722781 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5148 12:29:26.729051 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 12:29:26.732636 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 12:29:26.736062 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 12:29:26.742485 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 12:29:26.745625 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 12:29:26.748771 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5154 12:29:26.755495 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5155 12:29:26.759006 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5156 12:29:26.762153 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 12:29:26.768761 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 12:29:26.771759 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 12:29:26.775418 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 12:29:26.781823 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 12:29:26.785297 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5162 12:29:26.788251 0 15 28 | B1->B0 | 2c2c 4444 | 1 0 | (0 0) (0 0)
5163 12:29:26.795185 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5164 12:29:26.798149 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 12:29:26.801733 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 12:29:26.808161 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 12:29:26.811744 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 12:29:26.814738 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 12:29:26.821863 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5170 12:29:26.824708 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5171 12:29:26.828067 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 12:29:26.831392 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5173 12:29:26.838338 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 12:29:26.841240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 12:29:26.844860 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:29:26.851171 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 12:29:26.854386 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:29:26.858033 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 12:29:26.864582 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:29:26.868166 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:29:26.871160 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:29:26.877619 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:29:26.881166 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:29:26.884235 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:29:26.890901 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5186 12:29:26.894377 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 12:29:26.897784 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 12:29:26.900694 Total UI for P1: 0, mck2ui 16
5189 12:29:26.904372 best dqsien dly found for B0: ( 1, 2, 26)
5190 12:29:26.907809 Total UI for P1: 0, mck2ui 16
5191 12:29:26.910711 best dqsien dly found for B1: ( 1, 2, 30)
5192 12:29:26.914199 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5193 12:29:26.917188 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5194 12:29:26.920671
5195 12:29:26.924171 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5196 12:29:26.927308 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5197 12:29:26.930926 [Gating] SW calibration Done
5198 12:29:26.931011 ==
5199 12:29:26.933809 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 12:29:26.937268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 12:29:26.937374 ==
5202 12:29:26.937449 RX Vref Scan: 0
5203 12:29:26.940565
5204 12:29:26.940649 RX Vref 0 -> 0, step: 1
5205 12:29:26.940715
5206 12:29:26.943893 RX Delay -80 -> 252, step: 8
5207 12:29:26.947185 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5208 12:29:26.953865 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5209 12:29:26.957378 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5210 12:29:26.960559 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5211 12:29:26.963848 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5212 12:29:26.967019 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5213 12:29:26.970159 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5214 12:29:26.976610 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5215 12:29:26.980057 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5216 12:29:26.983193 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5217 12:29:26.986674 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5218 12:29:26.990140 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5219 12:29:26.993198 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5220 12:29:26.999705 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5221 12:29:27.003027 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5222 12:29:27.006585 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5223 12:29:27.006678 ==
5224 12:29:27.009612 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 12:29:27.012970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 12:29:27.013056 ==
5227 12:29:27.016298 DQS Delay:
5228 12:29:27.016381 DQS0 = 0, DQS1 = 0
5229 12:29:27.019869 DQM Delay:
5230 12:29:27.019953 DQM0 = 105, DQM1 = 90
5231 12:29:27.020020 DQ Delay:
5232 12:29:27.022784 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5233 12:29:27.026303 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5234 12:29:27.029758 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5235 12:29:27.032893 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5236 12:29:27.036333
5237 12:29:27.036417
5238 12:29:27.036483 ==
5239 12:29:27.039331 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 12:29:27.042846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 12:29:27.042932 ==
5242 12:29:27.042998
5243 12:29:27.043073
5244 12:29:27.046055 TX Vref Scan disable
5245 12:29:27.046139 == TX Byte 0 ==
5246 12:29:27.052528 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5247 12:29:27.055772 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5248 12:29:27.055857 == TX Byte 1 ==
5249 12:29:27.062568 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5250 12:29:27.065876 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5251 12:29:27.065960 ==
5252 12:29:27.069032 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 12:29:27.072648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 12:29:27.072760 ==
5255 12:29:27.072837
5256 12:29:27.072912
5257 12:29:27.075823 TX Vref Scan disable
5258 12:29:27.078943 == TX Byte 0 ==
5259 12:29:27.082489 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5260 12:29:27.085552 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5261 12:29:27.089092 == TX Byte 1 ==
5262 12:29:27.092166 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5263 12:29:27.095574 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5264 12:29:27.095660
5265 12:29:27.099196 [DATLAT]
5266 12:29:27.099296 Freq=933, CH0 RK0
5267 12:29:27.099377
5268 12:29:27.102246 DATLAT Default: 0xd
5269 12:29:27.102331 0, 0xFFFF, sum = 0
5270 12:29:27.105633 1, 0xFFFF, sum = 0
5271 12:29:27.105719 2, 0xFFFF, sum = 0
5272 12:29:27.109220 3, 0xFFFF, sum = 0
5273 12:29:27.109347 4, 0xFFFF, sum = 0
5274 12:29:27.112202 5, 0xFFFF, sum = 0
5275 12:29:27.112288 6, 0xFFFF, sum = 0
5276 12:29:27.115540 7, 0xFFFF, sum = 0
5277 12:29:27.115626 8, 0xFFFF, sum = 0
5278 12:29:27.118815 9, 0xFFFF, sum = 0
5279 12:29:27.118920 10, 0x0, sum = 1
5280 12:29:27.122265 11, 0x0, sum = 2
5281 12:29:27.122350 12, 0x0, sum = 3
5282 12:29:27.125210 13, 0x0, sum = 4
5283 12:29:27.125295 best_step = 11
5284 12:29:27.125362
5285 12:29:27.125423 ==
5286 12:29:27.128845 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 12:29:27.135342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 12:29:27.135441 ==
5289 12:29:27.135537 RX Vref Scan: 1
5290 12:29:27.135626
5291 12:29:27.138435 RX Vref 0 -> 0, step: 1
5292 12:29:27.138545
5293 12:29:27.141720 RX Delay -53 -> 252, step: 4
5294 12:29:27.141804
5295 12:29:27.145309 Set Vref, RX VrefLevel [Byte0]: 61
5296 12:29:27.148614 [Byte1]: 49
5297 12:29:27.148738
5298 12:29:27.151527 Final RX Vref Byte 0 = 61 to rank0
5299 12:29:27.155092 Final RX Vref Byte 1 = 49 to rank0
5300 12:29:27.158532 Final RX Vref Byte 0 = 61 to rank1
5301 12:29:27.161469 Final RX Vref Byte 1 = 49 to rank1==
5302 12:29:27.164744 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 12:29:27.168512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 12:29:27.171594 ==
5305 12:29:27.171694 DQS Delay:
5306 12:29:27.171792 DQS0 = 0, DQS1 = 0
5307 12:29:27.174801 DQM Delay:
5308 12:29:27.174887 DQM0 = 108, DQM1 = 92
5309 12:29:27.178072 DQ Delay:
5310 12:29:27.181166 DQ0 =106, DQ1 =106, DQ2 =106, DQ3 =104
5311 12:29:27.184518 DQ4 =110, DQ5 =98, DQ6 =118, DQ7 =116
5312 12:29:27.187975 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5313 12:29:27.191350 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5314 12:29:27.191449
5315 12:29:27.191561
5316 12:29:27.197699 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5317 12:29:27.201179 CH0 RK0: MR19=505, MR18=2622
5318 12:29:27.207653 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5319 12:29:27.207743
5320 12:29:27.210990 ----->DramcWriteLeveling(PI) begin...
5321 12:29:27.211078 ==
5322 12:29:27.214450 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 12:29:27.217907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 12:29:27.217994 ==
5325 12:29:27.221282 Write leveling (Byte 0): 32 => 32
5326 12:29:27.224531 Write leveling (Byte 1): 31 => 31
5327 12:29:27.227597 DramcWriteLeveling(PI) end<-----
5328 12:29:27.227683
5329 12:29:27.227762 ==
5330 12:29:27.231076 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 12:29:27.234168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 12:29:27.237616 ==
5333 12:29:27.237699 [Gating] SW mode calibration
5334 12:29:27.244046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5335 12:29:27.251070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5336 12:29:27.254293 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 12:29:27.260699 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 12:29:27.264329 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 12:29:27.267498 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 12:29:27.273885 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 12:29:27.277202 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 12:29:27.280553 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5343 12:29:27.287273 0 14 28 | B1->B0 | 2a2a 2525 | 0 0 | (0 1) (0 0)
5344 12:29:27.290595 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 12:29:27.293843 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 12:29:27.300809 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 12:29:27.303853 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 12:29:27.307414 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 12:29:27.313691 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 12:29:27.317079 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5351 12:29:27.320546 0 15 28 | B1->B0 | 4141 4444 | 1 0 | (0 0) (0 0)
5352 12:29:27.326859 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 12:29:27.330202 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 12:29:27.333673 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 12:29:27.340232 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 12:29:27.343663 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 12:29:27.346656 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 12:29:27.353261 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5359 12:29:27.356607 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5360 12:29:27.360077 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:29:27.366619 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:29:27.370167 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:29:27.373474 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:29:27.379816 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:29:27.383205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:29:27.386894 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 12:29:27.393344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:29:27.396644 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:29:27.399995 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:29:27.403317 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:29:27.409996 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 12:29:27.413074 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:29:27.416572 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:29:27.422985 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:29:27.426571 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5376 12:29:27.429648 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:29:27.433056 Total UI for P1: 0, mck2ui 16
5378 12:29:27.435983 best dqsien dly found for B0: ( 1, 2, 28)
5379 12:29:27.439452 Total UI for P1: 0, mck2ui 16
5380 12:29:27.442856 best dqsien dly found for B1: ( 1, 2, 28)
5381 12:29:27.446000 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5382 12:29:27.452907 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5383 12:29:27.452986
5384 12:29:27.456065 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5385 12:29:27.459556 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5386 12:29:27.462454 [Gating] SW calibration Done
5387 12:29:27.462540 ==
5388 12:29:27.465867 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 12:29:27.469473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 12:29:27.469560 ==
5391 12:29:27.469644 RX Vref Scan: 0
5392 12:29:27.472477
5393 12:29:27.472563 RX Vref 0 -> 0, step: 1
5394 12:29:27.472666
5395 12:29:27.475851 RX Delay -80 -> 252, step: 8
5396 12:29:27.479228 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5397 12:29:27.485667 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5398 12:29:27.489127 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5399 12:29:27.492422 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5400 12:29:27.495669 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5401 12:29:27.498932 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5402 12:29:27.502360 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5403 12:29:27.508957 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5404 12:29:27.512015 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5405 12:29:27.515551 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5406 12:29:27.519187 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5407 12:29:27.522034 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5408 12:29:27.525554 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5409 12:29:27.531926 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5410 12:29:27.535374 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5411 12:29:27.538799 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5412 12:29:27.538886 ==
5413 12:29:27.541832 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 12:29:27.545472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 12:29:27.545548 ==
5416 12:29:27.548427 DQS Delay:
5417 12:29:27.548529 DQS0 = 0, DQS1 = 0
5418 12:29:27.551934 DQM Delay:
5419 12:29:27.552040 DQM0 = 104, DQM1 = 91
5420 12:29:27.552137 DQ Delay:
5421 12:29:27.554855 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5422 12:29:27.558373 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5423 12:29:27.561426 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5424 12:29:27.564739 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5425 12:29:27.568083
5426 12:29:27.568170
5427 12:29:27.568242 ==
5428 12:29:27.571459 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 12:29:27.574973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 12:29:27.575076 ==
5431 12:29:27.575168
5432 12:29:27.575264
5433 12:29:27.578040 TX Vref Scan disable
5434 12:29:27.578121 == TX Byte 0 ==
5435 12:29:27.584728 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5436 12:29:27.587813 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5437 12:29:27.587899 == TX Byte 1 ==
5438 12:29:27.594292 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5439 12:29:27.598001 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5440 12:29:27.598130 ==
5441 12:29:27.601410 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 12:29:27.604597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 12:29:27.604715 ==
5444 12:29:27.604857
5445 12:29:27.604952
5446 12:29:27.607560 TX Vref Scan disable
5447 12:29:27.610972 == TX Byte 0 ==
5448 12:29:27.614308 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5449 12:29:27.617776 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5450 12:29:27.620834 == TX Byte 1 ==
5451 12:29:27.624362 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5452 12:29:27.627274 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5453 12:29:27.630759
5454 12:29:27.630864 [DATLAT]
5455 12:29:27.630966 Freq=933, CH0 RK1
5456 12:29:27.631059
5457 12:29:27.633899 DATLAT Default: 0xb
5458 12:29:27.634011 0, 0xFFFF, sum = 0
5459 12:29:27.637172 1, 0xFFFF, sum = 0
5460 12:29:27.637267 2, 0xFFFF, sum = 0
5461 12:29:27.640500 3, 0xFFFF, sum = 0
5462 12:29:27.640624 4, 0xFFFF, sum = 0
5463 12:29:27.644177 5, 0xFFFF, sum = 0
5464 12:29:27.647147 6, 0xFFFF, sum = 0
5465 12:29:27.647235 7, 0xFFFF, sum = 0
5466 12:29:27.650547 8, 0xFFFF, sum = 0
5467 12:29:27.650629 9, 0xFFFF, sum = 0
5468 12:29:27.654270 10, 0x0, sum = 1
5469 12:29:27.654347 11, 0x0, sum = 2
5470 12:29:27.654412 12, 0x0, sum = 3
5471 12:29:27.657295 13, 0x0, sum = 4
5472 12:29:27.657397 best_step = 11
5473 12:29:27.657468
5474 12:29:27.660694 ==
5475 12:29:27.663765 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 12:29:27.667263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 12:29:27.667343 ==
5478 12:29:27.667409 RX Vref Scan: 0
5479 12:29:27.667470
5480 12:29:27.670542 RX Vref 0 -> 0, step: 1
5481 12:29:27.670650
5482 12:29:27.673587 RX Delay -53 -> 252, step: 4
5483 12:29:27.677091 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5484 12:29:27.683909 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5485 12:29:27.686903 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5486 12:29:27.690290 iDelay=203, Bit 3, Center 100 (15 ~ 186) 172
5487 12:29:27.693747 iDelay=203, Bit 4, Center 108 (23 ~ 194) 172
5488 12:29:27.696708 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5489 12:29:27.703671 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5490 12:29:27.706621 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5491 12:29:27.710253 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5492 12:29:27.713033 iDelay=203, Bit 9, Center 78 (-5 ~ 162) 168
5493 12:29:27.716424 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5494 12:29:27.723121 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5495 12:29:27.726660 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5496 12:29:27.729625 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5497 12:29:27.732988 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5498 12:29:27.736543 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5499 12:29:27.739899 ==
5500 12:29:27.742879 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 12:29:27.746364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 12:29:27.746445 ==
5503 12:29:27.746510 DQS Delay:
5504 12:29:27.749807 DQS0 = 0, DQS1 = 0
5505 12:29:27.749880 DQM Delay:
5506 12:29:27.753190 DQM0 = 105, DQM1 = 92
5507 12:29:27.753267 DQ Delay:
5508 12:29:27.756198 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100
5509 12:29:27.759724 DQ4 =108, DQ5 =96, DQ6 =114, DQ7 =112
5510 12:29:27.762794 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =92
5511 12:29:27.766189 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5512 12:29:27.766303
5513 12:29:27.766397
5514 12:29:27.776157 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5515 12:29:27.776241 CH0 RK1: MR19=505, MR18=2B0D
5516 12:29:27.782545 CH0_RK1: MR19=0x505, MR18=0x2B0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5517 12:29:27.786174 [RxdqsGatingPostProcess] freq 933
5518 12:29:27.792374 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5519 12:29:27.795779 best DQS0 dly(2T, 0.5T) = (0, 10)
5520 12:29:27.799347 best DQS1 dly(2T, 0.5T) = (0, 10)
5521 12:29:27.802350 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5522 12:29:27.805899 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5523 12:29:27.809140 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 12:29:27.809247 best DQS1 dly(2T, 0.5T) = (0, 10)
5525 12:29:27.812453 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 12:29:27.815642 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5527 12:29:27.818999 Pre-setting of DQS Precalculation
5528 12:29:27.825734 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5529 12:29:27.825826 ==
5530 12:29:27.828701 Dram Type= 6, Freq= 0, CH_1, rank 0
5531 12:29:27.832199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 12:29:27.832290 ==
5533 12:29:27.838579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 12:29:27.845389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5535 12:29:27.848603 [CA 0] Center 37 (7~68) winsize 62
5536 12:29:27.852181 [CA 1] Center 37 (7~68) winsize 62
5537 12:29:27.855088 [CA 2] Center 36 (6~66) winsize 61
5538 12:29:27.858157 [CA 3] Center 35 (5~65) winsize 61
5539 12:29:27.861623 [CA 4] Center 35 (5~66) winsize 62
5540 12:29:27.865141 [CA 5] Center 34 (4~65) winsize 62
5541 12:29:27.865238
5542 12:29:27.868057 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5543 12:29:27.868133
5544 12:29:27.871422 [CATrainingPosCal] consider 1 rank data
5545 12:29:27.874894 u2DelayCellTimex100 = 270/100 ps
5546 12:29:27.878358 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5547 12:29:27.881541 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5548 12:29:27.884480 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5549 12:29:27.887932 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5550 12:29:27.891397 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5551 12:29:27.897698 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5552 12:29:27.897779
5553 12:29:27.901249 CA PerBit enable=1, Macro0, CA PI delay=34
5554 12:29:27.901325
5555 12:29:27.904311 [CBTSetCACLKResult] CA Dly = 34
5556 12:29:27.904386 CS Dly: 6 (0~37)
5557 12:29:27.904449 ==
5558 12:29:27.907698 Dram Type= 6, Freq= 0, CH_1, rank 1
5559 12:29:27.911160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 12:29:27.914582 ==
5561 12:29:27.917519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5562 12:29:27.924198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5563 12:29:27.927528 [CA 0] Center 38 (7~69) winsize 63
5564 12:29:27.931191 [CA 1] Center 38 (7~69) winsize 63
5565 12:29:27.934215 [CA 2] Center 36 (6~66) winsize 61
5566 12:29:27.937676 [CA 3] Center 35 (6~65) winsize 60
5567 12:29:27.941111 [CA 4] Center 35 (6~65) winsize 60
5568 12:29:27.944123 [CA 5] Center 35 (5~65) winsize 61
5569 12:29:27.944207
5570 12:29:27.947656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5571 12:29:27.947741
5572 12:29:27.950977 [CATrainingPosCal] consider 2 rank data
5573 12:29:27.954066 u2DelayCellTimex100 = 270/100 ps
5574 12:29:27.957564 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5575 12:29:27.960599 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5576 12:29:27.964052 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5577 12:29:27.970584 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5578 12:29:27.973962 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5579 12:29:27.976943 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5580 12:29:27.977027
5581 12:29:27.980501 CA PerBit enable=1, Macro0, CA PI delay=35
5582 12:29:27.980585
5583 12:29:27.983711 [CBTSetCACLKResult] CA Dly = 35
5584 12:29:27.983783 CS Dly: 7 (0~39)
5585 12:29:27.983847
5586 12:29:27.987188 ----->DramcWriteLeveling(PI) begin...
5587 12:29:27.990276 ==
5588 12:29:27.993840 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 12:29:27.996727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 12:29:27.996847 ==
5591 12:29:28.000115 Write leveling (Byte 0): 28 => 28
5592 12:29:28.003622 Write leveling (Byte 1): 30 => 30
5593 12:29:28.007113 DramcWriteLeveling(PI) end<-----
5594 12:29:28.007197
5595 12:29:28.007263 ==
5596 12:29:28.010133 Dram Type= 6, Freq= 0, CH_1, rank 0
5597 12:29:28.013717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 12:29:28.013801 ==
5599 12:29:28.016690 [Gating] SW mode calibration
5600 12:29:28.023506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5601 12:29:28.030142 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5602 12:29:28.033460 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 12:29:28.036676 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 12:29:28.042948 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 12:29:28.046462 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 12:29:28.049968 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 12:29:28.056321 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 12:29:28.059915 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (0 0) (0 1)
5609 12:29:28.062823 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5610 12:29:28.069832 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 12:29:28.072712 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 12:29:28.076172 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 12:29:28.082676 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 12:29:28.086184 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 12:29:28.089574 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 12:29:28.096146 0 15 24 | B1->B0 | 2727 2f2f | 0 0 | (1 1) (0 0)
5617 12:29:28.099060 0 15 28 | B1->B0 | 4343 4444 | 1 0 | (0 0) (0 0)
5618 12:29:28.102379 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 12:29:28.109352 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 12:29:28.112448 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 12:29:28.115987 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 12:29:28.122480 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 12:29:28.125405 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 12:29:28.129133 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5625 12:29:28.135309 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:29:28.138847 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:29:28.142326 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:29:28.148894 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:29:28.152032 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:29:28.155554 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:29:28.161890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:29:28.165533 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:29:28.168527 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:29:28.174963 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:29:28.178546 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:29:28.181435 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:29:28.188456 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:29:28.191410 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:29:28.194898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5640 12:29:28.201198 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5641 12:29:28.201296 Total UI for P1: 0, mck2ui 16
5642 12:29:28.208037 best dqsien dly found for B0: ( 1, 2, 20)
5643 12:29:28.211519 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5644 12:29:28.214580 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 12:29:28.218140 Total UI for P1: 0, mck2ui 16
5646 12:29:28.221212 best dqsien dly found for B1: ( 1, 2, 26)
5647 12:29:28.224705 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5648 12:29:28.227818 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5649 12:29:28.227903
5650 12:29:28.234588 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5651 12:29:28.237835 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5652 12:29:28.237945 [Gating] SW calibration Done
5653 12:29:28.241103 ==
5654 12:29:28.241187 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 12:29:28.247589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 12:29:28.247721 ==
5657 12:29:28.247833 RX Vref Scan: 0
5658 12:29:28.247911
5659 12:29:28.250849 RX Vref 0 -> 0, step: 1
5660 12:29:28.250925
5661 12:29:28.254445 RX Delay -80 -> 252, step: 8
5662 12:29:28.257768 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5663 12:29:28.260641 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5664 12:29:28.264056 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5665 12:29:28.270606 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5666 12:29:28.274088 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5667 12:29:28.277241 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5668 12:29:28.280741 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5669 12:29:28.283741 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5670 12:29:28.290646 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5671 12:29:28.293586 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5672 12:29:28.297333 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5673 12:29:28.300388 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5674 12:29:28.303893 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5675 12:29:28.310410 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5676 12:29:28.313847 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5677 12:29:28.316862 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5678 12:29:28.316948 ==
5679 12:29:28.320395 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 12:29:28.323452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 12:29:28.323539 ==
5682 12:29:28.327003 DQS Delay:
5683 12:29:28.327089 DQS0 = 0, DQS1 = 0
5684 12:29:28.327157 DQM Delay:
5685 12:29:28.330022 DQM0 = 104, DQM1 = 95
5686 12:29:28.330108 DQ Delay:
5687 12:29:28.333462 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5688 12:29:28.336871 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5689 12:29:28.339969 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5690 12:29:28.343293 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =99
5691 12:29:28.346937
5692 12:29:28.347022
5693 12:29:28.347088 ==
5694 12:29:28.350101 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 12:29:28.353374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 12:29:28.353461 ==
5697 12:29:28.353529
5698 12:29:28.353592
5699 12:29:28.356635 TX Vref Scan disable
5700 12:29:28.356748 == TX Byte 0 ==
5701 12:29:28.363278 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5702 12:29:28.366454 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5703 12:29:28.366540 == TX Byte 1 ==
5704 12:29:28.373340 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5705 12:29:28.376676 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5706 12:29:28.376794 ==
5707 12:29:28.379640 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 12:29:28.383120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 12:29:28.383207 ==
5710 12:29:28.383274
5711 12:29:28.383337
5712 12:29:28.386669 TX Vref Scan disable
5713 12:29:28.389561 == TX Byte 0 ==
5714 12:29:28.392901 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5715 12:29:28.396442 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5716 12:29:28.399870 == TX Byte 1 ==
5717 12:29:28.403042 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5718 12:29:28.406196 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5719 12:29:28.406281
5720 12:29:28.409753 [DATLAT]
5721 12:29:28.409842 Freq=933, CH1 RK0
5722 12:29:28.409932
5723 12:29:28.413186 DATLAT Default: 0xd
5724 12:29:28.413280 0, 0xFFFF, sum = 0
5725 12:29:28.416339 1, 0xFFFF, sum = 0
5726 12:29:28.416432 2, 0xFFFF, sum = 0
5727 12:29:28.419414 3, 0xFFFF, sum = 0
5728 12:29:28.419505 4, 0xFFFF, sum = 0
5729 12:29:28.422812 5, 0xFFFF, sum = 0
5730 12:29:28.422904 6, 0xFFFF, sum = 0
5731 12:29:28.426310 7, 0xFFFF, sum = 0
5732 12:29:28.426391 8, 0xFFFF, sum = 0
5733 12:29:28.429287 9, 0xFFFF, sum = 0
5734 12:29:28.429379 10, 0x0, sum = 1
5735 12:29:28.432728 11, 0x0, sum = 2
5736 12:29:28.432852 12, 0x0, sum = 3
5737 12:29:28.435762 13, 0x0, sum = 4
5738 12:29:28.435842 best_step = 11
5739 12:29:28.435928
5740 12:29:28.435994 ==
5741 12:29:28.439270 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 12:29:28.445804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 12:29:28.445912 ==
5744 12:29:28.446007 RX Vref Scan: 1
5745 12:29:28.446083
5746 12:29:28.449243 RX Vref 0 -> 0, step: 1
5747 12:29:28.449326
5748 12:29:28.452462 RX Delay -53 -> 252, step: 4
5749 12:29:28.452546
5750 12:29:28.455691 Set Vref, RX VrefLevel [Byte0]: 52
5751 12:29:28.458980 [Byte1]: 50
5752 12:29:28.459059
5753 12:29:28.462233 Final RX Vref Byte 0 = 52 to rank0
5754 12:29:28.465484 Final RX Vref Byte 1 = 50 to rank0
5755 12:29:28.469242 Final RX Vref Byte 0 = 52 to rank1
5756 12:29:28.472464 Final RX Vref Byte 1 = 50 to rank1==
5757 12:29:28.475543 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 12:29:28.478866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 12:29:28.478953 ==
5760 12:29:28.482336 DQS Delay:
5761 12:29:28.482414 DQS0 = 0, DQS1 = 0
5762 12:29:28.485426 DQM Delay:
5763 12:29:28.485516 DQM0 = 104, DQM1 = 96
5764 12:29:28.488944 DQ Delay:
5765 12:29:28.492302 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5766 12:29:28.495417 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5767 12:29:28.498523 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90
5768 12:29:28.502063 DQ12 =108, DQ13 =100, DQ14 =102, DQ15 =102
5769 12:29:28.502144
5770 12:29:28.502210
5771 12:29:28.508682 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5772 12:29:28.511779 CH1 RK0: MR19=505, MR18=1931
5773 12:29:28.518221 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5774 12:29:28.518304
5775 12:29:28.521577 ----->DramcWriteLeveling(PI) begin...
5776 12:29:28.521656 ==
5777 12:29:28.525154 Dram Type= 6, Freq= 0, CH_1, rank 1
5778 12:29:28.528144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 12:29:28.528227 ==
5780 12:29:28.531767 Write leveling (Byte 0): 27 => 27
5781 12:29:28.534727 Write leveling (Byte 1): 27 => 27
5782 12:29:28.538186 DramcWriteLeveling(PI) end<-----
5783 12:29:28.538263
5784 12:29:28.538336 ==
5785 12:29:28.541172 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 12:29:28.548131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 12:29:28.548211 ==
5788 12:29:28.548285 [Gating] SW mode calibration
5789 12:29:28.557963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5790 12:29:28.561347 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5791 12:29:28.567893 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5792 12:29:28.570959 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 12:29:28.574308 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 12:29:28.580856 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 12:29:28.584420 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 12:29:28.587482 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 12:29:28.594273 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 1) (0 0)
5798 12:29:28.597743 0 14 28 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 0)
5799 12:29:28.600664 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5800 12:29:28.604252 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 12:29:28.611093 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 12:29:28.614467 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 12:29:28.617486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 12:29:28.623961 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 12:29:28.627349 0 15 24 | B1->B0 | 2c2c 2727 | 1 0 | (0 0) (0 0)
5806 12:29:28.630841 0 15 28 | B1->B0 | 3a3a 3535 | 0 0 | (0 0) (0 0)
5807 12:29:28.637353 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5808 12:29:28.640718 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 12:29:28.643687 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 12:29:28.650191 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 12:29:28.653560 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 12:29:28.656934 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 12:29:28.663675 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5814 12:29:28.667142 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5815 12:29:28.670122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:29:28.676770 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:29:28.679910 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:29:28.683216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:29:28.690052 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:29:28.693298 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:29:28.696733 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:29:28.703263 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:29:28.706282 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:29:28.709795 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:29:28.716431 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:29:28.719939 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:29:28.723119 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:29:28.729498 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:29:28.732988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5830 12:29:28.736157 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 12:29:28.739553 Total UI for P1: 0, mck2ui 16
5832 12:29:28.742666 best dqsien dly found for B0: ( 1, 2, 24)
5833 12:29:28.746234 Total UI for P1: 0, mck2ui 16
5834 12:29:28.749659 best dqsien dly found for B1: ( 1, 2, 24)
5835 12:29:28.752671 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5836 12:29:28.756269 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5837 12:29:28.756360
5838 12:29:28.762614 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5839 12:29:28.766146 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5840 12:29:28.769567 [Gating] SW calibration Done
5841 12:29:28.769648 ==
5842 12:29:28.772910 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 12:29:28.775894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 12:29:28.775969 ==
5845 12:29:28.776040 RX Vref Scan: 0
5846 12:29:28.776103
5847 12:29:28.779438 RX Vref 0 -> 0, step: 1
5848 12:29:28.779513
5849 12:29:28.782628 RX Delay -80 -> 252, step: 8
5850 12:29:28.785897 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5851 12:29:28.789098 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5852 12:29:28.795705 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5853 12:29:28.799319 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5854 12:29:28.802523 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5855 12:29:28.805480 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5856 12:29:28.808950 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5857 12:29:28.812386 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5858 12:29:28.818652 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5859 12:29:28.821995 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5860 12:29:28.825071 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5861 12:29:28.828607 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5862 12:29:28.831968 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5863 12:29:28.838497 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5864 12:29:28.841940 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5865 12:29:28.845086 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5866 12:29:28.845170 ==
5867 12:29:28.848627 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 12:29:28.851625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 12:29:28.851714 ==
5870 12:29:28.855213 DQS Delay:
5871 12:29:28.855297 DQS0 = 0, DQS1 = 0
5872 12:29:28.858215 DQM Delay:
5873 12:29:28.858300 DQM0 = 101, DQM1 = 96
5874 12:29:28.858367 DQ Delay:
5875 12:29:28.861801 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5876 12:29:28.864722 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =99
5877 12:29:28.868263 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5878 12:29:28.871627 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =107
5879 12:29:28.874924
5880 12:29:28.874998
5881 12:29:28.875061 ==
5882 12:29:28.878011 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 12:29:28.881595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 12:29:28.881680 ==
5885 12:29:28.881746
5886 12:29:28.881807
5887 12:29:28.884623 TX Vref Scan disable
5888 12:29:28.884709 == TX Byte 0 ==
5889 12:29:28.891577 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5890 12:29:28.894510 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5891 12:29:28.894665 == TX Byte 1 ==
5892 12:29:28.901146 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5893 12:29:28.904392 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5894 12:29:28.904472 ==
5895 12:29:28.907909 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 12:29:28.910848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 12:29:28.910962 ==
5898 12:29:28.911059
5899 12:29:28.911154
5900 12:29:28.914282 TX Vref Scan disable
5901 12:29:28.917590 == TX Byte 0 ==
5902 12:29:28.921112 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5903 12:29:28.924439 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5904 12:29:28.927483 == TX Byte 1 ==
5905 12:29:28.931131 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5906 12:29:28.934132 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5907 12:29:28.934220
5908 12:29:28.937520 [DATLAT]
5909 12:29:28.937605 Freq=933, CH1 RK1
5910 12:29:28.937674
5911 12:29:28.940961 DATLAT Default: 0xb
5912 12:29:28.941046 0, 0xFFFF, sum = 0
5913 12:29:28.944165 1, 0xFFFF, sum = 0
5914 12:29:28.944251 2, 0xFFFF, sum = 0
5915 12:29:28.947693 3, 0xFFFF, sum = 0
5916 12:29:28.947780 4, 0xFFFF, sum = 0
5917 12:29:28.950618 5, 0xFFFF, sum = 0
5918 12:29:28.950705 6, 0xFFFF, sum = 0
5919 12:29:28.954149 7, 0xFFFF, sum = 0
5920 12:29:28.957250 8, 0xFFFF, sum = 0
5921 12:29:28.957337 9, 0xFFFF, sum = 0
5922 12:29:28.960601 10, 0x0, sum = 1
5923 12:29:28.960688 11, 0x0, sum = 2
5924 12:29:28.960757 12, 0x0, sum = 3
5925 12:29:28.964221 13, 0x0, sum = 4
5926 12:29:28.964308 best_step = 11
5927 12:29:28.964379
5928 12:29:28.967162 ==
5929 12:29:28.967263 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 12:29:28.973986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 12:29:28.974100 ==
5932 12:29:28.974191 RX Vref Scan: 0
5933 12:29:28.974256
5934 12:29:28.976914 RX Vref 0 -> 0, step: 1
5935 12:29:28.977029
5936 12:29:28.980320 RX Delay -53 -> 252, step: 4
5937 12:29:28.983736 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5938 12:29:28.990168 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5939 12:29:28.993645 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5940 12:29:28.997136 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5941 12:29:29.000555 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5942 12:29:29.003390 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5943 12:29:29.010400 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5944 12:29:29.013589 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5945 12:29:29.016770 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5946 12:29:29.020032 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5947 12:29:29.023436 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5948 12:29:29.026727 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5949 12:29:29.033620 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5950 12:29:29.036629 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5951 12:29:29.040043 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5952 12:29:29.043451 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5953 12:29:29.046451 ==
5954 12:29:29.046536 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 12:29:29.052987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 12:29:29.053074 ==
5957 12:29:29.053142 DQS Delay:
5958 12:29:29.056390 DQS0 = 0, DQS1 = 0
5959 12:29:29.056475 DQM Delay:
5960 12:29:29.059944 DQM0 = 105, DQM1 = 97
5961 12:29:29.060033 DQ Delay:
5962 12:29:29.062883 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
5963 12:29:29.066509 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =104
5964 12:29:29.069668 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5965 12:29:29.073158 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5966 12:29:29.073244
5967 12:29:29.073310
5968 12:29:29.082977 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5969 12:29:29.083065 CH1 RK1: MR19=504, MR18=20FE
5970 12:29:29.089465 CH1_RK1: MR19=0x504, MR18=0x20FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5971 12:29:29.092906 [RxdqsGatingPostProcess] freq 933
5972 12:29:29.099326 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5973 12:29:29.102907 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 12:29:29.106358 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 12:29:29.109130 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 12:29:29.112711 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 12:29:29.115909 best DQS0 dly(2T, 0.5T) = (0, 10)
5978 12:29:29.116021 best DQS1 dly(2T, 0.5T) = (0, 10)
5979 12:29:29.119131 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5980 12:29:29.122363 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5981 12:29:29.125723 Pre-setting of DQS Precalculation
5982 12:29:29.132508 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5983 12:29:29.139256 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5984 12:29:29.145455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5985 12:29:29.145569
5986 12:29:29.145666
5987 12:29:29.148932 [Calibration Summary] 1866 Mbps
5988 12:29:29.152403 CH 0, Rank 0
5989 12:29:29.152517 SW Impedance : PASS
5990 12:29:29.155556 DUTY Scan : NO K
5991 12:29:29.159041 ZQ Calibration : PASS
5992 12:29:29.159152 Jitter Meter : NO K
5993 12:29:29.162073 CBT Training : PASS
5994 12:29:29.162173 Write leveling : PASS
5995 12:29:29.165624 RX DQS gating : PASS
5996 12:29:29.168576 RX DQ/DQS(RDDQC) : PASS
5997 12:29:29.168678 TX DQ/DQS : PASS
5998 12:29:29.172089 RX DATLAT : PASS
5999 12:29:29.175116 RX DQ/DQS(Engine): PASS
6000 12:29:29.175231 TX OE : NO K
6001 12:29:29.178514 All Pass.
6002 12:29:29.178618
6003 12:29:29.178711 CH 0, Rank 1
6004 12:29:29.181946 SW Impedance : PASS
6005 12:29:29.182032 DUTY Scan : NO K
6006 12:29:29.185014 ZQ Calibration : PASS
6007 12:29:29.188574 Jitter Meter : NO K
6008 12:29:29.188686 CBT Training : PASS
6009 12:29:29.191630 Write leveling : PASS
6010 12:29:29.195292 RX DQS gating : PASS
6011 12:29:29.195377 RX DQ/DQS(RDDQC) : PASS
6012 12:29:29.198285 TX DQ/DQS : PASS
6013 12:29:29.201732 RX DATLAT : PASS
6014 12:29:29.201817 RX DQ/DQS(Engine): PASS
6015 12:29:29.205221 TX OE : NO K
6016 12:29:29.205333 All Pass.
6017 12:29:29.205428
6018 12:29:29.208246 CH 1, Rank 0
6019 12:29:29.208357 SW Impedance : PASS
6020 12:29:29.211743 DUTY Scan : NO K
6021 12:29:29.214778 ZQ Calibration : PASS
6022 12:29:29.214890 Jitter Meter : NO K
6023 12:29:29.218376 CBT Training : PASS
6024 12:29:29.221286 Write leveling : PASS
6025 12:29:29.221391 RX DQS gating : PASS
6026 12:29:29.224660 RX DQ/DQS(RDDQC) : PASS
6027 12:29:29.227949 TX DQ/DQS : PASS
6028 12:29:29.228035 RX DATLAT : PASS
6029 12:29:29.231218 RX DQ/DQS(Engine): PASS
6030 12:29:29.234434 TX OE : NO K
6031 12:29:29.234520 All Pass.
6032 12:29:29.234587
6033 12:29:29.234648 CH 1, Rank 1
6034 12:29:29.237758 SW Impedance : PASS
6035 12:29:29.241239 DUTY Scan : NO K
6036 12:29:29.241325 ZQ Calibration : PASS
6037 12:29:29.244358 Jitter Meter : NO K
6038 12:29:29.247798 CBT Training : PASS
6039 12:29:29.247879 Write leveling : PASS
6040 12:29:29.251290 RX DQS gating : PASS
6041 12:29:29.251404 RX DQ/DQS(RDDQC) : PASS
6042 12:29:29.254385 TX DQ/DQS : PASS
6043 12:29:29.257355 RX DATLAT : PASS
6044 12:29:29.257468 RX DQ/DQS(Engine): PASS
6045 12:29:29.260748 TX OE : NO K
6046 12:29:29.260875 All Pass.
6047 12:29:29.260972
6048 12:29:29.264306 DramC Write-DBI off
6049 12:29:29.267285 PER_BANK_REFRESH: Hybrid Mode
6050 12:29:29.267370 TX_TRACKING: ON
6051 12:29:29.277618 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6052 12:29:29.280629 [FAST_K] Save calibration result to emmc
6053 12:29:29.283895 dramc_set_vcore_voltage set vcore to 650000
6054 12:29:29.287400 Read voltage for 400, 6
6055 12:29:29.287478 Vio18 = 0
6056 12:29:29.290759 Vcore = 650000
6057 12:29:29.290870 Vdram = 0
6058 12:29:29.290971 Vddq = 0
6059 12:29:29.291051 Vmddr = 0
6060 12:29:29.297450 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6061 12:29:29.303871 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6062 12:29:29.303953 MEM_TYPE=3, freq_sel=20
6063 12:29:29.307299 sv_algorithm_assistance_LP4_800
6064 12:29:29.310372 ============ PULL DRAM RESETB DOWN ============
6065 12:29:29.317288 ========== PULL DRAM RESETB DOWN end =========
6066 12:29:29.320172 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6067 12:29:29.323650 ===================================
6068 12:29:29.326709 LPDDR4 DRAM CONFIGURATION
6069 12:29:29.330197 ===================================
6070 12:29:29.330290 EX_ROW_EN[0] = 0x0
6071 12:29:29.333534 EX_ROW_EN[1] = 0x0
6072 12:29:29.333657 LP4Y_EN = 0x0
6073 12:29:29.336684 WORK_FSP = 0x0
6074 12:29:29.339871 WL = 0x2
6075 12:29:29.339962 RL = 0x2
6076 12:29:29.343473 BL = 0x2
6077 12:29:29.343574 RPST = 0x0
6078 12:29:29.346628 RD_PRE = 0x0
6079 12:29:29.346744 WR_PRE = 0x1
6080 12:29:29.349903 WR_PST = 0x0
6081 12:29:29.350021 DBI_WR = 0x0
6082 12:29:29.353098 DBI_RD = 0x0
6083 12:29:29.353222 OTF = 0x1
6084 12:29:29.356473 ===================================
6085 12:29:29.359848 ===================================
6086 12:29:29.363339 ANA top config
6087 12:29:29.366358 ===================================
6088 12:29:29.366479 DLL_ASYNC_EN = 0
6089 12:29:29.369501 ALL_SLAVE_EN = 1
6090 12:29:29.372948 NEW_RANK_MODE = 1
6091 12:29:29.376393 DLL_IDLE_MODE = 1
6092 12:29:29.379476 LP45_APHY_COMB_EN = 1
6093 12:29:29.379581 TX_ODT_DIS = 1
6094 12:29:29.383071 NEW_8X_MODE = 1
6095 12:29:29.386059 ===================================
6096 12:29:29.389397 ===================================
6097 12:29:29.392745 data_rate = 800
6098 12:29:29.396164 CKR = 1
6099 12:29:29.399218 DQ_P2S_RATIO = 4
6100 12:29:29.402735 ===================================
6101 12:29:29.402840 CA_P2S_RATIO = 4
6102 12:29:29.406314 DQ_CA_OPEN = 0
6103 12:29:29.409193 DQ_SEMI_OPEN = 1
6104 12:29:29.412708 CA_SEMI_OPEN = 1
6105 12:29:29.415754 CA_FULL_RATE = 0
6106 12:29:29.419191 DQ_CKDIV4_EN = 0
6107 12:29:29.419297 CA_CKDIV4_EN = 1
6108 12:29:29.422576 CA_PREDIV_EN = 0
6109 12:29:29.426173 PH8_DLY = 0
6110 12:29:29.429067 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6111 12:29:29.432521 DQ_AAMCK_DIV = 0
6112 12:29:29.435530 CA_AAMCK_DIV = 0
6113 12:29:29.438878 CA_ADMCK_DIV = 4
6114 12:29:29.438985 DQ_TRACK_CA_EN = 0
6115 12:29:29.442130 CA_PICK = 800
6116 12:29:29.445825 CA_MCKIO = 400
6117 12:29:29.448990 MCKIO_SEMI = 400
6118 12:29:29.452043 PLL_FREQ = 3016
6119 12:29:29.455559 DQ_UI_PI_RATIO = 32
6120 12:29:29.458838 CA_UI_PI_RATIO = 32
6121 12:29:29.462058 ===================================
6122 12:29:29.465677 ===================================
6123 12:29:29.465790 memory_type:LPDDR4
6124 12:29:29.468633 GP_NUM : 10
6125 12:29:29.472187 SRAM_EN : 1
6126 12:29:29.472271 MD32_EN : 0
6127 12:29:29.475285 ===================================
6128 12:29:29.478732 [ANA_INIT] >>>>>>>>>>>>>>
6129 12:29:29.482225 <<<<<< [CONFIGURE PHASE]: ANA_TX
6130 12:29:29.485181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6131 12:29:29.488709 ===================================
6132 12:29:29.491961 data_rate = 800,PCW = 0X7400
6133 12:29:29.495426 ===================================
6134 12:29:29.498403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6135 12:29:29.501946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6136 12:29:29.515345 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 12:29:29.518404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6138 12:29:29.521852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6139 12:29:29.525164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6140 12:29:29.528168 [ANA_INIT] flow start
6141 12:29:29.531572 [ANA_INIT] PLL >>>>>>>>
6142 12:29:29.531692 [ANA_INIT] PLL <<<<<<<<
6143 12:29:29.535096 [ANA_INIT] MIDPI >>>>>>>>
6144 12:29:29.538087 [ANA_INIT] MIDPI <<<<<<<<
6145 12:29:29.538191 [ANA_INIT] DLL >>>>>>>>
6146 12:29:29.541589 [ANA_INIT] flow end
6147 12:29:29.544923 ============ LP4 DIFF to SE enter ============
6148 12:29:29.548344 ============ LP4 DIFF to SE exit ============
6149 12:29:29.551356 [ANA_INIT] <<<<<<<<<<<<<
6150 12:29:29.554670 [Flow] Enable top DCM control >>>>>
6151 12:29:29.557883 [Flow] Enable top DCM control <<<<<
6152 12:29:29.561470 Enable DLL master slave shuffle
6153 12:29:29.567975 ==============================================================
6154 12:29:29.568068 Gating Mode config
6155 12:29:29.574426 ==============================================================
6156 12:29:29.574535 Config description:
6157 12:29:29.584698 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6158 12:29:29.591250 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6159 12:29:29.597612 SELPH_MODE 0: By rank 1: By Phase
6160 12:29:29.604425 ==============================================================
6161 12:29:29.604533 GAT_TRACK_EN = 0
6162 12:29:29.607434 RX_GATING_MODE = 2
6163 12:29:29.611063 RX_GATING_TRACK_MODE = 2
6164 12:29:29.614173 SELPH_MODE = 1
6165 12:29:29.617544 PICG_EARLY_EN = 1
6166 12:29:29.621079 VALID_LAT_VALUE = 1
6167 12:29:29.627452 ==============================================================
6168 12:29:29.630730 Enter into Gating configuration >>>>
6169 12:29:29.633749 Exit from Gating configuration <<<<
6170 12:29:29.637301 Enter into DVFS_PRE_config >>>>>
6171 12:29:29.646972 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6172 12:29:29.650309 Exit from DVFS_PRE_config <<<<<
6173 12:29:29.653741 Enter into PICG configuration >>>>
6174 12:29:29.656740 Exit from PICG configuration <<<<
6175 12:29:29.660173 [RX_INPUT] configuration >>>>>
6176 12:29:29.663343 [RX_INPUT] configuration <<<<<
6177 12:29:29.666876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6178 12:29:29.673221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6179 12:29:29.679906 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 12:29:29.686810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 12:29:29.689808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 12:29:29.696543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 12:29:29.699882 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6184 12:29:29.706391 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6185 12:29:29.709870 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6186 12:29:29.713363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6187 12:29:29.716357 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6188 12:29:29.723105 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 12:29:29.726085 ===================================
6190 12:29:29.729585 LPDDR4 DRAM CONFIGURATION
6191 12:29:29.732976 ===================================
6192 12:29:29.733059 EX_ROW_EN[0] = 0x0
6193 12:29:29.736383 EX_ROW_EN[1] = 0x0
6194 12:29:29.736495 LP4Y_EN = 0x0
6195 12:29:29.739476 WORK_FSP = 0x0
6196 12:29:29.739559 WL = 0x2
6197 12:29:29.743051 RL = 0x2
6198 12:29:29.743134 BL = 0x2
6199 12:29:29.746508 RPST = 0x0
6200 12:29:29.746592 RD_PRE = 0x0
6201 12:29:29.749482 WR_PRE = 0x1
6202 12:29:29.749566 WR_PST = 0x0
6203 12:29:29.752826 DBI_WR = 0x0
6204 12:29:29.752909 DBI_RD = 0x0
6205 12:29:29.756329 OTF = 0x1
6206 12:29:29.759721 ===================================
6207 12:29:29.762836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6208 12:29:29.766285 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6209 12:29:29.772748 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 12:29:29.775907 ===================================
6211 12:29:29.775991 LPDDR4 DRAM CONFIGURATION
6212 12:29:29.779491 ===================================
6213 12:29:29.782854 EX_ROW_EN[0] = 0x10
6214 12:29:29.786151 EX_ROW_EN[1] = 0x0
6215 12:29:29.786249 LP4Y_EN = 0x0
6216 12:29:29.789371 WORK_FSP = 0x0
6217 12:29:29.789480 WL = 0x2
6218 12:29:29.792729 RL = 0x2
6219 12:29:29.792860 BL = 0x2
6220 12:29:29.795740 RPST = 0x0
6221 12:29:29.795840 RD_PRE = 0x0
6222 12:29:29.799296 WR_PRE = 0x1
6223 12:29:29.799397 WR_PST = 0x0
6224 12:29:29.802506 DBI_WR = 0x0
6225 12:29:29.802610 DBI_RD = 0x0
6226 12:29:29.805509 OTF = 0x1
6227 12:29:29.809026 ===================================
6228 12:29:29.815880 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6229 12:29:29.818963 nWR fixed to 30
6230 12:29:29.822514 [ModeRegInit_LP4] CH0 RK0
6231 12:29:29.822587 [ModeRegInit_LP4] CH0 RK1
6232 12:29:29.825816 [ModeRegInit_LP4] CH1 RK0
6233 12:29:29.828710 [ModeRegInit_LP4] CH1 RK1
6234 12:29:29.828851 match AC timing 19
6235 12:29:29.835270 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6236 12:29:29.838726 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6237 12:29:29.842214 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6238 12:29:29.848716 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6239 12:29:29.852165 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6240 12:29:29.852320 ==
6241 12:29:29.855153 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 12:29:29.858482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 12:29:29.858584 ==
6244 12:29:29.865071 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 12:29:29.871551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6246 12:29:29.874884 [CA 0] Center 36 (8~64) winsize 57
6247 12:29:29.878186 [CA 1] Center 36 (8~64) winsize 57
6248 12:29:29.881712 [CA 2] Center 36 (8~64) winsize 57
6249 12:29:29.885055 [CA 3] Center 36 (8~64) winsize 57
6250 12:29:29.885154 [CA 4] Center 36 (8~64) winsize 57
6251 12:29:29.888376 [CA 5] Center 36 (8~64) winsize 57
6252 12:29:29.888476
6253 12:29:29.894776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6254 12:29:29.894888
6255 12:29:29.897937 [CATrainingPosCal] consider 1 rank data
6256 12:29:29.901444 u2DelayCellTimex100 = 270/100 ps
6257 12:29:29.904799 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:29:29.908068 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:29:29.911520 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:29:29.914505 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:29:29.917889 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 12:29:29.921466 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 12:29:29.921604
6264 12:29:29.924548 CA PerBit enable=1, Macro0, CA PI delay=36
6265 12:29:29.924690
6266 12:29:29.928052 [CBTSetCACLKResult] CA Dly = 36
6267 12:29:29.931464 CS Dly: 1 (0~32)
6268 12:29:29.931571 ==
6269 12:29:29.934485 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 12:29:29.937905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 12:29:29.938020 ==
6272 12:29:29.944281 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6273 12:29:29.950694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6274 12:29:29.954244 [CA 0] Center 36 (8~64) winsize 57
6275 12:29:29.957295 [CA 1] Center 36 (8~64) winsize 57
6276 12:29:29.957410 [CA 2] Center 36 (8~64) winsize 57
6277 12:29:29.960730 [CA 3] Center 36 (8~64) winsize 57
6278 12:29:29.964162 [CA 4] Center 36 (8~64) winsize 57
6279 12:29:29.967180 [CA 5] Center 36 (8~64) winsize 57
6280 12:29:29.967289
6281 12:29:29.970672 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6282 12:29:29.974227
6283 12:29:29.977171 [CATrainingPosCal] consider 2 rank data
6284 12:29:29.980725 u2DelayCellTimex100 = 270/100 ps
6285 12:29:29.984109 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 12:29:29.987424 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 12:29:29.990608 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:29:29.993812 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 12:29:29.997041 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 12:29:30.000277 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 12:29:30.000381
6292 12:29:30.003498 CA PerBit enable=1, Macro0, CA PI delay=36
6293 12:29:30.003611
6294 12:29:30.007297 [CBTSetCACLKResult] CA Dly = 36
6295 12:29:30.010215 CS Dly: 1 (0~32)
6296 12:29:30.010319
6297 12:29:30.013552 ----->DramcWriteLeveling(PI) begin...
6298 12:29:30.013630 ==
6299 12:29:30.017090 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 12:29:30.019964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 12:29:30.020066 ==
6302 12:29:30.023432 Write leveling (Byte 0): 40 => 8
6303 12:29:30.026522 Write leveling (Byte 1): 32 => 0
6304 12:29:30.030038 DramcWriteLeveling(PI) end<-----
6305 12:29:30.030112
6306 12:29:30.030175 ==
6307 12:29:30.033377 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 12:29:30.036821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 12:29:30.036908 ==
6310 12:29:30.040250 [Gating] SW mode calibration
6311 12:29:30.046770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6312 12:29:30.053315 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6313 12:29:30.056730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6314 12:29:30.059731 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 12:29:30.066333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 12:29:30.069748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 12:29:30.073294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 12:29:30.079793 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 12:29:30.082814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 12:29:30.086308 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 12:29:30.092715 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 12:29:30.096147 Total UI for P1: 0, mck2ui 16
6323 12:29:30.099386 best dqsien dly found for B0: ( 0, 14, 24)
6324 12:29:30.102614 Total UI for P1: 0, mck2ui 16
6325 12:29:30.105820 best dqsien dly found for B1: ( 0, 14, 24)
6326 12:29:30.109161 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6327 12:29:30.112751 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6328 12:29:30.112845
6329 12:29:30.116020 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6330 12:29:30.119327 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 12:29:30.122783 [Gating] SW calibration Done
6332 12:29:30.122869 ==
6333 12:29:30.125675 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 12:29:30.129184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 12:29:30.129270 ==
6336 12:29:30.132657 RX Vref Scan: 0
6337 12:29:30.132741
6338 12:29:30.135585 RX Vref 0 -> 0, step: 1
6339 12:29:30.135659
6340 12:29:30.135722 RX Delay -410 -> 252, step: 16
6341 12:29:30.142522 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6342 12:29:30.146123 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6343 12:29:30.149465 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6344 12:29:30.155768 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6345 12:29:30.159388 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6346 12:29:30.162376 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6347 12:29:30.165512 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6348 12:29:30.172238 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6349 12:29:30.175338 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6350 12:29:30.178856 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6351 12:29:30.182430 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6352 12:29:30.188919 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6353 12:29:30.192247 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6354 12:29:30.195166 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6355 12:29:30.198737 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6356 12:29:30.205406 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6357 12:29:30.205498 ==
6358 12:29:30.208598 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 12:29:30.211830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 12:29:30.211935 ==
6361 12:29:30.212028 DQS Delay:
6362 12:29:30.214970 DQS0 = 27, DQS1 = 43
6363 12:29:30.215079 DQM Delay:
6364 12:29:30.218611 DQM0 = 13, DQM1 = 13
6365 12:29:30.218708 DQ Delay:
6366 12:29:30.221778 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6367 12:29:30.224938 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6368 12:29:30.228290 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6369 12:29:30.231798 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6370 12:29:30.231875
6371 12:29:30.231945
6372 12:29:30.232007 ==
6373 12:29:30.234820 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 12:29:30.238315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 12:29:30.238420 ==
6376 12:29:30.241633
6377 12:29:30.241711
6378 12:29:30.241775 TX Vref Scan disable
6379 12:29:30.244728 == TX Byte 0 ==
6380 12:29:30.248264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 12:29:30.251326 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 12:29:30.254696 == TX Byte 1 ==
6383 12:29:30.258216 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6384 12:29:30.261199 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6385 12:29:30.261276 ==
6386 12:29:30.264712 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 12:29:30.271436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 12:29:30.271584 ==
6389 12:29:30.271689
6390 12:29:30.271814
6391 12:29:30.271879 TX Vref Scan disable
6392 12:29:30.274344 == TX Byte 0 ==
6393 12:29:30.277787 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 12:29:30.280971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 12:29:30.284166 == TX Byte 1 ==
6396 12:29:30.287895 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6397 12:29:30.291259 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6398 12:29:30.291344
6399 12:29:30.294369 [DATLAT]
6400 12:29:30.294479 Freq=400, CH0 RK0
6401 12:29:30.294575
6402 12:29:30.297603 DATLAT Default: 0xf
6403 12:29:30.297707 0, 0xFFFF, sum = 0
6404 12:29:30.301092 1, 0xFFFF, sum = 0
6405 12:29:30.301166 2, 0xFFFF, sum = 0
6406 12:29:30.304044 3, 0xFFFF, sum = 0
6407 12:29:30.304116 4, 0xFFFF, sum = 0
6408 12:29:30.307551 5, 0xFFFF, sum = 0
6409 12:29:30.307656 6, 0xFFFF, sum = 0
6410 12:29:30.311003 7, 0xFFFF, sum = 0
6411 12:29:30.313866 8, 0xFFFF, sum = 0
6412 12:29:30.313956 9, 0xFFFF, sum = 0
6413 12:29:30.317299 10, 0xFFFF, sum = 0
6414 12:29:30.317385 11, 0xFFFF, sum = 0
6415 12:29:30.320532 12, 0xFFFF, sum = 0
6416 12:29:30.320620 13, 0x0, sum = 1
6417 12:29:30.323868 14, 0x0, sum = 2
6418 12:29:30.323955 15, 0x0, sum = 3
6419 12:29:30.326972 16, 0x0, sum = 4
6420 12:29:30.327060 best_step = 14
6421 12:29:30.327129
6422 12:29:30.327193 ==
6423 12:29:30.330369 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 12:29:30.333812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 12:29:30.333903 ==
6426 12:29:30.337335 RX Vref Scan: 1
6427 12:29:30.337422
6428 12:29:30.340402 RX Vref 0 -> 0, step: 1
6429 12:29:30.340489
6430 12:29:30.343513 RX Delay -327 -> 252, step: 8
6431 12:29:30.343600
6432 12:29:30.346910 Set Vref, RX VrefLevel [Byte0]: 61
6433 12:29:30.350045 [Byte1]: 49
6434 12:29:30.350132
6435 12:29:30.353293 Final RX Vref Byte 0 = 61 to rank0
6436 12:29:30.356781 Final RX Vref Byte 1 = 49 to rank0
6437 12:29:30.360213 Final RX Vref Byte 0 = 61 to rank1
6438 12:29:30.363269 Final RX Vref Byte 1 = 49 to rank1==
6439 12:29:30.366436 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 12:29:30.370028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 12:29:30.370110 ==
6442 12:29:30.373153 DQS Delay:
6443 12:29:30.373231 DQS0 = 24, DQS1 = 48
6444 12:29:30.376288 DQM Delay:
6445 12:29:30.376398 DQM0 = 8, DQM1 = 16
6446 12:29:30.376504 DQ Delay:
6447 12:29:30.379871 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6448 12:29:30.383093 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6449 12:29:30.386310 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6450 12:29:30.389768 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6451 12:29:30.389894
6452 12:29:30.390002
6453 12:29:30.399762 [DQSOSCAuto] RK0, (LSB)MR18= 0xaba3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6454 12:29:30.399894 CH0 RK0: MR19=C0C, MR18=ABA3
6455 12:29:30.406189 CH0_RK0: MR19=0xC0C, MR18=0xABA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6456 12:29:30.406310 ==
6457 12:29:30.409893 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 12:29:30.416249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 12:29:30.416375 ==
6460 12:29:30.419718 [Gating] SW mode calibration
6461 12:29:30.426031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6462 12:29:30.429471 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6463 12:29:30.436160 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6464 12:29:30.439404 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 12:29:30.442867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 12:29:30.449533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 12:29:30.452523 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 12:29:30.456049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 12:29:30.462887 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 12:29:30.465906 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 12:29:30.469384 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 12:29:30.472474 Total UI for P1: 0, mck2ui 16
6473 12:29:30.476056 best dqsien dly found for B0: ( 0, 14, 24)
6474 12:29:30.479420 Total UI for P1: 0, mck2ui 16
6475 12:29:30.482636 best dqsien dly found for B1: ( 0, 14, 24)
6476 12:29:30.486065 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6477 12:29:30.489411 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6478 12:29:30.489531
6479 12:29:30.495895 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6480 12:29:30.498902 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 12:29:30.498992 [Gating] SW calibration Done
6482 12:29:30.502427 ==
6483 12:29:30.505694 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 12:29:30.508771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 12:29:30.508870 ==
6486 12:29:30.508940 RX Vref Scan: 0
6487 12:29:30.509006
6488 12:29:30.512250 RX Vref 0 -> 0, step: 1
6489 12:29:30.512337
6490 12:29:30.515239 RX Delay -410 -> 252, step: 16
6491 12:29:30.518798 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6492 12:29:30.525136 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6493 12:29:30.528505 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6494 12:29:30.531670 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6495 12:29:30.535437 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6496 12:29:30.541821 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6497 12:29:30.545444 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6498 12:29:30.548278 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6499 12:29:30.551787 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6500 12:29:30.558216 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6501 12:29:30.561838 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6502 12:29:30.565327 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6503 12:29:30.568263 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6504 12:29:30.574856 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6505 12:29:30.578033 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6506 12:29:30.581217 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6507 12:29:30.581339 ==
6508 12:29:30.584839 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 12:29:30.591358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 12:29:30.591488 ==
6511 12:29:30.591589 DQS Delay:
6512 12:29:30.594477 DQS0 = 27, DQS1 = 43
6513 12:29:30.594596 DQM Delay:
6514 12:29:30.594696 DQM0 = 9, DQM1 = 15
6515 12:29:30.598240 DQ Delay:
6516 12:29:30.601433 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6517 12:29:30.601553 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6518 12:29:30.604463 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6519 12:29:30.608013 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6520 12:29:30.608137
6521 12:29:30.611379
6522 12:29:30.611462 ==
6523 12:29:30.614499 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 12:29:30.617946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 12:29:30.618046 ==
6526 12:29:30.618117
6527 12:29:30.618181
6528 12:29:30.621002 TX Vref Scan disable
6529 12:29:30.621080 == TX Byte 0 ==
6530 12:29:30.624326 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6531 12:29:30.630812 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6532 12:29:30.630894 == TX Byte 1 ==
6533 12:29:30.634197 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6534 12:29:30.640694 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6535 12:29:30.640819 ==
6536 12:29:30.643992 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 12:29:30.647379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 12:29:30.647498 ==
6539 12:29:30.647599
6540 12:29:30.647667
6541 12:29:30.650629 TX Vref Scan disable
6542 12:29:30.650712 == TX Byte 0 ==
6543 12:29:30.654289 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6544 12:29:30.660979 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6545 12:29:30.661089 == TX Byte 1 ==
6546 12:29:30.664075 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6547 12:29:30.670498 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6548 12:29:30.670585
6549 12:29:30.670653 [DATLAT]
6550 12:29:30.673921 Freq=400, CH0 RK1
6551 12:29:30.674000
6552 12:29:30.674066 DATLAT Default: 0xe
6553 12:29:30.677108 0, 0xFFFF, sum = 0
6554 12:29:30.677183 1, 0xFFFF, sum = 0
6555 12:29:30.680572 2, 0xFFFF, sum = 0
6556 12:29:30.680651 3, 0xFFFF, sum = 0
6557 12:29:30.683587 4, 0xFFFF, sum = 0
6558 12:29:30.683661 5, 0xFFFF, sum = 0
6559 12:29:30.687180 6, 0xFFFF, sum = 0
6560 12:29:30.687257 7, 0xFFFF, sum = 0
6561 12:29:30.690418 8, 0xFFFF, sum = 0
6562 12:29:30.690506 9, 0xFFFF, sum = 0
6563 12:29:30.693516 10, 0xFFFF, sum = 0
6564 12:29:30.693595 11, 0xFFFF, sum = 0
6565 12:29:30.697067 12, 0xFFFF, sum = 0
6566 12:29:30.697162 13, 0x0, sum = 1
6567 12:29:30.700134 14, 0x0, sum = 2
6568 12:29:30.700220 15, 0x0, sum = 3
6569 12:29:30.703575 16, 0x0, sum = 4
6570 12:29:30.703654 best_step = 14
6571 12:29:30.703729
6572 12:29:30.703791 ==
6573 12:29:30.707065 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 12:29:30.713747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 12:29:30.713828 ==
6576 12:29:30.713894 RX Vref Scan: 0
6577 12:29:30.713963
6578 12:29:30.716796 RX Vref 0 -> 0, step: 1
6579 12:29:30.716900
6580 12:29:30.720315 RX Delay -327 -> 252, step: 8
6581 12:29:30.726898 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6582 12:29:30.730471 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6583 12:29:30.733494 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6584 12:29:30.736747 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6585 12:29:30.743691 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6586 12:29:30.746520 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6587 12:29:30.749817 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6588 12:29:30.753246 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6589 12:29:30.759847 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6590 12:29:30.763218 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6591 12:29:30.766773 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6592 12:29:30.770153 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6593 12:29:30.776461 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6594 12:29:30.779950 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6595 12:29:30.783409 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6596 12:29:30.786397 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6597 12:29:30.789896 ==
6598 12:29:30.793273 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 12:29:30.796533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 12:29:30.796618 ==
6601 12:29:30.796685 DQS Delay:
6602 12:29:30.799583 DQS0 = 28, DQS1 = 44
6603 12:29:30.799668 DQM Delay:
6604 12:29:30.802922 DQM0 = 11, DQM1 = 15
6605 12:29:30.803006 DQ Delay:
6606 12:29:30.806459 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6607 12:29:30.809545 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6608 12:29:30.813175 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6609 12:29:30.816108 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6610 12:29:30.816184
6611 12:29:30.816247
6612 12:29:30.823258 [DQSOSCAuto] RK1, (LSB)MR18= 0xb569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6613 12:29:30.826399 CH0 RK1: MR19=C0C, MR18=B569
6614 12:29:30.832809 CH0_RK1: MR19=0xC0C, MR18=0xB569, DQSOSC=387, MR23=63, INC=394, DEC=262
6615 12:29:30.835933 [RxdqsGatingPostProcess] freq 400
6616 12:29:30.839724 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6617 12:29:30.842666 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 12:29:30.846210 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 12:29:30.849593 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 12:29:30.852522 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 12:29:30.856190 best DQS0 dly(2T, 0.5T) = (0, 10)
6622 12:29:30.859261 best DQS1 dly(2T, 0.5T) = (0, 10)
6623 12:29:30.862748 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6624 12:29:30.865639 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6625 12:29:30.869254 Pre-setting of DQS Precalculation
6626 12:29:30.875750 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6627 12:29:30.875863 ==
6628 12:29:30.879178 Dram Type= 6, Freq= 0, CH_1, rank 0
6629 12:29:30.882229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 12:29:30.882309 ==
6631 12:29:30.888931 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 12:29:30.892428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6633 12:29:30.895650 [CA 0] Center 36 (8~64) winsize 57
6634 12:29:30.898621 [CA 1] Center 36 (8~64) winsize 57
6635 12:29:30.902248 [CA 2] Center 36 (8~64) winsize 57
6636 12:29:30.905423 [CA 3] Center 36 (8~64) winsize 57
6637 12:29:30.908496 [CA 4] Center 36 (8~64) winsize 57
6638 12:29:30.912084 [CA 5] Center 36 (8~64) winsize 57
6639 12:29:30.912197
6640 12:29:30.915218 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6641 12:29:30.915304
6642 12:29:30.918696 [CATrainingPosCal] consider 1 rank data
6643 12:29:30.921685 u2DelayCellTimex100 = 270/100 ps
6644 12:29:30.925173 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:29:30.928360 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:29:30.935049 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:29:30.938167 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:29:30.941773 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 12:29:30.944651 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 12:29:30.944755
6651 12:29:30.948054 CA PerBit enable=1, Macro0, CA PI delay=36
6652 12:29:30.948132
6653 12:29:30.951455 [CBTSetCACLKResult] CA Dly = 36
6654 12:29:30.951532 CS Dly: 1 (0~32)
6655 12:29:30.955062 ==
6656 12:29:30.955137 Dram Type= 6, Freq= 0, CH_1, rank 1
6657 12:29:30.961406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 12:29:30.961494 ==
6659 12:29:30.964660 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6660 12:29:30.971389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6661 12:29:30.974671 [CA 0] Center 36 (8~64) winsize 57
6662 12:29:30.977988 [CA 1] Center 36 (8~64) winsize 57
6663 12:29:30.981056 [CA 2] Center 36 (8~64) winsize 57
6664 12:29:30.984391 [CA 3] Center 36 (8~64) winsize 57
6665 12:29:30.987993 [CA 4] Center 36 (8~64) winsize 57
6666 12:29:30.991123 [CA 5] Center 36 (8~64) winsize 57
6667 12:29:30.991247
6668 12:29:30.994203 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6669 12:29:30.994313
6670 12:29:30.997811 [CATrainingPosCal] consider 2 rank data
6671 12:29:31.000824 u2DelayCellTimex100 = 270/100 ps
6672 12:29:31.004330 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 12:29:31.007826 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 12:29:31.010846 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:29:31.014385 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 12:29:31.020794 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 12:29:31.024230 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 12:29:31.024336
6679 12:29:31.027155 CA PerBit enable=1, Macro0, CA PI delay=36
6680 12:29:31.027261
6681 12:29:31.030776 [CBTSetCACLKResult] CA Dly = 36
6682 12:29:31.030880 CS Dly: 1 (0~32)
6683 12:29:31.030974
6684 12:29:31.034261 ----->DramcWriteLeveling(PI) begin...
6685 12:29:31.034367 ==
6686 12:29:31.037297 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 12:29:31.044312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 12:29:31.044420 ==
6689 12:29:31.047307 Write leveling (Byte 0): 40 => 8
6690 12:29:31.050603 Write leveling (Byte 1): 32 => 0
6691 12:29:31.050709 DramcWriteLeveling(PI) end<-----
6692 12:29:31.050805
6693 12:29:31.054074 ==
6694 12:29:31.057130 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 12:29:31.060652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 12:29:31.060771 ==
6697 12:29:31.063691 [Gating] SW mode calibration
6698 12:29:31.070625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6699 12:29:31.074073 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6700 12:29:31.080353 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6701 12:29:31.083759 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 12:29:31.086768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 12:29:31.093549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 12:29:31.096882 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 12:29:31.099995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 12:29:31.106724 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 12:29:31.110314 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 12:29:31.113389 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 12:29:31.116878 Total UI for P1: 0, mck2ui 16
6710 12:29:31.120389 best dqsien dly found for B0: ( 0, 14, 24)
6711 12:29:31.123398 Total UI for P1: 0, mck2ui 16
6712 12:29:31.126804 best dqsien dly found for B1: ( 0, 14, 24)
6713 12:29:31.130149 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6714 12:29:31.133214 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6715 12:29:31.133296
6716 12:29:31.139786 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6717 12:29:31.143318 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 12:29:31.146257 [Gating] SW calibration Done
6719 12:29:31.146348 ==
6720 12:29:31.149855 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 12:29:31.152916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 12:29:31.153011 ==
6723 12:29:31.153090 RX Vref Scan: 0
6724 12:29:31.153191
6725 12:29:31.156333 RX Vref 0 -> 0, step: 1
6726 12:29:31.156450
6727 12:29:31.159762 RX Delay -410 -> 252, step: 16
6728 12:29:31.162776 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6729 12:29:31.169719 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6730 12:29:31.172665 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6731 12:29:31.176225 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6732 12:29:31.179743 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6733 12:29:31.186345 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6734 12:29:31.189753 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6735 12:29:31.192608 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6736 12:29:31.196088 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6737 12:29:31.202630 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6738 12:29:31.206142 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6739 12:29:31.209100 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6740 12:29:31.212933 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6741 12:29:31.219128 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6742 12:29:31.222307 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6743 12:29:31.225895 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6744 12:29:31.225986 ==
6745 12:29:31.229023 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 12:29:31.235513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 12:29:31.235602 ==
6748 12:29:31.235671 DQS Delay:
6749 12:29:31.239237 DQS0 = 27, DQS1 = 43
6750 12:29:31.239324 DQM Delay:
6751 12:29:31.239392 DQM0 = 5, DQM1 = 15
6752 12:29:31.242276 DQ Delay:
6753 12:29:31.245406 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6754 12:29:31.245493 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6755 12:29:31.248856 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6756 12:29:31.252297 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6757 12:29:31.255247
6758 12:29:31.255333
6759 12:29:31.255400 ==
6760 12:29:31.258511 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 12:29:31.261986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 12:29:31.262073 ==
6763 12:29:31.262143
6764 12:29:31.262206
6765 12:29:31.265497 TX Vref Scan disable
6766 12:29:31.265583 == TX Byte 0 ==
6767 12:29:31.268595 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 12:29:31.275264 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 12:29:31.275350 == TX Byte 1 ==
6770 12:29:31.278705 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6771 12:29:31.285253 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6772 12:29:31.285370 ==
6773 12:29:31.288547 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 12:29:31.291994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 12:29:31.292080 ==
6776 12:29:31.292148
6777 12:29:31.292211
6778 12:29:31.294887 TX Vref Scan disable
6779 12:29:31.294972 == TX Byte 0 ==
6780 12:29:31.302030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 12:29:31.305112 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 12:29:31.305198 == TX Byte 1 ==
6783 12:29:31.311714 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6784 12:29:31.315225 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6785 12:29:31.315325
6786 12:29:31.315423 [DATLAT]
6787 12:29:31.318599 Freq=400, CH1 RK0
6788 12:29:31.318684
6789 12:29:31.318749 DATLAT Default: 0xf
6790 12:29:31.321528 0, 0xFFFF, sum = 0
6791 12:29:31.321614 1, 0xFFFF, sum = 0
6792 12:29:31.324966 2, 0xFFFF, sum = 0
6793 12:29:31.325051 3, 0xFFFF, sum = 0
6794 12:29:31.328048 4, 0xFFFF, sum = 0
6795 12:29:31.328133 5, 0xFFFF, sum = 0
6796 12:29:31.331576 6, 0xFFFF, sum = 0
6797 12:29:31.331661 7, 0xFFFF, sum = 0
6798 12:29:31.334971 8, 0xFFFF, sum = 0
6799 12:29:31.335086 9, 0xFFFF, sum = 0
6800 12:29:31.338355 10, 0xFFFF, sum = 0
6801 12:29:31.341381 11, 0xFFFF, sum = 0
6802 12:29:31.341465 12, 0xFFFF, sum = 0
6803 12:29:31.344974 13, 0x0, sum = 1
6804 12:29:31.345058 14, 0x0, sum = 2
6805 12:29:31.348020 15, 0x0, sum = 3
6806 12:29:31.348105 16, 0x0, sum = 4
6807 12:29:31.348173 best_step = 14
6808 12:29:31.348234
6809 12:29:31.351434 ==
6810 12:29:31.354858 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 12:29:31.357821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 12:29:31.357906 ==
6813 12:29:31.357972 RX Vref Scan: 1
6814 12:29:31.358034
6815 12:29:31.361182 RX Vref 0 -> 0, step: 1
6816 12:29:31.361266
6817 12:29:31.364433 RX Delay -327 -> 252, step: 8
6818 12:29:31.364518
6819 12:29:31.367898 Set Vref, RX VrefLevel [Byte0]: 52
6820 12:29:31.370845 [Byte1]: 50
6821 12:29:31.374770
6822 12:29:31.374874 Final RX Vref Byte 0 = 52 to rank0
6823 12:29:31.378152 Final RX Vref Byte 1 = 50 to rank0
6824 12:29:31.381441 Final RX Vref Byte 0 = 52 to rank1
6825 12:29:31.384652 Final RX Vref Byte 1 = 50 to rank1==
6826 12:29:31.388096 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 12:29:31.394775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 12:29:31.394883 ==
6829 12:29:31.394979 DQS Delay:
6830 12:29:31.398042 DQS0 = 28, DQS1 = 40
6831 12:29:31.398127 DQM Delay:
6832 12:29:31.398193 DQM0 = 8, DQM1 = 12
6833 12:29:31.401193 DQ Delay:
6834 12:29:31.404499 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6835 12:29:31.404609 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6836 12:29:31.408178 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6837 12:29:31.411260 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6838 12:29:31.411363
6839 12:29:31.411456
6840 12:29:31.421251 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6841 12:29:31.424326 CH1 RK0: MR19=C0C, MR18=8DC8
6842 12:29:31.430750 CH1_RK0: MR19=0xC0C, MR18=0x8DC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6843 12:29:31.430853 ==
6844 12:29:31.434354 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 12:29:31.437356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 12:29:31.437442 ==
6847 12:29:31.440731 [Gating] SW mode calibration
6848 12:29:31.447410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6849 12:29:31.454115 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6850 12:29:31.457571 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6851 12:29:31.460427 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 12:29:31.467752 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 12:29:31.470433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 12:29:31.473949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 12:29:31.480552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 12:29:31.483579 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 12:29:31.487036 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 12:29:31.493627 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 12:29:31.493728 Total UI for P1: 0, mck2ui 16
6860 12:29:31.500096 best dqsien dly found for B0: ( 0, 14, 24)
6861 12:29:31.500217 Total UI for P1: 0, mck2ui 16
6862 12:29:31.506521 best dqsien dly found for B1: ( 0, 14, 24)
6863 12:29:31.510184 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6864 12:29:31.513123 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6865 12:29:31.513234
6866 12:29:31.516545 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6867 12:29:31.519724 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 12:29:31.523250 [Gating] SW calibration Done
6869 12:29:31.523354 ==
6870 12:29:31.526376 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 12:29:31.529902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 12:29:31.530013 ==
6873 12:29:31.533127 RX Vref Scan: 0
6874 12:29:31.533213
6875 12:29:31.533281 RX Vref 0 -> 0, step: 1
6876 12:29:31.536143
6877 12:29:31.536232 RX Delay -410 -> 252, step: 16
6878 12:29:31.542778 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6879 12:29:31.546203 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6880 12:29:31.549310 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6881 12:29:31.552737 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6882 12:29:31.559288 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6883 12:29:31.562710 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6884 12:29:31.566281 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6885 12:29:31.569289 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6886 12:29:31.576148 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6887 12:29:31.579452 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6888 12:29:31.582509 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6889 12:29:31.589219 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6890 12:29:31.592651 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6891 12:29:31.595742 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6892 12:29:31.599303 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6893 12:29:31.605659 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6894 12:29:31.605775 ==
6895 12:29:31.608718 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 12:29:31.612199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 12:29:31.612306 ==
6898 12:29:31.612402 DQS Delay:
6899 12:29:31.615666 DQS0 = 35, DQS1 = 43
6900 12:29:31.615773 DQM Delay:
6901 12:29:31.619044 DQM0 = 16, DQM1 = 19
6902 12:29:31.619130 DQ Delay:
6903 12:29:31.622015 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6904 12:29:31.625637 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6905 12:29:31.628663 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6906 12:29:31.632281 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6907 12:29:31.632368
6908 12:29:31.632437
6909 12:29:31.632500 ==
6910 12:29:31.635457 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 12:29:31.638357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 12:29:31.641940 ==
6913 12:29:31.642045
6914 12:29:31.642140
6915 12:29:31.642232 TX Vref Scan disable
6916 12:29:31.645107 == TX Byte 0 ==
6917 12:29:31.648659 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6918 12:29:31.652065 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6919 12:29:31.655153 == TX Byte 1 ==
6920 12:29:31.658244 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6921 12:29:31.661852 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6922 12:29:31.661945 ==
6923 12:29:31.664835 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 12:29:31.671422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 12:29:31.671567 ==
6926 12:29:31.671673
6927 12:29:31.671769
6928 12:29:31.671862 TX Vref Scan disable
6929 12:29:31.674886 == TX Byte 0 ==
6930 12:29:31.678474 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6931 12:29:31.681823 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6932 12:29:31.684965 == TX Byte 1 ==
6933 12:29:31.687929 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6934 12:29:31.691404 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6935 12:29:31.691511
6936 12:29:31.694860 [DATLAT]
6937 12:29:31.694949 Freq=400, CH1 RK1
6938 12:29:31.695017
6939 12:29:31.698238 DATLAT Default: 0xe
6940 12:29:31.698320 0, 0xFFFF, sum = 0
6941 12:29:31.701328 1, 0xFFFF, sum = 0
6942 12:29:31.701411 2, 0xFFFF, sum = 0
6943 12:29:31.704877 3, 0xFFFF, sum = 0
6944 12:29:31.704991 4, 0xFFFF, sum = 0
6945 12:29:31.708331 5, 0xFFFF, sum = 0
6946 12:29:31.708438 6, 0xFFFF, sum = 0
6947 12:29:31.711353 7, 0xFFFF, sum = 0
6948 12:29:31.711432 8, 0xFFFF, sum = 0
6949 12:29:31.714906 9, 0xFFFF, sum = 0
6950 12:29:31.714993 10, 0xFFFF, sum = 0
6951 12:29:31.718110 11, 0xFFFF, sum = 0
6952 12:29:31.721169 12, 0xFFFF, sum = 0
6953 12:29:31.721257 13, 0x0, sum = 1
6954 12:29:31.721326 14, 0x0, sum = 2
6955 12:29:31.724502 15, 0x0, sum = 3
6956 12:29:31.724590 16, 0x0, sum = 4
6957 12:29:31.728087 best_step = 14
6958 12:29:31.728200
6959 12:29:31.728297 ==
6960 12:29:31.731006 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 12:29:31.734429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 12:29:31.734544 ==
6963 12:29:31.738003 RX Vref Scan: 0
6964 12:29:31.738107
6965 12:29:31.738215 RX Vref 0 -> 0, step: 1
6966 12:29:31.738317
6967 12:29:31.740922 RX Delay -327 -> 252, step: 8
6968 12:29:31.749428 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6969 12:29:31.752991 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6970 12:29:31.756014 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6971 12:29:31.759120 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6972 12:29:31.765863 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6973 12:29:31.769435 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6974 12:29:31.772340 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6975 12:29:31.775953 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6976 12:29:31.782279 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6977 12:29:31.785765 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6978 12:29:31.788924 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6979 12:29:31.795849 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6980 12:29:31.798777 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6981 12:29:31.802135 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6982 12:29:31.805731 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6983 12:29:31.812498 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6984 12:29:31.812606 ==
6985 12:29:31.815375 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 12:29:31.818916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 12:29:31.819022 ==
6988 12:29:31.819129 DQS Delay:
6989 12:29:31.822387 DQS0 = 32, DQS1 = 36
6990 12:29:31.822492 DQM Delay:
6991 12:29:31.825377 DQM0 = 12, DQM1 = 12
6992 12:29:31.825483 DQ Delay:
6993 12:29:31.828744 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6994 12:29:31.832013 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
6995 12:29:31.835054 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6996 12:29:31.838586 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6997 12:29:31.838700
6998 12:29:31.838799
6999 12:29:31.845258 [DQSOSCAuto] RK1, (LSB)MR18= 0xa851, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7000 12:29:31.848301 CH1 RK1: MR19=C0C, MR18=A851
7001 12:29:31.855424 CH1_RK1: MR19=0xC0C, MR18=0xA851, DQSOSC=388, MR23=63, INC=392, DEC=261
7002 12:29:31.858596 [RxdqsGatingPostProcess] freq 400
7003 12:29:31.865163 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7004 12:29:31.868246 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 12:29:31.871697 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 12:29:31.875109 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 12:29:31.878140 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 12:29:31.878227 best DQS0 dly(2T, 0.5T) = (0, 10)
7009 12:29:31.881495 best DQS1 dly(2T, 0.5T) = (0, 10)
7010 12:29:31.884835 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7011 12:29:31.888383 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7012 12:29:31.891495 Pre-setting of DQS Precalculation
7013 12:29:31.897939 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7014 12:29:31.904602 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7015 12:29:31.911234 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7016 12:29:31.911321
7017 12:29:31.911390
7018 12:29:31.914546 [Calibration Summary] 800 Mbps
7019 12:29:31.917953 CH 0, Rank 0
7020 12:29:31.918039 SW Impedance : PASS
7021 12:29:31.920995 DUTY Scan : NO K
7022 12:29:31.921082 ZQ Calibration : PASS
7023 12:29:31.924446 Jitter Meter : NO K
7024 12:29:31.927869 CBT Training : PASS
7025 12:29:31.927983 Write leveling : PASS
7026 12:29:31.931112 RX DQS gating : PASS
7027 12:29:31.934340 RX DQ/DQS(RDDQC) : PASS
7028 12:29:31.934453 TX DQ/DQS : PASS
7029 12:29:31.937677 RX DATLAT : PASS
7030 12:29:31.940932 RX DQ/DQS(Engine): PASS
7031 12:29:31.941045 TX OE : NO K
7032 12:29:31.944194 All Pass.
7033 12:29:31.944302
7034 12:29:31.944397 CH 0, Rank 1
7035 12:29:31.947733 SW Impedance : PASS
7036 12:29:31.947845 DUTY Scan : NO K
7037 12:29:31.950710 ZQ Calibration : PASS
7038 12:29:31.954324 Jitter Meter : NO K
7039 12:29:31.954430 CBT Training : PASS
7040 12:29:31.957384 Write leveling : NO K
7041 12:29:31.960839 RX DQS gating : PASS
7042 12:29:31.960941 RX DQ/DQS(RDDQC) : PASS
7043 12:29:31.964195 TX DQ/DQS : PASS
7044 12:29:31.967166 RX DATLAT : PASS
7045 12:29:31.967254 RX DQ/DQS(Engine): PASS
7046 12:29:31.970731 TX OE : NO K
7047 12:29:31.970847 All Pass.
7048 12:29:31.970947
7049 12:29:31.973674 CH 1, Rank 0
7050 12:29:31.973751 SW Impedance : PASS
7051 12:29:31.977156 DUTY Scan : NO K
7052 12:29:31.980540 ZQ Calibration : PASS
7053 12:29:31.980647 Jitter Meter : NO K
7054 12:29:31.984170 CBT Training : PASS
7055 12:29:31.984243 Write leveling : PASS
7056 12:29:31.987017 RX DQS gating : PASS
7057 12:29:31.990426 RX DQ/DQS(RDDQC) : PASS
7058 12:29:31.990512 TX DQ/DQS : PASS
7059 12:29:31.993892 RX DATLAT : PASS
7060 12:29:31.996892 RX DQ/DQS(Engine): PASS
7061 12:29:31.996977 TX OE : NO K
7062 12:29:32.000452 All Pass.
7063 12:29:32.000564
7064 12:29:32.000661 CH 1, Rank 1
7065 12:29:32.003754 SW Impedance : PASS
7066 12:29:32.003867 DUTY Scan : NO K
7067 12:29:32.007198 ZQ Calibration : PASS
7068 12:29:32.010577 Jitter Meter : NO K
7069 12:29:32.010670 CBT Training : PASS
7070 12:29:32.013551 Write leveling : NO K
7071 12:29:32.017059 RX DQS gating : PASS
7072 12:29:32.017151 RX DQ/DQS(RDDQC) : PASS
7073 12:29:32.020330 TX DQ/DQS : PASS
7074 12:29:32.023679 RX DATLAT : PASS
7075 12:29:32.023784 RX DQ/DQS(Engine): PASS
7076 12:29:32.027245 TX OE : NO K
7077 12:29:32.027338 All Pass.
7078 12:29:32.027430
7079 12:29:32.030156 DramC Write-DBI off
7080 12:29:32.033727 PER_BANK_REFRESH: Hybrid Mode
7081 12:29:32.033813 TX_TRACKING: ON
7082 12:29:32.043470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7083 12:29:32.046660 [FAST_K] Save calibration result to emmc
7084 12:29:32.050064 dramc_set_vcore_voltage set vcore to 725000
7085 12:29:32.053574 Read voltage for 1600, 0
7086 12:29:32.053662 Vio18 = 0
7087 12:29:32.053730 Vcore = 725000
7088 12:29:32.056638 Vdram = 0
7089 12:29:32.056724 Vddq = 0
7090 12:29:32.056801 Vmddr = 0
7091 12:29:32.063575 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7092 12:29:32.066481 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7093 12:29:32.069794 MEM_TYPE=3, freq_sel=13
7094 12:29:32.073405 sv_algorithm_assistance_LP4_3733
7095 12:29:32.076486 ============ PULL DRAM RESETB DOWN ============
7096 12:29:32.079862 ========== PULL DRAM RESETB DOWN end =========
7097 12:29:32.086354 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7098 12:29:32.089881 ===================================
7099 12:29:32.093156 LPDDR4 DRAM CONFIGURATION
7100 12:29:32.096197 ===================================
7101 12:29:32.096279 EX_ROW_EN[0] = 0x0
7102 12:29:32.099623 EX_ROW_EN[1] = 0x0
7103 12:29:32.099710 LP4Y_EN = 0x0
7104 12:29:32.103000 WORK_FSP = 0x1
7105 12:29:32.103118 WL = 0x5
7106 12:29:32.106098 RL = 0x5
7107 12:29:32.106185 BL = 0x2
7108 12:29:32.109405 RPST = 0x0
7109 12:29:32.109492 RD_PRE = 0x0
7110 12:29:32.112685 WR_PRE = 0x1
7111 12:29:32.112802 WR_PST = 0x1
7112 12:29:32.116133 DBI_WR = 0x0
7113 12:29:32.116219 DBI_RD = 0x0
7114 12:29:32.119574 OTF = 0x1
7115 12:29:32.122950 ===================================
7116 12:29:32.126094 ===================================
7117 12:29:32.126181 ANA top config
7118 12:29:32.129557 ===================================
7119 12:29:32.132650 DLL_ASYNC_EN = 0
7120 12:29:32.136229 ALL_SLAVE_EN = 0
7121 12:29:32.139261 NEW_RANK_MODE = 1
7122 12:29:32.139350 DLL_IDLE_MODE = 1
7123 12:29:32.142696 LP45_APHY_COMB_EN = 1
7124 12:29:32.146200 TX_ODT_DIS = 0
7125 12:29:32.149267 NEW_8X_MODE = 1
7126 12:29:32.152593 ===================================
7127 12:29:32.155972 ===================================
7128 12:29:32.159552 data_rate = 3200
7129 12:29:32.162548 CKR = 1
7130 12:29:32.162624 DQ_P2S_RATIO = 8
7131 12:29:32.166216 ===================================
7132 12:29:32.169352 CA_P2S_RATIO = 8
7133 12:29:32.172667 DQ_CA_OPEN = 0
7134 12:29:32.175871 DQ_SEMI_OPEN = 0
7135 12:29:32.179370 CA_SEMI_OPEN = 0
7136 12:29:32.179455 CA_FULL_RATE = 0
7137 12:29:32.182377 DQ_CKDIV4_EN = 0
7138 12:29:32.185879 CA_CKDIV4_EN = 0
7139 12:29:32.188918 CA_PREDIV_EN = 0
7140 12:29:32.192584 PH8_DLY = 12
7141 12:29:32.195790 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7142 12:29:32.198910 DQ_AAMCK_DIV = 4
7143 12:29:32.198997 CA_AAMCK_DIV = 4
7144 12:29:32.202448 CA_ADMCK_DIV = 4
7145 12:29:32.205477 DQ_TRACK_CA_EN = 0
7146 12:29:32.208869 CA_PICK = 1600
7147 12:29:32.212254 CA_MCKIO = 1600
7148 12:29:32.215595 MCKIO_SEMI = 0
7149 12:29:32.219187 PLL_FREQ = 3068
7150 12:29:32.219277 DQ_UI_PI_RATIO = 32
7151 12:29:32.222374 CA_UI_PI_RATIO = 0
7152 12:29:32.225913 ===================================
7153 12:29:32.228796 ===================================
7154 12:29:32.232173 memory_type:LPDDR4
7155 12:29:32.235787 GP_NUM : 10
7156 12:29:32.235874 SRAM_EN : 1
7157 12:29:32.238886 MD32_EN : 0
7158 12:29:32.241889 ===================================
7159 12:29:32.245441 [ANA_INIT] >>>>>>>>>>>>>>
7160 12:29:32.245528 <<<<<< [CONFIGURE PHASE]: ANA_TX
7161 12:29:32.248916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7162 12:29:32.251981 ===================================
7163 12:29:32.255494 data_rate = 3200,PCW = 0X7600
7164 12:29:32.258931 ===================================
7165 12:29:32.262155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7166 12:29:32.268315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7167 12:29:32.275181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 12:29:32.278244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7169 12:29:32.281676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7170 12:29:32.285270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7171 12:29:32.288347 [ANA_INIT] flow start
7172 12:29:32.288433 [ANA_INIT] PLL >>>>>>>>
7173 12:29:32.291724 [ANA_INIT] PLL <<<<<<<<
7174 12:29:32.294730 [ANA_INIT] MIDPI >>>>>>>>
7175 12:29:32.298228 [ANA_INIT] MIDPI <<<<<<<<
7176 12:29:32.298315 [ANA_INIT] DLL >>>>>>>>
7177 12:29:32.301614 [ANA_INIT] DLL <<<<<<<<
7178 12:29:32.301701 [ANA_INIT] flow end
7179 12:29:32.308121 ============ LP4 DIFF to SE enter ============
7180 12:29:32.311241 ============ LP4 DIFF to SE exit ============
7181 12:29:32.314643 [ANA_INIT] <<<<<<<<<<<<<
7182 12:29:32.318193 [Flow] Enable top DCM control >>>>>
7183 12:29:32.321288 [Flow] Enable top DCM control <<<<<
7184 12:29:32.324483 Enable DLL master slave shuffle
7185 12:29:32.327891 ==============================================================
7186 12:29:32.331241 Gating Mode config
7187 12:29:32.334700 ==============================================================
7188 12:29:32.337875 Config description:
7189 12:29:32.347543 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7190 12:29:32.354468 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7191 12:29:32.357518 SELPH_MODE 0: By rank 1: By Phase
7192 12:29:32.364081 ==============================================================
7193 12:29:32.367507 GAT_TRACK_EN = 1
7194 12:29:32.370953 RX_GATING_MODE = 2
7195 12:29:32.374197 RX_GATING_TRACK_MODE = 2
7196 12:29:32.377620 SELPH_MODE = 1
7197 12:29:32.380590 PICG_EARLY_EN = 1
7198 12:29:32.384194 VALID_LAT_VALUE = 1
7199 12:29:32.387302 ==============================================================
7200 12:29:32.390877 Enter into Gating configuration >>>>
7201 12:29:32.393838 Exit from Gating configuration <<<<
7202 12:29:32.397474 Enter into DVFS_PRE_config >>>>>
7203 12:29:32.410523 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7204 12:29:32.413666 Exit from DVFS_PRE_config <<<<<
7205 12:29:32.413774 Enter into PICG configuration >>>>
7206 12:29:32.417235 Exit from PICG configuration <<<<
7207 12:29:32.420233 [RX_INPUT] configuration >>>>>
7208 12:29:32.423519 [RX_INPUT] configuration <<<<<
7209 12:29:32.430117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7210 12:29:32.433523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7211 12:29:32.440068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 12:29:32.446730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 12:29:32.453571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 12:29:32.460159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 12:29:32.463267 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7216 12:29:32.466777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7217 12:29:32.469688 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7218 12:29:32.476550 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7219 12:29:32.479642 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7220 12:29:32.483083 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 12:29:32.486141 ===================================
7222 12:29:32.489636 LPDDR4 DRAM CONFIGURATION
7223 12:29:32.493236 ===================================
7224 12:29:32.496200 EX_ROW_EN[0] = 0x0
7225 12:29:32.496279 EX_ROW_EN[1] = 0x0
7226 12:29:32.499499 LP4Y_EN = 0x0
7227 12:29:32.499573 WORK_FSP = 0x1
7228 12:29:32.503096 WL = 0x5
7229 12:29:32.503200 RL = 0x5
7230 12:29:32.506167 BL = 0x2
7231 12:29:32.506255 RPST = 0x0
7232 12:29:32.509443 RD_PRE = 0x0
7233 12:29:32.509530 WR_PRE = 0x1
7234 12:29:32.513055 WR_PST = 0x1
7235 12:29:32.513142 DBI_WR = 0x0
7236 12:29:32.516524 DBI_RD = 0x0
7237 12:29:32.516611 OTF = 0x1
7238 12:29:32.519698 ===================================
7239 12:29:32.525917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7240 12:29:32.529449 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7241 12:29:32.532906 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 12:29:32.535996 ===================================
7243 12:29:32.539466 LPDDR4 DRAM CONFIGURATION
7244 12:29:32.542995 ===================================
7245 12:29:32.546082 EX_ROW_EN[0] = 0x10
7246 12:29:32.546197 EX_ROW_EN[1] = 0x0
7247 12:29:32.549271 LP4Y_EN = 0x0
7248 12:29:32.549366 WORK_FSP = 0x1
7249 12:29:32.552692 WL = 0x5
7250 12:29:32.552822 RL = 0x5
7251 12:29:32.555819 BL = 0x2
7252 12:29:32.555926 RPST = 0x0
7253 12:29:32.559266 RD_PRE = 0x0
7254 12:29:32.559387 WR_PRE = 0x1
7255 12:29:32.562369 WR_PST = 0x1
7256 12:29:32.562475 DBI_WR = 0x0
7257 12:29:32.565504 DBI_RD = 0x0
7258 12:29:32.565604 OTF = 0x1
7259 12:29:32.568937 ===================================
7260 12:29:32.575823 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7261 12:29:32.575904 ==
7262 12:29:32.579083 Dram Type= 6, Freq= 0, CH_0, rank 0
7263 12:29:32.585550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7264 12:29:32.585664 ==
7265 12:29:32.585783 [Duty_Offset_Calibration]
7266 12:29:32.589143 B0:2 B1:0 CA:1
7267 12:29:32.589254
7268 12:29:32.592309 [DutyScan_Calibration_Flow] k_type=0
7269 12:29:32.600568
7270 12:29:32.600680 ==CLK 0==
7271 12:29:32.604162 Final CLK duty delay cell = -4
7272 12:29:32.607270 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7273 12:29:32.610636 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7274 12:29:32.614165 [-4] AVG Duty = 4906%(X100)
7275 12:29:32.614275
7276 12:29:32.617146 CH0 CLK Duty spec in!! Max-Min= 187%
7277 12:29:32.620646 [DutyScan_Calibration_Flow] ====Done====
7278 12:29:32.620772
7279 12:29:32.623752 [DutyScan_Calibration_Flow] k_type=1
7280 12:29:32.640465
7281 12:29:32.640584 ==DQS 0 ==
7282 12:29:32.643653 Final DQS duty delay cell = 0
7283 12:29:32.646724 [0] MAX Duty = 5249%(X100), DQS PI = 32
7284 12:29:32.650358 [0] MIN Duty = 4938%(X100), DQS PI = 0
7285 12:29:32.653453 [0] AVG Duty = 5093%(X100)
7286 12:29:32.653564
7287 12:29:32.653666 ==DQS 1 ==
7288 12:29:32.657093 Final DQS duty delay cell = -4
7289 12:29:32.660056 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7290 12:29:32.663563 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7291 12:29:32.666588 [-4] AVG Duty = 5000%(X100)
7292 12:29:32.666664
7293 12:29:32.670153 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7294 12:29:32.670228
7295 12:29:32.673319 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7296 12:29:32.676456 [DutyScan_Calibration_Flow] ====Done====
7297 12:29:32.676557
7298 12:29:32.680429 [DutyScan_Calibration_Flow] k_type=3
7299 12:29:32.697887
7300 12:29:32.697973 ==DQM 0 ==
7301 12:29:32.700778 Final DQM duty delay cell = 0
7302 12:29:32.704302 [0] MAX Duty = 5093%(X100), DQS PI = 26
7303 12:29:32.707760 [0] MIN Duty = 4813%(X100), DQS PI = 50
7304 12:29:32.710739 [0] AVG Duty = 4953%(X100)
7305 12:29:32.710825
7306 12:29:32.710892 ==DQM 1 ==
7307 12:29:32.714295 Final DQM duty delay cell = 0
7308 12:29:32.717716 [0] MAX Duty = 5249%(X100), DQS PI = 46
7309 12:29:32.720577 [0] MIN Duty = 5031%(X100), DQS PI = 18
7310 12:29:32.724098 [0] AVG Duty = 5140%(X100)
7311 12:29:32.724184
7312 12:29:32.727674 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7313 12:29:32.727760
7314 12:29:32.730562 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7315 12:29:32.734327 [DutyScan_Calibration_Flow] ====Done====
7316 12:29:32.734441
7317 12:29:32.737336 [DutyScan_Calibration_Flow] k_type=2
7318 12:29:32.754920
7319 12:29:32.755041 ==DQ 0 ==
7320 12:29:32.758501 Final DQ duty delay cell = 0
7321 12:29:32.761497 [0] MAX Duty = 5124%(X100), DQS PI = 34
7322 12:29:32.764920 [0] MIN Duty = 5000%(X100), DQS PI = 0
7323 12:29:32.765014 [0] AVG Duty = 5062%(X100)
7324 12:29:32.765083
7325 12:29:32.768345 ==DQ 1 ==
7326 12:29:32.771312 Final DQ duty delay cell = 0
7327 12:29:32.774762 [0] MAX Duty = 4969%(X100), DQS PI = 44
7328 12:29:32.778289 [0] MIN Duty = 4875%(X100), DQS PI = 10
7329 12:29:32.778370 [0] AVG Duty = 4922%(X100)
7330 12:29:32.778436
7331 12:29:32.781261 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7332 12:29:32.784855
7333 12:29:32.788214 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7334 12:29:32.791324 [DutyScan_Calibration_Flow] ====Done====
7335 12:29:32.791411 ==
7336 12:29:32.794671 Dram Type= 6, Freq= 0, CH_1, rank 0
7337 12:29:32.797972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7338 12:29:32.798060 ==
7339 12:29:32.801484 [Duty_Offset_Calibration]
7340 12:29:32.801588 B0:0 B1:-1 CA:2
7341 12:29:32.801682
7342 12:29:32.804523 [DutyScan_Calibration_Flow] k_type=0
7343 12:29:32.815328
7344 12:29:32.815411 ==CLK 0==
7345 12:29:32.818356 Final CLK duty delay cell = 0
7346 12:29:32.821579 [0] MAX Duty = 5156%(X100), DQS PI = 10
7347 12:29:32.825054 [0] MIN Duty = 4906%(X100), DQS PI = 46
7348 12:29:32.828098 [0] AVG Duty = 5031%(X100)
7349 12:29:32.828207
7350 12:29:32.831710 CH1 CLK Duty spec in!! Max-Min= 250%
7351 12:29:32.834617 [DutyScan_Calibration_Flow] ====Done====
7352 12:29:32.834726
7353 12:29:32.838253 [DutyScan_Calibration_Flow] k_type=1
7354 12:29:32.854748
7355 12:29:32.854833 ==DQS 0 ==
7356 12:29:32.858278 Final DQS duty delay cell = 0
7357 12:29:32.861302 [0] MAX Duty = 5124%(X100), DQS PI = 26
7358 12:29:32.864742 [0] MIN Duty = 4969%(X100), DQS PI = 2
7359 12:29:32.867874 [0] AVG Duty = 5046%(X100)
7360 12:29:32.867956
7361 12:29:32.868021 ==DQS 1 ==
7362 12:29:32.871198 Final DQS duty delay cell = 0
7363 12:29:32.874738 [0] MAX Duty = 5187%(X100), DQS PI = 60
7364 12:29:32.877781 [0] MIN Duty = 4844%(X100), DQS PI = 32
7365 12:29:32.881378 [0] AVG Duty = 5015%(X100)
7366 12:29:32.881462
7367 12:29:32.884867 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7368 12:29:32.884951
7369 12:29:32.887804 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7370 12:29:32.891275 [DutyScan_Calibration_Flow] ====Done====
7371 12:29:32.891358
7372 12:29:32.894176 [DutyScan_Calibration_Flow] k_type=3
7373 12:29:32.912506
7374 12:29:32.912618 ==DQM 0 ==
7375 12:29:32.915993 Final DQM duty delay cell = 4
7376 12:29:32.918972 [4] MAX Duty = 5125%(X100), DQS PI = 22
7377 12:29:32.922332 [4] MIN Duty = 4969%(X100), DQS PI = 46
7378 12:29:32.925767 [4] AVG Duty = 5047%(X100)
7379 12:29:32.925856
7380 12:29:32.925923 ==DQM 1 ==
7381 12:29:32.929213 Final DQM duty delay cell = 0
7382 12:29:32.932150 [0] MAX Duty = 5281%(X100), DQS PI = 58
7383 12:29:32.935642 [0] MIN Duty = 4876%(X100), DQS PI = 34
7384 12:29:32.939093 [0] AVG Duty = 5078%(X100)
7385 12:29:32.939193
7386 12:29:32.941997 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7387 12:29:32.942074
7388 12:29:32.945372 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7389 12:29:32.948752 [DutyScan_Calibration_Flow] ====Done====
7390 12:29:32.948891
7391 12:29:32.951842 [DutyScan_Calibration_Flow] k_type=2
7392 12:29:32.969469
7393 12:29:32.969554 ==DQ 0 ==
7394 12:29:32.972531 Final DQ duty delay cell = 0
7395 12:29:32.975836 [0] MAX Duty = 5093%(X100), DQS PI = 20
7396 12:29:32.979367 [0] MIN Duty = 4969%(X100), DQS PI = 48
7397 12:29:32.979455 [0] AVG Duty = 5031%(X100)
7398 12:29:32.983012
7399 12:29:32.983115 ==DQ 1 ==
7400 12:29:32.986048 Final DQ duty delay cell = 0
7401 12:29:32.989521 [0] MAX Duty = 5062%(X100), DQS PI = 2
7402 12:29:32.992452 [0] MIN Duty = 4813%(X100), DQS PI = 34
7403 12:29:32.992523 [0] AVG Duty = 4937%(X100)
7404 12:29:32.992586
7405 12:29:32.995972 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7406 12:29:32.999464
7407 12:29:33.002743 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7408 12:29:33.006109 [DutyScan_Calibration_Flow] ====Done====
7409 12:29:33.008933 nWR fixed to 30
7410 12:29:33.009037 [ModeRegInit_LP4] CH0 RK0
7411 12:29:33.012222 [ModeRegInit_LP4] CH0 RK1
7412 12:29:33.015660 [ModeRegInit_LP4] CH1 RK0
7413 12:29:33.019138 [ModeRegInit_LP4] CH1 RK1
7414 12:29:33.019249 match AC timing 5
7415 12:29:33.025768 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7416 12:29:33.029158 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7417 12:29:33.032046 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7418 12:29:33.038882 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7419 12:29:33.042343 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7420 12:29:33.042428 [MiockJmeterHQA]
7421 12:29:33.042494
7422 12:29:33.045674 [DramcMiockJmeter] u1RxGatingPI = 0
7423 12:29:33.048878 0 : 4259, 4029
7424 12:29:33.048992 4 : 4363, 4138
7425 12:29:33.052209 8 : 4253, 4026
7426 12:29:33.052319 12 : 4255, 4030
7427 12:29:33.052420 16 : 4252, 4027
7428 12:29:33.055323 20 : 4252, 4027
7429 12:29:33.055430 24 : 4363, 4137
7430 12:29:33.058645 28 : 4252, 4027
7431 12:29:33.058761 32 : 4360, 4137
7432 12:29:33.062021 36 : 4252, 4027
7433 12:29:33.062135 40 : 4250, 4027
7434 12:29:33.065375 44 : 4250, 4026
7435 12:29:33.065489 48 : 4252, 4030
7436 12:29:33.065574 52 : 4250, 4027
7437 12:29:33.068833 56 : 4250, 4027
7438 12:29:33.068948 60 : 4363, 4140
7439 12:29:33.071741 64 : 4250, 4026
7440 12:29:33.071844 68 : 4252, 4030
7441 12:29:33.075299 72 : 4250, 4027
7442 12:29:33.075413 76 : 4361, 4137
7443 12:29:33.078269 80 : 4250, 4027
7444 12:29:33.078356 84 : 4361, 4137
7445 12:29:33.078424 88 : 4250, 3563
7446 12:29:33.081798 92 : 4250, 0
7447 12:29:33.081962 96 : 4252, 0
7448 12:29:33.084838 100 : 4250, 0
7449 12:29:33.084994 104 : 4250, 0
7450 12:29:33.085182 108 : 4250, 0
7451 12:29:33.088452 112 : 4253, 0
7452 12:29:33.088538 116 : 4363, 0
7453 12:29:33.091919 120 : 4250, 0
7454 12:29:33.092005 124 : 4250, 0
7455 12:29:33.092073 128 : 4250, 0
7456 12:29:33.094973 132 : 4361, 0
7457 12:29:33.095059 136 : 4360, 0
7458 12:29:33.095128 140 : 4250, 0
7459 12:29:33.098452 144 : 4360, 0
7460 12:29:33.098541 148 : 4250, 0
7461 12:29:33.101534 152 : 4249, 0
7462 12:29:33.101648 156 : 4250, 0
7463 12:29:33.101747 160 : 4250, 0
7464 12:29:33.104959 164 : 4252, 0
7465 12:29:33.105073 168 : 4361, 0
7466 12:29:33.107962 172 : 4250, 0
7467 12:29:33.108076 176 : 4250, 0
7468 12:29:33.108179 180 : 4250, 0
7469 12:29:33.111523 184 : 4361, 0
7470 12:29:33.111660 188 : 4361, 0
7471 12:29:33.114747 192 : 4250, 0
7472 12:29:33.114853 196 : 4250, 0
7473 12:29:33.114953 200 : 4250, 5
7474 12:29:33.118062 204 : 4252, 2335
7475 12:29:33.118134 208 : 4364, 4140
7476 12:29:33.121419 212 : 4253, 4029
7477 12:29:33.121497 216 : 4250, 4026
7478 12:29:33.124454 220 : 4250, 4027
7479 12:29:33.124559 224 : 4252, 4029
7480 12:29:33.127990 228 : 4250, 4026
7481 12:29:33.128091 232 : 4250, 4026
7482 12:29:33.131483 236 : 4250, 4027
7483 12:29:33.131584 240 : 4252, 4029
7484 12:29:33.134436 244 : 4250, 4026
7485 12:29:33.134534 248 : 4361, 4137
7486 12:29:33.137960 252 : 4361, 4137
7487 12:29:33.138061 256 : 4247, 4024
7488 12:29:33.138153 260 : 4364, 4140
7489 12:29:33.140947 264 : 4361, 4137
7490 12:29:33.141019 268 : 4250, 4026
7491 12:29:33.144509 272 : 4250, 4027
7492 12:29:33.144610 276 : 4252, 4030
7493 12:29:33.147434 280 : 4250, 4026
7494 12:29:33.147542 284 : 4250, 4026
7495 12:29:33.150829 288 : 4250, 4027
7496 12:29:33.150938 292 : 4252, 4030
7497 12:29:33.154200 296 : 4250, 4027
7498 12:29:33.154391 300 : 4361, 4137
7499 12:29:33.157542 304 : 4361, 4137
7500 12:29:33.157656 308 : 4250, 4027
7501 12:29:33.161008 312 : 4363, 4001
7502 12:29:33.161089 316 : 4361, 2148
7503 12:29:33.161195
7504 12:29:33.164308 MIOCK jitter meter ch=0
7505 12:29:33.164393
7506 12:29:33.167707 1T = (316-92) = 224 dly cells
7507 12:29:33.170694 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7508 12:29:33.170783 ==
7509 12:29:33.174381 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 12:29:33.180909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 12:29:33.180995 ==
7512 12:29:33.184182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 12:29:33.190691 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 12:29:33.193793 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 12:29:33.200382 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 12:29:33.208099 [CA 0] Center 43 (13~73) winsize 61
7517 12:29:33.211886 [CA 1] Center 43 (13~73) winsize 61
7518 12:29:33.214878 [CA 2] Center 38 (8~68) winsize 61
7519 12:29:33.218399 [CA 3] Center 37 (8~67) winsize 60
7520 12:29:33.221739 [CA 4] Center 36 (6~66) winsize 61
7521 12:29:33.224647 [CA 5] Center 35 (6~65) winsize 60
7522 12:29:33.224730
7523 12:29:33.227994 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 12:29:33.228083
7525 12:29:33.231562 [CATrainingPosCal] consider 1 rank data
7526 12:29:33.234638 u2DelayCellTimex100 = 290/100 ps
7527 12:29:33.241172 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7528 12:29:33.244551 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7529 12:29:33.247659 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7530 12:29:33.251184 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7531 12:29:33.254413 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7532 12:29:33.257833 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7533 12:29:33.257915
7534 12:29:33.261358 CA PerBit enable=1, Macro0, CA PI delay=35
7535 12:29:33.261441
7536 12:29:33.264295 [CBTSetCACLKResult] CA Dly = 35
7537 12:29:33.267650 CS Dly: 9 (0~40)
7538 12:29:33.271047 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 12:29:33.274470 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 12:29:33.274550 ==
7541 12:29:33.277498 Dram Type= 6, Freq= 0, CH_0, rank 1
7542 12:29:33.284442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 12:29:33.284525 ==
7544 12:29:33.287716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 12:29:33.291109 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 12:29:33.297511 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 12:29:33.304177 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 12:29:33.311635 [CA 0] Center 43 (13~74) winsize 62
7549 12:29:33.315061 [CA 1] Center 43 (13~73) winsize 61
7550 12:29:33.318139 [CA 2] Center 38 (9~68) winsize 60
7551 12:29:33.321502 [CA 3] Center 38 (9~68) winsize 60
7552 12:29:33.324999 [CA 4] Center 37 (7~67) winsize 61
7553 12:29:33.328276 [CA 5] Center 36 (6~66) winsize 61
7554 12:29:33.328380
7555 12:29:33.331559 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7556 12:29:33.331637
7557 12:29:33.335039 [CATrainingPosCal] consider 2 rank data
7558 12:29:33.337951 u2DelayCellTimex100 = 290/100 ps
7559 12:29:33.341200 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7560 12:29:33.348191 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7561 12:29:33.351149 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7562 12:29:33.354614 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7563 12:29:33.357908 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7564 12:29:33.361170 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7565 12:29:33.361249
7566 12:29:33.364611 CA PerBit enable=1, Macro0, CA PI delay=35
7567 12:29:33.364690
7568 12:29:33.367516 [CBTSetCACLKResult] CA Dly = 35
7569 12:29:33.370840 CS Dly: 11 (0~44)
7570 12:29:33.374551 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 12:29:33.377648 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 12:29:33.377733
7573 12:29:33.381243 ----->DramcWriteLeveling(PI) begin...
7574 12:29:33.381318 ==
7575 12:29:33.384195 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 12:29:33.391125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 12:29:33.391209 ==
7578 12:29:33.394466 Write leveling (Byte 0): 35 => 35
7579 12:29:33.397501 Write leveling (Byte 1): 30 => 30
7580 12:29:33.397585 DramcWriteLeveling(PI) end<-----
7581 12:29:33.400906
7582 12:29:33.400989 ==
7583 12:29:33.403910 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 12:29:33.407351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 12:29:33.407435 ==
7586 12:29:33.410920 [Gating] SW mode calibration
7587 12:29:33.417429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7588 12:29:33.423816 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7589 12:29:33.427285 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 12:29:33.430386 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 12:29:33.436926 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7592 12:29:33.439892 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7593 12:29:33.443346 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7594 12:29:33.450187 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7595 12:29:33.453562 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 12:29:33.456507 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 12:29:33.463366 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 12:29:33.466728 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 12:29:33.469720 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
7600 12:29:33.476454 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7601 12:29:33.479720 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7602 12:29:33.483252 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7603 12:29:33.489730 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:29:33.493197 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 12:29:33.496167 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 12:29:33.502892 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 12:29:33.505964 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7608 12:29:33.509542 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7609 12:29:33.516224 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7610 12:29:33.519237 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:29:33.522612 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:29:33.529183 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 12:29:33.532068 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 12:29:33.535513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 12:29:33.542410 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 12:29:33.545390 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 12:29:33.548881 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 12:29:33.555758 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 12:29:33.558677 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:29:33.562237 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:29:33.568865 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:29:33.572239 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:29:33.575220 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:29:33.581878 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:29:33.585419 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:29:33.588503 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:29:33.595079 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:29:33.598502 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:29:33.601851 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:29:33.608381 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 12:29:33.611487 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 12:29:33.614953 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 12:29:33.621541 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7634 12:29:33.621627 Total UI for P1: 0, mck2ui 16
7635 12:29:33.624572 best dqsien dly found for B0: ( 1, 9, 10)
7636 12:29:33.631428 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 12:29:33.634456 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 12:29:33.637940 Total UI for P1: 0, mck2ui 16
7639 12:29:33.641560 best dqsien dly found for B1: ( 1, 9, 20)
7640 12:29:33.644641 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7641 12:29:33.647890 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7642 12:29:33.647975
7643 12:29:33.651189 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7644 12:29:33.657953 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7645 12:29:33.658037 [Gating] SW calibration Done
7646 12:29:33.660997 ==
7647 12:29:33.664530 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 12:29:33.667848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 12:29:33.667933 ==
7650 12:29:33.667999 RX Vref Scan: 0
7651 12:29:33.668061
7652 12:29:33.671643 RX Vref 0 -> 0, step: 1
7653 12:29:33.671756
7654 12:29:33.674531 RX Delay 0 -> 252, step: 8
7655 12:29:33.677380 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7656 12:29:33.680951 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7657 12:29:33.684274 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7658 12:29:33.690796 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7659 12:29:33.693846 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7660 12:29:33.697384 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7661 12:29:33.700927 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7662 12:29:33.703824 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7663 12:29:33.710697 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7664 12:29:33.714147 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7665 12:29:33.717128 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7666 12:29:33.720494 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7667 12:29:33.723946 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7668 12:29:33.730365 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7669 12:29:33.733880 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7670 12:29:33.736874 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7671 12:29:33.736961 ==
7672 12:29:33.740417 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 12:29:33.743505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 12:29:33.743592 ==
7675 12:29:33.747110 DQS Delay:
7676 12:29:33.747197 DQS0 = 0, DQS1 = 0
7677 12:29:33.750412 DQM Delay:
7678 12:29:33.750511 DQM0 = 137, DQM1 = 127
7679 12:29:33.753570 DQ Delay:
7680 12:29:33.756945 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7681 12:29:33.760259 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7682 12:29:33.763154 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7683 12:29:33.766521 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7684 12:29:33.766612
7685 12:29:33.766716
7686 12:29:33.766816 ==
7687 12:29:33.770142 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 12:29:33.773368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 12:29:33.773447 ==
7690 12:29:33.776306
7691 12:29:33.776396
7692 12:29:33.776495 TX Vref Scan disable
7693 12:29:33.779791 == TX Byte 0 ==
7694 12:29:33.783286 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7695 12:29:33.786189 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7696 12:29:33.789707 == TX Byte 1 ==
7697 12:29:33.793052 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7698 12:29:33.796067 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7699 12:29:33.799579 ==
7700 12:29:33.799655 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 12:29:33.806114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 12:29:33.806192 ==
7703 12:29:33.818454
7704 12:29:33.821404 TX Vref early break, caculate TX vref
7705 12:29:33.824875 TX Vref=16, minBit 12, minWin=22, winSum=373
7706 12:29:33.828400 TX Vref=18, minBit 5, minWin=23, winSum=385
7707 12:29:33.831461 TX Vref=20, minBit 5, minWin=24, winSum=396
7708 12:29:33.834897 TX Vref=22, minBit 1, minWin=25, winSum=407
7709 12:29:33.837857 TX Vref=24, minBit 1, minWin=25, winSum=419
7710 12:29:33.844416 TX Vref=26, minBit 5, minWin=25, winSum=420
7711 12:29:33.847932 TX Vref=28, minBit 12, minWin=25, winSum=428
7712 12:29:33.851405 TX Vref=30, minBit 0, minWin=25, winSum=424
7713 12:29:33.854234 TX Vref=32, minBit 1, minWin=25, winSum=413
7714 12:29:33.857529 TX Vref=34, minBit 0, minWin=25, winSum=403
7715 12:29:33.864184 [TxChooseVref] Worse bit 12, Min win 25, Win sum 428, Final Vref 28
7716 12:29:33.864275
7717 12:29:33.867389 Final TX Range 0 Vref 28
7718 12:29:33.867494
7719 12:29:33.867580 ==
7720 12:29:33.870694 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 12:29:33.874304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 12:29:33.874390 ==
7723 12:29:33.877557
7724 12:29:33.877643
7725 12:29:33.877728 TX Vref Scan disable
7726 12:29:33.884008 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7727 12:29:33.884096 == TX Byte 0 ==
7728 12:29:33.887569 u2DelayCellOfst[0]=13 cells (4 PI)
7729 12:29:33.890882 u2DelayCellOfst[1]=16 cells (5 PI)
7730 12:29:33.894233 u2DelayCellOfst[2]=13 cells (4 PI)
7731 12:29:33.897502 u2DelayCellOfst[3]=13 cells (4 PI)
7732 12:29:33.900727 u2DelayCellOfst[4]=6 cells (2 PI)
7733 12:29:33.904313 u2DelayCellOfst[5]=0 cells (0 PI)
7734 12:29:33.907351 u2DelayCellOfst[6]=16 cells (5 PI)
7735 12:29:33.910774 u2DelayCellOfst[7]=16 cells (5 PI)
7736 12:29:33.914170 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7737 12:29:33.917189 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7738 12:29:33.920622 == TX Byte 1 ==
7739 12:29:33.923686 u2DelayCellOfst[8]=3 cells (1 PI)
7740 12:29:33.927181 u2DelayCellOfst[9]=0 cells (0 PI)
7741 12:29:33.930326 u2DelayCellOfst[10]=6 cells (2 PI)
7742 12:29:33.933908 u2DelayCellOfst[11]=3 cells (1 PI)
7743 12:29:33.933994 u2DelayCellOfst[12]=13 cells (4 PI)
7744 12:29:33.936894 u2DelayCellOfst[13]=13 cells (4 PI)
7745 12:29:33.940369 u2DelayCellOfst[14]=13 cells (4 PI)
7746 12:29:33.943854 u2DelayCellOfst[15]=10 cells (3 PI)
7747 12:29:33.950497 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7748 12:29:33.953574 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7749 12:29:33.953661 DramC Write-DBI on
7750 12:29:33.957048 ==
7751 12:29:33.960169 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 12:29:33.963387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 12:29:33.963474 ==
7754 12:29:33.963588
7755 12:29:33.963667
7756 12:29:33.966556 TX Vref Scan disable
7757 12:29:33.966645 == TX Byte 0 ==
7758 12:29:33.973044 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7759 12:29:33.973131 == TX Byte 1 ==
7760 12:29:33.976499 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7761 12:29:33.979888 DramC Write-DBI off
7762 12:29:33.979975
7763 12:29:33.980059 [DATLAT]
7764 12:29:33.983213 Freq=1600, CH0 RK0
7765 12:29:33.983300
7766 12:29:33.983384 DATLAT Default: 0xf
7767 12:29:33.986598 0, 0xFFFF, sum = 0
7768 12:29:33.986687 1, 0xFFFF, sum = 0
7769 12:29:33.989928 2, 0xFFFF, sum = 0
7770 12:29:33.990015 3, 0xFFFF, sum = 0
7771 12:29:33.992966 4, 0xFFFF, sum = 0
7772 12:29:33.993054 5, 0xFFFF, sum = 0
7773 12:29:33.996338 6, 0xFFFF, sum = 0
7774 12:29:33.999596 7, 0xFFFF, sum = 0
7775 12:29:33.999700 8, 0xFFFF, sum = 0
7776 12:29:34.003269 9, 0xFFFF, sum = 0
7777 12:29:34.003357 10, 0xFFFF, sum = 0
7778 12:29:34.006262 11, 0xFFFF, sum = 0
7779 12:29:34.006350 12, 0xFFFF, sum = 0
7780 12:29:34.009692 13, 0xFFFF, sum = 0
7781 12:29:34.009779 14, 0x0, sum = 1
7782 12:29:34.012641 15, 0x0, sum = 2
7783 12:29:34.012754 16, 0x0, sum = 3
7784 12:29:34.016276 17, 0x0, sum = 4
7785 12:29:34.016364 best_step = 15
7786 12:29:34.016448
7787 12:29:34.016529 ==
7788 12:29:34.019545 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 12:29:34.023051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 12:29:34.026126 ==
7791 12:29:34.026212 RX Vref Scan: 1
7792 12:29:34.026297
7793 12:29:34.029663 Set Vref Range= 24 -> 127
7794 12:29:34.029750
7795 12:29:34.032701 RX Vref 24 -> 127, step: 1
7796 12:29:34.032809
7797 12:29:34.032895 RX Delay 19 -> 252, step: 4
7798 12:29:34.032975
7799 12:29:34.036149 Set Vref, RX VrefLevel [Byte0]: 24
7800 12:29:34.039212 [Byte1]: 24
7801 12:29:34.043041
7802 12:29:34.043127 Set Vref, RX VrefLevel [Byte0]: 25
7803 12:29:34.046531 [Byte1]: 25
7804 12:29:34.050447
7805 12:29:34.050534 Set Vref, RX VrefLevel [Byte0]: 26
7806 12:29:34.053980 [Byte1]: 26
7807 12:29:34.058535
7808 12:29:34.058621 Set Vref, RX VrefLevel [Byte0]: 27
7809 12:29:34.064497 [Byte1]: 27
7810 12:29:34.064583
7811 12:29:34.067862 Set Vref, RX VrefLevel [Byte0]: 28
7812 12:29:34.071071 [Byte1]: 28
7813 12:29:34.071158
7814 12:29:34.074388 Set Vref, RX VrefLevel [Byte0]: 29
7815 12:29:34.077707 [Byte1]: 29
7816 12:29:34.077794
7817 12:29:34.081521 Set Vref, RX VrefLevel [Byte0]: 30
7818 12:29:34.084515 [Byte1]: 30
7819 12:29:34.088726
7820 12:29:34.088860 Set Vref, RX VrefLevel [Byte0]: 31
7821 12:29:34.091699 [Byte1]: 31
7822 12:29:34.096150
7823 12:29:34.096237 Set Vref, RX VrefLevel [Byte0]: 32
7824 12:29:34.099647 [Byte1]: 32
7825 12:29:34.103507
7826 12:29:34.103594 Set Vref, RX VrefLevel [Byte0]: 33
7827 12:29:34.106882 [Byte1]: 33
7828 12:29:34.111228
7829 12:29:34.111339 Set Vref, RX VrefLevel [Byte0]: 34
7830 12:29:34.114769 [Byte1]: 34
7831 12:29:34.118777
7832 12:29:34.118868 Set Vref, RX VrefLevel [Byte0]: 35
7833 12:29:34.122135 [Byte1]: 35
7834 12:29:34.126527
7835 12:29:34.126638 Set Vref, RX VrefLevel [Byte0]: 36
7836 12:29:34.129510 [Byte1]: 36
7837 12:29:34.134073
7838 12:29:34.134172 Set Vref, RX VrefLevel [Byte0]: 37
7839 12:29:34.137174 [Byte1]: 37
7840 12:29:34.141713
7841 12:29:34.141828 Set Vref, RX VrefLevel [Byte0]: 38
7842 12:29:34.144671 [Byte1]: 38
7843 12:29:34.149002
7844 12:29:34.149109 Set Vref, RX VrefLevel [Byte0]: 39
7845 12:29:34.152477 [Byte1]: 39
7846 12:29:34.156836
7847 12:29:34.156923 Set Vref, RX VrefLevel [Byte0]: 40
7848 12:29:34.159743 [Byte1]: 40
7849 12:29:34.164317
7850 12:29:34.164419 Set Vref, RX VrefLevel [Byte0]: 41
7851 12:29:34.167733 [Byte1]: 41
7852 12:29:34.171838
7853 12:29:34.171947 Set Vref, RX VrefLevel [Byte0]: 42
7854 12:29:34.174950 [Byte1]: 42
7855 12:29:34.179221
7856 12:29:34.179326 Set Vref, RX VrefLevel [Byte0]: 43
7857 12:29:34.182556 [Byte1]: 43
7858 12:29:34.186798
7859 12:29:34.186908 Set Vref, RX VrefLevel [Byte0]: 44
7860 12:29:34.190137 [Byte1]: 44
7861 12:29:34.194419
7862 12:29:34.194497 Set Vref, RX VrefLevel [Byte0]: 45
7863 12:29:34.198082 [Byte1]: 45
7864 12:29:34.201888
7865 12:29:34.202023 Set Vref, RX VrefLevel [Byte0]: 46
7866 12:29:34.205187 [Byte1]: 46
7867 12:29:34.209687
7868 12:29:34.209790 Set Vref, RX VrefLevel [Byte0]: 47
7869 12:29:34.213138 [Byte1]: 47
7870 12:29:34.217242
7871 12:29:34.217335 Set Vref, RX VrefLevel [Byte0]: 48
7872 12:29:34.220257 [Byte1]: 48
7873 12:29:34.224681
7874 12:29:34.224801 Set Vref, RX VrefLevel [Byte0]: 49
7875 12:29:34.228036 [Byte1]: 49
7876 12:29:34.232573
7877 12:29:34.232676 Set Vref, RX VrefLevel [Byte0]: 50
7878 12:29:34.235547 [Byte1]: 50
7879 12:29:34.240151
7880 12:29:34.240225 Set Vref, RX VrefLevel [Byte0]: 51
7881 12:29:34.243246 [Byte1]: 51
7882 12:29:34.247744
7883 12:29:34.247838 Set Vref, RX VrefLevel [Byte0]: 52
7884 12:29:34.250517 [Byte1]: 52
7885 12:29:34.254936
7886 12:29:34.255038 Set Vref, RX VrefLevel [Byte0]: 53
7887 12:29:34.258389 [Byte1]: 53
7888 12:29:34.262404
7889 12:29:34.262508 Set Vref, RX VrefLevel [Byte0]: 54
7890 12:29:34.265899 [Byte1]: 54
7891 12:29:34.270408
7892 12:29:34.270514 Set Vref, RX VrefLevel [Byte0]: 55
7893 12:29:34.273488 [Byte1]: 55
7894 12:29:34.277998
7895 12:29:34.278078 Set Vref, RX VrefLevel [Byte0]: 56
7896 12:29:34.280872 [Byte1]: 56
7897 12:29:34.285462
7898 12:29:34.285568 Set Vref, RX VrefLevel [Byte0]: 57
7899 12:29:34.288742 [Byte1]: 57
7900 12:29:34.292693
7901 12:29:34.292837 Set Vref, RX VrefLevel [Byte0]: 58
7902 12:29:34.296469 [Byte1]: 58
7903 12:29:34.300363
7904 12:29:34.300468 Set Vref, RX VrefLevel [Byte0]: 59
7905 12:29:34.303586 [Byte1]: 59
7906 12:29:34.308231
7907 12:29:34.308335 Set Vref, RX VrefLevel [Byte0]: 60
7908 12:29:34.311149 [Byte1]: 60
7909 12:29:34.315423
7910 12:29:34.315527 Set Vref, RX VrefLevel [Byte0]: 61
7911 12:29:34.318933 [Byte1]: 61
7912 12:29:34.323416
7913 12:29:34.323581 Set Vref, RX VrefLevel [Byte0]: 62
7914 12:29:34.326531 [Byte1]: 62
7915 12:29:34.330889
7916 12:29:34.330994 Set Vref, RX VrefLevel [Byte0]: 63
7917 12:29:34.334040 [Byte1]: 63
7918 12:29:34.338518
7919 12:29:34.338594 Set Vref, RX VrefLevel [Byte0]: 64
7920 12:29:34.341556 [Byte1]: 64
7921 12:29:34.346150
7922 12:29:34.346252 Set Vref, RX VrefLevel [Byte0]: 65
7923 12:29:34.349102 [Byte1]: 65
7924 12:29:34.353523
7925 12:29:34.353637 Set Vref, RX VrefLevel [Byte0]: 66
7926 12:29:34.356839 [Byte1]: 66
7927 12:29:34.361418
7928 12:29:34.361521 Set Vref, RX VrefLevel [Byte0]: 67
7929 12:29:34.364396 [Byte1]: 67
7930 12:29:34.368894
7931 12:29:34.368974 Set Vref, RX VrefLevel [Byte0]: 68
7932 12:29:34.372036 [Byte1]: 68
7933 12:29:34.376475
7934 12:29:34.376597 Set Vref, RX VrefLevel [Byte0]: 69
7935 12:29:34.379532 [Byte1]: 69
7936 12:29:34.383509
7937 12:29:34.383613 Set Vref, RX VrefLevel [Byte0]: 70
7938 12:29:34.386942 [Byte1]: 70
7939 12:29:34.391244
7940 12:29:34.394577 Set Vref, RX VrefLevel [Byte0]: 71
7941 12:29:34.397876 [Byte1]: 71
7942 12:29:34.397977
7943 12:29:34.401048 Set Vref, RX VrefLevel [Byte0]: 72
7944 12:29:34.404603 [Byte1]: 72
7945 12:29:34.404709
7946 12:29:34.407806 Set Vref, RX VrefLevel [Byte0]: 73
7947 12:29:34.411195 [Byte1]: 73
7948 12:29:34.411276
7949 12:29:34.414437 Set Vref, RX VrefLevel [Byte0]: 74
7950 12:29:34.417595 [Byte1]: 74
7951 12:29:34.421903
7952 12:29:34.422015 Set Vref, RX VrefLevel [Byte0]: 75
7953 12:29:34.424806 [Byte1]: 75
7954 12:29:34.429556
7955 12:29:34.429666 Set Vref, RX VrefLevel [Byte0]: 76
7956 12:29:34.432484 [Byte1]: 76
7957 12:29:34.436856
7958 12:29:34.436939 Set Vref, RX VrefLevel [Byte0]: 77
7959 12:29:34.440326 [Byte1]: 77
7960 12:29:34.444399
7961 12:29:34.444515 Set Vref, RX VrefLevel [Byte0]: 78
7962 12:29:34.447481 [Byte1]: 78
7963 12:29:34.451994
7964 12:29:34.452097 Set Vref, RX VrefLevel [Byte0]: 79
7965 12:29:34.455427 [Byte1]: 79
7966 12:29:34.459324
7967 12:29:34.459426 Set Vref, RX VrefLevel [Byte0]: 80
7968 12:29:34.462760 [Byte1]: 80
7969 12:29:34.467195
7970 12:29:34.467301 Final RX Vref Byte 0 = 61 to rank0
7971 12:29:34.470194 Final RX Vref Byte 1 = 61 to rank0
7972 12:29:34.473733 Final RX Vref Byte 0 = 61 to rank1
7973 12:29:34.477251 Final RX Vref Byte 1 = 61 to rank1==
7974 12:29:34.480284 Dram Type= 6, Freq= 0, CH_0, rank 0
7975 12:29:34.486699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 12:29:34.486806 ==
7977 12:29:34.486911 DQS Delay:
7978 12:29:34.490105 DQS0 = 0, DQS1 = 0
7979 12:29:34.490206 DQM Delay:
7980 12:29:34.490303 DQM0 = 136, DQM1 = 124
7981 12:29:34.493286 DQ Delay:
7982 12:29:34.496537 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =134
7983 12:29:34.499821 DQ4 =140, DQ5 =126, DQ6 =142, DQ7 =144
7984 12:29:34.503167 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7985 12:29:34.506751 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =134
7986 12:29:34.506866
7987 12:29:34.506967
7988 12:29:34.507093
7989 12:29:34.510076 [DramC_TX_OE_Calibration] TA2
7990 12:29:34.513126 Original DQ_B0 (3 6) =30, OEN = 27
7991 12:29:34.516331 Original DQ_B1 (3 6) =30, OEN = 27
7992 12:29:34.519681 24, 0x0, End_B0=24 End_B1=24
7993 12:29:34.522940 25, 0x0, End_B0=25 End_B1=25
7994 12:29:34.523047 26, 0x0, End_B0=26 End_B1=26
7995 12:29:34.526151 27, 0x0, End_B0=27 End_B1=27
7996 12:29:34.529642 28, 0x0, End_B0=28 End_B1=28
7997 12:29:34.532754 29, 0x0, End_B0=29 End_B1=29
7998 12:29:34.532871 30, 0x0, End_B0=30 End_B1=30
7999 12:29:34.536221 31, 0x4545, End_B0=30 End_B1=30
8000 12:29:34.539577 Byte0 end_step=30 best_step=27
8001 12:29:34.542629 Byte1 end_step=30 best_step=27
8002 12:29:34.546120 Byte0 TX OE(2T, 0.5T) = (3, 3)
8003 12:29:34.549180 Byte1 TX OE(2T, 0.5T) = (3, 3)
8004 12:29:34.549254
8005 12:29:34.549317
8006 12:29:34.556126 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
8007 12:29:34.559193 CH0 RK0: MR19=303, MR18=1B19
8008 12:29:34.565725 CH0_RK0: MR19=0x303, MR18=0x1B19, DQSOSC=396, MR23=63, INC=23, DEC=15
8009 12:29:34.565804
8010 12:29:34.569237 ----->DramcWriteLeveling(PI) begin...
8011 12:29:34.569311 ==
8012 12:29:34.572684 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 12:29:34.575678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 12:29:34.575777 ==
8015 12:29:34.579268 Write leveling (Byte 0): 35 => 35
8016 12:29:34.582463 Write leveling (Byte 1): 29 => 29
8017 12:29:34.585531 DramcWriteLeveling(PI) end<-----
8018 12:29:34.585634
8019 12:29:34.585745 ==
8020 12:29:34.588991 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 12:29:34.595439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 12:29:34.595549 ==
8023 12:29:34.595644 [Gating] SW mode calibration
8024 12:29:34.605719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8025 12:29:34.608772 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8026 12:29:34.612335 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 12:29:34.618950 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 12:29:34.622140 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8029 12:29:34.625596 1 4 12 | B1->B0 | 2525 3232 | 1 1 | (1 1) (1 1)
8030 12:29:34.631801 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8031 12:29:34.635415 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 12:29:34.638343 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 12:29:34.645330 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 12:29:34.648236 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 12:29:34.651736 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 12:29:34.658439 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 12:29:34.661427 1 5 12 | B1->B0 | 3232 2626 | 1 0 | (1 0) (1 0)
8038 12:29:34.665020 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8039 12:29:34.671499 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 12:29:34.674569 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 12:29:34.678094 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 12:29:34.684647 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 12:29:34.687704 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 12:29:34.691286 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8045 12:29:34.697781 1 6 12 | B1->B0 | 2b2b 4141 | 1 0 | (0 0) (0 0)
8046 12:29:34.700702 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8047 12:29:34.704274 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 12:29:34.710792 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 12:29:34.714207 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 12:29:34.717760 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 12:29:34.723968 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 12:29:34.727317 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 12:29:34.734107 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8054 12:29:34.737451 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8055 12:29:34.740631 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:29:34.747001 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:29:34.750018 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:29:34.753473 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:29:34.760043 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:29:34.763487 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:29:34.766543 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 12:29:34.773324 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:29:34.776730 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 12:29:34.779895 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 12:29:34.786451 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 12:29:34.789943 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 12:29:34.792959 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 12:29:34.800127 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8069 12:29:34.803041 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8070 12:29:34.806558 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8071 12:29:34.809859 Total UI for P1: 0, mck2ui 16
8072 12:29:34.813135 best dqsien dly found for B0: ( 1, 9, 10)
8073 12:29:34.816419 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 12:29:34.819811 Total UI for P1: 0, mck2ui 16
8075 12:29:34.822804 best dqsien dly found for B1: ( 1, 9, 14)
8076 12:29:34.826383 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8077 12:29:34.832565 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8078 12:29:34.832651
8079 12:29:34.835924 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8080 12:29:34.839575 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8081 12:29:34.842819 [Gating] SW calibration Done
8082 12:29:34.842909 ==
8083 12:29:34.846127 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 12:29:34.849511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 12:29:34.849596 ==
8086 12:29:34.852747 RX Vref Scan: 0
8087 12:29:34.852871
8088 12:29:34.852939 RX Vref 0 -> 0, step: 1
8089 12:29:34.853002
8090 12:29:34.855866 RX Delay 0 -> 252, step: 8
8091 12:29:34.859258 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8092 12:29:34.866256 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8093 12:29:34.869215 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8094 12:29:34.872747 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8095 12:29:34.875758 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8096 12:29:34.879178 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8097 12:29:34.885730 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8098 12:29:34.889252 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8099 12:29:34.892239 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8100 12:29:34.895703 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8101 12:29:34.898764 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8102 12:29:34.905815 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8103 12:29:34.908926 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8104 12:29:34.912432 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8105 12:29:34.915983 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8106 12:29:34.919175 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8107 12:29:34.919261 ==
8108 12:29:34.922346 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 12:29:34.928668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 12:29:34.928787 ==
8111 12:29:34.928885 DQS Delay:
8112 12:29:34.932172 DQS0 = 0, DQS1 = 0
8113 12:29:34.932248 DQM Delay:
8114 12:29:34.935609 DQM0 = 136, DQM1 = 125
8115 12:29:34.935695 DQ Delay:
8116 12:29:34.939016 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8117 12:29:34.942253 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8118 12:29:34.945434 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8119 12:29:34.948652 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8120 12:29:34.948787
8121 12:29:34.948873
8122 12:29:34.948935 ==
8123 12:29:34.952110 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 12:29:34.958767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 12:29:34.958853 ==
8126 12:29:34.958921
8127 12:29:34.959001
8128 12:29:34.959080 TX Vref Scan disable
8129 12:29:34.962230 == TX Byte 0 ==
8130 12:29:34.965747 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8131 12:29:34.972409 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8132 12:29:34.972494 == TX Byte 1 ==
8133 12:29:34.975200 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8134 12:29:34.982159 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8135 12:29:34.982274 ==
8136 12:29:34.985181 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 12:29:34.988644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 12:29:34.988728 ==
8139 12:29:35.001853
8140 12:29:35.005286 TX Vref early break, caculate TX vref
8141 12:29:35.008356 TX Vref=16, minBit 8, minWin=23, winSum=387
8142 12:29:35.011724 TX Vref=18, minBit 1, minWin=24, winSum=399
8143 12:29:35.014764 TX Vref=20, minBit 1, minWin=24, winSum=405
8144 12:29:35.018419 TX Vref=22, minBit 0, minWin=25, winSum=416
8145 12:29:35.021666 TX Vref=24, minBit 0, minWin=26, winSum=424
8146 12:29:35.028143 TX Vref=26, minBit 0, minWin=26, winSum=430
8147 12:29:35.031477 TX Vref=28, minBit 1, minWin=26, winSum=434
8148 12:29:35.034882 TX Vref=30, minBit 2, minWin=25, winSum=426
8149 12:29:35.037862 TX Vref=32, minBit 2, minWin=25, winSum=413
8150 12:29:35.041364 TX Vref=34, minBit 1, minWin=24, winSum=407
8151 12:29:35.048244 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
8152 12:29:35.048334
8153 12:29:35.051448 Final TX Range 0 Vref 28
8154 12:29:35.051553
8155 12:29:35.051657 ==
8156 12:29:35.054650 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 12:29:35.057974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 12:29:35.058103 ==
8159 12:29:35.058259
8160 12:29:35.058363
8161 12:29:35.061184 TX Vref Scan disable
8162 12:29:35.067615 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8163 12:29:35.067700 == TX Byte 0 ==
8164 12:29:35.071199 u2DelayCellOfst[0]=13 cells (4 PI)
8165 12:29:35.074644 u2DelayCellOfst[1]=16 cells (5 PI)
8166 12:29:35.077519 u2DelayCellOfst[2]=13 cells (4 PI)
8167 12:29:35.081218 u2DelayCellOfst[3]=13 cells (4 PI)
8168 12:29:35.084108 u2DelayCellOfst[4]=10 cells (3 PI)
8169 12:29:35.087454 u2DelayCellOfst[5]=0 cells (0 PI)
8170 12:29:35.090965 u2DelayCellOfst[6]=16 cells (5 PI)
8171 12:29:35.094450 u2DelayCellOfst[7]=16 cells (5 PI)
8172 12:29:35.097435 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8173 12:29:35.100933 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8174 12:29:35.104003 == TX Byte 1 ==
8175 12:29:35.107522 u2DelayCellOfst[8]=0 cells (0 PI)
8176 12:29:35.110534 u2DelayCellOfst[9]=0 cells (0 PI)
8177 12:29:35.114011 u2DelayCellOfst[10]=6 cells (2 PI)
8178 12:29:35.114086 u2DelayCellOfst[11]=3 cells (1 PI)
8179 12:29:35.117067 u2DelayCellOfst[12]=13 cells (4 PI)
8180 12:29:35.120553 u2DelayCellOfst[13]=10 cells (3 PI)
8181 12:29:35.124003 u2DelayCellOfst[14]=13 cells (4 PI)
8182 12:29:35.126992 u2DelayCellOfst[15]=10 cells (3 PI)
8183 12:29:35.133535 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8184 12:29:35.136823 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8185 12:29:35.136930 DramC Write-DBI on
8186 12:29:35.140329 ==
8187 12:29:35.143333 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 12:29:35.146768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 12:29:35.146875 ==
8190 12:29:35.146971
8191 12:29:35.147062
8192 12:29:35.149725 TX Vref Scan disable
8193 12:29:35.149827 == TX Byte 0 ==
8194 12:29:35.156490 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8195 12:29:35.156603 == TX Byte 1 ==
8196 12:29:35.160116 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8197 12:29:35.163327 DramC Write-DBI off
8198 12:29:35.163430
8199 12:29:35.163523 [DATLAT]
8200 12:29:35.166506 Freq=1600, CH0 RK1
8201 12:29:35.166619
8202 12:29:35.166729 DATLAT Default: 0xf
8203 12:29:35.170127 0, 0xFFFF, sum = 0
8204 12:29:35.170224 1, 0xFFFF, sum = 0
8205 12:29:35.173162 2, 0xFFFF, sum = 0
8206 12:29:35.173248 3, 0xFFFF, sum = 0
8207 12:29:35.176570 4, 0xFFFF, sum = 0
8208 12:29:35.176648 5, 0xFFFF, sum = 0
8209 12:29:35.180080 6, 0xFFFF, sum = 0
8210 12:29:35.180169 7, 0xFFFF, sum = 0
8211 12:29:35.183140 8, 0xFFFF, sum = 0
8212 12:29:35.186522 9, 0xFFFF, sum = 0
8213 12:29:35.186603 10, 0xFFFF, sum = 0
8214 12:29:35.189872 11, 0xFFFF, sum = 0
8215 12:29:35.189986 12, 0xFFFF, sum = 0
8216 12:29:35.193308 13, 0xFFFF, sum = 0
8217 12:29:35.193422 14, 0x0, sum = 1
8218 12:29:35.196261 15, 0x0, sum = 2
8219 12:29:35.196348 16, 0x0, sum = 3
8220 12:29:35.199600 17, 0x0, sum = 4
8221 12:29:35.199687 best_step = 15
8222 12:29:35.199753
8223 12:29:35.199816 ==
8224 12:29:35.203217 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 12:29:35.206185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 12:29:35.206275 ==
8227 12:29:35.209600 RX Vref Scan: 0
8228 12:29:35.209688
8229 12:29:35.213080 RX Vref 0 -> 0, step: 1
8230 12:29:35.213168
8231 12:29:35.213255 RX Delay 11 -> 252, step: 4
8232 12:29:35.220150 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8233 12:29:35.223727 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8234 12:29:35.226770 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8235 12:29:35.230343 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8236 12:29:35.233270 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8237 12:29:35.240286 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8238 12:29:35.243124 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8239 12:29:35.246533 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8240 12:29:35.249821 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8241 12:29:35.253401 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8242 12:29:35.260120 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8243 12:29:35.263376 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8244 12:29:35.266575 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8245 12:29:35.269801 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8246 12:29:35.276228 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8247 12:29:35.279727 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8248 12:29:35.279834 ==
8249 12:29:35.282777 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 12:29:35.286251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 12:29:35.286358 ==
8252 12:29:35.289799 DQS Delay:
8253 12:29:35.289877 DQS0 = 0, DQS1 = 0
8254 12:29:35.289958 DQM Delay:
8255 12:29:35.292758 DQM0 = 133, DQM1 = 123
8256 12:29:35.292841 DQ Delay:
8257 12:29:35.296247 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8258 12:29:35.299725 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8259 12:29:35.302618 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8260 12:29:35.309179 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8261 12:29:35.309260
8262 12:29:35.309325
8263 12:29:35.309386
8264 12:29:35.312715 [DramC_TX_OE_Calibration] TA2
8265 12:29:35.316235 Original DQ_B0 (3 6) =30, OEN = 27
8266 12:29:35.316340 Original DQ_B1 (3 6) =30, OEN = 27
8267 12:29:35.319198 24, 0x0, End_B0=24 End_B1=24
8268 12:29:35.322653 25, 0x0, End_B0=25 End_B1=25
8269 12:29:35.326112 26, 0x0, End_B0=26 End_B1=26
8270 12:29:35.329139 27, 0x0, End_B0=27 End_B1=27
8271 12:29:35.329215 28, 0x0, End_B0=28 End_B1=28
8272 12:29:35.332588 29, 0x0, End_B0=29 End_B1=29
8273 12:29:35.336073 30, 0x0, End_B0=30 End_B1=30
8274 12:29:35.339562 31, 0x4545, End_B0=30 End_B1=30
8275 12:29:35.342757 Byte0 end_step=30 best_step=27
8276 12:29:35.342863 Byte1 end_step=30 best_step=27
8277 12:29:35.345893 Byte0 TX OE(2T, 0.5T) = (3, 3)
8278 12:29:35.349328 Byte1 TX OE(2T, 0.5T) = (3, 3)
8279 12:29:35.349421
8280 12:29:35.349515
8281 12:29:35.358977 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8282 12:29:35.359090 CH0 RK1: MR19=303, MR18=1E0B
8283 12:29:35.365838 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8284 12:29:35.369177 [RxdqsGatingPostProcess] freq 1600
8285 12:29:35.375631 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8286 12:29:35.378722 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 12:29:35.382043 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 12:29:35.385523 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 12:29:35.389025 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 12:29:35.392126 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 12:29:35.392230 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 12:29:35.395519 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 12:29:35.398874 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 12:29:35.401964 Pre-setting of DQS Precalculation
8295 12:29:35.408556 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8296 12:29:35.408666 ==
8297 12:29:35.412142 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 12:29:35.415198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 12:29:35.415304 ==
8300 12:29:35.422267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 12:29:35.425198 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 12:29:35.428687 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 12:29:35.435276 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 12:29:35.444173 [CA 0] Center 41 (12~71) winsize 60
8305 12:29:35.447593 [CA 1] Center 42 (13~72) winsize 60
8306 12:29:35.451192 [CA 2] Center 38 (9~68) winsize 60
8307 12:29:35.454267 [CA 3] Center 37 (8~67) winsize 60
8308 12:29:35.457590 [CA 4] Center 37 (8~67) winsize 60
8309 12:29:35.460870 [CA 5] Center 37 (8~67) winsize 60
8310 12:29:35.460978
8311 12:29:35.464417 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8312 12:29:35.464526
8313 12:29:35.467466 [CATrainingPosCal] consider 1 rank data
8314 12:29:35.470679 u2DelayCellTimex100 = 290/100 ps
8315 12:29:35.477553 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8316 12:29:35.480920 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8317 12:29:35.484214 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8318 12:29:35.487480 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8319 12:29:35.490896 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8320 12:29:35.493897 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8321 12:29:35.493984
8322 12:29:35.497406 CA PerBit enable=1, Macro0, CA PI delay=37
8323 12:29:35.497492
8324 12:29:35.500295 [CBTSetCACLKResult] CA Dly = 37
8325 12:29:35.503719 CS Dly: 8 (0~39)
8326 12:29:35.507219 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 12:29:35.510244 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 12:29:35.510350 ==
8329 12:29:35.513668 Dram Type= 6, Freq= 0, CH_1, rank 1
8330 12:29:35.520164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 12:29:35.520250 ==
8332 12:29:35.523697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8333 12:29:35.526705 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8334 12:29:35.533737 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8335 12:29:35.540230 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8336 12:29:35.547730 [CA 0] Center 42 (13~72) winsize 60
8337 12:29:35.550706 [CA 1] Center 42 (12~72) winsize 61
8338 12:29:35.554016 [CA 2] Center 38 (9~68) winsize 60
8339 12:29:35.557653 [CA 3] Center 37 (8~67) winsize 60
8340 12:29:35.561003 [CA 4] Center 38 (9~67) winsize 59
8341 12:29:35.564325 [CA 5] Center 37 (8~67) winsize 60
8342 12:29:35.564409
8343 12:29:35.567193 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8344 12:29:35.567267
8345 12:29:35.570542 [CATrainingPosCal] consider 2 rank data
8346 12:29:35.574051 u2DelayCellTimex100 = 290/100 ps
8347 12:29:35.577449 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8348 12:29:35.584052 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8349 12:29:35.587307 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8350 12:29:35.590501 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8351 12:29:35.593683 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8352 12:29:35.597018 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8353 12:29:35.597097
8354 12:29:35.600438 CA PerBit enable=1, Macro0, CA PI delay=37
8355 12:29:35.600538
8356 12:29:35.603808 [CBTSetCACLKResult] CA Dly = 37
8357 12:29:35.606819 CS Dly: 9 (0~42)
8358 12:29:35.610247 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8359 12:29:35.613742 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8360 12:29:35.613823
8361 12:29:35.616749 ----->DramcWriteLeveling(PI) begin...
8362 12:29:35.616854 ==
8363 12:29:35.620381 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 12:29:35.626896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 12:29:35.627006 ==
8366 12:29:35.629902 Write leveling (Byte 0): 24 => 24
8367 12:29:35.629983 Write leveling (Byte 1): 28 => 28
8368 12:29:35.633500 DramcWriteLeveling(PI) end<-----
8369 12:29:35.633583
8370 12:29:35.637097 ==
8371 12:29:35.637181 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 12:29:35.643245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 12:29:35.643330 ==
8374 12:29:35.646628 [Gating] SW mode calibration
8375 12:29:35.653291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8376 12:29:35.656363 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8377 12:29:35.663348 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 12:29:35.666778 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 12:29:35.669949 1 4 8 | B1->B0 | 2828 3131 | 1 1 | (1 1) (1 1)
8380 12:29:35.676278 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8381 12:29:35.679655 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 12:29:35.683025 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 12:29:35.689672 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 12:29:35.693058 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 12:29:35.696205 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 12:29:35.702935 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8387 12:29:35.705876 1 5 8 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
8388 12:29:35.709337 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8389 12:29:35.715895 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 12:29:35.719546 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 12:29:35.722466 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 12:29:35.728921 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 12:29:35.732463 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 12:29:35.735587 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 12:29:35.742170 1 6 8 | B1->B0 | 3333 4242 | 1 0 | (0 0) (0 0)
8396 12:29:35.745578 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:29:35.749094 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:29:35.755712 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:29:35.758747 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 12:29:35.762244 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 12:29:35.768970 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 12:29:35.772255 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 12:29:35.775437 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8404 12:29:35.781884 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8405 12:29:35.785382 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:29:35.788886 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:29:35.795366 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:29:35.798594 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:29:35.801872 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:29:35.808297 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:29:35.811776 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:29:35.814752 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:29:35.821318 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:29:35.824969 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:29:35.827881 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 12:29:35.834844 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 12:29:35.837846 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 12:29:35.841354 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 12:29:35.847913 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8420 12:29:35.851328 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8421 12:29:35.854407 Total UI for P1: 0, mck2ui 16
8422 12:29:35.857742 best dqsien dly found for B0: ( 1, 9, 8)
8423 12:29:35.861253 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 12:29:35.864302 Total UI for P1: 0, mck2ui 16
8425 12:29:35.867774 best dqsien dly found for B1: ( 1, 9, 12)
8426 12:29:35.871047 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8427 12:29:35.874287 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8428 12:29:35.874382
8429 12:29:35.877643 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8430 12:29:35.884146 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8431 12:29:35.884273 [Gating] SW calibration Done
8432 12:29:35.887446 ==
8433 12:29:35.890875 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 12:29:35.894026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 12:29:35.894146 ==
8436 12:29:35.894282 RX Vref Scan: 0
8437 12:29:35.894416
8438 12:29:35.897323 RX Vref 0 -> 0, step: 1
8439 12:29:35.897442
8440 12:29:35.900612 RX Delay 0 -> 252, step: 8
8441 12:29:35.904132 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8442 12:29:35.907441 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8443 12:29:35.910440 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8444 12:29:35.917575 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8445 12:29:35.920398 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8446 12:29:35.923951 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8447 12:29:35.927311 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8448 12:29:35.930373 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8449 12:29:35.936871 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8450 12:29:35.940379 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8451 12:29:35.943874 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8452 12:29:35.946842 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8453 12:29:35.950473 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8454 12:29:35.957081 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8455 12:29:35.960067 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8456 12:29:35.963498 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8457 12:29:35.963584 ==
8458 12:29:35.967046 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 12:29:35.970354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 12:29:35.970440 ==
8461 12:29:35.973697 DQS Delay:
8462 12:29:35.973782 DQS0 = 0, DQS1 = 0
8463 12:29:35.977101 DQM Delay:
8464 12:29:35.977189 DQM0 = 138, DQM1 = 130
8465 12:29:35.980056 DQ Delay:
8466 12:29:35.983436 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8467 12:29:35.986732 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8468 12:29:35.990078 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8469 12:29:35.993532 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8470 12:29:35.993632
8471 12:29:35.993699
8472 12:29:35.993760 ==
8473 12:29:35.996878 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 12:29:35.999823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 12:29:35.999968 ==
8476 12:29:36.000062
8477 12:29:36.003295
8478 12:29:36.003385 TX Vref Scan disable
8479 12:29:36.006508 == TX Byte 0 ==
8480 12:29:36.009678 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8481 12:29:36.013054 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8482 12:29:36.016384 == TX Byte 1 ==
8483 12:29:36.019634 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8484 12:29:36.022793 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8485 12:29:36.022881 ==
8486 12:29:36.026146 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 12:29:36.032860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 12:29:36.032948 ==
8489 12:29:36.045563
8490 12:29:36.048939 TX Vref early break, caculate TX vref
8491 12:29:36.052059 TX Vref=16, minBit 1, minWin=22, winSum=373
8492 12:29:36.055497 TX Vref=18, minBit 15, minWin=22, winSum=383
8493 12:29:36.058857 TX Vref=20, minBit 0, minWin=24, winSum=392
8494 12:29:36.061823 TX Vref=22, minBit 9, minWin=24, winSum=404
8495 12:29:36.068438 TX Vref=24, minBit 15, minWin=24, winSum=415
8496 12:29:36.071915 TX Vref=26, minBit 2, minWin=25, winSum=419
8497 12:29:36.075306 TX Vref=28, minBit 1, minWin=26, winSum=427
8498 12:29:36.078197 TX Vref=30, minBit 10, minWin=25, winSum=422
8499 12:29:36.081749 TX Vref=32, minBit 10, minWin=24, winSum=411
8500 12:29:36.085226 TX Vref=34, minBit 10, minWin=24, winSum=405
8501 12:29:36.091420 TX Vref=36, minBit 10, minWin=22, winSum=391
8502 12:29:36.094920 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
8503 12:29:36.095009
8504 12:29:36.098387 Final TX Range 0 Vref 28
8505 12:29:36.098472
8506 12:29:36.098540 ==
8507 12:29:36.101846 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 12:29:36.108351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 12:29:36.108436 ==
8510 12:29:36.108502
8511 12:29:36.108563
8512 12:29:36.108620 TX Vref Scan disable
8513 12:29:36.115391 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8514 12:29:36.115517 == TX Byte 0 ==
8515 12:29:36.118628 u2DelayCellOfst[0]=16 cells (5 PI)
8516 12:29:36.121866 u2DelayCellOfst[1]=10 cells (3 PI)
8517 12:29:36.125058 u2DelayCellOfst[2]=0 cells (0 PI)
8518 12:29:36.128390 u2DelayCellOfst[3]=6 cells (2 PI)
8519 12:29:36.131708 u2DelayCellOfst[4]=6 cells (2 PI)
8520 12:29:36.135145 u2DelayCellOfst[5]=16 cells (5 PI)
8521 12:29:36.138165 u2DelayCellOfst[6]=16 cells (5 PI)
8522 12:29:36.141714 u2DelayCellOfst[7]=6 cells (2 PI)
8523 12:29:36.145248 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8524 12:29:36.148171 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8525 12:29:36.151671 == TX Byte 1 ==
8526 12:29:36.155158 u2DelayCellOfst[8]=0 cells (0 PI)
8527 12:29:36.158164 u2DelayCellOfst[9]=0 cells (0 PI)
8528 12:29:36.161734 u2DelayCellOfst[10]=10 cells (3 PI)
8529 12:29:36.164653 u2DelayCellOfst[11]=3 cells (1 PI)
8530 12:29:36.168195 u2DelayCellOfst[12]=13 cells (4 PI)
8531 12:29:36.168279 u2DelayCellOfst[13]=13 cells (4 PI)
8532 12:29:36.171272 u2DelayCellOfst[14]=13 cells (4 PI)
8533 12:29:36.174764 u2DelayCellOfst[15]=10 cells (3 PI)
8534 12:29:36.181304 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8535 12:29:36.184652 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8536 12:29:36.184737 DramC Write-DBI on
8537 12:29:36.188079 ==
8538 12:29:36.191539 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 12:29:36.194801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 12:29:36.194884 ==
8541 12:29:36.194950
8542 12:29:36.195010
8543 12:29:36.198189 TX Vref Scan disable
8544 12:29:36.198273 == TX Byte 0 ==
8545 12:29:36.204518 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8546 12:29:36.204603 == TX Byte 1 ==
8547 12:29:36.208101 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8548 12:29:36.211069 DramC Write-DBI off
8549 12:29:36.211202
8550 12:29:36.211298 [DATLAT]
8551 12:29:36.214530 Freq=1600, CH1 RK0
8552 12:29:36.214614
8553 12:29:36.214680 DATLAT Default: 0xf
8554 12:29:36.217811 0, 0xFFFF, sum = 0
8555 12:29:36.217896 1, 0xFFFF, sum = 0
8556 12:29:36.221061 2, 0xFFFF, sum = 0
8557 12:29:36.221146 3, 0xFFFF, sum = 0
8558 12:29:36.224273 4, 0xFFFF, sum = 0
8559 12:29:36.224358 5, 0xFFFF, sum = 0
8560 12:29:36.227581 6, 0xFFFF, sum = 0
8561 12:29:36.230882 7, 0xFFFF, sum = 0
8562 12:29:36.230967 8, 0xFFFF, sum = 0
8563 12:29:36.234144 9, 0xFFFF, sum = 0
8564 12:29:36.234228 10, 0xFFFF, sum = 0
8565 12:29:36.237619 11, 0xFFFF, sum = 0
8566 12:29:36.237703 12, 0xFFFF, sum = 0
8567 12:29:36.240616 13, 0xFFFF, sum = 0
8568 12:29:36.240700 14, 0x0, sum = 1
8569 12:29:36.244205 15, 0x0, sum = 2
8570 12:29:36.244290 16, 0x0, sum = 3
8571 12:29:36.247226 17, 0x0, sum = 4
8572 12:29:36.247311 best_step = 15
8573 12:29:36.247376
8574 12:29:36.247437 ==
8575 12:29:36.250700 Dram Type= 6, Freq= 0, CH_1, rank 0
8576 12:29:36.254159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8577 12:29:36.257215 ==
8578 12:29:36.257298 RX Vref Scan: 1
8579 12:29:36.257364
8580 12:29:36.260799 Set Vref Range= 24 -> 127
8581 12:29:36.260883
8582 12:29:36.260949 RX Vref 24 -> 127, step: 1
8583 12:29:36.263899
8584 12:29:36.263983 RX Delay 19 -> 252, step: 4
8585 12:29:36.264048
8586 12:29:36.267446 Set Vref, RX VrefLevel [Byte0]: 24
8587 12:29:36.270437 [Byte1]: 24
8588 12:29:36.273976
8589 12:29:36.277454 Set Vref, RX VrefLevel [Byte0]: 25
8590 12:29:36.280387 [Byte1]: 25
8591 12:29:36.280470
8592 12:29:36.283767 Set Vref, RX VrefLevel [Byte0]: 26
8593 12:29:36.287069 [Byte1]: 26
8594 12:29:36.287153
8595 12:29:36.290441 Set Vref, RX VrefLevel [Byte0]: 27
8596 12:29:36.293825 [Byte1]: 27
8597 12:29:36.297151
8598 12:29:36.297234 Set Vref, RX VrefLevel [Byte0]: 28
8599 12:29:36.300135 [Byte1]: 28
8600 12:29:36.304488
8601 12:29:36.304571 Set Vref, RX VrefLevel [Byte0]: 29
8602 12:29:36.307888 [Byte1]: 29
8603 12:29:36.312058
8604 12:29:36.312157 Set Vref, RX VrefLevel [Byte0]: 30
8605 12:29:36.315463 [Byte1]: 30
8606 12:29:36.319839
8607 12:29:36.319939 Set Vref, RX VrefLevel [Byte0]: 31
8608 12:29:36.322761 [Byte1]: 31
8609 12:29:36.327247
8610 12:29:36.327347 Set Vref, RX VrefLevel [Byte0]: 32
8611 12:29:36.330505 [Byte1]: 32
8612 12:29:36.334852
8613 12:29:36.334936 Set Vref, RX VrefLevel [Byte0]: 33
8614 12:29:36.338111 [Byte1]: 33
8615 12:29:36.342565
8616 12:29:36.342650 Set Vref, RX VrefLevel [Byte0]: 34
8617 12:29:36.345512 [Byte1]: 34
8618 12:29:36.350056
8619 12:29:36.350168 Set Vref, RX VrefLevel [Byte0]: 35
8620 12:29:36.353040 [Byte1]: 35
8621 12:29:36.357727
8622 12:29:36.357835 Set Vref, RX VrefLevel [Byte0]: 36
8623 12:29:36.360701 [Byte1]: 36
8624 12:29:36.365086
8625 12:29:36.365160 Set Vref, RX VrefLevel [Byte0]: 37
8626 12:29:36.368503 [Byte1]: 37
8627 12:29:36.372651
8628 12:29:36.372736 Set Vref, RX VrefLevel [Byte0]: 38
8629 12:29:36.376196 [Byte1]: 38
8630 12:29:36.380218
8631 12:29:36.380332 Set Vref, RX VrefLevel [Byte0]: 39
8632 12:29:36.383715 [Byte1]: 39
8633 12:29:36.387692
8634 12:29:36.387787 Set Vref, RX VrefLevel [Byte0]: 40
8635 12:29:36.390920 [Byte1]: 40
8636 12:29:36.395257
8637 12:29:36.395333 Set Vref, RX VrefLevel [Byte0]: 41
8638 12:29:36.398659 [Byte1]: 41
8639 12:29:36.402894
8640 12:29:36.402999 Set Vref, RX VrefLevel [Byte0]: 42
8641 12:29:36.406378 [Byte1]: 42
8642 12:29:36.410502
8643 12:29:36.410606 Set Vref, RX VrefLevel [Byte0]: 43
8644 12:29:36.413923 [Byte1]: 43
8645 12:29:36.417929
8646 12:29:36.418029 Set Vref, RX VrefLevel [Byte0]: 44
8647 12:29:36.421506 [Byte1]: 44
8648 12:29:36.425765
8649 12:29:36.425864 Set Vref, RX VrefLevel [Byte0]: 45
8650 12:29:36.428821 [Byte1]: 45
8651 12:29:36.433248
8652 12:29:36.433336 Set Vref, RX VrefLevel [Byte0]: 46
8653 12:29:36.436477 [Byte1]: 46
8654 12:29:36.440653
8655 12:29:36.440760 Set Vref, RX VrefLevel [Byte0]: 47
8656 12:29:36.444325 [Byte1]: 47
8657 12:29:36.448398
8658 12:29:36.448502 Set Vref, RX VrefLevel [Byte0]: 48
8659 12:29:36.451740 [Byte1]: 48
8660 12:29:36.455763
8661 12:29:36.455840 Set Vref, RX VrefLevel [Byte0]: 49
8662 12:29:36.459442 [Byte1]: 49
8663 12:29:36.463538
8664 12:29:36.463639 Set Vref, RX VrefLevel [Byte0]: 50
8665 12:29:36.467086 [Byte1]: 50
8666 12:29:36.471243
8667 12:29:36.471316 Set Vref, RX VrefLevel [Byte0]: 51
8668 12:29:36.474242 [Byte1]: 51
8669 12:29:36.478766
8670 12:29:36.478837 Set Vref, RX VrefLevel [Byte0]: 52
8671 12:29:36.481743 [Byte1]: 52
8672 12:29:36.486303
8673 12:29:36.486418 Set Vref, RX VrefLevel [Byte0]: 53
8674 12:29:36.489487 [Byte1]: 53
8675 12:29:36.493927
8676 12:29:36.494013 Set Vref, RX VrefLevel [Byte0]: 54
8677 12:29:36.497267 [Byte1]: 54
8678 12:29:36.501533
8679 12:29:36.501619 Set Vref, RX VrefLevel [Byte0]: 55
8680 12:29:36.505009 [Byte1]: 55
8681 12:29:36.509244
8682 12:29:36.509322 Set Vref, RX VrefLevel [Byte0]: 56
8683 12:29:36.512207 [Byte1]: 56
8684 12:29:36.516559
8685 12:29:36.516661 Set Vref, RX VrefLevel [Byte0]: 57
8686 12:29:36.520089 [Byte1]: 57
8687 12:29:36.523962
8688 12:29:36.524048 Set Vref, RX VrefLevel [Byte0]: 58
8689 12:29:36.527398 [Byte1]: 58
8690 12:29:36.531765
8691 12:29:36.531859 Set Vref, RX VrefLevel [Byte0]: 59
8692 12:29:36.535149 [Byte1]: 59
8693 12:29:36.539166
8694 12:29:36.542431 Set Vref, RX VrefLevel [Byte0]: 60
8695 12:29:36.542553 [Byte1]: 60
8696 12:29:36.546594
8697 12:29:36.546705 Set Vref, RX VrefLevel [Byte0]: 61
8698 12:29:36.550275 [Byte1]: 61
8699 12:29:36.554412
8700 12:29:36.554528 Set Vref, RX VrefLevel [Byte0]: 62
8701 12:29:36.557742 [Byte1]: 62
8702 12:29:36.561901
8703 12:29:36.561976 Set Vref, RX VrefLevel [Byte0]: 63
8704 12:29:36.565472 [Byte1]: 63
8705 12:29:36.569533
8706 12:29:36.569617 Set Vref, RX VrefLevel [Byte0]: 64
8707 12:29:36.573066 [Byte1]: 64
8708 12:29:36.577042
8709 12:29:36.577227 Set Vref, RX VrefLevel [Byte0]: 65
8710 12:29:36.580608 [Byte1]: 65
8711 12:29:36.584582
8712 12:29:36.584688 Set Vref, RX VrefLevel [Byte0]: 66
8713 12:29:36.588172 [Byte1]: 66
8714 12:29:36.592272
8715 12:29:36.592384 Set Vref, RX VrefLevel [Byte0]: 67
8716 12:29:36.595816 [Byte1]: 67
8717 12:29:36.600081
8718 12:29:36.600180 Set Vref, RX VrefLevel [Byte0]: 68
8719 12:29:36.603022 [Byte1]: 68
8720 12:29:36.607468
8721 12:29:36.607576 Set Vref, RX VrefLevel [Byte0]: 69
8722 12:29:36.610737 [Byte1]: 69
8723 12:29:36.615145
8724 12:29:36.615251 Set Vref, RX VrefLevel [Byte0]: 70
8725 12:29:36.618109 [Byte1]: 70
8726 12:29:36.622589
8727 12:29:36.622676 Set Vref, RX VrefLevel [Byte0]: 71
8728 12:29:36.625987 [Byte1]: 71
8729 12:29:36.630080
8730 12:29:36.630205 Set Vref, RX VrefLevel [Byte0]: 72
8731 12:29:36.633548 [Byte1]: 72
8732 12:29:36.637545
8733 12:29:36.637655 Set Vref, RX VrefLevel [Byte0]: 73
8734 12:29:36.640947 [Byte1]: 73
8735 12:29:36.645444
8736 12:29:36.645551 Set Vref, RX VrefLevel [Byte0]: 74
8737 12:29:36.648645 [Byte1]: 74
8738 12:29:36.652795
8739 12:29:36.652903 Final RX Vref Byte 0 = 52 to rank0
8740 12:29:36.656024 Final RX Vref Byte 1 = 61 to rank0
8741 12:29:36.659585 Final RX Vref Byte 0 = 52 to rank1
8742 12:29:36.662839 Final RX Vref Byte 1 = 61 to rank1==
8743 12:29:36.665880 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 12:29:36.672480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 12:29:36.672587 ==
8746 12:29:36.672683 DQS Delay:
8747 12:29:36.676116 DQS0 = 0, DQS1 = 0
8748 12:29:36.676195 DQM Delay:
8749 12:29:36.676276 DQM0 = 133, DQM1 = 128
8750 12:29:36.679044 DQ Delay:
8751 12:29:36.682457 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8752 12:29:36.685900 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8753 12:29:36.689013 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8754 12:29:36.692431 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8755 12:29:36.692532
8756 12:29:36.692626
8757 12:29:36.692721
8758 12:29:36.695505 [DramC_TX_OE_Calibration] TA2
8759 12:29:36.699020 Original DQ_B0 (3 6) =30, OEN = 27
8760 12:29:36.702410 Original DQ_B1 (3 6) =30, OEN = 27
8761 12:29:36.705587 24, 0x0, End_B0=24 End_B1=24
8762 12:29:36.708906 25, 0x0, End_B0=25 End_B1=25
8763 12:29:36.708991 26, 0x0, End_B0=26 End_B1=26
8764 12:29:36.712336 27, 0x0, End_B0=27 End_B1=27
8765 12:29:36.715520 28, 0x0, End_B0=28 End_B1=28
8766 12:29:36.718465 29, 0x0, End_B0=29 End_B1=29
8767 12:29:36.718579 30, 0x0, End_B0=30 End_B1=30
8768 12:29:36.721899 31, 0x4141, End_B0=30 End_B1=30
8769 12:29:36.725396 Byte0 end_step=30 best_step=27
8770 12:29:36.728459 Byte1 end_step=30 best_step=27
8771 12:29:36.732101 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 12:29:36.735084 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 12:29:36.735182
8774 12:29:36.735273
8775 12:29:36.741863 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8776 12:29:36.745299 CH1 RK0: MR19=303, MR18=1927
8777 12:29:36.751633 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8778 12:29:36.751742
8779 12:29:36.755277 ----->DramcWriteLeveling(PI) begin...
8780 12:29:36.755379 ==
8781 12:29:36.758577 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 12:29:36.761800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 12:29:36.761902 ==
8784 12:29:36.765023 Write leveling (Byte 0): 23 => 23
8785 12:29:36.768334 Write leveling (Byte 1): 29 => 29
8786 12:29:36.771374 DramcWriteLeveling(PI) end<-----
8787 12:29:36.771450
8788 12:29:36.771534 ==
8789 12:29:36.774811 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 12:29:36.778441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 12:29:36.781391 ==
8792 12:29:36.781467 [Gating] SW mode calibration
8793 12:29:36.791295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 12:29:36.794683 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 12:29:36.798173 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 12:29:36.804262 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 12:29:36.807604 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8798 12:29:36.811011 1 4 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8799 12:29:36.817743 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 12:29:36.821164 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 12:29:36.824192 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 12:29:36.831017 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 12:29:36.833972 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 12:29:36.837488 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8805 12:29:36.844092 1 5 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 0)
8806 12:29:36.847125 1 5 12 | B1->B0 | 2323 3030 | 0 0 | (1 0) (0 1)
8807 12:29:36.850591 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8808 12:29:36.857038 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 12:29:36.860300 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 12:29:36.863983 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 12:29:36.870548 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 12:29:36.873818 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 12:29:36.877236 1 6 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8814 12:29:36.883729 1 6 12 | B1->B0 | 4646 3636 | 0 1 | (0 0) (1 1)
8815 12:29:36.887114 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 12:29:36.890203 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 12:29:36.896781 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 12:29:36.900204 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 12:29:36.903278 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 12:29:36.910308 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 12:29:36.913193 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8822 12:29:36.916542 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8823 12:29:36.923153 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:29:36.926554 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:29:36.929935 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:29:36.936436 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:29:36.939942 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:29:36.943402 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 12:29:36.949600 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 12:29:36.953088 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 12:29:36.956242 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 12:29:36.962643 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 12:29:36.966406 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 12:29:36.969582 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 12:29:36.976036 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 12:29:36.979199 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 12:29:36.982565 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8838 12:29:36.989520 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8839 12:29:36.992868 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8840 12:29:36.995903 Total UI for P1: 0, mck2ui 16
8841 12:29:36.999569 best dqsien dly found for B0: ( 1, 9, 10)
8842 12:29:37.002640 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 12:29:37.006078 Total UI for P1: 0, mck2ui 16
8844 12:29:37.009195 best dqsien dly found for B1: ( 1, 9, 12)
8845 12:29:37.012627 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8846 12:29:37.016062 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8847 12:29:37.016165
8848 12:29:37.022716 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8849 12:29:37.025573 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8850 12:29:37.028902 [Gating] SW calibration Done
8851 12:29:37.028988 ==
8852 12:29:37.032326 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 12:29:37.035641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 12:29:37.035731 ==
8855 12:29:37.035795 RX Vref Scan: 0
8856 12:29:37.035856
8857 12:29:37.038927 RX Vref 0 -> 0, step: 1
8858 12:29:37.039013
8859 12:29:37.042506 RX Delay 0 -> 252, step: 8
8860 12:29:37.045519 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8861 12:29:37.048944 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8862 12:29:37.055354 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8863 12:29:37.058790 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8864 12:29:37.062246 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8865 12:29:37.065243 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8866 12:29:37.068684 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8867 12:29:37.075189 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8868 12:29:37.078678 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8869 12:29:37.081881 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8870 12:29:37.085177 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8871 12:29:37.088550 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8872 12:29:37.095193 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8873 12:29:37.098264 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8874 12:29:37.101801 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8875 12:29:37.104865 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8876 12:29:37.104951 ==
8877 12:29:37.108431 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 12:29:37.115175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 12:29:37.115290 ==
8880 12:29:37.115389 DQS Delay:
8881 12:29:37.118006 DQS0 = 0, DQS1 = 0
8882 12:29:37.118092 DQM Delay:
8883 12:29:37.118161 DQM0 = 138, DQM1 = 130
8884 12:29:37.121424 DQ Delay:
8885 12:29:37.124706 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8886 12:29:37.128125 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8887 12:29:37.131488 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =127
8888 12:29:37.134844 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8889 12:29:37.134960
8890 12:29:37.135059
8891 12:29:37.135154 ==
8892 12:29:37.137871 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 12:29:37.144461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 12:29:37.144575 ==
8895 12:29:37.144676
8896 12:29:37.144774
8897 12:29:37.144844 TX Vref Scan disable
8898 12:29:37.147881 == TX Byte 0 ==
8899 12:29:37.151038 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8900 12:29:37.154719 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8901 12:29:37.157708 == TX Byte 1 ==
8902 12:29:37.160822 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8903 12:29:37.167780 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8904 12:29:37.167890 ==
8905 12:29:37.170778 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 12:29:37.174394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 12:29:37.174498 ==
8908 12:29:37.188182
8909 12:29:37.191299 TX Vref early break, caculate TX vref
8910 12:29:37.194469 TX Vref=16, minBit 9, minWin=23, winSum=387
8911 12:29:37.197988 TX Vref=18, minBit 9, minWin=22, winSum=395
8912 12:29:37.201585 TX Vref=20, minBit 13, minWin=23, winSum=396
8913 12:29:37.204555 TX Vref=22, minBit 9, minWin=24, winSum=406
8914 12:29:37.208175 TX Vref=24, minBit 9, minWin=25, winSum=418
8915 12:29:37.214672 TX Vref=26, minBit 13, minWin=24, winSum=421
8916 12:29:37.217649 TX Vref=28, minBit 10, minWin=24, winSum=422
8917 12:29:37.221125 TX Vref=30, minBit 9, minWin=25, winSum=419
8918 12:29:37.224461 TX Vref=32, minBit 0, minWin=25, winSum=408
8919 12:29:37.227918 TX Vref=34, minBit 10, minWin=24, winSum=404
8920 12:29:37.234496 TX Vref=36, minBit 10, minWin=23, winSum=392
8921 12:29:37.237341 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 30
8922 12:29:37.237453
8923 12:29:37.240889 Final TX Range 0 Vref 30
8924 12:29:37.240995
8925 12:29:37.241096 ==
8926 12:29:37.244232 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 12:29:37.247804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 12:29:37.250758 ==
8929 12:29:37.250861
8930 12:29:37.250975
8931 12:29:37.251068 TX Vref Scan disable
8932 12:29:37.257668 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8933 12:29:37.257780 == TX Byte 0 ==
8934 12:29:37.261140 u2DelayCellOfst[0]=16 cells (5 PI)
8935 12:29:37.264215 u2DelayCellOfst[1]=10 cells (3 PI)
8936 12:29:37.267637 u2DelayCellOfst[2]=0 cells (0 PI)
8937 12:29:37.271172 u2DelayCellOfst[3]=3 cells (1 PI)
8938 12:29:37.274138 u2DelayCellOfst[4]=6 cells (2 PI)
8939 12:29:37.277711 u2DelayCellOfst[5]=16 cells (5 PI)
8940 12:29:37.280693 u2DelayCellOfst[6]=16 cells (5 PI)
8941 12:29:37.284091 u2DelayCellOfst[7]=3 cells (1 PI)
8942 12:29:37.287308 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8943 12:29:37.290903 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8944 12:29:37.293804 == TX Byte 1 ==
8945 12:29:37.297293 u2DelayCellOfst[8]=0 cells (0 PI)
8946 12:29:37.300454 u2DelayCellOfst[9]=6 cells (2 PI)
8947 12:29:37.303922 u2DelayCellOfst[10]=13 cells (4 PI)
8948 12:29:37.307413 u2DelayCellOfst[11]=6 cells (2 PI)
8949 12:29:37.310450 u2DelayCellOfst[12]=16 cells (5 PI)
8950 12:29:37.313965 u2DelayCellOfst[13]=20 cells (6 PI)
8951 12:29:37.316903 u2DelayCellOfst[14]=20 cells (6 PI)
8952 12:29:37.316997 u2DelayCellOfst[15]=20 cells (6 PI)
8953 12:29:37.324072 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8954 12:29:37.326907 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8955 12:29:37.330303 DramC Write-DBI on
8956 12:29:37.330387 ==
8957 12:29:37.333643 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 12:29:37.337020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 12:29:37.337113 ==
8960 12:29:37.337192
8961 12:29:37.337256
8962 12:29:37.340248 TX Vref Scan disable
8963 12:29:37.340350 == TX Byte 0 ==
8964 12:29:37.346585 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8965 12:29:37.346693 == TX Byte 1 ==
8966 12:29:37.350047 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8967 12:29:37.353654 DramC Write-DBI off
8968 12:29:37.353730
8969 12:29:37.353794 [DATLAT]
8970 12:29:37.356662 Freq=1600, CH1 RK1
8971 12:29:37.356784
8972 12:29:37.356856 DATLAT Default: 0xf
8973 12:29:37.360079 0, 0xFFFF, sum = 0
8974 12:29:37.360195 1, 0xFFFF, sum = 0
8975 12:29:37.363385 2, 0xFFFF, sum = 0
8976 12:29:37.366847 3, 0xFFFF, sum = 0
8977 12:29:37.366936 4, 0xFFFF, sum = 0
8978 12:29:37.369693 5, 0xFFFF, sum = 0
8979 12:29:37.369781 6, 0xFFFF, sum = 0
8980 12:29:37.373305 7, 0xFFFF, sum = 0
8981 12:29:37.373396 8, 0xFFFF, sum = 0
8982 12:29:37.376284 9, 0xFFFF, sum = 0
8983 12:29:37.376399 10, 0xFFFF, sum = 0
8984 12:29:37.379654 11, 0xFFFF, sum = 0
8985 12:29:37.379762 12, 0xFFFF, sum = 0
8986 12:29:37.383237 13, 0xFFFF, sum = 0
8987 12:29:37.383312 14, 0x0, sum = 1
8988 12:29:37.386670 15, 0x0, sum = 2
8989 12:29:37.386743 16, 0x0, sum = 3
8990 12:29:37.389833 17, 0x0, sum = 4
8991 12:29:37.389920 best_step = 15
8992 12:29:37.389988
8993 12:29:37.390057 ==
8994 12:29:37.393092 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 12:29:37.399364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 12:29:37.399451 ==
8997 12:29:37.399557 RX Vref Scan: 0
8998 12:29:37.399654
8999 12:29:37.402740 RX Vref 0 -> 0, step: 1
9000 12:29:37.402816
9001 12:29:37.406093 RX Delay 11 -> 252, step: 4
9002 12:29:37.409433 iDelay=195, Bit 0, Center 138 (99 ~ 178) 80
9003 12:29:37.413021 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9004 12:29:37.415931 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
9005 12:29:37.422909 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9006 12:29:37.426007 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9007 12:29:37.429060 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9008 12:29:37.432434 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9009 12:29:37.435776 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9010 12:29:37.439302 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9011 12:29:37.445520 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9012 12:29:37.448945 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9013 12:29:37.452362 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9014 12:29:37.455853 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9015 12:29:37.461926 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9016 12:29:37.465255 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9017 12:29:37.469037 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9018 12:29:37.469113 ==
9019 12:29:37.472105 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 12:29:37.475761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 12:29:37.475861 ==
9022 12:29:37.478803 DQS Delay:
9023 12:29:37.478876 DQS0 = 0, DQS1 = 0
9024 12:29:37.481933 DQM Delay:
9025 12:29:37.482005 DQM0 = 134, DQM1 = 129
9026 12:29:37.482080 DQ Delay:
9027 12:29:37.488626 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9028 12:29:37.492143 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9029 12:29:37.495007 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9030 12:29:37.498395 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
9031 12:29:37.498469
9032 12:29:37.498565
9033 12:29:37.498653
9034 12:29:37.501758 [DramC_TX_OE_Calibration] TA2
9035 12:29:37.505339 Original DQ_B0 (3 6) =30, OEN = 27
9036 12:29:37.508724 Original DQ_B1 (3 6) =30, OEN = 27
9037 12:29:37.508854 24, 0x0, End_B0=24 End_B1=24
9038 12:29:37.512076 25, 0x0, End_B0=25 End_B1=25
9039 12:29:37.515383 26, 0x0, End_B0=26 End_B1=26
9040 12:29:37.518311 27, 0x0, End_B0=27 End_B1=27
9041 12:29:37.521872 28, 0x0, End_B0=28 End_B1=28
9042 12:29:37.521952 29, 0x0, End_B0=29 End_B1=29
9043 12:29:37.524908 30, 0x0, End_B0=30 End_B1=30
9044 12:29:37.528484 31, 0x5151, End_B0=30 End_B1=30
9045 12:29:37.531632 Byte0 end_step=30 best_step=27
9046 12:29:37.534640 Byte1 end_step=30 best_step=27
9047 12:29:37.538401 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 12:29:37.538520 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 12:29:37.538618
9050 12:29:37.541187
9051 12:29:37.547775 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9052 12:29:37.551288 CH1 RK1: MR19=303, MR18=1B05
9053 12:29:37.557738 CH1_RK1: MR19=0x303, MR18=0x1B05, DQSOSC=396, MR23=63, INC=23, DEC=15
9054 12:29:37.561336 [RxdqsGatingPostProcess] freq 1600
9055 12:29:37.564299 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 12:29:37.567703 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 12:29:37.570986 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 12:29:37.574165 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 12:29:37.577715 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 12:29:37.580745 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 12:29:37.584277 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 12:29:37.587664 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 12:29:37.590569 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 12:29:37.594059 Pre-setting of DQS Precalculation
9065 12:29:37.597481 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 12:29:37.603824 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 12:29:37.610825 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 12:29:37.613731
9069 12:29:37.613845
9070 12:29:37.613946 [Calibration Summary] 3200 Mbps
9071 12:29:37.617025 CH 0, Rank 0
9072 12:29:37.617137 SW Impedance : PASS
9073 12:29:37.620573 DUTY Scan : NO K
9074 12:29:37.623585 ZQ Calibration : PASS
9075 12:29:37.623697 Jitter Meter : NO K
9076 12:29:37.627227 CBT Training : PASS
9077 12:29:37.630279 Write leveling : PASS
9078 12:29:37.630403 RX DQS gating : PASS
9079 12:29:37.633702 RX DQ/DQS(RDDQC) : PASS
9080 12:29:37.636661 TX DQ/DQS : PASS
9081 12:29:37.636773 RX DATLAT : PASS
9082 12:29:37.640153 RX DQ/DQS(Engine): PASS
9083 12:29:37.643568 TX OE : PASS
9084 12:29:37.643680 All Pass.
9085 12:29:37.643793
9086 12:29:37.643894 CH 0, Rank 1
9087 12:29:37.646944 SW Impedance : PASS
9088 12:29:37.649919 DUTY Scan : NO K
9089 12:29:37.650028 ZQ Calibration : PASS
9090 12:29:37.653294 Jitter Meter : NO K
9091 12:29:37.656573 CBT Training : PASS
9092 12:29:37.656699 Write leveling : PASS
9093 12:29:37.660074 RX DQS gating : PASS
9094 12:29:37.663032 RX DQ/DQS(RDDQC) : PASS
9095 12:29:37.663142 TX DQ/DQS : PASS
9096 12:29:37.666526 RX DATLAT : PASS
9097 12:29:37.669578 RX DQ/DQS(Engine): PASS
9098 12:29:37.669664 TX OE : PASS
9099 12:29:37.673146 All Pass.
9100 12:29:37.673231
9101 12:29:37.673299 CH 1, Rank 0
9102 12:29:37.676605 SW Impedance : PASS
9103 12:29:37.676692 DUTY Scan : NO K
9104 12:29:37.679603 ZQ Calibration : PASS
9105 12:29:37.683001 Jitter Meter : NO K
9106 12:29:37.683087 CBT Training : PASS
9107 12:29:37.686333 Write leveling : PASS
9108 12:29:37.689403 RX DQS gating : PASS
9109 12:29:37.689488 RX DQ/DQS(RDDQC) : PASS
9110 12:29:37.692814 TX DQ/DQS : PASS
9111 12:29:37.696414 RX DATLAT : PASS
9112 12:29:37.696500 RX DQ/DQS(Engine): PASS
9113 12:29:37.699498 TX OE : PASS
9114 12:29:37.699585 All Pass.
9115 12:29:37.699653
9116 12:29:37.699715 CH 1, Rank 1
9117 12:29:37.702705 SW Impedance : PASS
9118 12:29:37.706178 DUTY Scan : NO K
9119 12:29:37.706293 ZQ Calibration : PASS
9120 12:29:37.709175 Jitter Meter : NO K
9121 12:29:37.713025 CBT Training : PASS
9122 12:29:37.713107 Write leveling : PASS
9123 12:29:37.716272 RX DQS gating : PASS
9124 12:29:37.719189 RX DQ/DQS(RDDQC) : PASS
9125 12:29:37.719296 TX DQ/DQS : PASS
9126 12:29:37.722528 RX DATLAT : PASS
9127 12:29:37.725737 RX DQ/DQS(Engine): PASS
9128 12:29:37.725845 TX OE : PASS
9129 12:29:37.729305 All Pass.
9130 12:29:37.729382
9131 12:29:37.729476 DramC Write-DBI on
9132 12:29:37.732240 PER_BANK_REFRESH: Hybrid Mode
9133 12:29:37.732342 TX_TRACKING: ON
9134 12:29:37.742204 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 12:29:37.752314 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 12:29:37.759071 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 12:29:37.762088 [FAST_K] Save calibration result to emmc
9138 12:29:37.764991 sync common calibartion params.
9139 12:29:37.765065 sync cbt_mode0:1, 1:1
9140 12:29:37.768569 dram_init: ddr_geometry: 2
9141 12:29:37.771672 dram_init: ddr_geometry: 2
9142 12:29:37.775214 dram_init: ddr_geometry: 2
9143 12:29:37.775300 0:dram_rank_size:100000000
9144 12:29:37.778532 1:dram_rank_size:100000000
9145 12:29:37.785071 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 12:29:37.785161 DFS_SHUFFLE_HW_MODE: ON
9147 12:29:37.791652 dramc_set_vcore_voltage set vcore to 725000
9148 12:29:37.791766 Read voltage for 1600, 0
9149 12:29:37.795149 Vio18 = 0
9150 12:29:37.795260 Vcore = 725000
9151 12:29:37.795357 Vdram = 0
9152 12:29:37.798221 Vddq = 0
9153 12:29:37.798322 Vmddr = 0
9154 12:29:37.801750 switch to 3200 Mbps bootup
9155 12:29:37.801823 [DramcRunTimeConfig]
9156 12:29:37.801885 PHYPLL
9157 12:29:37.805190 DPM_CONTROL_AFTERK: ON
9158 12:29:37.808087 PER_BANK_REFRESH: ON
9159 12:29:37.808166 REFRESH_OVERHEAD_REDUCTION: ON
9160 12:29:37.811640 CMD_PICG_NEW_MODE: OFF
9161 12:29:37.814691 XRTWTW_NEW_MODE: ON
9162 12:29:37.814763 XRTRTR_NEW_MODE: ON
9163 12:29:37.818159 TX_TRACKING: ON
9164 12:29:37.818252 RDSEL_TRACKING: OFF
9165 12:29:37.821426 DQS Precalculation for DVFS: ON
9166 12:29:37.821502 RX_TRACKING: OFF
9167 12:29:37.824520 HW_GATING DBG: ON
9168 12:29:37.824592 ZQCS_ENABLE_LP4: ON
9169 12:29:37.827922 RX_PICG_NEW_MODE: ON
9170 12:29:37.831277 TX_PICG_NEW_MODE: ON
9171 12:29:37.831378 ENABLE_RX_DCM_DPHY: ON
9172 12:29:37.834820 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 12:29:37.837906 DUMMY_READ_FOR_TRACKING: OFF
9174 12:29:37.841433 !!! SPM_CONTROL_AFTERK: OFF
9175 12:29:37.844470 !!! SPM could not control APHY
9176 12:29:37.844583 IMPEDANCE_TRACKING: ON
9177 12:29:37.848039 TEMP_SENSOR: ON
9178 12:29:37.848152 HW_SAVE_FOR_SR: OFF
9179 12:29:37.851299 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 12:29:37.854265 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 12:29:37.857735 Read ODT Tracking: ON
9182 12:29:37.857820 Refresh Rate DeBounce: ON
9183 12:29:37.861054 DFS_NO_QUEUE_FLUSH: ON
9184 12:29:37.864509 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 12:29:37.867645 ENABLE_DFS_RUNTIME_MRW: OFF
9186 12:29:37.871073 DDR_RESERVE_NEW_MODE: ON
9187 12:29:37.871159 MR_CBT_SWITCH_FREQ: ON
9188 12:29:37.874053 =========================
9189 12:29:37.892672 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 12:29:37.895752 dram_init: ddr_geometry: 2
9191 12:29:37.914078 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 12:29:37.917208 dram_init: dram init end (result: 0)
9193 12:29:37.924207 DRAM-K: Full calibration passed in 24519 msecs
9194 12:29:37.927021 MRC: failed to locate region type 0.
9195 12:29:37.927105 DRAM rank0 size:0x100000000,
9196 12:29:37.930486 DRAM rank1 size=0x100000000
9197 12:29:37.940246 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 12:29:37.947022 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 12:29:37.953540 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 12:29:37.963613 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 12:29:37.963701 DRAM rank0 size:0x100000000,
9202 12:29:37.967006 DRAM rank1 size=0x100000000
9203 12:29:37.967090 CBMEM:
9204 12:29:37.970081 IMD: root @ 0xfffff000 254 entries.
9205 12:29:37.973571 IMD: root @ 0xffffec00 62 entries.
9206 12:29:37.976455 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 12:29:37.983059 WARNING: RO_VPD is uninitialized or empty.
9208 12:29:37.986509 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 12:29:37.997454 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 12:29:38.007054 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9211 12:29:38.018386 BS: romstage times (exec / console): total (unknown) / 24017 ms
9212 12:29:38.018473
9213 12:29:38.018541
9214 12:29:38.027850 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 12:29:38.031238 ARM64: Exception handlers installed.
9216 12:29:38.034626 ARM64: Testing exception
9217 12:29:38.037939 ARM64: Done test exception
9218 12:29:38.038015 Enumerating buses...
9219 12:29:38.040970 Show all devs... Before device enumeration.
9220 12:29:38.044570 Root Device: enabled 1
9221 12:29:38.047578 CPU_CLUSTER: 0: enabled 1
9222 12:29:38.047688 CPU: 00: enabled 1
9223 12:29:38.051090 Compare with tree...
9224 12:29:38.051175 Root Device: enabled 1
9225 12:29:38.054627 CPU_CLUSTER: 0: enabled 1
9226 12:29:38.057651 CPU: 00: enabled 1
9227 12:29:38.057737 Root Device scanning...
9228 12:29:38.061195 scan_static_bus for Root Device
9229 12:29:38.064484 CPU_CLUSTER: 0 enabled
9230 12:29:38.067394 scan_static_bus for Root Device done
9231 12:29:38.070671 scan_bus: bus Root Device finished in 8 msecs
9232 12:29:38.070755 done
9233 12:29:38.077554 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 12:29:38.081029 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 12:29:38.087560 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 12:29:38.090878 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 12:29:38.094324 Allocating resources...
9238 12:29:38.097345 Reading resources...
9239 12:29:38.100530 Root Device read_resources bus 0 link: 0
9240 12:29:38.104062 DRAM rank0 size:0x100000000,
9241 12:29:38.104166 DRAM rank1 size=0x100000000
9242 12:29:38.110536 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 12:29:38.110618 CPU: 00 missing read_resources
9244 12:29:38.117248 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 12:29:38.120540 Root Device read_resources bus 0 link: 0 done
9246 12:29:38.123870 Done reading resources.
9247 12:29:38.127452 Show resources in subtree (Root Device)...After reading.
9248 12:29:38.130423 Root Device child on link 0 CPU_CLUSTER: 0
9249 12:29:38.134017 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 12:29:38.143692 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 12:29:38.143795 CPU: 00
9252 12:29:38.147054 Root Device assign_resources, bus 0 link: 0
9253 12:29:38.150312 CPU_CLUSTER: 0 missing set_resources
9254 12:29:38.156933 Root Device assign_resources, bus 0 link: 0 done
9255 12:29:38.157014 Done setting resources.
9256 12:29:38.163753 Show resources in subtree (Root Device)...After assigning values.
9257 12:29:38.167019 Root Device child on link 0 CPU_CLUSTER: 0
9258 12:29:38.169991 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 12:29:38.180116 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 12:29:38.180198 CPU: 00
9261 12:29:38.183404 Done allocating resources.
9262 12:29:38.189758 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 12:29:38.189845 Enabling resources...
9264 12:29:38.189916 done.
9265 12:29:38.196627 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 12:29:38.200030 Initializing devices...
9267 12:29:38.200109 Root Device init
9268 12:29:38.203110 init hardware done!
9269 12:29:38.203183 0x00000018: ctrlr->caps
9270 12:29:38.206201 52.000 MHz: ctrlr->f_max
9271 12:29:38.209771 0.400 MHz: ctrlr->f_min
9272 12:29:38.209861 0x40ff8080: ctrlr->voltages
9273 12:29:38.213323 sclk: 390625
9274 12:29:38.213418 Bus Width = 1
9275 12:29:38.213568 sclk: 390625
9276 12:29:38.216328 Bus Width = 1
9277 12:29:38.219774 Early init status = 3
9278 12:29:38.223248 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 12:29:38.226252 in-header: 03 fc 00 00 01 00 00 00
9280 12:29:38.229758 in-data: 00
9281 12:29:38.233220 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9282 12:29:38.237196 in-header: 03 fd 00 00 00 00 00 00
9283 12:29:38.240526 in-data:
9284 12:29:38.243825 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9285 12:29:38.247706 in-header: 03 fc 00 00 01 00 00 00
9286 12:29:38.251249 in-data: 00
9287 12:29:38.254582 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9288 12:29:38.259915 in-header: 03 fd 00 00 00 00 00 00
9289 12:29:38.263383 in-data:
9290 12:29:38.266728 [SSUSB] Setting up USB HOST controller...
9291 12:29:38.270185 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9292 12:29:38.273093 [SSUSB] phy power-on done.
9293 12:29:38.276389 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9294 12:29:38.283218 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9295 12:29:38.286198 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9296 12:29:38.292885 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9297 12:29:38.299376 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9298 12:29:38.306222 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9299 12:29:38.313026 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9300 12:29:38.319634 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9301 12:29:38.322649 SPM: binary array size = 0x9dc
9302 12:29:38.326140 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9303 12:29:38.332723 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9304 12:29:38.339176 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9305 12:29:38.346028 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9306 12:29:38.348861 configure_display: Starting display init
9307 12:29:38.382993 anx7625_power_on_init: Init interface.
9308 12:29:38.386451 anx7625_disable_pd_protocol: Disabled PD feature.
9309 12:29:38.389978 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9310 12:29:38.417672 anx7625_start_dp_work: Secure OCM version=00
9311 12:29:38.420657 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9312 12:29:38.435697 sp_tx_get_edid_block: EDID Block = 1
9313 12:29:38.538132 Extracted contents:
9314 12:29:38.541716 header: 00 ff ff ff ff ff ff 00
9315 12:29:38.544674 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9316 12:29:38.548218 version: 01 04
9317 12:29:38.551497 basic params: 95 1f 11 78 0a
9318 12:29:38.554474 chroma info: 76 90 94 55 54 90 27 21 50 54
9319 12:29:38.557863 established: 00 00 00
9320 12:29:38.564357 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9321 12:29:38.571103 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9322 12:29:38.574485 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 12:29:38.580837 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9324 12:29:38.587515 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9325 12:29:38.590794 extensions: 00
9326 12:29:38.590902 checksum: fb
9327 12:29:38.590998
9328 12:29:38.597761 Manufacturer: IVO Model 57d Serial Number 0
9329 12:29:38.597842 Made week 0 of 2020
9330 12:29:38.600863 EDID version: 1.4
9331 12:29:38.600964 Digital display
9332 12:29:38.603899 6 bits per primary color channel
9333 12:29:38.607477 DisplayPort interface
9334 12:29:38.607585 Maximum image size: 31 cm x 17 cm
9335 12:29:38.610869 Gamma: 220%
9336 12:29:38.610981 Check DPMS levels
9337 12:29:38.617241 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9338 12:29:38.620838 First detailed timing is preferred timing
9339 12:29:38.620949 Established timings supported:
9340 12:29:38.623881 Standard timings supported:
9341 12:29:38.627455 Detailed timings
9342 12:29:38.630476 Hex of detail: 383680a07038204018303c0035ae10000019
9343 12:29:38.637049 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9344 12:29:38.640538 0780 0798 07c8 0820 hborder 0
9345 12:29:38.643529 0438 043b 0447 0458 vborder 0
9346 12:29:38.647044 -hsync -vsync
9347 12:29:38.647146 Did detailed timing
9348 12:29:38.653904 Hex of detail: 000000000000000000000000000000000000
9349 12:29:38.656757 Manufacturer-specified data, tag 0
9350 12:29:38.660104 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9351 12:29:38.663599 ASCII string: InfoVision
9352 12:29:38.667130 Hex of detail: 000000fe00523134304e574635205248200a
9353 12:29:38.670143 ASCII string: R140NWF5 RH
9354 12:29:38.670229 Checksum
9355 12:29:38.673729 Checksum: 0xfb (valid)
9356 12:29:38.676601 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9357 12:29:38.679888 DSI data_rate: 832800000 bps
9358 12:29:38.686901 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9359 12:29:38.690095 anx7625_parse_edid: pixelclock(138800).
9360 12:29:38.693264 hactive(1920), hsync(48), hfp(24), hbp(88)
9361 12:29:38.696610 vactive(1080), vsync(12), vfp(3), vbp(17)
9362 12:29:38.700097 anx7625_dsi_config: config dsi.
9363 12:29:38.706250 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9364 12:29:38.720076 anx7625_dsi_config: success to config DSI
9365 12:29:38.723151 anx7625_dp_start: MIPI phy setup OK.
9366 12:29:38.726757 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9367 12:29:38.729772 mtk_ddp_mode_set invalid vrefresh 60
9368 12:29:38.733345 main_disp_path_setup
9369 12:29:38.733418 ovl_layer_smi_id_en
9370 12:29:38.736864 ovl_layer_smi_id_en
9371 12:29:38.736936 ccorr_config
9372 12:29:38.737012 aal_config
9373 12:29:38.740030 gamma_config
9374 12:29:38.740107 postmask_config
9375 12:29:38.743061 dither_config
9376 12:29:38.746331 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9377 12:29:38.753412 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9378 12:29:38.756403 Root Device init finished in 553 msecs
9379 12:29:38.759884 CPU_CLUSTER: 0 init
9380 12:29:38.766310 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9381 12:29:38.772757 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9382 12:29:38.772873 APU_MBOX 0x190000b0 = 0x10001
9383 12:29:38.776364 APU_MBOX 0x190001b0 = 0x10001
9384 12:29:38.779364 APU_MBOX 0x190005b0 = 0x10001
9385 12:29:38.782791 APU_MBOX 0x190006b0 = 0x10001
9386 12:29:38.789275 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9387 12:29:38.799052 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9388 12:29:38.811686 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9389 12:29:38.818070 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9390 12:29:38.829878 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9391 12:29:38.838845 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9392 12:29:38.842450 CPU_CLUSTER: 0 init finished in 81 msecs
9393 12:29:38.845551 Devices initialized
9394 12:29:38.848878 Show all devs... After init.
9395 12:29:38.848987 Root Device: enabled 1
9396 12:29:38.852407 CPU_CLUSTER: 0: enabled 1
9397 12:29:38.855413 CPU: 00: enabled 1
9398 12:29:38.859022 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9399 12:29:38.862400 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9400 12:29:38.865303 ELOG: NV offset 0x57f000 size 0x1000
9401 12:29:38.872199 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9402 12:29:38.878642 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9403 12:29:38.882146 ELOG: Event(17) added with size 13 at 2023-06-06 12:29:36 UTC
9404 12:29:38.888556 out: cmd=0x121: 03 db 21 01 00 00 00 00
9405 12:29:38.891733 in-header: 03 1c 00 00 2c 00 00 00
9406 12:29:38.901809 in-data: 43 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 12:29:38.908335 ELOG: Event(A1) added with size 10 at 2023-06-06 12:29:36 UTC
9408 12:29:38.914699 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9409 12:29:38.921596 ELOG: Event(A0) added with size 9 at 2023-06-06 12:29:36 UTC
9410 12:29:38.924561 elog_add_boot_reason: Logged dev mode boot
9411 12:29:38.931448 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9412 12:29:38.931538 Finalize devices...
9413 12:29:38.934519 Devices finalized
9414 12:29:38.938058 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9415 12:29:38.941553 Writing coreboot table at 0xffe64000
9416 12:29:38.944647 0. 000000000010a000-0000000000113fff: RAMSTAGE
9417 12:29:38.951009 1. 0000000040000000-00000000400fffff: RAM
9418 12:29:38.954291 2. 0000000040100000-000000004032afff: RAMSTAGE
9419 12:29:38.957752 3. 000000004032b000-00000000545fffff: RAM
9420 12:29:38.961346 4. 0000000054600000-000000005465ffff: BL31
9421 12:29:38.964349 5. 0000000054660000-00000000ffe63fff: RAM
9422 12:29:38.970984 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9423 12:29:38.974364 7. 0000000100000000-000000023fffffff: RAM
9424 12:29:38.977399 Passing 5 GPIOs to payload:
9425 12:29:38.980821 NAME | PORT | POLARITY | VALUE
9426 12:29:38.987344 EC in RW | 0x000000aa | low | undefined
9427 12:29:38.990897 EC interrupt | 0x00000005 | low | undefined
9428 12:29:38.994193 TPM interrupt | 0x000000ab | high | undefined
9429 12:29:39.000755 SD card detect | 0x00000011 | high | undefined
9430 12:29:39.003720 speaker enable | 0x00000093 | high | undefined
9431 12:29:39.007163 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9432 12:29:39.010561 in-header: 03 f9 00 00 02 00 00 00
9433 12:29:39.013881 in-data: 02 00
9434 12:29:39.017194 ADC[4]: Raw value=901032 ID=7
9435 12:29:39.020190 ADC[3]: Raw value=213179 ID=1
9436 12:29:39.020306 RAM Code: 0x71
9437 12:29:39.023568 ADC[6]: Raw value=74502 ID=0
9438 12:29:39.027229 ADC[5]: Raw value=212072 ID=1
9439 12:29:39.027313 SKU Code: 0x1
9440 12:29:39.033401 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9441 12:29:39.033504 coreboot table: 964 bytes.
9442 12:29:39.036951 IMD ROOT 0. 0xfffff000 0x00001000
9443 12:29:39.040034 IMD SMALL 1. 0xffffe000 0x00001000
9444 12:29:39.043205 RO MCACHE 2. 0xffffc000 0x00001104
9445 12:29:39.046760 CONSOLE 3. 0xfff7c000 0x00080000
9446 12:29:39.049810 FMAP 4. 0xfff7b000 0x00000452
9447 12:29:39.053479 TIME STAMP 5. 0xfff7a000 0x00000910
9448 12:29:39.056444 VBOOT WORK 6. 0xfff66000 0x00014000
9449 12:29:39.060329 RAMOOPS 7. 0xffe66000 0x00100000
9450 12:29:39.063437 COREBOOT 8. 0xffe64000 0x00002000
9451 12:29:39.066574 IMD small region:
9452 12:29:39.069904 IMD ROOT 0. 0xffffec00 0x00000400
9453 12:29:39.073433 VPD 1. 0xffffeba0 0x0000004c
9454 12:29:39.076408 MMC STATUS 2. 0xffffeb80 0x00000004
9455 12:29:39.082996 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9456 12:29:39.083084 Probing TPM: done!
9457 12:29:39.090139 Connected to device vid:did:rid of 1ae0:0028:00
9458 12:29:39.096563 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9459 12:29:39.100089 Initialized TPM device CR50 revision 0
9460 12:29:39.103027 Checking cr50 for pending updates
9461 12:29:39.108852 Reading cr50 TPM mode
9462 12:29:39.117411 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9463 12:29:39.123497 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9464 12:29:39.164027 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9465 12:29:39.167048 Checking segment from ROM address 0x40100000
9466 12:29:39.170587 Checking segment from ROM address 0x4010001c
9467 12:29:39.177437 Loading segment from ROM address 0x40100000
9468 12:29:39.177543 code (compression=0)
9469 12:29:39.187054 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9470 12:29:39.194147 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9471 12:29:39.194296 it's not compressed!
9472 12:29:39.200661 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9473 12:29:39.206916 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9474 12:29:39.224416 Loading segment from ROM address 0x4010001c
9475 12:29:39.224553 Entry Point 0x80000000
9476 12:29:39.227772 Loaded segments
9477 12:29:39.231086 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9478 12:29:39.237771 Jumping to boot code at 0x80000000(0xffe64000)
9479 12:29:39.244130 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9480 12:29:39.250688 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9481 12:29:39.258857 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9482 12:29:39.261919 Checking segment from ROM address 0x40100000
9483 12:29:39.265355 Checking segment from ROM address 0x4010001c
9484 12:29:39.272191 Loading segment from ROM address 0x40100000
9485 12:29:39.272364 code (compression=1)
9486 12:29:39.278736 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9487 12:29:39.288661 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9488 12:29:39.288808 using LZMA
9489 12:29:39.297173 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9490 12:29:39.303517 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9491 12:29:39.306853 Loading segment from ROM address 0x4010001c
9492 12:29:39.306937 Entry Point 0x54601000
9493 12:29:39.310202 Loaded segments
9494 12:29:39.313539 NOTICE: MT8192 bl31_setup
9495 12:29:39.320695 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9496 12:29:39.324199 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9497 12:29:39.327628 WARNING: region 0:
9498 12:29:39.330888 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 12:29:39.331004 WARNING: region 1:
9500 12:29:39.337318 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9501 12:29:39.340634 WARNING: region 2:
9502 12:29:39.344004 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9503 12:29:39.347520 WARNING: region 3:
9504 12:29:39.350624 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 12:29:39.354176 WARNING: region 4:
9506 12:29:39.360642 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 12:29:39.360756 WARNING: region 5:
9508 12:29:39.363758 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 12:29:39.367217 WARNING: region 6:
9510 12:29:39.370624 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 12:29:39.373726 WARNING: region 7:
9512 12:29:39.377276 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 12:29:39.383763 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9514 12:29:39.387152 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9515 12:29:39.390189 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9516 12:29:39.397111 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9517 12:29:39.400106 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9518 12:29:39.406999 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9519 12:29:39.410558 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9520 12:29:39.413375 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9521 12:29:39.420108 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9522 12:29:39.423518 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9523 12:29:39.427075 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9524 12:29:39.433327 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9525 12:29:39.436907 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9526 12:29:39.443448 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9527 12:29:39.446625 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9528 12:29:39.449939 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9529 12:29:39.456461 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9530 12:29:39.460151 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9531 12:29:39.466585 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9532 12:29:39.469631 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9533 12:29:39.473005 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9534 12:29:39.479798 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9535 12:29:39.483241 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9536 12:29:39.486718 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9537 12:29:39.493104 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9538 12:29:39.496497 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9539 12:29:39.503064 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9540 12:29:39.506503 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9541 12:29:39.510056 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9542 12:29:39.516552 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9543 12:29:39.519440 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9544 12:29:39.526165 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9545 12:29:39.529608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9546 12:29:39.533237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9547 12:29:39.536452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9548 12:29:39.542818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9549 12:29:39.546498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9550 12:29:39.549832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9551 12:29:39.553200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9552 12:29:39.559593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9553 12:29:39.563169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9554 12:29:39.566138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9555 12:29:39.569622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9556 12:29:39.576107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9557 12:29:39.579540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9558 12:29:39.582574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9559 12:29:39.586121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9560 12:29:39.592570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9561 12:29:39.595860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9562 12:29:39.602775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9563 12:29:39.605833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9564 12:29:39.609291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9565 12:29:39.615874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9566 12:29:39.619284 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9567 12:29:39.625604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9568 12:29:39.628938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9569 12:29:39.635705 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9570 12:29:39.639174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9571 12:29:39.642448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9572 12:29:39.649029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9573 12:29:39.652541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9574 12:29:39.658795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9575 12:29:39.662488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9576 12:29:39.669123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9577 12:29:39.672117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9578 12:29:39.679090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9579 12:29:39.682423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9580 12:29:39.685452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9581 12:29:39.692202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9582 12:29:39.695665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9583 12:29:39.702232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9584 12:29:39.705229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9585 12:29:39.711687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9586 12:29:39.715231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9587 12:29:39.721731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9588 12:29:39.725183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9589 12:29:39.728468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9590 12:29:39.735115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9591 12:29:39.738040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9592 12:29:39.745012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9593 12:29:39.747936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9594 12:29:39.755081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9595 12:29:39.758000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9596 12:29:39.764737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9597 12:29:39.768121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9598 12:29:39.771553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9599 12:29:39.778018 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9600 12:29:39.781562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9601 12:29:39.788394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9602 12:29:39.791289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9603 12:29:39.797853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9604 12:29:39.801401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9605 12:29:39.808196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9606 12:29:39.811172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9607 12:29:39.814732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9608 12:29:39.821295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9609 12:29:39.824344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9610 12:29:39.827634 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9611 12:29:39.834451 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9612 12:29:39.837879 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9613 12:29:39.841190 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9614 12:29:39.847602 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9615 12:29:39.850935 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9616 12:29:39.854427 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9617 12:29:39.860912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9618 12:29:39.864015 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9619 12:29:39.870735 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9620 12:29:39.874168 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9621 12:29:39.877516 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9622 12:29:39.883984 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9623 12:29:39.887504 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9624 12:29:39.894408 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9625 12:29:39.897562 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9626 12:29:39.900979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9627 12:29:39.907411 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9628 12:29:39.910803 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9629 12:29:39.914193 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9630 12:29:39.920666 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9631 12:29:39.924286 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9632 12:29:39.927389 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9633 12:29:39.930782 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9634 12:29:39.937455 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9635 12:29:39.940990 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9636 12:29:39.944232 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9637 12:29:39.950690 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9638 12:29:39.954114 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9639 12:29:39.957151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9640 12:29:39.964164 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9641 12:29:39.967142 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9642 12:29:39.973828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9643 12:29:39.977489 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9644 12:29:39.980793 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9645 12:29:39.987285 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9646 12:29:39.990246 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9647 12:29:39.996895 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9648 12:29:40.000476 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9649 12:29:40.003575 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9650 12:29:40.010087 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9651 12:29:40.013836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9652 12:29:40.020286 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9653 12:29:40.023754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9654 12:29:40.026846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9655 12:29:40.033294 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9656 12:29:40.036608 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9657 12:29:40.043268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9658 12:29:40.046658 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9659 12:29:40.050201 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9660 12:29:40.056507 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9661 12:29:40.059927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9662 12:29:40.066560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9663 12:29:40.070080 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9664 12:29:40.073204 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9665 12:29:40.080228 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9666 12:29:40.083045 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9667 12:29:40.086734 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9668 12:29:40.093556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9669 12:29:40.096552 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9670 12:29:40.103253 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9671 12:29:40.106353 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9672 12:29:40.109891 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9673 12:29:40.116352 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9674 12:29:40.119827 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9675 12:29:40.126458 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9676 12:29:40.129496 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9677 12:29:40.132960 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9678 12:29:40.139328 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9679 12:29:40.142307 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9680 12:29:40.149061 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9681 12:29:40.152338 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9682 12:29:40.155904 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9683 12:29:40.162300 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9684 12:29:40.165863 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9685 12:29:40.172359 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9686 12:29:40.175389 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9687 12:29:40.178959 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9688 12:29:40.185499 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9689 12:29:40.188396 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9690 12:29:40.195122 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9691 12:29:40.198691 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9692 12:29:40.201618 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9693 12:29:40.208079 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9694 12:29:40.211618 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9695 12:29:40.218116 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9696 12:29:40.221398 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9697 12:29:40.227831 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9698 12:29:40.231412 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9699 12:29:40.234439 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9700 12:29:40.240950 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9701 12:29:40.244406 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9702 12:29:40.250680 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9703 12:29:40.254500 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9704 12:29:40.260659 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9705 12:29:40.264255 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9706 12:29:40.267658 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9707 12:29:40.274265 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9708 12:29:40.277691 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9709 12:29:40.284082 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9710 12:29:40.287143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9711 12:29:40.290679 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9712 12:29:40.297232 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9713 12:29:40.300586 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9714 12:29:40.307086 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9715 12:29:40.310592 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9716 12:29:40.317172 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9717 12:29:40.320108 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9718 12:29:40.323828 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9719 12:29:40.330187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9720 12:29:40.333754 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9721 12:29:40.340323 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9722 12:29:40.343287 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9723 12:29:40.350267 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9724 12:29:40.353168 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9725 12:29:40.356897 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9726 12:29:40.363221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9727 12:29:40.366753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9728 12:29:40.373253 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9729 12:29:40.376736 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9730 12:29:40.383197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9731 12:29:40.386195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9732 12:29:40.389723 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9733 12:29:40.396264 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9734 12:29:40.399587 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9735 12:29:40.406144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9736 12:29:40.409304 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9737 12:29:40.416228 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9738 12:29:40.419279 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9739 12:29:40.422685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9740 12:29:40.429105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9741 12:29:40.432542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9742 12:29:40.435533 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9743 12:29:40.442337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9744 12:29:40.445770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9745 12:29:40.448722 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9746 12:29:40.452096 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9747 12:29:40.458909 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9748 12:29:40.462472 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9749 12:29:40.468681 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9750 12:29:40.471723 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9751 12:29:40.475126 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9752 12:29:40.481941 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9753 12:29:40.484968 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9754 12:29:40.488435 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9755 12:29:40.495003 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9756 12:29:40.498561 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9757 12:29:40.501620 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9758 12:29:40.508265 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9759 12:29:40.512084 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9760 12:29:40.518261 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9761 12:29:40.521652 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9762 12:29:40.525115 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9763 12:29:40.531459 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9764 12:29:40.534890 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9765 12:29:40.541351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9766 12:29:40.544833 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9767 12:29:40.547896 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9768 12:29:40.554485 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9769 12:29:40.557902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9770 12:29:40.561275 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9771 12:29:40.567831 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9772 12:29:40.570696 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9773 12:29:40.577579 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9774 12:29:40.581083 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9775 12:29:40.584089 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9776 12:29:40.590607 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9777 12:29:40.594138 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9778 12:29:40.597230 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9779 12:29:40.603695 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9780 12:29:40.607143 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9781 12:29:40.610655 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9782 12:29:40.617132 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9783 12:29:40.620370 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9784 12:29:40.623834 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9785 12:29:40.627240 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9786 12:29:40.630238 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9787 12:29:40.636727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9788 12:29:40.640429 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9789 12:29:40.643487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9790 12:29:40.650459 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9791 12:29:40.653487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9792 12:29:40.656886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9793 12:29:40.663340 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9794 12:29:40.666671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9795 12:29:40.670023 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9796 12:29:40.676815 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9797 12:29:40.679796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9798 12:29:40.683093 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9799 12:29:40.690146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9800 12:29:40.693126 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9801 12:29:40.699975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9802 12:29:40.703100 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9803 12:29:40.706576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9804 12:29:40.713179 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9805 12:29:40.716167 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9806 12:29:40.723203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9807 12:29:40.726452 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9808 12:29:40.732727 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9809 12:29:40.736128 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9810 12:29:40.739599 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9811 12:29:40.746101 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9812 12:29:40.749691 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9813 12:29:40.756179 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9814 12:29:40.759253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9815 12:29:40.762714 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9816 12:29:40.769379 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9817 12:29:40.772723 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9818 12:29:40.779499 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9819 12:29:40.782440 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9820 12:29:40.785750 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9821 12:29:40.792710 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9822 12:29:40.795742 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9823 12:29:40.802294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9824 12:29:40.805410 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9825 12:29:40.812002 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9826 12:29:40.815445 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9827 12:29:40.818938 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9828 12:29:40.825342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9829 12:29:40.829004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9830 12:29:40.835381 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9831 12:29:40.838879 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9832 12:29:40.845416 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9833 12:29:40.848794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9834 12:29:40.851782 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9835 12:29:40.858605 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9836 12:29:40.861703 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9837 12:29:40.868306 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9838 12:29:40.871660 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9839 12:29:40.875045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9840 12:29:40.881421 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9841 12:29:40.884734 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9842 12:29:40.891296 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9843 12:29:40.894780 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9844 12:29:40.901245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9845 12:29:40.904653 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9846 12:29:40.907662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9847 12:29:40.914208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9848 12:29:40.917778 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9849 12:29:40.924255 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9850 12:29:40.927708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9851 12:29:40.930651 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9852 12:29:40.937302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9853 12:29:40.940548 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9854 12:29:40.947339 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9855 12:29:40.950753 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9856 12:29:40.957182 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9857 12:29:40.960635 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9858 12:29:40.963608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9859 12:29:40.970521 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9860 12:29:40.973929 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9861 12:29:40.980168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9862 12:29:40.983644 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9863 12:29:40.990318 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9864 12:29:40.993316 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9865 12:29:40.996700 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9866 12:29:41.003304 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9867 12:29:41.006278 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9868 12:29:41.013375 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9869 12:29:41.016311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9870 12:29:41.022898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9871 12:29:41.026538 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9872 12:29:41.033013 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9873 12:29:41.036123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9874 12:29:41.039550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9875 12:29:41.045889 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9876 12:29:41.049255 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9877 12:29:41.056301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9878 12:29:41.059332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9879 12:29:41.065994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9880 12:29:41.068934 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9881 12:29:41.075776 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9882 12:29:41.079153 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9883 12:29:41.082545 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9884 12:29:41.088889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9885 12:29:41.092207 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9886 12:29:41.098867 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9887 12:29:41.102506 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9888 12:29:41.109018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9889 12:29:41.111951 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9890 12:29:41.115513 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9891 12:29:41.122162 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9892 12:29:41.125203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9893 12:29:41.132183 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9894 12:29:41.135169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9895 12:29:41.142167 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9896 12:29:41.145069 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9897 12:29:41.151828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9898 12:29:41.155129 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9899 12:29:41.158194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9900 12:29:41.164953 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9901 12:29:41.168526 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9902 12:29:41.175112 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9903 12:29:41.178041 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9904 12:29:41.184790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9905 12:29:41.188220 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9906 12:29:41.191634 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9907 12:29:41.198016 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9908 12:29:41.201486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9909 12:29:41.207827 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9910 12:29:41.211402 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9911 12:29:41.217879 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9912 12:29:41.221376 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9913 12:29:41.227994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9914 12:29:41.230963 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9915 12:29:41.234549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9916 12:29:41.241081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9917 12:29:41.244122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9918 12:29:41.251087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9919 12:29:41.254026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9920 12:29:41.260772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9921 12:29:41.264080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9922 12:29:41.270400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9923 12:29:41.273903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9924 12:29:41.280443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9925 12:29:41.283968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9926 12:29:41.290264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9927 12:29:41.293613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9928 12:29:41.300550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9929 12:29:41.303478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9930 12:29:41.310445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9931 12:29:41.313620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9932 12:29:41.320225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9933 12:29:41.323240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9934 12:29:41.329879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9935 12:29:41.333433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9936 12:29:41.339623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9937 12:29:41.343082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9938 12:29:41.349501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9939 12:29:41.353111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9940 12:29:41.359448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9941 12:29:41.363014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9942 12:29:41.369685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9943 12:29:41.373026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9944 12:29:41.379451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9945 12:29:41.383021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9946 12:29:41.389541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9947 12:29:41.392769 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9948 12:29:41.395807 INFO: [APUAPC] vio 0
9949 12:29:41.399212 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9950 12:29:41.405968 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9951 12:29:41.408954 INFO: [APUAPC] D0_APC_0: 0x400510
9952 12:29:41.409034 INFO: [APUAPC] D0_APC_1: 0x0
9953 12:29:41.412302 INFO: [APUAPC] D0_APC_2: 0x1540
9954 12:29:41.415770 INFO: [APUAPC] D0_APC_3: 0x0
9955 12:29:41.418754 INFO: [APUAPC] D1_APC_0: 0xffffffff
9956 12:29:41.422324 INFO: [APUAPC] D1_APC_1: 0xffffffff
9957 12:29:41.425345 INFO: [APUAPC] D1_APC_2: 0x3fffff
9958 12:29:41.428902 INFO: [APUAPC] D1_APC_3: 0x0
9959 12:29:41.431988 INFO: [APUAPC] D2_APC_0: 0xffffffff
9960 12:29:41.435585 INFO: [APUAPC] D2_APC_1: 0xffffffff
9961 12:29:41.438712 INFO: [APUAPC] D2_APC_2: 0x3fffff
9962 12:29:41.442156 INFO: [APUAPC] D2_APC_3: 0x0
9963 12:29:41.445106 INFO: [APUAPC] D3_APC_0: 0xffffffff
9964 12:29:41.448428 INFO: [APUAPC] D3_APC_1: 0xffffffff
9965 12:29:41.451930 INFO: [APUAPC] D3_APC_2: 0x3fffff
9966 12:29:41.455007 INFO: [APUAPC] D3_APC_3: 0x0
9967 12:29:41.458533 INFO: [APUAPC] D4_APC_0: 0xffffffff
9968 12:29:41.461728 INFO: [APUAPC] D4_APC_1: 0xffffffff
9969 12:29:41.465164 INFO: [APUAPC] D4_APC_2: 0x3fffff
9970 12:29:41.468500 INFO: [APUAPC] D4_APC_3: 0x0
9971 12:29:41.471881 INFO: [APUAPC] D5_APC_0: 0xffffffff
9972 12:29:41.475260 INFO: [APUAPC] D5_APC_1: 0xffffffff
9973 12:29:41.478428 INFO: [APUAPC] D5_APC_2: 0x3fffff
9974 12:29:41.481455 INFO: [APUAPC] D5_APC_3: 0x0
9975 12:29:41.485046 INFO: [APUAPC] D6_APC_0: 0xffffffff
9976 12:29:41.488127 INFO: [APUAPC] D6_APC_1: 0xffffffff
9977 12:29:41.491586 INFO: [APUAPC] D6_APC_2: 0x3fffff
9978 12:29:41.494951 INFO: [APUAPC] D6_APC_3: 0x0
9979 12:29:41.497868 INFO: [APUAPC] D7_APC_0: 0xffffffff
9980 12:29:41.501241 INFO: [APUAPC] D7_APC_1: 0xffffffff
9981 12:29:41.504778 INFO: [APUAPC] D7_APC_2: 0x3fffff
9982 12:29:41.508230 INFO: [APUAPC] D7_APC_3: 0x0
9983 12:29:41.511280 INFO: [APUAPC] D8_APC_0: 0xffffffff
9984 12:29:41.514662 INFO: [APUAPC] D8_APC_1: 0xffffffff
9985 12:29:41.518049 INFO: [APUAPC] D8_APC_2: 0x3fffff
9986 12:29:41.521037 INFO: [APUAPC] D8_APC_3: 0x0
9987 12:29:41.524558 INFO: [APUAPC] D9_APC_0: 0xffffffff
9988 12:29:41.527873 INFO: [APUAPC] D9_APC_1: 0xffffffff
9989 12:29:41.531101 INFO: [APUAPC] D9_APC_2: 0x3fffff
9990 12:29:41.534544 INFO: [APUAPC] D9_APC_3: 0x0
9991 12:29:41.537556 INFO: [APUAPC] D10_APC_0: 0xffffffff
9992 12:29:41.541144 INFO: [APUAPC] D10_APC_1: 0xffffffff
9993 12:29:41.544260 INFO: [APUAPC] D10_APC_2: 0x3fffff
9994 12:29:41.547660 INFO: [APUAPC] D10_APC_3: 0x0
9995 12:29:41.551232 INFO: [APUAPC] D11_APC_0: 0xffffffff
9996 12:29:41.554107 INFO: [APUAPC] D11_APC_1: 0xffffffff
9997 12:29:41.557773 INFO: [APUAPC] D11_APC_2: 0x3fffff
9998 12:29:41.560721 INFO: [APUAPC] D11_APC_3: 0x0
9999 12:29:41.564173 INFO: [APUAPC] D12_APC_0: 0xffffffff
10000 12:29:41.567688 INFO: [APUAPC] D12_APC_1: 0xffffffff
10001 12:29:41.570728 INFO: [APUAPC] D12_APC_2: 0x3fffff
10002 12:29:41.574195 INFO: [APUAPC] D12_APC_3: 0x0
10003 12:29:41.577640 INFO: [APUAPC] D13_APC_0: 0xffffffff
10004 12:29:41.580892 INFO: [APUAPC] D13_APC_1: 0xffffffff
10005 12:29:41.584250 INFO: [APUAPC] D13_APC_2: 0x3fffff
10006 12:29:41.587733 INFO: [APUAPC] D13_APC_3: 0x0
10007 12:29:41.590770 INFO: [APUAPC] D14_APC_0: 0xffffffff
10008 12:29:41.594253 INFO: [APUAPC] D14_APC_1: 0xffffffff
10009 12:29:41.597531 INFO: [APUAPC] D14_APC_2: 0x3fffff
10010 12:29:41.600449 INFO: [APUAPC] D14_APC_3: 0x0
10011 12:29:41.603836 INFO: [APUAPC] D15_APC_0: 0xffffffff
10012 12:29:41.607261 INFO: [APUAPC] D15_APC_1: 0xffffffff
10013 12:29:41.610749 INFO: [APUAPC] D15_APC_2: 0x3fffff
10014 12:29:41.614028 INFO: [APUAPC] D15_APC_3: 0x0
10015 12:29:41.616961 INFO: [APUAPC] APC_CON: 0x4
10016 12:29:41.620353 INFO: [NOCDAPC] D0_APC_0: 0x0
10017 12:29:41.623773 INFO: [NOCDAPC] D0_APC_1: 0x0
10018 12:29:41.623858 INFO: [NOCDAPC] D1_APC_0: 0x0
10019 12:29:41.626836 INFO: [NOCDAPC] D1_APC_1: 0xfff
10020 12:29:41.630465 INFO: [NOCDAPC] D2_APC_0: 0x0
10021 12:29:41.633444 INFO: [NOCDAPC] D2_APC_1: 0xfff
10022 12:29:41.637102 INFO: [NOCDAPC] D3_APC_0: 0x0
10023 12:29:41.640051 INFO: [NOCDAPC] D3_APC_1: 0xfff
10024 12:29:41.643674 INFO: [NOCDAPC] D4_APC_0: 0x0
10025 12:29:41.646768 INFO: [NOCDAPC] D4_APC_1: 0xfff
10026 12:29:41.650212 INFO: [NOCDAPC] D5_APC_0: 0x0
10027 12:29:41.653285 INFO: [NOCDAPC] D5_APC_1: 0xfff
10028 12:29:41.656692 INFO: [NOCDAPC] D6_APC_0: 0x0
10029 12:29:41.660078 INFO: [NOCDAPC] D6_APC_1: 0xfff
10030 12:29:41.660162 INFO: [NOCDAPC] D7_APC_0: 0x0
10031 12:29:41.663152 INFO: [NOCDAPC] D7_APC_1: 0xfff
10032 12:29:41.666737 INFO: [NOCDAPC] D8_APC_0: 0x0
10033 12:29:41.670135 INFO: [NOCDAPC] D8_APC_1: 0xfff
10034 12:29:41.673070 INFO: [NOCDAPC] D9_APC_0: 0x0
10035 12:29:41.676534 INFO: [NOCDAPC] D9_APC_1: 0xfff
10036 12:29:41.679570 INFO: [NOCDAPC] D10_APC_0: 0x0
10037 12:29:41.683119 INFO: [NOCDAPC] D10_APC_1: 0xfff
10038 12:29:41.686365 INFO: [NOCDAPC] D11_APC_0: 0x0
10039 12:29:41.689568 INFO: [NOCDAPC] D11_APC_1: 0xfff
10040 12:29:41.692900 INFO: [NOCDAPC] D12_APC_0: 0x0
10041 12:29:41.696416 INFO: [NOCDAPC] D12_APC_1: 0xfff
10042 12:29:41.699759 INFO: [NOCDAPC] D13_APC_0: 0x0
10043 12:29:41.699843 INFO: [NOCDAPC] D13_APC_1: 0xfff
10044 12:29:41.703145 INFO: [NOCDAPC] D14_APC_0: 0x0
10045 12:29:41.706459 INFO: [NOCDAPC] D14_APC_1: 0xfff
10046 12:29:41.709827 INFO: [NOCDAPC] D15_APC_0: 0x0
10047 12:29:41.712725 INFO: [NOCDAPC] D15_APC_1: 0xfff
10048 12:29:41.716165 INFO: [NOCDAPC] APC_CON: 0x4
10049 12:29:41.719479 INFO: [APUAPC] set_apusys_apc done
10050 12:29:41.722864 INFO: [DEVAPC] devapc_init done
10051 12:29:41.726298 INFO: GICv3 without legacy support detected.
10052 12:29:41.733020 INFO: ARM GICv3 driver initialized in EL3
10053 12:29:41.736035 INFO: Maximum SPI INTID supported: 639
10054 12:29:41.739598 INFO: BL31: Initializing runtime services
10055 12:29:41.746013 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10056 12:29:41.746101 INFO: SPM: enable CPC mode
10057 12:29:41.752743 INFO: mcdi ready for mcusys-off-idle and system suspend
10058 12:29:41.755710 INFO: BL31: Preparing for EL3 exit to normal world
10059 12:29:41.762237 INFO: Entry point address = 0x80000000
10060 12:29:41.762321 INFO: SPSR = 0x8
10061 12:29:41.768700
10062 12:29:41.768820
10063 12:29:41.768886
10064 12:29:41.772171 Starting depthcharge on Spherion...
10065 12:29:41.772254
10066 12:29:41.772320 Wipe memory regions:
10067 12:29:41.772387
10068 12:29:41.773076 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10069 12:29:41.773206 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10070 12:29:41.773291 Setting prompt string to ['asurada:']
10071 12:29:41.773370 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10072 12:29:41.774861 [0x00000040000000, 0x00000054600000)
10073 12:29:41.897710
10074 12:29:41.897837 [0x00000054660000, 0x00000080000000)
10075 12:29:42.158104
10076 12:29:42.158251 [0x000000821a7280, 0x000000ffe64000)
10077 12:29:42.902502
10078 12:29:42.902640 [0x00000100000000, 0x00000240000000)
10079 12:29:44.792510
10080 12:29:44.795838 Initializing XHCI USB controller at 0x11200000.
10081 12:29:45.833561
10082 12:29:45.836521 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10083 12:29:45.836628
10084 12:29:45.836724
10085 12:29:45.836821
10086 12:29:45.837103 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 12:29:45.937446 asurada: tftpboot 192.168.201.1 10605793/tftp-deploy-se3bmgto/kernel/image.itb 10605793/tftp-deploy-se3bmgto/kernel/cmdline
10089 12:29:45.937616 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 12:29:45.937707 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10091 12:29:45.942085 tftpboot 192.168.201.1 10605793/tftp-deploy-se3bmgto/kernel/image.itp-deploy-se3bmgto/kernel/cmdline
10092 12:29:45.942174
10093 12:29:45.942241 Waiting for link
10094 12:29:46.102501
10095 12:29:46.102677 R8152: Initializing
10096 12:29:46.102745
10097 12:29:46.105988 Version 9 (ocp_data = 6010)
10098 12:29:46.106074
10099 12:29:46.109031 R8152: Done initializing
10100 12:29:46.109133
10101 12:29:46.109201 Adding net device
10102 12:29:48.055108
10103 12:29:48.055258 done.
10104 12:29:48.055327
10105 12:29:48.055419 MAC: 00:e0:4c:72:2d:d6
10106 12:29:48.055478
10107 12:29:48.058062 Sending DHCP discover... done.
10108 12:29:48.058177
10109 12:29:48.061943 Waiting for reply... done.
10110 12:29:48.062057
10111 12:29:48.064866 Sending DHCP request... done.
10112 12:29:48.064972
10113 12:29:48.071080 Waiting for reply... done.
10114 12:29:48.071188
10115 12:29:48.071286 My ip is 192.168.201.21
10116 12:29:48.071377
10117 12:29:48.074545 The DHCP server ip is 192.168.201.1
10118 12:29:48.074650
10119 12:29:48.081386 TFTP server IP predefined by user: 192.168.201.1
10120 12:29:48.081469
10121 12:29:48.087774 Bootfile predefined by user: 10605793/tftp-deploy-se3bmgto/kernel/image.itb
10122 12:29:48.087855
10123 12:29:48.091294 Sending tftp read request... done.
10124 12:29:48.091374
10125 12:29:48.091458 Waiting for the transfer...
10126 12:29:48.094261
10127 12:29:48.352913 00000000 ################################################################
10128 12:29:48.353099
10129 12:29:48.607309 00080000 ################################################################
10130 12:29:48.607461
10131 12:29:48.873021 00100000 ################################################################
10132 12:29:48.873175
10133 12:29:49.123384 00180000 ################################################################
10134 12:29:49.123563
10135 12:29:49.374807 00200000 ################################################################
10136 12:29:49.374975
10137 12:29:49.630342 00280000 ################################################################
10138 12:29:49.630484
10139 12:29:49.878596 00300000 ################################################################
10140 12:29:49.878761
10141 12:29:50.133995 00380000 ################################################################
10142 12:29:50.134135
10143 12:29:50.393360 00400000 ################################################################
10144 12:29:50.393503
10145 12:29:50.690530 00480000 ################################################################
10146 12:29:50.690678
10147 12:29:50.948040 00500000 ################################################################
10148 12:29:50.948211
10149 12:29:51.198034 00580000 ################################################################
10150 12:29:51.198206
10151 12:29:51.448132 00600000 ################################################################
10152 12:29:51.448300
10153 12:29:51.707644 00680000 ################################################################
10154 12:29:51.707838
10155 12:29:51.966495 00700000 ################################################################
10156 12:29:51.966643
10157 12:29:52.223794 00780000 ################################################################
10158 12:29:52.223946
10159 12:29:52.472054 00800000 ################################################################
10160 12:29:52.472231
10161 12:29:52.717232 00880000 ################################################################
10162 12:29:52.717439
10163 12:29:52.991996 00900000 ################################################################
10164 12:29:52.992188
10165 12:29:53.257308 00980000 ################################################################
10166 12:29:53.257479
10167 12:29:53.519753 00a00000 ################################################################
10168 12:29:53.519893
10169 12:29:53.768813 00a80000 ################################################################
10170 12:29:53.768961
10171 12:29:54.024684 00b00000 ################################################################
10172 12:29:54.024847
10173 12:29:54.278116 00b80000 ################################################################
10174 12:29:54.278291
10175 12:29:54.528619 00c00000 ################################################################
10176 12:29:54.528797
10177 12:29:54.780892 00c80000 ################################################################
10178 12:29:54.781030
10179 12:29:55.041223 00d00000 ################################################################
10180 12:29:55.041378
10181 12:29:55.301510 00d80000 ################################################################
10182 12:29:55.301656
10183 12:29:55.566268 00e00000 ################################################################
10184 12:29:55.566423
10185 12:29:55.822019 00e80000 ################################################################
10186 12:29:55.822168
10187 12:29:56.078927 00f00000 ################################################################
10188 12:29:56.079114
10189 12:29:56.325553 00f80000 ################################################################
10190 12:29:56.325707
10191 12:29:56.577570 01000000 ################################################################
10192 12:29:56.577749
10193 12:29:56.846814 01080000 ################################################################
10194 12:29:56.846978
10195 12:29:57.100848 01100000 ################################################################
10196 12:29:57.100988
10197 12:29:57.349354 01180000 ################################################################
10198 12:29:57.349507
10199 12:29:57.613574 01200000 ################################################################
10200 12:29:57.613728
10201 12:29:57.866577 01280000 ################################################################
10202 12:29:57.866728
10203 12:29:58.123444 01300000 ################################################################
10204 12:29:58.123584
10205 12:29:58.402863 01380000 ################################################################
10206 12:29:58.403016
10207 12:29:58.673996 01400000 ################################################################
10208 12:29:58.674178
10209 12:29:58.927288 01480000 ################################################################
10210 12:29:58.927467
10211 12:29:59.173337 01500000 ################################################################
10212 12:29:59.173496
10213 12:29:59.420701 01580000 ################################################################
10214 12:29:59.420893
10215 12:29:59.688998 01600000 ################################################################
10216 12:29:59.689150
10217 12:29:59.939323 01680000 ################################################################
10218 12:29:59.939474
10219 12:30:00.226924 01700000 ################################################################
10220 12:30:00.227177
10221 12:30:00.512595 01780000 ################################################################
10222 12:30:00.512749
10223 12:30:00.799466 01800000 ################################################################
10224 12:30:00.799612
10225 12:30:01.086586 01880000 ################################################################
10226 12:30:01.086777
10227 12:30:01.373097 01900000 ################################################################
10228 12:30:01.373247
10229 12:30:01.662200 01980000 ################################################################
10230 12:30:01.662354
10231 12:30:01.916749 01a00000 ################################################################ done.
10232 12:30:01.916914
10233 12:30:01.919908 The bootfile was 27781842 bytes long.
10234 12:30:01.920392
10235 12:30:01.923399 Sending tftp read request... done.
10236 12:30:01.923829
10237 12:30:01.927353 Waiting for the transfer...
10238 12:30:01.928089
10239 12:30:01.928800 00000000 # done.
10240 12:30:01.929498
10241 12:30:01.936420 Command line loaded dynamically from TFTP file: 10605793/tftp-deploy-se3bmgto/kernel/cmdline
10242 12:30:01.937181
10243 12:30:01.956524 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10244 12:30:01.957062
10245 12:30:01.957485 Loading FIT.
10246 12:30:01.957872
10247 12:30:01.959384 Image ramdisk-1 has 17646135 bytes.
10248 12:30:01.959860
10249 12:30:01.962713 Image fdt-1 has 46924 bytes.
10250 12:30:01.963147
10251 12:30:01.965921 Image kernel-1 has 10086749 bytes.
10252 12:30:01.966401
10253 12:30:01.975949 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10254 12:30:01.976427
10255 12:30:01.992338 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10256 12:30:01.992924
10257 12:30:01.996228 Choosing best match conf-1 for compat google,spherion-rev2.
10258 12:30:02.001486
10259 12:30:02.005724 Connected to device vid:did:rid of 1ae0:0028:00
10260 12:30:02.012848
10261 12:30:02.016390 tpm_get_response: command 0x17b, return code 0x0
10262 12:30:02.016856
10263 12:30:02.019327 ec_init: CrosEC protocol v3 supported (256, 248)
10264 12:30:02.024745
10265 12:30:02.028226 tpm_cleanup: add release locality here.
10266 12:30:02.028661
10267 12:30:02.029049 Shutting down all USB controllers.
10268 12:30:02.031336
10269 12:30:02.031769 Removing current net device
10270 12:30:02.032108
10271 12:30:02.038395 Exiting depthcharge with code 4 at timestamp: 49585498
10272 12:30:02.038830
10273 12:30:02.041360 LZMA decompressing kernel-1 to 0x821a6718
10274 12:30:02.041792
10275 12:30:02.044677 LZMA decompressing kernel-1 to 0x40000000
10276 12:30:03.310961
10277 12:30:03.311195 jumping to kernel
10278 12:30:03.311836 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10279 12:30:03.312054 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10280 12:30:03.312218 Setting prompt string to ['Linux version [0-9]']
10281 12:30:03.312363 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10282 12:30:03.312508 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10283 12:30:03.394026
10284 12:30:03.397270 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10285 12:30:03.400872 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10286 12:30:03.400969 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10287 12:30:03.401053 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10288 12:30:03.401128 Using line separator: #'\n'#
10289 12:30:03.401189 No login prompt set.
10290 12:30:03.401262 Parsing kernel messages
10291 12:30:03.401323 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10292 12:30:03.401427 [login-action] Waiting for messages, (timeout 00:04:04)
10293 12:30:03.420144 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10294 12:30:03.423536 [ 0.000000] random: crng init done
10295 12:30:03.430373 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 12:30:03.430455 [ 0.000000] efi: UEFI not found.
10297 12:30:03.439928 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 12:30:03.446508 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 12:30:03.456900 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 12:30:03.466883 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 12:30:03.473657 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10302 12:30:03.479951 [ 0.000000] printk: bootconsole [mtk8250] enabled
10303 12:30:03.486494 [ 0.000000] NUMA: No NUMA configuration found
10304 12:30:03.492749 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10305 12:30:03.496099 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10306 12:30:03.499681 [ 0.000000] Zone ranges:
10307 12:30:03.506424 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10308 12:30:03.509568 [ 0.000000] DMA32 empty
10309 12:30:03.516375 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10310 12:30:03.519271 [ 0.000000] Movable zone start for each node
10311 12:30:03.522681 [ 0.000000] Early memory node ranges
10312 12:30:03.529588 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10313 12:30:03.536059 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10314 12:30:03.542194 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10315 12:30:03.549247 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10316 12:30:03.552478 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10317 12:30:03.562020 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10318 12:30:03.617648 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10319 12:30:03.624440 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10320 12:30:03.630813 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10321 12:30:03.634147 [ 0.000000] psci: probing for conduit method from DT.
10322 12:30:03.640713 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10323 12:30:03.644130 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10324 12:30:03.650999 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10325 12:30:03.654279 [ 0.000000] psci: SMC Calling Convention v1.2
10326 12:30:03.660662 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10327 12:30:03.664322 [ 0.000000] Detected VIPT I-cache on CPU0
10328 12:30:03.671138 [ 0.000000] CPU features: detected: GIC system register CPU interface
10329 12:30:03.677667 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10330 12:30:03.683992 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10331 12:30:03.690968 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10332 12:30:03.700515 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10333 12:30:03.707196 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10334 12:30:03.710699 [ 0.000000] alternatives: applying boot alternatives
10335 12:30:03.717455 [ 0.000000] Fallback order for Node 0: 0
10336 12:30:03.723886 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10337 12:30:03.726996 [ 0.000000] Policy zone: Normal
10338 12:30:03.746915 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10339 12:30:03.756872 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10340 12:30:03.769239 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10341 12:30:03.778658 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10342 12:30:03.785497 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10343 12:30:03.788520 <6>[ 0.000000] software IO TLB: area num 8.
10344 12:30:03.845322 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10345 12:30:03.994417 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10346 12:30:04.001181 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10347 12:30:04.007580 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10348 12:30:04.011009 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10349 12:30:04.017818 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10350 12:30:04.023911 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10351 12:30:04.027298 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10352 12:30:04.037372 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10353 12:30:04.044052 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10354 12:30:04.050381 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10355 12:30:04.057103 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10356 12:30:04.060492 <6>[ 0.000000] GICv3: 608 SPIs implemented
10357 12:30:04.063940 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10358 12:30:04.070422 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10359 12:30:04.073650 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10360 12:30:04.080457 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10361 12:30:04.093527 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10362 12:30:04.103848 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10363 12:30:04.113605 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10364 12:30:04.120938 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10365 12:30:04.134043 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10366 12:30:04.140972 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10367 12:30:04.147348 <6>[ 0.009227] Console: colour dummy device 80x25
10368 12:30:04.157690 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10369 12:30:04.164056 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10370 12:30:04.167517 <6>[ 0.029272] LSM: Security Framework initializing
10371 12:30:04.173683 <6>[ 0.034209] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 12:30:04.183758 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 12:30:04.193882 <6>[ 0.051449] cblist_init_generic: Setting adjustable number of callback queues.
10374 12:30:04.196674 <6>[ 0.058901] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 12:30:04.203413 <6>[ 0.065240] cblist_init_generic: Setting shift to 3 and lim to 1.
10376 12:30:04.210322 <6>[ 0.071648] rcu: Hierarchical SRCU implementation.
10377 12:30:04.216843 <6>[ 0.076661] rcu: Max phase no-delay instances is 1000.
10378 12:30:04.223230 <6>[ 0.083675] EFI services will not be available.
10379 12:30:04.226736 <6>[ 0.088674] smp: Bringing up secondary CPUs ...
10380 12:30:04.234214 <6>[ 0.093727] Detected VIPT I-cache on CPU1
10381 12:30:04.240857 <6>[ 0.093799] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10382 12:30:04.247094 <6>[ 0.093830] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10383 12:30:04.250590 <6>[ 0.094158] Detected VIPT I-cache on CPU2
10384 12:30:04.260375 <6>[ 0.094206] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10385 12:30:04.267136 <6>[ 0.094221] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10386 12:30:04.270545 <6>[ 0.094476] Detected VIPT I-cache on CPU3
10387 12:30:04.276755 <6>[ 0.094522] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10388 12:30:04.283343 <6>[ 0.094536] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10389 12:30:04.286859 <6>[ 0.094839] CPU features: detected: Spectre-v4
10390 12:30:04.293485 <6>[ 0.094846] CPU features: detected: Spectre-BHB
10391 12:30:04.296907 <6>[ 0.094852] Detected PIPT I-cache on CPU4
10392 12:30:04.303341 <6>[ 0.094910] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10393 12:30:04.309981 <6>[ 0.094926] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10394 12:30:04.316486 <6>[ 0.095221] Detected PIPT I-cache on CPU5
10395 12:30:04.323338 <6>[ 0.095285] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10396 12:30:04.329860 <6>[ 0.095301] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10397 12:30:04.333233 <6>[ 0.095587] Detected PIPT I-cache on CPU6
10398 12:30:04.340068 <6>[ 0.095653] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10399 12:30:04.346144 <6>[ 0.095669] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10400 12:30:04.353085 <6>[ 0.095969] Detected PIPT I-cache on CPU7
10401 12:30:04.359543 <6>[ 0.096034] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10402 12:30:04.366499 <6>[ 0.096050] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10403 12:30:04.369674 <6>[ 0.096099] smp: Brought up 1 node, 8 CPUs
10404 12:30:04.376297 <6>[ 0.237309] SMP: Total of 8 processors activated.
10405 12:30:04.379721 <6>[ 0.242260] CPU features: detected: 32-bit EL0 Support
10406 12:30:04.389363 <6>[ 0.247624] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10407 12:30:04.396211 <6>[ 0.256424] CPU features: detected: Common not Private translations
10408 12:30:04.402813 <6>[ 0.262940] CPU features: detected: CRC32 instructions
10409 12:30:04.405765 <6>[ 0.268291] CPU features: detected: RCpc load-acquire (LDAPR)
10410 12:30:04.412821 <6>[ 0.274251] CPU features: detected: LSE atomic instructions
10411 12:30:04.419291 <6>[ 0.280032] CPU features: detected: Privileged Access Never
10412 12:30:04.425666 <6>[ 0.285812] CPU features: detected: RAS Extension Support
10413 12:30:04.432619 <6>[ 0.291421] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10414 12:30:04.435281 <6>[ 0.298641] CPU: All CPU(s) started at EL2
10415 12:30:04.442021 <6>[ 0.302984] alternatives: applying system-wide alternatives
10416 12:30:04.451816 <6>[ 0.313697] devtmpfs: initialized
10417 12:30:04.467072 <6>[ 0.322625] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10418 12:30:04.473806 <6>[ 0.332587] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10419 12:30:04.480486 <6>[ 0.340625] pinctrl core: initialized pinctrl subsystem
10420 12:30:04.483914 <6>[ 0.347286] DMI not present or invalid.
10421 12:30:04.490278 <6>[ 0.351699] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10422 12:30:04.500140 <6>[ 0.358579] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10423 12:30:04.506572 <6>[ 0.366161] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10424 12:30:04.516703 <6>[ 0.374377] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10425 12:30:04.519956 <6>[ 0.382616] audit: initializing netlink subsys (disabled)
10426 12:30:04.529653 <5>[ 0.388309] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10427 12:30:04.536679 <6>[ 0.389023] thermal_sys: Registered thermal governor 'step_wise'
10428 12:30:04.542998 <6>[ 0.396276] thermal_sys: Registered thermal governor 'power_allocator'
10429 12:30:04.546557 <6>[ 0.402532] cpuidle: using governor menu
10430 12:30:04.552877 <6>[ 0.413493] NET: Registered PF_QIPCRTR protocol family
10431 12:30:04.559452 <6>[ 0.418979] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10432 12:30:04.566435 <6>[ 0.426082] ASID allocator initialised with 32768 entries
10433 12:30:04.569402 <6>[ 0.432668] Serial: AMBA PL011 UART driver
10434 12:30:04.579242 <4>[ 0.441285] Trying to register duplicate clock ID: 134
10435 12:30:04.633226 <6>[ 0.498562] KASLR enabled
10436 12:30:04.647675 <6>[ 0.506290] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10437 12:30:04.654095 <6>[ 0.513302] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10438 12:30:04.660700 <6>[ 0.519790] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10439 12:30:04.667384 <6>[ 0.526795] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10440 12:30:04.674185 <6>[ 0.533280] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10441 12:30:04.680461 <6>[ 0.540283] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10442 12:30:04.687014 <6>[ 0.546771] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10443 12:30:04.693829 <6>[ 0.553778] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10444 12:30:04.697094 <6>[ 0.561261] ACPI: Interpreter disabled.
10445 12:30:04.705718 <6>[ 0.567711] iommu: Default domain type: Translated
10446 12:30:04.712229 <6>[ 0.572825] iommu: DMA domain TLB invalidation policy: strict mode
10447 12:30:04.715449 <5>[ 0.579493] SCSI subsystem initialized
10448 12:30:04.721711 <6>[ 0.583730] usbcore: registered new interface driver usbfs
10449 12:30:04.728738 <6>[ 0.589461] usbcore: registered new interface driver hub
10450 12:30:04.731885 <6>[ 0.595011] usbcore: registered new device driver usb
10451 12:30:04.739235 <6>[ 0.601117] pps_core: LinuxPPS API ver. 1 registered
10452 12:30:04.748975 <6>[ 0.606313] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10453 12:30:04.752286 <6>[ 0.615654] PTP clock support registered
10454 12:30:04.755655 <6>[ 0.619894] EDAC MC: Ver: 3.0.0
10455 12:30:04.763157 <6>[ 0.625084] FPGA manager framework
10456 12:30:04.769832 <6>[ 0.628761] Advanced Linux Sound Architecture Driver Initialized.
10457 12:30:04.772699 <6>[ 0.635533] vgaarb: loaded
10458 12:30:04.779654 <6>[ 0.638638] clocksource: Switched to clocksource arch_sys_counter
10459 12:30:04.782821 <5>[ 0.645082] VFS: Disk quotas dquot_6.6.0
10460 12:30:04.789436 <6>[ 0.649271] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10461 12:30:04.792525 <6>[ 0.656462] pnp: PnP ACPI: disabled
10462 12:30:04.801139 <6>[ 0.663123] NET: Registered PF_INET protocol family
10463 12:30:04.811059 <6>[ 0.668708] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10464 12:30:04.821937 <6>[ 0.681034] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10465 12:30:04.832295 <6>[ 0.689853] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10466 12:30:04.839275 <6>[ 0.697822] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10467 12:30:04.848534 <6>[ 0.706522] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10468 12:30:04.855442 <6>[ 0.716265] TCP: Hash tables configured (established 65536 bind 65536)
10469 12:30:04.861704 <6>[ 0.723122] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10470 12:30:04.871751 <6>[ 0.730319] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 12:30:04.878519 <6>[ 0.738019] NET: Registered PF_UNIX/PF_LOCAL protocol family
10472 12:30:04.884939 <6>[ 0.744182] RPC: Registered named UNIX socket transport module.
10473 12:30:04.888325 <6>[ 0.750338] RPC: Registered udp transport module.
10474 12:30:04.894776 <6>[ 0.755272] RPC: Registered tcp transport module.
10475 12:30:04.901592 <6>[ 0.760206] RPC: Registered tcp NFSv4.1 backchannel transport module.
10476 12:30:04.904891 <6>[ 0.766876] PCI: CLS 0 bytes, default 64
10477 12:30:04.907829 <6>[ 0.771260] Unpacking initramfs...
10478 12:30:04.917890 <6>[ 0.775071] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10479 12:30:04.924433 <6>[ 0.783737] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10480 12:30:04.931050 <6>[ 0.792574] kvm [1]: IPA Size Limit: 40 bits
10481 12:30:04.934227 <6>[ 0.797098] kvm [1]: GICv3: no GICV resource entry
10482 12:30:04.940622 <6>[ 0.802120] kvm [1]: disabling GICv2 emulation
10483 12:30:04.947573 <6>[ 0.806803] kvm [1]: GIC system register CPU interface enabled
10484 12:30:04.951002 <6>[ 0.812971] kvm [1]: vgic interrupt IRQ18
10485 12:30:04.957165 <6>[ 0.817330] kvm [1]: VHE mode initialized successfully
10486 12:30:04.960670 <5>[ 0.823633] Initialise system trusted keyrings
10487 12:30:04.967144 <6>[ 0.828446] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10488 12:30:04.976563 <6>[ 0.838537] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10489 12:30:04.983450 <5>[ 0.844923] NFS: Registering the id_resolver key type
10490 12:30:04.986416 <5>[ 0.850225] Key type id_resolver registered
10491 12:30:04.993561 <5>[ 0.854643] Key type id_legacy registered
10492 12:30:04.999577 <6>[ 0.858921] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10493 12:30:05.006285 <6>[ 0.865843] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10494 12:30:05.012972 <6>[ 0.873553] 9p: Installing v9fs 9p2000 file system support
10495 12:30:05.048939 <5>[ 0.910671] Key type asymmetric registered
10496 12:30:05.052531 <5>[ 0.915001] Asymmetric key parser 'x509' registered
10497 12:30:05.062034 <6>[ 0.920139] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10498 12:30:05.065561 <6>[ 0.927752] io scheduler mq-deadline registered
10499 12:30:05.068899 <6>[ 0.932513] io scheduler kyber registered
10500 12:30:05.087508 <6>[ 0.949265] EINJ: ACPI disabled.
10501 12:30:05.119297 <4>[ 0.974422] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10502 12:30:05.129021 <4>[ 0.985034] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 12:30:05.143745 <6>[ 1.005662] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10504 12:30:05.152021 <6>[ 1.013608] printk: console [ttyS0] disabled
10505 12:30:05.179529 <6>[ 1.038253] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10506 12:30:05.186214 <6>[ 1.047724] printk: console [ttyS0] enabled
10507 12:30:05.189549 <6>[ 1.047724] printk: console [ttyS0] enabled
10508 12:30:05.196249 <6>[ 1.056617] printk: bootconsole [mtk8250] disabled
10509 12:30:05.199138 <6>[ 1.056617] printk: bootconsole [mtk8250] disabled
10510 12:30:05.206152 <6>[ 1.067622] SuperH (H)SCI(F) driver initialized
10511 12:30:05.209049 <6>[ 1.072872] msm_serial: driver initialized
10512 12:30:05.223253 <6>[ 1.081756] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10513 12:30:05.233056 <6>[ 1.090302] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10514 12:30:05.239685 <6>[ 1.098844] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10515 12:30:05.249216 <6>[ 1.107471] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10516 12:30:05.259439 <6>[ 1.116177] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10517 12:30:05.266202 <6>[ 1.124891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10518 12:30:05.275968 <6>[ 1.133433] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10519 12:30:05.282471 <6>[ 1.142227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10520 12:30:05.292565 <6>[ 1.150770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10521 12:30:05.304295 <6>[ 1.166154] loop: module loaded
10522 12:30:05.310969 <6>[ 1.172254] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10523 12:30:05.333602 <4>[ 1.195463] mtk-pmic-keys: Failed to locate of_node [id: -1]
10524 12:30:05.340003 <6>[ 1.202170] megasas: 07.719.03.00-rc1
10525 12:30:05.349919 <6>[ 1.211739] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10526 12:30:05.356498 <6>[ 1.218058] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10527 12:30:05.372858 <6>[ 1.234825] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10528 12:30:05.433564 <6>[ 1.289048] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10529 12:30:05.631562 <6>[ 1.493491] Freeing initrd memory: 17228K
10530 12:30:05.641878 <6>[ 1.503854] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10531 12:30:05.652478 <6>[ 1.514607] tun: Universal TUN/TAP device driver, 1.6
10532 12:30:05.655816 <6>[ 1.520649] thunder_xcv, ver 1.0
10533 12:30:05.659199 <6>[ 1.524157] thunder_bgx, ver 1.0
10534 12:30:05.662769 <6>[ 1.527654] nicpf, ver 1.0
10535 12:30:05.672959 <6>[ 1.531648] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10536 12:30:05.676384 <6>[ 1.539125] hns3: Copyright (c) 2017 Huawei Corporation.
10537 12:30:05.682664 <6>[ 1.544711] hclge is initializing
10538 12:30:05.686231 <6>[ 1.548287] e1000: Intel(R) PRO/1000 Network Driver
10539 12:30:05.693060 <6>[ 1.553415] e1000: Copyright (c) 1999-2006 Intel Corporation.
10540 12:30:05.695865 <6>[ 1.559431] e1000e: Intel(R) PRO/1000 Network Driver
10541 12:30:05.702557 <6>[ 1.564647] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10542 12:30:05.709141 <6>[ 1.570832] igb: Intel(R) Gigabit Ethernet Network Driver
10543 12:30:05.715918 <6>[ 1.576482] igb: Copyright (c) 2007-2014 Intel Corporation.
10544 12:30:05.722791 <6>[ 1.582318] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10545 12:30:05.729538 <6>[ 1.588836] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10546 12:30:05.732371 <6>[ 1.595294] sky2: driver version 1.30
10547 12:30:05.738918 <6>[ 1.600265] VFIO - User Level meta-driver version: 0.3
10548 12:30:05.746315 <6>[ 1.608462] usbcore: registered new interface driver usb-storage
10549 12:30:05.752487 <6>[ 1.614906] usbcore: registered new device driver onboard-usb-hub
10550 12:30:05.761415 <6>[ 1.623988] mt6397-rtc mt6359-rtc: registered as rtc0
10551 12:30:05.771509 <6>[ 1.629460] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:30:03 UTC (1686054603)
10552 12:30:05.774984 <6>[ 1.639038] i2c_dev: i2c /dev entries driver
10553 12:30:05.791480 <6>[ 1.650624] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10554 12:30:05.798251 <6>[ 1.660804] sdhci: Secure Digital Host Controller Interface driver
10555 12:30:05.804935 <6>[ 1.667241] sdhci: Copyright(c) Pierre Ossman
10556 12:30:05.811994 <6>[ 1.672632] Synopsys Designware Multimedia Card Interface Driver
10557 12:30:05.815278 <6>[ 1.679256] mmc0: CQHCI version 5.10
10558 12:30:05.821566 <6>[ 1.679776] sdhci-pltfm: SDHCI platform and OF driver helper
10559 12:30:05.828998 <6>[ 1.691428] ledtrig-cpu: registered to indicate activity on CPUs
10560 12:30:05.839646 <6>[ 1.698835] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10561 12:30:05.843057 <6>[ 1.706229] usbcore: registered new interface driver usbhid
10562 12:30:05.849557 <6>[ 1.712063] usbhid: USB HID core driver
10563 12:30:05.856111 <6>[ 1.716317] spi_master spi0: will run message pump with realtime priority
10564 12:30:05.901822 <6>[ 1.757628] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10565 12:30:05.920816 <6>[ 1.772995] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10566 12:30:05.924255 <6>[ 1.786567] mmc0: Command Queue Engine enabled
10567 12:30:05.931085 <6>[ 1.788258] cros-ec-spi spi0.0: Chrome EC device registered
10568 12:30:05.937815 <6>[ 1.791307] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10569 12:30:05.941295 <6>[ 1.804742] mmcblk0: mmc0:0001 DA4128 116 GiB
10570 12:30:05.956483 <6>[ 1.815422] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10571 12:30:05.963006 <6>[ 1.816933] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10572 12:30:05.969529 <6>[ 1.826889] NET: Registered PF_PACKET protocol family
10573 12:30:05.972965 <6>[ 1.832043] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10574 12:30:05.979218 <6>[ 1.836090] 9pnet: Installing 9P2000 support
10575 12:30:05.982518 <6>[ 1.841801] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10576 12:30:05.989426 <5>[ 1.845764] Key type dns_resolver registered
10577 12:30:05.995654 <6>[ 1.851593] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10578 12:30:05.999328 <6>[ 1.856056] registered taskstats version 1
10579 12:30:06.002629 <5>[ 1.866360] Loading compiled-in X.509 certificates
10580 12:30:06.038764 <4>[ 1.894191] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 12:30:06.048834 <4>[ 1.904887] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 12:30:06.059421 <3>[ 1.917642] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10583 12:30:06.071414 <6>[ 1.933145] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10584 12:30:06.078255 <6>[ 1.939979] xhci-mtk 11200000.usb: xHCI Host Controller
10585 12:30:06.084413 <6>[ 1.945482] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10586 12:30:06.094896 <6>[ 1.953345] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10587 12:30:06.101296 <6>[ 1.962790] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10588 12:30:06.108314 <6>[ 1.968996] xhci-mtk 11200000.usb: xHCI Host Controller
10589 12:30:06.114518 <6>[ 1.974495] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10590 12:30:06.121113 <6>[ 1.982162] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10591 12:30:06.128028 <6>[ 1.990066] hub 1-0:1.0: USB hub found
10592 12:30:06.131559 <6>[ 1.994100] hub 1-0:1.0: 1 port detected
10593 12:30:06.141476 <6>[ 1.998472] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10594 12:30:06.144494 <6>[ 2.007291] hub 2-0:1.0: USB hub found
10595 12:30:06.147783 <6>[ 2.011328] hub 2-0:1.0: 1 port detected
10596 12:30:06.156698 <6>[ 2.018454] mtk-msdc 11f70000.mmc: Got CD GPIO
10597 12:30:06.174687 <6>[ 2.033178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10598 12:30:06.181265 <6>[ 2.041223] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10599 12:30:06.191303 <4>[ 2.049208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10600 12:30:06.201012 <6>[ 2.058878] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10601 12:30:06.207797 <6>[ 2.066960] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10602 12:30:06.214161 <6>[ 2.074998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10603 12:30:06.224139 <6>[ 2.082911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10604 12:30:06.230960 <6>[ 2.090732] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10605 12:30:06.240987 <6>[ 2.098558] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10606 12:30:06.250721 <6>[ 2.109281] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10607 12:30:06.260398 <6>[ 2.117648] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10608 12:30:06.267398 <6>[ 2.126000] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10609 12:30:06.277223 <6>[ 2.134342] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10610 12:30:06.283680 <6>[ 2.142687] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10611 12:30:06.293502 <6>[ 2.151030] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10612 12:30:06.300471 <6>[ 2.159372] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10613 12:30:06.310291 <6>[ 2.167716] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10614 12:30:06.316490 <6>[ 2.176059] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10615 12:30:06.326571 <6>[ 2.184402] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10616 12:30:06.333015 <6>[ 2.192746] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10617 12:30:06.342830 <6>[ 2.201089] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10618 12:30:06.349674 <6>[ 2.209438] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10619 12:30:06.359399 <6>[ 2.217782] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10620 12:30:06.366109 <6>[ 2.226126] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10621 12:30:06.372671 <6>[ 2.235044] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10622 12:30:06.380251 <6>[ 2.242493] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10623 12:30:06.387467 <6>[ 2.249513] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10624 12:30:06.397922 <6>[ 2.256599] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10625 12:30:06.404522 <6>[ 2.263884] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10626 12:30:06.414343 <6>[ 2.270813] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10627 12:30:06.421276 <6>[ 2.279951] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10628 12:30:06.431109 <6>[ 2.289078] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10629 12:30:06.441086 <6>[ 2.298380] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10630 12:30:06.451124 <6>[ 2.307854] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10631 12:30:06.460830 <6>[ 2.317328] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10632 12:30:06.467283 <6>[ 2.326455] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10633 12:30:06.477168 <6>[ 2.335935] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10634 12:30:06.487199 <6>[ 2.345062] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10635 12:30:06.497116 <6>[ 2.354363] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10636 12:30:06.507072 <6>[ 2.364529] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10637 12:30:06.517589 <6>[ 2.376320] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10638 12:30:06.524197 <6>[ 2.386248] Trying to probe devices needed for running init ...
10639 12:30:06.555981 <6>[ 2.414862] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10640 12:30:06.708701 <6>[ 2.570900] hub 1-1:1.0: USB hub found
10641 12:30:06.712210 <6>[ 2.575267] hub 1-1:1.0: 4 ports detected
10642 12:30:06.835837 <6>[ 2.695074] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10643 12:30:06.860698 <6>[ 2.722735] hub 2-1:1.0: USB hub found
10644 12:30:06.863507 <6>[ 2.727104] hub 2-1:1.0: 3 ports detected
10645 12:30:07.032009 <6>[ 2.890943] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10646 12:30:07.164687 <6>[ 3.027060] hub 1-1.4:1.0: USB hub found
10647 12:30:07.167863 <6>[ 3.031761] hub 1-1.4:1.0: 2 ports detected
10648 12:30:07.243761 <6>[ 3.103168] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10649 12:30:07.463949 <6>[ 3.322917] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10650 12:30:07.655796 <6>[ 3.514916] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10651 12:30:18.799974 <6>[ 14.667466] ALSA device list:
10652 12:30:18.806850 <6>[ 14.670723] No soundcards found.
10653 12:30:18.818986 <6>[ 14.683101] Freeing unused kernel memory: 8384K
10654 12:30:18.822391 <6>[ 14.688035] Run /init as init process
10655 12:30:18.833054 Loading, please wait...
10656 12:30:18.852925 Starting version 247.3-7+deb11u2
10657 12:30:19.173816 <6>[ 15.034451] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10658 12:30:19.186678 <6>[ 15.050777] remoteproc remoteproc0: scp is available
10659 12:30:19.196629 <4>[ 15.056837] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10660 12:30:19.203743 <6>[ 15.066945] remoteproc remoteproc0: powering up scp
10661 12:30:19.213613 <4>[ 15.072117] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10662 12:30:19.219979 <3>[ 15.073223] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 12:30:19.226640 <3>[ 15.081944] remoteproc remoteproc0: request_firmware failed: -2
10664 12:30:19.236370 <3>[ 15.096258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 12:30:19.243171 <3>[ 15.104361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 12:30:19.263068 <3>[ 15.123673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 12:30:19.269687 <6>[ 15.124860] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10668 12:30:19.279524 <3>[ 15.131814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 12:30:19.286169 <3>[ 15.147533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 12:30:19.296057 <4>[ 15.150286] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10671 12:30:19.299454 <4>[ 15.150286] Fallback method does not support PEC.
10672 12:30:19.309099 <6>[ 15.154127] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10673 12:30:19.315889 <6>[ 15.154162] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10674 12:30:19.325663 <6>[ 15.154174] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10675 12:30:19.333080 <3>[ 15.155621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 12:30:19.342864 <3>[ 15.155628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 12:30:19.345929 <6>[ 15.171292] mc: Linux media interface: v0.10
10678 12:30:19.352858 <3>[ 15.171760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 12:30:19.363034 <3>[ 15.178773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 12:30:19.370056 <4>[ 15.189226] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10681 12:30:19.376535 <3>[ 15.194277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 12:30:19.386180 <3>[ 15.194289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 12:30:19.392976 <4>[ 15.202801] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10684 12:30:19.399491 <3>[ 15.210582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 12:30:19.409442 <3>[ 15.211179] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 12:30:19.416222 <6>[ 15.216005] videodev: Linux video capture interface: v2.00
10687 12:30:19.422576 <6>[ 15.216624] usbcore: registered new interface driver r8152
10688 12:30:19.429167 <3>[ 15.223077] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 12:30:19.435857 <3>[ 15.223086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 12:30:19.445859 <3>[ 15.237932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 12:30:19.455667 <3>[ 15.238465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 12:30:19.462436 <3>[ 15.238473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 12:30:19.468894 <6>[ 15.271991] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10694 12:30:19.479039 <3>[ 15.278815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 12:30:19.482266 <6>[ 15.284529] pci_bus 0000:00: root bus resource [bus 00-ff]
10696 12:30:19.492369 <6>[ 15.303532] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10697 12:30:19.498626 <6>[ 15.306472] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10698 12:30:19.508713 <6>[ 15.315836] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10699 12:30:19.518507 <6>[ 15.323355] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10700 12:30:19.525326 <3>[ 15.323611] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10701 12:30:19.531695 <6>[ 15.394921] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10702 12:30:19.538129 <6>[ 15.395125] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10703 12:30:19.548458 <6>[ 15.401209] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10704 12:30:19.551374 <6>[ 15.401288] pci 0000:00:00.0: supports D1 D2
10705 12:30:19.558049 <6>[ 15.420394] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10706 12:30:19.564853 <3>[ 15.422973] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10707 12:30:19.571354 <6>[ 15.429123] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10708 12:30:19.581126 <4>[ 15.434272] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10709 12:30:19.587873 <6>[ 15.442060] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10710 12:30:19.598124 <4>[ 15.451016] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10711 12:30:19.604381 <6>[ 15.457278] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10712 12:30:19.611261 <6>[ 15.472820] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10713 12:30:19.617640 <6>[ 15.480308] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10714 12:30:19.624599 <6>[ 15.487889] pci 0000:01:00.0: supports D1 D2
10715 12:30:19.630957 <6>[ 15.492413] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10716 12:30:19.650217 <6>[ 15.510920] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10717 12:30:19.656637 <6>[ 15.517832] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10718 12:30:19.663273 <6>[ 15.525922] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10719 12:30:19.670006 <6>[ 15.526834] r8152 2-1.3:1.0 eth0: v1.12.13
10720 12:30:19.676560 <3>[ 15.530960] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10721 12:30:19.683147 <3>[ 15.531330] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10722 12:30:19.693296 <6>[ 15.531438] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10723 12:30:19.699825 <6>[ 15.533943] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10724 12:30:19.706536 <6>[ 15.551988] usbcore: registered new interface driver cdc_ether
10725 12:30:19.712937 <6>[ 15.560872] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10726 12:30:19.716129 <6>[ 15.561583] Bluetooth: Core ver 2.22
10727 12:30:19.723157 <6>[ 15.561736] NET: Registered PF_BLUETOOTH protocol family
10728 12:30:19.729643 <6>[ 15.561742] Bluetooth: HCI device and connection manager initialized
10729 12:30:19.736363 <6>[ 15.561789] Bluetooth: HCI socket layer initialized
10730 12:30:19.739355 <6>[ 15.561800] Bluetooth: L2CAP socket layer initialized
10731 12:30:19.746167 <6>[ 15.561821] Bluetooth: SCO socket layer initialized
10732 12:30:19.752990 <6>[ 15.575567] usbcore: registered new interface driver r8153_ecm
10733 12:30:19.759154 <6>[ 15.582997] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10734 12:30:19.766120 <6>[ 15.584599] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10735 12:30:19.779156 <6>[ 15.585925] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10736 12:30:19.785746 <6>[ 15.586070] usbcore: registered new interface driver uvcvideo
10737 12:30:19.792431 <6>[ 15.595672] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10738 12:30:19.795722 <6>[ 15.599028] pci 0000:00:00.0: PCI bridge to [bus 01]
10739 12:30:19.802264 <6>[ 15.599877] usbcore: registered new interface driver btusb
10740 12:30:19.808991 <6>[ 15.600210] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10741 12:30:19.818740 <4>[ 15.600961] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10742 12:30:19.825213 <3>[ 15.600980] Bluetooth: hci0: Failed to load firmware file (-2)
10743 12:30:19.831960 <3>[ 15.600984] Bluetooth: hci0: Failed to set up firmware (-2)
10744 12:30:19.841942 <4>[ 15.600988] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10745 12:30:19.848569 <6>[ 15.710489] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10746 12:30:19.854868 <6>[ 15.718680] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10747 12:30:19.861575 <6>[ 15.725882] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10748 12:30:19.868945 <6>[ 15.732599] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10749 12:30:19.888811 <5>[ 15.749107] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10750 12:30:19.907341 <5>[ 15.767829] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10751 12:30:19.914340 <4>[ 15.774749] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10752 12:30:19.920582 <6>[ 15.783644] cfg80211: failed to load regulatory.db
10753 12:30:19.964749 <6>[ 15.825189] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10754 12:30:19.971465 <6>[ 15.832724] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10755 12:30:19.995675 <6>[ 15.859412] mt7921e 0000:01:00.0: ASIC revision: 79610010
10756 12:30:20.101335 <4>[ 15.958417] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10757 12:30:20.104580 Begin: Loading essential drivers ... done.
10758 12:30:20.111537 Begin: Running /scripts/init-premount ... done.
10759 12:30:20.117885 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10760 12:30:20.124433 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10761 12:30:20.131057 Device /sys/class/net/enx00e04c722dd6 found
10762 12:30:20.131823 done.
10763 12:30:20.178807 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10764 12:30:20.223538 <4>[ 16.080907] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10765 12:30:20.343509 <4>[ 16.200533] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 12:30:20.459376 <4>[ 16.316360] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 12:30:20.574632 <4>[ 16.432236] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 12:30:20.690653 <4>[ 16.548200] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 12:30:20.806879 <4>[ 16.664140] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 12:30:20.923044 <4>[ 16.780121] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 12:30:21.038578 <4>[ 16.896061] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 12:30:21.154502 <4>[ 17.012063] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 12:30:21.262056 <3>[ 17.125982] mt7921e 0000:01:00.0: hardware init failed
10774 12:30:21.264967 IP-Config: no response after 2 secs - giving up
10775 12:30:21.301344 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mt<6>[ 17.163088] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10776 12:30:21.301471 u 1500 DHCP
10777 12:30:22.402841 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10778 12:30:22.409206 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10779 12:30:22.416010 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10780 12:30:22.422555 host : mt8192-asurada-spherion-r0-cbg-1
10781 12:30:22.429050 domain : lava-rack
10782 12:30:22.435960 rootserver: 192.168.201.1 rootpath:
10783 12:30:22.436126 filename :
10784 12:30:22.448030 done.
10785 12:30:22.454753 Begin: Running /scripts/nfs-bottom ... done.
10786 12:30:22.471168 Begin: Running /scripts/init-bottom ... done.
10787 12:30:23.548092 <6>[ 19.412514] NET: Registered PF_INET6 protocol family
10788 12:30:23.554875 <6>[ 19.419183] Segment Routing with IPv6
10789 12:30:23.557806 <6>[ 19.423151] In-situ OAM (IOAM) with IPv6
10790 12:30:23.664075 <30>[ 19.509068] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10791 12:30:23.667351 <30>[ 19.532866] systemd[1]: Detected architecture arm64.
10792 12:30:23.685501
10793 12:30:23.689083 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10794 12:30:23.689225
10795 12:30:23.703811 <30>[ 19.568433] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10796 12:30:24.159069 <30>[ 20.020286] systemd[1]: Queued start job for default target Graphical Interface.
10797 12:30:24.191438 <30>[ 20.056004] systemd[1]: Created slice system-getty.slice.
10798 12:30:24.197805 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10799 12:30:24.215213 <30>[ 20.079688] systemd[1]: Created slice system-modprobe.slice.
10800 12:30:24.221970 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10801 12:30:24.238910 <30>[ 20.103622] systemd[1]: Created slice system-serial\x2dgetty.slice.
10802 12:30:24.249069 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10803 12:30:24.263144 <30>[ 20.127470] systemd[1]: Created slice User and Session Slice.
10804 12:30:24.269400 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10805 12:30:24.289916 <30>[ 20.151101] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10806 12:30:24.299473 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10807 12:30:24.313711 <30>[ 20.175061] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10808 12:30:24.320659 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10809 12:30:24.341020 <30>[ 20.198999] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10810 12:30:24.347718 <30>[ 20.211028] systemd[1]: Reached target Local Encrypted Volumes.
10811 12:30:24.354338 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10812 12:30:24.370364 <30>[ 20.235103] systemd[1]: Reached target Paths.
10813 12:30:24.373878 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10814 12:30:24.390160 <30>[ 20.254944] systemd[1]: Reached target Remote File Systems.
10815 12:30:24.396591 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10816 12:30:24.410153 <30>[ 20.274926] systemd[1]: Reached target Slices.
10817 12:30:24.413657 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10818 12:30:24.430510 <30>[ 20.294946] systemd[1]: Reached target Swap.
10819 12:30:24.433624 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10820 12:30:24.453676 <30>[ 20.315211] systemd[1]: Listening on initctl Compatibility Named Pipe.
10821 12:30:24.460544 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10822 12:30:24.466853 <30>[ 20.330421] systemd[1]: Listening on Journal Audit Socket.
10823 12:30:24.473725 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10824 12:30:24.487000 <30>[ 20.351833] systemd[1]: Listening on Journal Socket (/dev/log).
10825 12:30:24.493799 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10826 12:30:24.511193 <30>[ 20.375738] systemd[1]: Listening on Journal Socket.
10827 12:30:24.517578 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10828 12:30:24.534707 <30>[ 20.396073] systemd[1]: Listening on Network Service Netlink Socket.
10829 12:30:24.541465 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10830 12:30:24.556886 <30>[ 20.421340] systemd[1]: Listening on udev Control Socket.
10831 12:30:24.563443 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10832 12:30:24.578707 <30>[ 20.443217] systemd[1]: Listening on udev Kernel Socket.
10833 12:30:24.585080 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10834 12:30:24.642566 <30>[ 20.507025] systemd[1]: Mounting Huge Pages File System...
10835 12:30:24.648987 Mounting [0;1;39mHuge Pages File System[0m...
10836 12:30:24.664890 <30>[ 20.529658] systemd[1]: Mounting POSIX Message Queue File System...
10837 12:30:24.671639 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10838 12:30:24.688833 <30>[ 20.553411] systemd[1]: Mounting Kernel Debug File System...
10839 12:30:24.695507 Mounting [0;1;39mKernel Debug File System[0m...
10840 12:30:24.713748 <30>[ 20.575264] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10841 12:30:24.731559 <30>[ 20.592987] systemd[1]: Starting Create list of static device nodes for the current kernel...
10842 12:30:24.738165 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10843 12:30:24.756996 <30>[ 20.621434] systemd[1]: Starting Load Kernel Module configfs...
10844 12:30:24.763186 Starting [0;1;39mLoad Kernel Module configfs[0m...
10845 12:30:24.780601 <30>[ 20.645300] systemd[1]: Starting Load Kernel Module drm...
10846 12:30:24.787281 Starting [0;1;39mLoad Kernel Module drm[0m...
10847 12:30:24.804687 <30>[ 20.669486] systemd[1]: Starting Load Kernel Module fuse...
10848 12:30:24.811446 Starting [0;1;39mLoad Kernel Module fuse[0m...
10849 12:30:24.838830 <6>[ 20.703525] fuse: init (API version 7.37)
10850 12:30:24.848760 <30>[ 20.703847] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10851 12:30:24.887068 <30>[ 20.751440] systemd[1]: Starting Journal Service...
10852 12:30:24.889834 Starting [0;1;39mJournal Service[0m...
10853 12:30:24.913163 <30>[ 20.777974] systemd[1]: Starting Load Kernel Modules...
10854 12:30:24.919986 Starting [0;1;39mLoad Kernel Modules[0m...
10855 12:30:24.940629 <30>[ 20.801768] systemd[1]: Starting Remount Root and Kernel File Systems...
10856 12:30:24.946658 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10857 12:30:24.962292 <30>[ 20.826811] systemd[1]: Starting Coldplug All udev Devices...
10858 12:30:24.968984 Starting [0;1;39mColdplug All udev Devices[0m...
10859 12:30:24.985693 <30>[ 20.850370] systemd[1]: Mounted Huge Pages File System.
10860 12:30:24.992416 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10861 12:30:25.006860 <30>[ 20.871422] systemd[1]: Mounted POSIX Message Queue File System.
10862 12:30:25.013382 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10863 12:30:25.031081 <30>[ 20.895351] systemd[1]: Mounted Kernel Debug File System.
10864 12:30:25.037952 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10865 12:30:25.049117 <3>[ 20.910310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 12:30:25.058748 <30>[ 20.920324] systemd[1]: Finished Create list of static device nodes for the current kernel.
10867 12:30:25.069537 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10868 12:30:25.079507 <3>[ 20.939927] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 12:30:25.085881 <30>[ 20.949815] systemd[1]: modprobe@configfs.service: Succeeded.
10870 12:30:25.092659 <30>[ 20.956518] systemd[1]: Finished Load Kernel Module configfs.
10871 12:30:25.099013 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10872 12:30:25.119878 <30>[ 20.984008] systemd[1]: modprobe@drm.service: Succeeded.
10873 12:30:25.129583 <3>[ 20.989072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 12:30:25.132938 <30>[ 20.990780] systemd[1]: Finished Load Kernel Module drm.
10875 12:30:25.139761 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10876 12:30:25.157574 <3>[ 21.018992] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 12:30:25.164339 <30>[ 21.019970] systemd[1]: modprobe@fuse.service: Succeeded.
10878 12:30:25.170950 <30>[ 21.034145] systemd[1]: Finished Load Kernel Module fuse.
10879 12:30:25.177711 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10880 12:30:25.187853 <3>[ 21.049132] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 12:30:25.195108 <30>[ 21.059504] systemd[1]: Finished Load Kernel Modules.
10882 12:30:25.201319 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10883 12:30:25.217755 <3>[ 21.079304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 12:30:25.224528 <30>[ 21.080061] systemd[1]: Finished Remount Root and Kernel File Systems.
10885 12:30:25.234139 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10886 12:30:25.247174 <3>[ 21.108805] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 12:30:25.279716 <3>[ 21.141249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 12:30:25.303850 <30>[ 21.168124] systemd[1]: Mounting FUSE Control File System...
10889 12:30:25.317036 Mounting [0;1;39mFUSE <3>[ 21.176258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 12:30:25.317190 Control File System[0m...
10891 12:30:25.337570 <30>[ 21.201701] systemd[1]: Mounting Kernel Configuration File System...
10892 12:30:25.347294 <3>[ 21.206814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:30:25.353788 Mounting [0;1;39mKernel Configuration File System[0m...
10894 12:30:25.378000 <30>[ 21.238956] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10895 12:30:25.387690 <30>[ 21.247962] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10896 12:30:25.419145 <30>[ 21.283562] systemd[1]: Starting Load/Save Random Seed...
10897 12:30:25.425348 Starting [0;1;39mLoad/Save Random Seed[0m...
10898 12:30:25.445459 <30>[ 21.309953] systemd[1]: Starting Apply Kernel Variables...
10899 12:30:25.452610 Starting [0;1;39mApply Kernel Variables[0m...
10900 12:30:25.470412 <30>[ 21.335256] systemd[1]: Starting Create System Users...
10901 12:30:25.477227 Starting [0;1;39mCreate System Users[0m...
10902 12:30:25.492509 <30>[ 21.357338] systemd[1]: Started Journal Service.
10903 12:30:25.509337 <4>[ 21.359481] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10904 12:30:25.515571 <3>[ 21.377980] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10905 12:30:25.522264 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10906 12:30:25.540670 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10907 12:30:25.554208 See 'systemctl status systemd-udev-trigger.service' for details.
10908 12:30:25.571083 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10909 12:30:25.586797 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10910 12:30:25.603290 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10911 12:30:25.619338 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10912 12:30:25.634876 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10913 12:30:25.683181 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10914 12:30:25.705051 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10915 12:30:25.728609 <46>[ 21.589810] systemd-journald[296]: Received client request to flush runtime journal.
10916 12:30:26.480887 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10917 12:30:26.498678 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10918 12:30:26.514206 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10919 12:30:26.565660 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10920 12:30:27.109035 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10921 12:30:27.150756 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10922 12:30:27.174818 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10923 12:30:27.200264 Starting [0;1;39mNetwork Service[0m...
10924 12:30:27.554538 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10925 12:30:27.575995 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10926 12:30:27.623413 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10927 12:30:27.746675 <6>[ 23.611651] remoteproc remoteproc0: powering up scp
10928 12:30:27.782907 <4>[ 23.644480] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10929 12:30:27.789368 <3>[ 23.654430] remoteproc remoteproc0: request_firmware failed: -2
10930 12:30:27.799078 <3>[ 23.660620] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10931 12:30:27.903407 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10932 12:30:27.923721 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10933 12:30:27.942414 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10934 12:30:27.971587 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10935 12:30:27.993602 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10936 12:30:28.030664 Starting [0;1;39mNetwork Name Resolution[0m...
10937 12:30:28.053555 Starting [0;1;39mNetwork Time Synchronization[0m...
10938 12:30:28.072593 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10939 12:30:28.098762 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10940 12:30:28.131603 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10941 12:30:28.168700 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10942 12:30:28.273029 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10943 12:30:28.290249 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10944 12:30:28.309180 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10945 12:30:28.321929 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10946 12:30:28.337880 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10947 12:30:28.486787 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10948 12:30:28.527840 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10949 12:30:28.988460 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10950 12:30:29.257531 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10951 12:30:29.270174 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10952 12:30:29.291766 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10953 12:30:29.306148 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10954 12:30:29.321933 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10955 12:30:29.374577 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10956 12:30:29.637941 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10957 12:30:29.681758 Starting [0;1;39mUser Login Management[0m...
10958 12:30:29.699124 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10959 12:30:29.715929 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10960 12:30:29.733285 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10961 12:30:29.762667 Starting [0;1;39mPermit User Sessions[0m...
10962 12:30:29.890216 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10963 12:30:29.926312 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10964 12:30:29.975057 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 12:30:29.992742 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 12:30:30.010854 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10967 12:30:30.032300 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10968 12:30:30.051507 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10969 12:30:30.066298 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10970 12:30:30.114355 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 12:30:30.149794 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10972 12:30:30.238397
10973 12:30:30.238553
10974 12:30:30.241716 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10975 12:30:30.241810
10976 12:30:30.245007 debian-bullseye-arm64 login: root (automatic login)
10977 12:30:30.245093
10978 12:30:30.245160
10979 12:30:30.467086 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
10980 12:30:30.467277
10981 12:30:30.473783 The programs included with the Debian GNU/Linux system are free software;
10982 12:30:30.480177 the exact distribution terms for each program are described in the
10983 12:30:30.483762 individual files in /usr/share/doc/*/copyright.
10984 12:30:30.483873
10985 12:30:30.490360 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10986 12:30:30.493174 permitted by applicable law.
10987 12:30:30.514380 Matched prompt #10: / #
10989 12:30:30.514775 Setting prompt string to ['/ #']
10990 12:30:30.514908 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10992 12:30:30.515228 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10993 12:30:30.515357 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
10994 12:30:30.515464 Setting prompt string to ['/ #']
10995 12:30:30.515561 Forcing a shell prompt, looking for ['/ #']
10997 12:30:30.565830 / #
10998 12:30:30.566040 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10999 12:30:30.566159 Waiting using forced prompt support (timeout 00:02:30)
11000 12:30:30.570746
11001 12:30:30.571053 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11002 12:30:30.571150 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11004 12:30:30.671519 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj'
11005 12:30:30.676838 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605793/extract-nfsrootfs-zl0c9dyj'
11007 12:30:30.777419 / # export NFS_SERVER_IP='192.168.201.1'
11008 12:30:30.782214 export NFS_SERVER_IP='192.168.201.1'
11009 12:30:30.782539 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 12:30:30.782644 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11011 12:30:30.782739 end: 2 depthcharge-action (duration 00:01:24) [common]
11012 12:30:30.782834 start: 3 lava-test-retry (timeout 00:30:00) [common]
11013 12:30:30.782926 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11014 12:30:30.783003 Using namespace: common
11016 12:30:30.883314 / # #
11017 12:30:30.883526 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11018 12:30:30.888424 #
11019 12:30:30.888697 Using /lava-10605793
11021 12:30:30.989105 / # export SHELL=/bin/sh
11022 12:30:30.994033 export SHELL=/bin/sh
11024 12:30:31.094635 / # . /lava-10605793/environment
11025 12:30:31.099345 . /lava-10605793/environment
11027 12:30:31.203790 / # /lava-10605793/bin/lava-test-runner /lava-10605793/0
11028 12:30:31.203985 Test shell timeout: 10s (minimum of the action and connection timeout)
11029 12:30:31.208589 /lava-10605793/bin/lava-test-runner /lava-10605793/0
11030 12:30:31.380115 + export TESTRUN_ID=0_lc-compliance
11031 12:30:31.386394 + cd /lava-10605793/0/tests/0_lc-compliance
11032 12:30:31.386481 + cat uuid
11033 12:30:31.389779 + UUID=10605793_1.6.2.3.1
11034 12:30:31.389873 + set +x
11035 12:30:31.392689 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10605793_1.6.2.3.1>
11036 12:30:31.392957 Received signal: <STARTRUN> 0_lc-compliance 10605793_1.6.2.3.1
11037 12:30:31.393032 Starting test lava.0_lc-compliance (10605793_1.6.2.3.1)
11038 12:30:31.393133 Skipping test definition patterns.
11039 12:30:31.396057 + /usr/bin/lc-compliance-parser.sh
11040 12:30:32.508744 [0:00:28.257028847] [404] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11041 12:30:32.512092 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11042 12:30:32.525569 [0:00:28.273016309] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11043 12:30:32.574634 [==========] Running 120 tests from 1 test suite.
11044 12:30:32.584413 [0:00:28.334727539] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11045 12:30:32.627143 [----------] Global test environment set-up.
11046 12:30:32.642807 [0:00:28.391182155] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11047 12:30:32.678490 [----------] 120 tests from CaptureTests/SingleStream
11048 12:30:32.699409 [0:00:28.447620232] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11049 12:30:32.732619 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11050 12:30:32.769077 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11051 12:30:32.769411 Received signal: <TESTSET> START CaptureTests/SingleStream
11052 12:30:32.769496 Starting test_set CaptureTests/SingleStream
11053 12:30:32.772507 Camera needs 4 requests, can't test only 1
11054 12:30:32.811604 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11055 12:30:32.851069
11056 12:30:32.901332 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (62 ms)
11057 12:30:32.958902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11058 12:30:32.959240 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11060 12:30:32.970050 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11061 12:30:33.007669 Camera needs 4 requests, can't test only 2
11062 12:30:33.065097 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11063 12:30:33.113322
11064 12:30:33.131271 [0:00:28.879782616] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11065 12:30:33.175279 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (57 ms)
11066 12:30:33.227942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11067 12:30:33.228269 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11069 12:30:33.237316 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11070 12:30:33.269490 Camera needs 4 requests, can't test only 3
11071 12:30:33.310797 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11072 12:30:33.349221
11073 12:30:33.400990 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (56 ms)
11074 12:30:33.458298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11075 12:30:33.458643 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11077 12:30:33.470759 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11078 12:30:33.511464 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (432 ms)
11079 12:30:33.568068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11080 12:30:33.568437 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11082 12:30:33.578450 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11083 12:30:33.624652 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (502 ms)
11084 12:30:33.634686 [0:00:29.383066539] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 12:30:33.687726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11086 12:30:33.688064 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11088 12:30:33.698656 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11089 12:30:34.324113 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (699 ms)
11090 12:30:34.333913 [0:00:30.082359232] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 12:30:34.402125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11092 12:30:34.402461 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11094 12:30:34.411326 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11095 12:30:35.261778 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (938 ms)
11096 12:30:35.271447 [0:00:31.019657078] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 12:30:35.333335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11098 12:30:35.334283 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11100 12:30:35.345371 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11101 12:30:36.660842 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1399 ms)
11102 12:30:36.670205 [0:00:32.418640232] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 12:30:36.732507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11104 12:30:36.732826 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11106 12:30:36.741951 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11107 12:30:38.759687 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2099 ms)
11108 12:30:38.769440 [0:00:34.517697001] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 12:30:38.825384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11110 12:30:38.826399 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11112 12:30:38.837831 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11113 12:30:41.960834 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3202 ms)
11114 12:30:41.970686 [0:00:37.719706694] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 12:30:42.030148 [0:00:37.779268309] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11116 12:30:42.042632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11117 12:30:42.043343 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11119 12:30:42.055851 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11120 12:30:42.086389 [0:00:37.835515232] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 12:30:42.100514 Camera needs 4 requests, can't test only 1
11122 12:30:42.146165 [0:00:37.895370002] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11123 12:30:42.167326 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11124 12:30:42.213719
11125 12:30:42.264283 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (60 ms)
11126 12:30:42.328972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11127 12:30:42.329725 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11129 12:30:42.341649 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11130 12:30:42.385536 Camera needs 4 requests, can't test only 2
11131 12:30:42.453434 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11132 12:30:42.522008
11133 12:30:42.579751 [0:00:38.328725002] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11134 12:30:42.602116 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (57 ms)
11135 12:30:42.665398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11136 12:30:42.665738 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11138 12:30:42.675578 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11139 12:30:42.711529 Camera needs 4 requests, can't test only 3
11140 12:30:42.766337 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11141 12:30:42.816953
11142 12:30:42.878375 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (58 ms)
11143 12:30:42.946171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11144 12:30:42.946472 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11146 12:30:42.960254 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11147 12:30:42.998215 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (434 ms)
11148 12:30:43.071747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11149 12:30:43.072579 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11151 12:30:43.085248 [0:00:38.830634463] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11152 12:30:43.092061 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11153 12:30:43.133722 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (501 ms)
11154 12:30:43.195960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11155 12:30:43.196385 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11157 12:30:43.206867 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11158 12:30:43.772006 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (700 ms)
11159 12:30:43.785041 [0:00:39.531184309] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11160 12:30:43.835006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11161 12:30:43.835341 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11163 12:30:43.845247 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11164 12:30:44.771433 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1000 ms)
11165 12:30:44.784275 [0:00:40.530849925] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 12:30:44.832083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11167 12:30:44.832395 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11169 12:30:44.841706 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11170 12:30:46.170219 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1399 ms)
11171 12:30:46.183430 [0:00:41.930234079] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 12:30:46.231308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11173 12:30:46.231600 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11175 12:30:46.240851 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11176 12:30:48.270196 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2100 ms)
11177 12:30:48.282904 [0:00:44.030031233] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 12:30:48.330527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11179 12:30:48.330811 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11181 12:30:48.340208 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11182 12:30:50.284214 <6>[ 46.154958] vpu: disabling
11183 12:30:50.287259 <6>[ 46.158008] vproc2: disabling
11184 12:30:50.290799 <6>[ 46.161281] vproc1: disabling
11185 12:30:50.294136 <6>[ 46.164542] vaud18: disabling
11186 12:30:50.300625 <6>[ 46.167948] vsram_others: disabling
11187 12:30:50.300756 <6>[ 46.171819] va09: disabling
11188 12:30:50.307159 <6>[ 46.174922] vsram_md: disabling
11189 12:30:50.307246 <6>[ 46.178414] Vgpu: disabling
11190 12:30:51.536662 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3267 ms)
11191 12:30:51.549738 [0:00:47.296337925] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11192 12:30:51.593663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11193 12:30:51.594016 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11195 12:30:51.606566 [0:00:47.354772156] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11196 12:30:51.609779 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11197 12:30:51.641836 Camera needs 4 requests, can't test only 1
11198 12:30:51.660678 [0:00:47.411228233] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11199 12:30:51.692045 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11200 12:30:51.716932 [0:00:47.467666694] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11201 12:30:51.747957
11202 12:30:51.793981 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (58 ms)
11203 12:30:51.854143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11204 12:30:51.854509 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11206 12:30:51.865603 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11207 12:30:51.902845 Camera needs 4 requests, can't test only 2
11208 12:30:51.959246 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11209 12:30:52.010241
11210 12:30:52.072795 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (58 ms)
11211 12:30:52.085640 [0:00:47.836284694] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 12:30:52.140777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11213 12:30:52.141109 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11215 12:30:52.154734 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11216 12:30:52.191822 Camera needs 4 requests, can't test only 3
11217 12:30:52.243690 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11218 12:30:52.290880
11219 12:30:52.337207 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
11220 12:30:52.399425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11221 12:30:52.399800 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11223 12:30:52.409626 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11224 12:30:52.442497 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (369 ms)
11225 12:30:52.490393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11226 12:30:52.490706 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11228 12:30:52.500697 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11229 12:30:52.547085 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (469 ms)
11230 12:30:52.560291 [0:00:48.307419925] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 12:30:52.609760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11232 12:30:52.610077 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11234 12:30:52.619934 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11235 12:30:53.280802 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (734 ms)
11236 12:30:53.293819 [0:00:49.039941310] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11237 12:30:53.350368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11238 12:30:53.351032 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11240 12:30:53.360569 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11241 12:30:54.183147 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (902 ms)
11242 12:30:54.196676 [0:00:49.943375925] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 12:30:54.249931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11244 12:30:54.250246 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11246 12:30:54.259497 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11247 12:30:55.584549 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1399 ms)
11248 12:30:55.594794 [0:00:51.342042002] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 12:30:55.649096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11250 12:30:55.649395 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11252 12:30:55.659597 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11253 12:30:57.681309 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2100 ms)
11254 12:30:57.694531 [0:00:53.442346233] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11255 12:30:57.754315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11256 12:30:57.755075 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11258 12:30:57.764927 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11259 12:31:00.883526 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3202 ms)
11260 12:31:00.896393 [0:00:56.644175685] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 12:31:00.948902 [0:00:56.700188595] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 12:31:00.955024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11263 12:31:00.955287 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11265 12:31:00.963376 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11266 12:31:00.992794 Camera needs 4 requests, can't test only 1
11267 12:31:01.002517 [0:00:56.756395203] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11268 12:31:01.042565 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11269 12:31:01.063440 [0:00:56.814927199] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11270 12:31:01.091319
11271 12:31:01.139412 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11272 12:31:01.196357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11273 12:31:01.196691 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11275 12:31:01.206914 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11276 12:31:01.244560 Camera needs 4 requests, can't test only 2
11277 12:31:01.301046 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11278 12:31:01.353865
11279 12:31:01.418831 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11280 12:31:01.495772 [0:00:57.246722920] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11281 12:31:01.502043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11282 12:31:01.502775 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11284 12:31:01.513142 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11285 12:31:01.555052 Camera needs 4 requests, can't test only 3
11286 12:31:01.614216 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11287 12:31:01.661973
11288 12:31:01.715586 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (57 ms)
11289 12:31:01.777920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11290 12:31:01.778212 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11292 12:31:01.792318 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11293 12:31:01.829922 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (433 ms)
11294 12:31:01.886721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11295 12:31:01.887200 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11297 12:31:01.896864 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11298 12:31:01.987571 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (501 ms)
11299 12:31:02.001000 [0:00:57.748031790] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 12:31:02.074091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11301 12:31:02.074981 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11303 12:31:02.086940 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11304 12:31:02.687814 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (700 ms)
11305 12:31:02.700933 [0:00:58.448228554] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 12:31:02.749585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11307 12:31:02.750032 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11309 12:31:02.757535 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11310 12:31:03.623028 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (936 ms)
11311 12:31:03.636168 [0:00:59.383399987] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 12:31:03.683811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11313 12:31:03.684152 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11315 12:31:03.693018 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11316 12:31:05.020271 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1397 ms)
11317 12:31:05.033234 [0:01:00.780297263] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 12:31:05.085177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11319 12:31:05.085599 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11321 12:31:05.095412 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11322 12:31:07.117875 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2098 ms)
11323 12:31:07.130838 [0:01:02.879478231] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11324 12:31:07.179117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11325 12:31:07.179515 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11327 12:31:07.189854 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11328 12:31:10.382032 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3265 ms)
11329 12:31:10.395026 [0:01:06.143543991] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 12:31:10.446910 [0:01:06.200289919] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11331 12:31:10.841829 [0:01:06.257181158] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 12:31:10.842218 [0:01:06.312359672] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11333 12:31:10.848929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11334 12:31:10.849196 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11336 12:31:10.859358 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11337 12:31:10.893270 Camera needs 4 requests, can't test only 1
11338 12:31:10.946965 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11339 12:31:10.989682
11340 12:31:11.038819 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11341 12:31:11.275864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11342 12:31:11.276199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11344 12:31:11.287538 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11345 12:31:11.319326 Camera needs 4 requests, can't test only 2
11346 12:31:11.375242 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11347 12:31:11.416979
11348 12:31:11.463436 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11349 12:31:11.690974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11350 12:31:11.691307 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11352 12:31:11.699475 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11353 12:31:11.732674 Camera needs 4 requests, can't test only 3
11354 12:31:11.754053 [0:01:07.507215558] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 12:31:11.789214 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11356 12:31:11.832751
11357 12:31:11.881923 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11358 12:31:12.107642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11359 12:31:12.108005 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11361 12:31:12.117739 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11362 12:31:12.152413 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1195 ms)
11363 12:31:12.207442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11364 12:31:12.207790 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11366 12:31:12.221409 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11367 12:31:13.140880 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1395 ms)
11368 12:31:13.154222 [0:01:08.903310536] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 12:31:13.461104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11370 12:31:13.461474 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11372 12:31:13.471067 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11373 12:31:15.196593 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2056 ms)
11374 12:31:15.209394 [0:01:10.959442762] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 12:31:15.264528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11376 12:31:15.264881 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11378 12:31:15.273400 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11379 12:31:17.985879 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2789 ms)
11380 12:31:17.998618 [0:01:13.748147913] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 12:31:18.046411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11382 12:31:18.046741 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11384 12:31:18.055141 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11385 12:31:22.171379 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4186 ms)
11386 12:31:22.184312 [0:01:17.935331971] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 12:31:22.227511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11388 12:31:22.227847 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11390 12:31:22.236567 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11391 12:31:28.489875 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6320 ms)
11392 12:31:28.502858 [0:01:24.254704276] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11393 12:31:28.548113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11394 12:31:28.548422 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11396 12:31:28.558810 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11397 12:31:38.112232 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9624 ms)
11398 12:31:38.125732 [0:01:33.878730374] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 12:31:38.178445 [0:01:33.935228859] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11400 12:31:38.233826 [0:01:33.990253262] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11401 12:31:38.240194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11402 12:31:38.240515 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11404 12:31:38.246953 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11405 12:31:38.274458 Camera needs 4 requests, can't test only 1
11406 12:31:38.291155 [0:01:34.047900981] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11407 12:31:38.328937 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11408 12:31:38.365105
11409 12:31:38.413180 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11410 12:31:38.584450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11411 12:31:38.584811 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11413 12:31:38.591927 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11414 12:31:38.624978 Camera needs 4 requests, can't test only 2
11415 12:31:38.680352 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11416 12:31:38.723879
11417 12:31:38.776408 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11418 12:31:38.831570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11419 12:31:38.831913 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11421 12:31:38.837952 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11422 12:31:38.871003 Camera needs 4 requests, can't test only 3
11423 12:31:38.920455 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11424 12:31:38.961548
11425 12:31:39.019017 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (58 ms)
11426 12:31:39.106475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11427 12:31:39.106816 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11429 12:31:39.113237 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11430 12:31:39.485074 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1199 ms)
11431 12:31:39.495021 [0:01:35.246634664] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11432 12:31:39.729829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11433 12:31:39.730184 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11435 12:31:39.736144 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11436 12:31:40.893166 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1396 ms)
11437 12:31:40.893307 [0:01:36.642394450] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 12:31:40.976470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11439 12:31:40.976653 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11440 12:31:40.976938 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11442 12:31:42.998670 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2118 ms)
11443 12:31:43.008279 [0:01:38.760393286] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 12:31:43.177247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11445 12:31:43.177574 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11447 12:31:43.184559 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11448 12:31:45.722949 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2725 ms)
11449 12:31:45.732994 [0:01:41.484875051] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 12:31:45.789578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11451 12:31:45.789891 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11453 12:31:45.798553 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11454 12:31:49.844002 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4121 ms)
11455 12:31:49.853824 [0:01:45.606290959] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 12:31:49.926214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11457 12:31:49.926963 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11459 12:31:49.934253 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11460 12:31:56.161256 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6318 ms)
11461 12:31:56.170834 [0:01:51.924424865] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 12:31:56.232374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11463 12:31:56.232704 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11465 12:31:56.241576 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11466 12:32:05.781382 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9621 ms)
11467 12:32:05.791165 [0:02:01.545949563] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 12:32:05.842468 [0:02:01.602645697] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11469 12:32:05.855137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11470 12:32:05.855412 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11472 12:32:05.862198 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11473 12:32:05.899017 [0:02:01.658759907] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 12:32:05.902091 Camera needs 4 requests, can't test only 1
11475 12:32:05.948623 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11476 12:32:05.958502 [0:02:01.716367414] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11477 12:32:06.003242
11478 12:32:06.061281 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (56 ms)
11479 12:32:06.124602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11480 12:32:06.124979 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11482 12:32:06.132271 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11483 12:32:06.164594 Camera needs 4 requests, can't test only 2
11484 12:32:06.212521 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11485 12:32:06.255430
11486 12:32:06.309467 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11487 12:32:06.364010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11488 12:32:06.364330 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11490 12:32:06.370854 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11491 12:32:06.407321 Camera needs 4 requests, can't test only 3
11492 12:32:06.452741 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11493 12:32:06.494238
11494 12:32:06.541091 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11495 12:32:06.588647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11496 12:32:06.588995 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11498 12:32:06.594842 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11499 12:32:07.145336 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1193 ms)
11500 12:32:07.154703 [0:02:02.909324061] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 12:32:07.209004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11502 12:32:07.209354 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11504 12:32:07.215562 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11505 12:32:08.534742 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1389 ms)
11506 12:32:08.544300 [0:02:04.298460434] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 12:32:08.605410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11508 12:32:08.605776 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11510 12:32:08.614373 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11511 12:32:10.589477 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2055 ms)
11512 12:32:10.599138 [0:02:06.355283182] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 12:32:10.651857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11514 12:32:10.652157 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11516 12:32:10.658325 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11517 12:32:13.318815 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2729 ms)
11518 12:32:13.328741 [0:02:09.084363504] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 12:32:13.392425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11520 12:32:13.392779 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11522 12:32:13.399535 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11523 12:32:17.443438 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4124 ms)
11524 12:32:17.453695 [0:02:13.206980360] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 12:32:17.504776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11526 12:32:17.505085 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11528 12:32:17.511398 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11529 12:32:23.761239 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6317 ms)
11530 12:32:23.771632 [0:02:19.525014689] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 12:32:23.820922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11532 12:32:23.821312 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11534 12:32:23.830424 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11535 12:32:33.448078 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9686 ms)
11536 12:32:33.457976 [0:02:29.212062461] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 12:32:33.510673 [0:02:29.268590457] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11538 12:32:33.517108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11539 12:32:33.517393 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11541 12:32:33.524961 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11542 12:32:33.555685 Camera needs 4 requests, can't test only 1
11543 12:32:33.568892 [0:02:29.326624950] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 12:32:33.610592 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11545 12:32:33.626387 [0:02:29.384141202] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11546 12:32:33.661746
11547 12:32:33.715899 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11548 12:32:33.765754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11549 12:32:33.766079 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11551 12:32:33.772571 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11552 12:32:33.805293 Camera needs 4 requests, can't test only 2
11553 12:32:33.850947 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11554 12:32:33.895493
11555 12:32:33.952617 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11556 12:32:34.003063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11557 12:32:34.003409 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11559 12:32:34.009597 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11560 12:32:34.042922 Camera needs 4 requests, can't test only 3
11561 12:32:34.100845 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11562 12:32:34.144945
11563 12:32:34.205243 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (59 ms)
11564 12:32:34.269388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11565 12:32:34.269710 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11567 12:32:34.278621 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11568 12:32:34.814039 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1192 ms)
11569 12:32:34.823948 [0:02:30.578743964] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11570 12:32:34.880388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11571 12:32:34.880681 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11573 12:32:34.886951 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11574 12:32:36.207053 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1393 ms)
11575 12:32:36.217172 [0:02:31.971693645] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11576 12:32:36.294194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11577 12:32:36.294544 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11579 12:32:36.302081 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11580 12:32:38.267118 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2060 ms)
11581 12:32:38.276734 [0:02:34.031209496] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 12:32:38.343879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11583 12:32:38.344979 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11585 12:32:38.353462 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11586 12:32:40.995245 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2728 ms)
11587 12:32:41.005262 [0:02:36.759767774] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 12:32:41.057935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11589 12:32:41.058243 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11591 12:32:41.066764 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11592 12:32:45.183990 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4189 ms)
11593 12:32:45.193346 [0:02:40.947643696] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 12:32:45.264970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11595 12:32:45.265273 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11597 12:32:45.271852 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11598 12:32:51.503677 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6320 ms)
11599 12:32:51.513745 [0:02:47.267860507] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 12:32:51.570087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11601 12:32:51.570421 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11603 12:32:51.580293 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11604 12:33:01.191155 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9688 ms)
11605 12:33:01.200776 [0:02:56.955572562] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 12:33:01.271240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11607 12:33:01.271690 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11609 12:33:01.279791 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11610 12:33:01.520983 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (333 ms)
11611 12:33:01.533795 [0:02:57.286776211] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 12:33:01.600381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11613 12:33:01.600663 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11615 12:33:01.613411 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11616 12:33:01.786944 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (266 ms)
11617 12:33:01.800051 [0:02:57.552923514] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 12:33:01.861272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11619 12:33:01.861579 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11621 12:33:01.877808 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11622 12:33:02.086812 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (300 ms)
11623 12:33:02.099607 [0:02:57.852450473] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 12:33:02.163359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11625 12:33:02.164184 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11627 12:33:02.176110 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11628 12:33:02.518535 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (431 ms)
11629 12:33:02.531386 [0:02:58.286457586] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 12:33:02.579602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11631 12:33:02.579894 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11633 12:33:02.591477 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11634 12:33:03.020209 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (502 ms)
11635 12:33:03.033067 [0:02:58.787949614] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 12:33:03.094172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11637 12:33:03.094935 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11639 12:33:03.105231 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11640 12:33:03.719832 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (700 ms)
11641 12:33:03.732728 [0:02:59.487520753] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 12:33:03.783776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11643 12:33:03.784079 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11645 12:33:03.794492 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11646 12:33:04.719431 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (999 ms)
11647 12:33:04.732145 [0:03:00.487410667] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 12:33:04.791411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11649 12:33:04.792370 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11651 12:33:04.801689 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11652 12:33:06.118476 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1400 ms)
11653 12:33:06.131838 [0:03:01.886541991] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 12:33:06.199595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11655 12:33:06.200329 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11657 12:33:06.214301 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11658 12:33:08.249851 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2131 ms)
11659 12:33:08.262703 [0:03:04.016823931] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 12:33:08.315088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11661 12:33:08.315374 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11663 12:33:08.324576 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11664 12:33:11.481149 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3231 ms)
11665 12:33:11.494425 [0:03:07.248565595] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 12:33:11.553858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11667 12:33:11.554175 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11669 12:33:11.564166 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11670 12:33:11.784501 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (300 ms)
11671 12:33:11.794219 [0:03:07.548894880] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 12:33:11.850060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11673 12:33:11.850362 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11675 12:33:11.857127 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11676 12:33:12.085626 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (301 ms)
11677 12:33:12.095354 [0:03:07.851255070] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 12:33:12.160922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11679 12:33:12.161634 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11681 12:33:12.168396 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11682 12:33:12.388581 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (303 ms)
11683 12:33:12.398318 [0:03:08.152801384] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 12:33:12.462255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11685 12:33:12.463043 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11687 12:33:12.471407 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11688 12:33:12.854676 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (465 ms)
11689 12:33:12.864396 [0:03:08.619347710] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 12:33:12.929845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11691 12:33:12.930126 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11693 12:33:12.936416 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11694 12:33:13.419976 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (566 ms)
11695 12:33:13.429500 [0:03:09.184366150] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 12:33:13.481263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11697 12:33:13.481662 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11699 12:33:13.489483 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11700 12:33:14.119158 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (699 ms)
11701 12:33:14.129107 [0:03:09.882552424] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 12:33:14.191684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11703 12:33:14.191964 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11705 12:33:14.199193 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11706 12:33:15.019072 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (900 ms)
11707 12:33:15.028831 [0:03:10.782489719] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 12:33:15.092207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11709 12:33:15.092509 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11711 12:33:15.100608 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11712 12:33:16.352864 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1335 ms)
11713 12:33:16.362831 [0:03:12.116508144] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 12:33:16.412407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11715 12:33:16.412738 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11717 12:33:16.418947 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11718 12:33:18.450629 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2097 ms)
11719 12:33:18.460341 [0:03:14.214866548] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 12:33:18.526202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11721 12:33:18.526559 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11723 12:33:18.536487 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11724 12:33:21.649547 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3199 ms)
11725 12:33:21.659628 [0:03:17.414120783] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 12:33:21.719922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11727 12:33:21.720305 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11729 12:33:21.726329 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11730 12:33:21.948393 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (299 ms)
11731 12:33:21.957883 [0:03:17.712569184] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 12:33:22.020374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11733 12:33:22.020643 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11735 12:33:22.029642 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11736 12:33:22.215362 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (267 ms)
11737 12:33:22.224681 [0:03:17.979902372] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 12:33:22.277413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11739 12:33:22.277705 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11741 12:33:22.283990 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11742 12:33:22.515873 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (301 ms)
11743 12:33:22.525913 [0:03:18.280365194] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 12:33:22.588162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11745 12:33:22.588484 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11747 12:33:22.594679 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11748 12:33:22.882416 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (366 ms)
11749 12:33:22.892243 [0:03:18.646389952] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 12:33:22.948686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11751 12:33:22.949484 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11753 12:33:22.958227 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11754 12:33:23.349112 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (467 ms)
11755 12:33:23.358872 [0:03:19.112992150] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 12:33:23.421862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11757 12:33:23.422134 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11759 12:33:23.428612 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11760 12:33:24.045772 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (697 ms)
11761 12:33:24.055705 [0:03:19.810276351] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 12:33:24.107326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11763 12:33:24.107689 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11765 12:33:24.114427 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11766 12:33:24.981096 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (935 ms)
11767 12:33:24.990950 [0:03:20.745554469] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 12:33:25.037313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11769 12:33:25.037631 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11771 12:33:25.043876 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11772 12:33:26.378216 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1398 ms)
11773 12:33:26.388542 [0:03:22.142825253] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 12:33:26.435495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11775 12:33:26.435824 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11777 12:33:26.442209 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11778 12:33:28.475258 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2097 ms)
11779 12:33:28.485041 [0:03:24.239864325] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 12:33:28.541164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11781 12:33:28.541460 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11783 12:33:28.547788 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11784 12:33:31.675722 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3200 ms)
11785 12:33:31.685267 [0:03:27.440339764] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 12:33:31.739571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11787 12:33:31.739901 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11789 12:33:31.745896 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11790 12:33:32.007757 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (332 ms)
11791 12:33:32.017341 [0:03:27.772535396] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 12:33:32.079205 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11794 12:33:32.082567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11795 12:33:32.089481 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11796 12:33:32.372993 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (364 ms)
11797 12:33:32.382653 [0:03:28.138124948] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 12:33:32.436301 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11800 12:33:32.439467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11801 12:33:32.445982 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11802 12:33:32.675599 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (302 ms)
11803 12:33:32.685444 [0:03:28.440183499] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 12:33:32.738051 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11806 12:33:32.741185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11807 12:33:32.748087 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11808 12:33:33.043256 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (368 ms)
11809 12:33:33.053103 [0:03:28.808411387] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 12:33:33.111892 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11812 12:33:33.114964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11813 12:33:33.122989 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11814 12:33:33.510469 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (467 ms)
11815 12:33:33.520269 [0:03:29.275197016] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 12:33:33.577682 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11818 12:33:33.580592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11819 12:33:33.588786 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11820 12:33:34.208984 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (699 ms)
11821 12:33:34.219001 [0:03:29.974085811] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 12:33:34.268641 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11824 12:33:34.271654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11825 12:33:34.278821 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11826 12:33:35.208292 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (999 ms)
11827 12:33:35.218139 [0:03:30.973917042] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 12:33:35.276995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11829 12:33:35.277336 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11831 12:33:35.285819 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11832 12:33:36.543693 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1336 ms)
11833 12:33:36.553973 [0:03:32.309013471] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 12:33:36.616147 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11836 12:33:36.619048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11837 12:33:36.625628 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11838 12:33:38.642246 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2099 ms)
11839 12:33:38.652143 [0:03:34.407750893] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 12:33:38.713022 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11842 12:33:38.715981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11843 12:33:38.725532 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11844 12:33:41.842153 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3200 ms)
11845 12:33:41.902348 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11847 12:33:41.905016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11848 12:33:41.912762 [----------] 120 tests from CaptureTests/SingleStream (189336 ms total)
11849 12:33:41.956701
11850 12:33:42.007838 [----------] Global test environment tear-down
11851 12:33:42.052307 [==========] 120 tests from 1 test suite ran. (189337 ms total)
11852 12:33:42.096039 <LAVA_SIGNAL_TESTSET STOP>
11853 12:33:42.096385 Received signal: <TESTSET> STOP
11854 12:33:42.096470 Closing test_set CaptureTests/SingleStream
11855 12:33:42.101357 + set +x
11856 12:33:42.104654 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10605793_1.6.2.3.1>
11857 12:33:42.104946 Received signal: <ENDRUN> 0_lc-compliance 10605793_1.6.2.3.1
11858 12:33:42.105032 Ending use of test pattern.
11859 12:33:42.105098 Ending test lava.0_lc-compliance (10605793_1.6.2.3.1), duration 190.71
11861 12:33:42.107854 <LAVA_TEST_RUNNER EXIT>
11862 12:33:42.108099 ok: lava_test_shell seems to have completed
11863 12:33:42.110973 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11864 12:33:42.111184 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11865 12:33:42.111309 end: 3 lava-test-retry (duration 00:03:11) [common]
11866 12:33:42.111428 start: 4 finalize (timeout 00:10:00) [common]
11867 12:33:42.111553 start: 4.1 power-off (timeout 00:00:30) [common]
11868 12:33:42.111860 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11869 12:33:42.186416 >> Command sent successfully.
11870 12:33:42.189086 Returned 0 in 0 seconds
11871 12:33:42.289500 end: 4.1 power-off (duration 00:00:00) [common]
11873 12:33:42.289838 start: 4.2 read-feedback (timeout 00:10:00) [common]
11874 12:33:42.290101 Listened to connection for namespace 'common' for up to 1s
11875 12:33:43.291060 Finalising connection for namespace 'common'
11876 12:33:43.291226 Disconnecting from shell: Finalise
11877 12:33:43.291310 / #
11878 12:33:43.391661 end: 4.2 read-feedback (duration 00:00:01) [common]
11879 12:33:43.391861 end: 4 finalize (duration 00:00:01) [common]
11880 12:33:43.391979 Cleaning after the job
11881 12:33:43.392079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/ramdisk
11882 12:33:43.394441 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/kernel
11883 12:33:43.404434 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/dtb
11884 12:33:43.404719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/nfsrootfs
11885 12:33:43.452868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605793/tftp-deploy-se3bmgto/modules
11886 12:33:43.459254 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605793
11887 12:33:43.725508 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605793
11888 12:33:43.725697 Job finished correctly