Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 34
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 27
1 12:25:17.401524 lava-dispatcher, installed at version: 2023.05.1
2 12:25:17.401740 start: 0 validate
3 12:25:17.401886 Start time: 2023-06-06 12:25:17.401878+00:00 (UTC)
4 12:25:17.402021 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:25:17.402154 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:25:17.942021 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:25:17.942200 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:26:09.013247 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:26:09.013428 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:26:09.300599 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:26:09.300772 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:26:21.372841 validate duration: 63.97
14 12:26:21.373129 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:26:21.373230 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:26:21.373315 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:26:21.373441 Not decompressing ramdisk as can be used compressed.
18 12:26:21.373528 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 12:26:21.373592 saving as /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/ramdisk/rootfs.cpio.gz
20 12:26:21.373652 total size: 27151647 (25MB)
21 12:26:21.667005 progress 0% (0MB)
22 12:26:21.674144 progress 5% (1MB)
23 12:26:21.681414 progress 10% (2MB)
24 12:26:21.689390 progress 15% (3MB)
25 12:26:21.696417 progress 20% (5MB)
26 12:26:21.703824 progress 25% (6MB)
27 12:26:21.711053 progress 30% (7MB)
28 12:26:21.718160 progress 35% (9MB)
29 12:26:21.725179 progress 40% (10MB)
30 12:26:21.732188 progress 45% (11MB)
31 12:26:21.739344 progress 50% (12MB)
32 12:26:21.746315 progress 55% (14MB)
33 12:26:21.753479 progress 60% (15MB)
34 12:26:21.760877 progress 65% (16MB)
35 12:26:21.768430 progress 70% (18MB)
36 12:26:21.775633 progress 75% (19MB)
37 12:26:21.783067 progress 80% (20MB)
38 12:26:21.790591 progress 85% (22MB)
39 12:26:21.797786 progress 90% (23MB)
40 12:26:21.804936 progress 95% (24MB)
41 12:26:21.811817 progress 100% (25MB)
42 12:26:21.812070 25MB downloaded in 0.44s (59.06MB/s)
43 12:26:21.812234 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:26:21.812479 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:26:21.812592 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:26:21.812681 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:26:21.812811 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:26:21.812885 saving as /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/kernel/Image
50 12:26:21.812948 total size: 45746688 (43MB)
51 12:26:21.813010 No compression specified
52 12:26:21.814128 progress 0% (0MB)
53 12:26:21.825716 progress 5% (2MB)
54 12:26:21.837670 progress 10% (4MB)
55 12:26:21.849496 progress 15% (6MB)
56 12:26:21.861740 progress 20% (8MB)
57 12:26:21.874083 progress 25% (10MB)
58 12:26:21.886096 progress 30% (13MB)
59 12:26:21.898311 progress 35% (15MB)
60 12:26:21.910523 progress 40% (17MB)
61 12:26:21.922336 progress 45% (19MB)
62 12:26:21.934124 progress 50% (21MB)
63 12:26:21.945941 progress 55% (24MB)
64 12:26:21.958215 progress 60% (26MB)
65 12:26:21.970860 progress 65% (28MB)
66 12:26:21.983091 progress 70% (30MB)
67 12:26:21.995137 progress 75% (32MB)
68 12:26:22.007138 progress 80% (34MB)
69 12:26:22.019213 progress 85% (37MB)
70 12:26:22.031412 progress 90% (39MB)
71 12:26:22.043607 progress 95% (41MB)
72 12:26:22.055714 progress 100% (43MB)
73 12:26:22.055928 43MB downloaded in 0.24s (179.56MB/s)
74 12:26:22.056134 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:26:22.056534 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:26:22.056638 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:26:22.056736 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:26:22.056873 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:26:22.056949 saving as /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/dtb/mt8192-asurada-spherion-r0.dtb
81 12:26:22.057013 total size: 46924 (0MB)
82 12:26:22.057075 No compression specified
83 12:26:22.351860 progress 69% (0MB)
84 12:26:22.352202 progress 100% (0MB)
85 12:26:22.352397 0MB downloaded in 0.30s (0.15MB/s)
86 12:26:22.352605 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:26:22.352876 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:26:22.352997 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:26:22.353119 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:26:22.353285 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:26:22.353383 saving as /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/modules/modules.tar
93 12:26:22.353479 total size: 8539116 (8MB)
94 12:26:22.353574 Using unxz to decompress xz
95 12:26:22.357510 progress 0% (0MB)
96 12:26:22.380295 progress 5% (0MB)
97 12:26:22.407170 progress 10% (0MB)
98 12:26:22.432829 progress 15% (1MB)
99 12:26:22.464540 progress 20% (1MB)
100 12:26:22.493034 progress 25% (2MB)
101 12:26:22.520533 progress 30% (2MB)
102 12:26:22.548933 progress 35% (2MB)
103 12:26:22.576534 progress 40% (3MB)
104 12:26:22.602763 progress 45% (3MB)
105 12:26:22.630579 progress 50% (4MB)
106 12:26:22.656965 progress 55% (4MB)
107 12:26:22.684652 progress 60% (4MB)
108 12:26:22.712737 progress 65% (5MB)
109 12:26:22.740445 progress 70% (5MB)
110 12:26:22.769744 progress 75% (6MB)
111 12:26:22.804071 progress 80% (6MB)
112 12:26:22.828650 progress 85% (6MB)
113 12:26:22.855476 progress 90% (7MB)
114 12:26:22.882334 progress 95% (7MB)
115 12:26:22.910526 progress 100% (8MB)
116 12:26:22.916755 8MB downloaded in 0.56s (14.46MB/s)
117 12:26:22.917138 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:26:22.917609 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:26:22.917756 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:26:22.917906 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:26:22.918032 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:26:22.918159 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:26:22.918476 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj
125 12:26:22.918677 makedir: /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin
126 12:26:22.918821 makedir: /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/tests
127 12:26:22.918991 makedir: /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/results
128 12:26:22.919153 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-add-keys
129 12:26:22.919378 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-add-sources
130 12:26:22.919546 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-background-process-start
131 12:26:22.919737 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-background-process-stop
132 12:26:22.919917 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-common-functions
133 12:26:22.920108 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-echo-ipv4
134 12:26:22.920283 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-install-packages
135 12:26:22.920469 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-installed-packages
136 12:26:22.920688 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-os-build
137 12:26:22.920884 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-probe-channel
138 12:26:22.921074 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-probe-ip
139 12:26:22.921268 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-target-ip
140 12:26:22.921462 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-target-mac
141 12:26:22.921641 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-target-storage
142 12:26:22.921843 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-case
143 12:26:22.922028 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-event
144 12:26:22.922210 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-feedback
145 12:26:22.922407 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-raise
146 12:26:22.922593 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-reference
147 12:26:22.922799 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-runner
148 12:26:22.922970 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-set
149 12:26:22.923157 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-test-shell
150 12:26:22.923331 Updating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-install-packages (oe)
151 12:26:22.923533 Updating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/bin/lava-installed-packages (oe)
152 12:26:22.923695 Creating /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/environment
153 12:26:22.923804 LAVA metadata
154 12:26:22.923894 - LAVA_JOB_ID=10605760
155 12:26:22.923962 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:26:22.924075 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 12:26:22.924165 skipped lava-vland-overlay
158 12:26:22.924247 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:26:22.924335 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 12:26:22.924416 skipped lava-multinode-overlay
161 12:26:22.924504 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:26:22.924612 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 12:26:22.924711 Loading test definitions
164 12:26:22.924810 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:58) [common]
165 12:26:22.924889 Using /lava-10605760 at stage 0
166 12:26:22.925225 uuid=10605760_1.5.2.3.1 testdef=None
167 12:26:22.925318 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:26:22.925424 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
169 12:26:22.925970 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:26:22.926223 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
172 12:26:22.926913 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:26:22.927170 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
175 12:26:22.928112 runner path: /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10605760_1.5.2.3.1
176 12:26:22.928360 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:26:22.928717 Creating lava-test-runner.conf files
179 12:26:22.928801 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605760/lava-overlay-o5g3zsdj/lava-10605760/0 for stage 0
180 12:26:22.928896 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:26:22.929024 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:26:22.929113 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
183 12:26:22.938583 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:26:22.938779 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
185 12:26:22.938953 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:26:22.939135 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:26:22.939311 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
188 12:26:23.694498 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:26:23.695041 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:26:23.695234 extracting modules file /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605760/extract-overlay-ramdisk-h3rtovp4/ramdisk
191 12:26:23.927192 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:26:23.927368 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:26:23.927475 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605760/compress-overlay-uryqtj7q/overlay-1.5.2.4.tar.gz to ramdisk
194 12:26:23.927553 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605760/compress-overlay-uryqtj7q/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605760/extract-overlay-ramdisk-h3rtovp4/ramdisk
195 12:26:23.934071 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:26:23.934203 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:26:23.934297 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:26:23.934388 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:26:23.934470 Building ramdisk /var/lib/lava/dispatcher/tmp/10605760/extract-overlay-ramdisk-h3rtovp4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605760/extract-overlay-ramdisk-h3rtovp4/ramdisk
200 12:26:24.697882 >> 230342 blocks
201 12:26:29.260729 rename /var/lib/lava/dispatcher/tmp/10605760/extract-overlay-ramdisk-h3rtovp4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/ramdisk/ramdisk.cpio.gz
202 12:26:29.261161 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:26:29.261310 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 12:26:29.261415 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 12:26:29.261522 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/kernel/Image'
206 12:26:43.757821 Returned 0 in 14 seconds
207 12:26:43.858442 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/kernel/image.itb
208 12:26:44.678595 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:26:44.678988 output: Created: Tue Jun 6 13:26:44 2023
210 12:26:44.679096 output: Image 0 (kernel-1)
211 12:26:44.679204 output: Description:
212 12:26:44.679309 output: Created: Tue Jun 6 13:26:44 2023
213 12:26:44.679420 output: Type: Kernel Image
214 12:26:44.679526 output: Compression: lzma compressed
215 12:26:44.679598 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
216 12:26:44.679662 output: Architecture: AArch64
217 12:26:44.679734 output: OS: Linux
218 12:26:44.679801 output: Load Address: 0x00000000
219 12:26:44.679911 output: Entry Point: 0x00000000
220 12:26:44.680014 output: Hash algo: crc32
221 12:26:44.680118 output: Hash value: a26c3f91
222 12:26:44.680211 output: Image 1 (fdt-1)
223 12:26:44.680303 output: Description: mt8192-asurada-spherion-r0
224 12:26:44.680392 output: Created: Tue Jun 6 13:26:44 2023
225 12:26:44.680482 output: Type: Flat Device Tree
226 12:26:44.680594 output: Compression: uncompressed
227 12:26:44.680680 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:26:44.680771 output: Architecture: AArch64
229 12:26:44.680857 output: Hash algo: crc32
230 12:26:44.680946 output: Hash value: 1df858fa
231 12:26:44.681031 output: Image 2 (ramdisk-1)
232 12:26:44.681119 output: Description: unavailable
233 12:26:44.681206 output: Created: Tue Jun 6 13:26:44 2023
234 12:26:44.681291 output: Type: RAMDisk Image
235 12:26:44.681381 output: Compression: Unknown Compression
236 12:26:44.681466 output: Data Size: 40144546 Bytes = 39203.66 KiB = 38.28 MiB
237 12:26:44.681557 output: Architecture: AArch64
238 12:26:44.681641 output: OS: Linux
239 12:26:44.681730 output: Load Address: unavailable
240 12:26:44.681815 output: Entry Point: unavailable
241 12:26:44.681907 output: Hash algo: crc32
242 12:26:44.681997 output: Hash value: 464cf7de
243 12:26:44.682082 output: Default Configuration: 'conf-1'
244 12:26:44.682169 output: Configuration 0 (conf-1)
245 12:26:44.682254 output: Description: mt8192-asurada-spherion-r0
246 12:26:44.682342 output: Kernel: kernel-1
247 12:26:44.682428 output: Init Ramdisk: ramdisk-1
248 12:26:44.682512 output: FDT: fdt-1
249 12:26:44.682600 output: Loadables: kernel-1
250 12:26:44.682684 output:
251 12:26:44.682928 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 12:26:44.683062 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 12:26:44.683212 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:26:44.683345 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 12:26:44.683460 No LXC device requested
256 12:26:44.683572 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:26:44.683665 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 12:26:44.683749 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:26:44.683823 Checking files for TFTP limit of 4294967296 bytes.
260 12:26:44.684477 end: 1 tftp-deploy (duration 00:00:23) [common]
261 12:26:44.684624 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:26:44.684765 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:26:44.684940 substitutions:
264 12:26:44.685041 - {DTB}: 10605760/tftp-deploy-v5jpqhoi/dtb/mt8192-asurada-spherion-r0.dtb
265 12:26:44.685142 - {INITRD}: 10605760/tftp-deploy-v5jpqhoi/ramdisk/ramdisk.cpio.gz
266 12:26:44.685233 - {KERNEL}: 10605760/tftp-deploy-v5jpqhoi/kernel/Image
267 12:26:44.685326 - {LAVA_MAC}: None
268 12:26:44.685416 - {PRESEED_CONFIG}: None
269 12:26:44.685508 - {PRESEED_LOCAL}: None
270 12:26:44.685595 - {RAMDISK}: 10605760/tftp-deploy-v5jpqhoi/ramdisk/ramdisk.cpio.gz
271 12:26:44.685689 - {ROOT_PART}: None
272 12:26:44.685784 - {ROOT}: None
273 12:26:44.685885 - {SERVER_IP}: 192.168.201.1
274 12:26:44.685975 - {TEE}: None
275 12:26:44.686067 Parsed boot commands:
276 12:26:44.686155 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:26:44.686378 Parsed boot commands: tftpboot 192.168.201.1 10605760/tftp-deploy-v5jpqhoi/kernel/image.itb 10605760/tftp-deploy-v5jpqhoi/kernel/cmdline
278 12:26:44.686501 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:26:44.686621 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:26:44.686751 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:26:44.686894 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:26:44.687013 Not connected, no need to disconnect.
283 12:26:44.687144 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:26:44.687272 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:26:44.687374 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
286 12:26:44.691250 Setting prompt string to ['lava-test: # ']
287 12:26:44.691685 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:26:44.691842 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:26:44.691980 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:26:44.692113 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:26:44.692448 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 12:26:49.827802 >> Command sent successfully.
293 12:26:49.830330 Returned 0 in 5 seconds
294 12:26:49.930744 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:26:49.931459 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:26:49.931594 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:26:49.931714 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:26:49.931816 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:26:49.931921 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:26:49.932284 [Enter `^Ec?' for help]
302 12:26:50.105162
303 12:26:50.105327
304 12:26:50.105404 F0: 102B 0000
305 12:26:50.105470
306 12:26:50.105532 F3: 1001 0000 [0200]
307 12:26:50.108326
308 12:26:50.108412 F3: 1001 0000
309 12:26:50.108480
310 12:26:50.108556 F7: 102D 0000
311 12:26:50.108617
312 12:26:50.111977 F1: 0000 0000
313 12:26:50.112086
314 12:26:50.112158 V0: 0000 0000 [0001]
315 12:26:50.112222
316 12:26:50.115220 00: 0007 8000
317 12:26:50.115328
318 12:26:50.115403 01: 0000 0000
319 12:26:50.115470
320 12:26:50.115545 BP: 0C00 0209 [0000]
321 12:26:50.115607
322 12:26:50.118536 G0: 1182 0000
323 12:26:50.118623
324 12:26:50.118691 EC: 0000 0021 [4000]
325 12:26:50.118755
326 12:26:50.121687 S7: 0000 0000 [0000]
327 12:26:50.121774
328 12:26:50.125447 CC: 0000 0000 [0001]
329 12:26:50.125547
330 12:26:50.125617 T0: 0000 0040 [010F]
331 12:26:50.125682
332 12:26:50.125743 Jump to BL
333 12:26:50.125804
334 12:26:50.151902
335 12:26:50.152065
336 12:26:50.152144
337 12:26:50.159622 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:26:50.163250 ARM64: Exception handlers installed.
339 12:26:50.166600 ARM64: Testing exception
340 12:26:50.170120 ARM64: Done test exception
341 12:26:50.176882 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:26:50.187875 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:26:50.194935 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:26:50.201819 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:26:50.212084 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:26:50.218388 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:26:50.228510 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:26:50.235441 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:26:50.254752 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:26:50.257911 WDT: Last reset was cold boot
351 12:26:50.261629 SPI1(PAD0) initialized at 2873684 Hz
352 12:26:50.264493 SPI5(PAD0) initialized at 992727 Hz
353 12:26:50.267745 VBOOT: Loading verstage.
354 12:26:50.274862 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:26:50.277886 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:26:50.281605 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:26:50.284928 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:26:50.291973 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:26:50.298890 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:26:50.309675 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:26:50.309813
362 12:26:50.309916
363 12:26:50.319720 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:26:50.322807 ARM64: Exception handlers installed.
365 12:26:50.326610 ARM64: Testing exception
366 12:26:50.326758 ARM64: Done test exception
367 12:26:50.332840 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:26:50.336359 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:26:50.350364 Probing TPM: . done!
370 12:26:50.350510 TPM ready after 0 ms
371 12:26:50.357630 Connected to device vid:did:rid of 1ae0:0028:00
372 12:26:50.367431 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:26:50.405815 Initialized TPM device CR50 revision 0
374 12:26:50.417730 tlcl_send_startup: Startup return code is 0
375 12:26:50.417860 TPM: setup succeeded
376 12:26:50.430473 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:26:50.438607 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:26:50.445692 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:26:50.458949 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:26:50.462162 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:26:50.465810 in-header: 03 07 00 00 08 00 00 00
382 12:26:50.468680 in-data: aa e4 47 04 13 02 00 00
383 12:26:50.472339 Chrome EC: UHEPI supported
384 12:26:50.479149 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:26:50.482106 in-header: 03 ad 00 00 08 00 00 00
386 12:26:50.485099 in-data: 00 20 20 08 00 00 00 00
387 12:26:50.485225 Phase 1
388 12:26:50.488614 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:26:50.495426 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:26:50.501670 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:26:50.505030 Recovery requested (1009000e)
392 12:26:50.509356 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:26:50.517567 tlcl_extend: response is 0
394 12:26:50.528385 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:26:50.531562 tlcl_extend: response is 0
396 12:26:50.537820 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:26:50.558516 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:26:50.565076 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:26:50.565187
400 12:26:50.565257
401 12:26:50.575875 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:26:50.579329 ARM64: Exception handlers installed.
403 12:26:50.579444 ARM64: Testing exception
404 12:26:50.582328 ARM64: Done test exception
405 12:26:50.600764 pmic_efuse_setting: Set efuses in 11 msecs
406 12:26:50.609729 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:26:50.613016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:26:50.616539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:26:50.623091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:26:50.626869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:26:50.633709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:26:50.636980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:26:50.643463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:26:50.647149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:26:50.650270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:26:50.656772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:26:50.659984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:26:50.663693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:26:50.670467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:26:50.676964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:26:50.679973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:26:50.686485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:26:50.693674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:26:50.699983 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:26:50.703476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:26:50.709653 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:26:50.717245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:26:50.720453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:26:50.728206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:26:50.732067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:26:50.738453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:26:50.742164 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:26:50.749159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:26:50.752224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:26:50.759241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:26:50.763054 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:26:50.769879 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:26:50.773032 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:26:50.776180 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:26:50.782969 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:26:50.786495 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:26:50.793010 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:26:50.796312 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:26:50.803499 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:26:50.807202 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:26:50.810318 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:26:50.817595 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:26:50.820808 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:26:50.824582 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:26:50.827775 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:26:50.834038 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:26:50.837890 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:26:50.840966 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:26:50.847372 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:26:50.850516 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:26:50.854297 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:26:50.857446 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:26:50.867648 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:26:50.873863 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:26:50.880750 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:26:50.887180 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:26:50.897311 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:26:50.900230 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:26:50.903692 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:26:50.910430 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:26:50.917328 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
467 12:26:50.923966 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:26:50.927870 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 12:26:50.931087 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:26:50.941159 [RTC]rtc_get_frequency_meter,154: input=15, output=836
471 12:26:50.950674 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 12:26:50.960443 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 12:26:50.969614 [RTC]rtc_get_frequency_meter,154: input=13, output=804
474 12:26:50.979266 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 12:26:50.988542 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 12:26:50.997958 [RTC]rtc_get_frequency_meter,154: input=13, output=804
477 12:26:51.001651 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 12:26:51.008449 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 12:26:51.011717 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:26:51.014909 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:26:51.021791 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:26:51.025327 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:26:51.028507 ADC[4]: Raw value=903031 ID=7
484 12:26:51.029025 ADC[3]: Raw value=213652 ID=1
485 12:26:51.032317 RAM Code: 0x71
486 12:26:51.035522 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:26:51.041851 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:26:51.048607 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:26:51.054735 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:26:51.058019 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:26:51.061687 in-header: 03 07 00 00 08 00 00 00
492 12:26:51.064803 in-data: aa e4 47 04 13 02 00 00
493 12:26:51.068042 Chrome EC: UHEPI supported
494 12:26:51.074547 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:26:51.077697 in-header: 03 dd 00 00 08 00 00 00
496 12:26:51.081477 in-data: 90 20 60 08 00 00 00 00
497 12:26:51.084470 MRC: failed to locate region type 0.
498 12:26:51.091355 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:26:51.094502 DRAM-K: Running full calibration
500 12:26:51.101087 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:26:51.101325 header.status = 0x0
502 12:26:51.104311 header.version = 0x6 (expected: 0x6)
503 12:26:51.107569 header.size = 0xd00 (expected: 0xd00)
504 12:26:51.111206 header.flags = 0x0
505 12:26:51.117894 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:26:51.135217 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 12:26:51.141427 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:26:51.144878 dram_init: ddr_geometry: 2
509 12:26:51.148591 [EMI] MDL number = 2
510 12:26:51.149253 [EMI] Get MDL freq = 0
511 12:26:51.151769 dram_init: ddr_type: 0
512 12:26:51.152244 is_discrete_lpddr4: 1
513 12:26:51.154735 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:26:51.155189
515 12:26:51.157794
516 12:26:51.158087 [Bian_co] ETT version 0.0.0.1
517 12:26:51.164233 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:26:51.164502
519 12:26:51.167912 dramc_set_vcore_voltage set vcore to 650000
520 12:26:51.171076 Read voltage for 800, 4
521 12:26:51.171283 Vio18 = 0
522 12:26:51.171459 Vcore = 650000
523 12:26:51.174340 Vdram = 0
524 12:26:51.174474 Vddq = 0
525 12:26:51.174580 Vmddr = 0
526 12:26:51.177628 dram_init: config_dvfs: 1
527 12:26:51.181374 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:26:51.187540 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:26:51.191159 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 12:26:51.194227 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 12:26:51.197482 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 12:26:51.204382 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 12:26:51.204501 MEM_TYPE=3, freq_sel=18
534 12:26:51.207673 sv_algorithm_assistance_LP4_1600
535 12:26:51.210905 ============ PULL DRAM RESETB DOWN ============
536 12:26:51.217684 ========== PULL DRAM RESETB DOWN end =========
537 12:26:51.220614 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:26:51.223637 ===================================
539 12:26:51.227073 LPDDR4 DRAM CONFIGURATION
540 12:26:51.230800 ===================================
541 12:26:51.231002 EX_ROW_EN[0] = 0x0
542 12:26:51.234007 EX_ROW_EN[1] = 0x0
543 12:26:51.234273 LP4Y_EN = 0x0
544 12:26:51.237322 WORK_FSP = 0x0
545 12:26:51.240959 WL = 0x2
546 12:26:51.241295 RL = 0x2
547 12:26:51.244009 BL = 0x2
548 12:26:51.244395 RPST = 0x0
549 12:26:51.247643 RD_PRE = 0x0
550 12:26:51.248073 WR_PRE = 0x1
551 12:26:51.250721 WR_PST = 0x0
552 12:26:51.251152 DBI_WR = 0x0
553 12:26:51.254407 DBI_RD = 0x0
554 12:26:51.254837 OTF = 0x1
555 12:26:51.257595 ===================================
556 12:26:51.260730 ===================================
557 12:26:51.263819 ANA top config
558 12:26:51.267785 ===================================
559 12:26:51.268218 DLL_ASYNC_EN = 0
560 12:26:51.270777 ALL_SLAVE_EN = 1
561 12:26:51.273884 NEW_RANK_MODE = 1
562 12:26:51.277728 DLL_IDLE_MODE = 1
563 12:26:51.278157 LP45_APHY_COMB_EN = 1
564 12:26:51.280855 TX_ODT_DIS = 1
565 12:26:51.284031 NEW_8X_MODE = 1
566 12:26:51.518254 ===================================
567 12:26:51.519705 ===================================
568 12:26:51.520552 data_rate = 1600
569 12:26:51.521239 CKR = 1
570 12:26:51.521875 DQ_P2S_RATIO = 8
571 12:26:51.522495 ===================================
572 12:26:51.522996 CA_P2S_RATIO = 8
573 12:26:51.523446 DQ_CA_OPEN = 0
574 12:26:51.523889 DQ_SEMI_OPEN = 0
575 12:26:51.524327 CA_SEMI_OPEN = 0
576 12:26:51.524804 CA_FULL_RATE = 0
577 12:26:51.525347 DQ_CKDIV4_EN = 1
578 12:26:51.525718 CA_CKDIV4_EN = 1
579 12:26:51.526190 CA_PREDIV_EN = 0
580 12:26:51.526570 PH8_DLY = 0
581 12:26:51.526900 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:26:51.527214 DQ_AAMCK_DIV = 4
583 12:26:51.527548 CA_AAMCK_DIV = 4
584 12:26:51.527855 CA_ADMCK_DIV = 4
585 12:26:51.528380 DQ_TRACK_CA_EN = 0
586 12:26:51.528852 CA_PICK = 800
587 12:26:51.529400 CA_MCKIO = 800
588 12:26:51.529891 MCKIO_SEMI = 0
589 12:26:51.530490 PLL_FREQ = 3068
590 12:26:51.531105 DQ_UI_PI_RATIO = 32
591 12:26:51.531577 CA_UI_PI_RATIO = 0
592 12:26:51.532031 ===================================
593 12:26:51.532605 ===================================
594 12:26:51.533102 memory_type:LPDDR4
595 12:26:51.533619 GP_NUM : 10
596 12:26:51.534095 SRAM_EN : 1
597 12:26:51.534553 MD32_EN : 0
598 12:26:51.535045 ===================================
599 12:26:51.535491 [ANA_INIT] >>>>>>>>>>>>>>
600 12:26:51.535973 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:26:51.536447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:26:51.537039 ===================================
603 12:26:51.537643 data_rate = 1600,PCW = 0X7600
604 12:26:51.538275 ===================================
605 12:26:51.538793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:26:51.539305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:26:51.539778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:26:51.540222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:26:51.540664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:26:51.541063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:26:51.541537 [ANA_INIT] flow start
612 12:26:51.541887 [ANA_INIT] PLL >>>>>>>>
613 12:26:51.542282 [ANA_INIT] PLL <<<<<<<<
614 12:26:51.542614 [ANA_INIT] MIDPI >>>>>>>>
615 12:26:51.542950 [ANA_INIT] MIDPI <<<<<<<<
616 12:26:51.543269 [ANA_INIT] DLL >>>>>>>>
617 12:26:51.543566 [ANA_INIT] flow end
618 12:26:51.543845 ============ LP4 DIFF to SE enter ============
619 12:26:51.544171 ============ LP4 DIFF to SE exit ============
620 12:26:51.544453 [ANA_INIT] <<<<<<<<<<<<<
621 12:26:51.544818 [Flow] Enable top DCM control >>>>>
622 12:26:51.545282 [Flow] Enable top DCM control <<<<<
623 12:26:51.545669 Enable DLL master slave shuffle
624 12:26:51.545984 ==============================================================
625 12:26:51.546297 Gating Mode config
626 12:26:51.546596 ==============================================================
627 12:26:51.546864 Config description:
628 12:26:51.547147 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:26:51.547493 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:26:51.547830 SELPH_MODE 0: By rank 1: By Phase
631 12:26:51.548159 ==============================================================
632 12:26:51.548493 GAT_TRACK_EN = 1
633 12:26:51.548770 RX_GATING_MODE = 2
634 12:26:51.549070 RX_GATING_TRACK_MODE = 2
635 12:26:51.549279 SELPH_MODE = 1
636 12:26:51.549538 PICG_EARLY_EN = 1
637 12:26:51.549761 VALID_LAT_VALUE = 1
638 12:26:51.550024 ==============================================================
639 12:26:51.550234 Enter into Gating configuration >>>>
640 12:26:51.550432 Exit from Gating configuration <<<<
641 12:26:51.550628 Enter into DVFS_PRE_config >>>>>
642 12:26:51.550852 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:26:51.551201 Exit from DVFS_PRE_config <<<<<
644 12:26:51.551420 Enter into PICG configuration >>>>
645 12:26:51.552017 Exit from PICG configuration <<<<
646 12:26:51.552244 [RX_INPUT] configuration >>>>>
647 12:26:51.555130 [RX_INPUT] configuration <<<<<
648 12:26:51.562552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:26:51.565756 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:26:51.572411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:26:51.579977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:26:51.586920 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:26:51.590870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:26:51.594540 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:26:51.600941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:26:51.605272 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:26:51.608278 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:26:51.612119 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:26:51.615932 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:26:51.619269 ===================================
661 12:26:51.623008 LPDDR4 DRAM CONFIGURATION
662 12:26:51.626871 ===================================
663 12:26:51.626969 EX_ROW_EN[0] = 0x0
664 12:26:51.630128 EX_ROW_EN[1] = 0x0
665 12:26:51.630225 LP4Y_EN = 0x0
666 12:26:51.633981 WORK_FSP = 0x0
667 12:26:51.634087 WL = 0x2
668 12:26:51.637139 RL = 0x2
669 12:26:51.637285 BL = 0x2
670 12:26:51.640938 RPST = 0x0
671 12:26:51.641054 RD_PRE = 0x0
672 12:26:51.645271 WR_PRE = 0x1
673 12:26:51.645398 WR_PST = 0x0
674 12:26:51.649073 DBI_WR = 0x0
675 12:26:51.649537 DBI_RD = 0x0
676 12:26:51.649921 OTF = 0x1
677 12:26:51.652625 ===================================
678 12:26:51.656344 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:26:51.663759 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:26:51.666910 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:26:51.670584 ===================================
682 12:26:51.671016 LPDDR4 DRAM CONFIGURATION
683 12:26:51.674093 ===================================
684 12:26:51.678036 EX_ROW_EN[0] = 0x10
685 12:26:51.678630 EX_ROW_EN[1] = 0x0
686 12:26:51.681723 LP4Y_EN = 0x0
687 12:26:51.682216 WORK_FSP = 0x0
688 12:26:51.685550 WL = 0x2
689 12:26:51.686004 RL = 0x2
690 12:26:51.689314 BL = 0x2
691 12:26:51.689689 RPST = 0x0
692 12:26:51.693141 RD_PRE = 0x0
693 12:26:51.693547 WR_PRE = 0x1
694 12:26:51.696870 WR_PST = 0x0
695 12:26:51.697310 DBI_WR = 0x0
696 12:26:51.697756 DBI_RD = 0x0
697 12:26:51.700459 OTF = 0x1
698 12:26:51.703759 ===================================
699 12:26:51.711504 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:26:51.714533 nWR fixed to 40
701 12:26:51.715037 [ModeRegInit_LP4] CH0 RK0
702 12:26:51.718659 [ModeRegInit_LP4] CH0 RK1
703 12:26:51.722187 [ModeRegInit_LP4] CH1 RK0
704 12:26:51.722617 [ModeRegInit_LP4] CH1 RK1
705 12:26:51.725892 match AC timing 13
706 12:26:51.729464 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:26:51.732627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:26:51.735733 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:26:51.742881 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:26:51.746157 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:26:51.749397 [EMI DOE] emi_dcm 0
712 12:26:51.753009 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:26:51.753563 ==
714 12:26:51.756332 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:26:51.759149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:26:51.759648 ==
717 12:26:51.765645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:26:51.772359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:26:51.780227 [CA 0] Center 37 (7~68) winsize 62
720 12:26:51.783942 [CA 1] Center 36 (6~67) winsize 62
721 12:26:51.787117 [CA 2] Center 34 (4~65) winsize 62
722 12:26:51.790321 [CA 3] Center 34 (4~65) winsize 62
723 12:26:51.794170 [CA 4] Center 33 (3~64) winsize 62
724 12:26:51.797426 [CA 5] Center 33 (3~64) winsize 62
725 12:26:51.797613
726 12:26:51.800605 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 12:26:51.800761
728 12:26:51.803953 [CATrainingPosCal] consider 1 rank data
729 12:26:51.807679 u2DelayCellTimex100 = 270/100 ps
730 12:26:51.810826 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:26:51.813977 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 12:26:51.817739 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 12:26:51.824110 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:26:51.827716 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 12:26:51.830771 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:26:51.831063
737 12:26:51.833945 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:26:51.834331
739 12:26:51.837324 [CBTSetCACLKResult] CA Dly = 33
740 12:26:51.837814 CS Dly: 6 (0~37)
741 12:26:51.838209 ==
742 12:26:51.840352 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:26:51.847435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:26:51.848065 ==
745 12:26:51.850454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:26:51.857424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:26:51.866860 [CA 0] Center 37 (6~68) winsize 63
748 12:26:51.870319 [CA 1] Center 37 (7~68) winsize 62
749 12:26:51.873844 [CA 2] Center 34 (4~65) winsize 62
750 12:26:51.876799 [CA 3] Center 34 (4~65) winsize 62
751 12:26:51.880408 [CA 4] Center 33 (3~64) winsize 62
752 12:26:51.883327 [CA 5] Center 33 (3~64) winsize 62
753 12:26:51.883662
754 12:26:51.886442 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 12:26:51.886715
756 12:26:51.890109 [CATrainingPosCal] consider 2 rank data
757 12:26:51.893210 u2DelayCellTimex100 = 270/100 ps
758 12:26:51.896266 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:26:51.903047 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 12:26:51.906938 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 12:26:51.910577 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:26:51.913807 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 12:26:51.917129 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:26:51.917464
765 12:26:51.921016 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:26:51.921294
767 12:26:51.924677 [CBTSetCACLKResult] CA Dly = 33
768 12:26:51.925027 CS Dly: 6 (0~38)
769 12:26:51.925247
770 12:26:51.927791 ----->DramcWriteLeveling(PI) begin...
771 12:26:51.928055 ==
772 12:26:51.930854 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:26:51.934808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:26:51.935069 ==
775 12:26:51.938010 Write leveling (Byte 0): 32 => 32
776 12:26:51.941909 Write leveling (Byte 1): 28 => 28
777 12:26:51.944989 DramcWriteLeveling(PI) end<-----
778 12:26:51.945250
779 12:26:51.945456 ==
780 12:26:51.948098 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:26:51.951352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:26:51.955222 ==
783 12:26:51.955579 [Gating] SW mode calibration
784 12:26:51.961578 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:26:51.968174 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:26:51.971632 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:26:51.978215 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 12:26:51.981760 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 12:26:51.984813 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
790 12:26:51.991350 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:26:51.995035 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:26:51.998124 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:26:52.004636 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:26:52.008310 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:26:52.011410 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:26:52.017870 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:26:52.021562 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:26:52.024816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:26:52.031665 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:26:52.034841 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:26:52.038070 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:26:52.041272 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:26:52.047616 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 12:26:52.051458 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 12:26:52.054568 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 12:26:52.060965 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:26:52.064461 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:26:52.067655 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:26:52.074308 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:26:52.077211 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:26:52.080800 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:26:52.087387 0 9 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
813 12:26:52.090438 0 9 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
814 12:26:52.093998 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:26:52.100830 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:26:52.103847 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:26:52.106904 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:26:52.113572 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:26:52.117254 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
820 12:26:52.120397 0 10 8 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (1 0)
821 12:26:52.127396 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
822 12:26:52.130580 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:26:52.134204 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:26:52.138134 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:26:52.144645 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:26:52.148416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:26:52.152374 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 12:26:52.158916 0 11 8 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
829 12:26:52.162122 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
830 12:26:52.165738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:26:52.169476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:26:52.173256 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:26:52.180656 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:26:52.184401 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:26:52.188173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:26:52.191982 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 12:26:52.195544 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:26:52.201817 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:26:52.205536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:26:52.208756 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:26:52.215349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:26:52.218372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:26:52.221811 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:26:52.228681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:26:52.231776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:26:52.234991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:26:52.241862 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:26:52.245657 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:26:52.248873 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:26:52.252676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:26:52.259656 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:26:52.263685 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:26:52.263772 Total UI for P1: 0, mck2ui 16
854 12:26:52.267667 best dqsien dly found for B0: ( 0, 14, 4)
855 12:26:52.273954 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:26:52.277851 Total UI for P1: 0, mck2ui 16
857 12:26:52.281007 best dqsien dly found for B1: ( 0, 14, 8)
858 12:26:52.284035 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 12:26:52.287682 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:26:52.287797
861 12:26:52.290874 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 12:26:52.294601 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:26:52.297657 [Gating] SW calibration Done
864 12:26:52.297742 ==
865 12:26:52.301339 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:26:52.304241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:26:52.304343 ==
868 12:26:52.307913 RX Vref Scan: 0
869 12:26:52.308039
870 12:26:52.308110 RX Vref 0 -> 0, step: 1
871 12:26:52.308173
872 12:26:52.310945 RX Delay -130 -> 252, step: 16
873 12:26:52.314603 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 12:26:52.320845 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 12:26:52.324425 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 12:26:52.327972 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 12:26:52.330950 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 12:26:52.334177 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 12:26:52.341063 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 12:26:52.344276 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 12:26:52.347534 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 12:26:52.350636 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 12:26:52.354571 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 12:26:52.360928 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 12:26:52.364130 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 12:26:52.367451 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 12:26:52.370749 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 12:26:52.373955 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 12:26:52.377136 ==
890 12:26:52.381010 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:26:52.384196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:26:52.384307 ==
893 12:26:52.384403 DQS Delay:
894 12:26:52.387315 DQS0 = 0, DQS1 = 0
895 12:26:52.387414 DQM Delay:
896 12:26:52.390985 DQM0 = 86, DQM1 = 77
897 12:26:52.391076 DQ Delay:
898 12:26:52.394179 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 12:26:52.397408 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
900 12:26:52.400415 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 12:26:52.404169 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 12:26:52.404293
903 12:26:52.404401
904 12:26:52.404505 ==
905 12:26:52.407230 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:26:52.410878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:26:52.410969 ==
908 12:26:52.411038
909 12:26:52.411100
910 12:26:52.414036 TX Vref Scan disable
911 12:26:52.417080 == TX Byte 0 ==
912 12:26:52.420711 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 12:26:52.424202 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 12:26:52.427309 == TX Byte 1 ==
915 12:26:52.430387 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 12:26:52.433978 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 12:26:52.434057 ==
918 12:26:52.437568 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:26:52.440646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:26:52.443786 ==
921 12:26:52.455727 TX Vref=22, minBit 8, minWin=27, winSum=442
922 12:26:52.458885 TX Vref=24, minBit 5, minWin=27, winSum=446
923 12:26:52.462086 TX Vref=26, minBit 8, minWin=27, winSum=446
924 12:26:52.465223 TX Vref=28, minBit 8, minWin=27, winSum=447
925 12:26:52.469165 TX Vref=30, minBit 10, minWin=27, winSum=446
926 12:26:52.472322 TX Vref=32, minBit 5, minWin=27, winSum=443
927 12:26:52.479369 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
928 12:26:52.479456
929 12:26:52.483319 Final TX Range 1 Vref 28
930 12:26:52.483404
931 12:26:52.483471 ==
932 12:26:52.487066 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:26:52.490192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:26:52.490299 ==
935 12:26:52.490383
936 12:26:52.490458
937 12:26:52.493326 TX Vref Scan disable
938 12:26:52.497056 == TX Byte 0 ==
939 12:26:52.500421 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 12:26:52.504179 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 12:26:52.504264 == TX Byte 1 ==
942 12:26:52.511591 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 12:26:52.515329 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 12:26:52.515437
945 12:26:52.515559 [DATLAT]
946 12:26:52.515684 Freq=800, CH0 RK0
947 12:26:52.518472
948 12:26:52.518543 DATLAT Default: 0xa
949 12:26:52.518605 0, 0xFFFF, sum = 0
950 12:26:52.522385 1, 0xFFFF, sum = 0
951 12:26:52.522468 2, 0xFFFF, sum = 0
952 12:26:52.525501 3, 0xFFFF, sum = 0
953 12:26:52.525600 4, 0xFFFF, sum = 0
954 12:26:52.529183 5, 0xFFFF, sum = 0
955 12:26:52.529272 6, 0xFFFF, sum = 0
956 12:26:52.532821 7, 0xFFFF, sum = 0
957 12:26:52.532920 8, 0xFFFF, sum = 0
958 12:26:52.536156 9, 0x0, sum = 1
959 12:26:52.536284 10, 0x0, sum = 2
960 12:26:52.539896 11, 0x0, sum = 3
961 12:26:52.540054 12, 0x0, sum = 4
962 12:26:52.540142 best_step = 10
963 12:26:52.540208
964 12:26:52.543731 ==
965 12:26:52.543830 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:26:52.551163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:26:52.551289 ==
968 12:26:52.551370 RX Vref Scan: 1
969 12:26:52.551444
970 12:26:52.554349 Set Vref Range= 32 -> 127
971 12:26:52.554459
972 12:26:52.557543 RX Vref 32 -> 127, step: 1
973 12:26:52.557661
974 12:26:52.557754 RX Delay -95 -> 252, step: 8
975 12:26:52.557841
976 12:26:52.561260 Set Vref, RX VrefLevel [Byte0]: 32
977 12:26:52.565073 [Byte1]: 32
978 12:26:52.568904
979 12:26:52.569066 Set Vref, RX VrefLevel [Byte0]: 33
980 12:26:52.572700 [Byte1]: 33
981 12:26:52.576730
982 12:26:52.576979 Set Vref, RX VrefLevel [Byte0]: 34
983 12:26:52.580032 [Byte1]: 34
984 12:26:52.583708
985 12:26:52.583949 Set Vref, RX VrefLevel [Byte0]: 35
986 12:26:52.587605 [Byte1]: 35
987 12:26:52.591321
988 12:26:52.591582 Set Vref, RX VrefLevel [Byte0]: 36
989 12:26:52.594619 [Byte1]: 36
990 12:26:52.598947
991 12:26:52.599280 Set Vref, RX VrefLevel [Byte0]: 37
992 12:26:52.602038 [Byte1]: 37
993 12:26:52.606370
994 12:26:52.606835 Set Vref, RX VrefLevel [Byte0]: 38
995 12:26:52.610259 [Byte1]: 38
996 12:26:52.614433
997 12:26:52.614808 Set Vref, RX VrefLevel [Byte0]: 39
998 12:26:52.617379 [Byte1]: 39
999 12:26:52.622340
1000 12:26:52.622785 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:26:52.625430 [Byte1]: 40
1002 12:26:52.629318
1003 12:26:52.629742 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:26:52.633076 [Byte1]: 41
1005 12:26:52.637309
1006 12:26:52.637761 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:26:52.640796 [Byte1]: 42
1008 12:26:52.644593
1009 12:26:52.648194 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:26:52.648725 [Byte1]: 43
1011 12:26:52.652280
1012 12:26:52.652781 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:26:52.655956 [Byte1]: 44
1014 12:26:52.659859
1015 12:26:52.660183 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:26:52.662983 [Byte1]: 45
1017 12:26:52.667413
1018 12:26:52.667823 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:26:52.670652 [Byte1]: 46
1020 12:26:52.675172
1021 12:26:52.675610 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:26:52.678476 [Byte1]: 47
1023 12:26:52.682811
1024 12:26:52.683274 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:26:52.686217 [Byte1]: 48
1026 12:26:52.690787
1027 12:26:52.691144 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:26:52.693800 [Byte1]: 49
1029 12:26:52.698325
1030 12:26:52.698792 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:26:52.701562 [Byte1]: 50
1032 12:26:52.705235
1033 12:26:52.705660 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:26:52.708908 [Byte1]: 51
1035 12:26:52.713330
1036 12:26:52.713773 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:26:52.715774 [Byte1]: 52
1038 12:26:52.720293
1039 12:26:52.720835 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:26:52.723847 [Byte1]: 53
1041 12:26:52.728212
1042 12:26:52.728675 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:26:52.731847 [Byte1]: 54
1044 12:26:52.735666
1045 12:26:52.736037 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:26:52.739334 [Byte1]: 55
1047 12:26:52.742952
1048 12:26:52.746627 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:26:52.747113 [Byte1]: 56
1050 12:26:52.750882
1051 12:26:52.751550 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:26:52.754584 [Byte1]: 57
1053 12:26:52.759015
1054 12:26:52.759494 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:26:52.762229 [Byte1]: 58
1056 12:26:52.766017
1057 12:26:52.766522 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:26:52.769957 [Byte1]: 59
1059 12:26:52.773857
1060 12:26:52.774313 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:26:52.777569 [Byte1]: 60
1062 12:26:52.781392
1063 12:26:52.781875 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:26:52.784733 [Byte1]: 61
1065 12:26:52.789188
1066 12:26:52.789651 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:26:52.792398 [Byte1]: 62
1068 12:26:52.796184
1069 12:26:52.796646 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:26:52.800095 [Byte1]: 63
1071 12:26:52.804704
1072 12:26:52.805070 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:26:52.807777 [Byte1]: 64
1074 12:26:52.811927
1075 12:26:52.812355 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:26:52.815235 [Byte1]: 65
1077 12:26:52.819052
1078 12:26:52.819491 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:26:52.822329 [Byte1]: 66
1080 12:26:52.827290
1081 12:26:52.827824 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:26:52.830719 [Byte1]: 67
1083 12:26:52.834663
1084 12:26:52.834995 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:26:52.837542 [Byte1]: 68
1086 12:26:52.841800
1087 12:26:52.842237 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:26:52.845560 [Byte1]: 69
1089 12:26:52.849710
1090 12:26:52.850111 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:26:52.853362 [Byte1]: 70
1092 12:26:52.857568
1093 12:26:52.857906 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:26:52.860674 [Byte1]: 71
1095 12:26:52.864595
1096 12:26:52.864932 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:26:52.868147 [Byte1]: 72
1098 12:26:52.872463
1099 12:26:52.872909 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:26:52.876302 [Byte1]: 73
1101 12:26:52.880177
1102 12:26:52.880674 Set Vref, RX VrefLevel [Byte0]: 74
1103 12:26:52.884092 [Byte1]: 74
1104 12:26:52.887732
1105 12:26:52.888162 Set Vref, RX VrefLevel [Byte0]: 75
1106 12:26:52.891552 [Byte1]: 75
1107 12:26:52.894862
1108 12:26:52.898583 Set Vref, RX VrefLevel [Byte0]: 76
1109 12:26:52.899027 [Byte1]: 76
1110 12:26:52.903133
1111 12:26:52.903590 Set Vref, RX VrefLevel [Byte0]: 77
1112 12:26:52.906952 [Byte1]: 77
1113 12:26:52.910684
1114 12:26:52.911168 Set Vref, RX VrefLevel [Byte0]: 78
1115 12:26:52.913653 [Byte1]: 78
1116 12:26:52.918244
1117 12:26:52.918682 Set Vref, RX VrefLevel [Byte0]: 79
1118 12:26:52.922019 [Byte1]: 79
1119 12:26:52.925887
1120 12:26:52.926224 Set Vref, RX VrefLevel [Byte0]: 80
1121 12:26:52.929025 [Byte1]: 80
1122 12:26:52.933469
1123 12:26:52.933800 Set Vref, RX VrefLevel [Byte0]: 81
1124 12:26:52.936565 [Byte1]: 81
1125 12:26:52.940740
1126 12:26:52.941066 Final RX Vref Byte 0 = 64 to rank0
1127 12:26:52.944353 Final RX Vref Byte 1 = 54 to rank0
1128 12:26:52.947900 Final RX Vref Byte 0 = 64 to rank1
1129 12:26:52.951187 Final RX Vref Byte 1 = 54 to rank1==
1130 12:26:52.954816 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 12:26:52.958608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 12:26:52.959010 ==
1133 12:26:52.962149 DQS Delay:
1134 12:26:52.962568 DQS0 = 0, DQS1 = 0
1135 12:26:52.962837 DQM Delay:
1136 12:26:52.965744 DQM0 = 87, DQM1 = 75
1137 12:26:52.966070 DQ Delay:
1138 12:26:52.969342 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1139 12:26:52.972834 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1140 12:26:52.975513 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1141 12:26:52.979265 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1142 12:26:52.979755
1143 12:26:52.980070
1144 12:26:52.986345 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1145 12:26:52.990300 CH0 RK0: MR19=606, MR18=4325
1146 12:26:52.997229 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1147 12:26:52.997591
1148 12:26:53.000895 ----->DramcWriteLeveling(PI) begin...
1149 12:26:53.001356 ==
1150 12:26:53.004855 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 12:26:53.008475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 12:26:53.008994 ==
1153 12:26:53.012332 Write leveling (Byte 0): 30 => 30
1154 12:26:53.012785 Write leveling (Byte 1): 29 => 29
1155 12:26:53.015600 DramcWriteLeveling(PI) end<-----
1156 12:26:53.015961
1157 12:26:53.016304 ==
1158 12:26:53.019099 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 12:26:53.025513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 12:26:53.025968 ==
1161 12:26:53.029072 [Gating] SW mode calibration
1162 12:26:53.072879 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 12:26:53.073612 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 12:26:53.073908 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 12:26:53.074160 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1166 12:26:53.074770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1167 12:26:53.075209 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 12:26:53.075589 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:26:53.076026 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:26:53.076411 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:26:53.116843 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:26:53.117243 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:26:53.117525 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:26:53.118134 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:26:53.118477 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:26:53.118756 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:26:53.119014 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:26:53.119268 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:26:53.119520 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:26:53.119830 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:26:53.120088 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1182 12:26:53.124436 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1183 12:26:53.127610 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:26:53.130941 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:26:53.138134 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:26:53.141262 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:26:53.144486 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:26:53.151229 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:26:53.154556 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:26:53.157619 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1191 12:26:53.164407 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1192 12:26:53.167415 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 12:26:53.171051 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 12:26:53.174141 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 12:26:53.180704 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 12:26:53.183792 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 12:26:53.187523 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 12:26:53.194071 0 10 8 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
1199 12:26:53.197297 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1200 12:26:53.200395 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:26:53.207229 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:26:53.210429 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:26:53.214288 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:26:53.220662 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:26:53.223852 0 11 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
1206 12:26:53.227431 0 11 8 | B1->B0 | 2929 3d3d | 0 0 | (1 1) (0 0)
1207 12:26:53.233791 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1208 12:26:53.237061 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 12:26:53.240761 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:26:53.247281 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 12:26:53.250464 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:26:53.254015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 12:26:53.260853 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1214 12:26:53.264022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1215 12:26:53.267071 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1216 12:26:53.273847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:26:53.277110 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:26:53.280713 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:26:53.284223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:26:53.291088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:26:53.294076 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:26:53.297596 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:26:53.304268 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:26:53.307467 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:26:53.310671 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:26:53.317231 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:26:53.320221 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:26:53.324040 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:26:53.330176 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:26:53.334130 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1231 12:26:53.337222 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1232 12:26:53.340362 Total UI for P1: 0, mck2ui 16
1233 12:26:53.343627 best dqsien dly found for B0: ( 0, 14, 8)
1234 12:26:53.350504 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 12:26:53.350843 Total UI for P1: 0, mck2ui 16
1236 12:26:53.356692 best dqsien dly found for B1: ( 0, 14, 12)
1237 12:26:53.360364 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1238 12:26:53.363465 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1239 12:26:53.363827
1240 12:26:53.366563 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1241 12:26:53.370487 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1242 12:26:53.373659 [Gating] SW calibration Done
1243 12:26:53.374186 ==
1244 12:26:53.377037 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 12:26:53.380172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 12:26:53.380653 ==
1247 12:26:53.383253 RX Vref Scan: 0
1248 12:26:53.383593
1249 12:26:53.383865 RX Vref 0 -> 0, step: 1
1250 12:26:53.384190
1251 12:26:53.386809 RX Delay -130 -> 252, step: 16
1252 12:26:53.393599 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1253 12:26:53.396541 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1254 12:26:53.400154 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1255 12:26:53.403198 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1256 12:26:53.406696 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1257 12:26:53.413179 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1258 12:26:53.416291 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1259 12:26:53.420131 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1260 12:26:53.423199 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1261 12:26:53.426432 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1262 12:26:53.433327 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1263 12:26:53.436391 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1264 12:26:53.439482 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1265 12:26:53.443280 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1266 12:26:53.446486 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1267 12:26:53.452968 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1268 12:26:53.453398 ==
1269 12:26:53.456187 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 12:26:53.459411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 12:26:53.459809 ==
1272 12:26:53.460086 DQS Delay:
1273 12:26:53.463122 DQS0 = 0, DQS1 = 0
1274 12:26:53.463514 DQM Delay:
1275 12:26:53.466203 DQM0 = 85, DQM1 = 76
1276 12:26:53.466593 DQ Delay:
1277 12:26:53.469362 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1278 12:26:53.472556 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1279 12:26:53.476412 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1280 12:26:53.479531 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1281 12:26:53.479950
1282 12:26:53.480364
1283 12:26:53.480752 ==
1284 12:26:53.482758 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:26:53.486473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:26:53.486865 ==
1287 12:26:53.489676
1288 12:26:53.490055
1289 12:26:53.490426 TX Vref Scan disable
1290 12:26:53.492723 == TX Byte 0 ==
1291 12:26:53.495858 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1292 12:26:53.499479 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1293 12:26:53.502563 == TX Byte 1 ==
1294 12:26:53.506244 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1295 12:26:53.509322 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1296 12:26:53.512722 ==
1297 12:26:53.513111 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 12:26:53.519156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 12:26:53.519386 ==
1300 12:26:53.531228 TX Vref=22, minBit 5, minWin=27, winSum=444
1301 12:26:53.534442 TX Vref=24, minBit 9, minWin=27, winSum=449
1302 12:26:53.537937 TX Vref=26, minBit 9, minWin=27, winSum=449
1303 12:26:53.541223 TX Vref=28, minBit 9, minWin=27, winSum=448
1304 12:26:53.544391 TX Vref=30, minBit 9, minWin=27, winSum=447
1305 12:26:53.551388 TX Vref=32, minBit 8, minWin=27, winSum=445
1306 12:26:53.554534 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 24
1307 12:26:53.554665
1308 12:26:53.557772 Final TX Range 1 Vref 24
1309 12:26:53.557859
1310 12:26:53.557925 ==
1311 12:26:53.560867 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 12:26:53.564009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 12:26:53.564116 ==
1314 12:26:53.567574
1315 12:26:53.567652
1316 12:26:53.567716 TX Vref Scan disable
1317 12:26:53.570733 == TX Byte 0 ==
1318 12:26:53.574432 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1319 12:26:53.580671 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1320 12:26:53.580754 == TX Byte 1 ==
1321 12:26:53.584477 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1322 12:26:53.590749 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1323 12:26:53.590866
1324 12:26:53.590961 [DATLAT]
1325 12:26:53.591075 Freq=800, CH0 RK1
1326 12:26:53.591175
1327 12:26:53.593786 DATLAT Default: 0xa
1328 12:26:53.593898 0, 0xFFFF, sum = 0
1329 12:26:53.597485 1, 0xFFFF, sum = 0
1330 12:26:53.601090 2, 0xFFFF, sum = 0
1331 12:26:53.601203 3, 0xFFFF, sum = 0
1332 12:26:53.604144 4, 0xFFFF, sum = 0
1333 12:26:53.604257 5, 0xFFFF, sum = 0
1334 12:26:53.607178 6, 0xFFFF, sum = 0
1335 12:26:53.607284 7, 0xFFFF, sum = 0
1336 12:26:53.610834 8, 0xFFFF, sum = 0
1337 12:26:53.610949 9, 0x0, sum = 1
1338 12:26:53.613919 10, 0x0, sum = 2
1339 12:26:53.614033 11, 0x0, sum = 3
1340 12:26:53.614143 12, 0x0, sum = 4
1341 12:26:53.617634 best_step = 10
1342 12:26:53.617739
1343 12:26:53.617835 ==
1344 12:26:53.620509 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 12:26:53.624359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 12:26:53.624489 ==
1347 12:26:53.627493 RX Vref Scan: 0
1348 12:26:53.627598
1349 12:26:53.627704 RX Vref 0 -> 0, step: 1
1350 12:26:53.630575
1351 12:26:53.630686 RX Delay -111 -> 252, step: 8
1352 12:26:53.637625 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1353 12:26:53.641238 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1354 12:26:53.644262 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1355 12:26:53.647450 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1356 12:26:53.654457 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1357 12:26:53.657633 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1358 12:26:53.660855 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1359 12:26:53.664462 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1360 12:26:53.667693 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1361 12:26:53.670816 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1362 12:26:53.677763 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1363 12:26:53.680928 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1364 12:26:53.684046 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1365 12:26:53.687184 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1366 12:26:53.694093 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1367 12:26:53.697358 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1368 12:26:53.697435 ==
1369 12:26:53.700493 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 12:26:53.704281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 12:26:53.704355 ==
1372 12:26:53.707392 DQS Delay:
1373 12:26:53.707521 DQS0 = 0, DQS1 = 0
1374 12:26:53.707614 DQM Delay:
1375 12:26:53.710597 DQM0 = 85, DQM1 = 76
1376 12:26:53.710699 DQ Delay:
1377 12:26:53.714191 DQ0 =84, DQ1 =88, DQ2 =76, DQ3 =84
1378 12:26:53.717058 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1379 12:26:53.720678 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1380 12:26:53.723850 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1381 12:26:53.723961
1382 12:26:53.724054
1383 12:26:53.734035 [DQSOSCAuto] RK1, (LSB)MR18= 0x4006, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1384 12:26:53.734161 CH0 RK1: MR19=606, MR18=4006
1385 12:26:53.740420 CH0_RK1: MR19=0x606, MR18=0x4006, DQSOSC=393, MR23=63, INC=95, DEC=63
1386 12:26:53.743529 [RxdqsGatingPostProcess] freq 800
1387 12:26:53.750352 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 12:26:53.753496 Pre-setting of DQS Precalculation
1389 12:26:53.756698 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 12:26:53.756804 ==
1391 12:26:53.759942 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 12:26:53.766999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 12:26:53.767087 ==
1394 12:26:53.770145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 12:26:53.776916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 12:26:53.786321 [CA 0] Center 36 (6~67) winsize 62
1397 12:26:53.789451 [CA 1] Center 37 (7~67) winsize 61
1398 12:26:53.792540 [CA 2] Center 34 (4~65) winsize 62
1399 12:26:53.796405 [CA 3] Center 34 (3~65) winsize 63
1400 12:26:53.799528 [CA 4] Center 34 (4~65) winsize 62
1401 12:26:53.802602 [CA 5] Center 34 (3~65) winsize 63
1402 12:26:53.802688
1403 12:26:53.805774 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 12:26:53.805849
1405 12:26:53.809019 [CATrainingPosCal] consider 1 rank data
1406 12:26:53.812680 u2DelayCellTimex100 = 270/100 ps
1407 12:26:53.815889 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 12:26:53.822443 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1409 12:26:53.826149 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 12:26:53.829117 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1411 12:26:53.832724 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 12:26:53.835586 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 12:26:53.835696
1414 12:26:53.839468 CA PerBit enable=1, Macro0, CA PI delay=34
1415 12:26:53.839567
1416 12:26:53.842659 [CBTSetCACLKResult] CA Dly = 34
1417 12:26:53.842762 CS Dly: 4 (0~35)
1418 12:26:53.845708 ==
1419 12:26:53.848831 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 12:26:53.852429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 12:26:53.852554 ==
1422 12:26:53.855507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 12:26:53.862638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 12:26:53.872034 [CA 0] Center 36 (6~67) winsize 62
1425 12:26:53.875332 [CA 1] Center 36 (6~67) winsize 62
1426 12:26:53.879026 [CA 2] Center 34 (4~65) winsize 62
1427 12:26:53.882034 [CA 3] Center 34 (3~65) winsize 63
1428 12:26:53.885243 [CA 4] Center 34 (4~65) winsize 62
1429 12:26:53.889107 [CA 5] Center 34 (3~65) winsize 63
1430 12:26:53.889184
1431 12:26:53.892200 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 12:26:53.892315
1433 12:26:53.895349 [CATrainingPosCal] consider 2 rank data
1434 12:26:53.899098 u2DelayCellTimex100 = 270/100 ps
1435 12:26:53.902206 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 12:26:53.905266 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1437 12:26:53.912319 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 12:26:53.915318 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 12:26:53.918954 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 12:26:53.922159 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1441 12:26:53.922264
1442 12:26:53.925788 CA PerBit enable=1, Macro0, CA PI delay=34
1443 12:26:53.925876
1444 12:26:53.928649 [CBTSetCACLKResult] CA Dly = 34
1445 12:26:53.928721 CS Dly: 5 (0~38)
1446 12:26:53.928796
1447 12:26:53.932484 ----->DramcWriteLeveling(PI) begin...
1448 12:26:53.935539 ==
1449 12:26:53.938693 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 12:26:53.942273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 12:26:53.942382 ==
1452 12:26:53.945357 Write leveling (Byte 0): 25 => 25
1453 12:26:53.948499 Write leveling (Byte 1): 27 => 27
1454 12:26:53.951725 DramcWriteLeveling(PI) end<-----
1455 12:26:53.951821
1456 12:26:53.951887 ==
1457 12:26:53.955494 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 12:26:53.958547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 12:26:53.958623 ==
1460 12:26:53.961592 [Gating] SW mode calibration
1461 12:26:53.968835 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 12:26:53.975335 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 12:26:53.978564 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1464 12:26:53.981913 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1465 12:26:53.988183 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1466 12:26:53.991438 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:26:53.995330 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:26:53.998391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:26:54.005133 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:26:54.008314 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:26:54.012104 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:26:54.018461 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:26:54.021762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:26:54.024947 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:26:54.031758 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:26:54.034805 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:26:54.038371 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:26:54.045209 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:26:54.048281 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1480 12:26:54.051431 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1481 12:26:54.058384 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:26:54.061341 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:26:54.064482 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:26:54.071495 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:26:54.074583 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:26:54.077864 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:26:54.084935 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:26:54.087938 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:26:54.091490 0 9 8 | B1->B0 | 2929 2f2f | 0 1 | (0 0) (0 0)
1490 12:26:54.097903 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 12:26:54.100942 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 12:26:54.104686 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:26:54.110885 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 12:26:54.114675 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 12:26:54.117814 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 12:26:54.124115 0 10 4 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
1497 12:26:54.127950 0 10 8 | B1->B0 | 2b2b 2b2b | 0 0 | (1 0) (0 0)
1498 12:26:54.131132 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:26:54.137401 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:26:54.141025 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:26:54.144159 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:26:54.150683 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:26:54.154342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:26:54.157451 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1505 12:26:54.164244 0 11 8 | B1->B0 | 3a3a 3b3b | 0 0 | (0 0) (0 0)
1506 12:26:54.167290 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 12:26:54.171039 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 12:26:54.177471 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:26:54.180751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:26:54.184039 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:26:54.187225 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 12:26:54.194018 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1513 12:26:54.197394 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:26:54.200607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:26:54.206886 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:26:54.210663 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:26:54.214024 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:26:54.220106 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:26:54.223439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:26:54.227233 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:26:54.233797 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:26:54.236985 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:26:54.240145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:26:54.247051 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:26:54.250110 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:26:54.253384 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:26:54.260545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 12:26:54.263213 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1529 12:26:54.266535 Total UI for P1: 0, mck2ui 16
1530 12:26:54.270346 best dqsien dly found for B0: ( 0, 14, 2)
1531 12:26:54.273436 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 12:26:54.276903 Total UI for P1: 0, mck2ui 16
1533 12:26:54.280148 best dqsien dly found for B1: ( 0, 14, 4)
1534 12:26:54.282867 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1535 12:26:54.286678 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1536 12:26:54.290048
1537 12:26:54.293394 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1538 12:26:54.296628 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1539 12:26:54.299846 [Gating] SW calibration Done
1540 12:26:54.299945 ==
1541 12:26:54.303114 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 12:26:54.306418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 12:26:54.306508 ==
1544 12:26:54.306575 RX Vref Scan: 0
1545 12:26:54.306637
1546 12:26:54.309611 RX Vref 0 -> 0, step: 1
1547 12:26:54.309695
1548 12:26:54.312698 RX Delay -130 -> 252, step: 16
1549 12:26:54.316099 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1550 12:26:54.319265 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1551 12:26:54.326119 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1552 12:26:54.329193 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1553 12:26:54.333100 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1554 12:26:54.336300 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1555 12:26:54.339406 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1556 12:26:54.346074 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1557 12:26:54.349342 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1558 12:26:54.352279 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1559 12:26:54.355943 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1560 12:26:54.362596 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1561 12:26:54.365738 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1562 12:26:54.368963 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1563 12:26:54.371996 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1564 12:26:54.375735 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1565 12:26:54.378875 ==
1566 12:26:54.382098 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 12:26:54.385157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 12:26:54.385245 ==
1569 12:26:54.385333 DQS Delay:
1570 12:26:54.389025 DQS0 = 0, DQS1 = 0
1571 12:26:54.389111 DQM Delay:
1572 12:26:54.392222 DQM0 = 89, DQM1 = 79
1573 12:26:54.392307 DQ Delay:
1574 12:26:54.395558 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1575 12:26:54.398722 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1576 12:26:54.401847 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1577 12:26:54.405586 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1578 12:26:54.405673
1579 12:26:54.405760
1580 12:26:54.405842 ==
1581 12:26:54.408798 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:26:54.412063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:26:54.412150 ==
1584 12:26:54.412254
1585 12:26:54.415164
1586 12:26:54.415250 TX Vref Scan disable
1587 12:26:54.418244 == TX Byte 0 ==
1588 12:26:54.422015 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1589 12:26:54.425221 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1590 12:26:54.428257 == TX Byte 1 ==
1591 12:26:54.431989 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1592 12:26:54.435080 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1593 12:26:54.435170 ==
1594 12:26:54.438294 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 12:26:54.444635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 12:26:54.444726 ==
1597 12:26:54.456880 TX Vref=22, minBit 13, minWin=26, winSum=438
1598 12:26:54.459926 TX Vref=24, minBit 0, minWin=27, winSum=443
1599 12:26:54.463548 TX Vref=26, minBit 0, minWin=27, winSum=447
1600 12:26:54.466560 TX Vref=28, minBit 9, minWin=27, winSum=451
1601 12:26:54.469732 TX Vref=30, minBit 1, minWin=27, winSum=445
1602 12:26:54.476638 TX Vref=32, minBit 8, minWin=27, winSum=443
1603 12:26:54.480272 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1604 12:26:54.480383
1605 12:26:54.483436 Final TX Range 1 Vref 28
1606 12:26:54.483546
1607 12:26:54.483641 ==
1608 12:26:54.486693 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 12:26:54.489814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 12:26:54.492921 ==
1611 12:26:54.493027
1612 12:26:54.493123
1613 12:26:54.493216 TX Vref Scan disable
1614 12:26:54.496738 == TX Byte 0 ==
1615 12:26:54.499992 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1616 12:26:54.506980 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1617 12:26:54.507091 == TX Byte 1 ==
1618 12:26:54.510111 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1619 12:26:54.513328 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1620 12:26:54.516932
1621 12:26:54.517016 [DATLAT]
1622 12:26:54.517082 Freq=800, CH1 RK0
1623 12:26:54.517145
1624 12:26:54.519934 DATLAT Default: 0xa
1625 12:26:54.520045 0, 0xFFFF, sum = 0
1626 12:26:54.523660 1, 0xFFFF, sum = 0
1627 12:26:54.523743 2, 0xFFFF, sum = 0
1628 12:26:54.526829 3, 0xFFFF, sum = 0
1629 12:26:54.529994 4, 0xFFFF, sum = 0
1630 12:26:54.530103 5, 0xFFFF, sum = 0
1631 12:26:54.533168 6, 0xFFFF, sum = 0
1632 12:26:54.533389 7, 0xFFFF, sum = 0
1633 12:26:54.536380 8, 0x0, sum = 1
1634 12:26:54.536495 9, 0x0, sum = 2
1635 12:26:54.536597 10, 0x0, sum = 3
1636 12:26:54.539602 11, 0x0, sum = 4
1637 12:26:54.539678 best_step = 9
1638 12:26:54.539757
1639 12:26:54.539846 ==
1640 12:26:54.542839 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 12:26:54.549909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 12:26:54.550007 ==
1643 12:26:54.550123 RX Vref Scan: 1
1644 12:26:54.550222
1645 12:26:54.553163 Set Vref Range= 32 -> 127
1646 12:26:54.553264
1647 12:26:54.556259 RX Vref 32 -> 127, step: 1
1648 12:26:54.556339
1649 12:26:54.560193 RX Delay -95 -> 252, step: 8
1650 12:26:54.560278
1651 12:26:54.563376 Set Vref, RX VrefLevel [Byte0]: 32
1652 12:26:54.566618 [Byte1]: 32
1653 12:26:54.566731
1654 12:26:54.569699 Set Vref, RX VrefLevel [Byte0]: 33
1655 12:26:54.573288 [Byte1]: 33
1656 12:26:54.573374
1657 12:26:54.576380 Set Vref, RX VrefLevel [Byte0]: 34
1658 12:26:54.579613 [Byte1]: 34
1659 12:26:54.579741
1660 12:26:54.583268 Set Vref, RX VrefLevel [Byte0]: 35
1661 12:26:54.586468 [Byte1]: 35
1662 12:26:54.590457
1663 12:26:54.590558 Set Vref, RX VrefLevel [Byte0]: 36
1664 12:26:54.593689 [Byte1]: 36
1665 12:26:54.598199
1666 12:26:54.598310 Set Vref, RX VrefLevel [Byte0]: 37
1667 12:26:54.600981 [Byte1]: 37
1668 12:26:54.605474
1669 12:26:54.605567 Set Vref, RX VrefLevel [Byte0]: 38
1670 12:26:54.608730 [Byte1]: 38
1671 12:26:54.613186
1672 12:26:54.613295 Set Vref, RX VrefLevel [Byte0]: 39
1673 12:26:54.616582 [Byte1]: 39
1674 12:26:54.620611
1675 12:26:54.620736 Set Vref, RX VrefLevel [Byte0]: 40
1676 12:26:54.624479 [Byte1]: 40
1677 12:26:54.628252
1678 12:26:54.628364 Set Vref, RX VrefLevel [Byte0]: 41
1679 12:26:54.631353 [Byte1]: 41
1680 12:26:54.636056
1681 12:26:54.636150 Set Vref, RX VrefLevel [Byte0]: 42
1682 12:26:54.639297 [Byte1]: 42
1683 12:26:54.643844
1684 12:26:54.643951 Set Vref, RX VrefLevel [Byte0]: 43
1685 12:26:54.647121 [Byte1]: 43
1686 12:26:54.650908
1687 12:26:54.650994 Set Vref, RX VrefLevel [Byte0]: 44
1688 12:26:54.654153 [Byte1]: 44
1689 12:26:54.658582
1690 12:26:54.658690 Set Vref, RX VrefLevel [Byte0]: 45
1691 12:26:54.662478 [Byte1]: 45
1692 12:26:54.666109
1693 12:26:54.666234 Set Vref, RX VrefLevel [Byte0]: 46
1694 12:26:54.669404 [Byte1]: 46
1695 12:26:54.673863
1696 12:26:54.673951 Set Vref, RX VrefLevel [Byte0]: 47
1697 12:26:54.677448 [Byte1]: 47
1698 12:26:54.681253
1699 12:26:54.681338 Set Vref, RX VrefLevel [Byte0]: 48
1700 12:26:54.684837 [Byte1]: 48
1701 12:26:54.689231
1702 12:26:54.689321 Set Vref, RX VrefLevel [Byte0]: 49
1703 12:26:54.692509 [Byte1]: 49
1704 12:26:54.697098
1705 12:26:54.697183 Set Vref, RX VrefLevel [Byte0]: 50
1706 12:26:54.700281 [Byte1]: 50
1707 12:26:54.704319
1708 12:26:54.704444 Set Vref, RX VrefLevel [Byte0]: 51
1709 12:26:54.707621 [Byte1]: 51
1710 12:26:54.712194
1711 12:26:54.712274 Set Vref, RX VrefLevel [Byte0]: 52
1712 12:26:54.715289 [Byte1]: 52
1713 12:26:54.719434
1714 12:26:54.719553 Set Vref, RX VrefLevel [Byte0]: 53
1715 12:26:54.722689 [Byte1]: 53
1716 12:26:54.727112
1717 12:26:54.727221 Set Vref, RX VrefLevel [Byte0]: 54
1718 12:26:54.730307 [Byte1]: 54
1719 12:26:54.734559
1720 12:26:54.734667 Set Vref, RX VrefLevel [Byte0]: 55
1721 12:26:54.738346 [Byte1]: 55
1722 12:26:54.742152
1723 12:26:54.742233 Set Vref, RX VrefLevel [Byte0]: 56
1724 12:26:54.745411 [Byte1]: 56
1725 12:26:54.749789
1726 12:26:54.749908 Set Vref, RX VrefLevel [Byte0]: 57
1727 12:26:54.753054 [Byte1]: 57
1728 12:26:54.757349
1729 12:26:54.757460 Set Vref, RX VrefLevel [Byte0]: 58
1730 12:26:54.761135 [Byte1]: 58
1731 12:26:54.764786
1732 12:26:54.764871 Set Vref, RX VrefLevel [Byte0]: 59
1733 12:26:54.768473 [Byte1]: 59
1734 12:26:54.772868
1735 12:26:54.775849 Set Vref, RX VrefLevel [Byte0]: 60
1736 12:26:54.778919 [Byte1]: 60
1737 12:26:54.779022
1738 12:26:54.782619 Set Vref, RX VrefLevel [Byte0]: 61
1739 12:26:54.785940 [Byte1]: 61
1740 12:26:54.786050
1741 12:26:54.789110 Set Vref, RX VrefLevel [Byte0]: 62
1742 12:26:54.792238 [Byte1]: 62
1743 12:26:54.795385
1744 12:26:54.795486 Set Vref, RX VrefLevel [Byte0]: 63
1745 12:26:54.798640 [Byte1]: 63
1746 12:26:54.803026
1747 12:26:54.803144 Set Vref, RX VrefLevel [Byte0]: 64
1748 12:26:54.806239 [Byte1]: 64
1749 12:26:54.810688
1750 12:26:54.810797 Set Vref, RX VrefLevel [Byte0]: 65
1751 12:26:54.813892 [Byte1]: 65
1752 12:26:54.818290
1753 12:26:54.818391 Set Vref, RX VrefLevel [Byte0]: 66
1754 12:26:54.821360 [Byte1]: 66
1755 12:26:54.825776
1756 12:26:54.825857 Set Vref, RX VrefLevel [Byte0]: 67
1757 12:26:54.828944 [Byte1]: 67
1758 12:26:54.833420
1759 12:26:54.833494 Set Vref, RX VrefLevel [Byte0]: 68
1760 12:26:54.836474 [Byte1]: 68
1761 12:26:54.841292
1762 12:26:54.841367 Set Vref, RX VrefLevel [Byte0]: 69
1763 12:26:54.844272 [Byte1]: 69
1764 12:26:54.848645
1765 12:26:54.848730 Set Vref, RX VrefLevel [Byte0]: 70
1766 12:26:54.851863 [Byte1]: 70
1767 12:26:54.856062
1768 12:26:54.856147 Set Vref, RX VrefLevel [Byte0]: 71
1769 12:26:54.859967 [Byte1]: 71
1770 12:26:54.863627
1771 12:26:54.863725 Set Vref, RX VrefLevel [Byte0]: 72
1772 12:26:54.867528 [Byte1]: 72
1773 12:26:54.871237
1774 12:26:54.874378 Set Vref, RX VrefLevel [Byte0]: 73
1775 12:26:54.878356 [Byte1]: 73
1776 12:26:54.878433
1777 12:26:54.881369 Set Vref, RX VrefLevel [Byte0]: 74
1778 12:26:54.884602 [Byte1]: 74
1779 12:26:54.884681
1780 12:26:54.887807 Set Vref, RX VrefLevel [Byte0]: 75
1781 12:26:54.890967 [Byte1]: 75
1782 12:26:54.891078
1783 12:26:54.894208 Final RX Vref Byte 0 = 56 to rank0
1784 12:26:54.898033 Final RX Vref Byte 1 = 64 to rank0
1785 12:26:54.901342 Final RX Vref Byte 0 = 56 to rank1
1786 12:26:54.904622 Final RX Vref Byte 1 = 64 to rank1==
1787 12:26:54.907875 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 12:26:54.911080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 12:26:54.914279 ==
1790 12:26:54.914386 DQS Delay:
1791 12:26:54.914480 DQS0 = 0, DQS1 = 0
1792 12:26:54.917542 DQM Delay:
1793 12:26:54.917627 DQM0 = 86, DQM1 = 79
1794 12:26:54.920826 DQ Delay:
1795 12:26:54.924364 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1796 12:26:54.924469 DQ4 =84, DQ5 =100, DQ6 =96, DQ7 =80
1797 12:26:54.927576 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1798 12:26:54.933955 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1799 12:26:54.934080
1800 12:26:54.934175
1801 12:26:54.940461 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1802 12:26:54.944311 CH1 RK0: MR19=606, MR18=301C
1803 12:26:54.950552 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1804 12:26:54.950666
1805 12:26:54.954247 ----->DramcWriteLeveling(PI) begin...
1806 12:26:54.954354 ==
1807 12:26:54.957376 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 12:26:54.960523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 12:26:54.960623 ==
1810 12:26:54.963648 Write leveling (Byte 0): 28 => 28
1811 12:26:54.966974 Write leveling (Byte 1): 30 => 30
1812 12:26:54.970116 DramcWriteLeveling(PI) end<-----
1813 12:26:54.970193
1814 12:26:54.970257 ==
1815 12:26:54.973915 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 12:26:54.977053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 12:26:54.977129 ==
1818 12:26:54.980565 [Gating] SW mode calibration
1819 12:26:54.986819 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 12:26:54.993656 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 12:26:54.996941 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1822 12:26:55.003555 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 12:26:55.006808 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:26:55.009946 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:26:55.017047 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:26:55.020085 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:26:55.023320 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:26:55.030152 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:26:55.033364 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:26:55.036447 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:26:55.042759 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:26:55.046434 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:26:55.049584 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:26:55.056011 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:26:55.059520 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:26:55.062509 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:26:55.069621 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:26:55.072681 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1839 12:26:55.076163 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:26:55.082519 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:26:55.086227 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:26:55.089238 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:26:55.095871 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:26:55.099092 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:26:55.102309 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:26:55.105988 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:26:55.113061 0 9 8 | B1->B0 | 3030 2929 | 1 1 | (1 1) (1 1)
1848 12:26:55.115633 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 12:26:55.118992 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:26:55.126030 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:26:55.129087 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 12:26:55.132876 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 12:26:55.138913 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 12:26:55.142324 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
1855 12:26:55.145464 0 10 8 | B1->B0 | 2424 2e2e | 1 0 | (1 0) (1 1)
1856 12:26:55.152307 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:26:55.155479 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:26:55.158781 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:26:55.165953 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:26:55.169093 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:26:55.172270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:26:55.178903 0 11 4 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
1863 12:26:55.182051 0 11 8 | B1->B0 | 4343 4040 | 0 0 | (0 0) (0 0)
1864 12:26:55.185220 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:26:55.192069 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:26:55.195133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:26:55.198879 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:26:55.205110 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:26:55.209090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:26:55.212196 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:26:55.218481 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1872 12:26:55.221827 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:26:55.225068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:26:55.232064 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:26:55.235067 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:26:55.238399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:26:55.244939 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:26:55.248189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:26:55.251393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:26:55.257851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:26:55.261149 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:26:55.265015 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:26:55.271294 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:26:55.274587 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:26:55.277819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1886 12:26:55.284246 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1887 12:26:55.287953 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1888 12:26:55.290935 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 12:26:55.294788 Total UI for P1: 0, mck2ui 16
1890 12:26:55.297944 best dqsien dly found for B0: ( 0, 14, 8)
1891 12:26:55.300875 Total UI for P1: 0, mck2ui 16
1892 12:26:55.304322 best dqsien dly found for B1: ( 0, 14, 4)
1893 12:26:55.307365 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1894 12:26:55.310971 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 12:26:55.311081
1896 12:26:55.314590 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1897 12:26:55.320975 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 12:26:55.321076 [Gating] SW calibration Done
1899 12:26:55.321154 ==
1900 12:26:55.324328 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 12:26:55.330783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 12:26:55.330897 ==
1903 12:26:55.331009 RX Vref Scan: 0
1904 12:26:55.331101
1905 12:26:55.333977 RX Vref 0 -> 0, step: 1
1906 12:26:55.334064
1907 12:26:55.337816 RX Delay -130 -> 252, step: 16
1908 12:26:55.340873 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1909 12:26:55.344186 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1910 12:26:55.347320 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1911 12:26:55.353807 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1912 12:26:55.357671 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1913 12:26:55.360642 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1914 12:26:55.363995 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1915 12:26:55.367128 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1916 12:26:55.374182 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1917 12:26:55.377388 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1918 12:26:55.380873 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1919 12:26:55.383964 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1920 12:26:55.390296 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1921 12:26:55.394157 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1922 12:26:55.397304 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1923 12:26:55.400551 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1924 12:26:55.400630 ==
1925 12:26:55.403689 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 12:26:55.407245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 12:26:55.410355 ==
1928 12:26:55.410462 DQS Delay:
1929 12:26:55.410564 DQS0 = 0, DQS1 = 0
1930 12:26:55.413518 DQM Delay:
1931 12:26:55.413633 DQM0 = 87, DQM1 = 81
1932 12:26:55.417213 DQ Delay:
1933 12:26:55.420280 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1934 12:26:55.423903 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1935 12:26:55.427105 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1936 12:26:55.430356 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 12:26:55.430459
1938 12:26:55.430555
1939 12:26:55.430645 ==
1940 12:26:55.433547 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 12:26:55.436954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 12:26:55.437065 ==
1943 12:26:55.437163
1944 12:26:55.437253
1945 12:26:55.440287 TX Vref Scan disable
1946 12:26:55.440396 == TX Byte 0 ==
1947 12:26:55.446615 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1948 12:26:55.449950 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1949 12:26:55.450064 == TX Byte 1 ==
1950 12:26:55.456464 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1951 12:26:55.459800 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1952 12:26:55.459885 ==
1953 12:26:55.463559 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:26:55.466752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:26:55.466861 ==
1956 12:26:55.480636 TX Vref=22, minBit 8, minWin=26, winSum=444
1957 12:26:55.483958 TX Vref=24, minBit 8, minWin=27, winSum=447
1958 12:26:55.487944 TX Vref=26, minBit 13, minWin=27, winSum=451
1959 12:26:55.491147 TX Vref=28, minBit 13, minWin=27, winSum=452
1960 12:26:55.494256 TX Vref=30, minBit 9, minWin=27, winSum=451
1961 12:26:55.500776 TX Vref=32, minBit 8, minWin=27, winSum=449
1962 12:26:55.503995 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1963 12:26:55.504120
1964 12:26:55.507229 Final TX Range 1 Vref 28
1965 12:26:55.507344
1966 12:26:55.507450 ==
1967 12:26:55.510479 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 12:26:55.514191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 12:26:55.517331 ==
1970 12:26:55.517413
1971 12:26:55.517479
1972 12:26:55.517575 TX Vref Scan disable
1973 12:26:55.520952 == TX Byte 0 ==
1974 12:26:55.524008 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1975 12:26:55.530632 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1976 12:26:55.530749 == TX Byte 1 ==
1977 12:26:55.533986 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1978 12:26:55.540945 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1979 12:26:55.541056
1980 12:26:55.541151 [DATLAT]
1981 12:26:55.541252 Freq=800, CH1 RK1
1982 12:26:55.541355
1983 12:26:55.544084 DATLAT Default: 0x9
1984 12:26:55.544191 0, 0xFFFF, sum = 0
1985 12:26:55.547588 1, 0xFFFF, sum = 0
1986 12:26:55.550691 2, 0xFFFF, sum = 0
1987 12:26:55.550803 3, 0xFFFF, sum = 0
1988 12:26:55.553898 4, 0xFFFF, sum = 0
1989 12:26:55.554014 5, 0xFFFF, sum = 0
1990 12:26:55.557159 6, 0xFFFF, sum = 0
1991 12:26:55.557285 7, 0xFFFF, sum = 0
1992 12:26:55.560898 8, 0xFFFF, sum = 0
1993 12:26:55.561014 9, 0x0, sum = 1
1994 12:26:55.564211 10, 0x0, sum = 2
1995 12:26:55.564320 11, 0x0, sum = 3
1996 12:26:55.567244 12, 0x0, sum = 4
1997 12:26:55.567355 best_step = 10
1998 12:26:55.567452
1999 12:26:55.567545 ==
2000 12:26:55.570881 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 12:26:55.574013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 12:26:55.574101 ==
2003 12:26:55.577238 RX Vref Scan: 0
2004 12:26:55.577347
2005 12:26:55.580484 RX Vref 0 -> 0, step: 1
2006 12:26:55.580581
2007 12:26:55.580646 RX Delay -95 -> 252, step: 8
2008 12:26:55.587596 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2009 12:26:55.590742 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2010 12:26:55.594417 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2011 12:26:55.597569 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2012 12:26:55.601366 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2013 12:26:55.607522 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2014 12:26:55.610646 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2015 12:26:55.614478 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2016 12:26:55.617461 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2017 12:26:55.621201 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2018 12:26:55.627205 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2019 12:26:55.630818 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2020 12:26:55.634210 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2021 12:26:55.637340 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2022 12:26:55.643758 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2023 12:26:55.647500 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2024 12:26:55.647586 ==
2025 12:26:55.650569 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 12:26:55.653633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 12:26:55.653716 ==
2028 12:26:55.657409 DQS Delay:
2029 12:26:55.657490 DQS0 = 0, DQS1 = 0
2030 12:26:55.657568 DQM Delay:
2031 12:26:55.660616 DQM0 = 87, DQM1 = 78
2032 12:26:55.660725 DQ Delay:
2033 12:26:55.663769 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2034 12:26:55.667409 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2035 12:26:55.670562 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2036 12:26:55.673610 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2037 12:26:55.673694
2038 12:26:55.673760
2039 12:26:55.683634 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2040 12:26:55.683718 CH1 RK1: MR19=606, MR18=1A12
2041 12:26:55.690517 CH1_RK1: MR19=0x606, MR18=0x1A12, DQSOSC=403, MR23=63, INC=90, DEC=60
2042 12:26:55.693645 [RxdqsGatingPostProcess] freq 800
2043 12:26:55.699980 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 12:26:55.703508 Pre-setting of DQS Precalculation
2045 12:26:55.707215 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
2046 12:26:55.713417 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 12:26:55.723278 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 12:26:55.723370
2049 12:26:55.723437
2050 12:26:55.726929 [Calibration Summary] 1600 Mbps
2051 12:26:55.727006 CH 0, Rank 0
2052 12:26:55.729965 SW Impedance : PASS
2053 12:26:55.730081 DUTY Scan : NO K
2054 12:26:55.733089 ZQ Calibration : PASS
2055 12:26:55.736608 Jitter Meter : NO K
2056 12:26:55.736686 CBT Training : PASS
2057 12:26:55.740058 Write leveling : PASS
2058 12:26:55.743308 RX DQS gating : PASS
2059 12:26:55.743393 RX DQ/DQS(RDDQC) : PASS
2060 12:26:55.746472 TX DQ/DQS : PASS
2061 12:26:55.749705 RX DATLAT : PASS
2062 12:26:55.749790 RX DQ/DQS(Engine): PASS
2063 12:26:55.753459 TX OE : NO K
2064 12:26:55.753543 All Pass.
2065 12:26:55.753609
2066 12:26:55.753670 CH 0, Rank 1
2067 12:26:55.756535 SW Impedance : PASS
2068 12:26:55.759935 DUTY Scan : NO K
2069 12:26:55.760026 ZQ Calibration : PASS
2070 12:26:55.763620 Jitter Meter : NO K
2071 12:26:55.766822 CBT Training : PASS
2072 12:26:55.766906 Write leveling : PASS
2073 12:26:55.769994 RX DQS gating : PASS
2074 12:26:55.773182 RX DQ/DQS(RDDQC) : PASS
2075 12:26:55.773265 TX DQ/DQS : PASS
2076 12:26:55.776422 RX DATLAT : PASS
2077 12:26:55.779969 RX DQ/DQS(Engine): PASS
2078 12:26:55.780053 TX OE : NO K
2079 12:26:55.783087 All Pass.
2080 12:26:55.783176
2081 12:26:55.783243 CH 1, Rank 0
2082 12:26:55.786213 SW Impedance : PASS
2083 12:26:55.786297 DUTY Scan : NO K
2084 12:26:55.790053 ZQ Calibration : PASS
2085 12:26:55.793281 Jitter Meter : NO K
2086 12:26:55.793365 CBT Training : PASS
2087 12:26:55.796421 Write leveling : PASS
2088 12:26:55.799536 RX DQS gating : PASS
2089 12:26:55.799620 RX DQ/DQS(RDDQC) : PASS
2090 12:26:55.802793 TX DQ/DQS : PASS
2091 12:26:55.802877 RX DATLAT : PASS
2092 12:26:55.806649 RX DQ/DQS(Engine): PASS
2093 12:26:55.809709 TX OE : NO K
2094 12:26:55.809795 All Pass.
2095 12:26:55.809864
2096 12:26:55.809932 CH 1, Rank 1
2097 12:26:55.812865 SW Impedance : PASS
2098 12:26:55.816536 DUTY Scan : NO K
2099 12:26:55.816614 ZQ Calibration : PASS
2100 12:26:55.819878 Jitter Meter : NO K
2101 12:26:55.822959 CBT Training : PASS
2102 12:26:55.823043 Write leveling : PASS
2103 12:26:55.826498 RX DQS gating : PASS
2104 12:26:55.829510 RX DQ/DQS(RDDQC) : PASS
2105 12:26:55.829595 TX DQ/DQS : PASS
2106 12:26:55.833304 RX DATLAT : PASS
2107 12:26:55.836548 RX DQ/DQS(Engine): PASS
2108 12:26:55.836633 TX OE : NO K
2109 12:26:55.839553 All Pass.
2110 12:26:55.839637
2111 12:26:55.839704 DramC Write-DBI off
2112 12:26:55.843172 PER_BANK_REFRESH: Hybrid Mode
2113 12:26:55.843257 TX_TRACKING: ON
2114 12:26:55.846048 [GetDramInforAfterCalByMRR] Vendor 6.
2115 12:26:55.853043 [GetDramInforAfterCalByMRR] Revision 606.
2116 12:26:55.856277 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 12:26:55.856365 MR0 0x3b3b
2118 12:26:55.856433 MR8 0x5151
2119 12:26:55.859988 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 12:26:55.860073
2121 12:26:55.863243 MR0 0x3b3b
2122 12:26:55.863361 MR8 0x5151
2123 12:26:55.866542 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 12:26:55.866654
2125 12:26:55.876306 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 12:26:55.879548 [FAST_K] Save calibration result to emmc
2127 12:26:55.882661 [FAST_K] Save calibration result to emmc
2128 12:26:55.886432 dram_init: config_dvfs: 1
2129 12:26:55.889586 dramc_set_vcore_voltage set vcore to 662500
2130 12:26:55.893361 Read voltage for 1200, 2
2131 12:26:55.893466 Vio18 = 0
2132 12:26:55.893564 Vcore = 662500
2133 12:26:55.893666 Vdram = 0
2134 12:26:55.896022 Vddq = 0
2135 12:26:55.896129 Vmddr = 0
2136 12:26:55.902541 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 12:26:55.905809 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 12:26:55.909572 MEM_TYPE=3, freq_sel=15
2139 12:26:55.912875 sv_algorithm_assistance_LP4_1600
2140 12:26:55.915860 ============ PULL DRAM RESETB DOWN ============
2141 12:26:55.919035 ========== PULL DRAM RESETB DOWN end =========
2142 12:26:55.926141 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 12:26:55.929395 ===================================
2144 12:26:55.929511 LPDDR4 DRAM CONFIGURATION
2145 12:26:55.932934 ===================================
2146 12:26:55.936166 EX_ROW_EN[0] = 0x0
2147 12:26:55.939309 EX_ROW_EN[1] = 0x0
2148 12:26:55.939422 LP4Y_EN = 0x0
2149 12:26:55.942452 WORK_FSP = 0x0
2150 12:26:55.942531 WL = 0x4
2151 12:26:55.945625 RL = 0x4
2152 12:26:55.945729 BL = 0x2
2153 12:26:55.949377 RPST = 0x0
2154 12:26:55.949485 RD_PRE = 0x0
2155 12:26:55.952959 WR_PRE = 0x1
2156 12:26:55.953066 WR_PST = 0x0
2157 12:26:55.956252 DBI_WR = 0x0
2158 12:26:55.956354 DBI_RD = 0x0
2159 12:26:55.959434 OTF = 0x1
2160 12:26:55.962593 ===================================
2161 12:26:55.965834 ===================================
2162 12:26:55.965958 ANA top config
2163 12:26:55.968951 ===================================
2164 12:26:55.972251 DLL_ASYNC_EN = 0
2165 12:26:55.975438 ALL_SLAVE_EN = 0
2166 12:26:55.978794 NEW_RANK_MODE = 1
2167 12:26:55.978908 DLL_IDLE_MODE = 1
2168 12:26:55.982526 LP45_APHY_COMB_EN = 1
2169 12:26:55.985743 TX_ODT_DIS = 1
2170 12:26:55.988811 NEW_8X_MODE = 1
2171 12:26:55.991951 ===================================
2172 12:26:55.995878 ===================================
2173 12:26:55.999103 data_rate = 2400
2174 12:26:55.999215 CKR = 1
2175 12:26:56.002328 DQ_P2S_RATIO = 8
2176 12:26:56.005454 ===================================
2177 12:26:56.008676 CA_P2S_RATIO = 8
2178 12:26:56.012522 DQ_CA_OPEN = 0
2179 12:26:56.015659 DQ_SEMI_OPEN = 0
2180 12:26:56.018615 CA_SEMI_OPEN = 0
2181 12:26:56.018727 CA_FULL_RATE = 0
2182 12:26:56.022405 DQ_CKDIV4_EN = 0
2183 12:26:56.025616 CA_CKDIV4_EN = 0
2184 12:26:56.028789 CA_PREDIV_EN = 0
2185 12:26:56.031991 PH8_DLY = 17
2186 12:26:56.035221 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 12:26:56.035335 DQ_AAMCK_DIV = 4
2188 12:26:56.038375 CA_AAMCK_DIV = 4
2189 12:26:56.042232 CA_ADMCK_DIV = 4
2190 12:26:56.045407 DQ_TRACK_CA_EN = 0
2191 12:26:56.048616 CA_PICK = 1200
2192 12:26:56.051833 CA_MCKIO = 1200
2193 12:26:56.055527 MCKIO_SEMI = 0
2194 12:26:56.055642 PLL_FREQ = 2366
2195 12:26:56.058693 DQ_UI_PI_RATIO = 32
2196 12:26:56.061858 CA_UI_PI_RATIO = 0
2197 12:26:56.065054 ===================================
2198 12:26:56.068126 ===================================
2199 12:26:56.071970 memory_type:LPDDR4
2200 12:26:56.072048 GP_NUM : 10
2201 12:26:56.075303 SRAM_EN : 1
2202 12:26:56.078548 MD32_EN : 0
2203 12:26:56.081951 ===================================
2204 12:26:56.082037 [ANA_INIT] >>>>>>>>>>>>>>
2205 12:26:56.085187 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 12:26:56.088443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 12:26:56.091641 ===================================
2208 12:26:56.094865 data_rate = 2400,PCW = 0X5b00
2209 12:26:56.098086 ===================================
2210 12:26:56.101422 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 12:26:56.108412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 12:26:56.111722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 12:26:56.118146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 12:26:56.121364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 12:26:56.125090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 12:26:56.128336 [ANA_INIT] flow start
2217 12:26:56.128444 [ANA_INIT] PLL >>>>>>>>
2218 12:26:56.131530 [ANA_INIT] PLL <<<<<<<<
2219 12:26:56.134706 [ANA_INIT] MIDPI >>>>>>>>
2220 12:26:56.134815 [ANA_INIT] MIDPI <<<<<<<<
2221 12:26:56.137773 [ANA_INIT] DLL >>>>>>>>
2222 12:26:56.141557 [ANA_INIT] DLL <<<<<<<<
2223 12:26:56.141669 [ANA_INIT] flow end
2224 12:26:56.147967 ============ LP4 DIFF to SE enter ============
2225 12:26:56.151253 ============ LP4 DIFF to SE exit ============
2226 12:26:56.154567 [ANA_INIT] <<<<<<<<<<<<<
2227 12:26:56.157679 [Flow] Enable top DCM control >>>>>
2228 12:26:56.157789 [Flow] Enable top DCM control <<<<<
2229 12:26:56.161406 Enable DLL master slave shuffle
2230 12:26:56.168032 ==============================================================
2231 12:26:56.171692 Gating Mode config
2232 12:26:56.174315 ==============================================================
2233 12:26:56.177517 Config description:
2234 12:26:56.187956 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 12:26:56.194366 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 12:26:56.197647 SELPH_MODE 0: By rank 1: By Phase
2237 12:26:56.203948 ==============================================================
2238 12:26:56.207764 GAT_TRACK_EN = 1
2239 12:26:56.210868 RX_GATING_MODE = 2
2240 12:26:56.214015 RX_GATING_TRACK_MODE = 2
2241 12:26:56.214100 SELPH_MODE = 1
2242 12:26:56.217807 PICG_EARLY_EN = 1
2243 12:26:56.221037 VALID_LAT_VALUE = 1
2244 12:26:56.227189 ==============================================================
2245 12:26:56.230872 Enter into Gating configuration >>>>
2246 12:26:56.234078 Exit from Gating configuration <<<<
2247 12:26:56.236986 Enter into DVFS_PRE_config >>>>>
2248 12:26:56.247327 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 12:26:56.250508 Exit from DVFS_PRE_config <<<<<
2250 12:26:56.253650 Enter into PICG configuration >>>>
2251 12:26:56.257621 Exit from PICG configuration <<<<
2252 12:26:56.260968 [RX_INPUT] configuration >>>>>
2253 12:26:56.263939 [RX_INPUT] configuration <<<<<
2254 12:26:56.267061 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 12:26:56.273606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 12:26:56.280685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 12:26:56.287178 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 12:26:56.293437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 12:26:56.297294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 12:26:56.303521 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 12:26:56.306803 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 12:26:56.310622 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 12:26:56.313911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 12:26:56.320211 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 12:26:56.324051 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 12:26:56.327156 ===================================
2267 12:26:56.330396 LPDDR4 DRAM CONFIGURATION
2268 12:26:56.333582 ===================================
2269 12:26:56.333669 EX_ROW_EN[0] = 0x0
2270 12:26:56.336846 EX_ROW_EN[1] = 0x0
2271 12:26:56.336941 LP4Y_EN = 0x0
2272 12:26:56.339995 WORK_FSP = 0x0
2273 12:26:56.340080 WL = 0x4
2274 12:26:56.343854 RL = 0x4
2275 12:26:56.343939 BL = 0x2
2276 12:26:56.346991 RPST = 0x0
2277 12:26:56.347081 RD_PRE = 0x0
2278 12:26:56.350233 WR_PRE = 0x1
2279 12:26:56.350347 WR_PST = 0x0
2280 12:26:56.353329 DBI_WR = 0x0
2281 12:26:56.356512 DBI_RD = 0x0
2282 12:26:56.356619 OTF = 0x1
2283 12:26:56.360380 ===================================
2284 12:26:56.363504 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 12:26:56.366588 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 12:26:56.373400 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 12:26:56.376664 ===================================
2288 12:26:56.379791 LPDDR4 DRAM CONFIGURATION
2289 12:26:56.382969 ===================================
2290 12:26:56.383082 EX_ROW_EN[0] = 0x10
2291 12:26:56.386801 EX_ROW_EN[1] = 0x0
2292 12:26:56.386918 LP4Y_EN = 0x0
2293 12:26:56.389971 WORK_FSP = 0x0
2294 12:26:56.390054 WL = 0x4
2295 12:26:56.393248 RL = 0x4
2296 12:26:56.393357 BL = 0x2
2297 12:26:56.396547 RPST = 0x0
2298 12:26:56.396655 RD_PRE = 0x0
2299 12:26:56.399722 WR_PRE = 0x1
2300 12:26:56.399826 WR_PST = 0x0
2301 12:26:56.402917 DBI_WR = 0x0
2302 12:26:56.403030 DBI_RD = 0x0
2303 12:26:56.406160 OTF = 0x1
2304 12:26:56.409913 ===================================
2305 12:26:56.416261 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 12:26:56.416373 ==
2307 12:26:56.419401 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 12:26:56.423133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 12:26:56.423246 ==
2310 12:26:56.426373 [Duty_Offset_Calibration]
2311 12:26:56.426487 B0:1 B1:-1 CA:0
2312 12:26:56.426581
2313 12:26:56.429576 [DutyScan_Calibration_Flow] k_type=0
2314 12:26:56.440568
2315 12:26:56.440678 ==CLK 0==
2316 12:26:56.443693 Final CLK duty delay cell = 0
2317 12:26:56.447471 [0] MAX Duty = 5125%(X100), DQS PI = 22
2318 12:26:56.450533 [0] MIN Duty = 4875%(X100), DQS PI = 10
2319 12:26:56.450641 [0] AVG Duty = 5000%(X100)
2320 12:26:56.454235
2321 12:26:56.457270 CH0 CLK Duty spec in!! Max-Min= 250%
2322 12:26:56.460491 [DutyScan_Calibration_Flow] ====Done====
2323 12:26:56.460599
2324 12:26:56.463691 [DutyScan_Calibration_Flow] k_type=1
2325 12:26:56.478947
2326 12:26:56.479063 ==DQS 0 ==
2327 12:26:56.482794 Final DQS duty delay cell = -4
2328 12:26:56.485814 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2329 12:26:56.488955 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2330 12:26:56.492240 [-4] AVG Duty = 4968%(X100)
2331 12:26:56.492349
2332 12:26:56.492448 ==DQS 1 ==
2333 12:26:56.495928 Final DQS duty delay cell = 0
2334 12:26:56.499163 [0] MAX Duty = 5124%(X100), DQS PI = 4
2335 12:26:56.502283 [0] MIN Duty = 5000%(X100), DQS PI = 22
2336 12:26:56.505475 [0] AVG Duty = 5062%(X100)
2337 12:26:56.505586
2338 12:26:56.509370 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2339 12:26:56.509475
2340 12:26:56.512743 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2341 12:26:56.515754 [DutyScan_Calibration_Flow] ====Done====
2342 12:26:56.515862
2343 12:26:56.519038 [DutyScan_Calibration_Flow] k_type=3
2344 12:26:56.536663
2345 12:26:56.536779 ==DQM 0 ==
2346 12:26:56.540278 Final DQM duty delay cell = 0
2347 12:26:56.543324 [0] MAX Duty = 5031%(X100), DQS PI = 16
2348 12:26:56.547127 [0] MIN Duty = 4875%(X100), DQS PI = 8
2349 12:26:56.547233 [0] AVG Duty = 4953%(X100)
2350 12:26:56.550114
2351 12:26:56.550223 ==DQM 1 ==
2352 12:26:56.553260 Final DQM duty delay cell = 4
2353 12:26:56.556412 [4] MAX Duty = 5156%(X100), DQS PI = 8
2354 12:26:56.560135 [4] MIN Duty = 4969%(X100), DQS PI = 26
2355 12:26:56.560241 [4] AVG Duty = 5062%(X100)
2356 12:26:56.563168
2357 12:26:56.566374 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2358 12:26:56.566485
2359 12:26:56.570118 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2360 12:26:56.573227 [DutyScan_Calibration_Flow] ====Done====
2361 12:26:56.573331
2362 12:26:56.576800 [DutyScan_Calibration_Flow] k_type=2
2363 12:26:56.592193
2364 12:26:56.592308 ==DQ 0 ==
2365 12:26:56.595935 Final DQ duty delay cell = -4
2366 12:26:56.599092 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2367 12:26:56.602349 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2368 12:26:56.605512 [-4] AVG Duty = 4969%(X100)
2369 12:26:56.605624
2370 12:26:56.605719 ==DQ 1 ==
2371 12:26:56.609268 Final DQ duty delay cell = 0
2372 12:26:56.612349 [0] MAX Duty = 5093%(X100), DQS PI = 4
2373 12:26:56.615412 [0] MIN Duty = 4969%(X100), DQS PI = 40
2374 12:26:56.619000 [0] AVG Duty = 5031%(X100)
2375 12:26:56.619106
2376 12:26:56.622170 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2377 12:26:56.622278
2378 12:26:56.625985 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2379 12:26:56.629194 [DutyScan_Calibration_Flow] ====Done====
2380 12:26:56.629300 ==
2381 12:26:56.632296 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 12:26:56.635437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 12:26:56.635549 ==
2384 12:26:56.639114 [Duty_Offset_Calibration]
2385 12:26:56.639218 B0:-1 B1:1 CA:2
2386 12:26:56.639312
2387 12:26:56.642298 [DutyScan_Calibration_Flow] k_type=0
2388 12:26:56.652975
2389 12:26:56.653092 ==CLK 0==
2390 12:26:56.656077 Final CLK duty delay cell = 0
2391 12:26:56.659126 [0] MAX Duty = 5156%(X100), DQS PI = 22
2392 12:26:56.662858 [0] MIN Duty = 4969%(X100), DQS PI = 62
2393 12:26:56.662966 [0] AVG Duty = 5062%(X100)
2394 12:26:56.666029
2395 12:26:56.666136 CH1 CLK Duty spec in!! Max-Min= 187%
2396 12:26:56.672465 [DutyScan_Calibration_Flow] ====Done====
2397 12:26:56.672586
2398 12:26:56.676228 [DutyScan_Calibration_Flow] k_type=1
2399 12:26:56.692064
2400 12:26:56.692185 ==DQS 0 ==
2401 12:26:56.695127 Final DQS duty delay cell = 0
2402 12:26:56.698908 [0] MAX Duty = 5125%(X100), DQS PI = 16
2403 12:26:56.702159 [0] MIN Duty = 4907%(X100), DQS PI = 6
2404 12:26:56.705351 [0] AVG Duty = 5016%(X100)
2405 12:26:56.705460
2406 12:26:56.705554 ==DQS 1 ==
2407 12:26:56.708551 Final DQS duty delay cell = 0
2408 12:26:56.711779 [0] MAX Duty = 5062%(X100), DQS PI = 10
2409 12:26:56.715040 [0] MIN Duty = 4969%(X100), DQS PI = 58
2410 12:26:56.718702 [0] AVG Duty = 5015%(X100)
2411 12:26:56.718812
2412 12:26:56.721774 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2413 12:26:56.721887
2414 12:26:56.725667 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2415 12:26:56.728829 [DutyScan_Calibration_Flow] ====Done====
2416 12:26:56.728938
2417 12:26:56.731950 [DutyScan_Calibration_Flow] k_type=3
2418 12:26:56.747554
2419 12:26:56.747672 ==DQM 0 ==
2420 12:26:56.750870 Final DQM duty delay cell = -4
2421 12:26:56.754125 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2422 12:26:56.757287 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2423 12:26:56.761015 [-4] AVG Duty = 4969%(X100)
2424 12:26:56.761091
2425 12:26:56.761156 ==DQM 1 ==
2426 12:26:56.764020 Final DQM duty delay cell = 0
2427 12:26:56.767738 [0] MAX Duty = 5156%(X100), DQS PI = 6
2428 12:26:56.770785 [0] MIN Duty = 5000%(X100), DQS PI = 28
2429 12:26:56.774016 [0] AVG Duty = 5078%(X100)
2430 12:26:56.774092
2431 12:26:56.777162 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2432 12:26:56.777239
2433 12:26:56.780390 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2434 12:26:56.784068 [DutyScan_Calibration_Flow] ====Done====
2435 12:26:56.784170
2436 12:26:56.787619 [DutyScan_Calibration_Flow] k_type=2
2437 12:26:56.804413
2438 12:26:56.804532 ==DQ 0 ==
2439 12:26:56.807572 Final DQ duty delay cell = 0
2440 12:26:56.810864 [0] MAX Duty = 5187%(X100), DQS PI = 30
2441 12:26:56.814053 [0] MIN Duty = 4907%(X100), DQS PI = 8
2442 12:26:56.814169 [0] AVG Duty = 5047%(X100)
2443 12:26:56.814270
2444 12:26:56.817829 ==DQ 1 ==
2445 12:26:56.821219 Final DQ duty delay cell = 0
2446 12:26:56.824203 [0] MAX Duty = 5124%(X100), DQS PI = 10
2447 12:26:56.828006 [0] MIN Duty = 4969%(X100), DQS PI = 0
2448 12:26:56.828166 [0] AVG Duty = 5046%(X100)
2449 12:26:56.828240
2450 12:26:56.831035 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2451 12:26:56.831159
2452 12:26:56.837357 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2453 12:26:56.841104 [DutyScan_Calibration_Flow] ====Done====
2454 12:26:56.844253 nWR fixed to 30
2455 12:26:56.844445 [ModeRegInit_LP4] CH0 RK0
2456 12:26:56.847571 [ModeRegInit_LP4] CH0 RK1
2457 12:26:56.850634 [ModeRegInit_LP4] CH1 RK0
2458 12:26:56.850805 [ModeRegInit_LP4] CH1 RK1
2459 12:26:56.854341 match AC timing 7
2460 12:26:56.857486 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 12:26:56.860699 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 12:26:56.867513 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 12:26:56.870564 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 12:26:56.877340 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 12:26:56.877539 ==
2466 12:26:56.880511 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 12:26:56.883756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 12:26:56.883951 ==
2469 12:26:56.890474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 12:26:56.897206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2471 12:26:56.903939 [CA 0] Center 39 (9~70) winsize 62
2472 12:26:56.907677 [CA 1] Center 39 (9~69) winsize 61
2473 12:26:56.910725 [CA 2] Center 35 (5~66) winsize 62
2474 12:26:56.913917 [CA 3] Center 35 (4~66) winsize 63
2475 12:26:56.917661 [CA 4] Center 33 (4~63) winsize 60
2476 12:26:56.920843 [CA 5] Center 33 (3~63) winsize 61
2477 12:26:56.921090
2478 12:26:56.923978 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2479 12:26:56.924111
2480 12:26:56.927615 [CATrainingPosCal] consider 1 rank data
2481 12:26:56.930580 u2DelayCellTimex100 = 270/100 ps
2482 12:26:56.934382 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 12:26:56.937477 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2484 12:26:56.943784 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 12:26:56.947585 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2486 12:26:56.950663 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2487 12:26:56.953765 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2488 12:26:56.953916
2489 12:26:56.957447 CA PerBit enable=1, Macro0, CA PI delay=33
2490 12:26:56.957594
2491 12:26:56.960573 [CBTSetCACLKResult] CA Dly = 33
2492 12:26:56.960713 CS Dly: 8 (0~39)
2493 12:26:56.963737 ==
2494 12:26:56.967439 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 12:26:56.970576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 12:26:56.970734 ==
2497 12:26:56.973584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 12:26:56.980623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2499 12:26:56.990447 [CA 0] Center 39 (9~70) winsize 62
2500 12:26:56.993317 [CA 1] Center 39 (9~70) winsize 62
2501 12:26:56.996860 [CA 2] Center 35 (5~66) winsize 62
2502 12:26:56.999925 [CA 3] Center 34 (4~65) winsize 62
2503 12:26:57.002919 [CA 4] Center 33 (3~64) winsize 62
2504 12:26:57.006663 [CA 5] Center 33 (3~63) winsize 61
2505 12:26:57.006773
2506 12:26:57.009774 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 12:26:57.009882
2508 12:26:57.013474 [CATrainingPosCal] consider 2 rank data
2509 12:26:57.016653 u2DelayCellTimex100 = 270/100 ps
2510 12:26:57.019786 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 12:26:57.022857 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2512 12:26:57.029832 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 12:26:57.033020 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2514 12:26:57.036780 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2515 12:26:57.040010 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2516 12:26:57.040117
2517 12:26:57.043191 CA PerBit enable=1, Macro0, CA PI delay=33
2518 12:26:57.043297
2519 12:26:57.046350 [CBTSetCACLKResult] CA Dly = 33
2520 12:26:57.046467 CS Dly: 9 (0~41)
2521 12:26:57.046567
2522 12:26:57.049460 ----->DramcWriteLeveling(PI) begin...
2523 12:26:57.053300 ==
2524 12:26:57.056448 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 12:26:57.059656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 12:26:57.059783 ==
2527 12:26:57.062670 Write leveling (Byte 0): 32 => 32
2528 12:26:57.066512 Write leveling (Byte 1): 29 => 29
2529 12:26:57.069707 DramcWriteLeveling(PI) end<-----
2530 12:26:57.069826
2531 12:26:57.069923 ==
2532 12:26:57.072849 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 12:26:57.076031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 12:26:57.076146 ==
2535 12:26:57.079749 [Gating] SW mode calibration
2536 12:26:57.086528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 12:26:57.092824 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 12:26:57.096188 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2539 12:26:57.099796 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2540 12:26:57.103040 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 12:26:57.109733 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 12:26:57.112877 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 12:26:57.116528 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 12:26:57.122799 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 12:26:57.126023 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
2546 12:26:57.129187 1 0 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
2547 12:26:57.136239 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 12:26:57.139413 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:26:57.142504 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:26:57.149405 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:26:57.152534 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 12:26:57.155740 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 12:26:57.162714 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2554 12:26:57.165814 1 1 0 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2555 12:26:57.169533 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2556 12:26:57.175743 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:26:57.179449 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:26:57.182419 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:26:57.189238 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 12:26:57.192588 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 12:26:57.195860 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 12:26:57.202445 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2563 12:26:57.205576 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:26:57.208665 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:26:57.215322 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:26:57.219001 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:26:57.222113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:26:57.229262 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:26:57.232318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:26:57.235572 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:26:57.242012 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:26:57.245708 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:26:57.248907 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:26:57.255366 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:26:57.258592 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:26:57.262286 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 12:26:57.268640 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 12:26:57.272258 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2579 12:26:57.275365 Total UI for P1: 0, mck2ui 16
2580 12:26:57.278434 best dqsien dly found for B0: ( 1, 3, 26)
2581 12:26:57.282338 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 12:26:57.285418 Total UI for P1: 0, mck2ui 16
2583 12:26:57.288477 best dqsien dly found for B1: ( 1, 4, 0)
2584 12:26:57.291678 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2585 12:26:57.294930 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2586 12:26:57.295014
2587 12:26:57.298751 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2588 12:26:57.301954 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 12:26:57.305031 [Gating] SW calibration Done
2590 12:26:57.305121 ==
2591 12:26:57.308536 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 12:26:57.314906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 12:26:57.314990 ==
2594 12:26:57.315078 RX Vref Scan: 0
2595 12:26:57.315180
2596 12:26:57.318626 RX Vref 0 -> 0, step: 1
2597 12:26:57.318716
2598 12:26:57.321754 RX Delay -40 -> 252, step: 8
2599 12:26:57.324922 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2600 12:26:57.328081 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2601 12:26:57.331934 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2602 12:26:57.338182 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2603 12:26:57.341395 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2604 12:26:57.345045 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2605 12:26:57.348143 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2606 12:26:57.351658 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2607 12:26:57.354903 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2608 12:26:57.361237 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2609 12:26:57.365068 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2610 12:26:57.368403 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2611 12:26:57.371552 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2612 12:26:57.377947 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2613 12:26:57.381045 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2614 12:26:57.384869 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2615 12:26:57.384952 ==
2616 12:26:57.387903 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 12:26:57.391522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 12:26:57.391625 ==
2619 12:26:57.394637 DQS Delay:
2620 12:26:57.394719 DQS0 = 0, DQS1 = 0
2621 12:26:57.397720 DQM Delay:
2622 12:26:57.397817 DQM0 = 119, DQM1 = 107
2623 12:26:57.397885 DQ Delay:
2624 12:26:57.404696 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2625 12:26:57.407749 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2626 12:26:57.411336 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2627 12:26:57.414438 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2628 12:26:57.414521
2629 12:26:57.414585
2630 12:26:57.414645 ==
2631 12:26:57.417615 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 12:26:57.421337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 12:26:57.421421 ==
2634 12:26:57.421486
2635 12:26:57.421546
2636 12:26:57.424410 TX Vref Scan disable
2637 12:26:57.428068 == TX Byte 0 ==
2638 12:26:57.431278 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2639 12:26:57.434472 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2640 12:26:57.437664 == TX Byte 1 ==
2641 12:26:57.440911 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2642 12:26:57.444052 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2643 12:26:57.444162 ==
2644 12:26:57.447806 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 12:26:57.450882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 12:26:57.454014 ==
2647 12:26:57.464675 TX Vref=22, minBit 1, minWin=25, winSum=421
2648 12:26:57.467806 TX Vref=24, minBit 0, minWin=26, winSum=427
2649 12:26:57.470939 TX Vref=26, minBit 1, minWin=25, winSum=433
2650 12:26:57.474176 TX Vref=28, minBit 4, minWin=26, winSum=433
2651 12:26:57.477313 TX Vref=30, minBit 0, minWin=27, winSum=437
2652 12:26:57.484157 TX Vref=32, minBit 4, minWin=26, winSum=430
2653 12:26:57.487205 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 30
2654 12:26:57.487314
2655 12:26:57.490365 Final TX Range 1 Vref 30
2656 12:26:57.490475
2657 12:26:57.490567 ==
2658 12:26:57.493900 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 12:26:57.497650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 12:26:57.500626 ==
2661 12:26:57.500731
2662 12:26:57.500856
2663 12:26:57.500947 TX Vref Scan disable
2664 12:26:57.504405 == TX Byte 0 ==
2665 12:26:57.507474 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2666 12:26:57.514137 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2667 12:26:57.514253 == TX Byte 1 ==
2668 12:26:57.517275 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2669 12:26:57.523578 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2670 12:26:57.523684
2671 12:26:57.523777 [DATLAT]
2672 12:26:57.523867 Freq=1200, CH0 RK0
2673 12:26:57.523959
2674 12:26:57.527255 DATLAT Default: 0xd
2675 12:26:57.527359 0, 0xFFFF, sum = 0
2676 12:26:57.530387 1, 0xFFFF, sum = 0
2677 12:26:57.534048 2, 0xFFFF, sum = 0
2678 12:26:57.534151 3, 0xFFFF, sum = 0
2679 12:26:57.537155 4, 0xFFFF, sum = 0
2680 12:26:57.537226 5, 0xFFFF, sum = 0
2681 12:26:57.540305 6, 0xFFFF, sum = 0
2682 12:26:57.540402 7, 0xFFFF, sum = 0
2683 12:26:57.543594 8, 0xFFFF, sum = 0
2684 12:26:57.543697 9, 0xFFFF, sum = 0
2685 12:26:57.547336 10, 0xFFFF, sum = 0
2686 12:26:57.547437 11, 0xFFFF, sum = 0
2687 12:26:57.550431 12, 0x0, sum = 1
2688 12:26:57.550535 13, 0x0, sum = 2
2689 12:26:57.553571 14, 0x0, sum = 3
2690 12:26:57.553678 15, 0x0, sum = 4
2691 12:26:57.557365 best_step = 13
2692 12:26:57.557467
2693 12:26:57.557562 ==
2694 12:26:57.560338 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 12:26:57.563683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 12:26:57.563784 ==
2697 12:26:57.563875 RX Vref Scan: 1
2698 12:26:57.566886
2699 12:26:57.566987 Set Vref Range= 32 -> 127
2700 12:26:57.567081
2701 12:26:57.570010 RX Vref 32 -> 127, step: 1
2702 12:26:57.570111
2703 12:26:57.573834 RX Delay -21 -> 252, step: 4
2704 12:26:57.573940
2705 12:26:57.576892 Set Vref, RX VrefLevel [Byte0]: 32
2706 12:26:57.580122 [Byte1]: 32
2707 12:26:57.580228
2708 12:26:57.583182 Set Vref, RX VrefLevel [Byte0]: 33
2709 12:26:57.586959 [Byte1]: 33
2710 12:26:57.590661
2711 12:26:57.590774 Set Vref, RX VrefLevel [Byte0]: 34
2712 12:26:57.593853 [Byte1]: 34
2713 12:26:57.598768
2714 12:26:57.598851 Set Vref, RX VrefLevel [Byte0]: 35
2715 12:26:57.601898 [Byte1]: 35
2716 12:26:57.606239
2717 12:26:57.606318 Set Vref, RX VrefLevel [Byte0]: 36
2718 12:26:57.609414 [Byte1]: 36
2719 12:26:57.614397
2720 12:26:57.614477 Set Vref, RX VrefLevel [Byte0]: 37
2721 12:26:57.617428 [Byte1]: 37
2722 12:26:57.622437
2723 12:26:57.622537 Set Vref, RX VrefLevel [Byte0]: 38
2724 12:26:57.625641 [Byte1]: 38
2725 12:26:57.630004
2726 12:26:57.630076 Set Vref, RX VrefLevel [Byte0]: 39
2727 12:26:57.633685 [Byte1]: 39
2728 12:26:57.637963
2729 12:26:57.638037 Set Vref, RX VrefLevel [Byte0]: 40
2730 12:26:57.641229 [Byte1]: 40
2731 12:26:57.646312
2732 12:26:57.646456 Set Vref, RX VrefLevel [Byte0]: 41
2733 12:26:57.649368 [Byte1]: 41
2734 12:26:57.653838
2735 12:26:57.653946 Set Vref, RX VrefLevel [Byte0]: 42
2736 12:26:57.657000 [Byte1]: 42
2737 12:26:57.662102
2738 12:26:57.662250 Set Vref, RX VrefLevel [Byte0]: 43
2739 12:26:57.665100 [Byte1]: 43
2740 12:26:57.669471
2741 12:26:57.669575 Set Vref, RX VrefLevel [Byte0]: 44
2742 12:26:57.673295 [Byte1]: 44
2743 12:26:57.677636
2744 12:26:57.677742 Set Vref, RX VrefLevel [Byte0]: 45
2745 12:26:57.680798 [Byte1]: 45
2746 12:26:57.685646
2747 12:26:57.685731 Set Vref, RX VrefLevel [Byte0]: 46
2748 12:26:57.688723 [Byte1]: 46
2749 12:26:57.693780
2750 12:26:57.693855 Set Vref, RX VrefLevel [Byte0]: 47
2751 12:26:57.696838 [Byte1]: 47
2752 12:26:57.701184
2753 12:26:57.701280 Set Vref, RX VrefLevel [Byte0]: 48
2754 12:26:57.704870 [Byte1]: 48
2755 12:26:57.709155
2756 12:26:57.709231 Set Vref, RX VrefLevel [Byte0]: 49
2757 12:26:57.712423 [Byte1]: 49
2758 12:26:57.717540
2759 12:26:57.717612 Set Vref, RX VrefLevel [Byte0]: 50
2760 12:26:57.720534 [Byte1]: 50
2761 12:26:57.725356
2762 12:26:57.725428 Set Vref, RX VrefLevel [Byte0]: 51
2763 12:26:57.728503 [Byte1]: 51
2764 12:26:57.732936
2765 12:26:57.733018 Set Vref, RX VrefLevel [Byte0]: 52
2766 12:26:57.736458 [Byte1]: 52
2767 12:26:57.741056
2768 12:26:57.741140 Set Vref, RX VrefLevel [Byte0]: 53
2769 12:26:57.744319 [Byte1]: 53
2770 12:26:57.748842
2771 12:26:57.748944 Set Vref, RX VrefLevel [Byte0]: 54
2772 12:26:57.752300 [Byte1]: 54
2773 12:26:57.756893
2774 12:26:57.756975 Set Vref, RX VrefLevel [Byte0]: 55
2775 12:26:57.760436 [Byte1]: 55
2776 12:26:57.764836
2777 12:26:57.764916 Set Vref, RX VrefLevel [Byte0]: 56
2778 12:26:57.767884 [Byte1]: 56
2779 12:26:57.772946
2780 12:26:57.773028 Set Vref, RX VrefLevel [Byte0]: 57
2781 12:26:57.776161 [Byte1]: 57
2782 12:26:57.780532
2783 12:26:57.780616 Set Vref, RX VrefLevel [Byte0]: 58
2784 12:26:57.783778 [Byte1]: 58
2785 12:26:57.788671
2786 12:26:57.788770 Set Vref, RX VrefLevel [Byte0]: 59
2787 12:26:57.791641 [Byte1]: 59
2788 12:26:57.796705
2789 12:26:57.796792 Set Vref, RX VrefLevel [Byte0]: 60
2790 12:26:57.799643 [Byte1]: 60
2791 12:26:57.804566
2792 12:26:57.804675 Set Vref, RX VrefLevel [Byte0]: 61
2793 12:26:57.807712 [Byte1]: 61
2794 12:26:57.812573
2795 12:26:57.812655 Set Vref, RX VrefLevel [Byte0]: 62
2796 12:26:57.818447 [Byte1]: 62
2797 12:26:57.818529
2798 12:26:57.822323 Set Vref, RX VrefLevel [Byte0]: 63
2799 12:26:57.825339 [Byte1]: 63
2800 12:26:57.825423
2801 12:26:57.828881 Set Vref, RX VrefLevel [Byte0]: 64
2802 12:26:57.832344 [Byte1]: 64
2803 12:26:57.836237
2804 12:26:57.836337 Set Vref, RX VrefLevel [Byte0]: 65
2805 12:26:57.839283 [Byte1]: 65
2806 12:26:57.844232
2807 12:26:57.844340 Set Vref, RX VrefLevel [Byte0]: 66
2808 12:26:57.847388 [Byte1]: 66
2809 12:26:57.851864
2810 12:26:57.851944 Set Vref, RX VrefLevel [Byte0]: 67
2811 12:26:57.855070 [Byte1]: 67
2812 12:26:57.860103
2813 12:26:57.860177 Set Vref, RX VrefLevel [Byte0]: 68
2814 12:26:57.863271 [Byte1]: 68
2815 12:26:57.867805
2816 12:26:57.867906 Set Vref, RX VrefLevel [Byte0]: 69
2817 12:26:57.870917 [Byte1]: 69
2818 12:26:57.875838
2819 12:26:57.875914 Set Vref, RX VrefLevel [Byte0]: 70
2820 12:26:57.878864 [Byte1]: 70
2821 12:26:57.883897
2822 12:26:57.883971 Set Vref, RX VrefLevel [Byte0]: 71
2823 12:26:57.886987 [Byte1]: 71
2824 12:26:57.891460
2825 12:26:57.891533 Set Vref, RX VrefLevel [Byte0]: 72
2826 12:26:57.895209 [Byte1]: 72
2827 12:26:57.899383
2828 12:26:57.899454 Set Vref, RX VrefLevel [Byte0]: 73
2829 12:26:57.902623 [Byte1]: 73
2830 12:26:57.907623
2831 12:26:57.907706 Set Vref, RX VrefLevel [Byte0]: 74
2832 12:26:57.910792 [Byte1]: 74
2833 12:26:57.915599
2834 12:26:57.915681 Set Vref, RX VrefLevel [Byte0]: 75
2835 12:26:57.918673 [Byte1]: 75
2836 12:26:57.923147
2837 12:26:57.923245 Set Vref, RX VrefLevel [Byte0]: 76
2838 12:26:57.926898 [Byte1]: 76
2839 12:26:57.931179
2840 12:26:57.931264 Set Vref, RX VrefLevel [Byte0]: 77
2841 12:26:57.934905 [Byte1]: 77
2842 12:26:57.939255
2843 12:26:57.939340 Final RX Vref Byte 0 = 61 to rank0
2844 12:26:57.942341 Final RX Vref Byte 1 = 50 to rank0
2845 12:26:57.945950 Final RX Vref Byte 0 = 61 to rank1
2846 12:26:57.948989 Final RX Vref Byte 1 = 50 to rank1==
2847 12:26:57.952237 Dram Type= 6, Freq= 0, CH_0, rank 0
2848 12:26:57.959271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 12:26:57.959395 ==
2850 12:26:57.959492 DQS Delay:
2851 12:26:57.962316 DQS0 = 0, DQS1 = 0
2852 12:26:57.962431 DQM Delay:
2853 12:26:57.962522 DQM0 = 119, DQM1 = 106
2854 12:26:57.965394 DQ Delay:
2855 12:26:57.969169 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2856 12:26:57.972342 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2857 12:26:57.975515 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2858 12:26:57.978553 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2859 12:26:57.978629
2860 12:26:57.978699
2861 12:26:57.988846 [DQSOSCAuto] RK0, (LSB)MR18= 0xffb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2862 12:26:57.988934 CH0 RK0: MR19=403, MR18=FFB
2863 12:26:57.995280 CH0_RK0: MR19=0x403, MR18=0xFFB, DQSOSC=404, MR23=63, INC=40, DEC=26
2864 12:26:57.995360
2865 12:26:57.998981 ----->DramcWriteLeveling(PI) begin...
2866 12:26:57.999091 ==
2867 12:26:58.002196 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 12:26:58.005315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 12:26:58.008805 ==
2870 12:26:58.011978 Write leveling (Byte 0): 32 => 32
2871 12:26:58.012082 Write leveling (Byte 1): 29 => 29
2872 12:26:58.015055 DramcWriteLeveling(PI) end<-----
2873 12:26:58.015167
2874 12:26:58.015267 ==
2875 12:26:58.018791 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 12:26:58.024970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 12:26:58.025086 ==
2878 12:26:58.028273 [Gating] SW mode calibration
2879 12:26:58.035057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2880 12:26:58.038620 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2881 12:26:58.045386 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2882 12:26:58.048323 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2883 12:26:58.052052 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 12:26:58.058269 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 12:26:58.061505 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 12:26:58.064723 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 12:26:58.071575 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2888 12:26:58.074799 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2889 12:26:58.078001 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2890 12:26:58.081797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 12:26:58.088195 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 12:26:58.091406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 12:26:58.095000 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 12:26:58.101306 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 12:26:58.104928 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 12:26:58.108055 1 0 28 | B1->B0 | 2424 3130 | 0 1 | (0 0) (0 0)
2897 12:26:58.114931 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2898 12:26:58.117950 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 12:26:58.121530 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 12:26:58.127879 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 12:26:58.131596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 12:26:58.134646 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 12:26:58.141257 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 12:26:58.144404 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2905 12:26:58.148193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2906 12:26:58.154316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 12:26:58.158036 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 12:26:58.161178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 12:26:58.167420 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 12:26:58.171179 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 12:26:58.174368 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 12:26:58.180805 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 12:26:58.184687 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 12:26:58.187736 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 12:26:58.194345 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 12:26:58.197445 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:26:58.201370 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:26:58.207531 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:26:58.211265 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:26:58.214340 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2921 12:26:58.220769 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2922 12:26:58.220875 Total UI for P1: 0, mck2ui 16
2923 12:26:58.227843 best dqsien dly found for B0: ( 1, 3, 28)
2924 12:26:58.230922 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 12:26:58.234246 Total UI for P1: 0, mck2ui 16
2926 12:26:58.237379 best dqsien dly found for B1: ( 1, 4, 0)
2927 12:26:58.241233 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2928 12:26:58.244290 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2929 12:26:58.244403
2930 12:26:58.247433 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2931 12:26:58.250547 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2932 12:26:58.253751 [Gating] SW calibration Done
2933 12:26:58.253866 ==
2934 12:26:58.257580 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 12:26:58.260682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 12:26:58.260794 ==
2937 12:26:58.263889 RX Vref Scan: 0
2938 12:26:58.263974
2939 12:26:58.267652 RX Vref 0 -> 0, step: 1
2940 12:26:58.267737
2941 12:26:58.267804 RX Delay -40 -> 252, step: 8
2942 12:26:58.273923 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2943 12:26:58.277092 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2944 12:26:58.280963 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2945 12:26:58.284262 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2946 12:26:58.287288 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2947 12:26:58.294301 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2948 12:26:58.297492 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2949 12:26:58.300536 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2950 12:26:58.303784 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2951 12:26:58.307616 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2952 12:26:58.310776 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2953 12:26:58.317680 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2954 12:26:58.320883 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2955 12:26:58.323971 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2956 12:26:58.327123 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2957 12:26:58.333909 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2958 12:26:58.333992 ==
2959 12:26:58.337677 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 12:26:58.340782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 12:26:58.340857 ==
2962 12:26:58.340921 DQS Delay:
2963 12:26:58.344036 DQS0 = 0, DQS1 = 0
2964 12:26:58.344108 DQM Delay:
2965 12:26:58.346967 DQM0 = 117, DQM1 = 108
2966 12:26:58.347052 DQ Delay:
2967 12:26:58.350643 DQ0 =115, DQ1 =123, DQ2 =111, DQ3 =115
2968 12:26:58.353822 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2969 12:26:58.356933 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2970 12:26:58.360687 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2971 12:26:58.360783
2972 12:26:58.360873
2973 12:26:58.363626 ==
2974 12:26:58.367271 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 12:26:58.370448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 12:26:58.370531 ==
2977 12:26:58.370596
2978 12:26:58.370668
2979 12:26:58.373575 TX Vref Scan disable
2980 12:26:58.373685 == TX Byte 0 ==
2981 12:26:58.376853 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2982 12:26:58.383556 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2983 12:26:58.383662 == TX Byte 1 ==
2984 12:26:58.386728 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2985 12:26:58.393511 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2986 12:26:58.393622 ==
2987 12:26:58.396738 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 12:26:58.400040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 12:26:58.400127 ==
2990 12:26:58.412753 TX Vref=22, minBit 1, minWin=25, winSum=420
2991 12:26:58.415849 TX Vref=24, minBit 2, minWin=26, winSum=427
2992 12:26:58.418952 TX Vref=26, minBit 13, minWin=25, winSum=428
2993 12:26:58.422936 TX Vref=28, minBit 1, minWin=26, winSum=434
2994 12:26:58.426018 TX Vref=30, minBit 13, minWin=26, winSum=435
2995 12:26:58.432327 TX Vref=32, minBit 10, minWin=26, winSum=431
2996 12:26:58.435474 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 30
2997 12:26:58.435560
2998 12:26:58.439194 Final TX Range 1 Vref 30
2999 12:26:58.439281
3000 12:26:58.439357 ==
3001 12:26:58.442483 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 12:26:58.445542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 12:26:58.448644 ==
3004 12:26:58.448731
3005 12:26:58.448809
3006 12:26:58.448873 TX Vref Scan disable
3007 12:26:58.452390 == TX Byte 0 ==
3008 12:26:58.456122 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3009 12:26:58.462519 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3010 12:26:58.462660 == TX Byte 1 ==
3011 12:26:58.465710 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3012 12:26:58.472362 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3013 12:26:58.472509
3014 12:26:58.472619 [DATLAT]
3015 12:26:58.472717 Freq=1200, CH0 RK1
3016 12:26:58.472803
3017 12:26:58.475470 DATLAT Default: 0xd
3018 12:26:58.475588 0, 0xFFFF, sum = 0
3019 12:26:58.479340 1, 0xFFFF, sum = 0
3020 12:26:58.482604 2, 0xFFFF, sum = 0
3021 12:26:58.482703 3, 0xFFFF, sum = 0
3022 12:26:58.485861 4, 0xFFFF, sum = 0
3023 12:26:58.485975 5, 0xFFFF, sum = 0
3024 12:26:58.488996 6, 0xFFFF, sum = 0
3025 12:26:58.489102 7, 0xFFFF, sum = 0
3026 12:26:58.492668 8, 0xFFFF, sum = 0
3027 12:26:58.492749 9, 0xFFFF, sum = 0
3028 12:26:58.495859 10, 0xFFFF, sum = 0
3029 12:26:58.495939 11, 0xFFFF, sum = 0
3030 12:26:58.498861 12, 0x0, sum = 1
3031 12:26:58.498955 13, 0x0, sum = 2
3032 12:26:58.502690 14, 0x0, sum = 3
3033 12:26:58.502780 15, 0x0, sum = 4
3034 12:26:58.502866 best_step = 13
3035 12:26:58.505851
3036 12:26:58.505936 ==
3037 12:26:58.508987 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 12:26:58.512114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 12:26:58.512222 ==
3040 12:26:58.512329 RX Vref Scan: 0
3041 12:26:58.512430
3042 12:26:58.515972 RX Vref 0 -> 0, step: 1
3043 12:26:58.516063
3044 12:26:58.519089 RX Delay -21 -> 252, step: 4
3045 12:26:58.522163 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3046 12:26:58.529088 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3047 12:26:58.532211 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3048 12:26:58.535419 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3049 12:26:58.539089 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3050 12:26:58.542259 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3051 12:26:58.548801 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3052 12:26:58.551926 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3053 12:26:58.555089 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3054 12:26:58.558561 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3055 12:26:58.562237 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3056 12:26:58.568472 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3057 12:26:58.572225 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3058 12:26:58.575292 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3059 12:26:58.578263 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3060 12:26:58.585301 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3061 12:26:58.585414 ==
3062 12:26:58.588331 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 12:26:58.591551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 12:26:58.591637 ==
3065 12:26:58.591704 DQS Delay:
3066 12:26:58.594677 DQS0 = 0, DQS1 = 0
3067 12:26:58.594760 DQM Delay:
3068 12:26:58.598523 DQM0 = 116, DQM1 = 108
3069 12:26:58.598600 DQ Delay:
3070 12:26:58.601693 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3071 12:26:58.605294 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3072 12:26:58.608462 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3073 12:26:58.611577 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3074 12:26:58.611692
3075 12:26:58.611797
3076 12:26:58.621729 [DQSOSCAuto] RK1, (LSB)MR18= 0x10eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3077 12:26:58.624886 CH0 RK1: MR19=403, MR18=10EB
3078 12:26:58.627977 CH0_RK1: MR19=0x403, MR18=0x10EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3079 12:26:58.631824 [RxdqsGatingPostProcess] freq 1200
3080 12:26:58.638072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3081 12:26:58.641175 best DQS0 dly(2T, 0.5T) = (0, 11)
3082 12:26:58.644822 best DQS1 dly(2T, 0.5T) = (0, 12)
3083 12:26:58.647911 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3084 12:26:58.651792 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3085 12:26:58.654976 best DQS0 dly(2T, 0.5T) = (0, 11)
3086 12:26:58.658049 best DQS1 dly(2T, 0.5T) = (0, 12)
3087 12:26:58.661593 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3088 12:26:58.664555 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3089 12:26:58.664642 Pre-setting of DQS Precalculation
3090 12:26:58.671052 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3091 12:26:58.671178 ==
3092 12:26:58.674274 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 12:26:58.677877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 12:26:58.677957 ==
3095 12:26:58.684867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 12:26:58.691129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3097 12:26:58.698959 [CA 0] Center 37 (7~67) winsize 61
3098 12:26:58.702124 [CA 1] Center 38 (8~68) winsize 61
3099 12:26:58.705250 [CA 2] Center 34 (4~64) winsize 61
3100 12:26:58.708832 [CA 3] Center 33 (3~64) winsize 62
3101 12:26:58.712069 [CA 4] Center 34 (4~64) winsize 61
3102 12:26:58.715287 [CA 5] Center 33 (3~64) winsize 62
3103 12:26:58.715392
3104 12:26:58.718440 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3105 12:26:58.718519
3106 12:26:58.722268 [CATrainingPosCal] consider 1 rank data
3107 12:26:58.725578 u2DelayCellTimex100 = 270/100 ps
3108 12:26:58.728660 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3109 12:26:58.731839 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3110 12:26:58.738608 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 12:26:58.741794 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3112 12:26:58.745540 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 12:26:58.748656 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3114 12:26:58.748734
3115 12:26:58.751862 CA PerBit enable=1, Macro0, CA PI delay=33
3116 12:26:58.751938
3117 12:26:58.755461 [CBTSetCACLKResult] CA Dly = 33
3118 12:26:58.755584 CS Dly: 5 (0~36)
3119 12:26:58.758548 ==
3120 12:26:58.758676 Dram Type= 6, Freq= 0, CH_1, rank 1
3121 12:26:58.765389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 12:26:58.765506 ==
3123 12:26:58.768376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3124 12:26:58.774911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3125 12:26:58.784653 [CA 0] Center 37 (7~68) winsize 62
3126 12:26:58.787647 [CA 1] Center 38 (8~68) winsize 61
3127 12:26:58.790789 [CA 2] Center 34 (4~65) winsize 62
3128 12:26:58.794473 [CA 3] Center 33 (3~64) winsize 62
3129 12:26:58.797644 [CA 4] Center 34 (4~65) winsize 62
3130 12:26:58.801366 [CA 5] Center 33 (3~64) winsize 62
3131 12:26:58.801484
3132 12:26:58.804486 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3133 12:26:58.804625
3134 12:26:58.807651 [CATrainingPosCal] consider 2 rank data
3135 12:26:58.810751 u2DelayCellTimex100 = 270/100 ps
3136 12:26:58.813973 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3137 12:26:58.817792 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3138 12:26:58.824117 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3139 12:26:58.828019 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3140 12:26:58.831147 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 12:26:58.834111 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 12:26:58.834214
3143 12:26:58.837883 CA PerBit enable=1, Macro0, CA PI delay=33
3144 12:26:58.837977
3145 12:26:58.841041 [CBTSetCACLKResult] CA Dly = 33
3146 12:26:58.841121 CS Dly: 7 (0~40)
3147 12:26:58.841188
3148 12:26:58.844147 ----->DramcWriteLeveling(PI) begin...
3149 12:26:58.847324 ==
3150 12:26:58.850912 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 12:26:58.854089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 12:26:58.854219 ==
3153 12:26:58.857896 Write leveling (Byte 0): 25 => 25
3154 12:26:58.860979 Write leveling (Byte 1): 26 => 26
3155 12:26:58.864149 DramcWriteLeveling(PI) end<-----
3156 12:26:58.864263
3157 12:26:58.864363 ==
3158 12:26:58.867152 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 12:26:58.870815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 12:26:58.870928 ==
3161 12:26:58.873849 [Gating] SW mode calibration
3162 12:26:58.880713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3163 12:26:58.887463 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3164 12:26:58.890614 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3165 12:26:58.893742 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 12:26:58.900774 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 12:26:58.904019 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 12:26:58.907293 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 12:26:58.913647 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 12:26:58.917358 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
3171 12:26:58.920659 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3172 12:26:58.927024 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 12:26:58.930285 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 12:26:58.933437 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 12:26:58.937236 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 12:26:58.943430 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 12:26:58.947151 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 12:26:58.950456 1 0 24 | B1->B0 | 2727 3b3a | 0 1 | (0 0) (0 0)
3179 12:26:58.956485 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 12:26:58.960190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 12:26:58.963347 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 12:26:58.969741 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 12:26:58.973519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:26:58.976629 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 12:26:58.983355 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 12:26:58.986488 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3187 12:26:58.989541 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3188 12:26:58.996291 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3189 12:26:59.000025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 12:26:59.003247 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 12:26:59.009596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 12:26:59.012814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 12:26:59.016580 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 12:26:59.022866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 12:26:59.026061 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 12:26:59.029906 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 12:26:59.036278 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 12:26:59.039428 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:26:59.043050 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 12:26:59.049496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:26:59.052804 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:26:59.055987 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3203 12:26:59.063190 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3204 12:26:59.066260 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 12:26:59.069444 Total UI for P1: 0, mck2ui 16
3206 12:26:59.073168 best dqsien dly found for B0: ( 1, 3, 26)
3207 12:26:59.076195 Total UI for P1: 0, mck2ui 16
3208 12:26:59.079197 best dqsien dly found for B1: ( 1, 3, 26)
3209 12:26:59.082954 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3210 12:26:59.086070 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3211 12:26:59.086149
3212 12:26:59.089175 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3213 12:26:59.093003 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3214 12:26:59.096081 [Gating] SW calibration Done
3215 12:26:59.096166 ==
3216 12:26:59.099222 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 12:26:59.102926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 12:26:59.106067 ==
3219 12:26:59.106152 RX Vref Scan: 0
3220 12:26:59.106219
3221 12:26:59.109240 RX Vref 0 -> 0, step: 1
3222 12:26:59.109325
3223 12:26:59.109391 RX Delay -40 -> 252, step: 8
3224 12:26:59.116354 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3225 12:26:59.119576 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3226 12:26:59.122751 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3227 12:26:59.125948 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3228 12:26:59.129722 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3229 12:26:59.135952 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3230 12:26:59.139585 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3231 12:26:59.142819 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3232 12:26:59.145892 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3233 12:26:59.149057 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3234 12:26:59.155911 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3235 12:26:59.159017 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3236 12:26:59.162189 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3237 12:26:59.165852 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3238 12:26:59.172081 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3239 12:26:59.175446 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3240 12:26:59.175565 ==
3241 12:26:59.178614 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 12:26:59.182446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 12:26:59.182569 ==
3244 12:26:59.185536 DQS Delay:
3245 12:26:59.185613 DQS0 = 0, DQS1 = 0
3246 12:26:59.185695 DQM Delay:
3247 12:26:59.188964 DQM0 = 118, DQM1 = 109
3248 12:26:59.189051 DQ Delay:
3249 12:26:59.192082 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3250 12:26:59.195234 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3251 12:26:59.199016 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3252 12:26:59.202108 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3253 12:26:59.205133
3254 12:26:59.205222
3255 12:26:59.205290 ==
3256 12:26:59.208870 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 12:26:59.212072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 12:26:59.212150 ==
3259 12:26:59.212237
3260 12:26:59.212304
3261 12:26:59.215282 TX Vref Scan disable
3262 12:26:59.215357 == TX Byte 0 ==
3263 12:26:59.222191 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3264 12:26:59.225458 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3265 12:26:59.225537 == TX Byte 1 ==
3266 12:26:59.231859 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3267 12:26:59.235066 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3268 12:26:59.235185 ==
3269 12:26:59.238807 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 12:26:59.241844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 12:26:59.241927 ==
3272 12:26:59.254383 TX Vref=22, minBit 10, minWin=25, winSum=418
3273 12:26:59.257550 TX Vref=24, minBit 15, minWin=25, winSum=425
3274 12:26:59.260723 TX Vref=26, minBit 11, minWin=25, winSum=427
3275 12:26:59.263985 TX Vref=28, minBit 10, minWin=25, winSum=432
3276 12:26:59.267101 TX Vref=30, minBit 9, minWin=25, winSum=430
3277 12:26:59.273787 TX Vref=32, minBit 9, minWin=25, winSum=425
3278 12:26:59.277623 [TxChooseVref] Worse bit 10, Min win 25, Win sum 432, Final Vref 28
3279 12:26:59.277749
3280 12:26:59.280772 Final TX Range 1 Vref 28
3281 12:26:59.280852
3282 12:26:59.280924 ==
3283 12:26:59.283961 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 12:26:59.290603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 12:26:59.290691 ==
3286 12:26:59.290759
3287 12:26:59.290823
3288 12:26:59.290883 TX Vref Scan disable
3289 12:26:59.294698 == TX Byte 0 ==
3290 12:26:59.297844 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3291 12:26:59.304216 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3292 12:26:59.304304 == TX Byte 1 ==
3293 12:26:59.307308 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3294 12:26:59.314241 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3295 12:26:59.314333
3296 12:26:59.314400 [DATLAT]
3297 12:26:59.314461 Freq=1200, CH1 RK0
3298 12:26:59.314519
3299 12:26:59.317400 DATLAT Default: 0xd
3300 12:26:59.317471 0, 0xFFFF, sum = 0
3301 12:26:59.320488 1, 0xFFFF, sum = 0
3302 12:26:59.324296 2, 0xFFFF, sum = 0
3303 12:26:59.324409 3, 0xFFFF, sum = 0
3304 12:26:59.327422 4, 0xFFFF, sum = 0
3305 12:26:59.327537 5, 0xFFFF, sum = 0
3306 12:26:59.330810 6, 0xFFFF, sum = 0
3307 12:26:59.330928 7, 0xFFFF, sum = 0
3308 12:26:59.333880 8, 0xFFFF, sum = 0
3309 12:26:59.333958 9, 0xFFFF, sum = 0
3310 12:26:59.337525 10, 0xFFFF, sum = 0
3311 12:26:59.337615 11, 0xFFFF, sum = 0
3312 12:26:59.340617 12, 0x0, sum = 1
3313 12:26:59.340698 13, 0x0, sum = 2
3314 12:26:59.343783 14, 0x0, sum = 3
3315 12:26:59.343886 15, 0x0, sum = 4
3316 12:26:59.347002 best_step = 13
3317 12:26:59.347075
3318 12:26:59.347137 ==
3319 12:26:59.350915 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 12:26:59.353906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 12:26:59.354019 ==
3322 12:26:59.354115 RX Vref Scan: 1
3323 12:26:59.354205
3324 12:26:59.356979 Set Vref Range= 32 -> 127
3325 12:26:59.357082
3326 12:26:59.360903 RX Vref 32 -> 127, step: 1
3327 12:26:59.360986
3328 12:26:59.364039 RX Delay -21 -> 252, step: 4
3329 12:26:59.364122
3330 12:26:59.367262 Set Vref, RX VrefLevel [Byte0]: 32
3331 12:26:59.370351 [Byte1]: 32
3332 12:26:59.370439
3333 12:26:59.373939 Set Vref, RX VrefLevel [Byte0]: 33
3334 12:26:59.376944 [Byte1]: 33
3335 12:26:59.380853
3336 12:26:59.380936 Set Vref, RX VrefLevel [Byte0]: 34
3337 12:26:59.384064 [Byte1]: 34
3338 12:26:59.388508
3339 12:26:59.388601 Set Vref, RX VrefLevel [Byte0]: 35
3340 12:26:59.392146 [Byte1]: 35
3341 12:26:59.396316
3342 12:26:59.396400 Set Vref, RX VrefLevel [Byte0]: 36
3343 12:26:59.400041 [Byte1]: 36
3344 12:26:59.404422
3345 12:26:59.404542 Set Vref, RX VrefLevel [Byte0]: 37
3346 12:26:59.407523 [Byte1]: 37
3347 12:26:59.412380
3348 12:26:59.412486 Set Vref, RX VrefLevel [Byte0]: 38
3349 12:26:59.416034 [Byte1]: 38
3350 12:26:59.420372
3351 12:26:59.420456 Set Vref, RX VrefLevel [Byte0]: 39
3352 12:26:59.423530 [Byte1]: 39
3353 12:26:59.428051
3354 12:26:59.428170 Set Vref, RX VrefLevel [Byte0]: 40
3355 12:26:59.431805 [Byte1]: 40
3356 12:26:59.436247
3357 12:26:59.436325 Set Vref, RX VrefLevel [Byte0]: 41
3358 12:26:59.439485 [Byte1]: 41
3359 12:26:59.443814
3360 12:26:59.443898 Set Vref, RX VrefLevel [Byte0]: 42
3361 12:26:59.447534 [Byte1]: 42
3362 12:26:59.452023
3363 12:26:59.452167 Set Vref, RX VrefLevel [Byte0]: 43
3364 12:26:59.455264 [Byte1]: 43
3365 12:26:59.459546
3366 12:26:59.459660 Set Vref, RX VrefLevel [Byte0]: 44
3367 12:26:59.463446 [Byte1]: 44
3368 12:26:59.467680
3369 12:26:59.467796 Set Vref, RX VrefLevel [Byte0]: 45
3370 12:26:59.470901 [Byte1]: 45
3371 12:26:59.475770
3372 12:26:59.475852 Set Vref, RX VrefLevel [Byte0]: 46
3373 12:26:59.478841 [Byte1]: 46
3374 12:26:59.483768
3375 12:26:59.483887 Set Vref, RX VrefLevel [Byte0]: 47
3376 12:26:59.486844 [Byte1]: 47
3377 12:26:59.491350
3378 12:26:59.491436 Set Vref, RX VrefLevel [Byte0]: 48
3379 12:26:59.495082 [Byte1]: 48
3380 12:26:59.499435
3381 12:26:59.499539 Set Vref, RX VrefLevel [Byte0]: 49
3382 12:26:59.502967 [Byte1]: 49
3383 12:26:59.507139
3384 12:26:59.507219 Set Vref, RX VrefLevel [Byte0]: 50
3385 12:26:59.511043 [Byte1]: 50
3386 12:26:59.515196
3387 12:26:59.515273 Set Vref, RX VrefLevel [Byte0]: 51
3388 12:26:59.518269 [Byte1]: 51
3389 12:26:59.523318
3390 12:26:59.523395 Set Vref, RX VrefLevel [Byte0]: 52
3391 12:26:59.526530 [Byte1]: 52
3392 12:26:59.530873
3393 12:26:59.530953 Set Vref, RX VrefLevel [Byte0]: 53
3394 12:26:59.534142 [Byte1]: 53
3395 12:26:59.539275
3396 12:26:59.539353 Set Vref, RX VrefLevel [Byte0]: 54
3397 12:26:59.542468 [Byte1]: 54
3398 12:26:59.546914
3399 12:26:59.547001 Set Vref, RX VrefLevel [Byte0]: 55
3400 12:26:59.549997 [Byte1]: 55
3401 12:26:59.555144
3402 12:26:59.555232 Set Vref, RX VrefLevel [Byte0]: 56
3403 12:26:59.558322 [Byte1]: 56
3404 12:26:59.562501
3405 12:26:59.562582 Set Vref, RX VrefLevel [Byte0]: 57
3406 12:26:59.565746 [Byte1]: 57
3407 12:26:59.570803
3408 12:26:59.570891 Set Vref, RX VrefLevel [Byte0]: 58
3409 12:26:59.573919 [Byte1]: 58
3410 12:26:59.578400
3411 12:26:59.578507 Set Vref, RX VrefLevel [Byte0]: 59
3412 12:26:59.581939 [Byte1]: 59
3413 12:26:59.586385
3414 12:26:59.586465 Set Vref, RX VrefLevel [Byte0]: 60
3415 12:26:59.590176 [Byte1]: 60
3416 12:26:59.594621
3417 12:26:59.594708 Set Vref, RX VrefLevel [Byte0]: 61
3418 12:26:59.597797 [Byte1]: 61
3419 12:26:59.602204
3420 12:26:59.602299 Set Vref, RX VrefLevel [Byte0]: 62
3421 12:26:59.605774 [Byte1]: 62
3422 12:26:59.609991
3423 12:26:59.610070 Set Vref, RX VrefLevel [Byte0]: 63
3424 12:26:59.613760 [Byte1]: 63
3425 12:26:59.618114
3426 12:26:59.618204 Set Vref, RX VrefLevel [Byte0]: 64
3427 12:26:59.621636 [Byte1]: 64
3428 12:26:59.626232
3429 12:26:59.626311 Set Vref, RX VrefLevel [Byte0]: 65
3430 12:26:59.629321 [Byte1]: 65
3431 12:26:59.633786
3432 12:26:59.633864 Set Vref, RX VrefLevel [Byte0]: 66
3433 12:26:59.637567 [Byte1]: 66
3434 12:26:59.641995
3435 12:26:59.642074 Final RX Vref Byte 0 = 48 to rank0
3436 12:26:59.645233 Final RX Vref Byte 1 = 57 to rank0
3437 12:26:59.648418 Final RX Vref Byte 0 = 48 to rank1
3438 12:26:59.651700 Final RX Vref Byte 1 = 57 to rank1==
3439 12:26:59.655412 Dram Type= 6, Freq= 0, CH_1, rank 0
3440 12:26:59.661866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 12:26:59.661986 ==
3442 12:26:59.662089 DQS Delay:
3443 12:26:59.662182 DQS0 = 0, DQS1 = 0
3444 12:26:59.665043 DQM Delay:
3445 12:26:59.665155 DQM0 = 115, DQM1 = 111
3446 12:26:59.668123 DQ Delay:
3447 12:26:59.671401 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =110
3448 12:26:59.675234 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =114
3449 12:26:59.678360 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =100
3450 12:26:59.681489 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3451 12:26:59.681595
3452 12:26:59.681690
3453 12:26:59.691897 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3454 12:26:59.692016 CH1 RK0: MR19=403, MR18=1F4
3455 12:26:59.698197 CH1_RK0: MR19=0x403, MR18=0x1F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3456 12:26:59.698320
3457 12:26:59.701425 ----->DramcWriteLeveling(PI) begin...
3458 12:26:59.701532 ==
3459 12:26:59.704619 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 12:26:59.711501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 12:26:59.711613 ==
3462 12:26:59.714460 Write leveling (Byte 0): 24 => 24
3463 12:26:59.718197 Write leveling (Byte 1): 27 => 27
3464 12:26:59.718306 DramcWriteLeveling(PI) end<-----
3465 12:26:59.718407
3466 12:26:59.721336 ==
3467 12:26:59.724301 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 12:26:59.727948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 12:26:59.728075 ==
3470 12:26:59.731291 [Gating] SW mode calibration
3471 12:26:59.737595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3472 12:26:59.740838 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3473 12:26:59.747623 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 12:26:59.750884 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 12:26:59.754155 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 12:26:59.761018 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 12:26:59.764096 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 12:26:59.767207 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3479 12:26:59.774119 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3480 12:26:59.777278 0 15 28 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
3481 12:26:59.780494 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 12:26:59.786788 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 12:26:59.790329 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 12:26:59.793280 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 12:26:59.800174 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 12:26:59.803314 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3487 12:26:59.806540 1 0 24 | B1->B0 | 3636 2727 | 0 0 | (0 0) (0 0)
3488 12:26:59.813444 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3489 12:26:59.816509 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 12:26:59.820170 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 12:26:59.826334 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 12:26:59.829870 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 12:26:59.833142 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 12:26:59.839642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 12:26:59.842871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3496 12:26:59.846155 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3497 12:26:59.852975 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:26:59.856166 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:26:59.859309 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:26:59.866388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:26:59.869494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 12:26:59.872657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:26:59.879366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 12:26:59.882972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 12:26:59.886131 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 12:26:59.892385 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 12:26:59.895947 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 12:26:59.899113 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 12:26:59.905923 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 12:26:59.909036 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 12:26:59.912213 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3512 12:26:59.919075 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 12:26:59.922642 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 12:26:59.925744 Total UI for P1: 0, mck2ui 16
3515 12:26:59.928887 best dqsien dly found for B0: ( 1, 3, 26)
3516 12:26:59.932025 Total UI for P1: 0, mck2ui 16
3517 12:26:59.935514 best dqsien dly found for B1: ( 1, 3, 26)
3518 12:26:59.938682 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3519 12:26:59.941883 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3520 12:26:59.941993
3521 12:26:59.945762 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3522 12:26:59.948864 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3523 12:26:59.952004 [Gating] SW calibration Done
3524 12:26:59.952117 ==
3525 12:26:59.955158 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 12:26:59.962161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 12:26:59.962252 ==
3528 12:26:59.962320 RX Vref Scan: 0
3529 12:26:59.962384
3530 12:26:59.965483 RX Vref 0 -> 0, step: 1
3531 12:26:59.965568
3532 12:26:59.968538 RX Delay -40 -> 252, step: 8
3533 12:26:59.971640 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3534 12:26:59.974888 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3535 12:26:59.978571 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3536 12:26:59.984977 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3537 12:26:59.988092 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3538 12:26:59.991821 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3539 12:26:59.994940 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3540 12:26:59.997997 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3541 12:27:00.004791 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3542 12:27:00.007870 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3543 12:27:00.011659 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3544 12:27:00.014765 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3545 12:27:00.017998 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3546 12:27:00.024749 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3547 12:27:00.027877 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3548 12:27:00.030998 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3549 12:27:00.031112 ==
3550 12:27:00.034562 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 12:27:00.037679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 12:27:00.037764 ==
3553 12:27:00.040852 DQS Delay:
3554 12:27:00.040936 DQS0 = 0, DQS1 = 0
3555 12:27:00.044449 DQM Delay:
3556 12:27:00.044539 DQM0 = 116, DQM1 = 110
3557 12:27:00.047680 DQ Delay:
3558 12:27:00.050818 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3559 12:27:00.054496 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3560 12:27:00.057669 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3561 12:27:00.060864 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3562 12:27:00.060948
3563 12:27:00.061014
3564 12:27:00.061075 ==
3565 12:27:00.064031 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 12:27:00.067896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 12:27:00.067983 ==
3568 12:27:00.068050
3569 12:27:00.068112
3570 12:27:00.071034 TX Vref Scan disable
3571 12:27:00.074240 == TX Byte 0 ==
3572 12:27:00.077371 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 12:27:00.080539 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 12:27:00.084243 == TX Byte 1 ==
3575 12:27:00.087386 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3576 12:27:00.090553 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3577 12:27:00.090630 ==
3578 12:27:00.094161 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 12:27:00.100440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 12:27:00.100558 ==
3581 12:27:00.110997 TX Vref=22, minBit 11, minWin=25, winSum=424
3582 12:27:00.114039 TX Vref=24, minBit 8, minWin=26, winSum=429
3583 12:27:00.117141 TX Vref=26, minBit 8, minWin=26, winSum=432
3584 12:27:00.120961 TX Vref=28, minBit 9, minWin=26, winSum=434
3585 12:27:00.124186 TX Vref=30, minBit 7, minWin=26, winSum=433
3586 12:27:00.130829 TX Vref=32, minBit 8, minWin=26, winSum=432
3587 12:27:00.134053 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3588 12:27:00.134138
3589 12:27:00.137167 Final TX Range 1 Vref 28
3590 12:27:00.137258
3591 12:27:00.137324 ==
3592 12:27:00.140656 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 12:27:00.146813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 12:27:00.146900 ==
3595 12:27:00.146967
3596 12:27:00.147031
3597 12:27:00.147091 TX Vref Scan disable
3598 12:27:00.150566 == TX Byte 0 ==
3599 12:27:00.153814 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3600 12:27:00.160292 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3601 12:27:00.160380 == TX Byte 1 ==
3602 12:27:00.164164 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3603 12:27:00.170620 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3604 12:27:00.170741
3605 12:27:00.170840 [DATLAT]
3606 12:27:00.170936 Freq=1200, CH1 RK1
3607 12:27:00.171027
3608 12:27:00.173916 DATLAT Default: 0xd
3609 12:27:00.177041 0, 0xFFFF, sum = 0
3610 12:27:00.177128 1, 0xFFFF, sum = 0
3611 12:27:00.180094 2, 0xFFFF, sum = 0
3612 12:27:00.180180 3, 0xFFFF, sum = 0
3613 12:27:00.183764 4, 0xFFFF, sum = 0
3614 12:27:00.183850 5, 0xFFFF, sum = 0
3615 12:27:00.186844 6, 0xFFFF, sum = 0
3616 12:27:00.186928 7, 0xFFFF, sum = 0
3617 12:27:00.190578 8, 0xFFFF, sum = 0
3618 12:27:00.190665 9, 0xFFFF, sum = 0
3619 12:27:00.193690 10, 0xFFFF, sum = 0
3620 12:27:00.193804 11, 0xFFFF, sum = 0
3621 12:27:00.196786 12, 0x0, sum = 1
3622 12:27:00.196872 13, 0x0, sum = 2
3623 12:27:00.199869 14, 0x0, sum = 3
3624 12:27:00.199955 15, 0x0, sum = 4
3625 12:27:00.203630 best_step = 13
3626 12:27:00.203759
3627 12:27:00.203865 ==
3628 12:27:00.206736 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 12:27:00.209752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 12:27:00.209866 ==
3631 12:27:00.212981 RX Vref Scan: 0
3632 12:27:00.213066
3633 12:27:00.213134 RX Vref 0 -> 0, step: 1
3634 12:27:00.213201
3635 12:27:00.216624 RX Delay -21 -> 252, step: 4
3636 12:27:00.222839 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3637 12:27:00.226624 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3638 12:27:00.229647 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3639 12:27:00.233380 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3640 12:27:00.236341 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3641 12:27:00.243080 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3642 12:27:00.246127 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3643 12:27:00.249730 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3644 12:27:00.252986 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3645 12:27:00.256064 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3646 12:27:00.262546 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3647 12:27:00.265847 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3648 12:27:00.269623 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3649 12:27:00.272794 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3650 12:27:00.279182 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3651 12:27:00.282335 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3652 12:27:00.282440 ==
3653 12:27:00.285584 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 12:27:00.288783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 12:27:00.288886 ==
3656 12:27:00.292462 DQS Delay:
3657 12:27:00.292563 DQS0 = 0, DQS1 = 0
3658 12:27:00.292639 DQM Delay:
3659 12:27:00.295513 DQM0 = 117, DQM1 = 111
3660 12:27:00.295617 DQ Delay:
3661 12:27:00.298691 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3662 12:27:00.302288 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3663 12:27:00.305403 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3664 12:27:00.312236 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =120
3665 12:27:00.312344
3666 12:27:00.312442
3667 12:27:00.318841 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3668 12:27:00.321849 CH1 RK1: MR19=303, MR18=F3EF
3669 12:27:00.328275 CH1_RK1: MR19=0x303, MR18=0xF3EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3670 12:27:00.331982 [RxdqsGatingPostProcess] freq 1200
3671 12:27:00.335071 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3672 12:27:00.338585 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 12:27:00.341596 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 12:27:00.344821 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 12:27:00.348407 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 12:27:00.351535 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 12:27:00.354627 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 12:27:00.358515 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 12:27:00.361678 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 12:27:00.364837 Pre-setting of DQS Precalculation
3681 12:27:00.368529 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3682 12:27:00.378281 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3683 12:27:00.384670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3684 12:27:00.384766
3685 12:27:00.384861
3686 12:27:00.387935 [Calibration Summary] 2400 Mbps
3687 12:27:00.388035 CH 0, Rank 0
3688 12:27:00.391643 SW Impedance : PASS
3689 12:27:00.394772 DUTY Scan : NO K
3690 12:27:00.394877 ZQ Calibration : PASS
3691 12:27:00.397784 Jitter Meter : NO K
3692 12:27:00.397885 CBT Training : PASS
3693 12:27:00.401489 Write leveling : PASS
3694 12:27:00.404588 RX DQS gating : PASS
3695 12:27:00.404706 RX DQ/DQS(RDDQC) : PASS
3696 12:27:00.407675 TX DQ/DQS : PASS
3697 12:27:00.411504 RX DATLAT : PASS
3698 12:27:00.411614 RX DQ/DQS(Engine): PASS
3699 12:27:00.414701 TX OE : NO K
3700 12:27:00.414786 All Pass.
3701 12:27:00.414852
3702 12:27:00.417771 CH 0, Rank 1
3703 12:27:00.417856 SW Impedance : PASS
3704 12:27:00.421368 DUTY Scan : NO K
3705 12:27:00.424406 ZQ Calibration : PASS
3706 12:27:00.424524 Jitter Meter : NO K
3707 12:27:00.427573 CBT Training : PASS
3708 12:27:00.431333 Write leveling : PASS
3709 12:27:00.431413 RX DQS gating : PASS
3710 12:27:00.433974 RX DQ/DQS(RDDQC) : PASS
3711 12:27:00.437720 TX DQ/DQS : PASS
3712 12:27:00.437805 RX DATLAT : PASS
3713 12:27:00.440645 RX DQ/DQS(Engine): PASS
3714 12:27:00.444341 TX OE : NO K
3715 12:27:00.444423 All Pass.
3716 12:27:00.444490
3717 12:27:00.444563 CH 1, Rank 0
3718 12:27:00.447511 SW Impedance : PASS
3719 12:27:00.450614 DUTY Scan : NO K
3720 12:27:00.450718 ZQ Calibration : PASS
3721 12:27:00.454266 Jitter Meter : NO K
3722 12:27:00.457462 CBT Training : PASS
3723 12:27:00.457549 Write leveling : PASS
3724 12:27:00.460485 RX DQS gating : PASS
3725 12:27:00.464315 RX DQ/DQS(RDDQC) : PASS
3726 12:27:00.464429 TX DQ/DQS : PASS
3727 12:27:00.467393 RX DATLAT : PASS
3728 12:27:00.470662 RX DQ/DQS(Engine): PASS
3729 12:27:00.470746 TX OE : NO K
3730 12:27:00.470819 All Pass.
3731 12:27:00.470881
3732 12:27:00.473857 CH 1, Rank 1
3733 12:27:00.473969 SW Impedance : PASS
3734 12:27:00.477136 DUTY Scan : NO K
3735 12:27:00.480232 ZQ Calibration : PASS
3736 12:27:00.480354 Jitter Meter : NO K
3737 12:27:00.483489 CBT Training : PASS
3738 12:27:00.487213 Write leveling : PASS
3739 12:27:00.487330 RX DQS gating : PASS
3740 12:27:00.490473 RX DQ/DQS(RDDQC) : PASS
3741 12:27:00.493529 TX DQ/DQS : PASS
3742 12:27:00.493611 RX DATLAT : PASS
3743 12:27:00.496650 RX DQ/DQS(Engine): PASS
3744 12:27:00.500405 TX OE : NO K
3745 12:27:00.500522 All Pass.
3746 12:27:00.500611
3747 12:27:00.503484 DramC Write-DBI off
3748 12:27:00.503590 PER_BANK_REFRESH: Hybrid Mode
3749 12:27:00.506707 TX_TRACKING: ON
3750 12:27:00.513608 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3751 12:27:00.520029 [FAST_K] Save calibration result to emmc
3752 12:27:00.523022 dramc_set_vcore_voltage set vcore to 650000
3753 12:27:00.523121 Read voltage for 600, 5
3754 12:27:00.526545 Vio18 = 0
3755 12:27:00.526622 Vcore = 650000
3756 12:27:00.526686 Vdram = 0
3757 12:27:00.529759 Vddq = 0
3758 12:27:00.529842 Vmddr = 0
3759 12:27:00.536523 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3760 12:27:00.539689 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3761 12:27:00.542826 MEM_TYPE=3, freq_sel=19
3762 12:27:00.546407 sv_algorithm_assistance_LP4_1600
3763 12:27:00.549407 ============ PULL DRAM RESETB DOWN ============
3764 12:27:00.553166 ========== PULL DRAM RESETB DOWN end =========
3765 12:27:00.559339 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3766 12:27:00.563062 ===================================
3767 12:27:00.563148 LPDDR4 DRAM CONFIGURATION
3768 12:27:00.566209 ===================================
3769 12:27:00.569392 EX_ROW_EN[0] = 0x0
3770 12:27:00.572556 EX_ROW_EN[1] = 0x0
3771 12:27:00.572641 LP4Y_EN = 0x0
3772 12:27:00.575840 WORK_FSP = 0x0
3773 12:27:00.575928 WL = 0x2
3774 12:27:00.578920 RL = 0x2
3775 12:27:00.579029 BL = 0x2
3776 12:27:00.582780 RPST = 0x0
3777 12:27:00.582853 RD_PRE = 0x0
3778 12:27:00.585922 WR_PRE = 0x1
3779 12:27:00.586002 WR_PST = 0x0
3780 12:27:00.589085 DBI_WR = 0x0
3781 12:27:00.589164 DBI_RD = 0x0
3782 12:27:00.592279 OTF = 0x1
3783 12:27:00.596032 ===================================
3784 12:27:00.599105 ===================================
3785 12:27:00.599210 ANA top config
3786 12:27:00.602385 ===================================
3787 12:27:00.605431 DLL_ASYNC_EN = 0
3788 12:27:00.608524 ALL_SLAVE_EN = 1
3789 12:27:00.612369 NEW_RANK_MODE = 1
3790 12:27:00.612481 DLL_IDLE_MODE = 1
3791 12:27:00.615405 LP45_APHY_COMB_EN = 1
3792 12:27:00.618629 TX_ODT_DIS = 1
3793 12:27:00.621768 NEW_8X_MODE = 1
3794 12:27:00.625575 ===================================
3795 12:27:00.628638 ===================================
3796 12:27:00.632344 data_rate = 1200
3797 12:27:00.632447 CKR = 1
3798 12:27:00.635424 DQ_P2S_RATIO = 8
3799 12:27:00.638533 ===================================
3800 12:27:00.641671 CA_P2S_RATIO = 8
3801 12:27:00.645371 DQ_CA_OPEN = 0
3802 12:27:00.648369 DQ_SEMI_OPEN = 0
3803 12:27:00.651957 CA_SEMI_OPEN = 0
3804 12:27:00.652033 CA_FULL_RATE = 0
3805 12:27:00.654956 DQ_CKDIV4_EN = 1
3806 12:27:00.658089 CA_CKDIV4_EN = 1
3807 12:27:00.661804 CA_PREDIV_EN = 0
3808 12:27:00.664851 PH8_DLY = 0
3809 12:27:00.667991 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3810 12:27:00.671852 DQ_AAMCK_DIV = 4
3811 12:27:00.671946 CA_AAMCK_DIV = 4
3812 12:27:00.674895 CA_ADMCK_DIV = 4
3813 12:27:00.678127 DQ_TRACK_CA_EN = 0
3814 12:27:00.681321 CA_PICK = 600
3815 12:27:00.684488 CA_MCKIO = 600
3816 12:27:00.688202 MCKIO_SEMI = 0
3817 12:27:00.691432 PLL_FREQ = 2288
3818 12:27:00.691511 DQ_UI_PI_RATIO = 32
3819 12:27:00.694689 CA_UI_PI_RATIO = 0
3820 12:27:00.697737 ===================================
3821 12:27:00.701466 ===================================
3822 12:27:00.704562 memory_type:LPDDR4
3823 12:27:00.707626 GP_NUM : 10
3824 12:27:00.707701 SRAM_EN : 1
3825 12:27:00.711236 MD32_EN : 0
3826 12:27:00.714522 ===================================
3827 12:27:00.717650 [ANA_INIT] >>>>>>>>>>>>>>
3828 12:27:00.717736 <<<<<< [CONFIGURE PHASE]: ANA_TX
3829 12:27:00.721331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3830 12:27:00.724385 ===================================
3831 12:27:00.727539 data_rate = 1200,PCW = 0X5800
3832 12:27:00.730665 ===================================
3833 12:27:00.734425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3834 12:27:00.740912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 12:27:00.747362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 12:27:00.751096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3837 12:27:00.754089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3838 12:27:00.757747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3839 12:27:00.760856 [ANA_INIT] flow start
3840 12:27:00.760941 [ANA_INIT] PLL >>>>>>>>
3841 12:27:00.763999 [ANA_INIT] PLL <<<<<<<<
3842 12:27:00.767727 [ANA_INIT] MIDPI >>>>>>>>
3843 12:27:00.767806 [ANA_INIT] MIDPI <<<<<<<<
3844 12:27:00.770783 [ANA_INIT] DLL >>>>>>>>
3845 12:27:00.773841 [ANA_INIT] flow end
3846 12:27:00.777025 ============ LP4 DIFF to SE enter ============
3847 12:27:00.780813 ============ LP4 DIFF to SE exit ============
3848 12:27:00.784000 [ANA_INIT] <<<<<<<<<<<<<
3849 12:27:00.787154 [Flow] Enable top DCM control >>>>>
3850 12:27:00.790317 [Flow] Enable top DCM control <<<<<
3851 12:27:00.793518 Enable DLL master slave shuffle
3852 12:27:00.800562 ==============================================================
3853 12:27:00.800648 Gating Mode config
3854 12:27:00.806667 ==============================================================
3855 12:27:00.806751 Config description:
3856 12:27:00.816730 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3857 12:27:00.823569 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3858 12:27:00.829979 SELPH_MODE 0: By rank 1: By Phase
3859 12:27:00.833623 ==============================================================
3860 12:27:00.836849 GAT_TRACK_EN = 1
3861 12:27:00.839861 RX_GATING_MODE = 2
3862 12:27:00.842944 RX_GATING_TRACK_MODE = 2
3863 12:27:00.846505 SELPH_MODE = 1
3864 12:27:00.849796 PICG_EARLY_EN = 1
3865 12:27:00.852918 VALID_LAT_VALUE = 1
3866 12:27:00.859612 ==============================================================
3867 12:27:00.863304 Enter into Gating configuration >>>>
3868 12:27:00.866506 Exit from Gating configuration <<<<
3869 12:27:00.866591 Enter into DVFS_PRE_config >>>>>
3870 12:27:00.879485 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3871 12:27:00.883334 Exit from DVFS_PRE_config <<<<<
3872 12:27:00.886501 Enter into PICG configuration >>>>
3873 12:27:00.889673 Exit from PICG configuration <<<<
3874 12:27:00.889749 [RX_INPUT] configuration >>>>>
3875 12:27:00.892780 [RX_INPUT] configuration <<<<<
3876 12:27:00.899821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3877 12:27:00.906191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3878 12:27:00.909327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 12:27:00.916230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 12:27:00.922504 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 12:27:00.929512 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 12:27:00.932561 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3883 12:27:00.935736 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3884 12:27:00.942087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3885 12:27:00.945762 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3886 12:27:00.948770 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3887 12:27:00.955175 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 12:27:00.958837 ===================================
3889 12:27:00.958918 LPDDR4 DRAM CONFIGURATION
3890 12:27:00.961907 ===================================
3891 12:27:00.965524 EX_ROW_EN[0] = 0x0
3892 12:27:00.968716 EX_ROW_EN[1] = 0x0
3893 12:27:00.968796 LP4Y_EN = 0x0
3894 12:27:00.972001 WORK_FSP = 0x0
3895 12:27:00.972075 WL = 0x2
3896 12:27:00.975411 RL = 0x2
3897 12:27:00.975488 BL = 0x2
3898 12:27:00.978545 RPST = 0x0
3899 12:27:00.978646 RD_PRE = 0x0
3900 12:27:00.981708 WR_PRE = 0x1
3901 12:27:00.981792 WR_PST = 0x0
3902 12:27:00.985533 DBI_WR = 0x0
3903 12:27:00.985616 DBI_RD = 0x0
3904 12:27:00.988829 OTF = 0x1
3905 12:27:00.991992 ===================================
3906 12:27:00.995183 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3907 12:27:00.998365 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3908 12:27:01.005318 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 12:27:01.008439 ===================================
3910 12:27:01.008555 LPDDR4 DRAM CONFIGURATION
3911 12:27:01.011543 ===================================
3912 12:27:01.014874 EX_ROW_EN[0] = 0x10
3913 12:27:01.018007 EX_ROW_EN[1] = 0x0
3914 12:27:01.018091 LP4Y_EN = 0x0
3915 12:27:01.021712 WORK_FSP = 0x0
3916 12:27:01.021796 WL = 0x2
3917 12:27:01.024753 RL = 0x2
3918 12:27:01.024868 BL = 0x2
3919 12:27:01.027910 RPST = 0x0
3920 12:27:01.028013 RD_PRE = 0x0
3921 12:27:01.031625 WR_PRE = 0x1
3922 12:27:01.031703 WR_PST = 0x0
3923 12:27:01.034862 DBI_WR = 0x0
3924 12:27:01.034972 DBI_RD = 0x0
3925 12:27:01.037878 OTF = 0x1
3926 12:27:01.041562 ===================================
3927 12:27:01.048012 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3928 12:27:01.051064 nWR fixed to 30
3929 12:27:01.051178 [ModeRegInit_LP4] CH0 RK0
3930 12:27:01.054136 [ModeRegInit_LP4] CH0 RK1
3931 12:27:01.057974 [ModeRegInit_LP4] CH1 RK0
3932 12:27:01.061276 [ModeRegInit_LP4] CH1 RK1
3933 12:27:01.061388 match AC timing 17
3934 12:27:01.067333 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3935 12:27:01.071093 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3936 12:27:01.074125 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3937 12:27:01.080891 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3938 12:27:01.083967 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3939 12:27:01.084077 ==
3940 12:27:01.087154 Dram Type= 6, Freq= 0, CH_0, rank 0
3941 12:27:01.090432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 12:27:01.090543 ==
3943 12:27:01.097475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 12:27:01.103787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3945 12:27:01.106992 [CA 0] Center 36 (6~66) winsize 61
3946 12:27:01.110251 [CA 1] Center 36 (6~66) winsize 61
3947 12:27:01.114018 [CA 2] Center 34 (4~65) winsize 62
3948 12:27:01.117122 [CA 3] Center 34 (4~65) winsize 62
3949 12:27:01.120272 [CA 4] Center 33 (3~64) winsize 62
3950 12:27:01.123380 [CA 5] Center 33 (3~64) winsize 62
3951 12:27:01.123490
3952 12:27:01.127235 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3953 12:27:01.127344
3954 12:27:01.130137 [CATrainingPosCal] consider 1 rank data
3955 12:27:01.133255 u2DelayCellTimex100 = 270/100 ps
3956 12:27:01.136956 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 12:27:01.139914 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 12:27:01.143172 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 12:27:01.146316 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 12:27:01.150063 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 12:27:01.156771 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 12:27:01.156895
3963 12:27:01.159948 CA PerBit enable=1, Macro0, CA PI delay=33
3964 12:27:01.160052
3965 12:27:01.163163 [CBTSetCACLKResult] CA Dly = 33
3966 12:27:01.163263 CS Dly: 5 (0~36)
3967 12:27:01.163356 ==
3968 12:27:01.166389 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 12:27:01.173123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 12:27:01.173234 ==
3971 12:27:01.176292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 12:27:01.182630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3973 12:27:01.186255 [CA 0] Center 36 (6~66) winsize 61
3974 12:27:01.189262 [CA 1] Center 36 (6~66) winsize 61
3975 12:27:01.192402 [CA 2] Center 34 (4~65) winsize 62
3976 12:27:01.196230 [CA 3] Center 34 (4~65) winsize 62
3977 12:27:01.199466 [CA 4] Center 33 (3~64) winsize 62
3978 12:27:01.202560 [CA 5] Center 33 (3~64) winsize 62
3979 12:27:01.202640
3980 12:27:01.205746 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3981 12:27:01.205848
3982 12:27:01.208909 [CATrainingPosCal] consider 2 rank data
3983 12:27:01.212793 u2DelayCellTimex100 = 270/100 ps
3984 12:27:01.215889 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 12:27:01.222153 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 12:27:01.225953 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3987 12:27:01.229119 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 12:27:01.232185 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 12:27:01.235299 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 12:27:01.235413
3991 12:27:01.238937 CA PerBit enable=1, Macro0, CA PI delay=33
3992 12:27:01.239017
3993 12:27:01.242156 [CBTSetCACLKResult] CA Dly = 33
3994 12:27:01.245392 CS Dly: 5 (0~37)
3995 12:27:01.245502
3996 12:27:01.248395 ----->DramcWriteLeveling(PI) begin...
3997 12:27:01.248500 ==
3998 12:27:01.252273 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 12:27:01.255206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 12:27:01.255316 ==
4001 12:27:01.258279 Write leveling (Byte 0): 33 => 33
4002 12:27:01.261970 Write leveling (Byte 1): 30 => 30
4003 12:27:01.265098 DramcWriteLeveling(PI) end<-----
4004 12:27:01.265210
4005 12:27:01.265308 ==
4006 12:27:01.268111 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 12:27:01.271936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 12:27:01.272050 ==
4009 12:27:01.274916 [Gating] SW mode calibration
4010 12:27:01.281659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4011 12:27:01.288384 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4012 12:27:01.291433 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 12:27:01.294757 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 12:27:01.301153 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 12:27:01.304913 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4016 12:27:01.308027 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
4017 12:27:01.314385 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 12:27:01.318259 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 12:27:01.321498 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 12:27:01.327862 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 12:27:01.331109 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 12:27:01.334794 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 12:27:01.340934 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4024 12:27:01.344487 0 10 16 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
4025 12:27:01.347663 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 12:27:01.354013 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 12:27:01.357820 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 12:27:01.360768 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 12:27:01.367450 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 12:27:01.370699 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 12:27:01.373755 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4032 12:27:01.380488 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4033 12:27:01.383956 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:27:01.387135 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:27:01.393814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:27:01.396979 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:27:01.400037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:27:01.406980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:27:01.410138 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:27:01.413311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:27:01.420287 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 12:27:01.423467 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 12:27:01.426592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 12:27:01.432922 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:27:01.436770 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:27:01.439872 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:27:01.446660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4048 12:27:01.449860 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 12:27:01.452944 Total UI for P1: 0, mck2ui 16
4050 12:27:01.456742 best dqsien dly found for B0: ( 0, 13, 12)
4051 12:27:01.459862 Total UI for P1: 0, mck2ui 16
4052 12:27:01.463010 best dqsien dly found for B1: ( 0, 13, 14)
4053 12:27:01.466511 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4054 12:27:01.469490 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4055 12:27:01.469601
4056 12:27:01.472790 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4057 12:27:01.476056 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4058 12:27:01.479312 [Gating] SW calibration Done
4059 12:27:01.479411 ==
4060 12:27:01.482907 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 12:27:01.489582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 12:27:01.489686 ==
4063 12:27:01.489763 RX Vref Scan: 0
4064 12:27:01.489827
4065 12:27:01.492750 RX Vref 0 -> 0, step: 1
4066 12:27:01.492865
4067 12:27:01.495834 RX Delay -230 -> 252, step: 16
4068 12:27:01.499434 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4069 12:27:01.502634 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4070 12:27:01.505999 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4071 12:27:01.512892 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4072 12:27:01.516132 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4073 12:27:01.519333 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4074 12:27:01.522629 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4075 12:27:01.528985 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4076 12:27:01.532237 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4077 12:27:01.535983 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4078 12:27:01.539199 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4079 12:27:01.545925 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4080 12:27:01.549123 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4081 12:27:01.552100 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4082 12:27:01.555878 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4083 12:27:01.562054 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4084 12:27:01.562145 ==
4085 12:27:01.565279 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 12:27:01.568880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 12:27:01.568971 ==
4088 12:27:01.569039 DQS Delay:
4089 12:27:01.572017 DQS0 = 0, DQS1 = 0
4090 12:27:01.572101 DQM Delay:
4091 12:27:01.575249 DQM0 = 44, DQM1 = 30
4092 12:27:01.575362 DQ Delay:
4093 12:27:01.578939 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4094 12:27:01.582075 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4095 12:27:01.585112 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4096 12:27:01.588655 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4097 12:27:01.588751
4098 12:27:01.588827
4099 12:27:01.588890 ==
4100 12:27:01.591837 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 12:27:01.594978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 12:27:01.595088 ==
4103 12:27:01.598133
4104 12:27:01.598209
4105 12:27:01.598283 TX Vref Scan disable
4106 12:27:01.601770 == TX Byte 0 ==
4107 12:27:01.604825 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4108 12:27:01.607977 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4109 12:27:01.611232 == TX Byte 1 ==
4110 12:27:01.615104 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4111 12:27:01.618382 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4112 12:27:01.621620 ==
4113 12:27:01.621725 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 12:27:01.628052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 12:27:01.628202 ==
4116 12:27:01.628269
4117 12:27:01.628330
4118 12:27:01.631284 TX Vref Scan disable
4119 12:27:01.631385 == TX Byte 0 ==
4120 12:27:01.638160 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4121 12:27:01.641389 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4122 12:27:01.641481 == TX Byte 1 ==
4123 12:27:01.647821 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4124 12:27:01.650996 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4125 12:27:01.651121
4126 12:27:01.651184 [DATLAT]
4127 12:27:01.654743 Freq=600, CH0 RK0
4128 12:27:01.654831
4129 12:27:01.654896 DATLAT Default: 0x9
4130 12:27:01.658040 0, 0xFFFF, sum = 0
4131 12:27:01.661232 1, 0xFFFF, sum = 0
4132 12:27:01.661318 2, 0xFFFF, sum = 0
4133 12:27:01.664306 3, 0xFFFF, sum = 0
4134 12:27:01.664412 4, 0xFFFF, sum = 0
4135 12:27:01.667500 5, 0xFFFF, sum = 0
4136 12:27:01.667646 6, 0xFFFF, sum = 0
4137 12:27:01.670852 7, 0xFFFF, sum = 0
4138 12:27:01.670933 8, 0x0, sum = 1
4139 12:27:01.674423 9, 0x0, sum = 2
4140 12:27:01.674526 10, 0x0, sum = 3
4141 12:27:01.674635 11, 0x0, sum = 4
4142 12:27:01.677642 best_step = 9
4143 12:27:01.677751
4144 12:27:01.677845 ==
4145 12:27:01.680623 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 12:27:01.684328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 12:27:01.684470 ==
4148 12:27:01.687482 RX Vref Scan: 1
4149 12:27:01.687564
4150 12:27:01.687628 RX Vref 0 -> 0, step: 1
4151 12:27:01.690509
4152 12:27:01.690590 RX Delay -195 -> 252, step: 8
4153 12:27:01.690685
4154 12:27:01.694106 Set Vref, RX VrefLevel [Byte0]: 61
4155 12:27:01.697267 [Byte1]: 50
4156 12:27:01.701697
4157 12:27:01.701780 Final RX Vref Byte 0 = 61 to rank0
4158 12:27:01.705183 Final RX Vref Byte 1 = 50 to rank0
4159 12:27:01.708223 Final RX Vref Byte 0 = 61 to rank1
4160 12:27:01.711961 Final RX Vref Byte 1 = 50 to rank1==
4161 12:27:01.715059 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 12:27:01.721415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 12:27:01.721525 ==
4164 12:27:01.721633 DQS Delay:
4165 12:27:01.725177 DQS0 = 0, DQS1 = 0
4166 12:27:01.725277 DQM Delay:
4167 12:27:01.725367 DQM0 = 42, DQM1 = 32
4168 12:27:01.728355 DQ Delay:
4169 12:27:01.731546 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4170 12:27:01.734819 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4171 12:27:01.738050 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4172 12:27:01.741134 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4173 12:27:01.741218
4174 12:27:01.741284
4175 12:27:01.748063 [DQSOSCAuto] RK0, (LSB)MR18= 0x6840, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4176 12:27:01.751209 CH0 RK0: MR19=808, MR18=6840
4177 12:27:01.757570 CH0_RK0: MR19=0x808, MR18=0x6840, DQSOSC=390, MR23=63, INC=172, DEC=114
4178 12:27:01.757657
4179 12:27:01.760653 ----->DramcWriteLeveling(PI) begin...
4180 12:27:01.760740 ==
4181 12:27:01.763913 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 12:27:01.767677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 12:27:01.767762 ==
4184 12:27:01.770821 Write leveling (Byte 0): 33 => 33
4185 12:27:01.773982 Write leveling (Byte 1): 30 => 30
4186 12:27:01.777576 DramcWriteLeveling(PI) end<-----
4187 12:27:01.777692
4188 12:27:01.777798 ==
4189 12:27:01.780624 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 12:27:01.784288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 12:27:01.787468 ==
4192 12:27:01.787551 [Gating] SW mode calibration
4193 12:27:01.797367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4194 12:27:01.800482 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4195 12:27:01.804273 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 12:27:01.810492 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 12:27:01.814211 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 12:27:01.817395 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4199 12:27:01.823842 0 9 16 | B1->B0 | 3030 2b2b | 0 0 | (1 1) (0 0)
4200 12:27:01.826942 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 12:27:01.830157 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 12:27:01.836990 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 12:27:01.840249 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 12:27:01.843551 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 12:27:01.850346 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 12:27:01.853458 0 10 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4207 12:27:01.857335 0 10 16 | B1->B0 | 3737 3f3f | 0 0 | (0 0) (1 1)
4208 12:27:01.863578 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 12:27:01.866811 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 12:27:01.870561 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 12:27:01.876644 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 12:27:01.880398 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 12:27:01.883501 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 12:27:01.890114 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4215 12:27:01.893354 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:27:01.896464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:27:01.903184 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:27:01.906291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:27:01.909533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:27:01.916585 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:27:01.919681 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 12:27:01.922913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:27:01.929318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 12:27:01.932396 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:27:01.936295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 12:27:01.942714 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 12:27:01.945842 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:27:01.948968 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 12:27:01.955531 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4230 12:27:01.958727 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4231 12:27:01.962505 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 12:27:01.965463 Total UI for P1: 0, mck2ui 16
4233 12:27:01.969312 best dqsien dly found for B0: ( 0, 13, 10)
4234 12:27:01.972459 Total UI for P1: 0, mck2ui 16
4235 12:27:01.975532 best dqsien dly found for B1: ( 0, 13, 14)
4236 12:27:01.978625 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4237 12:27:01.982388 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4238 12:27:01.982493
4239 12:27:01.989001 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4240 12:27:01.992109 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4241 12:27:01.995232 [Gating] SW calibration Done
4242 12:27:01.995311 ==
4243 12:27:01.998481 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 12:27:02.001622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 12:27:02.001702 ==
4246 12:27:02.001779 RX Vref Scan: 0
4247 12:27:02.005278
4248 12:27:02.005366 RX Vref 0 -> 0, step: 1
4249 12:27:02.005432
4250 12:27:02.008280 RX Delay -230 -> 252, step: 16
4251 12:27:02.011958 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4252 12:27:02.018765 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4253 12:27:02.021772 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4254 12:27:02.024905 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4255 12:27:02.028125 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4256 12:27:02.032010 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4257 12:27:02.038449 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4258 12:27:02.041452 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4259 12:27:02.045134 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4260 12:27:02.048381 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4261 12:27:02.054756 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4262 12:27:02.057923 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4263 12:27:02.061641 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4264 12:27:02.064756 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4265 12:27:02.071492 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4266 12:27:02.074761 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4267 12:27:02.074853 ==
4268 12:27:02.077837 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 12:27:02.080910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 12:27:02.081001 ==
4271 12:27:02.084683 DQS Delay:
4272 12:27:02.084770 DQS0 = 0, DQS1 = 0
4273 12:27:02.084836 DQM Delay:
4274 12:27:02.087882 DQM0 = 44, DQM1 = 36
4275 12:27:02.087986 DQ Delay:
4276 12:27:02.090930 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4277 12:27:02.094550 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4278 12:27:02.097558 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4279 12:27:02.101278 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4280 12:27:02.101362
4281 12:27:02.101427
4282 12:27:02.101487 ==
4283 12:27:02.104394 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 12:27:02.110634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 12:27:02.110723 ==
4286 12:27:02.110790
4287 12:27:02.110869
4288 12:27:02.110930 TX Vref Scan disable
4289 12:27:02.114944 == TX Byte 0 ==
4290 12:27:02.118085 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4291 12:27:02.124760 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4292 12:27:02.124893 == TX Byte 1 ==
4293 12:27:02.127790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4294 12:27:02.134858 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4295 12:27:02.134974 ==
4296 12:27:02.138058 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 12:27:02.141337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 12:27:02.141456 ==
4299 12:27:02.141553
4300 12:27:02.141662
4301 12:27:02.144497 TX Vref Scan disable
4302 12:27:02.147751 == TX Byte 0 ==
4303 12:27:02.150935 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4304 12:27:02.154235 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4305 12:27:02.157449 == TX Byte 1 ==
4306 12:27:02.160763 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4307 12:27:02.164483 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4308 12:27:02.164581
4309 12:27:02.167657 [DATLAT]
4310 12:27:02.167738 Freq=600, CH0 RK1
4311 12:27:02.167802
4312 12:27:02.170927 DATLAT Default: 0x9
4313 12:27:02.171009 0, 0xFFFF, sum = 0
4314 12:27:02.174007 1, 0xFFFF, sum = 0
4315 12:27:02.174089 2, 0xFFFF, sum = 0
4316 12:27:02.177105 3, 0xFFFF, sum = 0
4317 12:27:02.177188 4, 0xFFFF, sum = 0
4318 12:27:02.180871 5, 0xFFFF, sum = 0
4319 12:27:02.180955 6, 0xFFFF, sum = 0
4320 12:27:02.183960 7, 0xFFFF, sum = 0
4321 12:27:02.184080 8, 0x0, sum = 1
4322 12:27:02.187624 9, 0x0, sum = 2
4323 12:27:02.187748 10, 0x0, sum = 3
4324 12:27:02.190832 11, 0x0, sum = 4
4325 12:27:02.190941 best_step = 9
4326 12:27:02.191031
4327 12:27:02.191127 ==
4328 12:27:02.193979 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 12:27:02.196972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 12:27:02.197093 ==
4331 12:27:02.200672 RX Vref Scan: 0
4332 12:27:02.200778
4333 12:27:02.203731 RX Vref 0 -> 0, step: 1
4334 12:27:02.203818
4335 12:27:02.203882 RX Delay -195 -> 252, step: 8
4336 12:27:02.212003 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4337 12:27:02.215552 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4338 12:27:02.218473 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4339 12:27:02.221723 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4340 12:27:02.228460 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4341 12:27:02.231538 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4342 12:27:02.235266 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4343 12:27:02.238481 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4344 12:27:02.244771 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4345 12:27:02.248445 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4346 12:27:02.251607 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4347 12:27:02.254898 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4348 12:27:02.258164 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4349 12:27:02.264551 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4350 12:27:02.268274 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4351 12:27:02.271298 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4352 12:27:02.271375 ==
4353 12:27:02.274538 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 12:27:02.281416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 12:27:02.281504 ==
4356 12:27:02.281571 DQS Delay:
4357 12:27:02.284557 DQS0 = 0, DQS1 = 0
4358 12:27:02.284630 DQM Delay:
4359 12:27:02.284691 DQM0 = 40, DQM1 = 33
4360 12:27:02.288344 DQ Delay:
4361 12:27:02.291496 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4362 12:27:02.294647 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4363 12:27:02.297833 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4364 12:27:02.301422 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4365 12:27:02.301518
4366 12:27:02.301615
4367 12:27:02.307519 [DQSOSCAuto] RK1, (LSB)MR18= 0x6113, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4368 12:27:02.310757 CH0 RK1: MR19=808, MR18=6113
4369 12:27:02.317629 CH0_RK1: MR19=0x808, MR18=0x6113, DQSOSC=391, MR23=63, INC=171, DEC=114
4370 12:27:02.320622 [RxdqsGatingPostProcess] freq 600
4371 12:27:02.324337 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4372 12:27:02.327427 Pre-setting of DQS Precalculation
4373 12:27:02.333976 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4374 12:27:02.334088 ==
4375 12:27:02.337147 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 12:27:02.340433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 12:27:02.340550 ==
4378 12:27:02.346876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4379 12:27:02.353819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4380 12:27:02.356918 [CA 0] Center 35 (5~66) winsize 62
4381 12:27:02.360153 [CA 1] Center 36 (6~66) winsize 61
4382 12:27:02.363906 [CA 2] Center 34 (4~65) winsize 62
4383 12:27:02.367074 [CA 3] Center 33 (3~64) winsize 62
4384 12:27:02.370309 [CA 4] Center 34 (4~65) winsize 62
4385 12:27:02.373356 [CA 5] Center 33 (3~64) winsize 62
4386 12:27:02.373434
4387 12:27:02.377083 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4388 12:27:02.377166
4389 12:27:02.380274 [CATrainingPosCal] consider 1 rank data
4390 12:27:02.384030 u2DelayCellTimex100 = 270/100 ps
4391 12:27:02.387219 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 12:27:02.390313 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4393 12:27:02.393390 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 12:27:02.397255 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 12:27:02.400335 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 12:27:02.403479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 12:27:02.403562
4398 12:27:02.410335 CA PerBit enable=1, Macro0, CA PI delay=33
4399 12:27:02.410445
4400 12:27:02.413322 [CBTSetCACLKResult] CA Dly = 33
4401 12:27:02.413400 CS Dly: 4 (0~35)
4402 12:27:02.413464 ==
4403 12:27:02.416544 Dram Type= 6, Freq= 0, CH_1, rank 1
4404 12:27:02.420325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 12:27:02.420432 ==
4406 12:27:02.426949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 12:27:02.433232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4408 12:27:02.436446 [CA 0] Center 35 (5~66) winsize 62
4409 12:27:02.440113 [CA 1] Center 36 (6~66) winsize 61
4410 12:27:02.443295 [CA 2] Center 34 (4~65) winsize 62
4411 12:27:02.446432 [CA 3] Center 34 (4~65) winsize 62
4412 12:27:02.449662 [CA 4] Center 34 (4~65) winsize 62
4413 12:27:02.452916 [CA 5] Center 34 (3~65) winsize 63
4414 12:27:02.453009
4415 12:27:02.456887 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4416 12:27:02.456986
4417 12:27:02.460085 [CATrainingPosCal] consider 2 rank data
4418 12:27:02.463335 u2DelayCellTimex100 = 270/100 ps
4419 12:27:02.466493 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4420 12:27:02.469567 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4421 12:27:02.472772 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 12:27:02.475952 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4423 12:27:02.482952 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 12:27:02.486143 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 12:27:02.486235
4426 12:27:02.489240 CA PerBit enable=1, Macro0, CA PI delay=33
4427 12:27:02.489346
4428 12:27:02.492368 [CBTSetCACLKResult] CA Dly = 33
4429 12:27:02.492497 CS Dly: 4 (0~36)
4430 12:27:02.492605
4431 12:27:02.496041 ----->DramcWriteLeveling(PI) begin...
4432 12:27:02.496143 ==
4433 12:27:02.499073 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 12:27:02.505696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 12:27:02.505796 ==
4436 12:27:02.509407 Write leveling (Byte 0): 29 => 29
4437 12:27:02.512444 Write leveling (Byte 1): 31 => 31
4438 12:27:02.515450 DramcWriteLeveling(PI) end<-----
4439 12:27:02.515568
4440 12:27:02.515639 ==
4441 12:27:02.519250 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 12:27:02.522369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 12:27:02.522476 ==
4444 12:27:02.525520 [Gating] SW mode calibration
4445 12:27:02.532216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4446 12:27:02.535334 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4447 12:27:02.542047 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 12:27:02.545062 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 12:27:02.548914 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 12:27:02.555491 0 9 12 | B1->B0 | 3131 3030 | 1 0 | (0 1) (0 1)
4451 12:27:02.558644 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4452 12:27:02.561783 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 12:27:02.568208 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 12:27:02.572035 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 12:27:02.575268 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 12:27:02.581725 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 12:27:02.584761 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4458 12:27:02.588479 0 10 12 | B1->B0 | 3030 3636 | 0 1 | (0 0) (0 0)
4459 12:27:02.594785 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 12:27:02.597904 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 12:27:02.601630 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 12:27:02.607855 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 12:27:02.611120 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 12:27:02.614804 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 12:27:02.621428 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 12:27:02.624406 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4467 12:27:02.627513 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:27:02.634647 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:27:02.637859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:27:02.640966 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:27:02.647904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:27:02.651054 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:27:02.654234 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:27:02.660608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:27:02.663836 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:27:02.667613 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:27:02.673899 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:27:02.677087 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:27:02.680362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:27:02.687327 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:27:02.690559 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:27:02.693682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4483 12:27:02.700728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 12:27:02.703844 Total UI for P1: 0, mck2ui 16
4485 12:27:02.706830 best dqsien dly found for B0: ( 0, 13, 12)
4486 12:27:02.710631 Total UI for P1: 0, mck2ui 16
4487 12:27:02.713764 best dqsien dly found for B1: ( 0, 13, 12)
4488 12:27:02.716878 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4489 12:27:02.720047 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4490 12:27:02.720129
4491 12:27:02.723629 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4492 12:27:02.726791 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4493 12:27:02.729929 [Gating] SW calibration Done
4494 12:27:02.730039 ==
4495 12:27:02.733155 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 12:27:02.736737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 12:27:02.736821 ==
4498 12:27:02.739726 RX Vref Scan: 0
4499 12:27:02.739811
4500 12:27:02.743492 RX Vref 0 -> 0, step: 1
4501 12:27:02.743577
4502 12:27:02.743678 RX Delay -230 -> 252, step: 16
4503 12:27:02.750197 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4504 12:27:02.753337 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4505 12:27:02.756539 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4506 12:27:02.759836 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4507 12:27:02.766223 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4508 12:27:02.770065 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4509 12:27:02.773190 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4510 12:27:02.776436 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4511 12:27:02.782729 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4512 12:27:02.786597 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4513 12:27:02.789655 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4514 12:27:02.792905 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4515 12:27:02.799371 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4516 12:27:02.802957 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4517 12:27:02.806156 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4518 12:27:02.809379 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4519 12:27:02.809487 ==
4520 12:27:02.812473 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 12:27:02.819469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 12:27:02.819588 ==
4523 12:27:02.819685 DQS Delay:
4524 12:27:02.822650 DQS0 = 0, DQS1 = 0
4525 12:27:02.822762 DQM Delay:
4526 12:27:02.822859 DQM0 = 47, DQM1 = 39
4527 12:27:02.825669 DQ Delay:
4528 12:27:02.828886 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4529 12:27:02.832781 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4530 12:27:02.835849 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4531 12:27:02.838890 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4532 12:27:02.839014
4533 12:27:02.839114
4534 12:27:02.839211 ==
4535 12:27:02.842447 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 12:27:02.845411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 12:27:02.845527 ==
4538 12:27:02.845624
4539 12:27:02.845727
4540 12:27:02.849177 TX Vref Scan disable
4541 12:27:02.852214 == TX Byte 0 ==
4542 12:27:02.855297 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4543 12:27:02.858482 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4544 12:27:02.862239 == TX Byte 1 ==
4545 12:27:02.865421 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4546 12:27:02.868486 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4547 12:27:02.868581 ==
4548 12:27:02.871768 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 12:27:02.875503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 12:27:02.878664 ==
4551 12:27:02.878774
4552 12:27:02.878875
4553 12:27:02.878967 TX Vref Scan disable
4554 12:27:02.882555 == TX Byte 0 ==
4555 12:27:02.885635 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 12:27:02.892849 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 12:27:02.892935 == TX Byte 1 ==
4558 12:27:02.896093 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4559 12:27:02.902388 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4560 12:27:02.902497
4561 12:27:02.902596 [DATLAT]
4562 12:27:02.902687 Freq=600, CH1 RK0
4563 12:27:02.902780
4564 12:27:02.906081 DATLAT Default: 0x9
4565 12:27:02.906187 0, 0xFFFF, sum = 0
4566 12:27:02.909268 1, 0xFFFF, sum = 0
4567 12:27:02.912361 2, 0xFFFF, sum = 0
4568 12:27:02.912472 3, 0xFFFF, sum = 0
4569 12:27:02.915378 4, 0xFFFF, sum = 0
4570 12:27:02.915494 5, 0xFFFF, sum = 0
4571 12:27:02.919028 6, 0xFFFF, sum = 0
4572 12:27:02.919145 7, 0xFFFF, sum = 0
4573 12:27:02.922283 8, 0x0, sum = 1
4574 12:27:02.922393 9, 0x0, sum = 2
4575 12:27:02.922490 10, 0x0, sum = 3
4576 12:27:02.925481 11, 0x0, sum = 4
4577 12:27:02.925603 best_step = 9
4578 12:27:02.925701
4579 12:27:02.928521 ==
4580 12:27:02.928632 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 12:27:02.935470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 12:27:02.935591 ==
4583 12:27:02.935688 RX Vref Scan: 1
4584 12:27:02.935779
4585 12:27:02.938723 RX Vref 0 -> 0, step: 1
4586 12:27:02.938830
4587 12:27:02.941739 RX Delay -195 -> 252, step: 8
4588 12:27:02.941815
4589 12:27:02.945308 Set Vref, RX VrefLevel [Byte0]: 48
4590 12:27:02.948292 [Byte1]: 57
4591 12:27:02.948395
4592 12:27:02.952086 Final RX Vref Byte 0 = 48 to rank0
4593 12:27:02.955225 Final RX Vref Byte 1 = 57 to rank0
4594 12:27:02.958227 Final RX Vref Byte 0 = 48 to rank1
4595 12:27:02.961967 Final RX Vref Byte 1 = 57 to rank1==
4596 12:27:02.965160 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 12:27:02.968266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 12:27:02.971462 ==
4599 12:27:02.971548 DQS Delay:
4600 12:27:02.971614 DQS0 = 0, DQS1 = 0
4601 12:27:02.975176 DQM Delay:
4602 12:27:02.975287 DQM0 = 47, DQM1 = 37
4603 12:27:02.978298 DQ Delay:
4604 12:27:02.978377 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4605 12:27:02.981439 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4606 12:27:02.984861 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4607 12:27:02.988008 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4608 12:27:02.991174
4609 12:27:02.991254
4610 12:27:02.998065 [DQSOSCAuto] RK0, (LSB)MR18= 0x5136, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4611 12:27:03.001273 CH1 RK0: MR19=808, MR18=5136
4612 12:27:03.007602 CH1_RK0: MR19=0x808, MR18=0x5136, DQSOSC=394, MR23=63, INC=168, DEC=112
4613 12:27:03.007690
4614 12:27:03.011256 ----->DramcWriteLeveling(PI) begin...
4615 12:27:03.011362 ==
4616 12:27:03.014424 Dram Type= 6, Freq= 0, CH_1, rank 1
4617 12:27:03.017544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 12:27:03.017636 ==
4619 12:27:03.020814 Write leveling (Byte 0): 29 => 29
4620 12:27:03.024627 Write leveling (Byte 1): 29 => 29
4621 12:27:03.027804 DramcWriteLeveling(PI) end<-----
4622 12:27:03.027911
4623 12:27:03.028005 ==
4624 12:27:03.030955 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 12:27:03.034548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 12:27:03.034655 ==
4627 12:27:03.037554 [Gating] SW mode calibration
4628 12:27:03.043837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4629 12:27:03.050645 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4630 12:27:03.053805 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 12:27:03.060564 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 12:27:03.063704 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 12:27:03.067512 0 9 12 | B1->B0 | 3131 3434 | 1 0 | (1 0) (0 1)
4634 12:27:03.073883 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4635 12:27:03.077079 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 12:27:03.080710 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 12:27:03.087152 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 12:27:03.090376 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 12:27:03.093579 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 12:27:03.100362 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 12:27:03.103470 0 10 12 | B1->B0 | 3434 2929 | 0 0 | (0 0) (0 0)
4642 12:27:03.106559 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4643 12:27:03.112987 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 12:27:03.116855 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 12:27:03.119948 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 12:27:03.126131 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 12:27:03.129320 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 12:27:03.133055 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 12:27:03.139860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4650 12:27:03.142896 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:27:03.146229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:27:03.152967 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:27:03.156036 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:27:03.159132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:27:03.166043 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:27:03.169137 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:27:03.172309 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:27:03.178646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:27:03.182490 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:27:03.185554 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:27:03.192002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 12:27:03.195158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 12:27:03.199012 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 12:27:03.205365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:27:03.208476 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4666 12:27:03.212286 Total UI for P1: 0, mck2ui 16
4667 12:27:03.215387 best dqsien dly found for B1: ( 0, 13, 10)
4668 12:27:03.218473 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 12:27:03.222257 Total UI for P1: 0, mck2ui 16
4670 12:27:03.225429 best dqsien dly found for B0: ( 0, 13, 12)
4671 12:27:03.228486 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4672 12:27:03.231861 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4673 12:27:03.231974
4674 12:27:03.238896 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4675 12:27:03.241923 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4676 12:27:03.245125 [Gating] SW calibration Done
4677 12:27:03.245244 ==
4678 12:27:03.248849 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 12:27:03.251976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 12:27:03.252077 ==
4681 12:27:03.252169 RX Vref Scan: 0
4682 12:27:03.252259
4683 12:27:03.254958 RX Vref 0 -> 0, step: 1
4684 12:27:03.255065
4685 12:27:03.258628 RX Delay -230 -> 252, step: 16
4686 12:27:03.261643 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4687 12:27:03.265258 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4688 12:27:03.271979 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4689 12:27:03.275178 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4690 12:27:03.278329 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4691 12:27:03.281382 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4692 12:27:03.288505 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4693 12:27:03.291775 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4694 12:27:03.294990 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4695 12:27:03.298125 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4696 12:27:03.304581 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4697 12:27:03.307897 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4698 12:27:03.311017 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4699 12:27:03.314227 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4700 12:27:03.321324 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4701 12:27:03.324389 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4702 12:27:03.324510 ==
4703 12:27:03.327640 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 12:27:03.330924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 12:27:03.331028 ==
4706 12:27:03.334659 DQS Delay:
4707 12:27:03.334745 DQS0 = 0, DQS1 = 0
4708 12:27:03.334818 DQM Delay:
4709 12:27:03.337891 DQM0 = 43, DQM1 = 36
4710 12:27:03.338003 DQ Delay:
4711 12:27:03.340998 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4712 12:27:03.344165 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4713 12:27:03.347289 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4714 12:27:03.351054 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4715 12:27:03.351159
4716 12:27:03.351257
4717 12:27:03.351348 ==
4718 12:27:03.354300 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 12:27:03.360492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 12:27:03.360601 ==
4721 12:27:03.360672
4722 12:27:03.360766
4723 12:27:03.360859 TX Vref Scan disable
4724 12:27:03.364127 == TX Byte 0 ==
4725 12:27:03.367830 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 12:27:03.374216 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 12:27:03.374327 == TX Byte 1 ==
4728 12:27:03.377867 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4729 12:27:03.384067 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4730 12:27:03.384150 ==
4731 12:27:03.387780 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 12:27:03.390868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 12:27:03.390978 ==
4734 12:27:03.391072
4735 12:27:03.391165
4736 12:27:03.394103 TX Vref Scan disable
4737 12:27:03.397220 == TX Byte 0 ==
4738 12:27:03.400415 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4739 12:27:03.404256 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4740 12:27:03.407362 == TX Byte 1 ==
4741 12:27:03.410498 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4742 12:27:03.413735 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4743 12:27:03.413839
4744 12:27:03.413936 [DATLAT]
4745 12:27:03.416922 Freq=600, CH1 RK1
4746 12:27:03.417001
4747 12:27:03.420071 DATLAT Default: 0x9
4748 12:27:03.420177 0, 0xFFFF, sum = 0
4749 12:27:03.423308 1, 0xFFFF, sum = 0
4750 12:27:03.423415 2, 0xFFFF, sum = 0
4751 12:27:03.426950 3, 0xFFFF, sum = 0
4752 12:27:03.427057 4, 0xFFFF, sum = 0
4753 12:27:03.430569 5, 0xFFFF, sum = 0
4754 12:27:03.430678 6, 0xFFFF, sum = 0
4755 12:27:03.433251 7, 0xFFFF, sum = 0
4756 12:27:03.433343 8, 0x0, sum = 1
4757 12:27:03.436994 9, 0x0, sum = 2
4758 12:27:03.437102 10, 0x0, sum = 3
4759 12:27:03.440061 11, 0x0, sum = 4
4760 12:27:03.440171 best_step = 9
4761 12:27:03.440274
4762 12:27:03.440378 ==
4763 12:27:03.443227 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 12:27:03.446470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 12:27:03.446585 ==
4766 12:27:03.450064 RX Vref Scan: 0
4767 12:27:03.450171
4768 12:27:03.453311 RX Vref 0 -> 0, step: 1
4769 12:27:03.453421
4770 12:27:03.453520 RX Delay -195 -> 252, step: 8
4771 12:27:03.461407 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4772 12:27:03.464431 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4773 12:27:03.468170 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4774 12:27:03.471253 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4775 12:27:03.478026 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4776 12:27:03.481251 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4777 12:27:03.484306 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4778 12:27:03.487985 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4779 12:27:03.494230 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4780 12:27:03.497355 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4781 12:27:03.500550 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4782 12:27:03.503809 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4783 12:27:03.510860 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4784 12:27:03.514042 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4785 12:27:03.517254 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4786 12:27:03.520378 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4787 12:27:03.520484 ==
4788 12:27:03.524206 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 12:27:03.530529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 12:27:03.530640 ==
4791 12:27:03.530737 DQS Delay:
4792 12:27:03.534213 DQS0 = 0, DQS1 = 0
4793 12:27:03.534301 DQM Delay:
4794 12:27:03.534378 DQM0 = 45, DQM1 = 37
4795 12:27:03.537388 DQ Delay:
4796 12:27:03.540626 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4797 12:27:03.543844 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4798 12:27:03.547086 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4799 12:27:03.550285 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4800 12:27:03.550379
4801 12:27:03.550452
4802 12:27:03.557035 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4803 12:27:03.560688 CH1 RK1: MR19=808, MR18=2A20
4804 12:27:03.566749 CH1_RK1: MR19=0x808, MR18=0x2A20, DQSOSC=401, MR23=63, INC=163, DEC=108
4805 12:27:03.570299 [RxdqsGatingPostProcess] freq 600
4806 12:27:03.573520 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4807 12:27:03.576608 Pre-setting of DQS Precalculation
4808 12:27:03.583475 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4809 12:27:03.590308 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4810 12:27:03.596501 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4811 12:27:03.596623
4812 12:27:03.596720
4813 12:27:03.600222 [Calibration Summary] 1200 Mbps
4814 12:27:03.600336 CH 0, Rank 0
4815 12:27:03.603397 SW Impedance : PASS
4816 12:27:03.606464 DUTY Scan : NO K
4817 12:27:03.606570 ZQ Calibration : PASS
4818 12:27:03.609728 Jitter Meter : NO K
4819 12:27:03.612903 CBT Training : PASS
4820 12:27:03.613016 Write leveling : PASS
4821 12:27:03.616241 RX DQS gating : PASS
4822 12:27:03.619400 RX DQ/DQS(RDDQC) : PASS
4823 12:27:03.619511 TX DQ/DQS : PASS
4824 12:27:03.623108 RX DATLAT : PASS
4825 12:27:03.626192 RX DQ/DQS(Engine): PASS
4826 12:27:03.626299 TX OE : NO K
4827 12:27:03.629541 All Pass.
4828 12:27:03.629649
4829 12:27:03.629751 CH 0, Rank 1
4830 12:27:03.632522 SW Impedance : PASS
4831 12:27:03.632633 DUTY Scan : NO K
4832 12:27:03.635877 ZQ Calibration : PASS
4833 12:27:03.639492 Jitter Meter : NO K
4834 12:27:03.639615 CBT Training : PASS
4835 12:27:03.642528 Write leveling : PASS
4836 12:27:03.646374 RX DQS gating : PASS
4837 12:27:03.646487 RX DQ/DQS(RDDQC) : PASS
4838 12:27:03.649564 TX DQ/DQS : PASS
4839 12:27:03.652697 RX DATLAT : PASS
4840 12:27:03.652776 RX DQ/DQS(Engine): PASS
4841 12:27:03.655812 TX OE : NO K
4842 12:27:03.655918 All Pass.
4843 12:27:03.656011
4844 12:27:03.659421 CH 1, Rank 0
4845 12:27:03.659500 SW Impedance : PASS
4846 12:27:03.662382 DUTY Scan : NO K
4847 12:27:03.665524 ZQ Calibration : PASS
4848 12:27:03.665625 Jitter Meter : NO K
4849 12:27:03.669402 CBT Training : PASS
4850 12:27:03.669515 Write leveling : PASS
4851 12:27:03.672468 RX DQS gating : PASS
4852 12:27:03.675518 RX DQ/DQS(RDDQC) : PASS
4853 12:27:03.675624 TX DQ/DQS : PASS
4854 12:27:03.679028 RX DATLAT : PASS
4855 12:27:03.682099 RX DQ/DQS(Engine): PASS
4856 12:27:03.682206 TX OE : NO K
4857 12:27:03.685762 All Pass.
4858 12:27:03.685869
4859 12:27:03.685981 CH 1, Rank 1
4860 12:27:03.688850 SW Impedance : PASS
4861 12:27:03.688955 DUTY Scan : NO K
4862 12:27:03.692064 ZQ Calibration : PASS
4863 12:27:03.695755 Jitter Meter : NO K
4864 12:27:03.695861 CBT Training : PASS
4865 12:27:03.698872 Write leveling : PASS
4866 12:27:03.702072 RX DQS gating : PASS
4867 12:27:03.702178 RX DQ/DQS(RDDQC) : PASS
4868 12:27:03.705847 TX DQ/DQS : PASS
4869 12:27:03.709092 RX DATLAT : PASS
4870 12:27:03.709210 RX DQ/DQS(Engine): PASS
4871 12:27:03.712290 TX OE : NO K
4872 12:27:03.712396 All Pass.
4873 12:27:03.712490
4874 12:27:03.715420 DramC Write-DBI off
4875 12:27:03.718839 PER_BANK_REFRESH: Hybrid Mode
4876 12:27:03.718949 TX_TRACKING: ON
4877 12:27:03.728885 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4878 12:27:03.731969 [FAST_K] Save calibration result to emmc
4879 12:27:03.735733 dramc_set_vcore_voltage set vcore to 662500
4880 12:27:03.738771 Read voltage for 933, 3
4881 12:27:03.738879 Vio18 = 0
4882 12:27:03.738975 Vcore = 662500
4883 12:27:03.741801 Vdram = 0
4884 12:27:03.741903 Vddq = 0
4885 12:27:03.742011 Vmddr = 0
4886 12:27:03.748767 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4887 12:27:03.751855 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4888 12:27:03.755042 MEM_TYPE=3, freq_sel=17
4889 12:27:03.758306 sv_algorithm_assistance_LP4_1600
4890 12:27:03.761961 ============ PULL DRAM RESETB DOWN ============
4891 12:27:03.765064 ========== PULL DRAM RESETB DOWN end =========
4892 12:27:03.771860 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4893 12:27:03.774922 ===================================
4894 12:27:03.775036 LPDDR4 DRAM CONFIGURATION
4895 12:27:03.778544 ===================================
4896 12:27:03.781592 EX_ROW_EN[0] = 0x0
4897 12:27:03.785210 EX_ROW_EN[1] = 0x0
4898 12:27:03.785290 LP4Y_EN = 0x0
4899 12:27:03.788356 WORK_FSP = 0x0
4900 12:27:03.788458 WL = 0x3
4901 12:27:03.791375 RL = 0x3
4902 12:27:03.791476 BL = 0x2
4903 12:27:03.795052 RPST = 0x0
4904 12:27:03.795125 RD_PRE = 0x0
4905 12:27:03.798213 WR_PRE = 0x1
4906 12:27:03.798297 WR_PST = 0x0
4907 12:27:03.801769 DBI_WR = 0x0
4908 12:27:03.801854 DBI_RD = 0x0
4909 12:27:03.805018 OTF = 0x1
4910 12:27:03.808299 ===================================
4911 12:27:03.811371 ===================================
4912 12:27:03.811455 ANA top config
4913 12:27:03.814573 ===================================
4914 12:27:03.817852 DLL_ASYNC_EN = 0
4915 12:27:03.821044 ALL_SLAVE_EN = 1
4916 12:27:03.824266 NEW_RANK_MODE = 1
4917 12:27:03.824342 DLL_IDLE_MODE = 1
4918 12:27:03.828069 LP45_APHY_COMB_EN = 1
4919 12:27:03.831246 TX_ODT_DIS = 1
4920 12:27:03.834400 NEW_8X_MODE = 1
4921 12:27:03.837510 ===================================
4922 12:27:03.841186 ===================================
4923 12:27:03.844331 data_rate = 1866
4924 12:27:03.847951 CKR = 1
4925 12:27:03.848031 DQ_P2S_RATIO = 8
4926 12:27:03.851151 ===================================
4927 12:27:03.854282 CA_P2S_RATIO = 8
4928 12:27:03.857611 DQ_CA_OPEN = 0
4929 12:27:03.860767 DQ_SEMI_OPEN = 0
4930 12:27:03.864350 CA_SEMI_OPEN = 0
4931 12:27:03.867454 CA_FULL_RATE = 0
4932 12:27:03.867540 DQ_CKDIV4_EN = 1
4933 12:27:03.870433 CA_CKDIV4_EN = 1
4934 12:27:03.874321 CA_PREDIV_EN = 0
4935 12:27:03.877477 PH8_DLY = 0
4936 12:27:03.880597 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4937 12:27:03.883575 DQ_AAMCK_DIV = 4
4938 12:27:03.883663 CA_AAMCK_DIV = 4
4939 12:27:03.887187 CA_ADMCK_DIV = 4
4940 12:27:03.890320 DQ_TRACK_CA_EN = 0
4941 12:27:03.894075 CA_PICK = 933
4942 12:27:03.897126 CA_MCKIO = 933
4943 12:27:03.900224 MCKIO_SEMI = 0
4944 12:27:03.903408 PLL_FREQ = 3732
4945 12:27:03.903491 DQ_UI_PI_RATIO = 32
4946 12:27:03.907163 CA_UI_PI_RATIO = 0
4947 12:27:03.910369 ===================================
4948 12:27:03.913506 ===================================
4949 12:27:03.916756 memory_type:LPDDR4
4950 12:27:03.919818 GP_NUM : 10
4951 12:27:03.919900 SRAM_EN : 1
4952 12:27:03.923646 MD32_EN : 0
4953 12:27:03.926855 ===================================
4954 12:27:03.930123 [ANA_INIT] >>>>>>>>>>>>>>
4955 12:27:03.933355 <<<<<< [CONFIGURE PHASE]: ANA_TX
4956 12:27:03.936983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4957 12:27:03.940093 ===================================
4958 12:27:03.940183 data_rate = 1866,PCW = 0X8f00
4959 12:27:03.943348 ===================================
4960 12:27:03.946498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4961 12:27:03.953323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4962 12:27:03.959436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 12:27:03.963301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4964 12:27:03.966415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4965 12:27:03.969534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4966 12:27:03.972751 [ANA_INIT] flow start
4967 12:27:03.976299 [ANA_INIT] PLL >>>>>>>>
4968 12:27:03.976413 [ANA_INIT] PLL <<<<<<<<
4969 12:27:03.979532 [ANA_INIT] MIDPI >>>>>>>>
4970 12:27:03.982675 [ANA_INIT] MIDPI <<<<<<<<
4971 12:27:03.982763 [ANA_INIT] DLL >>>>>>>>
4972 12:27:03.985759 [ANA_INIT] flow end
4973 12:27:03.989396 ============ LP4 DIFF to SE enter ============
4974 12:27:03.992374 ============ LP4 DIFF to SE exit ============
4975 12:27:03.996019 [ANA_INIT] <<<<<<<<<<<<<
4976 12:27:03.999170 [Flow] Enable top DCM control >>>>>
4977 12:27:04.002272 [Flow] Enable top DCM control <<<<<
4978 12:27:04.005867 Enable DLL master slave shuffle
4979 12:27:04.012159 ==============================================================
4980 12:27:04.012272 Gating Mode config
4981 12:27:04.019282 ==============================================================
4982 12:27:04.022449 Config description:
4983 12:27:04.028849 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4984 12:27:04.035162 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4985 12:27:04.042040 SELPH_MODE 0: By rank 1: By Phase
4986 12:27:04.048377 ==============================================================
4987 12:27:04.052137 GAT_TRACK_EN = 1
4988 12:27:04.052228 RX_GATING_MODE = 2
4989 12:27:04.055252 RX_GATING_TRACK_MODE = 2
4990 12:27:04.058403 SELPH_MODE = 1
4991 12:27:04.061618 PICG_EARLY_EN = 1
4992 12:27:04.064760 VALID_LAT_VALUE = 1
4993 12:27:04.071550 ==============================================================
4994 12:27:04.074659 Enter into Gating configuration >>>>
4995 12:27:04.077793 Exit from Gating configuration <<<<
4996 12:27:04.081550 Enter into DVFS_PRE_config >>>>>
4997 12:27:04.091006 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4998 12:27:04.094737 Exit from DVFS_PRE_config <<<<<
4999 12:27:04.097541 Enter into PICG configuration >>>>
5000 12:27:04.101283 Exit from PICG configuration <<<<
5001 12:27:04.104401 [RX_INPUT] configuration >>>>>
5002 12:27:04.108134 [RX_INPUT] configuration <<<<<
5003 12:27:04.111192 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5004 12:27:04.118051 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5005 12:27:04.124255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 12:27:04.130630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 12:27:04.134400 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 12:27:04.140740 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 12:27:04.147766 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5010 12:27:04.151065 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5011 12:27:04.154099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5012 12:27:04.157243 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5013 12:27:04.160969 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5014 12:27:04.167177 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 12:27:04.170925 ===================================
5016 12:27:04.173629 LPDDR4 DRAM CONFIGURATION
5017 12:27:04.177194 ===================================
5018 12:27:04.177275 EX_ROW_EN[0] = 0x0
5019 12:27:04.180253 EX_ROW_EN[1] = 0x0
5020 12:27:04.180359 LP4Y_EN = 0x0
5021 12:27:04.184080 WORK_FSP = 0x0
5022 12:27:04.184188 WL = 0x3
5023 12:27:04.187211 RL = 0x3
5024 12:27:04.187313 BL = 0x2
5025 12:27:04.190384 RPST = 0x0
5026 12:27:04.190487 RD_PRE = 0x0
5027 12:27:04.193497 WR_PRE = 0x1
5028 12:27:04.197139 WR_PST = 0x0
5029 12:27:04.197223 DBI_WR = 0x0
5030 12:27:04.200239 DBI_RD = 0x0
5031 12:27:04.200344 OTF = 0x1
5032 12:27:04.203285 ===================================
5033 12:27:04.206935 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5034 12:27:04.210039 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5035 12:27:04.216769 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 12:27:04.219881 ===================================
5037 12:27:04.223072 LPDDR4 DRAM CONFIGURATION
5038 12:27:04.226899 ===================================
5039 12:27:04.227003 EX_ROW_EN[0] = 0x10
5040 12:27:04.230148 EX_ROW_EN[1] = 0x0
5041 12:27:04.230249 LP4Y_EN = 0x0
5042 12:27:04.233451 WORK_FSP = 0x0
5043 12:27:04.233527 WL = 0x3
5044 12:27:04.236571 RL = 0x3
5045 12:27:04.236642 BL = 0x2
5046 12:27:04.239746 RPST = 0x0
5047 12:27:04.239823 RD_PRE = 0x0
5048 12:27:04.242981 WR_PRE = 0x1
5049 12:27:04.246197 WR_PST = 0x0
5050 12:27:04.246300 DBI_WR = 0x0
5051 12:27:04.249517 DBI_RD = 0x0
5052 12:27:04.249597 OTF = 0x1
5053 12:27:04.253087 ===================================
5054 12:27:04.259558 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5055 12:27:04.263174 nWR fixed to 30
5056 12:27:04.266322 [ModeRegInit_LP4] CH0 RK0
5057 12:27:04.266436 [ModeRegInit_LP4] CH0 RK1
5058 12:27:04.270131 [ModeRegInit_LP4] CH1 RK0
5059 12:27:04.273226 [ModeRegInit_LP4] CH1 RK1
5060 12:27:04.273312 match AC timing 9
5061 12:27:04.279509 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5062 12:27:04.283190 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5063 12:27:04.286347 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5064 12:27:04.293094 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5065 12:27:04.296294 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5066 12:27:04.296402 ==
5067 12:27:04.299926 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 12:27:04.302891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 12:27:04.302997 ==
5070 12:27:04.309511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 12:27:04.316280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5072 12:27:04.319267 [CA 0] Center 37 (7~68) winsize 62
5073 12:27:04.323083 [CA 1] Center 37 (7~68) winsize 62
5074 12:27:04.326316 [CA 2] Center 34 (4~65) winsize 62
5075 12:27:04.329448 [CA 3] Center 35 (5~65) winsize 61
5076 12:27:04.332726 [CA 4] Center 33 (3~64) winsize 62
5077 12:27:04.336505 [CA 5] Center 33 (3~64) winsize 62
5078 12:27:04.336601
5079 12:27:04.339724 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5080 12:27:04.339809
5081 12:27:04.342865 [CATrainingPosCal] consider 1 rank data
5082 12:27:04.346237 u2DelayCellTimex100 = 270/100 ps
5083 12:27:04.349423 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5084 12:27:04.352479 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5085 12:27:04.355688 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5086 12:27:04.359352 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5087 12:27:04.362585 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5088 12:27:04.369435 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5089 12:27:04.369535
5090 12:27:04.372564 CA PerBit enable=1, Macro0, CA PI delay=33
5091 12:27:04.372649
5092 12:27:04.375776 [CBTSetCACLKResult] CA Dly = 33
5093 12:27:04.375861 CS Dly: 7 (0~38)
5094 12:27:04.375928 ==
5095 12:27:04.378899 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 12:27:04.385877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 12:27:04.385965 ==
5098 12:27:04.388931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 12:27:04.395583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5100 12:27:04.398773 [CA 0] Center 37 (7~68) winsize 62
5101 12:27:04.402033 [CA 1] Center 37 (7~68) winsize 62
5102 12:27:04.405723 [CA 2] Center 34 (4~65) winsize 62
5103 12:27:04.408727 [CA 3] Center 34 (4~65) winsize 62
5104 12:27:04.411781 [CA 4] Center 33 (3~64) winsize 62
5105 12:27:04.415444 [CA 5] Center 33 (3~63) winsize 61
5106 12:27:04.415529
5107 12:27:04.418455 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5108 12:27:04.418540
5109 12:27:04.421578 [CATrainingPosCal] consider 2 rank data
5110 12:27:04.425248 u2DelayCellTimex100 = 270/100 ps
5111 12:27:04.428392 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5112 12:27:04.431618 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5113 12:27:04.438643 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5114 12:27:04.441799 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5115 12:27:04.444876 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5116 12:27:04.448794 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5117 12:27:04.448880
5118 12:27:04.451871 CA PerBit enable=1, Macro0, CA PI delay=33
5119 12:27:04.451950
5120 12:27:04.454980 [CBTSetCACLKResult] CA Dly = 33
5121 12:27:04.455083 CS Dly: 7 (0~39)
5122 12:27:04.455183
5123 12:27:04.458164 ----->DramcWriteLeveling(PI) begin...
5124 12:27:04.462005 ==
5125 12:27:04.465162 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 12:27:04.468218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 12:27:04.468325 ==
5128 12:27:04.471378 Write leveling (Byte 0): 34 => 34
5129 12:27:04.474620 Write leveling (Byte 1): 29 => 29
5130 12:27:04.478475 DramcWriteLeveling(PI) end<-----
5131 12:27:04.478560
5132 12:27:04.478626 ==
5133 12:27:04.481628 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 12:27:04.484887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 12:27:04.484973 ==
5136 12:27:04.488264 [Gating] SW mode calibration
5137 12:27:04.494614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5138 12:27:04.501130 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5139 12:27:04.504381 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5140 12:27:04.507635 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5141 12:27:04.514246 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 12:27:04.517846 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 12:27:04.520982 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 12:27:04.527745 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 12:27:04.530864 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 12:27:04.534670 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5147 12:27:04.537774 0 15 0 | B1->B0 | 3232 2626 | 1 0 | (1 0) (1 0)
5148 12:27:04.544648 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 12:27:04.548019 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 12:27:04.551350 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 12:27:04.557688 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 12:27:04.560811 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 12:27:04.567651 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 12:27:04.570729 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5155 12:27:04.573868 1 0 0 | B1->B0 | 2e2e 4242 | 1 0 | (0 0) (0 0)
5156 12:27:04.577580 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 12:27:04.583969 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 12:27:04.587148 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 12:27:04.593514 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 12:27:04.597225 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 12:27:04.600308 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 12:27:04.603497 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 12:27:04.610413 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5164 12:27:04.613606 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:27:04.617294 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:27:04.623830 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:27:04.626847 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:27:04.630423 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:27:04.636672 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:27:04.639830 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:27:04.646631 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 12:27:04.649776 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 12:27:04.653024 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 12:27:04.656808 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 12:27:04.663265 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:27:04.666619 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 12:27:04.669729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:27:04.676598 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5179 12:27:04.679870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5180 12:27:04.682966 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 12:27:04.686161 Total UI for P1: 0, mck2ui 16
5182 12:27:04.689912 best dqsien dly found for B0: ( 1, 2, 30)
5183 12:27:04.693155 Total UI for P1: 0, mck2ui 16
5184 12:27:04.696418 best dqsien dly found for B1: ( 1, 3, 2)
5185 12:27:04.699486 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5186 12:27:04.706215 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5187 12:27:04.706328
5188 12:27:04.709304 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5189 12:27:04.712445 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5190 12:27:04.715596 [Gating] SW calibration Done
5191 12:27:04.715677 ==
5192 12:27:04.718865 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 12:27:04.722574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 12:27:04.722688 ==
5195 12:27:04.725653 RX Vref Scan: 0
5196 12:27:04.725735
5197 12:27:04.725800 RX Vref 0 -> 0, step: 1
5198 12:27:04.725861
5199 12:27:04.729226 RX Delay -80 -> 252, step: 8
5200 12:27:04.732376 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5201 12:27:04.735492 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5202 12:27:04.742367 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5203 12:27:04.745555 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5204 12:27:04.748668 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5205 12:27:04.752344 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5206 12:27:04.755619 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5207 12:27:04.758772 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5208 12:27:04.765304 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5209 12:27:04.768382 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5210 12:27:04.772213 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5211 12:27:04.775414 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5212 12:27:04.781861 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5213 12:27:04.784802 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5214 12:27:04.788523 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5215 12:27:04.791736 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5216 12:27:04.791824 ==
5217 12:27:04.794770 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 12:27:04.798108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 12:27:04.801440 ==
5220 12:27:04.801550 DQS Delay:
5221 12:27:04.801643 DQS0 = 0, DQS1 = 0
5222 12:27:04.805013 DQM Delay:
5223 12:27:04.805099 DQM0 = 97, DQM1 = 86
5224 12:27:04.808184 DQ Delay:
5225 12:27:04.808320 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5226 12:27:04.811267 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5227 12:27:04.815063 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5228 12:27:04.818174 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5229 12:27:04.821349
5230 12:27:04.821430
5231 12:27:04.821491 ==
5232 12:27:04.824490 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 12:27:04.828270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 12:27:04.828370 ==
5235 12:27:04.828460
5236 12:27:04.828552
5237 12:27:04.831380 TX Vref Scan disable
5238 12:27:04.831452 == TX Byte 0 ==
5239 12:27:04.838117 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5240 12:27:04.841225 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5241 12:27:04.841323 == TX Byte 1 ==
5242 12:27:04.847518 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5243 12:27:04.850791 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5244 12:27:04.850892 ==
5245 12:27:04.854559 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 12:27:04.857858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 12:27:04.857932 ==
5248 12:27:04.858029
5249 12:27:04.860982
5250 12:27:04.861086 TX Vref Scan disable
5251 12:27:04.864160 == TX Byte 0 ==
5252 12:27:04.867351 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5253 12:27:04.870497 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5254 12:27:04.874284 == TX Byte 1 ==
5255 12:27:04.877562 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5256 12:27:04.883896 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5257 12:27:04.883975
5258 12:27:04.884039 [DATLAT]
5259 12:27:04.884126 Freq=933, CH0 RK0
5260 12:27:04.884215
5261 12:27:04.887516 DATLAT Default: 0xd
5262 12:27:04.887612 0, 0xFFFF, sum = 0
5263 12:27:04.890734 1, 0xFFFF, sum = 0
5264 12:27:04.890806 2, 0xFFFF, sum = 0
5265 12:27:04.893956 3, 0xFFFF, sum = 0
5266 12:27:04.897193 4, 0xFFFF, sum = 0
5267 12:27:04.897266 5, 0xFFFF, sum = 0
5268 12:27:04.900281 6, 0xFFFF, sum = 0
5269 12:27:04.900357 7, 0xFFFF, sum = 0
5270 12:27:04.903992 8, 0xFFFF, sum = 0
5271 12:27:04.904067 9, 0xFFFF, sum = 0
5272 12:27:04.907073 10, 0x0, sum = 1
5273 12:27:04.907186 11, 0x0, sum = 2
5274 12:27:04.910035 12, 0x0, sum = 3
5275 12:27:04.910150 13, 0x0, sum = 4
5276 12:27:04.910252 best_step = 11
5277 12:27:04.913777
5278 12:27:04.913860 ==
5279 12:27:04.916924 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 12:27:04.920064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 12:27:04.920148 ==
5282 12:27:04.920214 RX Vref Scan: 1
5283 12:27:04.920275
5284 12:27:04.923245 RX Vref 0 -> 0, step: 1
5285 12:27:04.923336
5286 12:27:04.926426 RX Delay -61 -> 252, step: 4
5287 12:27:04.926512
5288 12:27:04.930261 Set Vref, RX VrefLevel [Byte0]: 61
5289 12:27:04.933263 [Byte1]: 50
5290 12:27:04.936819
5291 12:27:04.936902 Final RX Vref Byte 0 = 61 to rank0
5292 12:27:04.939986 Final RX Vref Byte 1 = 50 to rank0
5293 12:27:04.943499 Final RX Vref Byte 0 = 61 to rank1
5294 12:27:04.946521 Final RX Vref Byte 1 = 50 to rank1==
5295 12:27:04.949766 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 12:27:04.956815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 12:27:04.956901 ==
5298 12:27:04.956966 DQS Delay:
5299 12:27:04.959976 DQS0 = 0, DQS1 = 0
5300 12:27:04.960057 DQM Delay:
5301 12:27:04.960137 DQM0 = 97, DQM1 = 85
5302 12:27:04.963271 DQ Delay:
5303 12:27:04.966381 DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94
5304 12:27:04.969547 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5305 12:27:04.973154 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =82
5306 12:27:04.976350 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =92
5307 12:27:04.976475
5308 12:27:04.976592
5309 12:27:04.982914 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5310 12:27:04.985943 CH0 RK0: MR19=505, MR18=2B11
5311 12:27:04.992855 CH0_RK0: MR19=0x505, MR18=0x2B11, DQSOSC=408, MR23=63, INC=65, DEC=43
5312 12:27:04.992938
5313 12:27:04.995963 ----->DramcWriteLeveling(PI) begin...
5314 12:27:04.996046 ==
5315 12:27:04.999845 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 12:27:05.002920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 12:27:05.003040 ==
5318 12:27:05.006069 Write leveling (Byte 0): 33 => 33
5319 12:27:05.009299 Write leveling (Byte 1): 28 => 28
5320 12:27:05.012931 DramcWriteLeveling(PI) end<-----
5321 12:27:05.013032
5322 12:27:05.013124 ==
5323 12:27:05.016014 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 12:27:05.019116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 12:27:05.019216 ==
5326 12:27:05.022798 [Gating] SW mode calibration
5327 12:27:05.029171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5328 12:27:05.036128 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5329 12:27:05.039117 0 14 0 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (1 1)
5330 12:27:05.045854 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 12:27:05.048981 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 12:27:05.052508 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 12:27:05.058880 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 12:27:05.062071 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 12:27:05.065954 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5336 12:27:05.072316 0 14 28 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)
5337 12:27:05.075502 0 15 0 | B1->B0 | 2e2e 2525 | 0 0 | (1 0) (0 0)
5338 12:27:05.078736 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5339 12:27:05.085670 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 12:27:05.088648 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 12:27:05.091922 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 12:27:05.098818 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 12:27:05.102034 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 12:27:05.105137 0 15 28 | B1->B0 | 2626 3535 | 0 1 | (0 0) (0 0)
5345 12:27:05.111454 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5346 12:27:05.115169 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 12:27:05.118093 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 12:27:05.124946 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 12:27:05.127873 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 12:27:05.131624 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 12:27:05.137765 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 12:27:05.141409 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 12:27:05.144438 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5354 12:27:05.151271 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:27:05.154333 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:27:05.158033 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:27:05.164478 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:27:05.167583 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:27:05.170840 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:27:05.177397 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:27:05.180533 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:27:05.184312 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:27:05.190567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:27:05.194362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:27:05.197469 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:27:05.203690 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 12:27:05.207467 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:27:05.210639 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5369 12:27:05.217173 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5370 12:27:05.217254 Total UI for P1: 0, mck2ui 16
5371 12:27:05.223891 best dqsien dly found for B0: ( 1, 2, 28)
5372 12:27:05.227013 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 12:27:05.230129 Total UI for P1: 0, mck2ui 16
5374 12:27:05.233788 best dqsien dly found for B1: ( 1, 2, 30)
5375 12:27:05.237022 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5376 12:27:05.240156 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5377 12:27:05.240261
5378 12:27:05.243177 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5379 12:27:05.246817 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5380 12:27:05.249787 [Gating] SW calibration Done
5381 12:27:05.249870 ==
5382 12:27:05.253403 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 12:27:05.259632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 12:27:05.259737 ==
5385 12:27:05.259840 RX Vref Scan: 0
5386 12:27:05.259931
5387 12:27:05.263330 RX Vref 0 -> 0, step: 1
5388 12:27:05.263415
5389 12:27:05.266529 RX Delay -80 -> 252, step: 8
5390 12:27:05.269697 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5391 12:27:05.272875 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5392 12:27:05.276604 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5393 12:27:05.279851 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5394 12:27:05.283038 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5395 12:27:05.289335 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5396 12:27:05.293217 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5397 12:27:05.296305 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5398 12:27:05.299416 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5399 12:27:05.303121 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5400 12:27:05.309593 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5401 12:27:05.312738 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5402 12:27:05.316469 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5403 12:27:05.319754 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5404 12:27:05.322922 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5405 12:27:05.329432 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5406 12:27:05.329537 ==
5407 12:27:05.332661 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 12:27:05.335723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 12:27:05.335827 ==
5410 12:27:05.335918 DQS Delay:
5411 12:27:05.339532 DQS0 = 0, DQS1 = 0
5412 12:27:05.339633 DQM Delay:
5413 12:27:05.342831 DQM0 = 97, DQM1 = 87
5414 12:27:05.342935 DQ Delay:
5415 12:27:05.345965 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5416 12:27:05.349116 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5417 12:27:05.352672 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5418 12:27:05.355619 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5419 12:27:05.355723
5420 12:27:05.355814
5421 12:27:05.355907 ==
5422 12:27:05.358809 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 12:27:05.362318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 12:27:05.365391 ==
5425 12:27:05.365582
5426 12:27:05.365748
5427 12:27:05.365815 TX Vref Scan disable
5428 12:27:05.368615 == TX Byte 0 ==
5429 12:27:05.372334 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5430 12:27:05.375583 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5431 12:27:05.378838 == TX Byte 1 ==
5432 12:27:05.382075 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5433 12:27:05.385217 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5434 12:27:05.388890 ==
5435 12:27:05.392034 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 12:27:05.395234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 12:27:05.395336 ==
5438 12:27:05.395427
5439 12:27:05.395515
5440 12:27:05.398425 TX Vref Scan disable
5441 12:27:05.398526 == TX Byte 0 ==
5442 12:27:05.405336 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5443 12:27:05.408450 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5444 12:27:05.408568 == TX Byte 1 ==
5445 12:27:05.414757 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5446 12:27:05.418446 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5447 12:27:05.418553
5448 12:27:05.418645 [DATLAT]
5449 12:27:05.421602 Freq=933, CH0 RK1
5450 12:27:05.421698
5451 12:27:05.421787 DATLAT Default: 0xb
5452 12:27:05.424915 0, 0xFFFF, sum = 0
5453 12:27:05.428026 1, 0xFFFF, sum = 0
5454 12:27:05.428135 2, 0xFFFF, sum = 0
5455 12:27:05.431620 3, 0xFFFF, sum = 0
5456 12:27:05.431728 4, 0xFFFF, sum = 0
5457 12:27:05.434789 5, 0xFFFF, sum = 0
5458 12:27:05.434910 6, 0xFFFF, sum = 0
5459 12:27:05.437893 7, 0xFFFF, sum = 0
5460 12:27:05.437995 8, 0xFFFF, sum = 0
5461 12:27:05.441677 9, 0xFFFF, sum = 0
5462 12:27:05.441781 10, 0x0, sum = 1
5463 12:27:05.444889 11, 0x0, sum = 2
5464 12:27:05.444996 12, 0x0, sum = 3
5465 12:27:05.448036 13, 0x0, sum = 4
5466 12:27:05.448136 best_step = 11
5467 12:27:05.448244
5468 12:27:05.448339 ==
5469 12:27:05.451152 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 12:27:05.454885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 12:27:05.454985 ==
5472 12:27:05.457835 RX Vref Scan: 0
5473 12:27:05.457939
5474 12:27:05.460899 RX Vref 0 -> 0, step: 1
5475 12:27:05.461025
5476 12:27:05.461135 RX Delay -61 -> 252, step: 4
5477 12:27:05.468775 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5478 12:27:05.472479 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5479 12:27:05.475657 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5480 12:27:05.478927 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5481 12:27:05.482044 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5482 12:27:05.488479 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5483 12:27:05.491774 iDelay=203, Bit 6, Center 108 (15 ~ 202) 188
5484 12:27:05.495538 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5485 12:27:05.498696 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5486 12:27:05.501946 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5487 12:27:05.508363 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5488 12:27:05.512085 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5489 12:27:05.515167 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5490 12:27:05.518538 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5491 12:27:05.521548 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5492 12:27:05.528543 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5493 12:27:05.528648 ==
5494 12:27:05.531634 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 12:27:05.534765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 12:27:05.534840 ==
5497 12:27:05.534903 DQS Delay:
5498 12:27:05.538512 DQS0 = 0, DQS1 = 0
5499 12:27:05.538617 DQM Delay:
5500 12:27:05.541642 DQM0 = 95, DQM1 = 86
5501 12:27:05.541719 DQ Delay:
5502 12:27:05.544841 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5503 12:27:05.548110 DQ4 =94, DQ5 =86, DQ6 =108, DQ7 =104
5504 12:27:05.551389 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5505 12:27:05.555094 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =92
5506 12:27:05.555166
5507 12:27:05.555231
5508 12:27:05.564782 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5509 12:27:05.564872 CH0 RK1: MR19=504, MR18=2BFB
5510 12:27:05.571552 CH0_RK1: MR19=0x504, MR18=0x2BFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5511 12:27:05.574593 [RxdqsGatingPostProcess] freq 933
5512 12:27:05.581006 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5513 12:27:05.584350 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 12:27:05.588009 best DQS1 dly(2T, 0.5T) = (0, 11)
5515 12:27:05.591344 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 12:27:05.594463 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5517 12:27:05.597619 best DQS0 dly(2T, 0.5T) = (0, 10)
5518 12:27:05.597702 best DQS1 dly(2T, 0.5T) = (0, 10)
5519 12:27:05.600810 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5520 12:27:05.603995 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5521 12:27:05.607848 Pre-setting of DQS Precalculation
5522 12:27:05.614084 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5523 12:27:05.614163 ==
5524 12:27:05.617226 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 12:27:05.620905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 12:27:05.620985 ==
5527 12:27:05.627098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 12:27:05.634101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5529 12:27:05.637167 [CA 0] Center 36 (6~67) winsize 62
5530 12:27:05.640471 [CA 1] Center 37 (7~67) winsize 61
5531 12:27:05.644263 [CA 2] Center 34 (4~64) winsize 61
5532 12:27:05.647313 [CA 3] Center 33 (3~64) winsize 62
5533 12:27:05.650394 [CA 4] Center 34 (4~64) winsize 61
5534 12:27:05.653514 [CA 5] Center 33 (3~64) winsize 62
5535 12:27:05.653600
5536 12:27:05.657295 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5537 12:27:05.657381
5538 12:27:05.660446 [CATrainingPosCal] consider 1 rank data
5539 12:27:05.663425 u2DelayCellTimex100 = 270/100 ps
5540 12:27:05.667144 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5541 12:27:05.670215 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5542 12:27:05.673271 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5543 12:27:05.677027 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5544 12:27:05.680076 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5545 12:27:05.683229 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5546 12:27:05.686509
5547 12:27:05.689829 CA PerBit enable=1, Macro0, CA PI delay=33
5548 12:27:05.689905
5549 12:27:05.693000 [CBTSetCACLKResult] CA Dly = 33
5550 12:27:05.693075 CS Dly: 6 (0~37)
5551 12:27:05.693143 ==
5552 12:27:05.696678 Dram Type= 6, Freq= 0, CH_1, rank 1
5553 12:27:05.699914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 12:27:05.699986 ==
5555 12:27:05.706793 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5556 12:27:05.713106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5557 12:27:05.716307 [CA 0] Center 36 (6~67) winsize 62
5558 12:27:05.719404 [CA 1] Center 37 (7~67) winsize 61
5559 12:27:05.722953 [CA 2] Center 34 (4~65) winsize 62
5560 12:27:05.726116 [CA 3] Center 33 (3~64) winsize 62
5561 12:27:05.729259 [CA 4] Center 34 (3~65) winsize 63
5562 12:27:05.732963 [CA 5] Center 33 (3~64) winsize 62
5563 12:27:05.733062
5564 12:27:05.736139 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5565 12:27:05.736237
5566 12:27:05.739288 [CATrainingPosCal] consider 2 rank data
5567 12:27:05.742898 u2DelayCellTimex100 = 270/100 ps
5568 12:27:05.745998 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 12:27:05.749151 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5570 12:27:05.752314 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 12:27:05.759059 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 12:27:05.762215 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 12:27:05.765896 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5574 12:27:05.765983
5575 12:27:05.768855 CA PerBit enable=1, Macro0, CA PI delay=33
5576 12:27:05.768937
5577 12:27:05.772575 [CBTSetCACLKResult] CA Dly = 33
5578 12:27:05.772662 CS Dly: 7 (0~39)
5579 12:27:05.772724
5580 12:27:05.775495 ----->DramcWriteLeveling(PI) begin...
5581 12:27:05.779130 ==
5582 12:27:05.779212 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 12:27:05.785440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 12:27:05.785525 ==
5585 12:27:05.788579 Write leveling (Byte 0): 27 => 27
5586 12:27:05.792506 Write leveling (Byte 1): 27 => 27
5587 12:27:05.795660 DramcWriteLeveling(PI) end<-----
5588 12:27:05.795743
5589 12:27:05.795809 ==
5590 12:27:05.798951 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 12:27:05.802163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 12:27:05.802247 ==
5593 12:27:05.805311 [Gating] SW mode calibration
5594 12:27:05.811753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5595 12:27:05.818541 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5596 12:27:05.821772 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 12:27:05.825510 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 12:27:05.828792 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 12:27:05.835085 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 12:27:05.838244 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 12:27:05.842052 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5602 12:27:05.848148 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5603 12:27:05.851858 0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (0 1) (0 0)
5604 12:27:05.855063 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5605 12:27:05.861341 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 12:27:05.865158 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 12:27:05.868306 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 12:27:05.874994 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 12:27:05.877957 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 12:27:05.881582 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5611 12:27:05.887847 0 15 28 | B1->B0 | 3535 3c3c | 0 0 | (1 1) (0 0)
5612 12:27:05.891584 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:27:05.894888 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:27:05.901238 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 12:27:05.904440 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 12:27:05.907676 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 12:27:05.914902 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 12:27:05.917841 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 12:27:05.921055 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:27:05.927780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:27:05.930915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:27:05.934116 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:27:05.941062 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:27:05.944343 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:27:05.947411 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:27:05.954248 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:27:05.957333 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:27:05.960503 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:27:05.967495 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:27:05.970617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:27:05.973873 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:27:05.980648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:27:05.983620 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:27:05.987241 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5635 12:27:05.990397 Total UI for P1: 0, mck2ui 16
5636 12:27:05.993311 best dqsien dly found for B0: ( 1, 2, 22)
5637 12:27:06.000251 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 12:27:06.003436 Total UI for P1: 0, mck2ui 16
5639 12:27:06.006709 best dqsien dly found for B1: ( 1, 2, 24)
5640 12:27:06.009907 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5641 12:27:06.013173 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5642 12:27:06.013247
5643 12:27:06.017096 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5644 12:27:06.020327 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5645 12:27:06.023401 [Gating] SW calibration Done
5646 12:27:06.023482 ==
5647 12:27:06.026718 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 12:27:06.029909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 12:27:06.029991 ==
5650 12:27:06.032973 RX Vref Scan: 0
5651 12:27:06.033054
5652 12:27:06.036688 RX Vref 0 -> 0, step: 1
5653 12:27:06.036778
5654 12:27:06.036843 RX Delay -80 -> 252, step: 8
5655 12:27:06.043025 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5656 12:27:06.046195 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5657 12:27:06.049981 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5658 12:27:06.053139 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5659 12:27:06.056563 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5660 12:27:06.059673 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5661 12:27:06.066106 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5662 12:27:06.069805 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5663 12:27:06.072997 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5664 12:27:06.076183 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5665 12:27:06.079168 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5666 12:27:06.085902 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5667 12:27:06.089556 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5668 12:27:06.092580 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5669 12:27:06.095643 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5670 12:27:06.098859 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5671 12:27:06.098941 ==
5672 12:27:06.102683 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 12:27:06.109025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 12:27:06.109109 ==
5675 12:27:06.109175 DQS Delay:
5676 12:27:06.112190 DQS0 = 0, DQS1 = 0
5677 12:27:06.112274 DQM Delay:
5678 12:27:06.112339 DQM0 = 100, DQM1 = 91
5679 12:27:06.115378 DQ Delay:
5680 12:27:06.119145 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5681 12:27:06.122414 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5682 12:27:06.125568 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =79
5683 12:27:06.128848 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5684 12:27:06.128931
5685 12:27:06.128998
5686 12:27:06.129059 ==
5687 12:27:06.131940 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 12:27:06.135535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 12:27:06.135614 ==
5690 12:27:06.135683
5691 12:27:06.135756
5692 12:27:06.138556 TX Vref Scan disable
5693 12:27:06.142311 == TX Byte 0 ==
5694 12:27:06.145457 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5695 12:27:06.148497 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5696 12:27:06.151765 == TX Byte 1 ==
5697 12:27:06.154943 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5698 12:27:06.158625 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5699 12:27:06.158709 ==
5700 12:27:06.161779 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:27:06.168081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:27:06.168166 ==
5703 12:27:06.168233
5704 12:27:06.168336
5705 12:27:06.168462 TX Vref Scan disable
5706 12:27:06.171948 == TX Byte 0 ==
5707 12:27:06.175573 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5708 12:27:06.181859 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5709 12:27:06.181943 == TX Byte 1 ==
5710 12:27:06.185530 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5711 12:27:06.192122 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5712 12:27:06.192205
5713 12:27:06.192270 [DATLAT]
5714 12:27:06.192331 Freq=933, CH1 RK0
5715 12:27:06.192390
5716 12:27:06.195101 DATLAT Default: 0xd
5717 12:27:06.195184 0, 0xFFFF, sum = 0
5718 12:27:06.198724 1, 0xFFFF, sum = 0
5719 12:27:06.201847 2, 0xFFFF, sum = 0
5720 12:27:06.201931 3, 0xFFFF, sum = 0
5721 12:27:06.204980 4, 0xFFFF, sum = 0
5722 12:27:06.205064 5, 0xFFFF, sum = 0
5723 12:27:06.208032 6, 0xFFFF, sum = 0
5724 12:27:06.208116 7, 0xFFFF, sum = 0
5725 12:27:06.211790 8, 0xFFFF, sum = 0
5726 12:27:06.211874 9, 0xFFFF, sum = 0
5727 12:27:06.214932 10, 0x0, sum = 1
5728 12:27:06.215016 11, 0x0, sum = 2
5729 12:27:06.218186 12, 0x0, sum = 3
5730 12:27:06.218269 13, 0x0, sum = 4
5731 12:27:06.221407 best_step = 11
5732 12:27:06.221489
5733 12:27:06.221555 ==
5734 12:27:06.224584 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 12:27:06.227799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:27:06.227881 ==
5737 12:27:06.227945 RX Vref Scan: 1
5738 12:27:06.231026
5739 12:27:06.231107 RX Vref 0 -> 0, step: 1
5740 12:27:06.231172
5741 12:27:06.234800 RX Delay -61 -> 252, step: 4
5742 12:27:06.234936
5743 12:27:06.237938 Set Vref, RX VrefLevel [Byte0]: 48
5744 12:27:06.241042 [Byte1]: 57
5745 12:27:06.244572
5746 12:27:06.244653 Final RX Vref Byte 0 = 48 to rank0
5747 12:27:06.247792 Final RX Vref Byte 1 = 57 to rank0
5748 12:27:06.251533 Final RX Vref Byte 0 = 48 to rank1
5749 12:27:06.254792 Final RX Vref Byte 1 = 57 to rank1==
5750 12:27:06.257949 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 12:27:06.264800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 12:27:06.264909 ==
5753 12:27:06.265014 DQS Delay:
5754 12:27:06.267895 DQS0 = 0, DQS1 = 0
5755 12:27:06.267976 DQM Delay:
5756 12:27:06.268040 DQM0 = 101, DQM1 = 94
5757 12:27:06.271158 DQ Delay:
5758 12:27:06.274371 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5759 12:27:06.277455 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5760 12:27:06.281191 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =86
5761 12:27:06.284354 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5762 12:27:06.284435
5763 12:27:06.284499
5764 12:27:06.291242 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5765 12:27:06.294241 CH1 RK0: MR19=505, MR18=1909
5766 12:27:06.300916 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5767 12:27:06.300999
5768 12:27:06.304044 ----->DramcWriteLeveling(PI) begin...
5769 12:27:06.304126 ==
5770 12:27:06.307237 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 12:27:06.311209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 12:27:06.311290 ==
5773 12:27:06.314345 Write leveling (Byte 0): 26 => 26
5774 12:27:06.317497 Write leveling (Byte 1): 28 => 28
5775 12:27:06.320699 DramcWriteLeveling(PI) end<-----
5776 12:27:06.320780
5777 12:27:06.320844 ==
5778 12:27:06.323987 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 12:27:06.330833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 12:27:06.330917 ==
5781 12:27:06.330982 [Gating] SW mode calibration
5782 12:27:06.340807 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5783 12:27:06.343949 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5784 12:27:06.350194 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5785 12:27:06.353904 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 12:27:06.356920 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 12:27:06.363890 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 12:27:06.367069 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 12:27:06.370005 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5790 12:27:06.376887 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5791 12:27:06.380236 0 14 28 | B1->B0 | 2b2b 2f2f | 1 1 | (1 0) (1 0)
5792 12:27:06.383342 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 12:27:06.390165 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 12:27:06.393331 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 12:27:06.396823 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 12:27:06.399868 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 12:27:06.406582 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 12:27:06.409615 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5799 12:27:06.413506 0 15 28 | B1->B0 | 4444 3837 | 0 1 | (0 0) (0 0)
5800 12:27:06.419932 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 12:27:06.423247 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 12:27:06.426478 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:27:06.432924 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 12:27:06.436024 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 12:27:06.439967 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 12:27:06.446183 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5807 12:27:06.449420 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:27:06.452560 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5809 12:27:06.459536 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:27:06.462686 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:27:06.466307 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:27:06.472636 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:27:06.475568 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:27:06.479412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:27:06.485446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:27:06.489133 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:27:06.492239 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:27:06.499111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:27:06.502145 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:27:06.505773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:27:06.512405 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:27:06.515648 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5823 12:27:06.518952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5824 12:27:06.522149 Total UI for P1: 0, mck2ui 16
5825 12:27:06.525370 best dqsien dly found for B1: ( 1, 2, 24)
5826 12:27:06.532229 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 12:27:06.535300 Total UI for P1: 0, mck2ui 16
5828 12:27:06.538484 best dqsien dly found for B0: ( 1, 2, 28)
5829 12:27:06.541723 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5830 12:27:06.544992 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5831 12:27:06.545080
5832 12:27:06.548154 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5833 12:27:06.551871 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5834 12:27:06.555032 [Gating] SW calibration Done
5835 12:27:06.555115 ==
5836 12:27:06.558242 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 12:27:06.561875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 12:27:06.561958 ==
5839 12:27:06.565002 RX Vref Scan: 0
5840 12:27:06.565112
5841 12:27:06.568095 RX Vref 0 -> 0, step: 1
5842 12:27:06.568199
5843 12:27:06.568294 RX Delay -80 -> 252, step: 8
5844 12:27:06.574819 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5845 12:27:06.577825 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5846 12:27:06.581503 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5847 12:27:06.584581 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5848 12:27:06.588349 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5849 12:27:06.591366 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5850 12:27:06.598218 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5851 12:27:06.601453 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5852 12:27:06.604592 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5853 12:27:06.608107 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5854 12:27:06.611287 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5855 12:27:06.617998 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5856 12:27:06.621275 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5857 12:27:06.624384 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5858 12:27:06.627712 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5859 12:27:06.630929 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5860 12:27:06.631033 ==
5861 12:27:06.634098 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 12:27:06.640972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 12:27:06.641081 ==
5864 12:27:06.641177 DQS Delay:
5865 12:27:06.644178 DQS0 = 0, DQS1 = 0
5866 12:27:06.644278 DQM Delay:
5867 12:27:06.644374 DQM0 = 100, DQM1 = 91
5868 12:27:06.647374 DQ Delay:
5869 12:27:06.650551 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5870 12:27:06.653686 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5871 12:27:06.656973 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5872 12:27:06.660792 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5873 12:27:06.660868
5874 12:27:06.660930
5875 12:27:06.661022 ==
5876 12:27:06.663855 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 12:27:06.667039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 12:27:06.667142 ==
5879 12:27:06.667236
5880 12:27:06.667323
5881 12:27:06.670309 TX Vref Scan disable
5882 12:27:06.673984 == TX Byte 0 ==
5883 12:27:06.677165 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5884 12:27:06.680415 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5885 12:27:06.684037 == TX Byte 1 ==
5886 12:27:06.687157 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5887 12:27:06.690210 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5888 12:27:06.690312 ==
5889 12:27:06.693460 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 12:27:06.696958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 12:27:06.700205 ==
5892 12:27:06.700318
5893 12:27:06.700412
5894 12:27:06.700531 TX Vref Scan disable
5895 12:27:06.703977 == TX Byte 0 ==
5896 12:27:06.707046 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 12:27:06.714194 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 12:27:06.714295 == TX Byte 1 ==
5899 12:27:06.717290 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5900 12:27:06.724047 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5901 12:27:06.724154
5902 12:27:06.724251 [DATLAT]
5903 12:27:06.724339 Freq=933, CH1 RK1
5904 12:27:06.724426
5905 12:27:06.727307 DATLAT Default: 0xb
5906 12:27:06.727403 0, 0xFFFF, sum = 0
5907 12:27:06.730435 1, 0xFFFF, sum = 0
5908 12:27:06.733629 2, 0xFFFF, sum = 0
5909 12:27:06.733730 3, 0xFFFF, sum = 0
5910 12:27:06.736826 4, 0xFFFF, sum = 0
5911 12:27:06.736929 5, 0xFFFF, sum = 0
5912 12:27:06.739973 6, 0xFFFF, sum = 0
5913 12:27:06.740073 7, 0xFFFF, sum = 0
5914 12:27:06.743834 8, 0xFFFF, sum = 0
5915 12:27:06.743944 9, 0xFFFF, sum = 0
5916 12:27:06.746958 10, 0x0, sum = 1
5917 12:27:06.747060 11, 0x0, sum = 2
5918 12:27:06.750097 12, 0x0, sum = 3
5919 12:27:06.750198 13, 0x0, sum = 4
5920 12:27:06.753260 best_step = 11
5921 12:27:06.753367
5922 12:27:06.753456 ==
5923 12:27:06.756415 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 12:27:06.759667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 12:27:06.759755 ==
5926 12:27:06.759845 RX Vref Scan: 0
5927 12:27:06.762948
5928 12:27:06.763044 RX Vref 0 -> 0, step: 1
5929 12:27:06.763141
5930 12:27:06.766084 RX Delay -61 -> 252, step: 4
5931 12:27:06.772945 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5932 12:27:06.776134 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5933 12:27:06.779941 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5934 12:27:06.783209 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
5935 12:27:06.786419 iDelay=207, Bit 4, Center 100 (7 ~ 194) 188
5936 12:27:06.792635 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5937 12:27:06.796061 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5938 12:27:06.799128 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5939 12:27:06.802670 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5940 12:27:06.805849 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5941 12:27:06.809486 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5942 12:27:06.816115 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5943 12:27:06.819374 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5944 12:27:06.822270 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5945 12:27:06.825954 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
5946 12:27:06.832363 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5947 12:27:06.832464 ==
5948 12:27:06.835510 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 12:27:06.838737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 12:27:06.838838 ==
5951 12:27:06.838931 DQS Delay:
5952 12:27:06.842518 DQS0 = 0, DQS1 = 0
5953 12:27:06.842616 DQM Delay:
5954 12:27:06.845737 DQM0 = 100, DQM1 = 94
5955 12:27:06.845837 DQ Delay:
5956 12:27:06.848869 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =96
5957 12:27:06.852170 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96
5958 12:27:06.855373 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5959 12:27:06.858532 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5960 12:27:06.858630
5961 12:27:06.858724
5962 12:27:06.868700 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5963 12:27:06.868811 CH1 RK1: MR19=504, MR18=5FF
5964 12:27:06.875793 CH1_RK1: MR19=0x504, MR18=0x5FF, DQSOSC=420, MR23=63, INC=61, DEC=40
5965 12:27:06.878330 [RxdqsGatingPostProcess] freq 933
5966 12:27:06.885275 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5967 12:27:06.888441 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 12:27:06.891566 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 12:27:06.894819 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 12:27:06.898084 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 12:27:06.901636 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 12:27:06.905120 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 12:27:06.908070 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 12:27:06.911731 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 12:27:06.911837 Pre-setting of DQS Precalculation
5976 12:27:06.917884 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5977 12:27:06.924541 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5978 12:27:06.931443 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5979 12:27:06.931556
5980 12:27:06.931649
5981 12:27:06.934902 [Calibration Summary] 1866 Mbps
5982 12:27:06.937779 CH 0, Rank 0
5983 12:27:06.937888 SW Impedance : PASS
5984 12:27:06.940995 DUTY Scan : NO K
5985 12:27:06.944193 ZQ Calibration : PASS
5986 12:27:06.944294 Jitter Meter : NO K
5987 12:27:06.947452 CBT Training : PASS
5988 12:27:06.950850 Write leveling : PASS
5989 12:27:06.950953 RX DQS gating : PASS
5990 12:27:06.954472 RX DQ/DQS(RDDQC) : PASS
5991 12:27:06.957764 TX DQ/DQS : PASS
5992 12:27:06.957870 RX DATLAT : PASS
5993 12:27:06.960903 RX DQ/DQS(Engine): PASS
5994 12:27:06.964079 TX OE : NO K
5995 12:27:06.964186 All Pass.
5996 12:27:06.964281
5997 12:27:06.964372 CH 0, Rank 1
5998 12:27:06.967379 SW Impedance : PASS
5999 12:27:06.970662 DUTY Scan : NO K
6000 12:27:06.970769 ZQ Calibration : PASS
6001 12:27:06.973849 Jitter Meter : NO K
6002 12:27:06.973949 CBT Training : PASS
6003 12:27:06.977479 Write leveling : PASS
6004 12:27:06.980720 RX DQS gating : PASS
6005 12:27:06.980827 RX DQ/DQS(RDDQC) : PASS
6006 12:27:06.983832 TX DQ/DQS : PASS
6007 12:27:06.987498 RX DATLAT : PASS
6008 12:27:06.987598 RX DQ/DQS(Engine): PASS
6009 12:27:06.990665 TX OE : NO K
6010 12:27:06.990776 All Pass.
6011 12:27:06.990869
6012 12:27:06.993745 CH 1, Rank 0
6013 12:27:06.993863 SW Impedance : PASS
6014 12:27:06.996894 DUTY Scan : NO K
6015 12:27:07.000822 ZQ Calibration : PASS
6016 12:27:07.000922 Jitter Meter : NO K
6017 12:27:07.003923 CBT Training : PASS
6018 12:27:07.006969 Write leveling : PASS
6019 12:27:07.007071 RX DQS gating : PASS
6020 12:27:07.010542 RX DQ/DQS(RDDQC) : PASS
6021 12:27:07.013864 TX DQ/DQS : PASS
6022 12:27:07.013965 RX DATLAT : PASS
6023 12:27:07.016872 RX DQ/DQS(Engine): PASS
6024 12:27:07.020259 TX OE : NO K
6025 12:27:07.020368 All Pass.
6026 12:27:07.020469
6027 12:27:07.020587 CH 1, Rank 1
6028 12:27:07.023783 SW Impedance : PASS
6029 12:27:07.026621 DUTY Scan : NO K
6030 12:27:07.026726 ZQ Calibration : PASS
6031 12:27:07.030250 Jitter Meter : NO K
6032 12:27:07.033241 CBT Training : PASS
6033 12:27:07.033345 Write leveling : PASS
6034 12:27:07.036901 RX DQS gating : PASS
6035 12:27:07.039970 RX DQ/DQS(RDDQC) : PASS
6036 12:27:07.040138 TX DQ/DQS : PASS
6037 12:27:07.043159 RX DATLAT : PASS
6038 12:27:07.043292 RX DQ/DQS(Engine): PASS
6039 12:27:07.047023 TX OE : NO K
6040 12:27:07.047125 All Pass.
6041 12:27:07.047216
6042 12:27:07.050170 DramC Write-DBI off
6043 12:27:07.053491 PER_BANK_REFRESH: Hybrid Mode
6044 12:27:07.053576 TX_TRACKING: ON
6045 12:27:07.063695 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6046 12:27:07.066713 [FAST_K] Save calibration result to emmc
6047 12:27:07.070034 dramc_set_vcore_voltage set vcore to 650000
6048 12:27:07.073385 Read voltage for 400, 6
6049 12:27:07.073468 Vio18 = 0
6050 12:27:07.076603 Vcore = 650000
6051 12:27:07.076688 Vdram = 0
6052 12:27:07.076753 Vddq = 0
6053 12:27:07.076812 Vmddr = 0
6054 12:27:07.082978 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6055 12:27:07.089907 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6056 12:27:07.089990 MEM_TYPE=3, freq_sel=20
6057 12:27:07.092879 sv_algorithm_assistance_LP4_800
6058 12:27:07.096015 ============ PULL DRAM RESETB DOWN ============
6059 12:27:07.102441 ========== PULL DRAM RESETB DOWN end =========
6060 12:27:07.106254 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6061 12:27:07.109413 ===================================
6062 12:27:07.112380 LPDDR4 DRAM CONFIGURATION
6063 12:27:07.116245 ===================================
6064 12:27:07.116365 EX_ROW_EN[0] = 0x0
6065 12:27:07.119405 EX_ROW_EN[1] = 0x0
6066 12:27:07.122538 LP4Y_EN = 0x0
6067 12:27:07.122621 WORK_FSP = 0x0
6068 12:27:07.125581 WL = 0x2
6069 12:27:07.125664 RL = 0x2
6070 12:27:07.129245 BL = 0x2
6071 12:27:07.129327 RPST = 0x0
6072 12:27:07.132100 RD_PRE = 0x0
6073 12:27:07.132188 WR_PRE = 0x1
6074 12:27:07.135529 WR_PST = 0x0
6075 12:27:07.135628 DBI_WR = 0x0
6076 12:27:07.138899 DBI_RD = 0x0
6077 12:27:07.138982 OTF = 0x1
6078 12:27:07.141882 ===================================
6079 12:27:07.145532 ===================================
6080 12:27:07.149093 ANA top config
6081 12:27:07.152275 ===================================
6082 12:27:07.152357 DLL_ASYNC_EN = 0
6083 12:27:07.155529 ALL_SLAVE_EN = 1
6084 12:27:07.158800 NEW_RANK_MODE = 1
6085 12:27:07.161931 DLL_IDLE_MODE = 1
6086 12:27:07.165119 LP45_APHY_COMB_EN = 1
6087 12:27:07.165231 TX_ODT_DIS = 1
6088 12:27:07.168322 NEW_8X_MODE = 1
6089 12:27:07.172228 ===================================
6090 12:27:07.175467 ===================================
6091 12:27:07.178618 data_rate = 800
6092 12:27:07.181892 CKR = 1
6093 12:27:07.185001 DQ_P2S_RATIO = 4
6094 12:27:07.188098 ===================================
6095 12:27:07.191852 CA_P2S_RATIO = 4
6096 12:27:07.191930 DQ_CA_OPEN = 0
6097 12:27:07.194963 DQ_SEMI_OPEN = 1
6098 12:27:07.198086 CA_SEMI_OPEN = 1
6099 12:27:07.201363 CA_FULL_RATE = 0
6100 12:27:07.205176 DQ_CKDIV4_EN = 0
6101 12:27:07.208351 CA_CKDIV4_EN = 1
6102 12:27:07.208464 CA_PREDIV_EN = 0
6103 12:27:07.211562 PH8_DLY = 0
6104 12:27:07.214772 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6105 12:27:07.217827 DQ_AAMCK_DIV = 0
6106 12:27:07.221063 CA_AAMCK_DIV = 0
6107 12:27:07.224822 CA_ADMCK_DIV = 4
6108 12:27:07.224908 DQ_TRACK_CA_EN = 0
6109 12:27:07.227971 CA_PICK = 800
6110 12:27:07.231177 CA_MCKIO = 400
6111 12:27:07.234245 MCKIO_SEMI = 400
6112 12:27:07.237919 PLL_FREQ = 3016
6113 12:27:07.240951 DQ_UI_PI_RATIO = 32
6114 12:27:07.244343 CA_UI_PI_RATIO = 32
6115 12:27:07.247736 ===================================
6116 12:27:07.250800 ===================================
6117 12:27:07.250883 memory_type:LPDDR4
6118 12:27:07.254247 GP_NUM : 10
6119 12:27:07.257877 SRAM_EN : 1
6120 12:27:07.257956 MD32_EN : 0
6121 12:27:07.261167 ===================================
6122 12:27:07.264447 [ANA_INIT] >>>>>>>>>>>>>>
6123 12:27:07.267821 <<<<<< [CONFIGURE PHASE]: ANA_TX
6124 12:27:07.270982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6125 12:27:07.274126 ===================================
6126 12:27:07.277365 data_rate = 800,PCW = 0X7400
6127 12:27:07.280595 ===================================
6128 12:27:07.283918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6129 12:27:07.287782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 12:27:07.300520 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 12:27:07.304314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6132 12:27:07.307611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6133 12:27:07.310254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6134 12:27:07.314177 [ANA_INIT] flow start
6135 12:27:07.317344 [ANA_INIT] PLL >>>>>>>>
6136 12:27:07.317470 [ANA_INIT] PLL <<<<<<<<
6137 12:27:07.320284 [ANA_INIT] MIDPI >>>>>>>>
6138 12:27:07.323983 [ANA_INIT] MIDPI <<<<<<<<
6139 12:27:07.324072 [ANA_INIT] DLL >>>>>>>>
6140 12:27:07.327222 [ANA_INIT] flow end
6141 12:27:07.330419 ============ LP4 DIFF to SE enter ============
6142 12:27:07.336590 ============ LP4 DIFF to SE exit ============
6143 12:27:07.336672 [ANA_INIT] <<<<<<<<<<<<<
6144 12:27:07.340338 [Flow] Enable top DCM control >>>>>
6145 12:27:07.343401 [Flow] Enable top DCM control <<<<<
6146 12:27:07.346393 Enable DLL master slave shuffle
6147 12:27:07.353432 ==============================================================
6148 12:27:07.353557 Gating Mode config
6149 12:27:07.359943 ==============================================================
6150 12:27:07.362941 Config description:
6151 12:27:07.372868 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6152 12:27:07.379947 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6153 12:27:07.383070 SELPH_MODE 0: By rank 1: By Phase
6154 12:27:07.389477 ==============================================================
6155 12:27:07.393332 GAT_TRACK_EN = 0
6156 12:27:07.393417 RX_GATING_MODE = 2
6157 12:27:07.396390 RX_GATING_TRACK_MODE = 2
6158 12:27:07.399707 SELPH_MODE = 1
6159 12:27:07.402778 PICG_EARLY_EN = 1
6160 12:27:07.405982 VALID_LAT_VALUE = 1
6161 12:27:07.412978 ==============================================================
6162 12:27:07.416080 Enter into Gating configuration >>>>
6163 12:27:07.419265 Exit from Gating configuration <<<<
6164 12:27:07.422477 Enter into DVFS_PRE_config >>>>>
6165 12:27:07.432389 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6166 12:27:07.436100 Exit from DVFS_PRE_config <<<<<
6167 12:27:07.439272 Enter into PICG configuration >>>>
6168 12:27:07.442441 Exit from PICG configuration <<<<
6169 12:27:07.445784 [RX_INPUT] configuration >>>>>
6170 12:27:07.448888 [RX_INPUT] configuration <<<<<
6171 12:27:07.452618 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6172 12:27:07.459113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6173 12:27:07.465466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 12:27:07.472046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 12:27:07.479040 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 12:27:07.482362 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 12:27:07.488500 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6178 12:27:07.492298 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6179 12:27:07.495407 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6180 12:27:07.498504 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6181 12:27:07.505440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6182 12:27:07.508538 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 12:27:07.511685 ===================================
6184 12:27:07.514954 LPDDR4 DRAM CONFIGURATION
6185 12:27:07.518154 ===================================
6186 12:27:07.518251 EX_ROW_EN[0] = 0x0
6187 12:27:07.521413 EX_ROW_EN[1] = 0x0
6188 12:27:07.521497 LP4Y_EN = 0x0
6189 12:27:07.525228 WORK_FSP = 0x0
6190 12:27:07.525329 WL = 0x2
6191 12:27:07.528265 RL = 0x2
6192 12:27:07.528347 BL = 0x2
6193 12:27:07.531421 RPST = 0x0
6194 12:27:07.531522 RD_PRE = 0x0
6195 12:27:07.534628 WR_PRE = 0x1
6196 12:27:07.537846 WR_PST = 0x0
6197 12:27:07.537928 DBI_WR = 0x0
6198 12:27:07.541539 DBI_RD = 0x0
6199 12:27:07.541621 OTF = 0x1
6200 12:27:07.544789 ===================================
6201 12:27:07.548017 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6202 12:27:07.551883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6203 12:27:07.558223 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 12:27:07.561265 ===================================
6205 12:27:07.565040 LPDDR4 DRAM CONFIGURATION
6206 12:27:07.567870 ===================================
6207 12:27:07.567986 EX_ROW_EN[0] = 0x10
6208 12:27:07.571395 EX_ROW_EN[1] = 0x0
6209 12:27:07.571495 LP4Y_EN = 0x0
6210 12:27:07.574447 WORK_FSP = 0x0
6211 12:27:07.574532 WL = 0x2
6212 12:27:07.578029 RL = 0x2
6213 12:27:07.578113 BL = 0x2
6214 12:27:07.581208 RPST = 0x0
6215 12:27:07.581292 RD_PRE = 0x0
6216 12:27:07.584327 WR_PRE = 0x1
6217 12:27:07.584439 WR_PST = 0x0
6218 12:27:07.588003 DBI_WR = 0x0
6219 12:27:07.591149 DBI_RD = 0x0
6220 12:27:07.591235 OTF = 0x1
6221 12:27:07.594304 ===================================
6222 12:27:07.601187 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6223 12:27:07.604456 nWR fixed to 30
6224 12:27:07.608137 [ModeRegInit_LP4] CH0 RK0
6225 12:27:07.608220 [ModeRegInit_LP4] CH0 RK1
6226 12:27:07.611325 [ModeRegInit_LP4] CH1 RK0
6227 12:27:07.614459 [ModeRegInit_LP4] CH1 RK1
6228 12:27:07.614544 match AC timing 19
6229 12:27:07.620866 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6230 12:27:07.624077 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6231 12:27:07.627275 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6232 12:27:07.634094 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6233 12:27:07.637711 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6234 12:27:07.637810 ==
6235 12:27:07.640923 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 12:27:07.643888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 12:27:07.643972 ==
6238 12:27:07.651111 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 12:27:07.657452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6240 12:27:07.660585 [CA 0] Center 36 (8~64) winsize 57
6241 12:27:07.663848 [CA 1] Center 36 (8~64) winsize 57
6242 12:27:07.667546 [CA 2] Center 36 (8~64) winsize 57
6243 12:27:07.670579 [CA 3] Center 36 (8~64) winsize 57
6244 12:27:07.674086 [CA 4] Center 36 (8~64) winsize 57
6245 12:27:07.676964 [CA 5] Center 36 (8~64) winsize 57
6246 12:27:07.677067
6247 12:27:07.680348 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6248 12:27:07.680454
6249 12:27:07.684012 [CATrainingPosCal] consider 1 rank data
6250 12:27:07.687136 u2DelayCellTimex100 = 270/100 ps
6251 12:27:07.690379 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:27:07.693573 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:27:07.696764 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:27:07.700010 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 12:27:07.703803 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:27:07.706992 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:27:07.707074
6258 12:27:07.710084 CA PerBit enable=1, Macro0, CA PI delay=36
6259 12:27:07.713280
6260 12:27:07.713368 [CBTSetCACLKResult] CA Dly = 36
6261 12:27:07.716636 CS Dly: 1 (0~32)
6262 12:27:07.716718 ==
6263 12:27:07.720235 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 12:27:07.723489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 12:27:07.723597 ==
6266 12:27:07.729996 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 12:27:07.737088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6268 12:27:07.740114 [CA 0] Center 36 (8~64) winsize 57
6269 12:27:07.743240 [CA 1] Center 36 (8~64) winsize 57
6270 12:27:07.747025 [CA 2] Center 36 (8~64) winsize 57
6271 12:27:07.747108 [CA 3] Center 36 (8~64) winsize 57
6272 12:27:07.750291 [CA 4] Center 36 (8~64) winsize 57
6273 12:27:07.753487 [CA 5] Center 36 (8~64) winsize 57
6274 12:27:07.753570
6275 12:27:07.756635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6276 12:27:07.759973
6277 12:27:07.763169 [CATrainingPosCal] consider 2 rank data
6278 12:27:07.766317 u2DelayCellTimex100 = 270/100 ps
6279 12:27:07.769434 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:27:07.773037 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:27:07.776088 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:27:07.779769 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:27:07.782807 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:27:07.786493 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:27:07.786581
6286 12:27:07.789531 CA PerBit enable=1, Macro0, CA PI delay=36
6287 12:27:07.789647
6288 12:27:07.792425 [CBTSetCACLKResult] CA Dly = 36
6289 12:27:07.796256 CS Dly: 1 (0~32)
6290 12:27:07.796388
6291 12:27:07.799196 ----->DramcWriteLeveling(PI) begin...
6292 12:27:07.799272 ==
6293 12:27:07.802293 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 12:27:07.805570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 12:27:07.805647 ==
6296 12:27:07.808837 Write leveling (Byte 0): 40 => 8
6297 12:27:07.812499 Write leveling (Byte 1): 32 => 0
6298 12:27:07.815514 DramcWriteLeveling(PI) end<-----
6299 12:27:07.815669
6300 12:27:07.815765 ==
6301 12:27:07.818715 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 12:27:07.822489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 12:27:07.822570 ==
6304 12:27:07.825482 [Gating] SW mode calibration
6305 12:27:07.832537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6306 12:27:07.838913 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6307 12:27:07.842082 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 12:27:07.848400 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 12:27:07.852299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 12:27:07.855517 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 12:27:07.861863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 12:27:07.865140 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 12:27:07.868280 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 12:27:07.875360 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 12:27:07.878576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 12:27:07.881695 Total UI for P1: 0, mck2ui 16
6317 12:27:07.885298 best dqsien dly found for B0: ( 0, 14, 24)
6318 12:27:07.888230 Total UI for P1: 0, mck2ui 16
6319 12:27:07.891920 best dqsien dly found for B1: ( 0, 14, 24)
6320 12:27:07.895011 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6321 12:27:07.897913 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6322 12:27:07.898019
6323 12:27:07.901746 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 12:27:07.904835 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 12:27:07.907937 [Gating] SW calibration Done
6326 12:27:07.908019 ==
6327 12:27:07.911638 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 12:27:07.914789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 12:27:07.917992 ==
6330 12:27:07.918103 RX Vref Scan: 0
6331 12:27:07.918202
6332 12:27:07.921055 RX Vref 0 -> 0, step: 1
6333 12:27:07.921135
6334 12:27:07.924833 RX Delay -410 -> 252, step: 16
6335 12:27:07.928015 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6336 12:27:07.931039 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6337 12:27:07.934361 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6338 12:27:07.940731 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6339 12:27:07.944435 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6340 12:27:07.947397 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6341 12:27:07.950538 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6342 12:27:07.957611 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6343 12:27:07.960804 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6344 12:27:07.963913 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6345 12:27:07.970582 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6346 12:27:07.973816 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6347 12:27:07.977050 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6348 12:27:07.980297 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6349 12:27:07.987286 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6350 12:27:07.990338 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6351 12:27:07.990413 ==
6352 12:27:07.993749 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 12:27:07.997123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 12:27:07.997198 ==
6355 12:27:07.999964 DQS Delay:
6356 12:27:08.000067 DQS0 = 43, DQS1 = 59
6357 12:27:08.003575 DQM Delay:
6358 12:27:08.003698 DQM0 = 10, DQM1 = 12
6359 12:27:08.003798 DQ Delay:
6360 12:27:08.007083 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6361 12:27:08.010019 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6362 12:27:08.013646 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6363 12:27:08.016946 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6364 12:27:08.017059
6365 12:27:08.017154
6366 12:27:08.017227 ==
6367 12:27:08.019959 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 12:27:08.026826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 12:27:08.026930 ==
6370 12:27:08.027031
6371 12:27:08.027118
6372 12:27:08.027203 TX Vref Scan disable
6373 12:27:08.030006 == TX Byte 0 ==
6374 12:27:08.033109 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 12:27:08.036352 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 12:27:08.039483 == TX Byte 1 ==
6377 12:27:08.043244 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6378 12:27:08.046424 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6379 12:27:08.049475 ==
6380 12:27:08.052695 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:27:08.056709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:27:08.056791 ==
6383 12:27:08.056855
6384 12:27:08.056915
6385 12:27:08.059670 TX Vref Scan disable
6386 12:27:08.059752 == TX Byte 0 ==
6387 12:27:08.062889 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 12:27:08.069317 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 12:27:08.069400 == TX Byte 1 ==
6390 12:27:08.073096 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 12:27:08.079456 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 12:27:08.079539
6393 12:27:08.079604 [DATLAT]
6394 12:27:08.079664 Freq=400, CH0 RK0
6395 12:27:08.079722
6396 12:27:08.082640 DATLAT Default: 0xf
6397 12:27:08.085811 0, 0xFFFF, sum = 0
6398 12:27:08.085894 1, 0xFFFF, sum = 0
6399 12:27:08.089056 2, 0xFFFF, sum = 0
6400 12:27:08.089138 3, 0xFFFF, sum = 0
6401 12:27:08.092248 4, 0xFFFF, sum = 0
6402 12:27:08.092331 5, 0xFFFF, sum = 0
6403 12:27:08.095941 6, 0xFFFF, sum = 0
6404 12:27:08.096066 7, 0xFFFF, sum = 0
6405 12:27:08.099089 8, 0xFFFF, sum = 0
6406 12:27:08.099172 9, 0xFFFF, sum = 0
6407 12:27:08.102621 10, 0xFFFF, sum = 0
6408 12:27:08.102732 11, 0xFFFF, sum = 0
6409 12:27:08.105566 12, 0xFFFF, sum = 0
6410 12:27:08.105649 13, 0x0, sum = 1
6411 12:27:08.109190 14, 0x0, sum = 2
6412 12:27:08.109273 15, 0x0, sum = 3
6413 12:27:08.112199 16, 0x0, sum = 4
6414 12:27:08.112308 best_step = 14
6415 12:27:08.112400
6416 12:27:08.112502 ==
6417 12:27:08.115584 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 12:27:08.122325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 12:27:08.122410 ==
6420 12:27:08.122475 RX Vref Scan: 1
6421 12:27:08.122535
6422 12:27:08.125448 RX Vref 0 -> 0, step: 1
6423 12:27:08.125517
6424 12:27:08.128972 RX Delay -359 -> 252, step: 8
6425 12:27:08.129055
6426 12:27:08.132195 Set Vref, RX VrefLevel [Byte0]: 61
6427 12:27:08.135403 [Byte1]: 50
6428 12:27:08.138477
6429 12:27:08.138563 Final RX Vref Byte 0 = 61 to rank0
6430 12:27:08.142237 Final RX Vref Byte 1 = 50 to rank0
6431 12:27:08.145403 Final RX Vref Byte 0 = 61 to rank1
6432 12:27:08.148495 Final RX Vref Byte 1 = 50 to rank1==
6433 12:27:08.151832 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 12:27:08.158463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 12:27:08.158552 ==
6436 12:27:08.158636 DQS Delay:
6437 12:27:08.161630 DQS0 = 48, DQS1 = 60
6438 12:27:08.161714 DQM Delay:
6439 12:27:08.161799 DQM0 = 11, DQM1 = 12
6440 12:27:08.165269 DQ Delay:
6441 12:27:08.168402 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6442 12:27:08.171638 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6443 12:27:08.171720 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6444 12:27:08.178303 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6445 12:27:08.178389
6446 12:27:08.178469
6447 12:27:08.184729 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6448 12:27:08.187875 CH0 RK0: MR19=C0C, MR18=BE82
6449 12:27:08.194823 CH0_RK0: MR19=0xC0C, MR18=0xBE82, DQSOSC=386, MR23=63, INC=396, DEC=264
6450 12:27:08.194907 ==
6451 12:27:08.197986 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 12:27:08.200933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 12:27:08.201017 ==
6454 12:27:08.204754 [Gating] SW mode calibration
6455 12:27:08.210843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6456 12:27:08.217605 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6457 12:27:08.221136 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 12:27:08.224076 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 12:27:08.230947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 12:27:08.234411 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 12:27:08.237420 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 12:27:08.244294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 12:27:08.247461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 12:27:08.250609 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 12:27:08.257354 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 12:27:08.260358 Total UI for P1: 0, mck2ui 16
6467 12:27:08.264056 best dqsien dly found for B0: ( 0, 14, 24)
6468 12:27:08.264159 Total UI for P1: 0, mck2ui 16
6469 12:27:08.270364 best dqsien dly found for B1: ( 0, 14, 24)
6470 12:27:08.273498 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6471 12:27:08.276716 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6472 12:27:08.276810
6473 12:27:08.280550 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 12:27:08.283718 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 12:27:08.287005 [Gating] SW calibration Done
6476 12:27:08.287107 ==
6477 12:27:08.290125 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 12:27:08.293301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 12:27:08.293404 ==
6480 12:27:08.296557 RX Vref Scan: 0
6481 12:27:08.296699
6482 12:27:08.300403 RX Vref 0 -> 0, step: 1
6483 12:27:08.300508
6484 12:27:08.300625 RX Delay -410 -> 252, step: 16
6485 12:27:08.307146 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6486 12:27:08.310354 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6487 12:27:08.313511 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6488 12:27:08.319781 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6489 12:27:08.323860 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6490 12:27:08.326824 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6491 12:27:08.329807 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6492 12:27:08.336695 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6493 12:27:08.339883 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6494 12:27:08.342839 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6495 12:27:08.346484 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6496 12:27:08.353230 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6497 12:27:08.356461 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6498 12:27:08.359734 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6499 12:27:08.362811 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6500 12:27:08.369589 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6501 12:27:08.369696 ==
6502 12:27:08.372662 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 12:27:08.376602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 12:27:08.376685 ==
6505 12:27:08.376757 DQS Delay:
6506 12:27:08.379845 DQS0 = 43, DQS1 = 59
6507 12:27:08.379927 DQM Delay:
6508 12:27:08.382968 DQM0 = 11, DQM1 = 16
6509 12:27:08.383050 DQ Delay:
6510 12:27:08.385998 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6511 12:27:08.389519 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6512 12:27:08.392729 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6513 12:27:08.395922 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6514 12:27:08.396023
6515 12:27:08.396131
6516 12:27:08.396247 ==
6517 12:27:08.399176 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 12:27:08.403034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 12:27:08.403117 ==
6520 12:27:08.403183
6521 12:27:08.403243
6522 12:27:08.406241 TX Vref Scan disable
6523 12:27:08.409273 == TX Byte 0 ==
6524 12:27:08.412442 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6525 12:27:08.415598 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6526 12:27:08.419457 == TX Byte 1 ==
6527 12:27:08.422479 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6528 12:27:08.425516 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6529 12:27:08.425599 ==
6530 12:27:08.429121 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:27:08.432124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:27:08.435774 ==
6533 12:27:08.435857
6534 12:27:08.435922
6535 12:27:08.435982 TX Vref Scan disable
6536 12:27:08.438882 == TX Byte 0 ==
6537 12:27:08.442432 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6538 12:27:08.445478 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6539 12:27:08.448642 == TX Byte 1 ==
6540 12:27:08.451660 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6541 12:27:08.455276 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6542 12:27:08.455379
6543 12:27:08.458531 [DATLAT]
6544 12:27:08.458633 Freq=400, CH0 RK1
6545 12:27:08.458724
6546 12:27:08.461683 DATLAT Default: 0xe
6547 12:27:08.461759 0, 0xFFFF, sum = 0
6548 12:27:08.465025 1, 0xFFFF, sum = 0
6549 12:27:08.465116 2, 0xFFFF, sum = 0
6550 12:27:08.468701 3, 0xFFFF, sum = 0
6551 12:27:08.468778 4, 0xFFFF, sum = 0
6552 12:27:08.471827 5, 0xFFFF, sum = 0
6553 12:27:08.471898 6, 0xFFFF, sum = 0
6554 12:27:08.475092 7, 0xFFFF, sum = 0
6555 12:27:08.475164 8, 0xFFFF, sum = 0
6556 12:27:08.478161 9, 0xFFFF, sum = 0
6557 12:27:08.478245 10, 0xFFFF, sum = 0
6558 12:27:08.481370 11, 0xFFFF, sum = 0
6559 12:27:08.485221 12, 0xFFFF, sum = 0
6560 12:27:08.485304 13, 0x0, sum = 1
6561 12:27:08.485370 14, 0x0, sum = 2
6562 12:27:08.488430 15, 0x0, sum = 3
6563 12:27:08.488561 16, 0x0, sum = 4
6564 12:27:08.491630 best_step = 14
6565 12:27:08.491712
6566 12:27:08.491776 ==
6567 12:27:08.494848 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 12:27:08.498036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 12:27:08.498119 ==
6570 12:27:08.501347 RX Vref Scan: 0
6571 12:27:08.501456
6572 12:27:08.501549 RX Vref 0 -> 0, step: 1
6573 12:27:08.501637
6574 12:27:08.504471 RX Delay -359 -> 252, step: 8
6575 12:27:08.512693 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6576 12:27:08.516370 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6577 12:27:08.519645 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6578 12:27:08.526085 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6579 12:27:08.529211 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6580 12:27:08.532860 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6581 12:27:08.535993 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6582 12:27:08.542750 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6583 12:27:08.545811 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6584 12:27:08.549529 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6585 12:27:08.552695 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6586 12:27:08.559018 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6587 12:27:08.562612 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6588 12:27:08.565856 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6589 12:27:08.569056 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6590 12:27:08.575301 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6591 12:27:08.575396 ==
6592 12:27:08.579007 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 12:27:08.582100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 12:27:08.582187 ==
6595 12:27:08.582253 DQS Delay:
6596 12:27:08.585338 DQS0 = 44, DQS1 = 60
6597 12:27:08.585421 DQM Delay:
6598 12:27:08.589155 DQM0 = 7, DQM1 = 15
6599 12:27:08.589239 DQ Delay:
6600 12:27:08.592297 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6601 12:27:08.595564 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6602 12:27:08.598916 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6603 12:27:08.602075 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6604 12:27:08.602178
6605 12:27:08.602270
6606 12:27:08.608501 [DQSOSCAuto] RK1, (LSB)MR18= 0xb842, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6607 12:27:08.611798 CH0 RK1: MR19=C0C, MR18=B842
6608 12:27:08.618655 CH0_RK1: MR19=0xC0C, MR18=0xB842, DQSOSC=386, MR23=63, INC=396, DEC=264
6609 12:27:08.621856 [RxdqsGatingPostProcess] freq 400
6610 12:27:08.628178 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6611 12:27:08.631914 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 12:27:08.635157 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 12:27:08.638189 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 12:27:08.641871 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 12:27:08.642023 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 12:27:08.644860 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 12:27:08.647992 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 12:27:08.651655 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 12:27:08.654817 Pre-setting of DQS Precalculation
6620 12:27:08.661114 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6621 12:27:08.661221 ==
6622 12:27:08.664736 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 12:27:08.667966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 12:27:08.668086 ==
6625 12:27:08.674451 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 12:27:08.681249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6627 12:27:08.684438 [CA 0] Center 36 (8~64) winsize 57
6628 12:27:08.687550 [CA 1] Center 36 (8~64) winsize 57
6629 12:27:08.687658 [CA 2] Center 36 (8~64) winsize 57
6630 12:27:08.690795 [CA 3] Center 36 (8~64) winsize 57
6631 12:27:08.694556 [CA 4] Center 36 (8~64) winsize 57
6632 12:27:08.697725 [CA 5] Center 36 (8~64) winsize 57
6633 12:27:08.697833
6634 12:27:08.704023 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6635 12:27:08.704131
6636 12:27:08.707273 [CATrainingPosCal] consider 1 rank data
6637 12:27:08.710412 u2DelayCellTimex100 = 270/100 ps
6638 12:27:08.713686 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:27:08.716932 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:27:08.720046 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:27:08.723881 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 12:27:08.727154 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:27:08.730302 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:27:08.730405
6645 12:27:08.733563 CA PerBit enable=1, Macro0, CA PI delay=36
6646 12:27:08.733665
6647 12:27:08.736663 [CBTSetCACLKResult] CA Dly = 36
6648 12:27:08.740324 CS Dly: 1 (0~32)
6649 12:27:08.740430 ==
6650 12:27:08.743266 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 12:27:08.746926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 12:27:08.747029 ==
6653 12:27:08.753538 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 12:27:08.759764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6655 12:27:08.763392 [CA 0] Center 36 (8~64) winsize 57
6656 12:27:08.766882 [CA 1] Center 36 (8~64) winsize 57
6657 12:27:08.766985 [CA 2] Center 36 (8~64) winsize 57
6658 12:27:08.770014 [CA 3] Center 36 (8~64) winsize 57
6659 12:27:08.773334 [CA 4] Center 36 (8~64) winsize 57
6660 12:27:08.776615 [CA 5] Center 36 (8~64) winsize 57
6661 12:27:08.776717
6662 12:27:08.779686 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6663 12:27:08.782782
6664 12:27:08.786079 [CATrainingPosCal] consider 2 rank data
6665 12:27:08.786180 u2DelayCellTimex100 = 270/100 ps
6666 12:27:08.792683 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:27:08.795858 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:27:08.799581 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:27:08.802853 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:27:08.806105 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:27:08.809296 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:27:08.809380
6673 12:27:08.812496 CA PerBit enable=1, Macro0, CA PI delay=36
6674 12:27:08.812617
6675 12:27:08.815774 [CBTSetCACLKResult] CA Dly = 36
6676 12:27:08.819652 CS Dly: 1 (0~32)
6677 12:27:08.819734
6678 12:27:08.822584 ----->DramcWriteLeveling(PI) begin...
6679 12:27:08.822668 ==
6680 12:27:08.826272 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 12:27:08.829378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 12:27:08.829460 ==
6683 12:27:08.832688 Write leveling (Byte 0): 40 => 8
6684 12:27:08.835886 Write leveling (Byte 1): 40 => 8
6685 12:27:08.838929 DramcWriteLeveling(PI) end<-----
6686 12:27:08.839015
6687 12:27:08.839082 ==
6688 12:27:08.842091 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 12:27:08.845902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 12:27:08.845977 ==
6691 12:27:08.848988 [Gating] SW mode calibration
6692 12:27:08.855627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6693 12:27:08.862445 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6694 12:27:08.865569 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6695 12:27:08.868476 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 12:27:08.875430 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 12:27:08.878763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 12:27:08.884859 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 12:27:08.888704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 12:27:08.891958 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 12:27:08.895051 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 12:27:08.901556 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 12:27:08.904757 Total UI for P1: 0, mck2ui 16
6704 12:27:08.907971 best dqsien dly found for B0: ( 0, 14, 24)
6705 12:27:08.911184 Total UI for P1: 0, mck2ui 16
6706 12:27:08.915018 best dqsien dly found for B1: ( 0, 14, 24)
6707 12:27:08.918304 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6708 12:27:08.921551 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6709 12:27:08.921625
6710 12:27:08.924889 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 12:27:08.927911 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 12:27:08.931602 [Gating] SW calibration Done
6713 12:27:08.931679 ==
6714 12:27:08.934819 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 12:27:08.937934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 12:27:08.938044 ==
6717 12:27:08.941120 RX Vref Scan: 0
6718 12:27:08.941195
6719 12:27:08.944445 RX Vref 0 -> 0, step: 1
6720 12:27:08.944567
6721 12:27:08.947634 RX Delay -410 -> 252, step: 16
6722 12:27:08.951245 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6723 12:27:08.954337 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6724 12:27:08.957433 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6725 12:27:08.964142 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6726 12:27:08.967356 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6727 12:27:08.971048 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6728 12:27:08.974105 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6729 12:27:08.980420 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6730 12:27:08.984188 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6731 12:27:08.987307 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6732 12:27:08.990866 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6733 12:27:08.997315 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6734 12:27:09.000348 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6735 12:27:09.003514 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6736 12:27:09.010483 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6737 12:27:09.013776 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6738 12:27:09.013866 ==
6739 12:27:09.017017 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 12:27:09.020183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 12:27:09.020262 ==
6742 12:27:09.023859 DQS Delay:
6743 12:27:09.023941 DQS0 = 43, DQS1 = 51
6744 12:27:09.027067 DQM Delay:
6745 12:27:09.027144 DQM0 = 12, DQM1 = 14
6746 12:27:09.027206 DQ Delay:
6747 12:27:09.030163 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6748 12:27:09.033813 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6749 12:27:09.036892 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6750 12:27:09.040024 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6751 12:27:09.040128
6752 12:27:09.040218
6753 12:27:09.040314 ==
6754 12:27:09.043303 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 12:27:09.046533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 12:27:09.050466 ==
6757 12:27:09.050548
6758 12:27:09.050611
6759 12:27:09.050670 TX Vref Scan disable
6760 12:27:09.053474 == TX Byte 0 ==
6761 12:27:09.056351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 12:27:09.060227 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 12:27:09.063256 == TX Byte 1 ==
6764 12:27:09.066986 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 12:27:09.070051 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 12:27:09.070150 ==
6767 12:27:09.073210 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:27:09.076336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:27:09.080138 ==
6770 12:27:09.080273
6771 12:27:09.080404
6772 12:27:09.080503 TX Vref Scan disable
6773 12:27:09.083306 == TX Byte 0 ==
6774 12:27:09.086440 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 12:27:09.089635 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 12:27:09.093209 == TX Byte 1 ==
6777 12:27:09.096204 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 12:27:09.099521 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 12:27:09.099605
6780 12:27:09.103126 [DATLAT]
6781 12:27:09.103304 Freq=400, CH1 RK0
6782 12:27:09.103508
6783 12:27:09.105967 DATLAT Default: 0xf
6784 12:27:09.106077 0, 0xFFFF, sum = 0
6785 12:27:09.109284 1, 0xFFFF, sum = 0
6786 12:27:09.109368 2, 0xFFFF, sum = 0
6787 12:27:09.113026 3, 0xFFFF, sum = 0
6788 12:27:09.113110 4, 0xFFFF, sum = 0
6789 12:27:09.116384 5, 0xFFFF, sum = 0
6790 12:27:09.116470 6, 0xFFFF, sum = 0
6791 12:27:09.119763 7, 0xFFFF, sum = 0
6792 12:27:09.119847 8, 0xFFFF, sum = 0
6793 12:27:09.122948 9, 0xFFFF, sum = 0
6794 12:27:09.123033 10, 0xFFFF, sum = 0
6795 12:27:09.126140 11, 0xFFFF, sum = 0
6796 12:27:09.129365 12, 0xFFFF, sum = 0
6797 12:27:09.129454 13, 0x0, sum = 1
6798 12:27:09.132497 14, 0x0, sum = 2
6799 12:27:09.132590 15, 0x0, sum = 3
6800 12:27:09.132658 16, 0x0, sum = 4
6801 12:27:09.135637 best_step = 14
6802 12:27:09.135750
6803 12:27:09.135820 ==
6804 12:27:09.139314 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 12:27:09.142257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 12:27:09.142342 ==
6807 12:27:09.145865 RX Vref Scan: 1
6808 12:27:09.145949
6809 12:27:09.149052 RX Vref 0 -> 0, step: 1
6810 12:27:09.149139
6811 12:27:09.149213 RX Delay -343 -> 252, step: 8
6812 12:27:09.149294
6813 12:27:09.152167 Set Vref, RX VrefLevel [Byte0]: 48
6814 12:27:09.155368 [Byte1]: 57
6815 12:27:09.160953
6816 12:27:09.161038 Final RX Vref Byte 0 = 48 to rank0
6817 12:27:09.163943 Final RX Vref Byte 1 = 57 to rank0
6818 12:27:09.167785 Final RX Vref Byte 0 = 48 to rank1
6819 12:27:09.170798 Final RX Vref Byte 1 = 57 to rank1==
6820 12:27:09.174443 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 12:27:09.180712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 12:27:09.180795 ==
6823 12:27:09.180862 DQS Delay:
6824 12:27:09.183961 DQS0 = 44, DQS1 = 52
6825 12:27:09.184036 DQM Delay:
6826 12:27:09.184098 DQM0 = 8, DQM1 = 10
6827 12:27:09.187671 DQ Delay:
6828 12:27:09.190909 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6829 12:27:09.191016 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6830 12:27:09.194046 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =0
6831 12:27:09.197110 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =20
6832 12:27:09.197185
6833 12:27:09.200922
6834 12:27:09.207033 [DQSOSCAuto] RK0, (LSB)MR18= 0x976d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6835 12:27:09.210664 CH1 RK0: MR19=C0C, MR18=976D
6836 12:27:09.217151 CH1_RK0: MR19=0xC0C, MR18=0x976D, DQSOSC=390, MR23=63, INC=388, DEC=258
6837 12:27:09.217231 ==
6838 12:27:09.220232 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 12:27:09.223556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 12:27:09.223657 ==
6841 12:27:09.226791 [Gating] SW mode calibration
6842 12:27:09.233802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6843 12:27:09.240186 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6844 12:27:09.243341 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6845 12:27:09.247068 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 12:27:09.253316 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 12:27:09.256402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 12:27:09.260192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 12:27:09.266496 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 12:27:09.270330 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 12:27:09.273453 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 12:27:09.280202 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 12:27:09.280288 Total UI for P1: 0, mck2ui 16
6854 12:27:09.286362 best dqsien dly found for B0: ( 0, 14, 24)
6855 12:27:09.286450 Total UI for P1: 0, mck2ui 16
6856 12:27:09.293389 best dqsien dly found for B1: ( 0, 14, 24)
6857 12:27:09.296446 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6858 12:27:09.299741 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6859 12:27:09.299825
6860 12:27:09.302887 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 12:27:09.305923 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 12:27:09.309882 [Gating] SW calibration Done
6863 12:27:09.310032 ==
6864 12:27:09.313005 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 12:27:09.316193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 12:27:09.316277 ==
6867 12:27:09.319393 RX Vref Scan: 0
6868 12:27:09.319475
6869 12:27:09.319559 RX Vref 0 -> 0, step: 1
6870 12:27:09.322560
6871 12:27:09.322645 RX Delay -410 -> 252, step: 16
6872 12:27:09.329525 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6873 12:27:09.332682 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6874 12:27:09.335773 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6875 12:27:09.339018 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6876 12:27:09.345500 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6877 12:27:09.349348 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6878 12:27:09.352387 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6879 12:27:09.355639 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6880 12:27:09.361805 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6881 12:27:09.365540 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6882 12:27:09.368730 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6883 12:27:09.375643 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6884 12:27:09.378638 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6885 12:27:09.382325 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6886 12:27:09.385365 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6887 12:27:09.392222 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6888 12:27:09.392338 ==
6889 12:27:09.395310 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 12:27:09.398478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 12:27:09.398556 ==
6892 12:27:09.398620 DQS Delay:
6893 12:27:09.401440 DQS0 = 51, DQS1 = 59
6894 12:27:09.401539 DQM Delay:
6895 12:27:09.404785 DQM0 = 19, DQM1 = 22
6896 12:27:09.404876 DQ Delay:
6897 12:27:09.408372 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6898 12:27:09.411490 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6899 12:27:09.414718 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6900 12:27:09.418324 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6901 12:27:09.418400
6902 12:27:09.418470
6903 12:27:09.418536 ==
6904 12:27:09.421483 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 12:27:09.424777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 12:27:09.427885 ==
6907 12:27:09.427974
6908 12:27:09.428040
6909 12:27:09.428106 TX Vref Scan disable
6910 12:27:09.431165 == TX Byte 0 ==
6911 12:27:09.434370 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6912 12:27:09.438188 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6913 12:27:09.441437 == TX Byte 1 ==
6914 12:27:09.444493 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6915 12:27:09.447552 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6916 12:27:09.447661 ==
6917 12:27:09.450791 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:27:09.457613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:27:09.457715 ==
6920 12:27:09.457782
6921 12:27:09.457843
6922 12:27:09.457901 TX Vref Scan disable
6923 12:27:09.461396 == TX Byte 0 ==
6924 12:27:09.464575 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6925 12:27:09.467622 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6926 12:27:09.471151 == TX Byte 1 ==
6927 12:27:09.474286 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6928 12:27:09.477387 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6929 12:27:09.477507
6930 12:27:09.481155 [DATLAT]
6931 12:27:09.481232 Freq=400, CH1 RK1
6932 12:27:09.481302
6933 12:27:09.484148 DATLAT Default: 0xe
6934 12:27:09.484261 0, 0xFFFF, sum = 0
6935 12:27:09.487811 1, 0xFFFF, sum = 0
6936 12:27:09.487890 2, 0xFFFF, sum = 0
6937 12:27:09.490919 3, 0xFFFF, sum = 0
6938 12:27:09.491027 4, 0xFFFF, sum = 0
6939 12:27:09.494078 5, 0xFFFF, sum = 0
6940 12:27:09.494206 6, 0xFFFF, sum = 0
6941 12:27:09.497258 7, 0xFFFF, sum = 0
6942 12:27:09.497350 8, 0xFFFF, sum = 0
6943 12:27:09.500429 9, 0xFFFF, sum = 0
6944 12:27:09.500564 10, 0xFFFF, sum = 0
6945 12:27:09.504255 11, 0xFFFF, sum = 0
6946 12:27:09.507558 12, 0xFFFF, sum = 0
6947 12:27:09.507674 13, 0x0, sum = 1
6948 12:27:09.510346 14, 0x0, sum = 2
6949 12:27:09.510457 15, 0x0, sum = 3
6950 12:27:09.510558 16, 0x0, sum = 4
6951 12:27:09.513667 best_step = 14
6952 12:27:09.513758
6953 12:27:09.513821 ==
6954 12:27:09.517406 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 12:27:09.520646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 12:27:09.520724 ==
6957 12:27:09.523816 RX Vref Scan: 0
6958 12:27:09.523898
6959 12:27:09.527006 RX Vref 0 -> 0, step: 1
6960 12:27:09.527088
6961 12:27:09.527152 RX Delay -359 -> 252, step: 8
6962 12:27:09.535951 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6963 12:27:09.538673 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6964 12:27:09.542449 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6965 12:27:09.548621 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6966 12:27:09.552476 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6967 12:27:09.555764 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6968 12:27:09.558894 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6969 12:27:09.565128 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6970 12:27:09.568327 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6971 12:27:09.572074 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6972 12:27:09.575170 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
6973 12:27:09.582163 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6974 12:27:09.585307 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6975 12:27:09.588348 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6976 12:27:09.591460 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6977 12:27:09.598207 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6978 12:27:09.598338 ==
6979 12:27:09.602055 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 12:27:09.605100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 12:27:09.605205 ==
6982 12:27:09.605331 DQS Delay:
6983 12:27:09.608252 DQS0 = 48, DQS1 = 56
6984 12:27:09.608336 DQM Delay:
6985 12:27:09.611493 DQM0 = 13, DQM1 = 11
6986 12:27:09.611566 DQ Delay:
6987 12:27:09.614689 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6988 12:27:09.618198 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6989 12:27:09.621444 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6990 12:27:09.624575 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6991 12:27:09.624668
6992 12:27:09.624735
6993 12:27:09.634543 [DQSOSCAuto] RK1, (LSB)MR18= 0x6856, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
6994 12:27:09.634628 CH1 RK1: MR19=C0C, MR18=6856
6995 12:27:09.641107 CH1_RK1: MR19=0xC0C, MR18=0x6856, DQSOSC=396, MR23=63, INC=376, DEC=251
6996 12:27:09.644303 [RxdqsGatingPostProcess] freq 400
6997 12:27:09.650654 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6998 12:27:09.654428 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 12:27:09.657753 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 12:27:09.660899 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 12:27:09.663881 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 12:27:09.667061 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 12:27:09.670836 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 12:27:09.674122 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 12:27:09.677305 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 12:27:09.677390 Pre-setting of DQS Precalculation
7007 12:27:09.683857 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7008 12:27:09.690643 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7009 12:27:09.696890 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7010 12:27:09.696990
7011 12:27:09.697056
7012 12:27:09.700469 [Calibration Summary] 800 Mbps
7013 12:27:09.703735 CH 0, Rank 0
7014 12:27:09.703817 SW Impedance : PASS
7015 12:27:09.706934 DUTY Scan : NO K
7016 12:27:09.710051 ZQ Calibration : PASS
7017 12:27:09.710142 Jitter Meter : NO K
7018 12:27:09.713232 CBT Training : PASS
7019 12:27:09.716997 Write leveling : PASS
7020 12:27:09.717079 RX DQS gating : PASS
7021 12:27:09.720063 RX DQ/DQS(RDDQC) : PASS
7022 12:27:09.723637 TX DQ/DQS : PASS
7023 12:27:09.723744 RX DATLAT : PASS
7024 12:27:09.726774 RX DQ/DQS(Engine): PASS
7025 12:27:09.729926 TX OE : NO K
7026 12:27:09.730098 All Pass.
7027 12:27:09.730197
7028 12:27:09.730286 CH 0, Rank 1
7029 12:27:09.733120 SW Impedance : PASS
7030 12:27:09.736361 DUTY Scan : NO K
7031 12:27:09.736472 ZQ Calibration : PASS
7032 12:27:09.739620 Jitter Meter : NO K
7033 12:27:09.739727 CBT Training : PASS
7034 12:27:09.742829 Write leveling : NO K
7035 12:27:09.746033 RX DQS gating : PASS
7036 12:27:09.746141 RX DQ/DQS(RDDQC) : PASS
7037 12:27:09.749883 TX DQ/DQS : PASS
7038 12:27:09.753060 RX DATLAT : PASS
7039 12:27:09.753132 RX DQ/DQS(Engine): PASS
7040 12:27:09.756408 TX OE : NO K
7041 12:27:09.756520 All Pass.
7042 12:27:09.756625
7043 12:27:09.759607 CH 1, Rank 0
7044 12:27:09.759702 SW Impedance : PASS
7045 12:27:09.762906 DUTY Scan : NO K
7046 12:27:09.766182 ZQ Calibration : PASS
7047 12:27:09.766261 Jitter Meter : NO K
7048 12:27:09.769100 CBT Training : PASS
7049 12:27:09.773062 Write leveling : PASS
7050 12:27:09.773152 RX DQS gating : PASS
7051 12:27:09.776270 RX DQ/DQS(RDDQC) : PASS
7052 12:27:09.779556 TX DQ/DQS : PASS
7053 12:27:09.779640 RX DATLAT : PASS
7054 12:27:09.782529 RX DQ/DQS(Engine): PASS
7055 12:27:09.786167 TX OE : NO K
7056 12:27:09.786250 All Pass.
7057 12:27:09.786316
7058 12:27:09.786375 CH 1, Rank 1
7059 12:27:09.789285 SW Impedance : PASS
7060 12:27:09.792428 DUTY Scan : NO K
7061 12:27:09.792556 ZQ Calibration : PASS
7062 12:27:09.795417 Jitter Meter : NO K
7063 12:27:09.799127 CBT Training : PASS
7064 12:27:09.799209 Write leveling : NO K
7065 12:27:09.802250 RX DQS gating : PASS
7066 12:27:09.805328 RX DQ/DQS(RDDQC) : PASS
7067 12:27:09.805410 TX DQ/DQS : PASS
7068 12:27:09.809059 RX DATLAT : PASS
7069 12:27:09.812122 RX DQ/DQS(Engine): PASS
7070 12:27:09.812205 TX OE : NO K
7071 12:27:09.815306 All Pass.
7072 12:27:09.815452
7073 12:27:09.815536 DramC Write-DBI off
7074 12:27:09.818530 PER_BANK_REFRESH: Hybrid Mode
7075 12:27:09.818676 TX_TRACKING: ON
7076 12:27:09.828258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7077 12:27:09.832111 [FAST_K] Save calibration result to emmc
7078 12:27:09.835203 dramc_set_vcore_voltage set vcore to 725000
7079 12:27:09.838303 Read voltage for 1600, 0
7080 12:27:09.838418 Vio18 = 0
7081 12:27:09.842040 Vcore = 725000
7082 12:27:09.842142 Vdram = 0
7083 12:27:09.842242 Vddq = 0
7084 12:27:09.845260 Vmddr = 0
7085 12:27:09.848407 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7086 12:27:09.854890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7087 12:27:09.855008 MEM_TYPE=3, freq_sel=13
7088 12:27:09.858123 sv_algorithm_assistance_LP4_3733
7089 12:27:09.865003 ============ PULL DRAM RESETB DOWN ============
7090 12:27:09.868131 ========== PULL DRAM RESETB DOWN end =========
7091 12:27:09.871277 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7092 12:27:09.874933 ===================================
7093 12:27:09.878246 LPDDR4 DRAM CONFIGURATION
7094 12:27:09.881515 ===================================
7095 12:27:09.881600 EX_ROW_EN[0] = 0x0
7096 12:27:09.884651 EX_ROW_EN[1] = 0x0
7097 12:27:09.888259 LP4Y_EN = 0x0
7098 12:27:09.888344 WORK_FSP = 0x1
7099 12:27:09.891293 WL = 0x5
7100 12:27:09.891379 RL = 0x5
7101 12:27:09.894417 BL = 0x2
7102 12:27:09.894502 RPST = 0x0
7103 12:27:09.898103 RD_PRE = 0x0
7104 12:27:09.898201 WR_PRE = 0x1
7105 12:27:09.901148 WR_PST = 0x1
7106 12:27:09.901232 DBI_WR = 0x0
7107 12:27:09.904946 DBI_RD = 0x0
7108 12:27:09.905030 OTF = 0x1
7109 12:27:09.907974 ===================================
7110 12:27:09.911034 ===================================
7111 12:27:09.914211 ANA top config
7112 12:27:09.918001 ===================================
7113 12:27:09.921292 DLL_ASYNC_EN = 0
7114 12:27:09.921376 ALL_SLAVE_EN = 0
7115 12:27:09.924551 NEW_RANK_MODE = 1
7116 12:27:09.927756 DLL_IDLE_MODE = 1
7117 12:27:09.930803 LP45_APHY_COMB_EN = 1
7118 12:27:09.930905 TX_ODT_DIS = 0
7119 12:27:09.934530 NEW_8X_MODE = 1
7120 12:27:09.937657 ===================================
7121 12:27:09.940743 ===================================
7122 12:27:09.944473 data_rate = 3200
7123 12:27:09.947778 CKR = 1
7124 12:27:09.950881 DQ_P2S_RATIO = 8
7125 12:27:09.954085 ===================================
7126 12:27:09.957285 CA_P2S_RATIO = 8
7127 12:27:09.957369 DQ_CA_OPEN = 0
7128 12:27:09.960441 DQ_SEMI_OPEN = 0
7129 12:27:09.964293 CA_SEMI_OPEN = 0
7130 12:27:09.967414 CA_FULL_RATE = 0
7131 12:27:09.970729 DQ_CKDIV4_EN = 0
7132 12:27:09.973807 CA_CKDIV4_EN = 0
7133 12:27:09.973912 CA_PREDIV_EN = 0
7134 12:27:09.977599 PH8_DLY = 12
7135 12:27:09.980874 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7136 12:27:09.984032 DQ_AAMCK_DIV = 4
7137 12:27:09.987139 CA_AAMCK_DIV = 4
7138 12:27:09.990908 CA_ADMCK_DIV = 4
7139 12:27:09.991007 DQ_TRACK_CA_EN = 0
7140 12:27:09.993803 CA_PICK = 1600
7141 12:27:09.997344 CA_MCKIO = 1600
7142 12:27:10.000327 MCKIO_SEMI = 0
7143 12:27:10.003888 PLL_FREQ = 3068
7144 12:27:10.006976 DQ_UI_PI_RATIO = 32
7145 12:27:10.010091 CA_UI_PI_RATIO = 0
7146 12:27:10.013793 ===================================
7147 12:27:10.017036 ===================================
7148 12:27:10.017114 memory_type:LPDDR4
7149 12:27:10.020166 GP_NUM : 10
7150 12:27:10.023783 SRAM_EN : 1
7151 12:27:10.023869 MD32_EN : 0
7152 12:27:10.027010 ===================================
7153 12:27:10.030221 [ANA_INIT] >>>>>>>>>>>>>>
7154 12:27:10.033274 <<<<<< [CONFIGURE PHASE]: ANA_TX
7155 12:27:10.037078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7156 12:27:10.040208 ===================================
7157 12:27:10.043272 data_rate = 3200,PCW = 0X7600
7158 12:27:10.046420 ===================================
7159 12:27:10.050305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7160 12:27:10.053514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 12:27:10.059750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 12:27:10.062943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7163 12:27:10.069745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7164 12:27:10.073081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7165 12:27:10.073188 [ANA_INIT] flow start
7166 12:27:10.076380 [ANA_INIT] PLL >>>>>>>>
7167 12:27:10.079492 [ANA_INIT] PLL <<<<<<<<
7168 12:27:10.079598 [ANA_INIT] MIDPI >>>>>>>>
7169 12:27:10.083181 [ANA_INIT] MIDPI <<<<<<<<
7170 12:27:10.086362 [ANA_INIT] DLL >>>>>>>>
7171 12:27:10.086463 [ANA_INIT] DLL <<<<<<<<
7172 12:27:10.089592 [ANA_INIT] flow end
7173 12:27:10.092795 ============ LP4 DIFF to SE enter ============
7174 12:27:10.099521 ============ LP4 DIFF to SE exit ============
7175 12:27:10.099603 [ANA_INIT] <<<<<<<<<<<<<
7176 12:27:10.102600 [Flow] Enable top DCM control >>>>>
7177 12:27:10.105832 [Flow] Enable top DCM control <<<<<
7178 12:27:10.109397 Enable DLL master slave shuffle
7179 12:27:10.115791 ==============================================================
7180 12:27:10.115902 Gating Mode config
7181 12:27:10.122852 ==============================================================
7182 12:27:10.125979 Config description:
7183 12:27:10.132278 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7184 12:27:10.139214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7185 12:27:10.145582 SELPH_MODE 0: By rank 1: By Phase
7186 12:27:10.151883 ==============================================================
7187 12:27:10.155725 GAT_TRACK_EN = 1
7188 12:27:10.155812 RX_GATING_MODE = 2
7189 12:27:10.158897 RX_GATING_TRACK_MODE = 2
7190 12:27:10.162184 SELPH_MODE = 1
7191 12:27:10.165253 PICG_EARLY_EN = 1
7192 12:27:10.168440 VALID_LAT_VALUE = 1
7193 12:27:10.175558 ==============================================================
7194 12:27:10.178725 Enter into Gating configuration >>>>
7195 12:27:10.181918 Exit from Gating configuration <<<<
7196 12:27:10.184972 Enter into DVFS_PRE_config >>>>>
7197 12:27:10.195378 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7198 12:27:10.198451 Exit from DVFS_PRE_config <<<<<
7199 12:27:10.201987 Enter into PICG configuration >>>>
7200 12:27:10.205142 Exit from PICG configuration <<<<
7201 12:27:10.208264 [RX_INPUT] configuration >>>>>
7202 12:27:10.211878 [RX_INPUT] configuration <<<<<
7203 12:27:10.214951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7204 12:27:10.221640 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7205 12:27:10.228437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 12:27:10.234740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 12:27:10.237872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 12:27:10.244874 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 12:27:10.248144 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7210 12:27:10.254900 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7211 12:27:10.257979 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7212 12:27:10.261267 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7213 12:27:10.264372 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7214 12:27:10.271367 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 12:27:10.274547 ===================================
7216 12:27:10.277867 LPDDR4 DRAM CONFIGURATION
7217 12:27:10.277954 ===================================
7218 12:27:10.281120 EX_ROW_EN[0] = 0x0
7219 12:27:10.284294 EX_ROW_EN[1] = 0x0
7220 12:27:10.284376 LP4Y_EN = 0x0
7221 12:27:10.287391 WORK_FSP = 0x1
7222 12:27:10.287472 WL = 0x5
7223 12:27:10.291098 RL = 0x5
7224 12:27:10.291179 BL = 0x2
7225 12:27:10.294139 RPST = 0x0
7226 12:27:10.294220 RD_PRE = 0x0
7227 12:27:10.297371 WR_PRE = 0x1
7228 12:27:10.297453 WR_PST = 0x1
7229 12:27:10.300504 DBI_WR = 0x0
7230 12:27:10.300623 DBI_RD = 0x0
7231 12:27:10.304246 OTF = 0x1
7232 12:27:10.307242 ===================================
7233 12:27:10.310953 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7234 12:27:10.313994 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7235 12:27:10.320750 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 12:27:10.323870 ===================================
7237 12:27:10.323952 LPDDR4 DRAM CONFIGURATION
7238 12:27:10.327012 ===================================
7239 12:27:10.330677 EX_ROW_EN[0] = 0x10
7240 12:27:10.333831 EX_ROW_EN[1] = 0x0
7241 12:27:10.333913 LP4Y_EN = 0x0
7242 12:27:10.337580 WORK_FSP = 0x1
7243 12:27:10.337662 WL = 0x5
7244 12:27:10.340803 RL = 0x5
7245 12:27:10.340908 BL = 0x2
7246 12:27:10.343929 RPST = 0x0
7247 12:27:10.344012 RD_PRE = 0x0
7248 12:27:10.347084 WR_PRE = 0x1
7249 12:27:10.347167 WR_PST = 0x1
7250 12:27:10.350188 DBI_WR = 0x0
7251 12:27:10.350271 DBI_RD = 0x0
7252 12:27:10.354020 OTF = 0x1
7253 12:27:10.356932 ===================================
7254 12:27:10.363925 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7255 12:27:10.364009 ==
7256 12:27:10.367161 Dram Type= 6, Freq= 0, CH_0, rank 0
7257 12:27:10.370359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7258 12:27:10.370443 ==
7259 12:27:10.373609 [Duty_Offset_Calibration]
7260 12:27:10.373692 B0:1 B1:-1 CA:0
7261 12:27:10.373758
7262 12:27:10.376723 [DutyScan_Calibration_Flow] k_type=0
7263 12:27:10.388096
7264 12:27:10.388180 ==CLK 0==
7265 12:27:10.391322 Final CLK duty delay cell = 0
7266 12:27:10.394502 [0] MAX Duty = 5125%(X100), DQS PI = 20
7267 12:27:10.397565 [0] MIN Duty = 4907%(X100), DQS PI = 6
7268 12:27:10.401430 [0] AVG Duty = 5016%(X100)
7269 12:27:10.401508
7270 12:27:10.404618 CH0 CLK Duty spec in!! Max-Min= 218%
7271 12:27:10.407785 [DutyScan_Calibration_Flow] ====Done====
7272 12:27:10.407868
7273 12:27:10.410887 [DutyScan_Calibration_Flow] k_type=1
7274 12:27:10.427050
7275 12:27:10.427138 ==DQS 0 ==
7276 12:27:10.430722 Final DQS duty delay cell = -4
7277 12:27:10.433851 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7278 12:27:10.436882 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7279 12:27:10.440082 [-4] AVG Duty = 4922%(X100)
7280 12:27:10.440154
7281 12:27:10.440217 ==DQS 1 ==
7282 12:27:10.443856 Final DQS duty delay cell = 0
7283 12:27:10.447203 [0] MAX Duty = 5156%(X100), DQS PI = 0
7284 12:27:10.450177 [0] MIN Duty = 5031%(X100), DQS PI = 18
7285 12:27:10.453324 [0] AVG Duty = 5093%(X100)
7286 12:27:10.453425
7287 12:27:10.457058 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7288 12:27:10.457142
7289 12:27:10.460294 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7290 12:27:10.463417 [DutyScan_Calibration_Flow] ====Done====
7291 12:27:10.463500
7292 12:27:10.466525 [DutyScan_Calibration_Flow] k_type=3
7293 12:27:10.484483
7294 12:27:10.484640 ==DQM 0 ==
7295 12:27:10.487839 Final DQM duty delay cell = 0
7296 12:27:10.490959 [0] MAX Duty = 5125%(X100), DQS PI = 24
7297 12:27:10.494164 [0] MIN Duty = 4876%(X100), DQS PI = 10
7298 12:27:10.497795 [0] AVG Duty = 5000%(X100)
7299 12:27:10.497901
7300 12:27:10.498000 ==DQM 1 ==
7301 12:27:10.500958 Final DQM duty delay cell = 0
7302 12:27:10.504168 [0] MAX Duty = 5000%(X100), DQS PI = 6
7303 12:27:10.507344 [0] MIN Duty = 4813%(X100), DQS PI = 20
7304 12:27:10.511119 [0] AVG Duty = 4906%(X100)
7305 12:27:10.511226
7306 12:27:10.514122 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7307 12:27:10.514231
7308 12:27:10.517176 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7309 12:27:10.521005 [DutyScan_Calibration_Flow] ====Done====
7310 12:27:10.521113
7311 12:27:10.523923 [DutyScan_Calibration_Flow] k_type=2
7312 12:27:10.540713
7313 12:27:10.540825 ==DQ 0 ==
7314 12:27:10.544459 Final DQ duty delay cell = -4
7315 12:27:10.547697 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7316 12:27:10.550859 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7317 12:27:10.553866 [-4] AVG Duty = 4953%(X100)
7318 12:27:10.553965
7319 12:27:10.554062 ==DQ 1 ==
7320 12:27:10.557480 Final DQ duty delay cell = 0
7321 12:27:10.560699 [0] MAX Duty = 5125%(X100), DQS PI = 2
7322 12:27:10.563940 [0] MIN Duty = 5000%(X100), DQS PI = 36
7323 12:27:10.567528 [0] AVG Duty = 5062%(X100)
7324 12:27:10.567627
7325 12:27:10.570823 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7326 12:27:10.570938
7327 12:27:10.573974 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7328 12:27:10.577249 [DutyScan_Calibration_Flow] ====Done====
7329 12:27:10.577332 ==
7330 12:27:10.580306 Dram Type= 6, Freq= 0, CH_1, rank 0
7331 12:27:10.584050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 12:27:10.584135 ==
7333 12:27:10.587269 [Duty_Offset_Calibration]
7334 12:27:10.587349 B0:-1 B1:1 CA:2
7335 12:27:10.587414
7336 12:27:10.590507 [DutyScan_Calibration_Flow] k_type=0
7337 12:27:10.601626
7338 12:27:10.601708 ==CLK 0==
7339 12:27:10.604960 Final CLK duty delay cell = 0
7340 12:27:10.608085 [0] MAX Duty = 5187%(X100), DQS PI = 24
7341 12:27:10.611256 [0] MIN Duty = 5000%(X100), DQS PI = 0
7342 12:27:10.614434 [0] AVG Duty = 5093%(X100)
7343 12:27:10.614515
7344 12:27:10.618079 CH1 CLK Duty spec in!! Max-Min= 187%
7345 12:27:10.621107 [DutyScan_Calibration_Flow] ====Done====
7346 12:27:10.621188
7347 12:27:10.624307 [DutyScan_Calibration_Flow] k_type=1
7348 12:27:10.640978
7349 12:27:10.641069 ==DQS 0 ==
7350 12:27:10.644191 Final DQS duty delay cell = 0
7351 12:27:10.647889 [0] MAX Duty = 5124%(X100), DQS PI = 16
7352 12:27:10.651110 [0] MIN Duty = 4907%(X100), DQS PI = 10
7353 12:27:10.654220 [0] AVG Duty = 5015%(X100)
7354 12:27:10.654320
7355 12:27:10.654452 ==DQS 1 ==
7356 12:27:10.657955 Final DQS duty delay cell = 0
7357 12:27:10.661013 [0] MAX Duty = 5093%(X100), DQS PI = 26
7358 12:27:10.664138 [0] MIN Duty = 4969%(X100), DQS PI = 56
7359 12:27:10.667489 [0] AVG Duty = 5031%(X100)
7360 12:27:10.667592
7361 12:27:10.671174 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7362 12:27:10.671296
7363 12:27:10.674192 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7364 12:27:10.677268 [DutyScan_Calibration_Flow] ====Done====
7365 12:27:10.677348
7366 12:27:10.680569 [DutyScan_Calibration_Flow] k_type=3
7367 12:27:10.697695
7368 12:27:10.697787 ==DQM 0 ==
7369 12:27:10.701549 Final DQM duty delay cell = 0
7370 12:27:10.704662 [0] MAX Duty = 5218%(X100), DQS PI = 18
7371 12:27:10.708285 [0] MIN Duty = 5031%(X100), DQS PI = 8
7372 12:27:10.708426 [0] AVG Duty = 5124%(X100)
7373 12:27:10.711501
7374 12:27:10.711584 ==DQM 1 ==
7375 12:27:10.714658 Final DQM duty delay cell = 0
7376 12:27:10.717796 [0] MAX Duty = 5156%(X100), DQS PI = 4
7377 12:27:10.721515 [0] MIN Duty = 4969%(X100), DQS PI = 28
7378 12:27:10.721609 [0] AVG Duty = 5062%(X100)
7379 12:27:10.724551
7380 12:27:10.727754 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7381 12:27:10.727832
7382 12:27:10.730954 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7383 12:27:10.734422 [DutyScan_Calibration_Flow] ====Done====
7384 12:27:10.734529
7385 12:27:10.737475 [DutyScan_Calibration_Flow] k_type=2
7386 12:27:10.754911
7387 12:27:10.755003 ==DQ 0 ==
7388 12:27:10.758117 Final DQ duty delay cell = 0
7389 12:27:10.761297 [0] MAX Duty = 5156%(X100), DQS PI = 30
7390 12:27:10.764901 [0] MIN Duty = 4906%(X100), DQS PI = 8
7391 12:27:10.764988 [0] AVG Duty = 5031%(X100)
7392 12:27:10.768162
7393 12:27:10.768275 ==DQ 1 ==
7394 12:27:10.771325 Final DQ duty delay cell = 0
7395 12:27:10.774557 [0] MAX Duty = 5156%(X100), DQS PI = 10
7396 12:27:10.778201 [0] MIN Duty = 4969%(X100), DQS PI = 56
7397 12:27:10.778316 [0] AVG Duty = 5062%(X100)
7398 12:27:10.781398
7399 12:27:10.784566 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7400 12:27:10.784671
7401 12:27:10.787771 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7402 12:27:10.790842 [DutyScan_Calibration_Flow] ====Done====
7403 12:27:10.794661 nWR fixed to 30
7404 12:27:10.794761 [ModeRegInit_LP4] CH0 RK0
7405 12:27:10.797879 [ModeRegInit_LP4] CH0 RK1
7406 12:27:10.801084 [ModeRegInit_LP4] CH1 RK0
7407 12:27:10.804264 [ModeRegInit_LP4] CH1 RK1
7408 12:27:10.804375 match AC timing 5
7409 12:27:10.811155 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7410 12:27:10.814259 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7411 12:27:10.817404 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7412 12:27:10.824279 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7413 12:27:10.827477 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7414 12:27:10.827564 [MiockJmeterHQA]
7415 12:27:10.827630
7416 12:27:10.831075 [DramcMiockJmeter] u1RxGatingPI = 0
7417 12:27:10.834152 0 : 4366, 4140
7418 12:27:10.834237 4 : 4255, 4027
7419 12:27:10.837735 8 : 4370, 4143
7420 12:27:10.837846 12 : 4253, 4026
7421 12:27:10.837944 16 : 4255, 4029
7422 12:27:10.840892 20 : 4363, 4137
7423 12:27:10.840977 24 : 4255, 4029
7424 12:27:10.844021 28 : 4255, 4029
7425 12:27:10.844112 32 : 4253, 4027
7426 12:27:10.847168 36 : 4252, 4027
7427 12:27:10.847253 40 : 4368, 4140
7428 12:27:10.850705 44 : 4252, 4027
7429 12:27:10.850789 48 : 4253, 4027
7430 12:27:10.850856 52 : 4254, 4029
7431 12:27:10.853921 56 : 4255, 4029
7432 12:27:10.854005 60 : 4255, 4030
7433 12:27:10.856995 64 : 4365, 4140
7434 12:27:10.857083 68 : 4363, 4137
7435 12:27:10.860784 72 : 4363, 4140
7436 12:27:10.860870 76 : 4250, 4027
7437 12:27:10.863968 80 : 4252, 4029
7438 12:27:10.864099 84 : 4250, 4027
7439 12:27:10.864199 88 : 4250, 4026
7440 12:27:10.867068 92 : 4365, 431
7441 12:27:10.867182 96 : 4252, 0
7442 12:27:10.870261 100 : 4361, 0
7443 12:27:10.870372 104 : 4250, 0
7444 12:27:10.870491 108 : 4360, 0
7445 12:27:10.873473 112 : 4250, 0
7446 12:27:10.873585 116 : 4250, 0
7447 12:27:10.876804 120 : 4360, 0
7448 12:27:10.876892 124 : 4250, 0
7449 12:27:10.876961 128 : 4250, 0
7450 12:27:10.880395 132 : 4255, 0
7451 12:27:10.880481 136 : 4255, 0
7452 12:27:10.883514 140 : 4250, 0
7453 12:27:10.883600 144 : 4250, 0
7454 12:27:10.883668 148 : 4250, 0
7455 12:27:10.887325 152 : 4361, 0
7456 12:27:10.887408 156 : 4361, 0
7457 12:27:10.887475 160 : 4255, 0
7458 12:27:10.890444 164 : 4250, 0
7459 12:27:10.890526 168 : 4361, 0
7460 12:27:10.893624 172 : 4250, 0
7461 12:27:10.893733 176 : 4250, 0
7462 12:27:10.893829 180 : 4250, 0
7463 12:27:10.896758 184 : 4250, 0
7464 12:27:10.896872 188 : 4255, 0
7465 12:27:10.900530 192 : 4361, 0
7466 12:27:10.900644 196 : 4250, 0
7467 12:27:10.900765 200 : 4250, 0
7468 12:27:10.903768 204 : 4361, 0
7469 12:27:10.903858 208 : 4250, 0
7470 12:27:10.907168 212 : 4250, 0
7471 12:27:10.907250 216 : 4255, 0
7472 12:27:10.907353 220 : 4250, 0
7473 12:27:10.910372 224 : 4360, 347
7474 12:27:10.910453 228 : 4250, 3511
7475 12:27:10.913446 232 : 4250, 4027
7476 12:27:10.913530 236 : 4253, 4030
7477 12:27:10.916592 240 : 4250, 4027
7478 12:27:10.916672 244 : 4253, 4029
7479 12:27:10.919708 248 : 4250, 4026
7480 12:27:10.919824 252 : 4250, 4027
7481 12:27:10.923405 256 : 4250, 4027
7482 12:27:10.923520 260 : 4363, 4140
7483 12:27:10.926549 264 : 4363, 4140
7484 12:27:10.926639 268 : 4250, 4027
7485 12:27:10.926719 272 : 4360, 4138
7486 12:27:10.929642 276 : 4250, 4027
7487 12:27:10.929721 280 : 4249, 4027
7488 12:27:10.933314 284 : 4253, 4029
7489 12:27:10.933410 288 : 4363, 4140
7490 12:27:10.936438 292 : 4250, 4027
7491 12:27:10.936531 296 : 4250, 4027
7492 12:27:10.939649 300 : 4361, 4137
7493 12:27:10.939734 304 : 4250, 4026
7494 12:27:10.943281 308 : 4252, 4029
7495 12:27:10.943383 312 : 4249, 4027
7496 12:27:10.946341 316 : 4360, 4137
7497 12:27:10.946426 320 : 4252, 4030
7498 12:27:10.949441 324 : 4255, 4029
7499 12:27:10.949526 328 : 4250, 4027
7500 12:27:10.953234 332 : 4250, 4027
7501 12:27:10.953319 336 : 4250, 3593
7502 12:27:10.953386 340 : 4363, 1798
7503 12:27:10.953448
7504 12:27:10.956266 MIOCK jitter meter ch=0
7505 12:27:10.956375
7506 12:27:10.959452 1T = (340-92) = 248 dly cells
7507 12:27:10.966353 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7508 12:27:10.966446 ==
7509 12:27:10.969593 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 12:27:10.972838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 12:27:10.972924 ==
7512 12:27:10.979100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 12:27:10.982786 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 12:27:10.985938 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 12:27:10.992351 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 12:27:11.001913 [CA 0] Center 43 (13~74) winsize 62
7517 12:27:11.005020 [CA 1] Center 43 (13~74) winsize 62
7518 12:27:11.008763 [CA 2] Center 39 (10~69) winsize 60
7519 12:27:11.011941 [CA 3] Center 39 (9~69) winsize 61
7520 12:27:11.015151 [CA 4] Center 37 (8~66) winsize 59
7521 12:27:11.018118 [CA 5] Center 36 (7~66) winsize 60
7522 12:27:11.018201
7523 12:27:11.021989 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 12:27:11.022072
7525 12:27:11.028253 [CATrainingPosCal] consider 1 rank data
7526 12:27:11.028370 u2DelayCellTimex100 = 262/100 ps
7527 12:27:11.035027 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7528 12:27:11.038152 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7529 12:27:11.041191 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7530 12:27:11.044903 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7531 12:27:11.048083 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7532 12:27:11.051091 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7533 12:27:11.051176
7534 12:27:11.054343 CA PerBit enable=1, Macro0, CA PI delay=36
7535 12:27:11.054427
7536 12:27:11.057973 [CBTSetCACLKResult] CA Dly = 36
7537 12:27:11.061108 CS Dly: 11 (0~42)
7538 12:27:11.064274 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 12:27:11.067494 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 12:27:11.067578 ==
7541 12:27:11.071250 Dram Type= 6, Freq= 0, CH_0, rank 1
7542 12:27:11.077443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 12:27:11.077558 ==
7544 12:27:11.081355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 12:27:11.087722 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 12:27:11.090738 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 12:27:11.097670 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 12:27:11.105977 [CA 0] Center 42 (12~73) winsize 62
7549 12:27:11.109183 [CA 1] Center 43 (13~73) winsize 61
7550 12:27:11.112385 [CA 2] Center 37 (8~67) winsize 60
7551 12:27:11.115562 [CA 3] Center 37 (7~67) winsize 61
7552 12:27:11.118774 [CA 4] Center 35 (6~65) winsize 60
7553 12:27:11.122433 [CA 5] Center 35 (5~65) winsize 61
7554 12:27:11.122517
7555 12:27:11.125430 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7556 12:27:11.125539
7557 12:27:11.128637 [CATrainingPosCal] consider 2 rank data
7558 12:27:11.131791 u2DelayCellTimex100 = 262/100 ps
7559 12:27:11.135026 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7560 12:27:11.142193 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7561 12:27:11.145527 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7562 12:27:11.148570 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7563 12:27:11.151550 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7564 12:27:11.155366 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7565 12:27:11.155449
7566 12:27:11.158625 CA PerBit enable=1, Macro0, CA PI delay=36
7567 12:27:11.158708
7568 12:27:11.161608 [CBTSetCACLKResult] CA Dly = 36
7569 12:27:11.164751 CS Dly: 11 (0~43)
7570 12:27:11.168533 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 12:27:11.171803 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 12:27:11.171887
7573 12:27:11.174871 ----->DramcWriteLeveling(PI) begin...
7574 12:27:11.174956 ==
7575 12:27:11.178037 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 12:27:11.184712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 12:27:11.184796 ==
7578 12:27:11.187896 Write leveling (Byte 0): 38 => 38
7579 12:27:11.191067 Write leveling (Byte 1): 25 => 25
7580 12:27:11.191148 DramcWriteLeveling(PI) end<-----
7581 12:27:11.194818
7582 12:27:11.194900 ==
7583 12:27:11.197920 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 12:27:11.201139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 12:27:11.201221 ==
7586 12:27:11.204375 [Gating] SW mode calibration
7587 12:27:11.211221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7588 12:27:11.214577 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7589 12:27:11.220947 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 12:27:11.224729 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 12:27:11.227832 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 12:27:11.234308 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7593 12:27:11.237487 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7594 12:27:11.241068 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7595 12:27:11.247320 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7596 12:27:11.250886 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 12:27:11.253909 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 12:27:11.260820 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 12:27:11.264023 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 12:27:11.267490 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7601 12:27:11.273689 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7602 12:27:11.277417 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7603 12:27:11.280724 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7604 12:27:11.287336 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 12:27:11.290372 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 12:27:11.293568 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 12:27:11.300547 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 12:27:11.303717 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7609 12:27:11.307010 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7610 12:27:11.313167 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7611 12:27:11.316410 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7612 12:27:11.320224 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 12:27:11.326736 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 12:27:11.329857 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 12:27:11.332947 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 12:27:11.339826 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 12:27:11.342892 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 12:27:11.346529 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 12:27:11.353477 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:27:11.356603 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:27:11.359593 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:27:11.366518 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:27:11.369601 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:27:11.372729 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:27:11.379521 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:27:11.382731 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:27:11.386502 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:27:11.392471 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:27:11.396317 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:27:11.399618 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 12:27:11.405830 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 12:27:11.409111 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 12:27:11.412836 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7634 12:27:11.416115 Total UI for P1: 0, mck2ui 16
7635 12:27:11.419168 best dqsien dly found for B0: ( 1, 9, 10)
7636 12:27:11.426084 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 12:27:11.429309 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 12:27:11.432462 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 12:27:11.435517 Total UI for P1: 0, mck2ui 16
7640 12:27:11.438674 best dqsien dly found for B1: ( 1, 9, 22)
7641 12:27:11.442549 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7642 12:27:11.445742 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7643 12:27:11.445863
7644 12:27:11.452493 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7645 12:27:11.455738 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7646 12:27:11.458881 [Gating] SW calibration Done
7647 12:27:11.458989 ==
7648 12:27:11.461981 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 12:27:11.465596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 12:27:11.465680 ==
7651 12:27:11.465784 RX Vref Scan: 0
7652 12:27:11.465885
7653 12:27:11.468693 RX Vref 0 -> 0, step: 1
7654 12:27:11.468775
7655 12:27:11.471804 RX Delay 0 -> 252, step: 8
7656 12:27:11.475506 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7657 12:27:11.478730 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7658 12:27:11.481812 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7659 12:27:11.488964 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7660 12:27:11.492090 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7661 12:27:11.495239 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7662 12:27:11.498251 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7663 12:27:11.505123 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7664 12:27:11.508315 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7665 12:27:11.511494 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7666 12:27:11.514703 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7667 12:27:11.517784 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7668 12:27:11.524488 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7669 12:27:11.527796 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7670 12:27:11.531593 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7671 12:27:11.534188 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7672 12:27:11.534299 ==
7673 12:27:11.537848 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 12:27:11.544245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 12:27:11.544331 ==
7676 12:27:11.544421 DQS Delay:
7677 12:27:11.547534 DQS0 = 0, DQS1 = 0
7678 12:27:11.547617 DQM Delay:
7679 12:27:11.551241 DQM0 = 137, DQM1 = 126
7680 12:27:11.551318 DQ Delay:
7681 12:27:11.554239 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7682 12:27:11.557334 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =147
7683 12:27:11.561069 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7684 12:27:11.564218 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7685 12:27:11.564291
7686 12:27:11.564353
7687 12:27:11.564410 ==
7688 12:27:11.567798 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 12:27:11.573995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 12:27:11.574120 ==
7691 12:27:11.574224
7692 12:27:11.574317
7693 12:27:11.574412 TX Vref Scan disable
7694 12:27:11.577696 == TX Byte 0 ==
7695 12:27:11.580811 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7696 12:27:11.587618 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7697 12:27:11.587713 == TX Byte 1 ==
7698 12:27:11.590709 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7699 12:27:11.597424 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7700 12:27:11.597511 ==
7701 12:27:11.601078 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 12:27:11.604209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 12:27:11.604320 ==
7704 12:27:11.617965
7705 12:27:11.621070 TX Vref early break, caculate TX vref
7706 12:27:11.624869 TX Vref=16, minBit 4, minWin=22, winSum=370
7707 12:27:11.627889 TX Vref=18, minBit 1, minWin=23, winSum=379
7708 12:27:11.631061 TX Vref=20, minBit 3, minWin=24, winSum=394
7709 12:27:11.634210 TX Vref=22, minBit 6, minWin=24, winSum=399
7710 12:27:11.637405 TX Vref=24, minBit 4, minWin=25, winSum=412
7711 12:27:11.644238 TX Vref=26, minBit 5, minWin=25, winSum=417
7712 12:27:11.647404 TX Vref=28, minBit 4, minWin=25, winSum=418
7713 12:27:11.651179 TX Vref=30, minBit 4, minWin=24, winSum=408
7714 12:27:11.654273 TX Vref=32, minBit 5, minWin=23, winSum=400
7715 12:27:11.657395 TX Vref=34, minBit 0, minWin=24, winSum=395
7716 12:27:11.664283 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
7717 12:27:11.664369
7718 12:27:11.667408 Final TX Range 0 Vref 28
7719 12:27:11.667493
7720 12:27:11.667559 ==
7721 12:27:11.670427 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 12:27:11.674128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 12:27:11.674247 ==
7724 12:27:11.674350
7725 12:27:11.674416
7726 12:27:11.677320 TX Vref Scan disable
7727 12:27:11.683642 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7728 12:27:11.683727 == TX Byte 0 ==
7729 12:27:11.687297 u2DelayCellOfst[0]=14 cells (4 PI)
7730 12:27:11.690358 u2DelayCellOfst[1]=18 cells (5 PI)
7731 12:27:11.693423 u2DelayCellOfst[2]=14 cells (4 PI)
7732 12:27:11.697197 u2DelayCellOfst[3]=14 cells (4 PI)
7733 12:27:11.700303 u2DelayCellOfst[4]=11 cells (3 PI)
7734 12:27:11.703436 u2DelayCellOfst[5]=0 cells (0 PI)
7735 12:27:11.706544 u2DelayCellOfst[6]=22 cells (6 PI)
7736 12:27:11.709847 u2DelayCellOfst[7]=22 cells (6 PI)
7737 12:27:11.713594 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7738 12:27:11.716770 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7739 12:27:11.719975 == TX Byte 1 ==
7740 12:27:11.723850 u2DelayCellOfst[8]=0 cells (0 PI)
7741 12:27:11.726986 u2DelayCellOfst[9]=3 cells (1 PI)
7742 12:27:11.730190 u2DelayCellOfst[10]=11 cells (3 PI)
7743 12:27:11.733341 u2DelayCellOfst[11]=0 cells (0 PI)
7744 12:27:11.733423 u2DelayCellOfst[12]=14 cells (4 PI)
7745 12:27:11.736680 u2DelayCellOfst[13]=14 cells (4 PI)
7746 12:27:11.739815 u2DelayCellOfst[14]=14 cells (4 PI)
7747 12:27:11.743062 u2DelayCellOfst[15]=11 cells (3 PI)
7748 12:27:11.749901 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7749 12:27:11.753235 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7750 12:27:11.753318 DramC Write-DBI on
7751 12:27:11.756426 ==
7752 12:27:11.759583 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 12:27:11.763244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 12:27:11.763326 ==
7755 12:27:11.763391
7756 12:27:11.763451
7757 12:27:11.766478 TX Vref Scan disable
7758 12:27:11.766560 == TX Byte 0 ==
7759 12:27:11.772744 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7760 12:27:11.772841 == TX Byte 1 ==
7761 12:27:11.776308 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7762 12:27:11.779350 DramC Write-DBI off
7763 12:27:11.779474
7764 12:27:11.779574 [DATLAT]
7765 12:27:11.783054 Freq=1600, CH0 RK0
7766 12:27:11.783133
7767 12:27:11.783198 DATLAT Default: 0xf
7768 12:27:11.786150 0, 0xFFFF, sum = 0
7769 12:27:11.786268 1, 0xFFFF, sum = 0
7770 12:27:11.789369 2, 0xFFFF, sum = 0
7771 12:27:11.789487 3, 0xFFFF, sum = 0
7772 12:27:11.792481 4, 0xFFFF, sum = 0
7773 12:27:11.796175 5, 0xFFFF, sum = 0
7774 12:27:11.796271 6, 0xFFFF, sum = 0
7775 12:27:11.799265 7, 0xFFFF, sum = 0
7776 12:27:11.799341 8, 0xFFFF, sum = 0
7777 12:27:11.802333 9, 0xFFFF, sum = 0
7778 12:27:11.802454 10, 0xFFFF, sum = 0
7779 12:27:11.806204 11, 0xFFFF, sum = 0
7780 12:27:11.806306 12, 0xFFFF, sum = 0
7781 12:27:11.809112 13, 0xFFFF, sum = 0
7782 12:27:11.809206 14, 0x0, sum = 1
7783 12:27:11.812193 15, 0x0, sum = 2
7784 12:27:11.812284 16, 0x0, sum = 3
7785 12:27:11.815541 17, 0x0, sum = 4
7786 12:27:11.815619 best_step = 15
7787 12:27:11.815688
7788 12:27:11.815752 ==
7789 12:27:11.819263 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 12:27:11.825520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 12:27:11.825601 ==
7792 12:27:11.825666 RX Vref Scan: 1
7793 12:27:11.825735
7794 12:27:11.828820 Set Vref Range= 24 -> 127
7795 12:27:11.828898
7796 12:27:11.832444 RX Vref 24 -> 127, step: 1
7797 12:27:11.832575
7798 12:27:11.832646 RX Delay 11 -> 252, step: 4
7799 12:27:11.832707
7800 12:27:11.835660 Set Vref, RX VrefLevel [Byte0]: 24
7801 12:27:11.838849 [Byte1]: 24
7802 12:27:11.842658
7803 12:27:11.842743 Set Vref, RX VrefLevel [Byte0]: 25
7804 12:27:11.845973 [Byte1]: 25
7805 12:27:11.850287
7806 12:27:11.850371 Set Vref, RX VrefLevel [Byte0]: 26
7807 12:27:11.854104 [Byte1]: 26
7808 12:27:11.857967
7809 12:27:11.858051 Set Vref, RX VrefLevel [Byte0]: 27
7810 12:27:11.861262 [Byte1]: 27
7811 12:27:11.865519
7812 12:27:11.865603 Set Vref, RX VrefLevel [Byte0]: 28
7813 12:27:11.869161 [Byte1]: 28
7814 12:27:11.873401
7815 12:27:11.873487 Set Vref, RX VrefLevel [Byte0]: 29
7816 12:27:11.876450 [Byte1]: 29
7817 12:27:11.880732
7818 12:27:11.880831 Set Vref, RX VrefLevel [Byte0]: 30
7819 12:27:11.884525 [Byte1]: 30
7820 12:27:11.888265
7821 12:27:11.888375 Set Vref, RX VrefLevel [Byte0]: 31
7822 12:27:11.892094 [Byte1]: 31
7823 12:27:11.895843
7824 12:27:11.895919 Set Vref, RX VrefLevel [Byte0]: 32
7825 12:27:11.899538 [Byte1]: 32
7826 12:27:11.903990
7827 12:27:11.904099 Set Vref, RX VrefLevel [Byte0]: 33
7828 12:27:11.907156 [Byte1]: 33
7829 12:27:11.911527
7830 12:27:11.911639 Set Vref, RX VrefLevel [Byte0]: 34
7831 12:27:11.914605 [Byte1]: 34
7832 12:27:11.919073
7833 12:27:11.919184 Set Vref, RX VrefLevel [Byte0]: 35
7834 12:27:11.922307 [Byte1]: 35
7835 12:27:11.926610
7836 12:27:11.926724 Set Vref, RX VrefLevel [Byte0]: 36
7837 12:27:11.929761 [Byte1]: 36
7838 12:27:11.934254
7839 12:27:11.934360 Set Vref, RX VrefLevel [Byte0]: 37
7840 12:27:11.937512 [Byte1]: 37
7841 12:27:11.941872
7842 12:27:11.941986 Set Vref, RX VrefLevel [Byte0]: 38
7843 12:27:11.948118 [Byte1]: 38
7844 12:27:11.948225
7845 12:27:11.951920 Set Vref, RX VrefLevel [Byte0]: 39
7846 12:27:11.954878 [Byte1]: 39
7847 12:27:11.954981
7848 12:27:11.958095 Set Vref, RX VrefLevel [Byte0]: 40
7849 12:27:11.961765 [Byte1]: 40
7850 12:27:11.961871
7851 12:27:11.964949 Set Vref, RX VrefLevel [Byte0]: 41
7852 12:27:11.968147 [Byte1]: 41
7853 12:27:11.972359
7854 12:27:11.972464 Set Vref, RX VrefLevel [Byte0]: 42
7855 12:27:11.975537 [Byte1]: 42
7856 12:27:11.979903
7857 12:27:11.979991 Set Vref, RX VrefLevel [Byte0]: 43
7858 12:27:11.982865 [Byte1]: 43
7859 12:27:11.987687
7860 12:27:11.987794 Set Vref, RX VrefLevel [Byte0]: 44
7861 12:27:11.990886 [Byte1]: 44
7862 12:27:11.995187
7863 12:27:11.995275 Set Vref, RX VrefLevel [Byte0]: 45
7864 12:27:11.998348 [Byte1]: 45
7865 12:27:12.002559
7866 12:27:12.002671 Set Vref, RX VrefLevel [Byte0]: 46
7867 12:27:12.006336 [Byte1]: 46
7868 12:27:12.010158
7869 12:27:12.010262 Set Vref, RX VrefLevel [Byte0]: 47
7870 12:27:12.013898 [Byte1]: 47
7871 12:27:12.018275
7872 12:27:12.018361 Set Vref, RX VrefLevel [Byte0]: 48
7873 12:27:12.021527 [Byte1]: 48
7874 12:27:12.025902
7875 12:27:12.026025 Set Vref, RX VrefLevel [Byte0]: 49
7876 12:27:12.028985 [Byte1]: 49
7877 12:27:12.033363
7878 12:27:12.033486 Set Vref, RX VrefLevel [Byte0]: 50
7879 12:27:12.036467 [Byte1]: 50
7880 12:27:12.040894
7881 12:27:12.040977 Set Vref, RX VrefLevel [Byte0]: 51
7882 12:27:12.043970 [Byte1]: 51
7883 12:27:12.048430
7884 12:27:12.048567 Set Vref, RX VrefLevel [Byte0]: 52
7885 12:27:12.051741 [Byte1]: 52
7886 12:27:12.056072
7887 12:27:12.056254 Set Vref, RX VrefLevel [Byte0]: 53
7888 12:27:12.059044 [Byte1]: 53
7889 12:27:12.063492
7890 12:27:12.063596 Set Vref, RX VrefLevel [Byte0]: 54
7891 12:27:12.066778 [Byte1]: 54
7892 12:27:12.071184
7893 12:27:12.071288 Set Vref, RX VrefLevel [Byte0]: 55
7894 12:27:12.074290 [Byte1]: 55
7895 12:27:12.079224
7896 12:27:12.079335 Set Vref, RX VrefLevel [Byte0]: 56
7897 12:27:12.082340 [Byte1]: 56
7898 12:27:12.086604
7899 12:27:12.086707 Set Vref, RX VrefLevel [Byte0]: 57
7900 12:27:12.089675 [Byte1]: 57
7901 12:27:12.094381
7902 12:27:12.094483 Set Vref, RX VrefLevel [Byte0]: 58
7903 12:27:12.097543 [Byte1]: 58
7904 12:27:12.101940
7905 12:27:12.102056 Set Vref, RX VrefLevel [Byte0]: 59
7906 12:27:12.105173 [Byte1]: 59
7907 12:27:12.109485
7908 12:27:12.109590 Set Vref, RX VrefLevel [Byte0]: 60
7909 12:27:12.112577 [Byte1]: 60
7910 12:27:12.117008
7911 12:27:12.117118 Set Vref, RX VrefLevel [Byte0]: 61
7912 12:27:12.120142 [Byte1]: 61
7913 12:27:12.124609
7914 12:27:12.124704 Set Vref, RX VrefLevel [Byte0]: 62
7915 12:27:12.127806 [Byte1]: 62
7916 12:27:12.132240
7917 12:27:12.132346 Set Vref, RX VrefLevel [Byte0]: 63
7918 12:27:12.135392 [Byte1]: 63
7919 12:27:12.139868
7920 12:27:12.139975 Set Vref, RX VrefLevel [Byte0]: 64
7921 12:27:12.146190 [Byte1]: 64
7922 12:27:12.146295
7923 12:27:12.149831 Set Vref, RX VrefLevel [Byte0]: 65
7924 12:27:12.153005 [Byte1]: 65
7925 12:27:12.153110
7926 12:27:12.156058 Set Vref, RX VrefLevel [Byte0]: 66
7927 12:27:12.159298 [Byte1]: 66
7928 12:27:12.159400
7929 12:27:12.162906 Set Vref, RX VrefLevel [Byte0]: 67
7930 12:27:12.166045 [Byte1]: 67
7931 12:27:12.170415
7932 12:27:12.170517 Set Vref, RX VrefLevel [Byte0]: 68
7933 12:27:12.173569 [Byte1]: 68
7934 12:27:12.177980
7935 12:27:12.178062 Set Vref, RX VrefLevel [Byte0]: 69
7936 12:27:12.181126 [Byte1]: 69
7937 12:27:12.185480
7938 12:27:12.185593 Set Vref, RX VrefLevel [Byte0]: 70
7939 12:27:12.188697 [Byte1]: 70
7940 12:27:12.192971
7941 12:27:12.193055 Set Vref, RX VrefLevel [Byte0]: 71
7942 12:27:12.196540 [Byte1]: 71
7943 12:27:12.200947
7944 12:27:12.201032 Set Vref, RX VrefLevel [Byte0]: 72
7945 12:27:12.204075 [Byte1]: 72
7946 12:27:12.208347
7947 12:27:12.208432 Set Vref, RX VrefLevel [Byte0]: 73
7948 12:27:12.211380 [Byte1]: 73
7949 12:27:12.216385
7950 12:27:12.216469 Set Vref, RX VrefLevel [Byte0]: 74
7951 12:27:12.219583 [Byte1]: 74
7952 12:27:12.223341
7953 12:27:12.223426 Set Vref, RX VrefLevel [Byte0]: 75
7954 12:27:12.226960 [Byte1]: 75
7955 12:27:12.231372
7956 12:27:12.231457 Set Vref, RX VrefLevel [Byte0]: 76
7957 12:27:12.234590 [Byte1]: 76
7958 12:27:12.238932
7959 12:27:12.239016 Set Vref, RX VrefLevel [Byte0]: 77
7960 12:27:12.242306 [Byte1]: 77
7961 12:27:12.246709
7962 12:27:12.246809 Set Vref, RX VrefLevel [Byte0]: 78
7963 12:27:12.249908 [Byte1]: 78
7964 12:27:12.254329
7965 12:27:12.254415 Final RX Vref Byte 0 = 64 to rank0
7966 12:27:12.257466 Final RX Vref Byte 1 = 58 to rank0
7967 12:27:12.260698 Final RX Vref Byte 0 = 64 to rank1
7968 12:27:12.263954 Final RX Vref Byte 1 = 58 to rank1==
7969 12:27:12.266980 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 12:27:12.273858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 12:27:12.273975 ==
7972 12:27:12.274094 DQS Delay:
7973 12:27:12.276962 DQS0 = 0, DQS1 = 0
7974 12:27:12.277039 DQM Delay:
7975 12:27:12.277106 DQM0 = 133, DQM1 = 123
7976 12:27:12.280073 DQ Delay:
7977 12:27:12.283775 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
7978 12:27:12.286800 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7979 12:27:12.290539 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
7980 12:27:12.293738 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
7981 12:27:12.293828
7982 12:27:12.293914
7983 12:27:12.294000
7984 12:27:12.296576 [DramC_TX_OE_Calibration] TA2
7985 12:27:12.300358 Original DQ_B0 (3 6) =30, OEN = 27
7986 12:27:12.303389 Original DQ_B1 (3 6) =30, OEN = 27
7987 12:27:12.306590 24, 0x0, End_B0=24 End_B1=24
7988 12:27:12.309723 25, 0x0, End_B0=25 End_B1=25
7989 12:27:12.309805 26, 0x0, End_B0=26 End_B1=26
7990 12:27:12.313419 27, 0x0, End_B0=27 End_B1=27
7991 12:27:12.316523 28, 0x0, End_B0=28 End_B1=28
7992 12:27:12.319710 29, 0x0, End_B0=29 End_B1=29
7993 12:27:12.319787 30, 0x0, End_B0=30 End_B1=30
7994 12:27:12.323495 31, 0x4141, End_B0=30 End_B1=30
7995 12:27:12.326639 Byte0 end_step=30 best_step=27
7996 12:27:12.329662 Byte1 end_step=30 best_step=27
7997 12:27:12.332971 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 12:27:12.336820 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 12:27:12.336930
8000 12:27:12.336994
8001 12:27:12.342888 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8002 12:27:12.346649 CH0 RK0: MR19=303, MR18=2011
8003 12:27:12.353090 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8004 12:27:12.353173
8005 12:27:12.356308 ----->DramcWriteLeveling(PI) begin...
8006 12:27:12.356448 ==
8007 12:27:12.359294 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 12:27:12.362620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 12:27:12.362709 ==
8010 12:27:12.366041 Write leveling (Byte 0): 37 => 37
8011 12:27:12.369653 Write leveling (Byte 1): 29 => 29
8012 12:27:12.372879 DramcWriteLeveling(PI) end<-----
8013 12:27:12.372960
8014 12:27:12.373024 ==
8015 12:27:12.376064 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 12:27:12.379831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 12:27:12.382951 ==
8018 12:27:12.383032 [Gating] SW mode calibration
8019 12:27:12.392945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 12:27:12.396066 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 12:27:12.399131 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 12:27:12.406001 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 12:27:12.409203 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 12:27:12.412255 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8025 12:27:12.419035 1 4 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8026 12:27:12.422113 1 4 20 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
8027 12:27:12.425817 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 12:27:12.432049 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 12:27:12.435805 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 12:27:12.439039 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 12:27:12.445341 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8032 12:27:12.448463 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8033 12:27:12.451660 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8034 12:27:12.458601 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8035 12:27:12.461693 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 12:27:12.464833 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 12:27:12.472014 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 12:27:12.474896 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 12:27:12.478159 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 12:27:12.485137 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8041 12:27:12.488245 1 6 16 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
8042 12:27:12.491372 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8043 12:27:12.498089 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 12:27:12.501703 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 12:27:12.504825 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 12:27:12.511129 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 12:27:12.514954 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 12:27:12.517934 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8049 12:27:12.524448 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8050 12:27:12.528266 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8051 12:27:12.531513 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:27:12.537673 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:27:12.541374 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:27:12.544411 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:27:12.551269 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:27:12.554489 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:27:12.557683 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:27:12.564043 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:27:12.567153 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:27:12.570935 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:27:12.577232 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 12:27:12.580884 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:27:12.583987 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8064 12:27:12.590276 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8065 12:27:12.594018 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8066 12:27:12.597139 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 12:27:12.600290 Total UI for P1: 0, mck2ui 16
8068 12:27:12.604078 best dqsien dly found for B0: ( 1, 9, 12)
8069 12:27:12.610201 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 12:27:12.610289 Total UI for P1: 0, mck2ui 16
8071 12:27:12.616856 best dqsien dly found for B1: ( 1, 9, 16)
8072 12:27:12.620134 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8073 12:27:12.623631 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8074 12:27:12.623744
8075 12:27:12.626692 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8076 12:27:12.629764 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8077 12:27:12.633653 [Gating] SW calibration Done
8078 12:27:12.633752 ==
8079 12:27:12.636902 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 12:27:12.640018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 12:27:12.640131 ==
8082 12:27:12.643066 RX Vref Scan: 0
8083 12:27:12.643179
8084 12:27:12.646371 RX Vref 0 -> 0, step: 1
8085 12:27:12.646483
8086 12:27:12.646584 RX Delay 0 -> 252, step: 8
8087 12:27:12.653162 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8088 12:27:12.656267 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8089 12:27:12.659492 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8090 12:27:12.663369 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8091 12:27:12.666563 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8092 12:27:12.669564 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8093 12:27:12.676711 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8094 12:27:12.679890 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8095 12:27:12.682911 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8096 12:27:12.686676 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8097 12:27:12.693169 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8098 12:27:12.696284 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8099 12:27:12.699897 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8100 12:27:12.702929 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8101 12:27:12.706179 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8102 12:27:12.712873 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8103 12:27:12.712984 ==
8104 12:27:12.715890 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 12:27:12.719691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 12:27:12.719797 ==
8107 12:27:12.719895 DQS Delay:
8108 12:27:12.722820 DQS0 = 0, DQS1 = 0
8109 12:27:12.722931 DQM Delay:
8110 12:27:12.726043 DQM0 = 133, DQM1 = 128
8111 12:27:12.726139 DQ Delay:
8112 12:27:12.729144 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8113 12:27:12.732202 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8114 12:27:12.735932 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8115 12:27:12.739041 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8116 12:27:12.742117
8117 12:27:12.742219
8118 12:27:12.742317 ==
8119 12:27:12.745998 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 12:27:12.749190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 12:27:12.749308 ==
8122 12:27:12.749433
8123 12:27:12.749548
8124 12:27:12.752406 TX Vref Scan disable
8125 12:27:12.752505 == TX Byte 0 ==
8126 12:27:12.758810 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8127 12:27:12.762575 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8128 12:27:12.762656 == TX Byte 1 ==
8129 12:27:12.768993 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8130 12:27:12.771964 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8131 12:27:12.772047 ==
8132 12:27:12.775234 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 12:27:12.778916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 12:27:12.779000 ==
8135 12:27:12.793508
8136 12:27:12.796799 TX Vref early break, caculate TX vref
8137 12:27:12.799923 TX Vref=16, minBit 1, minWin=22, winSum=375
8138 12:27:12.802971 TX Vref=18, minBit 0, minWin=23, winSum=391
8139 12:27:12.806646 TX Vref=20, minBit 0, minWin=23, winSum=396
8140 12:27:12.809836 TX Vref=22, minBit 2, minWin=23, winSum=408
8141 12:27:12.812842 TX Vref=24, minBit 0, minWin=25, winSum=417
8142 12:27:12.819663 TX Vref=26, minBit 4, minWin=24, winSum=417
8143 12:27:12.822695 TX Vref=28, minBit 1, minWin=24, winSum=413
8144 12:27:12.826529 TX Vref=30, minBit 0, minWin=24, winSum=409
8145 12:27:12.829575 TX Vref=32, minBit 0, minWin=24, winSum=399
8146 12:27:12.832781 TX Vref=34, minBit 0, minWin=23, winSum=387
8147 12:27:12.839830 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 24
8148 12:27:12.839951
8149 12:27:12.842872 Final TX Range 0 Vref 24
8150 12:27:12.842973
8151 12:27:12.843064 ==
8152 12:27:12.846017 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:27:12.849616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:27:12.849699 ==
8155 12:27:12.849765
8156 12:27:12.849826
8157 12:27:12.852956 TX Vref Scan disable
8158 12:27:12.859367 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8159 12:27:12.859451 == TX Byte 0 ==
8160 12:27:12.862467 u2DelayCellOfst[0]=11 cells (3 PI)
8161 12:27:12.865648 u2DelayCellOfst[1]=14 cells (4 PI)
8162 12:27:12.869372 u2DelayCellOfst[2]=11 cells (3 PI)
8163 12:27:12.872447 u2DelayCellOfst[3]=11 cells (3 PI)
8164 12:27:12.875676 u2DelayCellOfst[4]=7 cells (2 PI)
8165 12:27:12.879470 u2DelayCellOfst[5]=0 cells (0 PI)
8166 12:27:12.882533 u2DelayCellOfst[6]=14 cells (4 PI)
8167 12:27:12.885767 u2DelayCellOfst[7]=14 cells (4 PI)
8168 12:27:12.888836 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8169 12:27:12.892510 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8170 12:27:12.895801 == TX Byte 1 ==
8171 12:27:12.899040 u2DelayCellOfst[8]=0 cells (0 PI)
8172 12:27:12.902084 u2DelayCellOfst[9]=3 cells (1 PI)
8173 12:27:12.902206 u2DelayCellOfst[10]=7 cells (2 PI)
8174 12:27:12.905797 u2DelayCellOfst[11]=3 cells (1 PI)
8175 12:27:12.908859 u2DelayCellOfst[12]=14 cells (4 PI)
8176 12:27:12.912028 u2DelayCellOfst[13]=11 cells (3 PI)
8177 12:27:12.915719 u2DelayCellOfst[14]=18 cells (5 PI)
8178 12:27:12.918864 u2DelayCellOfst[15]=11 cells (3 PI)
8179 12:27:12.925460 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8180 12:27:12.928605 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8181 12:27:12.928722 DramC Write-DBI on
8182 12:27:12.928837 ==
8183 12:27:12.932124 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 12:27:12.938314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 12:27:12.938418 ==
8186 12:27:12.938512
8187 12:27:12.938599
8188 12:27:12.938685 TX Vref Scan disable
8189 12:27:12.942751 == TX Byte 0 ==
8190 12:27:12.945896 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8191 12:27:12.949066 == TX Byte 1 ==
8192 12:27:12.952735 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8193 12:27:12.955753 DramC Write-DBI off
8194 12:27:12.955861
8195 12:27:12.955945 [DATLAT]
8196 12:27:12.956044 Freq=1600, CH0 RK1
8197 12:27:12.956141
8198 12:27:12.959534 DATLAT Default: 0xf
8199 12:27:12.959676 0, 0xFFFF, sum = 0
8200 12:27:12.962796 1, 0xFFFF, sum = 0
8201 12:27:12.965831 2, 0xFFFF, sum = 0
8202 12:27:12.965917 3, 0xFFFF, sum = 0
8203 12:27:12.968946 4, 0xFFFF, sum = 0
8204 12:27:12.969031 5, 0xFFFF, sum = 0
8205 12:27:12.972875 6, 0xFFFF, sum = 0
8206 12:27:12.972960 7, 0xFFFF, sum = 0
8207 12:27:12.976041 8, 0xFFFF, sum = 0
8208 12:27:12.976127 9, 0xFFFF, sum = 0
8209 12:27:12.979054 10, 0xFFFF, sum = 0
8210 12:27:12.979181 11, 0xFFFF, sum = 0
8211 12:27:12.982248 12, 0xFFFF, sum = 0
8212 12:27:12.982333 13, 0xFFFF, sum = 0
8213 12:27:12.985419 14, 0x0, sum = 1
8214 12:27:12.985505 15, 0x0, sum = 2
8215 12:27:12.989370 16, 0x0, sum = 3
8216 12:27:12.989455 17, 0x0, sum = 4
8217 12:27:12.992488 best_step = 15
8218 12:27:12.992601
8219 12:27:12.992686 ==
8220 12:27:12.995553 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 12:27:12.998730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 12:27:12.998844 ==
8223 12:27:13.001932 RX Vref Scan: 0
8224 12:27:13.002104
8225 12:27:13.002189 RX Vref 0 -> 0, step: 1
8226 12:27:13.002271
8227 12:27:13.005135 RX Delay 11 -> 252, step: 4
8228 12:27:13.012028 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8229 12:27:13.015072 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8230 12:27:13.018774 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8231 12:27:13.021915 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8232 12:27:13.025080 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8233 12:27:13.031766 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8234 12:27:13.034996 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8235 12:27:13.038056 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8236 12:27:13.041862 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8237 12:27:13.044894 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8238 12:27:13.051189 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8239 12:27:13.054930 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8240 12:27:13.057968 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8241 12:27:13.061101 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8242 12:27:13.067976 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8243 12:27:13.071161 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8244 12:27:13.071240 ==
8245 12:27:13.074238 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 12:27:13.077299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 12:27:13.077404 ==
8248 12:27:13.081136 DQS Delay:
8249 12:27:13.081209 DQS0 = 0, DQS1 = 0
8250 12:27:13.081271 DQM Delay:
8251 12:27:13.084206 DQM0 = 130, DQM1 = 125
8252 12:27:13.084301 DQ Delay:
8253 12:27:13.087358 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8254 12:27:13.091129 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8255 12:27:13.094315 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8256 12:27:13.100542 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8257 12:27:13.100637
8258 12:27:13.100705
8259 12:27:13.100767
8260 12:27:13.104382 [DramC_TX_OE_Calibration] TA2
8261 12:27:13.107458 Original DQ_B0 (3 6) =30, OEN = 27
8262 12:27:13.110625 Original DQ_B1 (3 6) =30, OEN = 27
8263 12:27:13.110738 24, 0x0, End_B0=24 End_B1=24
8264 12:27:13.113747 25, 0x0, End_B0=25 End_B1=25
8265 12:27:13.117296 26, 0x0, End_B0=26 End_B1=26
8266 12:27:13.120634 27, 0x0, End_B0=27 End_B1=27
8267 12:27:13.120715 28, 0x0, End_B0=28 End_B1=28
8268 12:27:13.124095 29, 0x0, End_B0=29 End_B1=29
8269 12:27:13.127204 30, 0x0, End_B0=30 End_B1=30
8270 12:27:13.130404 31, 0x4141, End_B0=30 End_B1=30
8271 12:27:13.133460 Byte0 end_step=30 best_step=27
8272 12:27:13.137080 Byte1 end_step=30 best_step=27
8273 12:27:13.137165 Byte0 TX OE(2T, 0.5T) = (3, 3)
8274 12:27:13.140144 Byte1 TX OE(2T, 0.5T) = (3, 3)
8275 12:27:13.140252
8276 12:27:13.140352
8277 12:27:13.150282 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8278 12:27:13.153403 CH0 RK1: MR19=303, MR18=1F03
8279 12:27:13.159755 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8280 12:27:13.159908 [RxdqsGatingPostProcess] freq 1600
8281 12:27:13.166729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8282 12:27:13.169948 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 12:27:13.173036 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 12:27:13.176217 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 12:27:13.179436 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 12:27:13.183285 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 12:27:13.186430 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 12:27:13.189955 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 12:27:13.193012 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 12:27:13.193098 Pre-setting of DQS Precalculation
8291 12:27:13.199682 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8292 12:27:13.199774 ==
8293 12:27:13.202809 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 12:27:13.206522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 12:27:13.206617 ==
8296 12:27:13.212985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 12:27:13.216253 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 12:27:13.222550 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 12:27:13.225792 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 12:27:13.235903 [CA 0] Center 42 (13~71) winsize 59
8301 12:27:13.238930 [CA 1] Center 42 (13~72) winsize 60
8302 12:27:13.242599 [CA 2] Center 37 (9~66) winsize 58
8303 12:27:13.245840 [CA 3] Center 37 (8~67) winsize 60
8304 12:27:13.248967 [CA 4] Center 37 (8~67) winsize 60
8305 12:27:13.252653 [CA 5] Center 37 (8~67) winsize 60
8306 12:27:13.252735
8307 12:27:13.255614 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8308 12:27:13.255696
8309 12:27:13.258718 [CATrainingPosCal] consider 1 rank data
8310 12:27:13.262718 u2DelayCellTimex100 = 262/100 ps
8311 12:27:13.265899 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8312 12:27:13.272057 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8313 12:27:13.275319 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8314 12:27:13.279056 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 12:27:13.282257 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8316 12:27:13.285466 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8317 12:27:13.285548
8318 12:27:13.288538 CA PerBit enable=1, Macro0, CA PI delay=37
8319 12:27:13.288621
8320 12:27:13.291822 [CBTSetCACLKResult] CA Dly = 37
8321 12:27:13.295438 CS Dly: 9 (0~40)
8322 12:27:13.298631 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 12:27:13.301933 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 12:27:13.302012 ==
8325 12:27:13.305050 Dram Type= 6, Freq= 0, CH_1, rank 1
8326 12:27:13.311901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 12:27:13.311983 ==
8328 12:27:13.315147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 12:27:13.321445 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 12:27:13.325192 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 12:27:13.331414 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 12:27:13.338961 [CA 0] Center 42 (13~72) winsize 60
8333 12:27:13.342114 [CA 1] Center 42 (12~72) winsize 61
8334 12:27:13.345632 [CA 2] Center 37 (8~67) winsize 60
8335 12:27:13.348917 [CA 3] Center 37 (7~67) winsize 61
8336 12:27:13.352072 [CA 4] Center 38 (9~67) winsize 59
8337 12:27:13.355745 [CA 5] Center 37 (8~66) winsize 59
8338 12:27:13.355826
8339 12:27:13.358768 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8340 12:27:13.358847
8341 12:27:13.362548 [CATrainingPosCal] consider 2 rank data
8342 12:27:13.365691 u2DelayCellTimex100 = 262/100 ps
8343 12:27:13.371823 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8344 12:27:13.375484 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8345 12:27:13.378642 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8346 12:27:13.381727 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8347 12:27:13.385480 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8348 12:27:13.388624 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8349 12:27:13.388712
8350 12:27:13.391821 CA PerBit enable=1, Macro0, CA PI delay=37
8351 12:27:13.391899
8352 12:27:13.394953 [CBTSetCACLKResult] CA Dly = 37
8353 12:27:13.398627 CS Dly: 11 (0~44)
8354 12:27:13.401743 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 12:27:13.404997 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 12:27:13.405074
8357 12:27:13.408035 ----->DramcWriteLeveling(PI) begin...
8358 12:27:13.408105 ==
8359 12:27:13.411770 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 12:27:13.418090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 12:27:13.418169 ==
8362 12:27:13.421818 Write leveling (Byte 0): 25 => 25
8363 12:27:13.424860 Write leveling (Byte 1): 27 => 27
8364 12:27:13.424931 DramcWriteLeveling(PI) end<-----
8365 12:27:13.424991
8366 12:27:13.427904 ==
8367 12:27:13.431628 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 12:27:13.434870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 12:27:13.434944 ==
8370 12:27:13.437974 [Gating] SW mode calibration
8371 12:27:13.444823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8372 12:27:13.447993 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8373 12:27:13.454807 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:27:13.457960 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 12:27:13.461003 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 12:27:13.467260 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8377 12:27:13.470938 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:27:13.477169 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:27:13.480452 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:27:13.484136 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:27:13.490363 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 12:27:13.493693 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 12:27:13.497428 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8384 12:27:13.503597 1 5 12 | B1->B0 | 3232 2727 | 1 0 | (1 0) (1 0)
8385 12:27:13.507253 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:27:13.510386 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:27:13.513701 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:27:13.520449 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:27:13.523686 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 12:27:13.529876 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 12:27:13.533455 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 12:27:13.536508 1 6 12 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
8393 12:27:13.540378 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:27:13.546467 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:27:13.549794 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:27:13.553335 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:27:13.559641 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:27:13.563293 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:27:13.566272 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8400 12:27:13.573291 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 12:27:13.576286 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8402 12:27:13.579363 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:27:13.586247 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:27:13.589366 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:27:13.595692 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:27:13.599466 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:27:13.602631 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:27:13.608884 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:27:13.612520 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:27:13.615808 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:27:13.622018 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:27:13.625666 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:27:13.628753 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:27:13.635076 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:27:13.638771 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 12:27:13.641938 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 12:27:13.648786 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 12:27:13.648869 Total UI for P1: 0, mck2ui 16
8419 12:27:13.654993 best dqsien dly found for B0: ( 1, 9, 10)
8420 12:27:13.655075 Total UI for P1: 0, mck2ui 16
8421 12:27:13.658457 best dqsien dly found for B1: ( 1, 9, 10)
8422 12:27:13.665361 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8423 12:27:13.668282 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8424 12:27:13.668383
8425 12:27:13.671389 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 12:27:13.675171 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8427 12:27:13.678386 [Gating] SW calibration Done
8428 12:27:13.678468 ==
8429 12:27:13.681603 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 12:27:13.684768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 12:27:13.684850 ==
8432 12:27:13.687983 RX Vref Scan: 0
8433 12:27:13.688131
8434 12:27:13.688262 RX Vref 0 -> 0, step: 1
8435 12:27:13.688379
8436 12:27:13.691221 RX Delay 0 -> 252, step: 8
8437 12:27:13.694952 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8438 12:27:13.701217 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8439 12:27:13.704366 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8440 12:27:13.707590 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8441 12:27:13.711392 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8442 12:27:13.714490 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8443 12:27:13.721341 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8444 12:27:13.724442 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8445 12:27:13.727595 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8446 12:27:13.730844 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8447 12:27:13.733980 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8448 12:27:13.740824 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8449 12:27:13.743958 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8450 12:27:13.747743 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8451 12:27:13.750958 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8452 12:27:13.757590 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8453 12:27:13.757697 ==
8454 12:27:13.760790 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 12:27:13.763755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 12:27:13.763837 ==
8457 12:27:13.763901 DQS Delay:
8458 12:27:13.766998 DQS0 = 0, DQS1 = 0
8459 12:27:13.767080 DQM Delay:
8460 12:27:13.770763 DQM0 = 137, DQM1 = 129
8461 12:27:13.770844 DQ Delay:
8462 12:27:13.773828 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8463 12:27:13.777510 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8464 12:27:13.780591 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8465 12:27:13.783803 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8466 12:27:13.783884
8467 12:27:13.787457
8468 12:27:13.787537 ==
8469 12:27:13.790658 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 12:27:13.793841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 12:27:13.793922 ==
8472 12:27:13.793987
8473 12:27:13.794045
8474 12:27:13.796969 TX Vref Scan disable
8475 12:27:13.797049 == TX Byte 0 ==
8476 12:27:13.803916 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8477 12:27:13.807059 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8478 12:27:13.807141 == TX Byte 1 ==
8479 12:27:13.813336 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8480 12:27:13.817080 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8481 12:27:13.817161 ==
8482 12:27:13.820250 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 12:27:13.823438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 12:27:13.823519 ==
8485 12:27:13.836575
8486 12:27:13.839764 TX Vref early break, caculate TX vref
8487 12:27:13.843525 TX Vref=16, minBit 6, minWin=22, winSum=380
8488 12:27:13.846586 TX Vref=18, minBit 0, minWin=23, winSum=390
8489 12:27:13.849625 TX Vref=20, minBit 0, minWin=23, winSum=396
8490 12:27:13.852816 TX Vref=22, minBit 1, minWin=24, winSum=406
8491 12:27:13.856512 TX Vref=24, minBit 0, minWin=25, winSum=416
8492 12:27:13.863387 TX Vref=26, minBit 5, minWin=25, winSum=423
8493 12:27:13.866391 TX Vref=28, minBit 0, minWin=25, winSum=424
8494 12:27:13.869542 TX Vref=30, minBit 5, minWin=24, winSum=416
8495 12:27:13.872671 TX Vref=32, minBit 0, minWin=24, winSum=405
8496 12:27:13.876313 TX Vref=34, minBit 0, minWin=23, winSum=396
8497 12:27:13.882598 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8498 12:27:13.882682
8499 12:27:13.885907 Final TX Range 0 Vref 28
8500 12:27:13.885989
8501 12:27:13.886054 ==
8502 12:27:13.889630 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 12:27:13.892749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 12:27:13.892831 ==
8505 12:27:13.892896
8506 12:27:13.892956
8507 12:27:13.895960 TX Vref Scan disable
8508 12:27:13.902734 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8509 12:27:13.902817 == TX Byte 0 ==
8510 12:27:13.905890 u2DelayCellOfst[0]=18 cells (5 PI)
8511 12:27:13.909028 u2DelayCellOfst[1]=14 cells (4 PI)
8512 12:27:13.912206 u2DelayCellOfst[2]=0 cells (0 PI)
8513 12:27:13.915963 u2DelayCellOfst[3]=7 cells (2 PI)
8514 12:27:13.919143 u2DelayCellOfst[4]=11 cells (3 PI)
8515 12:27:13.922320 u2DelayCellOfst[5]=22 cells (6 PI)
8516 12:27:13.925501 u2DelayCellOfst[6]=22 cells (6 PI)
8517 12:27:13.928713 u2DelayCellOfst[7]=7 cells (2 PI)
8518 12:27:13.932424 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8519 12:27:13.935529 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8520 12:27:13.938714 == TX Byte 1 ==
8521 12:27:13.942571 u2DelayCellOfst[8]=0 cells (0 PI)
8522 12:27:13.945737 u2DelayCellOfst[9]=3 cells (1 PI)
8523 12:27:13.945821 u2DelayCellOfst[10]=11 cells (3 PI)
8524 12:27:13.948865 u2DelayCellOfst[11]=3 cells (1 PI)
8525 12:27:13.952376 u2DelayCellOfst[12]=14 cells (4 PI)
8526 12:27:13.955371 u2DelayCellOfst[13]=18 cells (5 PI)
8527 12:27:13.958609 u2DelayCellOfst[14]=18 cells (5 PI)
8528 12:27:13.961911 u2DelayCellOfst[15]=18 cells (5 PI)
8529 12:27:13.968500 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8530 12:27:13.971641 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8531 12:27:13.971724 DramC Write-DBI on
8532 12:27:13.971794 ==
8533 12:27:13.975372 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 12:27:13.981671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 12:27:13.981781 ==
8536 12:27:13.981884
8537 12:27:13.981979
8538 12:27:13.982121 TX Vref Scan disable
8539 12:27:13.985971 == TX Byte 0 ==
8540 12:27:13.989092 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8541 12:27:13.992897 == TX Byte 1 ==
8542 12:27:13.995998 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8543 12:27:13.999248 DramC Write-DBI off
8544 12:27:13.999350
8545 12:27:13.999442 [DATLAT]
8546 12:27:13.999531 Freq=1600, CH1 RK0
8547 12:27:13.999620
8548 12:27:14.002403 DATLAT Default: 0xf
8549 12:27:14.002503 0, 0xFFFF, sum = 0
8550 12:27:14.005551 1, 0xFFFF, sum = 0
8551 12:27:14.009241 2, 0xFFFF, sum = 0
8552 12:27:14.009355 3, 0xFFFF, sum = 0
8553 12:27:14.012385 4, 0xFFFF, sum = 0
8554 12:27:14.012488 5, 0xFFFF, sum = 0
8555 12:27:14.015624 6, 0xFFFF, sum = 0
8556 12:27:14.015696 7, 0xFFFF, sum = 0
8557 12:27:14.019359 8, 0xFFFF, sum = 0
8558 12:27:14.019460 9, 0xFFFF, sum = 0
8559 12:27:14.022428 10, 0xFFFF, sum = 0
8560 12:27:14.022531 11, 0xFFFF, sum = 0
8561 12:27:14.025701 12, 0xFFFF, sum = 0
8562 12:27:14.025806 13, 0xFFFF, sum = 0
8563 12:27:14.028985 14, 0x0, sum = 1
8564 12:27:14.029059 15, 0x0, sum = 2
8565 12:27:14.032149 16, 0x0, sum = 3
8566 12:27:14.032286 17, 0x0, sum = 4
8567 12:27:14.035385 best_step = 15
8568 12:27:14.035487
8569 12:27:14.035569 ==
8570 12:27:14.038988 Dram Type= 6, Freq= 0, CH_1, rank 0
8571 12:27:14.042199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8572 12:27:14.042301 ==
8573 12:27:14.045328 RX Vref Scan: 1
8574 12:27:14.045428
8575 12:27:14.045517 Set Vref Range= 24 -> 127
8576 12:27:14.045603
8577 12:27:14.048467 RX Vref 24 -> 127, step: 1
8578 12:27:14.048597
8579 12:27:14.052186 RX Delay 11 -> 252, step: 4
8580 12:27:14.052289
8581 12:27:14.055391 Set Vref, RX VrefLevel [Byte0]: 24
8582 12:27:14.058442 [Byte1]: 24
8583 12:27:14.058541
8584 12:27:14.062084 Set Vref, RX VrefLevel [Byte0]: 25
8585 12:27:14.065153 [Byte1]: 25
8586 12:27:14.068964
8587 12:27:14.069070 Set Vref, RX VrefLevel [Byte0]: 26
8588 12:27:14.072047 [Byte1]: 26
8589 12:27:14.076282
8590 12:27:14.076394 Set Vref, RX VrefLevel [Byte0]: 27
8591 12:27:14.079313 [Byte1]: 27
8592 12:27:14.083817
8593 12:27:14.083898 Set Vref, RX VrefLevel [Byte0]: 28
8594 12:27:14.087401 [Byte1]: 28
8595 12:27:14.091327
8596 12:27:14.091408 Set Vref, RX VrefLevel [Byte0]: 29
8597 12:27:14.095172 [Byte1]: 29
8598 12:27:14.099490
8599 12:27:14.099602 Set Vref, RX VrefLevel [Byte0]: 30
8600 12:27:14.102571 [Byte1]: 30
8601 12:27:14.107108
8602 12:27:14.107188 Set Vref, RX VrefLevel [Byte0]: 31
8603 12:27:14.110112 [Byte1]: 31
8604 12:27:14.114507
8605 12:27:14.114588 Set Vref, RX VrefLevel [Byte0]: 32
8606 12:27:14.117681 [Byte1]: 32
8607 12:27:14.122124
8608 12:27:14.122205 Set Vref, RX VrefLevel [Byte0]: 33
8609 12:27:14.125249 [Byte1]: 33
8610 12:27:14.129509
8611 12:27:14.129590 Set Vref, RX VrefLevel [Byte0]: 34
8612 12:27:14.132762 [Byte1]: 34
8613 12:27:14.137065
8614 12:27:14.137145 Set Vref, RX VrefLevel [Byte0]: 35
8615 12:27:14.140306 [Byte1]: 35
8616 12:27:14.144657
8617 12:27:14.144742 Set Vref, RX VrefLevel [Byte0]: 36
8618 12:27:14.148435 [Byte1]: 36
8619 12:27:14.152336
8620 12:27:14.152416 Set Vref, RX VrefLevel [Byte0]: 37
8621 12:27:14.155494 [Byte1]: 37
8622 12:27:14.159824
8623 12:27:14.159928 Set Vref, RX VrefLevel [Byte0]: 38
8624 12:27:14.163263 [Byte1]: 38
8625 12:27:14.167693
8626 12:27:14.167802 Set Vref, RX VrefLevel [Byte0]: 39
8627 12:27:14.170846 [Byte1]: 39
8628 12:27:14.175238
8629 12:27:14.175320 Set Vref, RX VrefLevel [Byte0]: 40
8630 12:27:14.178877 [Byte1]: 40
8631 12:27:14.183118
8632 12:27:14.183200 Set Vref, RX VrefLevel [Byte0]: 41
8633 12:27:14.186222 [Byte1]: 41
8634 12:27:14.190733
8635 12:27:14.190818 Set Vref, RX VrefLevel [Byte0]: 42
8636 12:27:14.193793 [Byte1]: 42
8637 12:27:14.198024
8638 12:27:14.198110 Set Vref, RX VrefLevel [Byte0]: 43
8639 12:27:14.201113 [Byte1]: 43
8640 12:27:14.206043
8641 12:27:14.206128 Set Vref, RX VrefLevel [Byte0]: 44
8642 12:27:14.209263 [Byte1]: 44
8643 12:27:14.213588
8644 12:27:14.213673 Set Vref, RX VrefLevel [Byte0]: 45
8645 12:27:14.216788 [Byte1]: 45
8646 12:27:14.221118
8647 12:27:14.221202 Set Vref, RX VrefLevel [Byte0]: 46
8648 12:27:14.224287 [Byte1]: 46
8649 12:27:14.228488
8650 12:27:14.228598 Set Vref, RX VrefLevel [Byte0]: 47
8651 12:27:14.231597 [Byte1]: 47
8652 12:27:14.236200
8653 12:27:14.236284 Set Vref, RX VrefLevel [Byte0]: 48
8654 12:27:14.239368 [Byte1]: 48
8655 12:27:14.243750
8656 12:27:14.243834 Set Vref, RX VrefLevel [Byte0]: 49
8657 12:27:14.246818 [Byte1]: 49
8658 12:27:14.251395
8659 12:27:14.251471 Set Vref, RX VrefLevel [Byte0]: 50
8660 12:27:14.254787 [Byte1]: 50
8661 12:27:14.259196
8662 12:27:14.259276 Set Vref, RX VrefLevel [Byte0]: 51
8663 12:27:14.262249 [Byte1]: 51
8664 12:27:14.266455
8665 12:27:14.266526 Set Vref, RX VrefLevel [Byte0]: 52
8666 12:27:14.270240 [Byte1]: 52
8667 12:27:14.274034
8668 12:27:14.274107 Set Vref, RX VrefLevel [Byte0]: 53
8669 12:27:14.277910 [Byte1]: 53
8670 12:27:14.281943
8671 12:27:14.282025 Set Vref, RX VrefLevel [Byte0]: 54
8672 12:27:14.284944 [Byte1]: 54
8673 12:27:14.289409
8674 12:27:14.293179 Set Vref, RX VrefLevel [Byte0]: 55
8675 12:27:14.293262 [Byte1]: 55
8676 12:27:14.297421
8677 12:27:14.297505 Set Vref, RX VrefLevel [Byte0]: 56
8678 12:27:14.300549 [Byte1]: 56
8679 12:27:14.304831
8680 12:27:14.304916 Set Vref, RX VrefLevel [Byte0]: 57
8681 12:27:14.308291 [Byte1]: 57
8682 12:27:14.312151
8683 12:27:14.312234 Set Vref, RX VrefLevel [Byte0]: 58
8684 12:27:14.315933 [Byte1]: 58
8685 12:27:14.320325
8686 12:27:14.320407 Set Vref, RX VrefLevel [Byte0]: 59
8687 12:27:14.323429 [Byte1]: 59
8688 12:27:14.327191
8689 12:27:14.327358 Set Vref, RX VrefLevel [Byte0]: 60
8690 12:27:14.330999 [Byte1]: 60
8691 12:27:14.335300
8692 12:27:14.335393 Set Vref, RX VrefLevel [Byte0]: 61
8693 12:27:14.338499 [Byte1]: 61
8694 12:27:14.343000
8695 12:27:14.343085 Set Vref, RX VrefLevel [Byte0]: 62
8696 12:27:14.346120 [Byte1]: 62
8697 12:27:14.350432
8698 12:27:14.350550 Set Vref, RX VrefLevel [Byte0]: 63
8699 12:27:14.353607 [Byte1]: 63
8700 12:27:14.357984
8701 12:27:14.358089 Set Vref, RX VrefLevel [Byte0]: 64
8702 12:27:14.361162 [Byte1]: 64
8703 12:27:14.365591
8704 12:27:14.365676 Set Vref, RX VrefLevel [Byte0]: 65
8705 12:27:14.369225 [Byte1]: 65
8706 12:27:14.373440
8707 12:27:14.373526 Set Vref, RX VrefLevel [Byte0]: 66
8708 12:27:14.376600 [Byte1]: 66
8709 12:27:14.380920
8710 12:27:14.381026 Set Vref, RX VrefLevel [Byte0]: 67
8711 12:27:14.384139 [Byte1]: 67
8712 12:27:14.388322
8713 12:27:14.388406 Set Vref, RX VrefLevel [Byte0]: 68
8714 12:27:14.391489 [Byte1]: 68
8715 12:27:14.395788
8716 12:27:14.395871 Set Vref, RX VrefLevel [Byte0]: 69
8717 12:27:14.399628 [Byte1]: 69
8718 12:27:14.403351
8719 12:27:14.403434 Set Vref, RX VrefLevel [Byte0]: 70
8720 12:27:14.407214 [Byte1]: 70
8721 12:27:14.410962
8722 12:27:14.411053 Set Vref, RX VrefLevel [Byte0]: 71
8723 12:27:14.414736 [Byte1]: 71
8724 12:27:14.418566
8725 12:27:14.418663 Set Vref, RX VrefLevel [Byte0]: 72
8726 12:27:14.422292 [Byte1]: 72
8727 12:27:14.426854
8728 12:27:14.426928 Set Vref, RX VrefLevel [Byte0]: 73
8729 12:27:14.430095 [Byte1]: 73
8730 12:27:14.433910
8731 12:27:14.433992 Final RX Vref Byte 0 = 53 to rank0
8732 12:27:14.437542 Final RX Vref Byte 1 = 58 to rank0
8733 12:27:14.440808 Final RX Vref Byte 0 = 53 to rank1
8734 12:27:14.443952 Final RX Vref Byte 1 = 58 to rank1==
8735 12:27:14.447144 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 12:27:14.454027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 12:27:14.454108 ==
8738 12:27:14.454182 DQS Delay:
8739 12:27:14.457145 DQS0 = 0, DQS1 = 0
8740 12:27:14.457217 DQM Delay:
8741 12:27:14.457286 DQM0 = 133, DQM1 = 127
8742 12:27:14.460340 DQ Delay:
8743 12:27:14.463560 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =132
8744 12:27:14.467253 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8745 12:27:14.470532 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8746 12:27:14.473583 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8747 12:27:14.473674
8748 12:27:14.473739
8749 12:27:14.473803
8750 12:27:14.477190 [DramC_TX_OE_Calibration] TA2
8751 12:27:14.480216 Original DQ_B0 (3 6) =30, OEN = 27
8752 12:27:14.483988 Original DQ_B1 (3 6) =30, OEN = 27
8753 12:27:14.487053 24, 0x0, End_B0=24 End_B1=24
8754 12:27:14.487136 25, 0x0, End_B0=25 End_B1=25
8755 12:27:14.490208 26, 0x0, End_B0=26 End_B1=26
8756 12:27:14.493238 27, 0x0, End_B0=27 End_B1=27
8757 12:27:14.497022 28, 0x0, End_B0=28 End_B1=28
8758 12:27:14.500176 29, 0x0, End_B0=29 End_B1=29
8759 12:27:14.500258 30, 0x0, End_B0=30 End_B1=30
8760 12:27:14.503808 31, 0x4141, End_B0=30 End_B1=30
8761 12:27:14.506861 Byte0 end_step=30 best_step=27
8762 12:27:14.510146 Byte1 end_step=30 best_step=27
8763 12:27:14.513860 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 12:27:14.516760 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 12:27:14.516860
8766 12:27:14.516949
8767 12:27:14.523187 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8768 12:27:14.526983 CH1 RK0: MR19=303, MR18=190F
8769 12:27:14.533251 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8770 12:27:14.533333
8771 12:27:14.536445 ----->DramcWriteLeveling(PI) begin...
8772 12:27:14.536573 ==
8773 12:27:14.540267 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 12:27:14.543241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 12:27:14.543323 ==
8776 12:27:14.546426 Write leveling (Byte 0): 24 => 24
8777 12:27:14.550274 Write leveling (Byte 1): 26 => 26
8778 12:27:14.553440 DramcWriteLeveling(PI) end<-----
8779 12:27:14.553521
8780 12:27:14.553585 ==
8781 12:27:14.556494 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 12:27:14.559607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 12:27:14.559727 ==
8784 12:27:14.563327 [Gating] SW mode calibration
8785 12:27:14.569645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 12:27:14.576491 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 12:27:14.579488 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 12:27:14.586274 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 12:27:14.589413 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8790 12:27:14.592493 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8791 12:27:14.599214 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 12:27:14.602994 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 12:27:14.606032 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 12:27:14.612769 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 12:27:14.615865 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 12:27:14.619501 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 12:27:14.625957 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8798 12:27:14.628964 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8799 12:27:14.632723 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8800 12:27:14.638909 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 12:27:14.642162 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:27:14.645314 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 12:27:14.652252 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 12:27:14.655476 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 12:27:14.658651 1 6 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
8806 12:27:14.665426 1 6 12 | B1->B0 | 4646 3232 | 0 1 | (0 0) (0 0)
8807 12:27:14.668501 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:27:14.671672 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:27:14.678832 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 12:27:14.681912 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 12:27:14.684849 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 12:27:14.691740 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 12:27:14.695009 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8814 12:27:14.698603 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8815 12:27:14.704809 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:27:14.708485 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:27:14.711614 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:27:14.718421 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:27:14.721481 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:27:14.725127 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:27:14.731627 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:27:14.734650 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:27:14.737878 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:27:14.744778 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:27:14.747949 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:27:14.751032 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:27:14.758027 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:27:14.761178 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 12:27:14.764353 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8830 12:27:14.771370 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8831 12:27:14.774022 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 12:27:14.777836 Total UI for P1: 0, mck2ui 16
8833 12:27:14.780892 best dqsien dly found for B0: ( 1, 9, 12)
8834 12:27:14.783987 Total UI for P1: 0, mck2ui 16
8835 12:27:14.787746 best dqsien dly found for B1: ( 1, 9, 10)
8836 12:27:14.790804 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8837 12:27:14.793876 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8838 12:27:14.793961
8839 12:27:14.797835 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8840 12:27:14.800953 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8841 12:27:14.803891 [Gating] SW calibration Done
8842 12:27:14.803974 ==
8843 12:27:14.807586 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 12:27:14.810635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 12:27:14.813667 ==
8846 12:27:14.813746 RX Vref Scan: 0
8847 12:27:14.813810
8848 12:27:14.817407 RX Vref 0 -> 0, step: 1
8849 12:27:14.817492
8850 12:27:14.820478 RX Delay 0 -> 252, step: 8
8851 12:27:14.823726 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8852 12:27:14.826899 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8853 12:27:14.830647 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8854 12:27:14.833874 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8855 12:27:14.840204 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8856 12:27:14.843422 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8857 12:27:14.846686 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8858 12:27:14.849892 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8859 12:27:14.853151 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8860 12:27:14.860043 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8861 12:27:14.863195 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8862 12:27:14.867049 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8863 12:27:14.870171 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8864 12:27:14.873386 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8865 12:27:14.879673 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8866 12:27:14.883426 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8867 12:27:14.883513 ==
8868 12:27:14.886564 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 12:27:14.889642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 12:27:14.889726 ==
8871 12:27:14.893325 DQS Delay:
8872 12:27:14.893408 DQS0 = 0, DQS1 = 0
8873 12:27:14.896537 DQM Delay:
8874 12:27:14.896638 DQM0 = 136, DQM1 = 129
8875 12:27:14.896704 DQ Delay:
8876 12:27:14.899627 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8877 12:27:14.902920 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8878 12:27:14.909728 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8879 12:27:14.912869 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8880 12:27:14.912957
8881 12:27:14.913022
8882 12:27:14.913081 ==
8883 12:27:14.915890 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 12:27:14.919426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 12:27:14.919532 ==
8886 12:27:14.919621
8887 12:27:14.919702
8888 12:27:14.922670 TX Vref Scan disable
8889 12:27:14.925844 == TX Byte 0 ==
8890 12:27:14.929648 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8891 12:27:14.932573 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8892 12:27:14.935700 == TX Byte 1 ==
8893 12:27:14.938939 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8894 12:27:14.942732 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8895 12:27:14.942817 ==
8896 12:27:14.945749 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 12:27:14.952052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 12:27:14.952144 ==
8899 12:27:14.963498
8900 12:27:14.967235 TX Vref early break, caculate TX vref
8901 12:27:14.970455 TX Vref=16, minBit 0, minWin=23, winSum=382
8902 12:27:14.973490 TX Vref=18, minBit 1, minWin=22, winSum=392
8903 12:27:14.977235 TX Vref=20, minBit 6, minWin=23, winSum=402
8904 12:27:14.980415 TX Vref=22, minBit 1, minWin=24, winSum=412
8905 12:27:14.983543 TX Vref=24, minBit 1, minWin=24, winSum=416
8906 12:27:14.989822 TX Vref=26, minBit 0, minWin=25, winSum=424
8907 12:27:14.993541 TX Vref=28, minBit 0, minWin=24, winSum=421
8908 12:27:14.996597 TX Vref=30, minBit 0, minWin=24, winSum=416
8909 12:27:15.000325 TX Vref=32, minBit 0, minWin=24, winSum=407
8910 12:27:15.003379 TX Vref=34, minBit 0, minWin=23, winSum=398
8911 12:27:15.010229 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8912 12:27:15.010325
8913 12:27:15.013330 Final TX Range 0 Vref 26
8914 12:27:15.013418
8915 12:27:15.013484 ==
8916 12:27:15.016429 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 12:27:15.019652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 12:27:15.019734 ==
8919 12:27:15.019807
8920 12:27:15.019869
8921 12:27:15.023329 TX Vref Scan disable
8922 12:27:15.029941 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8923 12:27:15.030021 == TX Byte 0 ==
8924 12:27:15.033074 u2DelayCellOfst[0]=18 cells (5 PI)
8925 12:27:15.036612 u2DelayCellOfst[1]=11 cells (3 PI)
8926 12:27:15.039924 u2DelayCellOfst[2]=0 cells (0 PI)
8927 12:27:15.043115 u2DelayCellOfst[3]=7 cells (2 PI)
8928 12:27:15.046355 u2DelayCellOfst[4]=7 cells (2 PI)
8929 12:27:15.049429 u2DelayCellOfst[5]=22 cells (6 PI)
8930 12:27:15.053211 u2DelayCellOfst[6]=18 cells (5 PI)
8931 12:27:15.056399 u2DelayCellOfst[7]=7 cells (2 PI)
8932 12:27:15.059674 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8933 12:27:15.062841 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8934 12:27:15.066049 == TX Byte 1 ==
8935 12:27:15.066157 u2DelayCellOfst[8]=0 cells (0 PI)
8936 12:27:15.069943 u2DelayCellOfst[9]=7 cells (2 PI)
8937 12:27:15.073113 u2DelayCellOfst[10]=11 cells (3 PI)
8938 12:27:15.076315 u2DelayCellOfst[11]=7 cells (2 PI)
8939 12:27:15.079388 u2DelayCellOfst[12]=14 cells (4 PI)
8940 12:27:15.082696 u2DelayCellOfst[13]=18 cells (5 PI)
8941 12:27:15.086586 u2DelayCellOfst[14]=18 cells (5 PI)
8942 12:27:15.089312 u2DelayCellOfst[15]=18 cells (5 PI)
8943 12:27:15.093036 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8944 12:27:15.099431 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8945 12:27:15.099544 DramC Write-DBI on
8946 12:27:15.099643 ==
8947 12:27:15.102684 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 12:27:15.108978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 12:27:15.109102 ==
8950 12:27:15.109264
8951 12:27:15.109366
8952 12:27:15.109543 TX Vref Scan disable
8953 12:27:15.112972 == TX Byte 0 ==
8954 12:27:15.116496 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8955 12:27:15.119749 == TX Byte 1 ==
8956 12:27:15.122798 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8957 12:27:15.126095 DramC Write-DBI off
8958 12:27:15.126204
8959 12:27:15.126307 [DATLAT]
8960 12:27:15.126399 Freq=1600, CH1 RK1
8961 12:27:15.126488
8962 12:27:15.129856 DATLAT Default: 0xf
8963 12:27:15.129934 0, 0xFFFF, sum = 0
8964 12:27:15.133028 1, 0xFFFF, sum = 0
8965 12:27:15.133124 2, 0xFFFF, sum = 0
8966 12:27:15.136249 3, 0xFFFF, sum = 0
8967 12:27:15.139357 4, 0xFFFF, sum = 0
8968 12:27:15.139463 5, 0xFFFF, sum = 0
8969 12:27:15.142531 6, 0xFFFF, sum = 0
8970 12:27:15.142617 7, 0xFFFF, sum = 0
8971 12:27:15.145878 8, 0xFFFF, sum = 0
8972 12:27:15.145954 9, 0xFFFF, sum = 0
8973 12:27:15.149106 10, 0xFFFF, sum = 0
8974 12:27:15.149193 11, 0xFFFF, sum = 0
8975 12:27:15.152859 12, 0xFFFF, sum = 0
8976 12:27:15.152946 13, 0xFFFF, sum = 0
8977 12:27:15.156061 14, 0x0, sum = 1
8978 12:27:15.156175 15, 0x0, sum = 2
8979 12:27:15.159377 16, 0x0, sum = 3
8980 12:27:15.159479 17, 0x0, sum = 4
8981 12:27:15.162656 best_step = 15
8982 12:27:15.162732
8983 12:27:15.162807 ==
8984 12:27:15.165784 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 12:27:15.169565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 12:27:15.169651 ==
8987 12:27:15.172882 RX Vref Scan: 0
8988 12:27:15.172958
8989 12:27:15.173023 RX Vref 0 -> 0, step: 1
8990 12:27:15.173101
8991 12:27:15.175985 RX Delay 11 -> 252, step: 4
8992 12:27:15.179348 iDelay=199, Bit 0, Center 138 (87 ~ 190) 104
8993 12:27:15.185552 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
8994 12:27:15.188896 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
8995 12:27:15.192840 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
8996 12:27:15.195933 iDelay=199, Bit 4, Center 132 (75 ~ 190) 116
8997 12:27:15.199036 iDelay=199, Bit 5, Center 142 (91 ~ 194) 104
8998 12:27:15.205545 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
8999 12:27:15.208632 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9000 12:27:15.212365 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9001 12:27:15.215684 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9002 12:27:15.222514 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9003 12:27:15.225562 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9004 12:27:15.228844 iDelay=199, Bit 12, Center 134 (79 ~ 190) 112
9005 12:27:15.232145 iDelay=199, Bit 13, Center 134 (79 ~ 190) 112
9006 12:27:15.235101 iDelay=199, Bit 14, Center 132 (75 ~ 190) 116
9007 12:27:15.241652 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9008 12:27:15.241734 ==
9009 12:27:15.245364 Dram Type= 6, Freq= 0, CH_1, rank 1
9010 12:27:15.248655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9011 12:27:15.248740 ==
9012 12:27:15.248823 DQS Delay:
9013 12:27:15.251435 DQS0 = 0, DQS1 = 0
9014 12:27:15.251519 DQM Delay:
9015 12:27:15.254738 DQM0 = 133, DQM1 = 126
9016 12:27:15.254821 DQ Delay:
9017 12:27:15.258625 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9018 12:27:15.261788 DQ4 =132, DQ5 =142, DQ6 =144, DQ7 =130
9019 12:27:15.264960 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9020 12:27:15.271443 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =138
9021 12:27:15.271530
9022 12:27:15.271625
9023 12:27:15.271715
9024 12:27:15.271818 [DramC_TX_OE_Calibration] TA2
9025 12:27:15.274829 Original DQ_B0 (3 6) =30, OEN = 27
9026 12:27:15.278095 Original DQ_B1 (3 6) =30, OEN = 27
9027 12:27:15.281475 24, 0x0, End_B0=24 End_B1=24
9028 12:27:15.284642 25, 0x0, End_B0=25 End_B1=25
9029 12:27:15.287743 26, 0x0, End_B0=26 End_B1=26
9030 12:27:15.287826 27, 0x0, End_B0=27 End_B1=27
9031 12:27:15.291431 28, 0x0, End_B0=28 End_B1=28
9032 12:27:15.294762 29, 0x0, End_B0=29 End_B1=29
9033 12:27:15.298090 30, 0x0, End_B0=30 End_B1=30
9034 12:27:15.301395 31, 0x4141, End_B0=30 End_B1=30
9035 12:27:15.304491 Byte0 end_step=30 best_step=27
9036 12:27:15.304610 Byte1 end_step=30 best_step=27
9037 12:27:15.307873 Byte0 TX OE(2T, 0.5T) = (3, 3)
9038 12:27:15.311004 Byte1 TX OE(2T, 0.5T) = (3, 3)
9039 12:27:15.311087
9040 12:27:15.311152
9041 12:27:15.321302 [DQSOSCAuto] RK1, (LSB)MR18= 0xc09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9042 12:27:15.321388 CH1 RK1: MR19=303, MR18=C09
9043 12:27:15.327582 CH1_RK1: MR19=0x303, MR18=0xC09, DQSOSC=403, MR23=63, INC=22, DEC=15
9044 12:27:15.330614 [RxdqsGatingPostProcess] freq 1600
9045 12:27:15.337238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9046 12:27:15.341040 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 12:27:15.344130 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 12:27:15.347318 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 12:27:15.351116 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 12:27:15.351199 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 12:27:15.354293 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 12:27:15.357526 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 12:27:15.360819 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 12:27:15.364088 Pre-setting of DQS Precalculation
9055 12:27:15.370751 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9056 12:27:15.376920 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9057 12:27:15.383888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9058 12:27:15.383975
9059 12:27:15.384042
9060 12:27:15.386997 [Calibration Summary] 3200 Mbps
9061 12:27:15.387082 CH 0, Rank 0
9062 12:27:15.390144 SW Impedance : PASS
9063 12:27:15.393728 DUTY Scan : NO K
9064 12:27:15.393814 ZQ Calibration : PASS
9065 12:27:15.397044 Jitter Meter : NO K
9066 12:27:15.400227 CBT Training : PASS
9067 12:27:15.400311 Write leveling : PASS
9068 12:27:15.403388 RX DQS gating : PASS
9069 12:27:15.406600 RX DQ/DQS(RDDQC) : PASS
9070 12:27:15.406685 TX DQ/DQS : PASS
9071 12:27:15.410251 RX DATLAT : PASS
9072 12:27:15.413338 RX DQ/DQS(Engine): PASS
9073 12:27:15.413422 TX OE : PASS
9074 12:27:15.416461 All Pass.
9075 12:27:15.416570
9076 12:27:15.416638 CH 0, Rank 1
9077 12:27:15.420223 SW Impedance : PASS
9078 12:27:15.420307 DUTY Scan : NO K
9079 12:27:15.423455 ZQ Calibration : PASS
9080 12:27:15.426481 Jitter Meter : NO K
9081 12:27:15.426563 CBT Training : PASS
9082 12:27:15.430132 Write leveling : PASS
9083 12:27:15.433254 RX DQS gating : PASS
9084 12:27:15.433334 RX DQ/DQS(RDDQC) : PASS
9085 12:27:15.436381 TX DQ/DQS : PASS
9086 12:27:15.436483 RX DATLAT : PASS
9087 12:27:15.440090 RX DQ/DQS(Engine): PASS
9088 12:27:15.443166 TX OE : PASS
9089 12:27:15.443269 All Pass.
9090 12:27:15.443361
9091 12:27:15.443450 CH 1, Rank 0
9092 12:27:15.446593 SW Impedance : PASS
9093 12:27:15.449831 DUTY Scan : NO K
9094 12:27:15.449912 ZQ Calibration : PASS
9095 12:27:15.452937 Jitter Meter : NO K
9096 12:27:15.455947 CBT Training : PASS
9097 12:27:15.456060 Write leveling : PASS
9098 12:27:15.459939 RX DQS gating : PASS
9099 12:27:15.463156 RX DQ/DQS(RDDQC) : PASS
9100 12:27:15.463265 TX DQ/DQS : PASS
9101 12:27:15.466529 RX DATLAT : PASS
9102 12:27:15.469762 RX DQ/DQS(Engine): PASS
9103 12:27:15.469846 TX OE : PASS
9104 12:27:15.472961 All Pass.
9105 12:27:15.473043
9106 12:27:15.473107 CH 1, Rank 1
9107 12:27:15.476164 SW Impedance : PASS
9108 12:27:15.476276 DUTY Scan : NO K
9109 12:27:15.479416 ZQ Calibration : PASS
9110 12:27:15.482633 Jitter Meter : NO K
9111 12:27:15.482735 CBT Training : PASS
9112 12:27:15.485902 Write leveling : PASS
9113 12:27:15.489041 RX DQS gating : PASS
9114 12:27:15.489123 RX DQ/DQS(RDDQC) : PASS
9115 12:27:15.492227 TX DQ/DQS : PASS
9116 12:27:15.495936 RX DATLAT : PASS
9117 12:27:15.496019 RX DQ/DQS(Engine): PASS
9118 12:27:15.499099 TX OE : PASS
9119 12:27:15.499222 All Pass.
9120 12:27:15.499319
9121 12:27:15.502285 DramC Write-DBI on
9122 12:27:15.505556 PER_BANK_REFRESH: Hybrid Mode
9123 12:27:15.505639 TX_TRACKING: ON
9124 12:27:15.515611 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9125 12:27:15.521988 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9126 12:27:15.528436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9127 12:27:15.532062 [FAST_K] Save calibration result to emmc
9128 12:27:15.535225 sync common calibartion params.
9129 12:27:15.538456 sync cbt_mode0:1, 1:1
9130 12:27:15.541619 dram_init: ddr_geometry: 2
9131 12:27:15.541701 dram_init: ddr_geometry: 2
9132 12:27:15.545400 dram_init: ddr_geometry: 2
9133 12:27:15.548524 0:dram_rank_size:100000000
9134 12:27:15.551623 1:dram_rank_size:100000000
9135 12:27:15.554800 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9136 12:27:15.558303 DFS_SHUFFLE_HW_MODE: ON
9137 12:27:15.561584 dramc_set_vcore_voltage set vcore to 725000
9138 12:27:15.564987 Read voltage for 1600, 0
9139 12:27:15.565089 Vio18 = 0
9140 12:27:15.568168 Vcore = 725000
9141 12:27:15.568304 Vdram = 0
9142 12:27:15.568425 Vddq = 0
9143 12:27:15.568529 Vmddr = 0
9144 12:27:15.571250 switch to 3200 Mbps bootup
9145 12:27:15.574527 [DramcRunTimeConfig]
9146 12:27:15.574607 PHYPLL
9147 12:27:15.577808 DPM_CONTROL_AFTERK: ON
9148 12:27:15.577889 PER_BANK_REFRESH: ON
9149 12:27:15.581068 REFRESH_OVERHEAD_REDUCTION: ON
9150 12:27:15.584807 CMD_PICG_NEW_MODE: OFF
9151 12:27:15.584904 XRTWTW_NEW_MODE: ON
9152 12:27:15.587759 XRTRTR_NEW_MODE: ON
9153 12:27:15.587849 TX_TRACKING: ON
9154 12:27:15.590932 RDSEL_TRACKING: OFF
9155 12:27:15.594233 DQS Precalculation for DVFS: ON
9156 12:27:15.594308 RX_TRACKING: OFF
9157 12:27:15.597668 HW_GATING DBG: ON
9158 12:27:15.597739 ZQCS_ENABLE_LP4: ON
9159 12:27:15.600857 RX_PICG_NEW_MODE: ON
9160 12:27:15.600927 TX_PICG_NEW_MODE: ON
9161 12:27:15.604620 ENABLE_RX_DCM_DPHY: ON
9162 12:27:15.607860 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9163 12:27:15.611071 DUMMY_READ_FOR_TRACKING: OFF
9164 12:27:15.611152 !!! SPM_CONTROL_AFTERK: OFF
9165 12:27:15.614265 !!! SPM could not control APHY
9166 12:27:15.617445 IMPEDANCE_TRACKING: ON
9167 12:27:15.617529 TEMP_SENSOR: ON
9168 12:27:15.620825 HW_SAVE_FOR_SR: OFF
9169 12:27:15.623874 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9170 12:27:15.627141 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9171 12:27:15.627224 Read ODT Tracking: ON
9172 12:27:15.630299 Refresh Rate DeBounce: ON
9173 12:27:15.634211 DFS_NO_QUEUE_FLUSH: ON
9174 12:27:15.637372 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9175 12:27:15.637473 ENABLE_DFS_RUNTIME_MRW: OFF
9176 12:27:15.640570 DDR_RESERVE_NEW_MODE: ON
9177 12:27:15.643793 MR_CBT_SWITCH_FREQ: ON
9178 12:27:15.643877 =========================
9179 12:27:15.664483 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9180 12:27:15.667833 dram_init: ddr_geometry: 2
9181 12:27:15.686020 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9182 12:27:15.689040 dram_init: dram init end (result: 0)
9183 12:27:15.695683 DRAM-K: Full calibration passed in 24589 msecs
9184 12:27:15.698935 MRC: failed to locate region type 0.
9185 12:27:15.699013 DRAM rank0 size:0x100000000,
9186 12:27:15.702199 DRAM rank1 size=0x100000000
9187 12:27:15.711589 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9188 12:27:15.718774 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9189 12:27:15.728410 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9190 12:27:15.734973 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9191 12:27:15.735067 DRAM rank0 size:0x100000000,
9192 12:27:15.738163 DRAM rank1 size=0x100000000
9193 12:27:15.738263 CBMEM:
9194 12:27:15.741925 IMD: root @ 0xfffff000 254 entries.
9195 12:27:15.745097 IMD: root @ 0xffffec00 62 entries.
9196 12:27:15.751257 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9197 12:27:15.755068 WARNING: RO_VPD is uninitialized or empty.
9198 12:27:15.758293 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9199 12:27:15.765914 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9200 12:27:15.778672 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9201 12:27:15.789829 BS: romstage times (exec / console): total (unknown) / 24086 ms
9202 12:27:15.789928
9203 12:27:15.789996
9204 12:27:15.800223 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9205 12:27:15.803478 ARM64: Exception handlers installed.
9206 12:27:15.806786 ARM64: Testing exception
9207 12:27:15.809911 ARM64: Done test exception
9208 12:27:15.810001 Enumerating buses...
9209 12:27:15.812931 Show all devs... Before device enumeration.
9210 12:27:15.816135 Root Device: enabled 1
9211 12:27:15.819362 CPU_CLUSTER: 0: enabled 1
9212 12:27:15.819446 CPU: 00: enabled 1
9213 12:27:15.823247 Compare with tree...
9214 12:27:15.823330 Root Device: enabled 1
9215 12:27:15.826447 CPU_CLUSTER: 0: enabled 1
9216 12:27:15.829549 CPU: 00: enabled 1
9217 12:27:15.829633 Root Device scanning...
9218 12:27:15.832648 scan_static_bus for Root Device
9219 12:27:15.835751 CPU_CLUSTER: 0 enabled
9220 12:27:15.839794 scan_static_bus for Root Device done
9221 12:27:15.842961 scan_bus: bus Root Device finished in 8 msecs
9222 12:27:15.843044 done
9223 12:27:15.849345 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9224 12:27:15.852611 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9225 12:27:15.859420 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9226 12:27:15.862610 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9227 12:27:15.865836 Allocating resources...
9228 12:27:15.869088 Reading resources...
9229 12:27:15.872271 Root Device read_resources bus 0 link: 0
9230 12:27:15.875565 DRAM rank0 size:0x100000000,
9231 12:27:15.875648 DRAM rank1 size=0x100000000
9232 12:27:15.882021 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9233 12:27:15.882108 CPU: 00 missing read_resources
9234 12:27:15.889069 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9235 12:27:15.892278 Root Device read_resources bus 0 link: 0 done
9236 12:27:15.895416 Done reading resources.
9237 12:27:15.898661 Show resources in subtree (Root Device)...After reading.
9238 12:27:15.901906 Root Device child on link 0 CPU_CLUSTER: 0
9239 12:27:15.905290 CPU_CLUSTER: 0 child on link 0 CPU: 00
9240 12:27:15.915053 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9241 12:27:15.915140 CPU: 00
9242 12:27:15.918327 Root Device assign_resources, bus 0 link: 0
9243 12:27:15.921582 CPU_CLUSTER: 0 missing set_resources
9244 12:27:15.928586 Root Device assign_resources, bus 0 link: 0 done
9245 12:27:15.928673 Done setting resources.
9246 12:27:15.934770 Show resources in subtree (Root Device)...After assigning values.
9247 12:27:15.937980 Root Device child on link 0 CPU_CLUSTER: 0
9248 12:27:15.941905 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 12:27:15.951560 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 12:27:15.951647 CPU: 00
9251 12:27:15.954632 Done allocating resources.
9252 12:27:15.961397 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9253 12:27:15.961483 Enabling resources...
9254 12:27:15.964415 done.
9255 12:27:15.968250 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9256 12:27:15.971511 Initializing devices...
9257 12:27:15.971599 Root Device init
9258 12:27:15.974630 init hardware done!
9259 12:27:15.974717 0x00000018: ctrlr->caps
9260 12:27:15.977980 52.000 MHz: ctrlr->f_max
9261 12:27:15.981228 0.400 MHz: ctrlr->f_min
9262 12:27:15.981319 0x40ff8080: ctrlr->voltages
9263 12:27:15.984475 sclk: 390625
9264 12:27:15.984575 Bus Width = 1
9265 12:27:15.988167 sclk: 390625
9266 12:27:15.988277 Bus Width = 1
9267 12:27:15.990952 Early init status = 3
9268 12:27:15.994295 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9269 12:27:15.997524 in-header: 03 fc 00 00 01 00 00 00
9270 12:27:16.001224 in-data: 00
9271 12:27:16.004382 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9272 12:27:16.008915 in-header: 03 fd 00 00 00 00 00 00
9273 12:27:16.012084 in-data:
9274 12:27:16.015307 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9275 12:27:16.019187 in-header: 03 fc 00 00 01 00 00 00
9276 12:27:16.023035 in-data: 00
9277 12:27:16.026227 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9278 12:27:16.030690 in-header: 03 fd 00 00 00 00 00 00
9279 12:27:16.034118 in-data:
9280 12:27:16.037338 [SSUSB] Setting up USB HOST controller...
9281 12:27:16.040352 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9282 12:27:16.043572 [SSUSB] phy power-on done.
9283 12:27:16.047315 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9284 12:27:16.053474 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9285 12:27:16.056705 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9286 12:27:16.063713 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9287 12:27:16.070395 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9288 12:27:16.076794 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9289 12:27:16.083268 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9290 12:27:16.089753 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9291 12:27:16.092945 SPM: binary array size = 0x9dc
9292 12:27:16.096170 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9293 12:27:16.103279 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9294 12:27:16.109680 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9295 12:27:16.116228 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9296 12:27:16.119511 configure_display: Starting display init
9297 12:27:16.154347 anx7625_power_on_init: Init interface.
9298 12:27:16.157543 anx7625_disable_pd_protocol: Disabled PD feature.
9299 12:27:16.160329 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9300 12:27:16.188504 anx7625_start_dp_work: Secure OCM version=00
9301 12:27:16.191437 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9302 12:27:16.206259 sp_tx_get_edid_block: EDID Block = 1
9303 12:27:16.309150 Extracted contents:
9304 12:27:16.312357 header: 00 ff ff ff ff ff ff 00
9305 12:27:16.315507 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9306 12:27:16.318825 version: 01 04
9307 12:27:16.322061 basic params: 95 1f 11 78 0a
9308 12:27:16.325355 chroma info: 76 90 94 55 54 90 27 21 50 54
9309 12:27:16.328541 established: 00 00 00
9310 12:27:16.335599 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9311 12:27:16.338858 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9312 12:27:16.345267 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9313 12:27:16.352151 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9314 12:27:16.358488 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9315 12:27:16.361735 extensions: 00
9316 12:27:16.361818 checksum: fb
9317 12:27:16.361883
9318 12:27:16.365392 Manufacturer: IVO Model 57d Serial Number 0
9319 12:27:16.368638 Made week 0 of 2020
9320 12:27:16.368721 EDID version: 1.4
9321 12:27:16.371834 Digital display
9322 12:27:16.375006 6 bits per primary color channel
9323 12:27:16.375090 DisplayPort interface
9324 12:27:16.378202 Maximum image size: 31 cm x 17 cm
9325 12:27:16.382006 Gamma: 220%
9326 12:27:16.382091 Check DPMS levels
9327 12:27:16.385079 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9328 12:27:16.391957 First detailed timing is preferred timing
9329 12:27:16.392043 Established timings supported:
9330 12:27:16.395044 Standard timings supported:
9331 12:27:16.398120 Detailed timings
9332 12:27:16.401882 Hex of detail: 383680a07038204018303c0035ae10000019
9333 12:27:16.408180 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9334 12:27:16.411503 0780 0798 07c8 0820 hborder 0
9335 12:27:16.414674 0438 043b 0447 0458 vborder 0
9336 12:27:16.418491 -hsync -vsync
9337 12:27:16.418585 Did detailed timing
9338 12:27:16.424880 Hex of detail: 000000000000000000000000000000000000
9339 12:27:16.428122 Manufacturer-specified data, tag 0
9340 12:27:16.431364 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9341 12:27:16.434598 ASCII string: InfoVision
9342 12:27:16.437731 Hex of detail: 000000fe00523134304e574635205248200a
9343 12:27:16.441055 ASCII string: R140NWF5 RH
9344 12:27:16.441199 Checksum
9345 12:27:16.444856 Checksum: 0xfb (valid)
9346 12:27:16.448074 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9347 12:27:16.451196 DSI data_rate: 832800000 bps
9348 12:27:16.458077 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9349 12:27:16.461084 anx7625_parse_edid: pixelclock(138800).
9350 12:27:16.464361 hactive(1920), hsync(48), hfp(24), hbp(88)
9351 12:27:16.467423 vactive(1080), vsync(12), vfp(3), vbp(17)
9352 12:27:16.471125 anx7625_dsi_config: config dsi.
9353 12:27:16.477569 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9354 12:27:16.491372 anx7625_dsi_config: success to config DSI
9355 12:27:16.494496 anx7625_dp_start: MIPI phy setup OK.
9356 12:27:16.497573 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9357 12:27:16.501090 mtk_ddp_mode_set invalid vrefresh 60
9358 12:27:16.504304 main_disp_path_setup
9359 12:27:16.504829 ovl_layer_smi_id_en
9360 12:27:16.507370 ovl_layer_smi_id_en
9361 12:27:16.507925 ccorr_config
9362 12:27:16.508290 aal_config
9363 12:27:16.511217 gamma_config
9364 12:27:16.511769 postmask_config
9365 12:27:16.514382 dither_config
9366 12:27:16.517701 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9367 12:27:16.524591 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9368 12:27:16.527853 Root Device init finished in 552 msecs
9369 12:27:16.531014 CPU_CLUSTER: 0 init
9370 12:27:16.537720 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9371 12:27:16.544021 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9372 12:27:16.544450 APU_MBOX 0x190000b0 = 0x10001
9373 12:27:16.547201 APU_MBOX 0x190001b0 = 0x10001
9374 12:27:16.551095 APU_MBOX 0x190005b0 = 0x10001
9375 12:27:16.553949 APU_MBOX 0x190006b0 = 0x10001
9376 12:27:16.560375 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9377 12:27:16.570049 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9378 12:27:16.582448 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9379 12:27:16.589280 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9380 12:27:16.600433 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9381 12:27:16.610133 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9382 12:27:16.613450 CPU_CLUSTER: 0 init finished in 81 msecs
9383 12:27:16.616626 Devices initialized
9384 12:27:16.619959 Show all devs... After init.
9385 12:27:16.620063 Root Device: enabled 1
9386 12:27:16.622982 CPU_CLUSTER: 0: enabled 1
9387 12:27:16.626347 CPU: 00: enabled 1
9388 12:27:16.629570 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9389 12:27:16.633329 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9390 12:27:16.636423 ELOG: NV offset 0x57f000 size 0x1000
9391 12:27:16.643319 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9392 12:27:16.649653 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9393 12:27:16.653003 ELOG: Event(17) added with size 13 at 2023-06-06 12:27:16 UTC
9394 12:27:16.660011 out: cmd=0x121: 03 db 21 01 00 00 00 00
9395 12:27:16.663069 in-header: 03 e1 00 00 2c 00 00 00
9396 12:27:16.673216 in-data: 7e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 12:27:16.679336 ELOG: Event(A1) added with size 10 at 2023-06-06 12:27:16 UTC
9398 12:27:16.686221 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9399 12:27:16.692967 ELOG: Event(A0) added with size 9 at 2023-06-06 12:27:16 UTC
9400 12:27:16.695844 elog_add_boot_reason: Logged dev mode boot
9401 12:27:16.702729 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9402 12:27:16.703304 Finalize devices...
9403 12:27:16.705934 Devices finalized
9404 12:27:16.708908 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9405 12:27:16.712727 Writing coreboot table at 0xffe64000
9406 12:27:16.715830 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 12:27:16.722725 1. 0000000040000000-00000000400fffff: RAM
9408 12:27:16.725955 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 12:27:16.729069 3. 000000004032b000-00000000545fffff: RAM
9410 12:27:16.732210 4. 0000000054600000-000000005465ffff: BL31
9411 12:27:16.735432 5. 0000000054660000-00000000ffe63fff: RAM
9412 12:27:16.742748 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 12:27:16.745741 7. 0000000100000000-000000023fffffff: RAM
9414 12:27:16.748805 Passing 5 GPIOs to payload:
9415 12:27:16.752594 NAME | PORT | POLARITY | VALUE
9416 12:27:16.758542 EC in RW | 0x000000aa | low | undefined
9417 12:27:16.762290 EC interrupt | 0x00000005 | low | undefined
9418 12:27:16.765437 TPM interrupt | 0x000000ab | high | undefined
9419 12:27:16.772181 SD card detect | 0x00000011 | high | undefined
9420 12:27:16.775220 speaker enable | 0x00000093 | high | undefined
9421 12:27:16.778393 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 12:27:16.782126 in-header: 03 f9 00 00 02 00 00 00
9423 12:27:16.785261 in-data: 02 00
9424 12:27:16.788857 ADC[4]: Raw value=903031 ID=7
9425 12:27:16.791885 ADC[3]: Raw value=212912 ID=1
9426 12:27:16.792446 RAM Code: 0x71
9427 12:27:16.795659 ADC[6]: Raw value=75036 ID=0
9428 12:27:16.798817 ADC[5]: Raw value=212912 ID=1
9429 12:27:16.799371 SKU Code: 0x1
9430 12:27:16.805584 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9431 12:27:16.806006 coreboot table: 964 bytes.
9432 12:27:16.808463 IMD ROOT 0. 0xfffff000 0x00001000
9433 12:27:16.812208 IMD SMALL 1. 0xffffe000 0x00001000
9434 12:27:16.815561 RO MCACHE 2. 0xffffc000 0x00001104
9435 12:27:16.818541 CONSOLE 3. 0xfff7c000 0x00080000
9436 12:27:16.821662 FMAP 4. 0xfff7b000 0x00000452
9437 12:27:16.824958 TIME STAMP 5. 0xfff7a000 0x00000910
9438 12:27:16.828589 VBOOT WORK 6. 0xfff66000 0x00014000
9439 12:27:16.831814 RAMOOPS 7. 0xffe66000 0x00100000
9440 12:27:16.834945 COREBOOT 8. 0xffe64000 0x00002000
9441 12:27:16.838726 IMD small region:
9442 12:27:16.841769 IMD ROOT 0. 0xffffec00 0x00000400
9443 12:27:16.844920 VPD 1. 0xffffeba0 0x0000004c
9444 12:27:16.848230 MMC STATUS 2. 0xffffeb80 0x00000004
9445 12:27:16.851875 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 12:27:16.855077 Probing TPM: done!
9447 12:27:16.858799 Connected to device vid:did:rid of 1ae0:0028:00
9448 12:27:16.870000 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9449 12:27:16.873035 Initialized TPM device CR50 revision 0
9450 12:27:16.876711 Checking cr50 for pending updates
9451 12:27:16.880440 Reading cr50 TPM mode
9452 12:27:16.889312 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9453 12:27:16.895563 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9454 12:27:16.935493 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9455 12:27:16.938654 Checking segment from ROM address 0x40100000
9456 12:27:16.941757 Checking segment from ROM address 0x4010001c
9457 12:27:16.948743 Loading segment from ROM address 0x40100000
9458 12:27:16.948856 code (compression=0)
9459 12:27:16.958330 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9460 12:27:16.964930 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9461 12:27:16.965041 it's not compressed!
9462 12:27:16.972003 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9463 12:27:16.978066 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9464 12:27:16.995843 Loading segment from ROM address 0x4010001c
9465 12:27:16.995935 Entry Point 0x80000000
9466 12:27:16.999386 Loaded segments
9467 12:27:17.002594 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9468 12:27:17.008899 Jumping to boot code at 0x80000000(0xffe64000)
9469 12:27:17.015864 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9470 12:27:17.022297 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9471 12:27:17.029865 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9472 12:27:17.033070 Checking segment from ROM address 0x40100000
9473 12:27:17.036363 Checking segment from ROM address 0x4010001c
9474 12:27:17.043447 Loading segment from ROM address 0x40100000
9475 12:27:17.043528 code (compression=1)
9476 12:27:17.049669 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9477 12:27:17.059935 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9478 12:27:17.060018 using LZMA
9479 12:27:17.068473 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9480 12:27:17.074969 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9481 12:27:17.078808 Loading segment from ROM address 0x4010001c
9482 12:27:17.078897 Entry Point 0x54601000
9483 12:27:17.081793 Loaded segments
9484 12:27:17.085020 NOTICE: MT8192 bl31_setup
9485 12:27:17.092363 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9486 12:27:17.095462 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9487 12:27:17.099279 WARNING: region 0:
9488 12:27:17.102451 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 12:27:17.102590 WARNING: region 1:
9490 12:27:17.108730 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9491 12:27:17.112414 WARNING: region 2:
9492 12:27:17.115587 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9493 12:27:17.118777 WARNING: region 3:
9494 12:27:17.121817 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 12:27:17.125684 WARNING: region 4:
9496 12:27:17.132020 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 12:27:17.132104 WARNING: region 5:
9498 12:27:17.135188 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 12:27:17.138889 WARNING: region 6:
9500 12:27:17.142077 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 12:27:17.145284 WARNING: region 7:
9502 12:27:17.148360 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 12:27:17.155434 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9504 12:27:17.158870 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9505 12:27:17.161916 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9506 12:27:17.168170 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9507 12:27:17.171432 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9508 12:27:17.178609 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9509 12:27:17.181521 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9510 12:27:17.184741 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9511 12:27:17.191601 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9512 12:27:17.194854 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9513 12:27:17.198001 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9514 12:27:17.205011 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9515 12:27:17.208216 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9516 12:27:17.214680 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9517 12:27:17.218341 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9518 12:27:17.221505 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9519 12:27:17.227712 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9520 12:27:17.231039 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9521 12:27:17.237810 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9522 12:27:17.241055 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9523 12:27:17.244271 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9524 12:27:17.251078 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9525 12:27:17.254260 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9526 12:27:17.257728 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9527 12:27:17.264226 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9528 12:27:17.268167 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9529 12:27:17.274733 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9530 12:27:17.278029 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9531 12:27:17.281234 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9532 12:27:17.287589 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9533 12:27:17.291096 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9534 12:27:17.298049 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9535 12:27:17.301137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9536 12:27:17.304358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9537 12:27:17.307521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9538 12:27:17.314538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9539 12:27:17.317553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9540 12:27:17.320750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9541 12:27:17.323867 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9542 12:27:17.330609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9543 12:27:17.333920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9544 12:27:17.337207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9545 12:27:17.340922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9546 12:27:17.347416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9547 12:27:17.350718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9548 12:27:17.353844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9549 12:27:17.360962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9550 12:27:17.364013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9551 12:27:17.367375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9552 12:27:17.374196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9553 12:27:17.377266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9554 12:27:17.383692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9555 12:27:17.387406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9556 12:27:17.390475 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9557 12:27:17.397173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9558 12:27:17.400040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9559 12:27:17.406999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9560 12:27:17.410085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9561 12:27:17.416849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9562 12:27:17.419882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9563 12:27:17.423771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9564 12:27:17.430452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9565 12:27:17.433461 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9566 12:27:17.440417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9567 12:27:17.443585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9568 12:27:17.449881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9569 12:27:17.453213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9570 12:27:17.460303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9571 12:27:17.463375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9572 12:27:17.466615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9573 12:27:17.472925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9574 12:27:17.476718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9575 12:27:17.482799 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9576 12:27:17.486559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9577 12:27:17.492873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9578 12:27:17.496593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9579 12:27:17.503315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9580 12:27:17.506454 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9581 12:27:17.509730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9582 12:27:17.515969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9583 12:27:17.519481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9584 12:27:17.525858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9585 12:27:17.529514 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9586 12:27:17.535813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9587 12:27:17.539449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9588 12:27:17.542694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9589 12:27:17.549506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9590 12:27:17.552705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9591 12:27:17.559806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9592 12:27:17.562810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9593 12:27:17.569703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9594 12:27:17.572984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9595 12:27:17.579448 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9596 12:27:17.582716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9597 12:27:17.585827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9598 12:27:17.592320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9599 12:27:17.596119 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9600 12:27:17.599238 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9601 12:27:17.605792 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9602 12:27:17.608902 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9603 12:27:17.612123 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9604 12:27:17.618954 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9605 12:27:17.622220 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9606 12:27:17.625459 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9607 12:27:17.632418 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9608 12:27:17.635574 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9609 12:27:17.642611 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9610 12:27:17.645679 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9611 12:27:17.648782 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9612 12:27:17.655770 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9613 12:27:17.658740 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9614 12:27:17.665748 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9615 12:27:17.668852 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9616 12:27:17.671917 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9617 12:27:17.678310 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9618 12:27:17.682153 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9619 12:27:17.685239 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9620 12:27:17.692024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9621 12:27:17.695199 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9622 12:27:17.698453 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9623 12:27:17.705229 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9624 12:27:17.708842 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9625 12:27:17.711968 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9626 12:27:17.715069 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9627 12:27:17.721857 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9628 12:27:17.725071 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9629 12:27:17.731924 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9630 12:27:17.734932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9631 12:27:17.737963 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9632 12:27:17.744829 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9633 12:27:17.748314 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9634 12:27:17.754693 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9635 12:27:17.758371 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9636 12:27:17.761460 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9637 12:27:17.767998 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9638 12:27:17.771245 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9639 12:27:17.778265 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9640 12:27:17.781393 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9641 12:27:17.784549 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9642 12:27:17.791620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9643 12:27:17.794743 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9644 12:27:17.797866 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9645 12:27:17.804961 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9646 12:27:17.808073 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9647 12:27:17.814256 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9648 12:27:17.818006 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9649 12:27:17.821234 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9650 12:27:17.827978 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9651 12:27:17.831068 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9652 12:27:17.837971 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9653 12:27:17.841139 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9654 12:27:17.844322 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9655 12:27:17.851202 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9656 12:27:17.854367 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9657 12:27:17.860927 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9658 12:27:17.863981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9659 12:27:17.867827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9660 12:27:17.874276 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9661 12:27:17.877473 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9662 12:27:17.884200 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9663 12:27:17.887468 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9664 12:27:17.890692 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9665 12:27:17.897074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9666 12:27:17.900253 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9667 12:27:17.907163 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9668 12:27:17.910352 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9669 12:27:17.913621 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9670 12:27:17.920386 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9671 12:27:17.923515 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9672 12:27:17.930340 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9673 12:27:17.933530 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9674 12:27:17.936606 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9675 12:27:17.943575 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9676 12:27:17.946818 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9677 12:27:17.953092 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9678 12:27:17.956233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9679 12:27:17.960046 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9680 12:27:17.966396 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9681 12:27:17.969529 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9682 12:27:17.976066 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9683 12:27:17.979889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9684 12:27:17.983122 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9685 12:27:17.989687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9686 12:27:17.992858 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9687 12:27:17.999220 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9688 12:27:18.002517 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9689 12:27:18.005774 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9690 12:27:18.012957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9691 12:27:18.016071 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9692 12:27:18.022388 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9693 12:27:18.025721 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9694 12:27:18.032176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9695 12:27:18.035934 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9696 12:27:18.038932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9697 12:27:18.045473 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9698 12:27:18.048496 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9699 12:27:18.055412 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9700 12:27:18.058565 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9701 12:27:18.065034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9702 12:27:18.068339 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9703 12:27:18.072137 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9704 12:27:18.078423 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9705 12:27:18.081579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9706 12:27:18.088577 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9707 12:27:18.091735 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9708 12:27:18.098635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9709 12:27:18.101768 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9710 12:27:18.104901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9711 12:27:18.111236 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9712 12:27:18.115044 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9713 12:27:18.121282 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9714 12:27:18.125136 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9715 12:27:18.128131 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9716 12:27:18.134483 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9717 12:27:18.138149 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9718 12:27:18.144368 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9719 12:27:18.148265 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9720 12:27:18.154406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9721 12:27:18.157566 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9722 12:27:18.160801 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9723 12:27:18.167752 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9724 12:27:18.170861 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9725 12:27:18.177583 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9726 12:27:18.180785 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9727 12:27:18.187169 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9728 12:27:18.190316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9729 12:27:18.193654 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9730 12:27:18.200228 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9731 12:27:18.203516 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9732 12:27:18.206736 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9733 12:27:18.213484 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9734 12:27:18.216778 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9735 12:27:18.219968 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9736 12:27:18.223816 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9737 12:27:18.230305 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9738 12:27:18.233278 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9739 12:27:18.240357 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9740 12:27:18.243446 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9741 12:27:18.246545 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9742 12:27:18.253207 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9743 12:27:18.256369 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9744 12:27:18.260154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9745 12:27:18.266503 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9746 12:27:18.269648 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9747 12:27:18.276276 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9748 12:27:18.280040 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9749 12:27:18.283344 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9750 12:27:18.289758 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9751 12:27:18.292881 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9752 12:27:18.296023 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9753 12:27:18.302498 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9754 12:27:18.305799 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9755 12:27:18.312683 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9756 12:27:18.315978 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9757 12:27:18.319252 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9758 12:27:18.325671 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9759 12:27:18.329457 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9760 12:27:18.335793 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9761 12:27:18.338971 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9762 12:27:18.342301 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9763 12:27:18.349184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9764 12:27:18.352316 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9765 12:27:18.355719 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9766 12:27:18.362585 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9767 12:27:18.365805 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9768 12:27:18.368827 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9769 12:27:18.375573 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9770 12:27:18.378865 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9771 12:27:18.381810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9772 12:27:18.388836 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9773 12:27:18.391900 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9774 12:27:18.395255 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9775 12:27:18.398368 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9776 12:27:18.404858 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9777 12:27:18.408213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9778 12:27:18.411977 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9779 12:27:18.415112 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9780 12:27:18.421404 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9781 12:27:18.425281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9782 12:27:18.428465 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9783 12:27:18.434797 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9784 12:27:18.437935 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9785 12:27:18.441557 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9786 12:27:18.447767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9787 12:27:18.451454 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9788 12:27:18.457905 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9789 12:27:18.461052 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9790 12:27:18.464799 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9791 12:27:18.471437 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9792 12:27:18.474446 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9793 12:27:18.481218 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9794 12:27:18.484414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9795 12:27:18.487467 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9796 12:27:18.494467 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9797 12:27:18.497580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9798 12:27:18.503906 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9799 12:27:18.507734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9800 12:27:18.511004 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9801 12:27:18.517340 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9802 12:27:18.520337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9803 12:27:18.527390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9804 12:27:18.530637 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9805 12:27:18.536776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9806 12:27:18.540507 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9807 12:27:18.546712 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9808 12:27:18.550583 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9809 12:27:18.553709 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9810 12:27:18.559823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9811 12:27:18.563111 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9812 12:27:18.570165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9813 12:27:18.573214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9814 12:27:18.576337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9815 12:27:18.583104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9816 12:27:18.586149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9817 12:27:18.593041 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9818 12:27:18.596202 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9819 12:27:18.599400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9820 12:27:18.606308 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9821 12:27:18.609702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9822 12:27:18.616033 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9823 12:27:18.619287 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9824 12:27:18.622373 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9825 12:27:18.629374 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9826 12:27:18.632547 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9827 12:27:18.638952 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9828 12:27:18.642736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9829 12:27:18.648880 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9830 12:27:18.652707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9831 12:27:18.658816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9832 12:27:18.662381 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9833 12:27:18.665458 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9834 12:27:18.672362 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9835 12:27:18.675416 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9836 12:27:18.682161 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9837 12:27:18.685219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9838 12:27:18.688941 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9839 12:27:18.695409 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9840 12:27:18.698641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9841 12:27:18.705258 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9842 12:27:18.708542 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9843 12:27:18.711656 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9844 12:27:18.718226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9845 12:27:18.722046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9846 12:27:18.728395 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9847 12:27:18.731589 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9848 12:27:18.734720 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9849 12:27:18.741567 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9850 12:27:18.744690 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9851 12:27:18.751395 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9852 12:27:18.754437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9853 12:27:18.761165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9854 12:27:18.764759 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9855 12:27:18.770942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9856 12:27:18.774627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9857 12:27:18.777737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9858 12:27:18.784368 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9859 12:27:18.787543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9860 12:27:18.794278 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9861 12:27:18.797464 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9862 12:27:18.804378 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9863 12:27:18.807472 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9864 12:27:18.810707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9865 12:27:18.817688 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9866 12:27:18.820922 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9867 12:27:18.827273 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9868 12:27:18.830549 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9869 12:27:18.837513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9870 12:27:18.840771 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9871 12:27:18.846875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9872 12:27:18.850059 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9873 12:27:18.853730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9874 12:27:18.860405 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9875 12:27:18.863492 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9876 12:27:18.870407 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9877 12:27:18.873611 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9878 12:27:18.879800 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9879 12:27:18.883441 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9880 12:27:18.886474 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9881 12:27:18.893273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9882 12:27:18.896880 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9883 12:27:18.903200 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9884 12:27:18.906834 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9885 12:27:18.913420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9886 12:27:18.916437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9887 12:27:18.923261 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9888 12:27:18.926486 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9889 12:27:18.929707 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9890 12:27:18.936046 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9891 12:27:18.939159 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9892 12:27:18.946100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9893 12:27:18.949174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9894 12:27:18.956082 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9895 12:27:18.959068 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9896 12:27:18.966016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9897 12:27:18.969196 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9898 12:27:18.972287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9899 12:27:18.979108 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9900 12:27:18.982408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9901 12:27:18.989300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9902 12:27:18.992320 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9903 12:27:18.999096 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9904 12:27:19.002167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9905 12:27:19.005445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9906 12:27:19.011784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9907 12:27:19.015520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9908 12:27:19.021826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9909 12:27:19.025500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9910 12:27:19.031929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9911 12:27:19.035145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9912 12:27:19.041959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9913 12:27:19.045110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9914 12:27:19.051531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9915 12:27:19.054630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9916 12:27:19.061783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9917 12:27:19.064749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9918 12:27:19.071642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9919 12:27:19.074636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9920 12:27:19.081404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9921 12:27:19.084586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9922 12:27:19.090975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9923 12:27:19.094812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9924 12:27:19.101027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9925 12:27:19.104613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9926 12:27:19.110974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9927 12:27:19.114618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9928 12:27:19.121057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9929 12:27:19.124129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9930 12:27:19.131012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9931 12:27:19.134239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9932 12:27:19.140774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9933 12:27:19.143928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9934 12:27:19.150868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9935 12:27:19.153989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9936 12:27:19.160284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9937 12:27:19.164031 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9938 12:27:19.167073 INFO: [APUAPC] vio 0
9939 12:27:19.170650 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9940 12:27:19.176921 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9941 12:27:19.180542 INFO: [APUAPC] D0_APC_0: 0x400510
9942 12:27:19.180687 INFO: [APUAPC] D0_APC_1: 0x0
9943 12:27:19.183731 INFO: [APUAPC] D0_APC_2: 0x1540
9944 12:27:19.187383 INFO: [APUAPC] D0_APC_3: 0x0
9945 12:27:19.190485 INFO: [APUAPC] D1_APC_0: 0xffffffff
9946 12:27:19.193645 INFO: [APUAPC] D1_APC_1: 0xffffffff
9947 12:27:19.196948 INFO: [APUAPC] D1_APC_2: 0x3fffff
9948 12:27:19.200006 INFO: [APUAPC] D1_APC_3: 0x0
9949 12:27:19.203848 INFO: [APUAPC] D2_APC_0: 0xffffffff
9950 12:27:19.206879 INFO: [APUAPC] D2_APC_1: 0xffffffff
9951 12:27:19.209862 INFO: [APUAPC] D2_APC_2: 0x3fffff
9952 12:27:19.213821 INFO: [APUAPC] D2_APC_3: 0x0
9953 12:27:19.216956 INFO: [APUAPC] D3_APC_0: 0xffffffff
9954 12:27:19.220012 INFO: [APUAPC] D3_APC_1: 0xffffffff
9955 12:27:19.223787 INFO: [APUAPC] D3_APC_2: 0x3fffff
9956 12:27:19.226886 INFO: [APUAPC] D3_APC_3: 0x0
9957 12:27:19.230089 INFO: [APUAPC] D4_APC_0: 0xffffffff
9958 12:27:19.233272 INFO: [APUAPC] D4_APC_1: 0xffffffff
9959 12:27:19.236541 INFO: [APUAPC] D4_APC_2: 0x3fffff
9960 12:27:19.240281 INFO: [APUAPC] D4_APC_3: 0x0
9961 12:27:19.243479 INFO: [APUAPC] D5_APC_0: 0xffffffff
9962 12:27:19.246776 INFO: [APUAPC] D5_APC_1: 0xffffffff
9963 12:27:19.249865 INFO: [APUAPC] D5_APC_2: 0x3fffff
9964 12:27:19.253462 INFO: [APUAPC] D5_APC_3: 0x0
9965 12:27:19.256764 INFO: [APUAPC] D6_APC_0: 0xffffffff
9966 12:27:19.259865 INFO: [APUAPC] D6_APC_1: 0xffffffff
9967 12:27:19.263646 INFO: [APUAPC] D6_APC_2: 0x3fffff
9968 12:27:19.266731 INFO: [APUAPC] D6_APC_3: 0x0
9969 12:27:19.269853 INFO: [APUAPC] D7_APC_0: 0xffffffff
9970 12:27:19.273418 INFO: [APUAPC] D7_APC_1: 0xffffffff
9971 12:27:19.276444 INFO: [APUAPC] D7_APC_2: 0x3fffff
9972 12:27:19.279515 INFO: [APUAPC] D7_APC_3: 0x0
9973 12:27:19.283070 INFO: [APUAPC] D8_APC_0: 0xffffffff
9974 12:27:19.286614 INFO: [APUAPC] D8_APC_1: 0xffffffff
9975 12:27:19.289712 INFO: [APUAPC] D8_APC_2: 0x3fffff
9976 12:27:19.292880 INFO: [APUAPC] D8_APC_3: 0x0
9977 12:27:19.296021 INFO: [APUAPC] D9_APC_0: 0xffffffff
9978 12:27:19.299698 INFO: [APUAPC] D9_APC_1: 0xffffffff
9979 12:27:19.302892 INFO: [APUAPC] D9_APC_2: 0x3fffff
9980 12:27:19.305957 INFO: [APUAPC] D9_APC_3: 0x0
9981 12:27:19.309593 INFO: [APUAPC] D10_APC_0: 0xffffffff
9982 12:27:19.312669 INFO: [APUAPC] D10_APC_1: 0xffffffff
9983 12:27:19.316355 INFO: [APUAPC] D10_APC_2: 0x3fffff
9984 12:27:19.319575 INFO: [APUAPC] D10_APC_3: 0x0
9985 12:27:19.322724 INFO: [APUAPC] D11_APC_0: 0xffffffff
9986 12:27:19.326588 INFO: [APUAPC] D11_APC_1: 0xffffffff
9987 12:27:19.329644 INFO: [APUAPC] D11_APC_2: 0x3fffff
9988 12:27:19.332917 INFO: [APUAPC] D11_APC_3: 0x0
9989 12:27:19.335921 INFO: [APUAPC] D12_APC_0: 0xffffffff
9990 12:27:19.339176 INFO: [APUAPC] D12_APC_1: 0xffffffff
9991 12:27:19.342823 INFO: [APUAPC] D12_APC_2: 0x3fffff
9992 12:27:19.346058 INFO: [APUAPC] D12_APC_3: 0x0
9993 12:27:19.349206 INFO: [APUAPC] D13_APC_0: 0xffffffff
9994 12:27:19.352832 INFO: [APUAPC] D13_APC_1: 0xffffffff
9995 12:27:19.355836 INFO: [APUAPC] D13_APC_2: 0x3fffff
9996 12:27:19.359122 INFO: [APUAPC] D13_APC_3: 0x0
9997 12:27:19.362326 INFO: [APUAPC] D14_APC_0: 0xffffffff
9998 12:27:19.366099 INFO: [APUAPC] D14_APC_1: 0xffffffff
9999 12:27:19.369225 INFO: [APUAPC] D14_APC_2: 0x3fffff
10000 12:27:19.372300 INFO: [APUAPC] D14_APC_3: 0x0
10001 12:27:19.375874 INFO: [APUAPC] D15_APC_0: 0xffffffff
10002 12:27:19.378942 INFO: [APUAPC] D15_APC_1: 0xffffffff
10003 12:27:19.382630 INFO: [APUAPC] D15_APC_2: 0x3fffff
10004 12:27:19.385611 INFO: [APUAPC] D15_APC_3: 0x0
10005 12:27:19.388726 INFO: [APUAPC] APC_CON: 0x4
10006 12:27:19.391890 INFO: [NOCDAPC] D0_APC_0: 0x0
10007 12:27:19.395630 INFO: [NOCDAPC] D0_APC_1: 0x0
10008 12:27:19.396211 INFO: [NOCDAPC] D1_APC_0: 0x0
10009 12:27:19.398723 INFO: [NOCDAPC] D1_APC_1: 0xfff
10010 12:27:19.401841 INFO: [NOCDAPC] D2_APC_0: 0x0
10011 12:27:19.405617 INFO: [NOCDAPC] D2_APC_1: 0xfff
10012 12:27:19.408746 INFO: [NOCDAPC] D3_APC_0: 0x0
10013 12:27:19.411874 INFO: [NOCDAPC] D3_APC_1: 0xfff
10014 12:27:19.415102 INFO: [NOCDAPC] D4_APC_0: 0x0
10015 12:27:19.418796 INFO: [NOCDAPC] D4_APC_1: 0xfff
10016 12:27:19.421981 INFO: [NOCDAPC] D5_APC_0: 0x0
10017 12:27:19.425016 INFO: [NOCDAPC] D5_APC_1: 0xfff
10018 12:27:19.428058 INFO: [NOCDAPC] D6_APC_0: 0x0
10019 12:27:19.432031 INFO: [NOCDAPC] D6_APC_1: 0xfff
10020 12:27:19.432640 INFO: [NOCDAPC] D7_APC_0: 0x0
10021 12:27:19.435330 INFO: [NOCDAPC] D7_APC_1: 0xfff
10022 12:27:19.438494 INFO: [NOCDAPC] D8_APC_0: 0x0
10023 12:27:19.441586 INFO: [NOCDAPC] D8_APC_1: 0xfff
10024 12:27:19.444721 INFO: [NOCDAPC] D9_APC_0: 0x0
10025 12:27:19.448560 INFO: [NOCDAPC] D9_APC_1: 0xfff
10026 12:27:19.451727 INFO: [NOCDAPC] D10_APC_0: 0x0
10027 12:27:19.454936 INFO: [NOCDAPC] D10_APC_1: 0xfff
10028 12:27:19.458105 INFO: [NOCDAPC] D11_APC_0: 0x0
10029 12:27:19.461238 INFO: [NOCDAPC] D11_APC_1: 0xfff
10030 12:27:19.464941 INFO: [NOCDAPC] D12_APC_0: 0x0
10031 12:27:19.468079 INFO: [NOCDAPC] D12_APC_1: 0xfff
10032 12:27:19.471282 INFO: [NOCDAPC] D13_APC_0: 0x0
10033 12:27:19.474875 INFO: [NOCDAPC] D13_APC_1: 0xfff
10034 12:27:19.475299 INFO: [NOCDAPC] D14_APC_0: 0x0
10035 12:27:19.478108 INFO: [NOCDAPC] D14_APC_1: 0xfff
10036 12:27:19.481319 INFO: [NOCDAPC] D15_APC_0: 0x0
10037 12:27:19.484796 INFO: [NOCDAPC] D15_APC_1: 0xfff
10038 12:27:19.487902 INFO: [NOCDAPC] APC_CON: 0x4
10039 12:27:19.491149 INFO: [APUAPC] set_apusys_apc done
10040 12:27:19.494527 INFO: [DEVAPC] devapc_init done
10041 12:27:19.497761 INFO: GICv3 without legacy support detected.
10042 12:27:19.504804 INFO: ARM GICv3 driver initialized in EL3
10043 12:27:19.507827 INFO: Maximum SPI INTID supported: 639
10044 12:27:19.511026 INFO: BL31: Initializing runtime services
10045 12:27:19.517900 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10046 12:27:19.518386 INFO: SPM: enable CPC mode
10047 12:27:19.524110 INFO: mcdi ready for mcusys-off-idle and system suspend
10048 12:27:19.530541 INFO: BL31: Preparing for EL3 exit to normal world
10049 12:27:19.533803 INFO: Entry point address = 0x80000000
10050 12:27:19.534504 INFO: SPSR = 0x8
10051 12:27:19.540635
10052 12:27:19.541239
10053 12:27:19.541807
10054 12:27:19.543825 Starting depthcharge on Spherion...
10055 12:27:19.544397
10056 12:27:19.544965 Wipe memory regions:
10057 12:27:19.545527
10058 12:27:19.548926 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10059 12:27:19.549699 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10060 12:27:19.550432 Setting prompt string to ['asurada:']
10061 12:27:19.551071 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10062 12:27:19.552128 [0x00000040000000, 0x00000054600000)
10063 12:27:19.668909
10064 12:27:19.669138 [0x00000054660000, 0x00000080000000)
10065 12:27:19.929830
10066 12:27:19.930172 [0x000000821a7280, 0x000000ffe64000)
10067 12:27:20.674598
10068 12:27:20.674754 [0x00000100000000, 0x00000240000000)
10069 12:27:22.565096
10070 12:27:22.567952 Initializing XHCI USB controller at 0x11200000.
10071 12:27:23.549828
10072 12:27:23.550051 R8152: Initializing
10073 12:27:23.550176
10074 12:27:23.552840 Version 9 (ocp_data = 6010)
10075 12:27:23.552923
10076 12:27:23.555971 R8152: Done initializing
10077 12:27:23.556053
10078 12:27:23.556117 Adding net device
10079 12:27:24.078418
10080 12:27:24.081198 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10081 12:27:24.081296
10082 12:27:24.081365
10083 12:27:24.081428
10084 12:27:24.081709 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 12:27:24.182025 asurada: tftpboot 192.168.201.1 10605760/tftp-deploy-v5jpqhoi/kernel/image.itb 10605760/tftp-deploy-v5jpqhoi/kernel/cmdline
10087 12:27:24.182179 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 12:27:24.182273 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10089 12:27:24.186487 tftpboot 192.168.201.1 10605760/tftp-deploy-v5jpqhoi/kernel/image.ittp-deploy-v5jpqhoi/kernel/cmdline
10090 12:27:24.186571
10091 12:27:24.186645 Waiting for link
10092 12:27:24.389070
10093 12:27:24.389272 done.
10094 12:27:24.389376
10095 12:27:24.389475 MAC: f4:f5:e8:50:de:0a
10096 12:27:24.389563
10097 12:27:24.392063 Sending DHCP discover... done.
10098 12:27:24.392167
10099 12:27:24.395724 Waiting for reply... done.
10100 12:27:24.395861
10101 12:27:24.398810 Sending DHCP request... done.
10102 12:27:24.398903
10103 12:27:24.401827 Waiting for reply... done.
10104 12:27:24.401915
10105 12:27:24.401981 My ip is 192.168.201.14
10106 12:27:24.402052
10107 12:27:24.405586 The DHCP server ip is 192.168.201.1
10108 12:27:24.405659
10109 12:27:24.408473 TFTP server IP predefined by user: 192.168.201.1
10110 12:27:24.412259
10111 12:27:24.418654 Bootfile predefined by user: 10605760/tftp-deploy-v5jpqhoi/kernel/image.itb
10112 12:27:24.418737
10113 12:27:24.418801 Sending tftp read request... done.
10114 12:27:24.421814
10115 12:27:24.425566 Waiting for the transfer...
10116 12:27:24.425650
10117 12:27:24.688967 00000000 ################################################################
10118 12:27:24.689133
10119 12:27:24.946898 00080000 ################################################################
10120 12:27:24.947183
10121 12:27:25.200073 00100000 ################################################################
10122 12:27:25.200243
10123 12:27:25.444179 00180000 ################################################################
10124 12:27:25.444348
10125 12:27:25.699954 00200000 ################################################################
10126 12:27:25.700121
10127 12:27:25.950778 00280000 ################################################################
10128 12:27:25.950956
10129 12:27:26.192701 00300000 ################################################################
10130 12:27:26.192851
10131 12:27:26.450347 00380000 ################################################################
10132 12:27:26.450524
10133 12:27:26.691092 00400000 ################################################################
10134 12:27:26.691227
10135 12:27:26.944487 00480000 ################################################################
10136 12:27:26.944684
10137 12:27:27.196937 00500000 ################################################################
10138 12:27:27.197098
10139 12:27:27.431687 00580000 ################################################################
10140 12:27:27.431870
10141 12:27:27.664444 00600000 ################################################################
10142 12:27:27.664642
10143 12:27:27.899545 00680000 ################################################################
10144 12:27:27.899721
10145 12:27:28.132496 00700000 ################################################################
10146 12:27:28.132664
10147 12:27:28.374678 00780000 ################################################################
10148 12:27:28.374827
10149 12:27:28.601101 00800000 ################################################################
10150 12:27:28.601270
10151 12:27:28.835665 00880000 ################################################################
10152 12:27:28.835812
10153 12:27:29.071710 00900000 ################################################################
10154 12:27:29.071871
10155 12:27:29.341918 00980000 ################################################################
10156 12:27:29.342067
10157 12:27:29.585017 00a00000 ################################################################
10158 12:27:29.585149
10159 12:27:29.867472 00a80000 ################################################################
10160 12:27:29.867619
10161 12:27:30.157193 00b00000 ################################################################
10162 12:27:30.157339
10163 12:27:30.405368 00b80000 ################################################################
10164 12:27:30.405549
10165 12:27:30.647410 00c00000 ################################################################
10166 12:27:30.647590
10167 12:27:30.896093 00c80000 ################################################################
10168 12:27:30.896272
10169 12:27:31.126667 00d00000 ################################################################
10170 12:27:31.126820
10171 12:27:31.369313 00d80000 ################################################################
10172 12:27:31.369469
10173 12:27:31.612209 00e00000 ################################################################
10174 12:27:31.612362
10175 12:27:31.839228 00e80000 ################################################################
10176 12:27:31.839363
10177 12:27:32.063122 00f00000 ################################################################
10178 12:27:32.063273
10179 12:27:32.290173 00f80000 ################################################################
10180 12:27:32.290354
10181 12:27:32.511511 01000000 ################################################################
10182 12:27:32.511679
10183 12:27:32.732363 01080000 ################################################################
10184 12:27:32.732534
10185 12:27:32.955400 01100000 ################################################################
10186 12:27:32.955545
10187 12:27:33.179222 01180000 ################################################################
10188 12:27:33.179372
10189 12:27:33.401405 01200000 ################################################################
10190 12:27:33.401559
10191 12:27:33.623387 01280000 ################################################################
10192 12:27:33.623541
10193 12:27:33.844300 01300000 ################################################################
10194 12:27:33.844496
10195 12:27:34.066996 01380000 ################################################################
10196 12:27:34.067171
10197 12:27:34.295748 01400000 ################################################################
10198 12:27:34.295940
10199 12:27:34.518991 01480000 ################################################################
10200 12:27:34.519157
10201 12:27:34.749989 01500000 ################################################################
10202 12:27:34.750149
10203 12:27:34.989840 01580000 ################################################################
10204 12:27:34.990001
10205 12:27:35.222848 01600000 ################################################################
10206 12:27:35.223002
10207 12:27:35.455525 01680000 ################################################################
10208 12:27:35.455701
10209 12:27:35.692283 01700000 ################################################################
10210 12:27:35.692465
10211 12:27:35.928096 01780000 ################################################################
10212 12:27:35.928266
10213 12:27:36.161689 01800000 ################################################################
10214 12:27:36.161838
10215 12:27:36.391814 01880000 ################################################################
10216 12:27:36.391988
10217 12:27:36.626631 01900000 ################################################################
10218 12:27:36.626814
10219 12:27:36.870798 01980000 ################################################################
10220 12:27:36.870975
10221 12:27:37.107303 01a00000 ################################################################
10222 12:27:37.107473
10223 12:27:37.336080 01a80000 ################################################################
10224 12:27:37.336253
10225 12:27:37.586928 01b00000 ################################################################
10226 12:27:37.587098
10227 12:27:37.829253 01b80000 ################################################################
10228 12:27:37.829389
10229 12:27:38.066250 01c00000 ################################################################
10230 12:27:38.066403
10231 12:27:38.317572 01c80000 ################################################################
10232 12:27:38.317744
10233 12:27:38.554049 01d00000 ################################################################
10234 12:27:38.554214
10235 12:27:38.887453 01d80000 ################################################################
10236 12:27:38.887607
10237 12:27:39.224667 01e00000 ################################################################
10238 12:27:39.224853
10239 12:27:39.556247 01e80000 ################################################################
10240 12:27:39.556443
10241 12:27:39.857971 01f00000 ################################################################
10242 12:27:39.858154
10243 12:27:40.110796 01f80000 ################################################################
10244 12:27:40.110933
10245 12:27:40.360808 02000000 ################################################################
10246 12:27:40.360961
10247 12:27:40.604139 02080000 ################################################################
10248 12:27:40.604284
10249 12:27:40.855853 02100000 ################################################################
10250 12:27:40.856079
10251 12:27:41.111648 02180000 ################################################################
10252 12:27:41.111824
10253 12:27:41.366620 02200000 ################################################################
10254 12:27:41.366789
10255 12:27:41.676506 02280000 ################################################################
10256 12:27:41.676669
10257 12:27:41.969653 02300000 ################################################################
10258 12:27:41.969789
10259 12:27:42.246228 02380000 ################################################################
10260 12:27:42.246389
10261 12:27:42.517177 02400000 ################################################################
10262 12:27:42.517341
10263 12:27:42.775848 02480000 ################################################################
10264 12:27:42.776001
10265 12:27:43.028323 02500000 ################################################################
10266 12:27:43.028476
10267 12:27:43.259874 02580000 ################################################################
10268 12:27:43.260019
10269 12:27:43.506916 02600000 ################################################################
10270 12:27:43.507066
10271 12:27:43.736630 02680000 ################################################################
10272 12:27:43.736789
10273 12:27:43.974965 02700000 ################################################################
10274 12:27:43.975103
10275 12:27:44.207908 02780000 ################################################################
10276 12:27:44.208058
10277 12:27:44.444198 02800000 ################################################################
10278 12:27:44.444384
10279 12:27:44.687454 02880000 ################################################################
10280 12:27:44.687624
10281 12:27:44.929041 02900000 ################################################################
10282 12:27:44.929199
10283 12:27:45.166962 02980000 ################################################################
10284 12:27:45.167116
10285 12:27:45.397738 02a00000 ################################################################
10286 12:27:45.397887
10287 12:27:45.619141 02a80000 ################################################################
10288 12:27:45.619316
10289 12:27:45.845767 02b00000 ################################################################
10290 12:27:45.845962
10291 12:27:46.070939 02b80000 ################################################################
10292 12:27:46.071107
10293 12:27:46.293085 02c00000 ################################################################
10294 12:27:46.293226
10295 12:27:46.513846 02c80000 ################################################################
10296 12:27:46.513997
10297 12:27:46.741339 02d00000 ################################################################
10298 12:27:46.741508
10299 12:27:46.971140 02d80000 ################################################################
10300 12:27:46.971319
10301 12:27:47.207390 02e00000 ################################################################
10302 12:27:47.207530
10303 12:27:47.426120 02e80000 ################################################################
10304 12:27:47.426263
10305 12:27:47.648562 02f00000 ################################################################
10306 12:27:47.648717
10307 12:27:47.846390 02f80000 ########################################################## done.
10308 12:27:47.846581
10309 12:27:47.850081 The bootfile was 50280254 bytes long.
10310 12:27:47.850176
10311 12:27:47.853214 Sending tftp read request... done.
10312 12:27:47.853308
10313 12:27:47.856316 Waiting for the transfer...
10314 12:27:47.856434
10315 12:27:47.860051 00000000 # done.
10316 12:27:47.860162
10317 12:27:47.866364 Command line loaded dynamically from TFTP file: 10605760/tftp-deploy-v5jpqhoi/kernel/cmdline
10318 12:27:47.866472
10319 12:27:47.876168 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10320 12:27:47.879328
10321 12:27:47.879434 Loading FIT.
10322 12:27:47.879532
10323 12:27:47.883138 Image ramdisk-1 has 40144546 bytes.
10324 12:27:47.883243
10325 12:27:47.886318 Image fdt-1 has 46924 bytes.
10326 12:27:47.886397
10327 12:27:47.889563 Image kernel-1 has 10086749 bytes.
10328 12:27:47.889672
10329 12:27:47.896536 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10330 12:27:47.896645
10331 12:27:47.915768 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10332 12:27:47.915887
10333 12:27:47.919581 Choosing best match conf-1 for compat google,spherion-rev2.
10334 12:27:47.923893
10335 12:27:47.928313 Connected to device vid:did:rid of 1ae0:0028:00
10336 12:27:47.935848
10337 12:27:47.938985 tpm_get_response: command 0x17b, return code 0x0
10338 12:27:47.939095
10339 12:27:47.942134 ec_init: CrosEC protocol v3 supported (256, 248)
10340 12:27:47.946684
10341 12:27:47.949695 tpm_cleanup: add release locality here.
10342 12:27:47.949799
10343 12:27:47.949909 Shutting down all USB controllers.
10344 12:27:47.952756
10345 12:27:47.952864 Removing current net device
10346 12:27:47.952960
10347 12:27:47.959583 Exiting depthcharge with code 4 at timestamp: 57803958
10348 12:27:47.959705
10349 12:27:47.962727 LZMA decompressing kernel-1 to 0x821a6718
10350 12:27:47.962837
10351 12:27:47.966390 LZMA decompressing kernel-1 to 0x40000000
10352 12:27:49.232846
10353 12:27:49.233004 jumping to kernel
10354 12:27:49.233770 end: 2.2.4 bootloader-commands (duration 00:00:30) [common]
10355 12:27:49.233938 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10356 12:27:49.234042 Setting prompt string to ['Linux version [0-9]']
10357 12:27:49.234140 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10358 12:27:49.234291 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10359 12:27:49.314604
10360 12:27:49.317639 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10361 12:27:49.321677 start: 2.2.5.1 login-action (timeout 00:03:55) [common]
10362 12:27:49.321800 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10363 12:27:49.321954 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10364 12:27:49.322064 Using line separator: #'\n'#
10365 12:27:49.322158 No login prompt set.
10366 12:27:49.322254 Parsing kernel messages
10367 12:27:49.322344 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10368 12:27:49.322526 [login-action] Waiting for messages, (timeout 00:03:55)
10369 12:27:49.340809 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10370 12:27:49.343866 [ 0.000000] random: crng init done
10371 12:27:49.350742 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10372 12:27:49.353812 [ 0.000000] efi: UEFI not found.
10373 12:27:49.360643 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10374 12:27:49.366888 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10375 12:27:49.376785 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10376 12:27:49.386720 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10377 12:27:49.393186 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10378 12:27:49.399585 [ 0.000000] printk: bootconsole [mtk8250] enabled
10379 12:27:49.406664 [ 0.000000] NUMA: No NUMA configuration found
10380 12:27:49.412893 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10381 12:27:49.416054 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcca00-0x23efcefff]
10382 12:27:49.419847 [ 0.000000] Zone ranges:
10383 12:27:49.426109 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10384 12:27:49.429798 [ 0.000000] DMA32 empty
10385 12:27:49.436249 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10386 12:27:49.439421 [ 0.000000] Movable zone start for each node
10387 12:27:49.442547 [ 0.000000] Early memory node ranges
10388 12:27:49.449495 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10389 12:27:49.455747 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10390 12:27:49.462395 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10391 12:27:49.468788 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10392 12:27:49.475810 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10393 12:27:49.482044 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10394 12:27:49.538462 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10395 12:27:49.545312 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10396 12:27:49.551882 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10397 12:27:49.555128 [ 0.000000] psci: probing for conduit method from DT.
10398 12:27:49.561424 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10399 12:27:49.565162 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10400 12:27:49.571262 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10401 12:27:49.574978 [ 0.000000] psci: SMC Calling Convention v1.2
10402 12:27:49.580975 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10403 12:27:49.584746 [ 0.000000] Detected VIPT I-cache on CPU0
10404 12:27:49.591095 [ 0.000000] CPU features: detected: GIC system register CPU interface
10405 12:27:49.598068 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10406 12:27:49.604260 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10407 12:27:49.611049 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10408 12:27:49.621103 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10409 12:27:49.627416 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10410 12:27:49.630566 [ 0.000000] alternatives: applying boot alternatives
10411 12:27:49.637424 [ 0.000000] Fallback order for Node 0: 0
10412 12:27:49.643717 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10413 12:27:49.647499 [ 0.000000] Policy zone: Normal
10414 12:27:49.657324 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10415 12:27:49.670459 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10416 12:27:49.680468 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10417 12:27:49.690687 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10418 12:27:49.696903 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10419 12:27:49.700073 <6>[ 0.000000] software IO TLB: area num 8.
10420 12:27:49.755965 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10421 12:27:49.905236 <6>[ 0.000000] Memory: 7933732K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419036K reserved, 32768K cma-reserved)
10422 12:27:49.912405 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10423 12:27:49.918739 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10424 12:27:49.921866 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10425 12:27:49.928223 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10426 12:27:49.935039 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10427 12:27:49.938140 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10428 12:27:49.948067 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10429 12:27:49.955069 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10430 12:27:49.961257 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10431 12:27:49.967963 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10432 12:27:49.971467 <6>[ 0.000000] GICv3: 608 SPIs implemented
10433 12:27:49.974699 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10434 12:27:49.980841 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10435 12:27:49.984369 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10436 12:27:49.991126 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10437 12:27:50.003922 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10438 12:27:50.017048 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10439 12:27:50.023979 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10440 12:27:50.032135 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10441 12:27:50.044918 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10442 12:27:50.051576 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10443 12:27:50.058399 <6>[ 0.009226] Console: colour dummy device 80x25
10444 12:27:50.068360 <6>[ 0.013980] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10445 12:27:50.074734 <6>[ 0.024421] pid_max: default: 32768 minimum: 301
10446 12:27:50.078662 <6>[ 0.029295] LSM: Security Framework initializing
10447 12:27:50.084846 <6>[ 0.034234] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 12:27:50.094689 <6>[ 0.042095] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10449 12:27:50.104413 <6>[ 0.051532] cblist_init_generic: Setting adjustable number of callback queues.
10450 12:27:50.111364 <6>[ 0.059013] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 12:27:50.114342 <6>[ 0.065390] cblist_init_generic: Setting shift to 3 and lim to 1.
10452 12:27:50.121283 <6>[ 0.071797] rcu: Hierarchical SRCU implementation.
10453 12:27:50.127581 <6>[ 0.076810] rcu: Max phase no-delay instances is 1000.
10454 12:27:50.134085 <6>[ 0.083826] EFI services will not be available.
10455 12:27:50.137116 <6>[ 0.088769] smp: Bringing up secondary CPUs ...
10456 12:27:50.145376 <6>[ 0.093849] Detected VIPT I-cache on CPU1
10457 12:27:50.152049 <6>[ 0.093922] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10458 12:27:50.158222 <6>[ 0.093954] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10459 12:27:50.161908 <6>[ 0.094286] Detected VIPT I-cache on CPU2
10460 12:27:50.168316 <6>[ 0.094335] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10461 12:27:50.178269 <6>[ 0.094350] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10462 12:27:50.181568 <6>[ 0.094608] Detected VIPT I-cache on CPU3
10463 12:27:50.188395 <6>[ 0.094654] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10464 12:27:50.194607 <6>[ 0.094668] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10465 12:27:50.201390 <6>[ 0.094970] CPU features: detected: Spectre-v4
10466 12:27:50.205037 <6>[ 0.094976] CPU features: detected: Spectre-BHB
10467 12:27:50.208129 <6>[ 0.094983] Detected PIPT I-cache on CPU4
10468 12:27:50.214435 <6>[ 0.095040] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10469 12:27:50.221413 <6>[ 0.095056] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10470 12:27:50.227793 <6>[ 0.095346] Detected PIPT I-cache on CPU5
10471 12:27:50.234237 <6>[ 0.095409] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10472 12:27:50.241156 <6>[ 0.095425] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10473 12:27:50.244279 <6>[ 0.095707] Detected PIPT I-cache on CPU6
10474 12:27:50.253691 <6>[ 0.095772] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10475 12:27:50.260526 <6>[ 0.095788] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10476 12:27:50.263808 <6>[ 0.096083] Detected PIPT I-cache on CPU7
10477 12:27:50.270103 <6>[ 0.096148] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10478 12:27:50.276841 <6>[ 0.096164] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10479 12:27:50.280715 <6>[ 0.096210] smp: Brought up 1 node, 8 CPUs
10480 12:27:50.286893 <6>[ 0.237487] SMP: Total of 8 processors activated.
10481 12:27:50.293786 <6>[ 0.242439] CPU features: detected: 32-bit EL0 Support
10482 12:27:50.299970 <6>[ 0.247802] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10483 12:27:50.306793 <6>[ 0.256656] CPU features: detected: Common not Private translations
10484 12:27:50.313618 <6>[ 0.263132] CPU features: detected: CRC32 instructions
10485 12:27:50.319812 <6>[ 0.268483] CPU features: detected: RCpc load-acquire (LDAPR)
10486 12:27:50.323552 <6>[ 0.274479] CPU features: detected: LSE atomic instructions
10487 12:27:50.329850 <6>[ 0.280260] CPU features: detected: Privileged Access Never
10488 12:27:50.336815 <6>[ 0.286040] CPU features: detected: RAS Extension Support
10489 12:27:50.343205 <6>[ 0.291649] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10490 12:27:50.346375 <6>[ 0.298872] CPU: All CPU(s) started at EL2
10491 12:27:50.352649 <6>[ 0.303215] alternatives: applying system-wide alternatives
10492 12:27:50.363229 <6>[ 0.313923] devtmpfs: initialized
10493 12:27:50.378228 <6>[ 0.322751] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10494 12:27:50.385131 <6>[ 0.332712] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10495 12:27:50.388241 <6>[ 0.340347] pinctrl core: initialized pinctrl subsystem
10496 12:27:50.395825 <6>[ 0.347003] DMI not present or invalid.
10497 12:27:50.402469 <6>[ 0.351411] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10498 12:27:50.409321 <6>[ 0.358291] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10499 12:27:50.419133 <6>[ 0.365874] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10500 12:27:50.426057 <6>[ 0.374098] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10501 12:27:50.432441 <6>[ 0.382342] audit: initializing netlink subsys (disabled)
10502 12:27:50.438681 <5>[ 0.388034] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10503 12:27:50.445664 <6>[ 0.388734] thermal_sys: Registered thermal governor 'step_wise'
10504 12:27:50.451944 <6>[ 0.395998] thermal_sys: Registered thermal governor 'power_allocator'
10505 12:27:50.458879 <6>[ 0.402250] cpuidle: using governor menu
10506 12:27:50.462141 <6>[ 0.413210] NET: Registered PF_QIPCRTR protocol family
10507 12:27:50.468891 <6>[ 0.418686] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10508 12:27:50.475107 <6>[ 0.425787] ASID allocator initialised with 32768 entries
10509 12:27:50.481510 <6>[ 0.432366] Serial: AMBA PL011 UART driver
10510 12:27:50.490353 <4>[ 0.440998] Trying to register duplicate clock ID: 134
10511 12:27:50.544135 <6>[ 0.498105] KASLR enabled
10512 12:27:50.558420 <6>[ 0.505839] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10513 12:27:50.564706 <6>[ 0.512851] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10514 12:27:50.571500 <6>[ 0.519341] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10515 12:27:50.577796 <6>[ 0.526348] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10516 12:27:50.584341 <6>[ 0.532836] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10517 12:27:50.591183 <6>[ 0.539841] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10518 12:27:50.597874 <6>[ 0.546325] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10519 12:27:50.604092 <6>[ 0.553328] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10520 12:27:50.607605 <6>[ 0.560855] ACPI: Interpreter disabled.
10521 12:27:50.616181 <6>[ 0.567235] iommu: Default domain type: Translated
10522 12:27:50.623056 <6>[ 0.572348] iommu: DMA domain TLB invalidation policy: strict mode
10523 12:27:50.626215 <5>[ 0.579006] SCSI subsystem initialized
10524 12:27:50.632675 <6>[ 0.583171] usbcore: registered new interface driver usbfs
10525 12:27:50.639523 <6>[ 0.588904] usbcore: registered new interface driver hub
10526 12:27:50.642831 <6>[ 0.594455] usbcore: registered new device driver usb
10527 12:27:50.649177 <6>[ 0.600534] pps_core: LinuxPPS API ver. 1 registered
10528 12:27:50.659193 <6>[ 0.605728] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10529 12:27:50.662808 <6>[ 0.615074] PTP clock support registered
10530 12:27:50.665867 <6>[ 0.619314] EDAC MC: Ver: 3.0.0
10531 12:27:50.673304 <6>[ 0.624457] FPGA manager framework
10532 12:27:50.680216 <6>[ 0.628138] Advanced Linux Sound Architecture Driver Initialized.
10533 12:27:50.683379 <6>[ 0.634911] vgaarb: loaded
10534 12:27:50.689768 <6>[ 0.638073] clocksource: Switched to clocksource arch_sys_counter
10535 12:27:50.693597 <5>[ 0.644512] VFS: Disk quotas dquot_6.6.0
10536 12:27:50.699975 <6>[ 0.648697] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10537 12:27:50.703049 <6>[ 0.655885] pnp: PnP ACPI: disabled
10538 12:27:50.711615 <6>[ 0.662619] NET: Registered PF_INET protocol family
10539 12:27:50.721513 <6>[ 0.668215] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10540 12:27:50.732651 <6>[ 0.680513] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10541 12:27:50.743107 <6>[ 0.689327] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10542 12:27:50.749535 <6>[ 0.697297] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10543 12:27:50.759040 <6>[ 0.705990] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10544 12:27:50.765678 <6>[ 0.715726] TCP: Hash tables configured (established 65536 bind 65536)
10545 12:27:50.773054 <6>[ 0.722580] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 12:27:50.783135 <6>[ 0.729777] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10547 12:27:50.789423 <6>[ 0.737480] NET: Registered PF_UNIX/PF_LOCAL protocol family
10548 12:27:50.795340 <6>[ 0.743647] RPC: Registered named UNIX socket transport module.
10549 12:27:50.799151 <6>[ 0.749803] RPC: Registered udp transport module.
10550 12:27:50.805362 <6>[ 0.754735] RPC: Registered tcp transport module.
10551 12:27:50.811759 <6>[ 0.759667] RPC: Registered tcp NFSv4.1 backchannel transport module.
10552 12:27:50.815564 <6>[ 0.766334] PCI: CLS 0 bytes, default 64
10553 12:27:50.818596 <6>[ 0.770676] Unpacking initramfs...
10554 12:27:50.828274 <6>[ 0.774788] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10555 12:27:50.835222 <6>[ 0.783434] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10556 12:27:50.841419 <6>[ 0.792268] kvm [1]: IPA Size Limit: 40 bits
10557 12:27:50.844609 <6>[ 0.796793] kvm [1]: GICv3: no GICV resource entry
10558 12:27:50.851582 <6>[ 0.801816] kvm [1]: disabling GICv2 emulation
10559 12:27:50.857818 <6>[ 0.806500] kvm [1]: GIC system register CPU interface enabled
10560 12:27:50.861085 <6>[ 0.812658] kvm [1]: vgic interrupt IRQ18
10561 12:27:50.867958 <6>[ 0.817012] kvm [1]: VHE mode initialized successfully
10562 12:27:50.871060 <5>[ 0.823384] Initialise system trusted keyrings
10563 12:27:50.877459 <6>[ 0.828169] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10564 12:27:50.887429 <6>[ 0.838406] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10565 12:27:50.894410 <5>[ 0.844786] NFS: Registering the id_resolver key type
10566 12:27:50.897589 <5>[ 0.850086] Key type id_resolver registered
10567 12:27:50.903892 <5>[ 0.854499] Key type id_legacy registered
10568 12:27:50.910811 <6>[ 0.858780] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10569 12:27:50.917050 <6>[ 0.865703] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10570 12:27:50.923869 <6>[ 0.873405] 9p: Installing v9fs 9p2000 file system support
10571 12:27:50.960455 <5>[ 0.911371] Key type asymmetric registered
10572 12:27:50.963630 <5>[ 0.915702] Asymmetric key parser 'x509' registered
10573 12:27:50.973714 <6>[ 0.920845] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10574 12:27:50.976790 <6>[ 0.928458] io scheduler mq-deadline registered
10575 12:27:50.979960 <6>[ 0.933215] io scheduler kyber registered
10576 12:27:50.998845 <6>[ 0.949991] EINJ: ACPI disabled.
10577 12:27:51.031168 <4>[ 0.975495] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 12:27:51.040898 <4>[ 0.986126] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 12:27:51.055827 <6>[ 1.006751] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10580 12:27:51.063463 <6>[ 1.014692] printk: console [ttyS0] disabled
10581 12:27:51.091718 <6>[ 1.039339] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10582 12:27:51.098102 <6>[ 1.048832] printk: console [ttyS0] enabled
10583 12:27:51.101947 <6>[ 1.048832] printk: console [ttyS0] enabled
10584 12:27:51.108207 <6>[ 1.057726] printk: bootconsole [mtk8250] disabled
10585 12:27:51.111938 <6>[ 1.057726] printk: bootconsole [mtk8250] disabled
10586 12:27:51.118190 <6>[ 1.068957] SuperH (H)SCI(F) driver initialized
10587 12:27:51.121377 <6>[ 1.074251] msm_serial: driver initialized
10588 12:27:51.135440 <6>[ 1.083140] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10589 12:27:51.145105 <6>[ 1.091684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10590 12:27:51.152063 <6>[ 1.100226] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10591 12:27:51.162004 <6>[ 1.108855] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10592 12:27:51.172141 <6>[ 1.117566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10593 12:27:51.178363 <6>[ 1.126279] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10594 12:27:51.188393 <6>[ 1.134819] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10595 12:27:51.194692 <6>[ 1.143637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10596 12:27:51.204936 <6>[ 1.152182] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10597 12:27:51.216664 <6>[ 1.167705] loop: module loaded
10598 12:27:51.223655 <6>[ 1.173667] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10599 12:27:51.245756 <4>[ 1.197049] mtk-pmic-keys: Failed to locate of_node [id: -1]
10600 12:27:51.252542 <6>[ 1.203857] megasas: 07.719.03.00-rc1
10601 12:27:51.262656 <6>[ 1.213303] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10602 12:27:51.270906 <6>[ 1.221460] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10603 12:27:51.287282 <6>[ 1.238217] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10604 12:27:51.348315 <6>[ 1.292443] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10605 12:27:52.468722 <6>[ 2.419798] Freeing initrd memory: 39200K
10606 12:27:52.478649 <6>[ 2.430032] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10607 12:27:52.489613 <6>[ 2.440911] tun: Universal TUN/TAP device driver, 1.6
10608 12:27:52.493232 <6>[ 2.446963] thunder_xcv, ver 1.0
10609 12:27:52.496263 <6>[ 2.450467] thunder_bgx, ver 1.0
10610 12:27:52.500004 <6>[ 2.453956] nicpf, ver 1.0
10611 12:27:52.510004 <6>[ 2.457955] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10612 12:27:52.513761 <6>[ 2.465431] hns3: Copyright (c) 2017 Huawei Corporation.
10613 12:27:52.520166 <6>[ 2.471016] hclge is initializing
10614 12:27:52.523373 <6>[ 2.474596] e1000: Intel(R) PRO/1000 Network Driver
10615 12:27:52.529817 <6>[ 2.479726] e1000: Copyright (c) 1999-2006 Intel Corporation.
10616 12:27:52.533506 <6>[ 2.485739] e1000e: Intel(R) PRO/1000 Network Driver
10617 12:27:52.539794 <6>[ 2.490955] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10618 12:27:52.546586 <6>[ 2.497143] igb: Intel(R) Gigabit Ethernet Network Driver
10619 12:27:52.552859 <6>[ 2.502793] igb: Copyright (c) 2007-2014 Intel Corporation.
10620 12:27:52.559968 <6>[ 2.508629] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10621 12:27:52.566227 <6>[ 2.515147] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10622 12:27:52.569371 <6>[ 2.521602] sky2: driver version 1.30
10623 12:27:52.576267 <6>[ 2.526575] VFIO - User Level meta-driver version: 0.3
10624 12:27:52.583942 <6>[ 2.534765] usbcore: registered new interface driver usb-storage
10625 12:27:52.590506 <6>[ 2.541203] usbcore: registered new device driver onboard-usb-hub
10626 12:27:52.598929 <6>[ 2.550277] mt6397-rtc mt6359-rtc: registered as rtc0
10627 12:27:52.609220 <6>[ 2.555741] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:27:52 UTC (1686054472)
10628 12:27:52.612263 <6>[ 2.565292] i2c_dev: i2c /dev entries driver
10629 12:27:52.629201 <6>[ 2.577027] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10630 12:27:52.636024 <6>[ 2.587207] sdhci: Secure Digital Host Controller Interface driver
10631 12:27:52.642996 <6>[ 2.593645] sdhci: Copyright(c) Pierre Ossman
10632 12:27:52.649279 <6>[ 2.599041] Synopsys Designware Multimedia Card Interface Driver
10633 12:27:52.652419 <6>[ 2.605637] mmc0: CQHCI version 5.10
10634 12:27:52.659229 <6>[ 2.606192] sdhci-pltfm: SDHCI platform and OF driver helper
10635 12:27:52.666147 <6>[ 2.617555] ledtrig-cpu: registered to indicate activity on CPUs
10636 12:27:52.676878 <6>[ 2.624876] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10637 12:27:52.683765 <6>[ 2.632264] usbcore: registered new interface driver usbhid
10638 12:27:52.686982 <6>[ 2.638096] usbhid: USB HID core driver
10639 12:27:52.693219 <6>[ 2.642332] spi_master spi0: will run message pump with realtime priority
10640 12:27:52.736309 <6>[ 2.680653] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10641 12:27:52.754464 <6>[ 2.695824] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10642 12:27:52.758386 <6>[ 2.709417] mmc0: Command Queue Engine enabled
10643 12:27:52.764668 <6>[ 2.714168] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10644 12:27:52.771021 <6>[ 2.721089] cros-ec-spi spi0.0: Chrome EC device registered
10645 12:27:52.774587 <6>[ 2.721460] mmcblk0: mmc0:0001 DA4128 116 GiB
10646 12:27:52.785857 <6>[ 2.736814] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10647 12:27:52.792857 <6>[ 2.743927] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10648 12:27:52.799587 <6>[ 2.749845] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10649 12:27:52.806307 <6>[ 2.755858] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10650 12:27:52.816130 <6>[ 2.763595] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10651 12:27:52.823900 <6>[ 2.775020] NET: Registered PF_PACKET protocol family
10652 12:27:52.830029 <6>[ 2.780455] 9pnet: Installing 9P2000 support
10653 12:27:52.833711 <5>[ 2.785030] Key type dns_resolver registered
10654 12:27:52.836897 <6>[ 2.790082] registered taskstats version 1
10655 12:27:52.843314 <5>[ 2.794473] Loading compiled-in X.509 certificates
10656 12:27:52.876870 <4>[ 2.821049] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 12:27:52.886704 <4>[ 2.831761] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 12:27:52.896717 <3>[ 2.844448] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10659 12:27:52.908307 <6>[ 2.859757] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10660 12:27:52.915727 <6>[ 2.866666] xhci-mtk 11200000.usb: xHCI Host Controller
10661 12:27:52.921894 <6>[ 2.872162] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10662 12:27:52.932375 <6>[ 2.880026] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10663 12:27:52.938721 <6>[ 2.889469] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10664 12:27:52.945112 <6>[ 2.895556] xhci-mtk 11200000.usb: xHCI Host Controller
10665 12:27:52.951834 <6>[ 2.901158] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10666 12:27:52.958632 <6>[ 2.908849] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10667 12:27:52.965622 <6>[ 2.916747] hub 1-0:1.0: USB hub found
10668 12:27:52.968634 <6>[ 2.920791] hub 1-0:1.0: 1 port detected
10669 12:27:52.978714 <6>[ 2.925168] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10670 12:27:52.981934 <6>[ 2.934012] hub 2-0:1.0: USB hub found
10671 12:27:52.984921 <6>[ 2.938074] hub 2-0:1.0: 1 port detected
10672 12:27:52.994130 <6>[ 2.945281] mtk-msdc 11f70000.mmc: Got CD GPIO
10673 12:27:53.010939 <6>[ 2.958783] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10674 12:27:53.017554 <6>[ 2.966828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10675 12:27:53.027252 <4>[ 2.974796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10676 12:27:53.037433 <6>[ 2.984462] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10677 12:27:53.043766 <6>[ 2.992544] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10678 12:27:53.054417 <6>[ 3.000565] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10679 12:27:53.060691 <6>[ 3.008488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10680 12:27:53.066997 <6>[ 3.016309] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10681 12:27:53.077025 <6>[ 3.024131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10682 12:27:53.087086 <6>[ 3.034859] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10683 12:27:53.096853 <6>[ 3.043251] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10684 12:27:53.103877 <6>[ 3.051602] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10685 12:27:53.113274 <6>[ 3.059945] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10686 12:27:53.120248 <6>[ 3.068290] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10687 12:27:53.129960 <6>[ 3.076634] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10688 12:27:53.136749 <6>[ 3.084977] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10689 12:27:53.146184 <6>[ 3.093322] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10690 12:27:53.153079 <6>[ 3.101665] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10691 12:27:53.163044 <6>[ 3.110013] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10692 12:27:53.169270 <6>[ 3.118357] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10693 12:27:53.179714 <6>[ 3.126700] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10694 12:27:53.186149 <6>[ 3.135044] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10695 12:27:53.196122 <6>[ 3.143390] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10696 12:27:53.202393 <6>[ 3.151738] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10697 12:27:53.209553 <6>[ 3.160642] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10698 12:27:53.216991 <6>[ 3.168116] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10699 12:27:53.223732 <6>[ 3.175176] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10700 12:27:53.234155 <6>[ 3.182291] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10701 12:27:53.241103 <6>[ 3.189576] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10702 12:27:53.251119 <6>[ 3.196489] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10703 12:27:53.257383 <6>[ 3.205630] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10704 12:27:53.267518 <6>[ 3.214758] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10705 12:27:53.277535 <6>[ 3.224061] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10706 12:27:53.287416 <6>[ 3.233536] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10707 12:27:53.297578 <6>[ 3.243013] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10708 12:27:53.303920 <6>[ 3.252142] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10709 12:27:53.313805 <6>[ 3.261616] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10710 12:27:53.323671 <6>[ 3.270743] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10711 12:27:53.333362 <6>[ 3.280045] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10712 12:27:53.343423 <6>[ 3.290211] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10713 12:27:53.354016 <6>[ 3.301654] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10714 12:27:53.390272 <6>[ 3.338350] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10715 12:27:53.544111 <6>[ 3.495556] hub 1-1:1.0: USB hub found
10716 12:27:53.547826 <6>[ 3.499984] hub 1-1:1.0: 4 ports detected
10717 12:27:53.670166 <6>[ 3.618378] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10718 12:27:53.695452 <6>[ 3.646514] hub 2-1:1.0: USB hub found
10719 12:27:53.698655 <6>[ 3.650917] hub 2-1:1.0: 3 ports detected
10720 12:27:53.870367 <6>[ 3.818343] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10721 12:27:54.001034 <6>[ 3.952278] hub 1-1.1:1.0: USB hub found
10722 12:27:54.004347 <6>[ 3.956558] hub 1-1.1:1.0: 4 ports detected
10723 12:27:54.117713 <6>[ 4.066120] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10724 12:27:54.251277 <6>[ 4.202410] hub 1-1.4:1.0: USB hub found
10725 12:27:54.254383 <6>[ 4.207064] hub 1-1.4:1.0: 2 ports detected
10726 12:27:54.330062 <6>[ 4.278289] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10727 12:27:54.518234 <6>[ 4.466341] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10728 12:27:54.603072 <3>[ 4.554558] usb 1-1.1.4: device descriptor read/64, error -32
10729 12:27:54.795391 <3>[ 4.746553] usb 1-1.1.4: device descriptor read/64, error -32
10730 12:27:54.990396 <6>[ 4.938371] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10731 12:27:55.178295 <6>[ 5.126343] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10732 12:27:55.263159 <3>[ 5.214433] usb 1-1.1.4: device descriptor read/64, error -32
10733 12:27:55.455125 <3>[ 5.406554] usb 1-1.1.4: device descriptor read/64, error -32
10734 12:27:55.567059 <6>[ 5.518762] usb 1-1.1-port4: attempt power cycle
10735 12:27:55.654092 <6>[ 5.602260] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10736 12:27:56.178663 <6>[ 6.126343] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10737 12:27:56.185049 <4>[ 6.133797] usb 1-1.1.4: Device not responding to setup address.
10738 12:27:56.395167 <4>[ 6.346607] usb 1-1.1.4: Device not responding to setup address.
10739 12:27:56.606657 <3>[ 6.558332] usb 1-1.1.4: device not accepting address 10, error -71
10740 12:27:56.693922 <6>[ 6.642372] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10741 12:27:56.700931 <4>[ 6.649839] usb 1-1.1.4: Device not responding to setup address.
10742 12:27:56.910925 <4>[ 6.862610] usb 1-1.1.4: Device not responding to setup address.
10743 12:27:57.122700 <3>[ 7.074332] usb 1-1.1.4: device not accepting address 11, error -71
10744 12:27:57.129538 <3>[ 7.081290] usb 1-1.1-port4: unable to enumerate USB device
10745 12:28:05.639450 <6>[ 15.594918] ALSA device list:
10746 12:28:05.645642 <6>[ 15.598176] No soundcards found.
10747 12:28:05.658287 <6>[ 15.610588] Freeing unused kernel memory: 8384K
10748 12:28:05.661524 <6>[ 15.615519] Run /init as init process
10749 12:28:05.691805 <6>[ 15.644303] NET: Registered PF_INET6 protocol family
10750 12:28:05.698260 <6>[ 15.650553] Segment Routing with IPv6
10751 12:28:05.701465 <6>[ 15.654516] In-situ OAM (IOAM) with IPv6
10752 12:28:05.737506 <30>[ 15.669370] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10753 12:28:05.740416 <30>[ 15.693172] systemd[1]: Detected architecture arm64.
10754 12:28:05.741013
10755 12:28:05.747179 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10756 12:28:05.747801
10757 12:28:05.761792 <30>[ 15.714506] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10758 12:28:05.911145 <30>[ 15.860296] systemd[1]: Queued start job for default target Graphical Interface.
10759 12:28:05.951177 <30>[ 15.903661] systemd[1]: Created slice system-getty.slice.
10760 12:28:05.957926 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10761 12:28:05.974959 <30>[ 15.927118] systemd[1]: Created slice system-modprobe.slice.
10762 12:28:05.981522 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10763 12:28:05.999359 <30>[ 15.951499] systemd[1]: Created slice system-serial\x2dgetty.slice.
10764 12:28:06.009209 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10765 12:28:06.022946 <30>[ 15.974866] systemd[1]: Created slice User and Session Slice.
10766 12:28:06.029466 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10767 12:28:06.049917 <30>[ 15.998910] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10768 12:28:06.060122 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10769 12:28:06.077688 <30>[ 16.026512] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10770 12:28:06.084079 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10771 12:28:06.104893 <30>[ 16.050441] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10772 12:28:06.111384 <30>[ 16.062487] systemd[1]: Reached target Local Encrypted Volumes.
10773 12:28:06.118390 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10774 12:28:06.134621 <30>[ 16.086698] systemd[1]: Reached target Paths.
10775 12:28:06.137559 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10776 12:28:06.154109 <30>[ 16.106405] systemd[1]: Reached target Remote File Systems.
10777 12:28:06.160692 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10778 12:28:06.178592 <30>[ 16.130613] systemd[1]: Reached target Slices.
10779 12:28:06.185035 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10780 12:28:06.198304 <30>[ 16.150422] systemd[1]: Reached target Swap.
10781 12:28:06.201518 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10782 12:28:06.221748 <30>[ 16.170704] systemd[1]: Listening on initctl Compatibility Named Pipe.
10783 12:28:06.228178 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10784 12:28:06.234879 <30>[ 16.185460] systemd[1]: Listening on Journal Audit Socket.
10785 12:28:06.241601 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10786 12:28:06.254532 <30>[ 16.206650] systemd[1]: Listening on Journal Socket (/dev/log).
10787 12:28:06.261266 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10788 12:28:06.278801 <30>[ 16.231137] systemd[1]: Listening on Journal Socket.
10789 12:28:06.285789 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10790 12:28:06.301602 <30>[ 16.250798] systemd[1]: Listening on Network Service Netlink Socket.
10791 12:28:06.308300 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10792 12:28:06.323006 <30>[ 16.275129] systemd[1]: Listening on udev Control Socket.
10793 12:28:06.329347 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10794 12:28:06.347217 <30>[ 16.299057] systemd[1]: Listening on udev Kernel Socket.
10795 12:28:06.353259 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10796 12:28:06.390256 <30>[ 16.342740] systemd[1]: Mounting Huge Pages File System...
10797 12:28:06.397243 Mounting [0;1;39mHuge Pages File System[0m...
10798 12:28:06.412605 <30>[ 16.364540] systemd[1]: Mounting POSIX Message Queue File System...
10799 12:28:06.419569 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10800 12:28:06.436622 <30>[ 16.388498] systemd[1]: Mounting Kernel Debug File System...
10801 12:28:06.442581 Mounting [0;1;39mKernel Debug File System[0m...
10802 12:28:06.461696 <30>[ 16.410812] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10803 12:28:06.494135 <30>[ 16.442853] systemd[1]: Starting Create list of static device nodes for the current kernel...
10804 12:28:06.500427 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10805 12:28:06.520276 <30>[ 16.472719] systemd[1]: Starting Load Kernel Module configfs...
10806 12:28:06.527450 Starting [0;1;39mLoad Kernel Module configfs[0m...
10807 12:28:06.544414 <30>[ 16.496801] systemd[1]: Starting Load Kernel Module drm...
10808 12:28:06.551045 Starting [0;1;39mLoad Kernel Module drm[0m...
10809 12:28:06.569292 <30>[ 16.518557] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10810 12:28:06.580315 <30>[ 16.532350] systemd[1]: Starting Journal Service...
10811 12:28:06.583397 Starting [0;1;39mJournal Service[0m...
10812 12:28:06.600909 <30>[ 16.553198] systemd[1]: Starting Load Kernel Modules...
10813 12:28:06.607257 Starting [0;1;39mLoad Kernel Modules[0m...
10814 12:28:06.628369 <30>[ 16.577100] systemd[1]: Starting Remount Root and Kernel File Systems...
10815 12:28:06.634867 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10816 12:28:06.679045 <30>[ 16.630909] systemd[1]: Starting Coldplug All udev Devices...
10817 12:28:06.685305 Starting [0;1;39mColdplug All udev Devices[0m...
10818 12:28:06.700827 <30>[ 16.653026] systemd[1]: Started Journal Service.
10819 12:28:06.707444 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10820 12:28:06.723771 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10821 12:28:06.742670 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10822 12:28:06.758847 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10823 12:28:06.778375 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10824 12:28:06.800475 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10825 12:28:06.820083 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10826 12:28:06.839430 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10827 12:28:06.863399 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10828 12:28:06.878620 See 'systemctl status systemd-remount-fs.service' for details.
10829 12:28:06.934766 Mounting [0;1;39mKernel Configuration File System[0m...
10830 12:28:06.953301 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10831 12:28:06.970700 <46>[ 16.919736] systemd-journald[175]: Received client request to flush runtime journal.
10832 12:28:06.979789 Starting [0;1;39mLoad/Save Random Seed[0m...
10833 12:28:06.997517 Starting [0;1;39mApply Kernel Variables[0m...
10834 12:28:07.016802 Starting [0;1;39mCreate System Users[0m...
10835 12:28:07.035390 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10836 12:28:07.054819 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10837 12:28:07.067117 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10838 12:28:07.083526 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10839 12:28:07.104035 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10840 12:28:07.123660 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10841 12:28:07.162973 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10842 12:28:07.186599 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10843 12:28:07.198716 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10844 12:28:07.214320 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10845 12:28:07.267067 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10846 12:28:07.289827 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10847 12:28:07.307395 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10848 12:28:07.327639 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10849 12:28:07.363537 Starting [0;1;39mNetwork Service[0m...
10850 12:28:07.384395 Starting [0;1;39mNetwork Time Synchronization[0m...
10851 12:28:07.407815 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10852 12:28:07.448017 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10853 12:28:07.465142 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10854 12:28:07.527324 Starting [0;1;39mNetwork Name Resolution[0m...
10855 12:28:07.543462 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10856 12:28:07.577495 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10857 12:28:07.605137 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10858 12:28:07.618473 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10859 12:28:07.634333 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10860 12:28:07.651201 <6>[ 17.600149] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10861 12:28:07.657823 <6>[ 17.600337] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10862 12:28:07.660905 <6>[ 17.611664] mc: Linux media interface: v0.10
10863 12:28:07.670771 <4>[ 17.614282] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10864 12:28:07.677600 <6>[ 17.615268] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10865 12:28:07.687384 <4>[ 17.627340] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10866 12:28:07.693770 <6>[ 17.635931] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10867 12:28:07.700702 <6>[ 17.643819] remoteproc remoteproc0: scp is available
10868 12:28:07.707503 <3>[ 17.653187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 12:28:07.714068 <6>[ 17.658727] remoteproc remoteproc0: powering up scp
10870 12:28:07.720123 <3>[ 17.665881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 12:28:07.730560 <6>[ 17.671010] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10872 12:28:07.736828 <6>[ 17.671043] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10873 12:28:07.743465 <3>[ 17.679169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 12:28:07.753707 <3>[ 17.701968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 12:28:07.763245 Startin<3>[ 17.710209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 12:28:07.773208 g [0;1;39mLoad/<3>[ 17.719619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 12:28:07.779537 Save Screen …o<3>[ 17.729103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 12:28:07.789741 f leds:white:kbd<3>[ 17.739319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 12:28:07.795803 _backlight[0m..<6>[ 17.740592] usbcore: registered new interface driver r8152
10880 12:28:07.798931 .
10881 12:28:07.805845 <3>[ 17.750190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10882 12:28:07.815857 <6>[ 17.758903] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10883 12:28:07.822450 <6>[ 17.760371] videodev: Linux video capture interface: v2.00
10884 12:28:07.832132 <6>[ 17.762156] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10885 12:28:07.839102 <3>[ 17.768530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 12:28:07.848816 <6>[ 17.782336] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10887 12:28:07.855188 <6>[ 17.786153] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10888 12:28:07.865432 <3>[ 17.788695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 12:28:07.871720 <6>[ 17.791099] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10890 12:28:07.874835 <6>[ 17.791107] pci_bus 0000:00: root bus resource [bus 00-ff]
10891 12:28:07.884864 <6>[ 17.791114] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10892 12:28:07.895031 <6>[ 17.791119] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10893 12:28:07.898182 <6>[ 17.791154] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10894 12:28:07.907916 <6>[ 17.791174] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10895 12:28:07.911652 <6>[ 17.791254] pci 0000:00:00.0: supports D1 D2
10896 12:28:07.917979 <6>[ 17.791258] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10897 12:28:07.927693 <4>[ 17.807543] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10898 12:28:07.931277 <4>[ 17.807543] Fallback method does not support PEC.
10899 12:28:07.941310 <3>[ 17.813458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 12:28:07.947948 <3>[ 17.824014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10901 12:28:07.957235 <6>[ 17.825269] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10902 12:28:07.964371 <6>[ 17.827613] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10903 12:28:07.970748 <6>[ 17.827653] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10904 12:28:07.977707 <6>[ 17.827674] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10905 12:28:07.987707 <6>[ 17.827693] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10906 12:28:07.990722 <6>[ 17.827854] pci 0000:01:00.0: supports D1 D2
10907 12:28:07.997844 <6>[ 17.827858] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10908 12:28:08.004892 <6>[ 17.828594] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10909 12:28:08.011247 <6>[ 17.834281] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10910 12:28:08.018070 <6>[ 17.834291] remoteproc remoteproc0: remote processor scp is now up
10911 12:28:08.028051 <3>[ 17.834366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10912 12:28:08.034880 <6>[ 17.834885] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10913 12:28:08.041168 <6>[ 17.847090] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10914 12:28:08.047922 <3>[ 17.851394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 12:28:08.058405 <6>[ 17.857767] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10916 12:28:08.064864 <3>[ 17.865138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 12:28:08.074536 <3>[ 17.865152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 12:28:08.078286 <6>[ 17.867066] Bluetooth: Core ver 2.22
10919 12:28:08.085323 <6>[ 17.867156] NET: Registered PF_BLUETOOTH protocol family
10920 12:28:08.088966 <6>[ 17.867159] Bluetooth: HCI device and connection manager initialized
10921 12:28:08.095976 <6>[ 17.867190] Bluetooth: HCI socket layer initialized
10922 12:28:08.099161 <6>[ 17.867203] Bluetooth: L2CAP socket layer initialized
10923 12:28:08.105514 <6>[ 17.867225] Bluetooth: SCO socket layer initialized
10924 12:28:08.112535 <6>[ 17.869733] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10925 12:28:08.119200 <6>[ 17.871286] usbcore: registered new interface driver cdc_ether
10926 12:28:08.129190 <3>[ 17.878250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 12:28:08.135238 <6>[ 17.890613] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10928 12:28:08.142114 <6>[ 17.937986] usbcore: registered new interface driver r8153_ecm
10929 12:28:08.149472 <6>[ 17.943800] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10930 12:28:08.156200 <6>[ 17.945216] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10931 12:28:08.166158 <3>[ 17.960791] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 12:28:08.172654 <6>[ 17.962106] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10933 12:28:08.186098 <6>[ 17.968452] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10934 12:28:08.192388 <6>[ 17.974794] usbcore: registered new interface driver uvcvideo
10935 12:28:08.199146 <6>[ 17.977133] pci 0000:00:00.0: PCI bridge to [bus 01]
10936 12:28:08.205657 <4>[ 17.981100] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10937 12:28:08.215952 <4>[ 17.981114] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10938 12:28:08.225271 <4>[ 18.004242] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10939 12:28:08.232160 <6>[ 18.004583] usbcore: registered new interface driver btusb
10940 12:28:08.238841 <6>[ 18.007295] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10941 12:28:08.245601 <6>[ 18.010579] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10942 12:28:08.251776 <3>[ 18.015441] Bluetooth: hci0: Failed to load firmware file (-2)
10943 12:28:08.258424 <6>[ 18.016339] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10944 12:28:08.265028 <6>[ 18.017188] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10945 12:28:08.275194 <6>[ 18.019599] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10946 12:28:08.284732 <3>[ 18.020249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:28:08.291693 <3>[ 18.020942] power_supply sbs-5-000b: driver failed to report `health' property: -6
10948 12:28:08.298376 <6>[ 18.025019] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10949 12:28:08.304723 <3>[ 18.031613] Bluetooth: hci0: Failed to set up firmware (-2)
10950 12:28:08.307835 <6>[ 18.035756] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10951 12:28:08.321380 <4>[ 18.041123] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10952 12:28:08.324509 <6>[ 18.042248] r8152 1-1.1.1:1.0 eth0: v1.12.13
10953 12:28:08.334472 <3>[ 18.050864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 12:28:08.341260 <3>[ 18.052894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10955 12:28:08.351149 <5>[ 18.061480] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10956 12:28:08.357590 <6>[ 18.066922] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10957 12:28:08.363876 <5>[ 18.082661] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10958 12:28:08.370571 <3>[ 18.108747] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 12:28:08.377507 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10960 12:28:08.390350 <4>[ 18.339699] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10961 12:28:08.396748 <6>[ 18.348707] cfg80211: failed to load regulatory.db
10962 12:28:08.407813 <3>[ 18.357054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 12:28:08.417433 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10964 12:28:08.442908 <3>[ 18.392104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 12:28:08.449478 <6>[ 18.394443] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10966 12:28:08.455698 <6>[ 18.408395] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10967 12:28:08.474080 <3>[ 18.423306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 12:28:08.482957 <6>[ 18.435100] mt7921e 0000:01:00.0: ASIC revision: 79610010
10969 12:28:08.507979 <3>[ 18.457540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 12:28:08.588324 <4>[ 18.534305] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10971 12:28:08.604594 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10972 12:28:08.618301 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10973 12:28:08.641002 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10974 12:28:08.653663 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10975 12:28:08.673660 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10976 12:28:08.689765 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10977 12:28:08.695921 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10978 12:28:08.706093 <4>[ 18.653380] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 12:28:08.718440 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10980 12:28:08.734366 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10981 12:28:08.753974 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10982 12:28:08.777202 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10983 12:28:08.826598 <4>[ 18.772665] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10984 12:28:08.833665 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10985 12:28:08.860462 Starting [0;1;39mUser Login Management[0m...
10986 12:28:08.875860 Starting [0;1;39mPermit User Sessions[0m...
10987 12:28:08.893814 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10988 12:28:08.910218 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10989 12:28:08.932063 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10990 12:28:08.948646 <4>[ 18.894885] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 12:28:08.954800 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10992 12:28:09.014008 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10993 12:28:09.029662 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10994 12:28:09.046720 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10995 12:28:09.075886 [[0;32m OK [0m] Reached targ<4>[ 19.021410] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 12:28:09.079144 et [0;1;39mMulti-User System[0m.
10997 12:28:09.094971 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10998 12:28:09.149784 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10999 12:28:09.174078 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11000 12:28:09.194043 <4>[ 19.140579] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11001 12:28:09.222678
11002 12:28:09.222794
11003 12:28:09.225761 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11004 12:28:09.225848
11005 12:28:09.229081 debian-bullseye-arm64 login: root (automatic login)
11006 12:28:09.229165
11007 12:28:09.229230
11008 12:28:09.245351 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11009 12:28:09.245437
11010 12:28:09.252362 The programs included with the Debian GNU/Linux system are free software;
11011 12:28:09.258808 the exact distribution terms for each program are described in the
11012 12:28:09.262001 individual files in /usr/share/doc/*/copyright.
11013 12:28:09.262085
11014 12:28:09.268809 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11015 12:28:09.271805 permitted by applicable law.
11016 12:28:09.272151 Matched prompt #10: / #
11018 12:28:09.272362 Setting prompt string to ['/ #']
11019 12:28:09.272458 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11021 12:28:09.272669 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11022 12:28:09.272758 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11023 12:28:09.272830 Setting prompt string to ['/ #']
11024 12:28:09.272892 Forcing a shell prompt, looking for ['/ #']
11026 12:28:09.323134 / #
11027 12:28:09.323298 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11028 12:28:09.323380 Waiting using forced prompt support (timeout 00:02:30)
11029 12:28:09.323500 <4>[ 19.260873] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 12:28:09.328899
11031 12:28:09.376864 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11032 12:28:09.377008 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11033 12:28:09.377116 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11034 12:28:09.377202 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11035 12:28:09.377290 end: 2 depthcharge-action (duration 00:01:25) [common]
11036 12:28:09.377374 start: 3 lava-test-retry (timeout 00:08:12) [common]
11037 12:28:09.377461 start: 3.1 lava-test-shell (timeout 00:08:12) [common]
11038 12:28:09.377533 Using namespace: common
11040 12:28:09.477854 / # #
11041 12:28:09.478052 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11042 12:28:09.478222 <4>[ 19.380616] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11043 12:28:09.482604 #
11044 12:28:09.482873 Using /lava-10605760
11046 12:28:09.583230 / # export SHELL=/bin/sh
11047 12:28:09.583453 export SHELL=/bin/sh<4>[ 19.500539] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11048 12:28:09.588422
11050 12:28:09.689051 / # . /lava-10605760/environment
11051 12:28:09.689747 . /lava-10605760/environment<4>[ 19.620461] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11052 12:28:09.695241
11054 12:28:09.796688 / # /lava-10605760/bin/lava-test-runner /lava-10605760/0
11055 12:28:09.797256 Test shell timeout: 10s (minimum of the action and connection timeout)
11056 12:28:09.798699 <6>[ 19.705876] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11057 12:28:09.799085 /lava-10605760/bi<6>[ 19.713912] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11058 12:28:09.799414 n/lava-test-run<3>[ 19.738698] mt7921e 0000:01:00.0: hardware init failed
11059 12:28:09.802467
11060 12:28:09.848924 -sh: 5: /lava-10605760/bin/lava-test-run: not found
11061 12:28:36.103458 / # <6>[ 46.062698] vpu: disabling
11062 12:28:36.106558 <6>[ 46.065754] vproc2: disabling
11063 12:28:36.109689 <6>[ 46.069034] vproc1: disabling
11064 12:28:36.113371 <6>[ 46.072295] vaud18: disabling
11065 12:28:36.119594 <6>[ 46.075704] vsram_others: disabling
11066 12:28:36.123283 <6>[ 46.079579] va09: disabling
11067 12:28:36.126345 <6>[ 46.082685] vsram_md: disabling
11068 12:28:36.129297 <6>[ 46.086169] Vgpu: disabling
11070 12:36:21.378303 end: 3.1 lava-test-shell (duration 00:08:12) [common]
11072 12:36:21.379218 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 492 seconds'
11074 12:36:21.380020 end: 3 lava-test-retry (duration 00:08:12) [common]
11076 12:36:21.381189 Cleaning after the job
11077 12:36:21.381622 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/ramdisk
11078 12:36:21.400806 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/kernel
11079 12:36:21.425189 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/dtb
11080 12:36:21.425480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605760/tftp-deploy-v5jpqhoi/modules
11081 12:36:21.432923 start: 4.1 power-off (timeout 00:00:30) [common]
11082 12:36:21.433155 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11083 12:36:21.517345 >> Command sent successfully.
11084 12:36:21.527678 Returned 0 in 0 seconds
11085 12:36:21.628892 end: 4.1 power-off (duration 00:00:00) [common]
11087 12:36:21.630367 start: 4.2 read-feedback (timeout 00:10:00) [common]
11088 12:36:21.631514 Listened to connection for namespace 'common' for up to 1s
11089 12:36:22.632208 Finalising connection for namespace 'common'
11090 12:36:22.632939 Disconnecting from shell: Finalise
11091 12:36:22.733890 end: 4.2 read-feedback (duration 00:00:01) [common]
11092 12:36:22.734471 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605760
11093 12:36:22.828672 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605760
11094 12:36:22.828869 TestError: A test failed to run, look at the error message.