Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 66
1 12:25:39.497836 lava-dispatcher, installed at version: 2023.05.1
2 12:25:39.498054 start: 0 validate
3 12:25:39.498192 Start time: 2023-06-06 12:25:39.498184+00:00 (UTC)
4 12:25:39.498325 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:25:39.498464 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:25:39.792872 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:25:39.793067 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:25:55.795999 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:25:55.796211 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:25:56.092076 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:25:56.092280 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:25:58.886545 validate duration: 19.39
14 12:25:58.886819 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:25:58.886921 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:25:58.887009 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:25:58.887140 Not decompressing ramdisk as can be used compressed.
18 12:25:58.887227 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 12:25:58.887294 saving as /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/ramdisk/rootfs.cpio.gz
20 12:25:58.887363 total size: 27151647 (25MB)
21 12:25:59.190505 progress 0% (0MB)
22 12:25:59.198525 progress 5% (1MB)
23 12:25:59.205981 progress 10% (2MB)
24 12:25:59.213312 progress 15% (3MB)
25 12:25:59.220353 progress 20% (5MB)
26 12:25:59.227741 progress 25% (6MB)
27 12:25:59.235026 progress 30% (7MB)
28 12:25:59.242474 progress 35% (9MB)
29 12:25:59.249486 progress 40% (10MB)
30 12:25:59.256646 progress 45% (11MB)
31 12:25:59.264036 progress 50% (12MB)
32 12:25:59.271430 progress 55% (14MB)
33 12:25:59.278675 progress 60% (15MB)
34 12:25:59.285792 progress 65% (16MB)
35 12:25:59.293063 progress 70% (18MB)
36 12:25:59.300216 progress 75% (19MB)
37 12:25:59.307360 progress 80% (20MB)
38 12:25:59.314546 progress 85% (22MB)
39 12:25:59.321397 progress 90% (23MB)
40 12:25:59.328419 progress 95% (24MB)
41 12:25:59.335343 progress 100% (25MB)
42 12:25:59.335565 25MB downloaded in 0.45s (57.77MB/s)
43 12:25:59.335729 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:25:59.335977 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:25:59.336072 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:25:59.336160 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:25:59.336303 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:25:59.336379 saving as /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/kernel/Image
50 12:25:59.336444 total size: 45746688 (43MB)
51 12:25:59.336508 No compression specified
52 12:25:59.337758 progress 0% (0MB)
53 12:25:59.349611 progress 5% (2MB)
54 12:25:59.362633 progress 10% (4MB)
55 12:25:59.375349 progress 15% (6MB)
56 12:25:59.387811 progress 20% (8MB)
57 12:25:59.399683 progress 25% (10MB)
58 12:25:59.411812 progress 30% (13MB)
59 12:25:59.424111 progress 35% (15MB)
60 12:25:59.436196 progress 40% (17MB)
61 12:25:59.449042 progress 45% (19MB)
62 12:25:59.461945 progress 50% (21MB)
63 12:25:59.474349 progress 55% (24MB)
64 12:25:59.487179 progress 60% (26MB)
65 12:25:59.499869 progress 65% (28MB)
66 12:25:59.511886 progress 70% (30MB)
67 12:25:59.524008 progress 75% (32MB)
68 12:25:59.536136 progress 80% (34MB)
69 12:25:59.547933 progress 85% (37MB)
70 12:25:59.559831 progress 90% (39MB)
71 12:25:59.572054 progress 95% (41MB)
72 12:25:59.584206 progress 100% (43MB)
73 12:25:59.584385 43MB downloaded in 0.25s (175.96MB/s)
74 12:25:59.584546 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:25:59.584785 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:25:59.584877 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:25:59.584973 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:25:59.585123 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:25:59.585202 saving as /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/dtb/mt8192-asurada-spherion-r0.dtb
81 12:25:59.585268 total size: 46924 (0MB)
82 12:25:59.585333 No compression specified
83 12:25:59.586484 progress 69% (0MB)
84 12:25:59.586763 progress 100% (0MB)
85 12:25:59.586920 0MB downloaded in 0.00s (27.12MB/s)
86 12:25:59.587046 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:25:59.587420 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:25:59.587528 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:25:59.587635 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:25:59.587774 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:25:59.587851 saving as /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/modules/modules.tar
93 12:25:59.587935 total size: 8539116 (8MB)
94 12:25:59.588048 Using unxz to decompress xz
95 12:25:59.592291 progress 0% (0MB)
96 12:25:59.616103 progress 5% (0MB)
97 12:25:59.645426 progress 10% (0MB)
98 12:25:59.673593 progress 15% (1MB)
99 12:25:59.705764 progress 20% (1MB)
100 12:25:59.733815 progress 25% (2MB)
101 12:25:59.761106 progress 30% (2MB)
102 12:25:59.788746 progress 35% (2MB)
103 12:25:59.817155 progress 40% (3MB)
104 12:25:59.845923 progress 45% (3MB)
105 12:25:59.876563 progress 50% (4MB)
106 12:25:59.903579 progress 55% (4MB)
107 12:25:59.931982 progress 60% (4MB)
108 12:25:59.960577 progress 65% (5MB)
109 12:25:59.991383 progress 70% (5MB)
110 12:26:00.021670 progress 75% (6MB)
111 12:26:00.058752 progress 80% (6MB)
112 12:26:00.085860 progress 85% (6MB)
113 12:26:00.114426 progress 90% (7MB)
114 12:26:00.143153 progress 95% (7MB)
115 12:26:00.170942 progress 100% (8MB)
116 12:26:00.177194 8MB downloaded in 0.59s (13.82MB/s)
117 12:26:00.177599 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:26:00.178019 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:26:00.178162 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:26:00.178308 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:26:00.178438 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:26:00.178574 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:26:00.178887 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7
125 12:26:00.179092 makedir: /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin
126 12:26:00.179254 makedir: /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/tests
127 12:26:00.179423 makedir: /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/results
128 12:26:00.179592 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-add-keys
129 12:26:00.179796 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-add-sources
130 12:26:00.179986 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-background-process-start
131 12:26:00.180173 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-background-process-stop
132 12:26:00.180354 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-common-functions
133 12:26:00.180538 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-echo-ipv4
134 12:26:00.180720 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-install-packages
135 12:26:00.180900 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-installed-packages
136 12:26:00.181084 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-os-build
137 12:26:00.181266 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-probe-channel
138 12:26:00.181450 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-probe-ip
139 12:26:00.181629 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-target-ip
140 12:26:00.181815 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-target-mac
141 12:26:00.182004 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-target-storage
142 12:26:00.182195 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-case
143 12:26:00.182379 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-event
144 12:26:00.182563 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-feedback
145 12:26:00.182750 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-raise
146 12:26:00.182934 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-reference
147 12:26:00.183118 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-runner
148 12:26:00.183303 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-set
149 12:26:00.183511 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-test-shell
150 12:26:00.183699 Updating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-install-packages (oe)
151 12:26:00.183914 Updating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/bin/lava-installed-packages (oe)
152 12:26:00.184093 Creating /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/environment
153 12:26:00.184246 LAVA metadata
154 12:26:00.184364 - LAVA_JOB_ID=10605759
155 12:26:00.184473 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:26:00.184633 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:26:00.184744 skipped lava-vland-overlay
158 12:26:00.184869 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:26:00.184999 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:26:00.185104 skipped lava-multinode-overlay
161 12:26:00.185225 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:26:00.185362 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:26:00.185482 Loading test definitions
164 12:26:00.185630 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:26:00.185751 Using /lava-10605759 at stage 0
166 12:26:00.186211 uuid=10605759_1.5.2.3.1 testdef=None
167 12:26:00.186341 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:26:00.186473 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:26:00.187225 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:26:00.187596 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:26:00.188500 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:26:00.188874 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:26:00.189766 runner path: /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/0/tests/0_v4l2-compliance-uvc test_uuid 10605759_1.5.2.3.1
176 12:26:00.189981 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:26:00.190319 Creating lava-test-runner.conf files
179 12:26:00.190422 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605759/lava-overlay-u0fu5ia7/lava-10605759/0 for stage 0
180 12:26:00.190558 - 0_v4l2-compliance-uvc
181 12:26:00.190700 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:26:00.190829 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:26:00.200427 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:26:00.200627 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:26:00.200767 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:26:00.200901 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:26:00.201045 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:26:00.997197 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:26:00.997607 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:26:00.997776 extracting modules file /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605759/extract-overlay-ramdisk-4uhy87ne/ramdisk
191 12:26:01.228785 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:26:01.228990 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:26:01.229150 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605759/compress-overlay-xt1pyra_/overlay-1.5.2.4.tar.gz to ramdisk
194 12:26:01.229259 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605759/compress-overlay-xt1pyra_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605759/extract-overlay-ramdisk-4uhy87ne/ramdisk
195 12:26:01.236705 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:26:01.236841 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:26:01.236941 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:26:01.237034 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:26:01.237121 Building ramdisk /var/lib/lava/dispatcher/tmp/10605759/extract-overlay-ramdisk-4uhy87ne/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605759/extract-overlay-ramdisk-4uhy87ne/ramdisk
200 12:26:02.000988 >> 230342 blocks
201 12:26:06.365816 rename /var/lib/lava/dispatcher/tmp/10605759/extract-overlay-ramdisk-4uhy87ne/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/ramdisk/ramdisk.cpio.gz
202 12:26:06.366268 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:26:06.366442 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:26:06.366583 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:26:06.366695 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/kernel/Image'
206 12:26:20.461334 Returned 0 in 14 seconds
207 12:26:20.561951 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/kernel/image.itb
208 12:26:21.172436 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:26:21.172848 output: Created: Tue Jun 6 13:26:21 2023
210 12:26:21.172963 output: Image 0 (kernel-1)
211 12:26:21.173076 output: Description:
212 12:26:21.173180 output: Created: Tue Jun 6 13:26:21 2023
213 12:26:21.173294 output: Type: Kernel Image
214 12:26:21.173392 output: Compression: lzma compressed
215 12:26:21.173490 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
216 12:26:21.173585 output: Architecture: AArch64
217 12:26:21.173690 output: OS: Linux
218 12:26:21.173795 output: Load Address: 0x00000000
219 12:26:21.173911 output: Entry Point: 0x00000000
220 12:26:21.174091 output: Hash algo: crc32
221 12:26:21.174182 output: Hash value: a26c3f91
222 12:26:21.174268 output: Image 1 (fdt-1)
223 12:26:21.174355 output: Description: mt8192-asurada-spherion-r0
224 12:26:21.174467 output: Created: Tue Jun 6 13:26:21 2023
225 12:26:21.174553 output: Type: Flat Device Tree
226 12:26:21.174644 output: Compression: uncompressed
227 12:26:21.174729 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:26:21.174830 output: Architecture: AArch64
229 12:26:21.174919 output: Hash algo: crc32
230 12:26:21.175028 output: Hash value: 1df858fa
231 12:26:21.175132 output: Image 2 (ramdisk-1)
232 12:26:21.175217 output: Description: unavailable
233 12:26:21.175301 output: Created: Tue Jun 6 13:26:21 2023
234 12:26:21.175426 output: Type: RAMDisk Image
235 12:26:21.175514 output: Compression: Unknown Compression
236 12:26:21.175599 output: Data Size: 40124880 Bytes = 39184.45 KiB = 38.27 MiB
237 12:26:21.175686 output: Architecture: AArch64
238 12:26:21.175771 output: OS: Linux
239 12:26:21.175901 output: Load Address: unavailable
240 12:26:21.175989 output: Entry Point: unavailable
241 12:26:21.176077 output: Hash algo: crc32
242 12:26:21.176161 output: Hash value: 00bd81f9
243 12:26:21.176262 output: Default Configuration: 'conf-1'
244 12:26:21.176347 output: Configuration 0 (conf-1)
245 12:26:21.176470 output: Description: mt8192-asurada-spherion-r0
246 12:26:21.176555 output: Kernel: kernel-1
247 12:26:21.176713 output: Init Ramdisk: ramdisk-1
248 12:26:21.176858 output: FDT: fdt-1
249 12:26:21.177028 output: Loadables: kernel-1
250 12:26:21.177117 output:
251 12:26:21.177410 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 12:26:21.177649 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 12:26:21.177854 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 12:26:21.177998 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 12:26:21.178125 No LXC device requested
256 12:26:21.178247 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:26:21.178389 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 12:26:21.178572 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:26:21.178694 Checking files for TFTP limit of 4294967296 bytes.
260 12:26:21.179469 end: 1 tftp-deploy (duration 00:00:22) [common]
261 12:26:21.179668 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:26:21.179806 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:26:21.180057 substitutions:
264 12:26:21.180174 - {DTB}: 10605759/tftp-deploy-yx_sj7lb/dtb/mt8192-asurada-spherion-r0.dtb
265 12:26:21.180290 - {INITRD}: 10605759/tftp-deploy-yx_sj7lb/ramdisk/ramdisk.cpio.gz
266 12:26:21.180455 - {KERNEL}: 10605759/tftp-deploy-yx_sj7lb/kernel/Image
267 12:26:21.180608 - {LAVA_MAC}: None
268 12:26:21.180702 - {PRESEED_CONFIG}: None
269 12:26:21.180811 - {PRESEED_LOCAL}: None
270 12:26:21.180904 - {RAMDISK}: 10605759/tftp-deploy-yx_sj7lb/ramdisk/ramdisk.cpio.gz
271 12:26:21.180999 - {ROOT_PART}: None
272 12:26:21.181092 - {ROOT}: None
273 12:26:21.181188 - {SERVER_IP}: 192.168.201.1
274 12:26:21.181291 - {TEE}: None
275 12:26:21.181385 Parsed boot commands:
276 12:26:21.181489 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:26:21.181726 Parsed boot commands: tftpboot 192.168.201.1 10605759/tftp-deploy-yx_sj7lb/kernel/image.itb 10605759/tftp-deploy-yx_sj7lb/kernel/cmdline
278 12:26:21.181853 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:26:21.181995 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:26:21.182142 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:26:21.182283 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:26:21.182394 Not connected, no need to disconnect.
283 12:26:21.182556 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:26:21.182690 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:26:21.182849 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 12:26:21.187109 Setting prompt string to ['lava-test: # ']
287 12:26:21.187619 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:26:21.187831 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:26:21.187970 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:26:21.188157 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:26:21.188545 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 12:26:26.320657 >> Command sent successfully.
293 12:26:26.323003 Returned 0 in 5 seconds
294 12:26:26.423440 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:26:26.424106 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:26:26.424248 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:26:26.424377 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:26:26.424472 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:26:26.424588 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:26:26.424956 [Enter `^Ec?' for help]
302 12:26:26.596265
303 12:26:26.596427
304 12:26:26.596505 F0: 102B 0000
305 12:26:26.596569
306 12:26:26.596630 F3: 1001 0000 [0200]
307 12:26:26.600041
308 12:26:26.600126 F3: 1001 0000
309 12:26:26.600194
310 12:26:26.600257 F7: 102D 0000
311 12:26:26.600318
312 12:26:26.603284 F1: 0000 0000
313 12:26:26.603405
314 12:26:26.603473 V0: 0000 0000 [0001]
315 12:26:26.603535
316 12:26:26.606632 00: 0007 8000
317 12:26:26.606720
318 12:26:26.606787 01: 0000 0000
319 12:26:26.606850
320 12:26:26.609740 BP: 0C00 0209 [0000]
321 12:26:26.609825
322 12:26:26.609893 G0: 1182 0000
323 12:26:26.609956
324 12:26:26.613491 EC: 0000 0021 [4000]
325 12:26:26.613576
326 12:26:26.613643 S7: 0000 0000 [0000]
327 12:26:26.613710
328 12:26:26.617369 CC: 0000 0000 [0001]
329 12:26:26.617456
330 12:26:26.617527 T0: 0000 0040 [010F]
331 12:26:26.617597
332 12:26:26.617663 Jump to BL
333 12:26:26.617730
334 12:26:26.643656
335 12:26:26.643745
336 12:26:26.643812
337 12:26:26.651309 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:26:26.654897 ARM64: Exception handlers installed.
339 12:26:26.658355 ARM64: Testing exception
340 12:26:26.661814 ARM64: Done test exception
341 12:26:26.668350 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:26:26.679065 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:26:26.685484 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:26:26.695480 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:26:26.702255 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:26:26.708645 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:26:26.720424 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:26:26.727278 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:26:26.746175 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:26:26.749598 WDT: Last reset was cold boot
351 12:26:26.753198 SPI1(PAD0) initialized at 2873684 Hz
352 12:26:26.755957 SPI5(PAD0) initialized at 992727 Hz
353 12:26:26.759476 VBOOT: Loading verstage.
354 12:26:26.766302 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:26:26.770561 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:26:26.773801 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:26:26.777208 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:26:26.783997 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:26:26.790713 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:26:26.801530 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:26:26.801636
362 12:26:26.801706
363 12:26:26.812208 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:26:26.815548 ARM64: Exception handlers installed.
365 12:26:26.815641 ARM64: Testing exception
366 12:26:26.818861 ARM64: Done test exception
367 12:26:26.822257 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:26:26.828731 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:26:26.842214 Probing TPM: . done!
370 12:26:26.842343 TPM ready after 0 ms
371 12:26:26.849678 Connected to device vid:did:rid of 1ae0:0028:00
372 12:26:26.856635 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 12:26:26.916920 Initialized TPM device CR50 revision 0
374 12:26:26.928291 tlcl_send_startup: Startup return code is 0
375 12:26:26.928465 TPM: setup succeeded
376 12:26:26.939983 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:26:26.948652 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:26:26.963269 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:26:26.970339 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:26:26.974343 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:26:26.977815 in-header: 03 07 00 00 08 00 00 00
382 12:26:26.981194 in-data: aa e4 47 04 13 02 00 00
383 12:26:26.981290 Chrome EC: UHEPI supported
384 12:26:26.988489 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:26:26.992573 in-header: 03 95 00 00 08 00 00 00
386 12:26:26.996544 in-data: 18 20 20 08 00 00 00 00
387 12:26:26.996650 Phase 1
388 12:26:26.999903 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:26:27.007227 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:26:27.011248 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:26:27.014771 Recovery requested (1009000e)
392 12:26:27.024853 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:26:27.030118 tlcl_extend: response is 0
394 12:26:27.039233 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:26:27.044858 tlcl_extend: response is 0
396 12:26:27.051941 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:26:27.071897 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:26:27.078689 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:26:27.078807
400 12:26:27.078879
401 12:26:27.088303 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:26:27.091720 ARM64: Exception handlers installed.
403 12:26:27.095088 ARM64: Testing exception
404 12:26:27.095187 ARM64: Done test exception
405 12:26:27.117068 pmic_efuse_setting: Set efuses in 11 msecs
406 12:26:27.120476 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:26:27.127887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:26:27.131220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:26:27.138511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:26:27.141931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:26:27.145595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:26:27.149528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:26:27.156694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:26:27.160543 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:26:27.163923 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:26:27.171472 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:26:27.175512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:26:27.178919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:26:27.183046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:26:27.190793 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:26:27.194292 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:26:27.202097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:26:27.205273 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:26:27.213462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:26:27.216908 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:26:27.224734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:26:27.228229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:26:27.235976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:26:27.239237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:26:27.247019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:26:27.250217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:26:27.258225 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:26:27.261465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:26:27.265285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:26:27.272893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:26:27.276416 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:26:27.279918 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:26:27.287418 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:26:27.290937 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:26:27.294419 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:26:27.302010 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:26:27.305558 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:26:27.312907 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:26:27.316830 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:26:27.320260 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:26:27.324430 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:26:27.331856 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:26:27.335255 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:26:27.338891 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:26:27.342285 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:26:27.346333 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:26:27.350266 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:26:27.356963 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:26:27.360982 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:26:27.364339 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:26:27.368278 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:26:27.372087 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:26:27.379741 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:26:27.387778 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:26:27.394885 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:26:27.401945 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:26:27.409593 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:26:27.413143 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:26:27.420546 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:26:27.424228 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:26:27.432069 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 12:26:27.434639 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:26:27.442461 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:26:27.445969 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:26:27.454670 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 12:26:27.464497 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 12:26:27.473573 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 12:26:27.483918 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 12:26:27.492771 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 12:26:27.502427 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 12:26:27.512167 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 12:26:27.515774 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:26:27.523297 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:26:27.527237 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:26:27.530673 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:26:27.533828 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:26:27.537857 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:26:27.541846 ADC[4]: Raw value=906573 ID=7
484 12:26:27.541962 ADC[3]: Raw value=213441 ID=1
485 12:26:27.545788 RAM Code: 0x71
486 12:26:27.549224 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:26:27.553364 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:26:27.564669 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:26:27.568762 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:26:27.571475 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:26:27.575345 in-header: 03 07 00 00 08 00 00 00
492 12:26:27.579397 in-data: aa e4 47 04 13 02 00 00
493 12:26:27.582875 Chrome EC: UHEPI supported
494 12:26:27.590119 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:26:27.593610 in-header: 03 95 00 00 08 00 00 00
496 12:26:27.593741 in-data: 18 20 20 08 00 00 00 00
497 12:26:27.597833 MRC: failed to locate region type 0.
498 12:26:27.604727 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:26:27.608214 DRAM-K: Running full calibration
500 12:26:27.616517 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:26:27.616700 header.status = 0x0
502 12:26:27.620066 header.version = 0x6 (expected: 0x6)
503 12:26:27.623572 header.size = 0xd00 (expected: 0xd00)
504 12:26:27.623708 header.flags = 0x0
505 12:26:27.630427 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:26:27.649224 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 12:26:27.657061 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:26:27.657206 dram_init: ddr_geometry: 2
509 12:26:27.661218 [EMI] MDL number = 2
510 12:26:27.661345 [EMI] Get MDL freq = 0
511 12:26:27.664756 dram_init: ddr_type: 0
512 12:26:27.664849 is_discrete_lpddr4: 1
513 12:26:27.668250 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:26:27.668342
515 12:26:27.668412
516 12:26:27.672084 [Bian_co] ETT version 0.0.0.1
517 12:26:27.675944 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:26:27.676043
519 12:26:27.679964 dramc_set_vcore_voltage set vcore to 650000
520 12:26:27.683179 Read voltage for 800, 4
521 12:26:27.683276 Vio18 = 0
522 12:26:27.686884 Vcore = 650000
523 12:26:27.687010 Vdram = 0
524 12:26:27.687084 Vddq = 0
525 12:26:27.687149 Vmddr = 0
526 12:26:27.691462 dram_init: config_dvfs: 1
527 12:26:27.695316 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:26:27.702246 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:26:27.706491 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 12:26:27.709909 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 12:26:27.713343 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 12:26:27.716937 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 12:26:27.717039 MEM_TYPE=3, freq_sel=18
534 12:26:27.721000 sv_algorithm_assistance_LP4_1600
535 12:26:27.724442 ============ PULL DRAM RESETB DOWN ============
536 12:26:27.731280 ========== PULL DRAM RESETB DOWN end =========
537 12:26:27.734649 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:26:27.737956 ===================================
539 12:26:27.741338 LPDDR4 DRAM CONFIGURATION
540 12:26:27.744788 ===================================
541 12:26:27.744887 EX_ROW_EN[0] = 0x0
542 12:26:27.748072 EX_ROW_EN[1] = 0x0
543 12:26:27.748165 LP4Y_EN = 0x0
544 12:26:27.752207 WORK_FSP = 0x0
545 12:26:27.752309 WL = 0x2
546 12:26:27.755668 RL = 0x2
547 12:26:27.755766 BL = 0x2
548 12:26:27.759583 RPST = 0x0
549 12:26:27.759681 RD_PRE = 0x0
550 12:26:27.763110 WR_PRE = 0x1
551 12:26:27.763204 WR_PST = 0x0
552 12:26:27.766715 DBI_WR = 0x0
553 12:26:27.766810 DBI_RD = 0x0
554 12:26:27.769533 OTF = 0x1
555 12:26:27.773164 ===================================
556 12:26:27.776573 ===================================
557 12:26:27.776666 ANA top config
558 12:26:27.779810 ===================================
559 12:26:27.783011 DLL_ASYNC_EN = 0
560 12:26:27.783106 ALL_SLAVE_EN = 1
561 12:26:27.786366 NEW_RANK_MODE = 1
562 12:26:27.789557 DLL_IDLE_MODE = 1
563 12:26:27.793485 LP45_APHY_COMB_EN = 1
564 12:26:27.796650 TX_ODT_DIS = 1
565 12:26:27.796745 NEW_8X_MODE = 1
566 12:26:27.799932 ===================================
567 12:26:27.803934 ===================================
568 12:26:27.806988 data_rate = 1600
569 12:26:27.810162 CKR = 1
570 12:26:27.813609 DQ_P2S_RATIO = 8
571 12:26:27.817092 ===================================
572 12:26:27.817189 CA_P2S_RATIO = 8
573 12:26:27.820512 DQ_CA_OPEN = 0
574 12:26:27.824009 DQ_SEMI_OPEN = 0
575 12:26:27.827356 CA_SEMI_OPEN = 0
576 12:26:27.830882 CA_FULL_RATE = 0
577 12:26:27.833617 DQ_CKDIV4_EN = 1
578 12:26:27.833709 CA_CKDIV4_EN = 1
579 12:26:27.837063 CA_PREDIV_EN = 0
580 12:26:27.840312 PH8_DLY = 0
581 12:26:27.843636 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:26:27.847248 DQ_AAMCK_DIV = 4
583 12:26:27.847370 CA_AAMCK_DIV = 4
584 12:26:27.850629 CA_ADMCK_DIV = 4
585 12:26:27.853932 DQ_TRACK_CA_EN = 0
586 12:26:27.857321 CA_PICK = 800
587 12:26:27.860701 CA_MCKIO = 800
588 12:26:27.864506 MCKIO_SEMI = 0
589 12:26:27.864603 PLL_FREQ = 3068
590 12:26:27.868263 DQ_UI_PI_RATIO = 32
591 12:26:27.871868 CA_UI_PI_RATIO = 0
592 12:26:27.876030 ===================================
593 12:26:27.879576 ===================================
594 12:26:27.879678 memory_type:LPDDR4
595 12:26:27.883819 GP_NUM : 10
596 12:26:27.883914 SRAM_EN : 1
597 12:26:27.887867 MD32_EN : 0
598 12:26:27.891140 ===================================
599 12:26:27.891275 [ANA_INIT] >>>>>>>>>>>>>>
600 12:26:27.894988 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:26:27.899082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:26:27.902295 ===================================
603 12:26:27.905587 data_rate = 1600,PCW = 0X7600
604 12:26:27.908610 ===================================
605 12:26:27.911836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:26:27.915186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:26:27.922354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:26:27.925115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:26:27.928769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:26:27.935588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:26:27.935735 [ANA_INIT] flow start
612 12:26:27.938933 [ANA_INIT] PLL >>>>>>>>
613 12:26:27.939061 [ANA_INIT] PLL <<<<<<<<
614 12:26:27.942413 [ANA_INIT] MIDPI >>>>>>>>
615 12:26:27.945201 [ANA_INIT] MIDPI <<<<<<<<
616 12:26:27.948539 [ANA_INIT] DLL >>>>>>>>
617 12:26:27.948654 [ANA_INIT] flow end
618 12:26:27.951940 ============ LP4 DIFF to SE enter ============
619 12:26:27.958927 ============ LP4 DIFF to SE exit ============
620 12:26:27.959073 [ANA_INIT] <<<<<<<<<<<<<
621 12:26:27.962127 [Flow] Enable top DCM control >>>>>
622 12:26:27.965354 [Flow] Enable top DCM control <<<<<
623 12:26:27.968741 Enable DLL master slave shuffle
624 12:26:27.975497 ==============================================================
625 12:26:27.975641 Gating Mode config
626 12:26:27.982521 ==============================================================
627 12:26:27.985394 Config description:
628 12:26:27.992090 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:26:27.998769 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:26:28.005385 SELPH_MODE 0: By rank 1: By Phase
631 12:26:28.011982 ==============================================================
632 12:26:28.012137 GAT_TRACK_EN = 1
633 12:26:28.015738 RX_GATING_MODE = 2
634 12:26:28.018891 RX_GATING_TRACK_MODE = 2
635 12:26:28.022141 SELPH_MODE = 1
636 12:26:28.025365 PICG_EARLY_EN = 1
637 12:26:28.028643 VALID_LAT_VALUE = 1
638 12:26:28.035536 ==============================================================
639 12:26:28.038935 Enter into Gating configuration >>>>
640 12:26:28.042299 Exit from Gating configuration <<<<
641 12:26:28.045734 Enter into DVFS_PRE_config >>>>>
642 12:26:28.055909 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:26:28.059398 Exit from DVFS_PRE_config <<<<<
644 12:26:28.062217 Enter into PICG configuration >>>>
645 12:26:28.065554 Exit from PICG configuration <<<<
646 12:26:28.068802 [RX_INPUT] configuration >>>>>
647 12:26:28.068919 [RX_INPUT] configuration <<<<<
648 12:26:28.075517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:26:28.082830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:26:28.085593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:26:28.092541 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:26:28.099302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:26:28.106065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:26:28.108795 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:26:28.112597 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:26:28.119472 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:26:28.122661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:26:28.125924 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:26:28.129281 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:26:28.132474 ===================================
661 12:26:28.135936 LPDDR4 DRAM CONFIGURATION
662 12:26:28.139292 ===================================
663 12:26:28.142750 EX_ROW_EN[0] = 0x0
664 12:26:28.142861 EX_ROW_EN[1] = 0x0
665 12:26:28.146195 LP4Y_EN = 0x0
666 12:26:28.146305 WORK_FSP = 0x0
667 12:26:28.149005 WL = 0x2
668 12:26:28.149107 RL = 0x2
669 12:26:28.152361 BL = 0x2
670 12:26:28.152471 RPST = 0x0
671 12:26:28.155716 RD_PRE = 0x0
672 12:26:28.155829 WR_PRE = 0x1
673 12:26:28.159244 WR_PST = 0x0
674 12:26:28.159384 DBI_WR = 0x0
675 12:26:28.162782 DBI_RD = 0x0
676 12:26:28.162882 OTF = 0x1
677 12:26:28.166251 ===================================
678 12:26:28.172952 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:26:28.176148 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:26:28.179446 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:26:28.182758 ===================================
682 12:26:28.186089 LPDDR4 DRAM CONFIGURATION
683 12:26:28.189423 ===================================
684 12:26:28.189538 EX_ROW_EN[0] = 0x10
685 12:26:28.192949 EX_ROW_EN[1] = 0x0
686 12:26:28.195729 LP4Y_EN = 0x0
687 12:26:28.195839 WORK_FSP = 0x0
688 12:26:28.199231 WL = 0x2
689 12:26:28.199361 RL = 0x2
690 12:26:28.202594 BL = 0x2
691 12:26:28.202705 RPST = 0x0
692 12:26:28.205961 RD_PRE = 0x0
693 12:26:28.206075 WR_PRE = 0x1
694 12:26:28.209405 WR_PST = 0x0
695 12:26:28.209535 DBI_WR = 0x0
696 12:26:28.212841 DBI_RD = 0x0
697 12:26:28.212921 OTF = 0x1
698 12:26:28.216116 ===================================
699 12:26:28.222873 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:26:28.226811 nWR fixed to 40
701 12:26:28.230006 [ModeRegInit_LP4] CH0 RK0
702 12:26:28.230134 [ModeRegInit_LP4] CH0 RK1
703 12:26:28.233399 [ModeRegInit_LP4] CH1 RK0
704 12:26:28.236646 [ModeRegInit_LP4] CH1 RK1
705 12:26:28.236727 match AC timing 13
706 12:26:28.243416 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:26:28.246757 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:26:28.250137 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:26:28.257113 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:26:28.260448 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:26:28.260551 [EMI DOE] emi_dcm 0
712 12:26:28.267243 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:26:28.267372 ==
714 12:26:28.270822 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:26:28.273575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:26:28.273665 ==
717 12:26:28.280518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:26:28.283840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:26:28.294547 [CA 0] Center 36 (6~67) winsize 62
720 12:26:28.298058 [CA 1] Center 36 (6~67) winsize 62
721 12:26:28.300785 [CA 2] Center 34 (4~65) winsize 62
722 12:26:28.304255 [CA 3] Center 34 (4~64) winsize 61
723 12:26:28.307580 [CA 4] Center 33 (3~64) winsize 62
724 12:26:28.310951 [CA 5] Center 32 (2~63) winsize 62
725 12:26:28.311044
726 12:26:28.314392 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:26:28.314481
728 12:26:28.317834 [CATrainingPosCal] consider 1 rank data
729 12:26:28.321330 u2DelayCellTimex100 = 270/100 ps
730 12:26:28.324745 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 12:26:28.327828 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 12:26:28.334312 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 12:26:28.338168 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 12:26:28.341446 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 12:26:28.344591 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
736 12:26:28.344684
737 12:26:28.347610 CA PerBit enable=1, Macro0, CA PI delay=32
738 12:26:28.347716
739 12:26:28.351144 [CBTSetCACLKResult] CA Dly = 32
740 12:26:28.351251 CS Dly: 5 (0~36)
741 12:26:28.351321 ==
742 12:26:28.354479 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:26:28.361443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:26:28.361576 ==
745 12:26:28.364765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:26:28.370990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:26:28.380796 [CA 0] Center 36 (6~67) winsize 62
748 12:26:28.384208 [CA 1] Center 36 (6~67) winsize 62
749 12:26:28.387670 [CA 2] Center 34 (3~65) winsize 63
750 12:26:28.390755 [CA 3] Center 33 (3~64) winsize 62
751 12:26:28.394226 [CA 4] Center 33 (3~63) winsize 61
752 12:26:28.397480 [CA 5] Center 32 (2~63) winsize 62
753 12:26:28.397585
754 12:26:28.400949 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 12:26:28.401053
756 12:26:28.404445 [CATrainingPosCal] consider 2 rank data
757 12:26:28.407110 u2DelayCellTimex100 = 270/100 ps
758 12:26:28.410496 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 12:26:28.413882 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 12:26:28.420617 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 12:26:28.424189 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 12:26:28.427627 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 12:26:28.430996 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
764 12:26:28.431105
765 12:26:28.434180 CA PerBit enable=1, Macro0, CA PI delay=32
766 12:26:28.434309
767 12:26:28.437407 [CBTSetCACLKResult] CA Dly = 32
768 12:26:28.437527 CS Dly: 5 (0~36)
769 12:26:28.437652
770 12:26:28.440737 ----->DramcWriteLeveling(PI) begin...
771 12:26:28.444573 ==
772 12:26:28.444695 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:26:28.452391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:26:28.452530 ==
775 12:26:28.452636 Write leveling (Byte 0): 32 => 32
776 12:26:28.456333 Write leveling (Byte 1): 31 => 31
777 12:26:28.459617 DramcWriteLeveling(PI) end<-----
778 12:26:28.459727
779 12:26:28.459827 ==
780 12:26:28.463151 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:26:28.466411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:26:28.466535 ==
783 12:26:28.469720 [Gating] SW mode calibration
784 12:26:28.477088 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:26:28.483406 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:26:28.486882 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:26:28.490283 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:26:28.493796 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 12:26:28.500408 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:26:28.503750 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:26:28.506964 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:26:28.513840 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:26:28.517144 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:26:28.520572 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:26:28.526711 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:26:28.530734 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:26:28.533534 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:26:28.540309 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:26:28.543565 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:26:28.547416 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:26:28.553978 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:26:28.557111 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:26:28.560966 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
804 12:26:28.564259 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 12:26:28.570345 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:26:28.573731 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:26:28.577230 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:26:28.584480 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:26:28.587216 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:26:28.590643 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:26:28.597531 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:26:28.601109 0 9 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
813 12:26:28.604278 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 12:26:28.610785 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:26:28.614055 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:26:28.617517 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:26:28.624187 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:26:28.627625 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:26:28.630956 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
820 12:26:28.637178 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
821 12:26:28.640567 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 12:26:28.643858 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:26:28.647186 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:26:28.653943 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:26:28.657769 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:26:28.661064 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:26:28.667433 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:26:28.670720 0 11 8 | B1->B0 | 2e2e 3c3c | 0 1 | (1 1) (0 0)
829 12:26:28.673979 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
830 12:26:28.680729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:26:28.684095 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:26:28.687498 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:26:28.694477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:26:28.697380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:26:28.700877 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:26:28.708242 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 12:26:28.710910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:26:28.714271 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:26:28.717450 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:26:28.724312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:26:28.727601 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:26:28.730992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:26:28.737885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:26:28.740707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:26:28.744157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:26:28.751167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:26:28.754496 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:26:28.757886 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:26:28.764212 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:26:28.768091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:26:28.770799 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:26:28.777996 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:26:28.778111 Total UI for P1: 0, mck2ui 16
854 12:26:28.784456 best dqsien dly found for B0: ( 0, 14, 4)
855 12:26:28.787703 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 12:26:28.791083 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:26:28.794462 Total UI for P1: 0, mck2ui 16
858 12:26:28.798646 best dqsien dly found for B1: ( 0, 14, 10)
859 12:26:28.802120 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 12:26:28.804913 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 12:26:28.805006
862 12:26:28.808444 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 12:26:28.811899 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 12:26:28.814996 [Gating] SW calibration Done
865 12:26:28.815090 ==
866 12:26:28.818392 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:26:28.821888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:26:28.824995 ==
869 12:26:28.825101 RX Vref Scan: 0
870 12:26:28.825170
871 12:26:28.828415 RX Vref 0 -> 0, step: 1
872 12:26:28.828519
873 12:26:28.831785 RX Delay -130 -> 252, step: 16
874 12:26:28.835154 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
875 12:26:28.838464 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 12:26:28.841944 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 12:26:28.845311 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 12:26:28.848767 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 12:26:28.855063 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 12:26:28.858520 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 12:26:28.861764 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 12:26:28.865125 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
883 12:26:28.868324 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
884 12:26:28.875503 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
885 12:26:28.878684 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 12:26:28.881978 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
887 12:26:28.885322 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
888 12:26:28.891631 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 12:26:28.895010 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
890 12:26:28.895124 ==
891 12:26:28.898474 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:26:28.902066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:26:28.902174 ==
894 12:26:28.902260 DQS Delay:
895 12:26:28.905410 DQS0 = 0, DQS1 = 0
896 12:26:28.905501 DQM Delay:
897 12:26:28.908260 DQM0 = 90, DQM1 = 86
898 12:26:28.908350 DQ Delay:
899 12:26:28.911778 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 12:26:28.915231 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
901 12:26:28.918631 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
902 12:26:28.922084 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
903 12:26:28.922192
904 12:26:28.922276
905 12:26:28.922385 ==
906 12:26:28.925241 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:26:28.928626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:26:28.931894 ==
909 12:26:28.931992
910 12:26:28.932075
911 12:26:28.932137 TX Vref Scan disable
912 12:26:28.935050 == TX Byte 0 ==
913 12:26:28.938434 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 12:26:28.941715 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 12:26:28.945160 == TX Byte 1 ==
916 12:26:28.948640 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 12:26:28.952111 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 12:26:28.955387 ==
919 12:26:28.955497 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:26:28.961619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:26:28.961718 ==
922 12:26:28.973957 TX Vref=22, minBit 5, minWin=27, winSum=444
923 12:26:28.977256 TX Vref=24, minBit 8, minWin=27, winSum=450
924 12:26:28.981081 TX Vref=26, minBit 0, minWin=28, winSum=454
925 12:26:28.984248 TX Vref=28, minBit 0, minWin=28, winSum=455
926 12:26:28.987616 TX Vref=30, minBit 6, minWin=28, winSum=455
927 12:26:28.990784 TX Vref=32, minBit 10, minWin=27, winSum=454
928 12:26:28.997873 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
929 12:26:28.997994
930 12:26:29.000629 Final TX Range 1 Vref 28
931 12:26:29.000731
932 12:26:29.000801 ==
933 12:26:29.004155 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:26:29.007346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:26:29.007471 ==
936 12:26:29.007577
937 12:26:29.007645
938 12:26:29.010807 TX Vref Scan disable
939 12:26:29.014343 == TX Byte 0 ==
940 12:26:29.017806 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 12:26:29.021369 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 12:26:29.024195 == TX Byte 1 ==
943 12:26:29.027489 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 12:26:29.031400 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 12:26:29.031526
946 12:26:29.034810 [DATLAT]
947 12:26:29.034897 Freq=800, CH0 RK0
948 12:26:29.034965
949 12:26:29.037517 DATLAT Default: 0xa
950 12:26:29.037598 0, 0xFFFF, sum = 0
951 12:26:29.040765 1, 0xFFFF, sum = 0
952 12:26:29.040856 2, 0xFFFF, sum = 0
953 12:26:29.044740 3, 0xFFFF, sum = 0
954 12:26:29.044833 4, 0xFFFF, sum = 0
955 12:26:29.047867 5, 0xFFFF, sum = 0
956 12:26:29.047956 6, 0xFFFF, sum = 0
957 12:26:29.051337 7, 0xFFFF, sum = 0
958 12:26:29.051426 8, 0xFFFF, sum = 0
959 12:26:29.054862 9, 0x0, sum = 1
960 12:26:29.054996 10, 0x0, sum = 2
961 12:26:29.057615 11, 0x0, sum = 3
962 12:26:29.057699 12, 0x0, sum = 4
963 12:26:29.061125 best_step = 10
964 12:26:29.061207
965 12:26:29.061282 ==
966 12:26:29.064607 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:26:29.068126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:26:29.068294 ==
969 12:26:29.071667 RX Vref Scan: 1
970 12:26:29.071834
971 12:26:29.071907 Set Vref Range= 32 -> 127
972 12:26:29.071981
973 12:26:29.074924 RX Vref 32 -> 127, step: 1
974 12:26:29.075079
975 12:26:29.078198 RX Delay -79 -> 252, step: 8
976 12:26:29.078465
977 12:26:29.080984 Set Vref, RX VrefLevel [Byte0]: 32
978 12:26:29.084874 [Byte1]: 32
979 12:26:29.085067
980 12:26:29.088197 Set Vref, RX VrefLevel [Byte0]: 33
981 12:26:29.091613 [Byte1]: 33
982 12:26:29.091806
983 12:26:29.094875 Set Vref, RX VrefLevel [Byte0]: 34
984 12:26:29.098011 [Byte1]: 34
985 12:26:29.101963
986 12:26:29.102098 Set Vref, RX VrefLevel [Byte0]: 35
987 12:26:29.105199 [Byte1]: 35
988 12:26:29.109815
989 12:26:29.109939 Set Vref, RX VrefLevel [Byte0]: 36
990 12:26:29.113339 [Byte1]: 36
991 12:26:29.117497
992 12:26:29.117605 Set Vref, RX VrefLevel [Byte0]: 37
993 12:26:29.120328 [Byte1]: 37
994 12:26:29.125196
995 12:26:29.125290 Set Vref, RX VrefLevel [Byte0]: 38
996 12:26:29.128024 [Byte1]: 38
997 12:26:29.132237
998 12:26:29.132372 Set Vref, RX VrefLevel [Byte0]: 39
999 12:26:29.135563 [Byte1]: 39
1000 12:26:29.140136
1001 12:26:29.140237 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:26:29.142802 [Byte1]: 40
1003 12:26:29.147304
1004 12:26:29.147434 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:26:29.150485 [Byte1]: 41
1006 12:26:29.154493
1007 12:26:29.154600 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:26:29.157975 [Byte1]: 42
1009 12:26:29.162202
1010 12:26:29.162341 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:26:29.165661 [Byte1]: 43
1012 12:26:29.169894
1013 12:26:29.170006 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:26:29.173413 [Byte1]: 44
1015 12:26:29.177569
1016 12:26:29.177681 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:26:29.180800 [Byte1]: 45
1018 12:26:29.184678
1019 12:26:29.184798 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:26:29.187960 [Byte1]: 46
1021 12:26:29.192578
1022 12:26:29.192669 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:26:29.195994 [Byte1]: 47
1024 12:26:29.199866
1025 12:26:29.199972 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:26:29.203022 [Byte1]: 48
1027 12:26:29.207507
1028 12:26:29.207614 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:26:29.210767 [Byte1]: 49
1030 12:26:29.214904
1031 12:26:29.215032 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:26:29.218297 [Byte1]: 50
1033 12:26:29.222457
1034 12:26:29.222573 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:26:29.226078 [Byte1]: 51
1036 12:26:29.230228
1037 12:26:29.230351 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:26:29.233680 [Byte1]: 52
1039 12:26:29.237864
1040 12:26:29.237984 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:26:29.241331 [Byte1]: 53
1042 12:26:29.245480
1043 12:26:29.245580 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:26:29.248747 [Byte1]: 54
1045 12:26:29.252537
1046 12:26:29.252639 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:26:29.255829 [Byte1]: 55
1048 12:26:29.260085
1049 12:26:29.260184 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:26:29.263390 [Byte1]: 56
1051 12:26:29.268213
1052 12:26:29.268313 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:26:29.270967 [Byte1]: 57
1054 12:26:29.275760
1055 12:26:29.275855 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:26:29.278561 [Byte1]: 58
1057 12:26:29.283313
1058 12:26:29.283418 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:26:29.286076 [Byte1]: 59
1060 12:26:29.290761
1061 12:26:29.290885 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:26:29.293988 [Byte1]: 60
1063 12:26:29.297854
1064 12:26:29.297947 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:26:29.301670 [Byte1]: 61
1066 12:26:29.305449
1067 12:26:29.305570 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:26:29.308719 [Byte1]: 62
1069 12:26:29.313302
1070 12:26:29.313389 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:26:29.316403 [Byte1]: 63
1072 12:26:29.320574
1073 12:26:29.320675 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:26:29.324050 [Byte1]: 64
1075 12:26:29.328130
1076 12:26:29.328219 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:26:29.331597 [Byte1]: 65
1078 12:26:29.335779
1079 12:26:29.335873 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:26:29.339247 [Byte1]: 66
1081 12:26:29.343435
1082 12:26:29.343548 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:26:29.346822 [Byte1]: 67
1084 12:26:29.350901
1085 12:26:29.351021 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:26:29.354304 [Byte1]: 68
1087 12:26:29.358433
1088 12:26:29.358536 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:26:29.361771 [Byte1]: 69
1090 12:26:29.366239
1091 12:26:29.366337 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:26:29.369423 [Byte1]: 70
1093 12:26:29.373482
1094 12:26:29.373577 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:26:29.376799 [Byte1]: 71
1096 12:26:29.381001
1097 12:26:29.381107 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:26:29.384604 [Byte1]: 72
1099 12:26:29.388674
1100 12:26:29.388765 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:26:29.392147 [Byte1]: 73
1102 12:26:29.396257
1103 12:26:29.396350 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:26:29.399628 [Byte1]: 74
1105 12:26:29.403669
1106 12:26:29.403760 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:26:29.406919 [Byte1]: 75
1108 12:26:29.411391
1109 12:26:29.411488 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:26:29.414699 [Byte1]: 76
1111 12:26:29.419285
1112 12:26:29.419403 Set Vref, RX VrefLevel [Byte0]: 77
1113 12:26:29.422554 [Byte1]: 77
1114 12:26:29.426477
1115 12:26:29.426568 Set Vref, RX VrefLevel [Byte0]: 78
1116 12:26:29.430078 [Byte1]: 78
1117 12:26:29.434268
1118 12:26:29.434372 Final RX Vref Byte 0 = 61 to rank0
1119 12:26:29.437597 Final RX Vref Byte 1 = 62 to rank0
1120 12:26:29.440443 Final RX Vref Byte 0 = 61 to rank1
1121 12:26:29.443837 Final RX Vref Byte 1 = 62 to rank1==
1122 12:26:29.447273 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 12:26:29.454226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 12:26:29.454327 ==
1125 12:26:29.454397 DQS Delay:
1126 12:26:29.454460 DQS0 = 0, DQS1 = 0
1127 12:26:29.457590 DQM Delay:
1128 12:26:29.457686 DQM0 = 92, DQM1 = 86
1129 12:26:29.460818 DQ Delay:
1130 12:26:29.460905 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1131 12:26:29.464158 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1132 12:26:29.467576 DQ8 =76, DQ9 =80, DQ10 =84, DQ11 =80
1133 12:26:29.470982 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1134 12:26:29.474246
1135 12:26:29.474425
1136 12:26:29.480804 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1137 12:26:29.484330 CH0 RK0: MR19=606, MR18=4B41
1138 12:26:29.491181 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1139 12:26:29.491318
1140 12:26:29.494536 ----->DramcWriteLeveling(PI) begin...
1141 12:26:29.494694 ==
1142 12:26:29.497996 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 12:26:29.500817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 12:26:29.500921 ==
1145 12:26:29.504097 Write leveling (Byte 0): 32 => 32
1146 12:26:29.507478 Write leveling (Byte 1): 32 => 32
1147 12:26:29.510768 DramcWriteLeveling(PI) end<-----
1148 12:26:29.510858
1149 12:26:29.510926 ==
1150 12:26:29.514597 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 12:26:29.517917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 12:26:29.518012 ==
1153 12:26:29.561487 [Gating] SW mode calibration
1154 12:26:29.561639 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 12:26:29.561714 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 12:26:29.562026 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 12:26:29.562128 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 12:26:29.562191 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1159 12:26:29.562249 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:26:29.562307 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:26:29.562404 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:26:29.576522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:26:29.576686 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:26:29.577297 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:26:29.579903 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:26:29.583111 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:26:29.586247 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:26:29.589989 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:26:29.593425 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:26:29.599472 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:26:29.603028 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:26:29.606428 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:26:29.613546 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1174 12:26:29.616803 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1175 12:26:29.620196 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:26:29.626672 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:26:29.629904 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:26:29.633236 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:26:29.639827 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:26:29.643265 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:26:29.646761 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:26:29.652973 0 9 8 | B1->B0 | 2929 2f2f | 1 0 | (0 0) (0 0)
1183 12:26:29.656467 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:26:29.659880 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:26:29.663166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:26:29.670046 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:26:29.673453 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:26:29.676760 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 12:26:29.683614 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (0 0) (0 0)
1190 12:26:29.686964 0 10 8 | B1->B0 | 2727 2626 | 0 1 | (0 0) (1 1)
1191 12:26:29.691090 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1192 12:26:29.694844 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:26:29.701975 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:26:29.705394 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:26:29.708769 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:26:29.712211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:26:29.719551 0 11 4 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1198 12:26:29.722746 0 11 8 | B1->B0 | 3a3a 3838 | 0 0 | (0 0) (0 0)
1199 12:26:29.726068 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:26:29.729264 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:26:29.736285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:26:29.739473 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:26:29.742853 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:26:29.749498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 12:26:29.752955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 12:26:29.756387 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 12:26:29.762738 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:26:29.766119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:26:29.769613 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:26:29.775815 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:26:29.779166 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:26:29.783140 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:26:29.789844 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:26:29.793228 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:26:29.796318 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:26:29.799701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:26:29.806139 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:26:29.809416 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:26:29.812924 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:26:29.819830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:26:29.822619 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:26:29.825900 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1223 12:26:29.832936 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 12:26:29.833051 Total UI for P1: 0, mck2ui 16
1225 12:26:29.839266 best dqsien dly found for B0: ( 0, 14, 8)
1226 12:26:29.839406 Total UI for P1: 0, mck2ui 16
1227 12:26:29.846256 best dqsien dly found for B1: ( 0, 14, 10)
1228 12:26:29.849444 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1229 12:26:29.852712 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1230 12:26:29.852802
1231 12:26:29.856584 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 12:26:29.859312 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1233 12:26:29.862789 [Gating] SW calibration Done
1234 12:26:29.862878 ==
1235 12:26:29.866148 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 12:26:29.869488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 12:26:29.869579 ==
1238 12:26:29.873009 RX Vref Scan: 0
1239 12:26:29.873096
1240 12:26:29.873163 RX Vref 0 -> 0, step: 1
1241 12:26:29.873225
1242 12:26:29.876528 RX Delay -130 -> 252, step: 16
1243 12:26:29.879343 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1244 12:26:29.886196 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1245 12:26:29.889664 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1246 12:26:29.892842 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1247 12:26:29.896337 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1248 12:26:29.899787 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1249 12:26:29.906462 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1250 12:26:29.909851 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1251 12:26:29.913135 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1252 12:26:29.916510 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1253 12:26:29.919863 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1254 12:26:29.926625 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1255 12:26:29.930052 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1256 12:26:29.933469 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1257 12:26:29.936192 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1258 12:26:29.939516 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1259 12:26:29.939628 ==
1260 12:26:29.943286 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 12:26:29.949814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 12:26:29.949947 ==
1263 12:26:29.950049 DQS Delay:
1264 12:26:29.953036 DQS0 = 0, DQS1 = 0
1265 12:26:29.953116 DQM Delay:
1266 12:26:29.956259 DQM0 = 91, DQM1 = 83
1267 12:26:29.956371 DQ Delay:
1268 12:26:29.959615 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1269 12:26:29.962806 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1270 12:26:29.966221 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1271 12:26:29.969563 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1272 12:26:29.969650
1273 12:26:29.969721
1274 12:26:29.969783 ==
1275 12:26:29.973089 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 12:26:29.976511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 12:26:29.976591 ==
1278 12:26:29.976657
1279 12:26:29.976717
1280 12:26:29.979993 TX Vref Scan disable
1281 12:26:29.982696 == TX Byte 0 ==
1282 12:26:29.986291 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1283 12:26:29.989647 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1284 12:26:29.992964 == TX Byte 1 ==
1285 12:26:29.996159 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1286 12:26:30.000029 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1287 12:26:30.000120 ==
1288 12:26:30.003488 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 12:26:30.006189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 12:26:30.006300 ==
1291 12:26:30.020576 TX Vref=22, minBit 1, minWin=28, winSum=450
1292 12:26:30.024340 TX Vref=24, minBit 13, minWin=27, winSum=451
1293 12:26:30.027144 TX Vref=26, minBit 1, minWin=28, winSum=456
1294 12:26:30.030421 TX Vref=28, minBit 4, minWin=28, winSum=459
1295 12:26:30.033944 TX Vref=30, minBit 7, minWin=28, winSum=459
1296 12:26:30.037343 TX Vref=32, minBit 4, minWin=28, winSum=457
1297 12:26:30.044061 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1298 12:26:30.044175
1299 12:26:30.047485 Final TX Range 1 Vref 28
1300 12:26:30.047575
1301 12:26:30.047640 ==
1302 12:26:30.050654 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 12:26:30.053867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 12:26:30.053961 ==
1305 12:26:30.054027
1306 12:26:30.057261
1307 12:26:30.057354 TX Vref Scan disable
1308 12:26:30.061016 == TX Byte 0 ==
1309 12:26:30.064350 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1310 12:26:30.067466 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1311 12:26:30.070833 == TX Byte 1 ==
1312 12:26:30.073781 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1313 12:26:30.077214 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1314 12:26:30.080663
1315 12:26:30.080754 [DATLAT]
1316 12:26:30.080821 Freq=800, CH0 RK1
1317 12:26:30.080908
1318 12:26:30.084128 DATLAT Default: 0xa
1319 12:26:30.084203 0, 0xFFFF, sum = 0
1320 12:26:30.087621 1, 0xFFFF, sum = 0
1321 12:26:30.087719 2, 0xFFFF, sum = 0
1322 12:26:30.090391 3, 0xFFFF, sum = 0
1323 12:26:30.090464 4, 0xFFFF, sum = 0
1324 12:26:30.093814 5, 0xFFFF, sum = 0
1325 12:26:30.093888 6, 0xFFFF, sum = 0
1326 12:26:30.097275 7, 0xFFFF, sum = 0
1327 12:26:30.097395 8, 0xFFFF, sum = 0
1328 12:26:30.100560 9, 0x0, sum = 1
1329 12:26:30.100658 10, 0x0, sum = 2
1330 12:26:30.104438 11, 0x0, sum = 3
1331 12:26:30.104525 12, 0x0, sum = 4
1332 12:26:30.107608 best_step = 10
1333 12:26:30.107693
1334 12:26:30.107771 ==
1335 12:26:30.110838 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 12:26:30.114270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 12:26:30.114358 ==
1338 12:26:30.117660 RX Vref Scan: 0
1339 12:26:30.117745
1340 12:26:30.117809 RX Vref 0 -> 0, step: 1
1341 12:26:30.117896
1342 12:26:30.121095 RX Delay -79 -> 252, step: 8
1343 12:26:30.127840 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1344 12:26:30.131113 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1345 12:26:30.134382 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1346 12:26:30.137921 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1347 12:26:30.141239 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1348 12:26:30.144104 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1349 12:26:30.151095 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1350 12:26:30.154551 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1351 12:26:30.157963 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1352 12:26:30.161210 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1353 12:26:30.164691 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1354 12:26:30.170963 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1355 12:26:30.174411 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1356 12:26:30.177677 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1357 12:26:30.180969 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1358 12:26:30.187935 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1359 12:26:30.188047 ==
1360 12:26:30.191296 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 12:26:30.194044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 12:26:30.194126 ==
1363 12:26:30.194193 DQS Delay:
1364 12:26:30.197607 DQS0 = 0, DQS1 = 0
1365 12:26:30.197696 DQM Delay:
1366 12:26:30.201068 DQM0 = 93, DQM1 = 83
1367 12:26:30.201165 DQ Delay:
1368 12:26:30.204490 DQ0 =92, DQ1 =92, DQ2 =92, DQ3 =88
1369 12:26:30.207938 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1370 12:26:30.211201 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1371 12:26:30.214520 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =92
1372 12:26:30.214612
1373 12:26:30.214678
1374 12:26:30.221182 [DQSOSCAuto] RK1, (LSB)MR18= 0x4617, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1375 12:26:30.224662 CH0 RK1: MR19=606, MR18=4617
1376 12:26:30.230818 CH0_RK1: MR19=0x606, MR18=0x4617, DQSOSC=392, MR23=63, INC=96, DEC=64
1377 12:26:30.234756 [RxdqsGatingPostProcess] freq 800
1378 12:26:30.241341 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 12:26:30.241454 Pre-setting of DQS Precalculation
1380 12:26:30.247610 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 12:26:30.247715 ==
1382 12:26:30.250899 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 12:26:30.254343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 12:26:30.254438 ==
1385 12:26:30.261372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 12:26:30.267995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 12:26:30.275700 [CA 0] Center 36 (6~67) winsize 62
1388 12:26:30.279073 [CA 1] Center 36 (6~67) winsize 62
1389 12:26:30.282221 [CA 2] Center 35 (4~66) winsize 63
1390 12:26:30.285373 [CA 3] Center 34 (4~65) winsize 62
1391 12:26:30.288847 [CA 4] Center 34 (4~65) winsize 62
1392 12:26:30.292231 [CA 5] Center 34 (4~65) winsize 62
1393 12:26:30.292344
1394 12:26:30.295736 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1395 12:26:30.295821
1396 12:26:30.299245 [CATrainingPosCal] consider 1 rank data
1397 12:26:30.302061 u2DelayCellTimex100 = 270/100 ps
1398 12:26:30.305579 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 12:26:30.309034 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1400 12:26:30.315253 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1401 12:26:30.318547 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 12:26:30.321802 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 12:26:30.325223 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 12:26:30.325318
1405 12:26:30.328547 CA PerBit enable=1, Macro0, CA PI delay=34
1406 12:26:30.328651
1407 12:26:30.332036 [CBTSetCACLKResult] CA Dly = 34
1408 12:26:30.332125 CS Dly: 6 (0~37)
1409 12:26:30.332192 ==
1410 12:26:30.335443 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 12:26:30.342328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 12:26:30.342467 ==
1413 12:26:30.345580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 12:26:30.352466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 12:26:30.362266 [CA 0] Center 36 (6~67) winsize 62
1416 12:26:30.365623 [CA 1] Center 36 (6~67) winsize 62
1417 12:26:30.369000 [CA 2] Center 35 (5~66) winsize 62
1418 12:26:30.372934 [CA 3] Center 34 (4~65) winsize 62
1419 12:26:30.376844 [CA 4] Center 35 (4~66) winsize 63
1420 12:26:30.380806 [CA 5] Center 34 (4~65) winsize 62
1421 12:26:30.380909
1422 12:26:30.384740 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 12:26:30.384860
1424 12:26:30.387985 [CATrainingPosCal] consider 2 rank data
1425 12:26:30.388073 u2DelayCellTimex100 = 270/100 ps
1426 12:26:30.391335 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 12:26:30.394678 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1428 12:26:30.401675 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1429 12:26:30.404982 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 12:26:30.408540 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 12:26:30.411959 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 12:26:30.412053
1433 12:26:30.415442 CA PerBit enable=1, Macro0, CA PI delay=34
1434 12:26:30.415561
1435 12:26:30.418982 [CBTSetCACLKResult] CA Dly = 34
1436 12:26:30.419068 CS Dly: 7 (0~39)
1437 12:26:30.419135
1438 12:26:30.421592 ----->DramcWriteLeveling(PI) begin...
1439 12:26:30.421680 ==
1440 12:26:30.425095 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 12:26:30.432188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 12:26:30.432296 ==
1443 12:26:30.434794 Write leveling (Byte 0): 28 => 28
1444 12:26:30.438272 Write leveling (Byte 1): 28 => 28
1445 12:26:30.441898 DramcWriteLeveling(PI) end<-----
1446 12:26:30.442021
1447 12:26:30.442117 ==
1448 12:26:30.445355 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:26:30.448778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 12:26:30.448883 ==
1451 12:26:30.451978 [Gating] SW mode calibration
1452 12:26:30.458797 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 12:26:30.462131 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 12:26:30.468878 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 12:26:30.472241 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 12:26:30.474964 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:26:30.482108 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:26:30.485316 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:26:30.488492 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:26:30.495112 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:26:30.499035 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:26:30.502226 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:26:30.508737 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:26:30.512175 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:26:30.515584 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:26:30.518430 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:26:30.525334 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:26:30.528813 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:26:30.532128 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:26:30.538781 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 12:26:30.542085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1472 12:26:30.545569 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:26:30.551781 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:26:30.555147 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:26:30.558976 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:26:30.565518 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:26:30.568997 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:26:30.572463 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:26:30.578651 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1480 12:26:30.582032 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1481 12:26:30.585365 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:26:30.592082 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:26:30.595854 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:26:30.598938 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:26:30.602074 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:26:30.609231 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1487 12:26:30.612389 0 10 4 | B1->B0 | 2f2f 2d2d | 1 0 | (0 0) (0 1)
1488 12:26:30.615784 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1489 12:26:30.622069 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:26:30.625511 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:26:30.628953 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:26:30.635871 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:26:30.639207 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:26:30.642553 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:26:30.649007 0 11 4 | B1->B0 | 2525 3333 | 0 0 | (0 0) (1 1)
1496 12:26:30.652467 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1497 12:26:30.656022 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:26:30.662210 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:26:30.665421 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:26:30.668734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:26:30.675474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:26:30.679029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 12:26:30.682386 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 12:26:30.685795 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:26:30.692484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:26:30.695553 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:26:30.698961 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:26:30.705399 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:26:30.709256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:26:30.712555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:26:30.719105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:26:30.722529 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:26:30.726030 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:26:30.732247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:26:30.735624 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:26:30.739134 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:26:30.745539 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:26:30.748801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:26:30.752734 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 12:26:30.758877 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 12:26:30.759034 Total UI for P1: 0, mck2ui 16
1522 12:26:30.762322 best dqsien dly found for B0: ( 0, 14, 4)
1523 12:26:30.765719 Total UI for P1: 0, mck2ui 16
1524 12:26:30.769090 best dqsien dly found for B1: ( 0, 14, 4)
1525 12:26:30.772356 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1526 12:26:30.778787 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1527 12:26:30.778925
1528 12:26:30.782271 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 12:26:30.785584 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1530 12:26:30.788946 [Gating] SW calibration Done
1531 12:26:30.789062 ==
1532 12:26:30.792361 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 12:26:30.795858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 12:26:30.795975 ==
1535 12:26:30.796073 RX Vref Scan: 0
1536 12:26:30.796173
1537 12:26:30.799202 RX Vref 0 -> 0, step: 1
1538 12:26:30.799309
1539 12:26:30.802420 RX Delay -130 -> 252, step: 16
1540 12:26:30.805545 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1541 12:26:30.809083 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1542 12:26:30.815782 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1543 12:26:30.819030 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1544 12:26:30.822903 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1545 12:26:30.825900 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1546 12:26:30.829170 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1547 12:26:30.832505 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1548 12:26:30.839420 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1549 12:26:30.842841 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1550 12:26:30.845682 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1551 12:26:30.849115 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1552 12:26:30.852666 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1553 12:26:30.859732 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1554 12:26:30.863154 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1555 12:26:30.865871 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1556 12:26:30.865964 ==
1557 12:26:30.869442 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 12:26:30.872849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 12:26:30.876396 ==
1560 12:26:30.876493 DQS Delay:
1561 12:26:30.876563 DQS0 = 0, DQS1 = 0
1562 12:26:30.879499 DQM Delay:
1563 12:26:30.879586 DQM0 = 94, DQM1 = 91
1564 12:26:30.879655 DQ Delay:
1565 12:26:30.882864 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1566 12:26:30.886248 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1567 12:26:30.889689 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1568 12:26:30.893213 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1569 12:26:30.893307
1570 12:26:30.896543
1571 12:26:30.896631 ==
1572 12:26:30.899402 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 12:26:30.902849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 12:26:30.902942 ==
1575 12:26:30.903011
1576 12:26:30.903074
1577 12:26:30.906236 TX Vref Scan disable
1578 12:26:30.906326 == TX Byte 0 ==
1579 12:26:30.912932 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 12:26:30.916231 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 12:26:30.916327 == TX Byte 1 ==
1582 12:26:30.923166 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1583 12:26:30.926402 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1584 12:26:30.926505 ==
1585 12:26:30.929530 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 12:26:30.933536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 12:26:30.933630 ==
1588 12:26:30.946209 TX Vref=22, minBit 3, minWin=26, winSum=434
1589 12:26:30.949745 TX Vref=24, minBit 3, minWin=26, winSum=441
1590 12:26:30.953166 TX Vref=26, minBit 1, minWin=27, winSum=449
1591 12:26:30.956770 TX Vref=28, minBit 0, minWin=27, winSum=452
1592 12:26:30.959461 TX Vref=30, minBit 0, minWin=27, winSum=449
1593 12:26:30.962928 TX Vref=32, minBit 0, minWin=27, winSum=448
1594 12:26:30.970054 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 28
1595 12:26:30.970173
1596 12:26:30.972858 Final TX Range 1 Vref 28
1597 12:26:30.972946
1598 12:26:30.973015 ==
1599 12:26:30.976221 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 12:26:30.979781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 12:26:30.979871 ==
1602 12:26:30.979948
1603 12:26:30.980015
1604 12:26:30.983128 TX Vref Scan disable
1605 12:26:30.986505 == TX Byte 0 ==
1606 12:26:30.989800 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 12:26:30.993137 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 12:26:30.996721 == TX Byte 1 ==
1609 12:26:31.000297 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 12:26:31.003132 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 12:26:31.003213
1612 12:26:31.006603 [DATLAT]
1613 12:26:31.006691 Freq=800, CH1 RK0
1614 12:26:31.006759
1615 12:26:31.010004 DATLAT Default: 0xa
1616 12:26:31.010092 0, 0xFFFF, sum = 0
1617 12:26:31.013324 1, 0xFFFF, sum = 0
1618 12:26:31.013407 2, 0xFFFF, sum = 0
1619 12:26:31.016760 3, 0xFFFF, sum = 0
1620 12:26:31.016842 4, 0xFFFF, sum = 0
1621 12:26:31.020091 5, 0xFFFF, sum = 0
1622 12:26:31.020182 6, 0xFFFF, sum = 0
1623 12:26:31.023448 7, 0xFFFF, sum = 0
1624 12:26:31.023541 8, 0xFFFF, sum = 0
1625 12:26:31.026787 9, 0x0, sum = 1
1626 12:26:31.026883 10, 0x0, sum = 2
1627 12:26:31.029926 11, 0x0, sum = 3
1628 12:26:31.030018 12, 0x0, sum = 4
1629 12:26:31.033591 best_step = 10
1630 12:26:31.033686
1631 12:26:31.033755 ==
1632 12:26:31.036844 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 12:26:31.040144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 12:26:31.040238 ==
1635 12:26:31.043429 RX Vref Scan: 1
1636 12:26:31.043533
1637 12:26:31.043603 Set Vref Range= 32 -> 127
1638 12:26:31.043667
1639 12:26:31.046687 RX Vref 32 -> 127, step: 1
1640 12:26:31.046775
1641 12:26:31.049946 RX Delay -63 -> 252, step: 8
1642 12:26:31.050036
1643 12:26:31.053407 Set Vref, RX VrefLevel [Byte0]: 32
1644 12:26:31.056876 [Byte1]: 32
1645 12:26:31.056968
1646 12:26:31.060386 Set Vref, RX VrefLevel [Byte0]: 33
1647 12:26:31.063105 [Byte1]: 33
1648 12:26:31.063196
1649 12:26:31.066574 Set Vref, RX VrefLevel [Byte0]: 34
1650 12:26:31.070080 [Byte1]: 34
1651 12:26:31.074026
1652 12:26:31.074153 Set Vref, RX VrefLevel [Byte0]: 35
1653 12:26:31.077363 [Byte1]: 35
1654 12:26:31.081203
1655 12:26:31.081317 Set Vref, RX VrefLevel [Byte0]: 36
1656 12:26:31.084542 [Byte1]: 36
1657 12:26:31.088774
1658 12:26:31.088903 Set Vref, RX VrefLevel [Byte0]: 37
1659 12:26:31.092078 [Byte1]: 37
1660 12:26:31.096628
1661 12:26:31.096760 Set Vref, RX VrefLevel [Byte0]: 38
1662 12:26:31.099854 [Byte1]: 38
1663 12:26:31.104048
1664 12:26:31.104165 Set Vref, RX VrefLevel [Byte0]: 39
1665 12:26:31.106831 [Byte1]: 39
1666 12:26:31.111616
1667 12:26:31.111721 Set Vref, RX VrefLevel [Byte0]: 40
1668 12:26:31.114386 [Byte1]: 40
1669 12:26:31.118474
1670 12:26:31.118593 Set Vref, RX VrefLevel [Byte0]: 41
1671 12:26:31.121878 [Byte1]: 41
1672 12:26:31.126033
1673 12:26:31.126161 Set Vref, RX VrefLevel [Byte0]: 42
1674 12:26:31.129372 [Byte1]: 42
1675 12:26:31.134097
1676 12:26:31.134228 Set Vref, RX VrefLevel [Byte0]: 43
1677 12:26:31.137372 [Byte1]: 43
1678 12:26:31.141249
1679 12:26:31.141377 Set Vref, RX VrefLevel [Byte0]: 44
1680 12:26:31.144416 [Byte1]: 44
1681 12:26:31.148948
1682 12:26:31.149083 Set Vref, RX VrefLevel [Byte0]: 45
1683 12:26:31.152251 [Byte1]: 45
1684 12:26:31.155912
1685 12:26:31.156035 Set Vref, RX VrefLevel [Byte0]: 46
1686 12:26:31.159823 [Byte1]: 46
1687 12:26:31.163963
1688 12:26:31.164090 Set Vref, RX VrefLevel [Byte0]: 47
1689 12:26:31.167334 [Byte1]: 47
1690 12:26:31.171540
1691 12:26:31.171638 Set Vref, RX VrefLevel [Byte0]: 48
1692 12:26:31.174333 [Byte1]: 48
1693 12:26:31.179003
1694 12:26:31.179130 Set Vref, RX VrefLevel [Byte0]: 49
1695 12:26:31.182367 [Byte1]: 49
1696 12:26:31.186330
1697 12:26:31.186430 Set Vref, RX VrefLevel [Byte0]: 50
1698 12:26:31.189772 [Byte1]: 50
1699 12:26:31.193943
1700 12:26:31.194028 Set Vref, RX VrefLevel [Byte0]: 51
1701 12:26:31.197333 [Byte1]: 51
1702 12:26:31.201228
1703 12:26:31.201349 Set Vref, RX VrefLevel [Byte0]: 52
1704 12:26:31.204500 [Byte1]: 52
1705 12:26:31.208679
1706 12:26:31.208774 Set Vref, RX VrefLevel [Byte0]: 53
1707 12:26:31.211953 [Byte1]: 53
1708 12:26:31.216104
1709 12:26:31.216228 Set Vref, RX VrefLevel [Byte0]: 54
1710 12:26:31.219551 [Byte1]: 54
1711 12:26:31.223560
1712 12:26:31.223658 Set Vref, RX VrefLevel [Byte0]: 55
1713 12:26:31.226902 [Byte1]: 55
1714 12:26:31.231086
1715 12:26:31.231216 Set Vref, RX VrefLevel [Byte0]: 56
1716 12:26:31.234503 [Byte1]: 56
1717 12:26:31.238495
1718 12:26:31.238622 Set Vref, RX VrefLevel [Byte0]: 57
1719 12:26:31.241764 [Byte1]: 57
1720 12:26:31.246455
1721 12:26:31.246571 Set Vref, RX VrefLevel [Byte0]: 58
1722 12:26:31.249759 [Byte1]: 58
1723 12:26:31.253783
1724 12:26:31.253906 Set Vref, RX VrefLevel [Byte0]: 59
1725 12:26:31.257006 [Byte1]: 59
1726 12:26:31.261516
1727 12:26:31.261681 Set Vref, RX VrefLevel [Byte0]: 60
1728 12:26:31.264869 [Byte1]: 60
1729 12:26:31.268944
1730 12:26:31.269088 Set Vref, RX VrefLevel [Byte0]: 61
1731 12:26:31.271818 [Byte1]: 61
1732 12:26:31.275971
1733 12:26:31.276058 Set Vref, RX VrefLevel [Byte0]: 62
1734 12:26:31.279384 [Byte1]: 62
1735 12:26:31.283423
1736 12:26:31.283516 Set Vref, RX VrefLevel [Byte0]: 63
1737 12:26:31.286848 [Byte1]: 63
1738 12:26:31.290951
1739 12:26:31.291069 Set Vref, RX VrefLevel [Byte0]: 64
1740 12:26:31.294233 [Byte1]: 64
1741 12:26:31.298323
1742 12:26:31.298425 Set Vref, RX VrefLevel [Byte0]: 65
1743 12:26:31.301769 [Byte1]: 65
1744 12:26:31.306340
1745 12:26:31.306445 Set Vref, RX VrefLevel [Byte0]: 66
1746 12:26:31.309744 [Byte1]: 66
1747 12:26:31.314070
1748 12:26:31.314218 Set Vref, RX VrefLevel [Byte0]: 67
1749 12:26:31.316931 [Byte1]: 67
1750 12:26:31.321099
1751 12:26:31.321201 Set Vref, RX VrefLevel [Byte0]: 68
1752 12:26:31.324636 [Byte1]: 68
1753 12:26:31.328852
1754 12:26:31.328991 Set Vref, RX VrefLevel [Byte0]: 69
1755 12:26:31.331735 [Byte1]: 69
1756 12:26:31.335921
1757 12:26:31.336053 Set Vref, RX VrefLevel [Byte0]: 70
1758 12:26:31.339506 [Byte1]: 70
1759 12:26:31.343739
1760 12:26:31.343848 Set Vref, RX VrefLevel [Byte0]: 71
1761 12:26:31.347296 [Byte1]: 71
1762 12:26:31.350994
1763 12:26:31.351132 Set Vref, RX VrefLevel [Byte0]: 72
1764 12:26:31.354430 [Byte1]: 72
1765 12:26:31.358481
1766 12:26:31.358629 Set Vref, RX VrefLevel [Byte0]: 73
1767 12:26:31.361811 [Byte1]: 73
1768 12:26:31.366458
1769 12:26:31.366608 Set Vref, RX VrefLevel [Byte0]: 74
1770 12:26:31.369142 [Byte1]: 74
1771 12:26:31.373901
1772 12:26:31.374042 Set Vref, RX VrefLevel [Byte0]: 75
1773 12:26:31.376673 [Byte1]: 75
1774 12:26:31.380971
1775 12:26:31.381113 Final RX Vref Byte 0 = 54 to rank0
1776 12:26:31.384554 Final RX Vref Byte 1 = 55 to rank0
1777 12:26:31.387925 Final RX Vref Byte 0 = 54 to rank1
1778 12:26:31.391472 Final RX Vref Byte 1 = 55 to rank1==
1779 12:26:31.394248 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 12:26:31.400890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 12:26:31.401016 ==
1782 12:26:31.401090 DQS Delay:
1783 12:26:31.401154 DQS0 = 0, DQS1 = 0
1784 12:26:31.404419 DQM Delay:
1785 12:26:31.404511 DQM0 = 95, DQM1 = 90
1786 12:26:31.407902 DQ Delay:
1787 12:26:31.411223 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1788 12:26:31.414478 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1789 12:26:31.417696 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1790 12:26:31.420994 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =96
1791 12:26:31.421082
1792 12:26:31.421185
1793 12:26:31.427823 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1794 12:26:31.431210 CH1 RK0: MR19=606, MR18=2E4B
1795 12:26:31.438052 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1796 12:26:31.438190
1797 12:26:31.440902 ----->DramcWriteLeveling(PI) begin...
1798 12:26:31.440987 ==
1799 12:26:31.444276 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 12:26:31.447786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 12:26:31.447919 ==
1802 12:26:31.451149 Write leveling (Byte 0): 27 => 27
1803 12:26:31.454618 Write leveling (Byte 1): 27 => 27
1804 12:26:31.458316 DramcWriteLeveling(PI) end<-----
1805 12:26:31.458424
1806 12:26:31.458499 ==
1807 12:26:31.460971 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 12:26:31.464504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 12:26:31.464626 ==
1810 12:26:31.468036 [Gating] SW mode calibration
1811 12:26:31.474913 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 12:26:31.481294 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 12:26:31.484837 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 12:26:31.488314 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1815 12:26:31.494374 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:26:31.497858 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:26:31.501389 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:26:31.508200 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:26:31.511147 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:26:31.514748 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:26:31.521679 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:26:31.524853 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:26:31.528357 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:26:31.534785 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:26:31.538123 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:26:31.541517 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:26:31.545032 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:26:31.551322 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:26:31.554698 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1830 12:26:31.558000 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1831 12:26:31.564793 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:26:31.568260 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:26:31.571665 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:26:31.578245 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:26:31.581830 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:26:31.585066 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:26:31.592040 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:26:31.594863 0 9 4 | B1->B0 | 2727 2323 | 1 0 | (1 1) (1 1)
1839 12:26:31.598230 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
1840 12:26:31.601687 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:26:31.608438 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:26:31.611834 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 12:26:31.615347 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 12:26:31.622176 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 12:26:31.624934 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 12:26:31.628253 0 10 4 | B1->B0 | 2c2c 3030 | 0 1 | (0 1) (1 0)
1847 12:26:31.635480 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:26:31.638757 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:26:31.642032 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:26:31.648747 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:26:31.652228 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:26:31.654950 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:26:31.661750 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1854 12:26:31.665172 0 11 4 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
1855 12:26:31.668558 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1856 12:26:31.674969 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 12:26:31.678760 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:26:31.681516 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 12:26:31.688541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 12:26:31.691805 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:26:31.695317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 12:26:31.698209 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1863 12:26:31.704998 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:26:31.708486 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:26:31.711903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:26:31.718907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:26:31.721772 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:26:31.725319 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:26:31.732170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:26:31.735405 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:26:31.738843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:26:31.745382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:26:31.748559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:26:31.752002 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:26:31.758986 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:26:31.762314 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:26:31.765756 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:26:31.768878 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1879 12:26:31.775725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 12:26:31.778458 Total UI for P1: 0, mck2ui 16
1881 12:26:31.781998 best dqsien dly found for B0: ( 0, 14, 4)
1882 12:26:31.785332 Total UI for P1: 0, mck2ui 16
1883 12:26:31.788511 best dqsien dly found for B1: ( 0, 14, 4)
1884 12:26:31.791942 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1885 12:26:31.795188 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1886 12:26:31.795317
1887 12:26:31.798466 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1888 12:26:31.801909 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 12:26:31.805263 [Gating] SW calibration Done
1890 12:26:31.805376 ==
1891 12:26:31.808666 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 12:26:31.812240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 12:26:31.812349 ==
1894 12:26:31.815088 RX Vref Scan: 0
1895 12:26:31.815178
1896 12:26:31.815267 RX Vref 0 -> 0, step: 1
1897 12:26:31.815401
1898 12:26:31.818607 RX Delay -130 -> 252, step: 16
1899 12:26:31.822169 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1900 12:26:31.829083 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1901 12:26:31.832432 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1902 12:26:31.836066 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1903 12:26:31.838809 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1904 12:26:31.842167 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1905 12:26:31.848989 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1906 12:26:31.852082 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1907 12:26:31.855444 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1908 12:26:31.859303 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1909 12:26:31.862157 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1910 12:26:31.868940 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1911 12:26:31.872322 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1912 12:26:31.875444 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1913 12:26:31.878988 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1914 12:26:31.882462 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1915 12:26:31.886064 ==
1916 12:26:31.886169 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:26:31.892233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 12:26:31.892371 ==
1919 12:26:31.892448 DQS Delay:
1920 12:26:31.895573 DQS0 = 0, DQS1 = 0
1921 12:26:31.895665 DQM Delay:
1922 12:26:31.898806 DQM0 = 93, DQM1 = 91
1923 12:26:31.898903 DQ Delay:
1924 12:26:31.902152 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1925 12:26:31.905511 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1926 12:26:31.908835 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1927 12:26:31.912210 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1928 12:26:31.912335
1929 12:26:31.912439
1930 12:26:31.912546 ==
1931 12:26:31.915715 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 12:26:31.919191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 12:26:31.919335 ==
1934 12:26:31.919463
1935 12:26:31.919561
1936 12:26:31.922571 TX Vref Scan disable
1937 12:26:31.925373 == TX Byte 0 ==
1938 12:26:31.928828 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1939 12:26:31.932192 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1940 12:26:31.935598 == TX Byte 1 ==
1941 12:26:31.939042 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1942 12:26:31.942460 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1943 12:26:31.942569 ==
1944 12:26:31.945850 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 12:26:31.949246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 12:26:31.952001 ==
1947 12:26:31.963804 TX Vref=22, minBit 7, minWin=26, winSum=440
1948 12:26:31.967120 TX Vref=24, minBit 3, minWin=26, winSum=441
1949 12:26:31.970456 TX Vref=26, minBit 2, minWin=26, winSum=449
1950 12:26:31.973793 TX Vref=28, minBit 3, minWin=26, winSum=448
1951 12:26:31.976998 TX Vref=30, minBit 4, minWin=27, winSum=453
1952 12:26:31.980271 TX Vref=32, minBit 0, minWin=27, winSum=448
1953 12:26:31.987277 [TxChooseVref] Worse bit 4, Min win 27, Win sum 453, Final Vref 30
1954 12:26:31.987423
1955 12:26:31.990789 Final TX Range 1 Vref 30
1956 12:26:31.990884
1957 12:26:31.990953 ==
1958 12:26:31.993504 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 12:26:31.996849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 12:26:31.996968 ==
1961 12:26:31.997066
1962 12:26:31.997161
1963 12:26:32.000300 TX Vref Scan disable
1964 12:26:32.003532 == TX Byte 0 ==
1965 12:26:32.007259 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1966 12:26:32.010634 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1967 12:26:32.013831 == TX Byte 1 ==
1968 12:26:32.016932 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1969 12:26:32.020392 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1970 12:26:32.020523
1971 12:26:32.023682 [DATLAT]
1972 12:26:32.023817 Freq=800, CH1 RK1
1973 12:26:32.023922
1974 12:26:32.027126 DATLAT Default: 0xa
1975 12:26:32.027248 0, 0xFFFF, sum = 0
1976 12:26:32.030577 1, 0xFFFF, sum = 0
1977 12:26:32.030703 2, 0xFFFF, sum = 0
1978 12:26:32.033979 3, 0xFFFF, sum = 0
1979 12:26:32.034066 4, 0xFFFF, sum = 0
1980 12:26:32.037405 5, 0xFFFF, sum = 0
1981 12:26:32.037495 6, 0xFFFF, sum = 0
1982 12:26:32.040812 7, 0xFFFF, sum = 0
1983 12:26:32.040896 8, 0xFFFF, sum = 0
1984 12:26:32.043726 9, 0x0, sum = 1
1985 12:26:32.043816 10, 0x0, sum = 2
1986 12:26:32.047073 11, 0x0, sum = 3
1987 12:26:32.047155 12, 0x0, sum = 4
1988 12:26:32.050375 best_step = 10
1989 12:26:32.050465
1990 12:26:32.050536 ==
1991 12:26:32.053823 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 12:26:32.057172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 12:26:32.057263 ==
1994 12:26:32.060694 RX Vref Scan: 0
1995 12:26:32.060828
1996 12:26:32.060937 RX Vref 0 -> 0, step: 1
1997 12:26:32.061037
1998 12:26:32.063882 RX Delay -63 -> 252, step: 8
1999 12:26:32.070406 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2000 12:26:32.074364 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2001 12:26:32.077566 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2002 12:26:32.080808 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2003 12:26:32.084012 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2004 12:26:32.087285 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2005 12:26:32.090668 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2006 12:26:32.097662 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
2007 12:26:32.100509 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2008 12:26:32.103946 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2009 12:26:32.107363 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2010 12:26:32.110824 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2011 12:26:32.117402 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2012 12:26:32.120548 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2013 12:26:32.123709 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2014 12:26:32.127547 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2015 12:26:32.127656 ==
2016 12:26:32.130805 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 12:26:32.137574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 12:26:32.137693 ==
2019 12:26:32.137774 DQS Delay:
2020 12:26:32.140366 DQS0 = 0, DQS1 = 0
2021 12:26:32.140449 DQM Delay:
2022 12:26:32.140516 DQM0 = 97, DQM1 = 91
2023 12:26:32.143858 DQ Delay:
2024 12:26:32.147277 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2025 12:26:32.150756 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =92
2026 12:26:32.154025 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2027 12:26:32.157363 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2028 12:26:32.157466
2029 12:26:32.157539
2030 12:26:32.164113 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2031 12:26:32.167444 CH1 RK1: MR19=606, MR18=440E
2032 12:26:32.174253 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2033 12:26:32.177331 [RxdqsGatingPostProcess] freq 800
2034 12:26:32.180705 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 12:26:32.184034 Pre-setting of DQS Precalculation
2036 12:26:32.190606 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 12:26:32.197511 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 12:26:32.203826 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 12:26:32.203970
2040 12:26:32.204078
2041 12:26:32.207311 [Calibration Summary] 1600 Mbps
2042 12:26:32.207430 CH 0, Rank 0
2043 12:26:32.210733 SW Impedance : PASS
2044 12:26:32.214258 DUTY Scan : NO K
2045 12:26:32.214393 ZQ Calibration : PASS
2046 12:26:32.217247 Jitter Meter : NO K
2047 12:26:32.220726 CBT Training : PASS
2048 12:26:32.220859 Write leveling : PASS
2049 12:26:32.223990 RX DQS gating : PASS
2050 12:26:32.227167 RX DQ/DQS(RDDQC) : PASS
2051 12:26:32.227282 TX DQ/DQS : PASS
2052 12:26:32.230929 RX DATLAT : PASS
2053 12:26:32.234126 RX DQ/DQS(Engine): PASS
2054 12:26:32.234243 TX OE : NO K
2055 12:26:32.234344 All Pass.
2056 12:26:32.237397
2057 12:26:32.237511 CH 0, Rank 1
2058 12:26:32.237614 SW Impedance : PASS
2059 12:26:32.240714 DUTY Scan : NO K
2060 12:26:32.244073 ZQ Calibration : PASS
2061 12:26:32.244210 Jitter Meter : NO K
2062 12:26:32.247416 CBT Training : PASS
2063 12:26:32.250844 Write leveling : PASS
2064 12:26:32.250975 RX DQS gating : PASS
2065 12:26:32.253537 RX DQ/DQS(RDDQC) : PASS
2066 12:26:32.257549 TX DQ/DQS : PASS
2067 12:26:32.257678 RX DATLAT : PASS
2068 12:26:32.260324 RX DQ/DQS(Engine): PASS
2069 12:26:32.263752 TX OE : NO K
2070 12:26:32.263894 All Pass.
2071 12:26:32.264008
2072 12:26:32.264111 CH 1, Rank 0
2073 12:26:32.267195 SW Impedance : PASS
2074 12:26:32.270788 DUTY Scan : NO K
2075 12:26:32.270918 ZQ Calibration : PASS
2076 12:26:32.274200 Jitter Meter : NO K
2077 12:26:32.277663 CBT Training : PASS
2078 12:26:32.277786 Write leveling : PASS
2079 12:26:32.280351 RX DQS gating : PASS
2080 12:26:32.283702 RX DQ/DQS(RDDQC) : PASS
2081 12:26:32.283817 TX DQ/DQS : PASS
2082 12:26:32.287516 RX DATLAT : PASS
2083 12:26:32.287637 RX DQ/DQS(Engine): PASS
2084 12:26:32.290780 TX OE : NO K
2085 12:26:32.290902 All Pass.
2086 12:26:32.291013
2087 12:26:32.294055 CH 1, Rank 1
2088 12:26:32.294170 SW Impedance : PASS
2089 12:26:32.297205 DUTY Scan : NO K
2090 12:26:32.300724 ZQ Calibration : PASS
2091 12:26:32.300860 Jitter Meter : NO K
2092 12:26:32.304245 CBT Training : PASS
2093 12:26:32.307024 Write leveling : PASS
2094 12:26:32.307145 RX DQS gating : PASS
2095 12:26:32.310481 RX DQ/DQS(RDDQC) : PASS
2096 12:26:32.314080 TX DQ/DQS : PASS
2097 12:26:32.314240 RX DATLAT : PASS
2098 12:26:32.317570 RX DQ/DQS(Engine): PASS
2099 12:26:32.320454 TX OE : NO K
2100 12:26:32.320612 All Pass.
2101 12:26:32.320719
2102 12:26:32.320853 DramC Write-DBI off
2103 12:26:32.323887 PER_BANK_REFRESH: Hybrid Mode
2104 12:26:32.327285 TX_TRACKING: ON
2105 12:26:32.330687 [GetDramInforAfterCalByMRR] Vendor 6.
2106 12:26:32.333920 [GetDramInforAfterCalByMRR] Revision 606.
2107 12:26:32.337291 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 12:26:32.337421 MR0 0x3b3b
2109 12:26:32.340702 MR8 0x5151
2110 12:26:32.343991 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 12:26:32.344115
2112 12:26:32.344212 MR0 0x3b3b
2113 12:26:32.344304 MR8 0x5151
2114 12:26:32.347272 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 12:26:32.347413
2116 12:26:32.357022 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 12:26:32.360413 [FAST_K] Save calibration result to emmc
2118 12:26:32.363810 [FAST_K] Save calibration result to emmc
2119 12:26:32.367352 dram_init: config_dvfs: 1
2120 12:26:32.370833 dramc_set_vcore_voltage set vcore to 662500
2121 12:26:32.374255 Read voltage for 1200, 2
2122 12:26:32.374385 Vio18 = 0
2123 12:26:32.374486 Vcore = 662500
2124 12:26:32.377703 Vdram = 0
2125 12:26:32.377818 Vddq = 0
2126 12:26:32.377916 Vmddr = 0
2127 12:26:32.384111 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 12:26:32.387414 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 12:26:32.390701 MEM_TYPE=3, freq_sel=15
2130 12:26:32.393894 sv_algorithm_assistance_LP4_1600
2131 12:26:32.397780 ============ PULL DRAM RESETB DOWN ============
2132 12:26:32.401011 ========== PULL DRAM RESETB DOWN end =========
2133 12:26:32.407807 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 12:26:32.410563 ===================================
2135 12:26:32.413996 LPDDR4 DRAM CONFIGURATION
2136 12:26:32.417557 ===================================
2137 12:26:32.417700 EX_ROW_EN[0] = 0x0
2138 12:26:32.420858 EX_ROW_EN[1] = 0x0
2139 12:26:32.420985 LP4Y_EN = 0x0
2140 12:26:32.424322 WORK_FSP = 0x0
2141 12:26:32.424453 WL = 0x4
2142 12:26:32.427866 RL = 0x4
2143 12:26:32.427981 BL = 0x2
2144 12:26:32.431142 RPST = 0x0
2145 12:26:32.431253 RD_PRE = 0x0
2146 12:26:32.434464 WR_PRE = 0x1
2147 12:26:32.434582 WR_PST = 0x0
2148 12:26:32.437888 DBI_WR = 0x0
2149 12:26:32.438009 DBI_RD = 0x0
2150 12:26:32.441219 OTF = 0x1
2151 12:26:32.444477 ===================================
2152 12:26:32.447701 ===================================
2153 12:26:32.447826 ANA top config
2154 12:26:32.451081 ===================================
2155 12:26:32.454570 DLL_ASYNC_EN = 0
2156 12:26:32.457860 ALL_SLAVE_EN = 0
2157 12:26:32.461359 NEW_RANK_MODE = 1
2158 12:26:32.461500 DLL_IDLE_MODE = 1
2159 12:26:32.464156 LP45_APHY_COMB_EN = 1
2160 12:26:32.467394 TX_ODT_DIS = 1
2161 12:26:32.470710 NEW_8X_MODE = 1
2162 12:26:32.474135 ===================================
2163 12:26:32.477672 ===================================
2164 12:26:32.477796 data_rate = 2400
2165 12:26:32.481118 CKR = 1
2166 12:26:32.484564 DQ_P2S_RATIO = 8
2167 12:26:32.488097 ===================================
2168 12:26:32.490827 CA_P2S_RATIO = 8
2169 12:26:32.494346 DQ_CA_OPEN = 0
2170 12:26:32.497703 DQ_SEMI_OPEN = 0
2171 12:26:32.497830 CA_SEMI_OPEN = 0
2172 12:26:32.501010 CA_FULL_RATE = 0
2173 12:26:32.504226 DQ_CKDIV4_EN = 0
2174 12:26:32.507442 CA_CKDIV4_EN = 0
2175 12:26:32.510811 CA_PREDIV_EN = 0
2176 12:26:32.514094 PH8_DLY = 17
2177 12:26:32.514225 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 12:26:32.517591 DQ_AAMCK_DIV = 4
2179 12:26:32.521087 CA_AAMCK_DIV = 4
2180 12:26:32.524473 CA_ADMCK_DIV = 4
2181 12:26:32.527879 DQ_TRACK_CA_EN = 0
2182 12:26:32.531320 CA_PICK = 1200
2183 12:26:32.534804 CA_MCKIO = 1200
2184 12:26:32.534912 MCKIO_SEMI = 0
2185 12:26:32.537476 PLL_FREQ = 2366
2186 12:26:32.540920 DQ_UI_PI_RATIO = 32
2187 12:26:32.544368 CA_UI_PI_RATIO = 0
2188 12:26:32.547562 ===================================
2189 12:26:32.550803 ===================================
2190 12:26:32.554564 memory_type:LPDDR4
2191 12:26:32.554705 GP_NUM : 10
2192 12:26:32.557720 SRAM_EN : 1
2193 12:26:32.557852 MD32_EN : 0
2194 12:26:32.561092 ===================================
2195 12:26:32.564353 [ANA_INIT] >>>>>>>>>>>>>>
2196 12:26:32.567575 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 12:26:32.571018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 12:26:32.574346 ===================================
2199 12:26:32.577901 data_rate = 2400,PCW = 0X5b00
2200 12:26:32.581405 ===================================
2201 12:26:32.584831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 12:26:32.591019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 12:26:32.594516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 12:26:32.601431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 12:26:32.604904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 12:26:32.608314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 12:26:32.608452 [ANA_INIT] flow start
2208 12:26:32.611488 [ANA_INIT] PLL >>>>>>>>
2209 12:26:32.614734 [ANA_INIT] PLL <<<<<<<<
2210 12:26:32.614852 [ANA_INIT] MIDPI >>>>>>>>
2211 12:26:32.617809 [ANA_INIT] MIDPI <<<<<<<<
2212 12:26:32.621089 [ANA_INIT] DLL >>>>>>>>
2213 12:26:32.621220 [ANA_INIT] DLL <<<<<<<<
2214 12:26:32.624548 [ANA_INIT] flow end
2215 12:26:32.627979 ============ LP4 DIFF to SE enter ============
2216 12:26:32.631395 ============ LP4 DIFF to SE exit ============
2217 12:26:32.634946 [ANA_INIT] <<<<<<<<<<<<<
2218 12:26:32.638307 [Flow] Enable top DCM control >>>>>
2219 12:26:32.641714 [Flow] Enable top DCM control <<<<<
2220 12:26:32.644452 Enable DLL master slave shuffle
2221 12:26:32.651515 ==============================================================
2222 12:26:32.651657 Gating Mode config
2223 12:26:32.658187 ==============================================================
2224 12:26:32.658329 Config description:
2225 12:26:32.667860 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 12:26:32.674642 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 12:26:32.681303 SELPH_MODE 0: By rank 1: By Phase
2228 12:26:32.684459 ==============================================================
2229 12:26:32.687862 GAT_TRACK_EN = 1
2230 12:26:32.691417 RX_GATING_MODE = 2
2231 12:26:32.694864 RX_GATING_TRACK_MODE = 2
2232 12:26:32.698215 SELPH_MODE = 1
2233 12:26:32.701522 PICG_EARLY_EN = 1
2234 12:26:32.704997 VALID_LAT_VALUE = 1
2235 12:26:32.708491 ==============================================================
2236 12:26:32.711332 Enter into Gating configuration >>>>
2237 12:26:32.714791 Exit from Gating configuration <<<<
2238 12:26:32.718102 Enter into DVFS_PRE_config >>>>>
2239 12:26:32.731791 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 12:26:32.734552 Exit from DVFS_PRE_config <<<<<
2241 12:26:32.734661 Enter into PICG configuration >>>>
2242 12:26:32.738078 Exit from PICG configuration <<<<
2243 12:26:32.741438 [RX_INPUT] configuration >>>>>
2244 12:26:32.745315 [RX_INPUT] configuration <<<<<
2245 12:26:32.751541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 12:26:32.754875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 12:26:32.761853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 12:26:32.768146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 12:26:32.774710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 12:26:32.781471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 12:26:32.784768 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 12:26:32.788273 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 12:26:32.791522 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 12:26:32.798380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 12:26:32.801586 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 12:26:32.804990 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 12:26:32.808415 ===================================
2258 12:26:32.811942 LPDDR4 DRAM CONFIGURATION
2259 12:26:32.814821 ===================================
2260 12:26:32.814940 EX_ROW_EN[0] = 0x0
2261 12:26:32.818255 EX_ROW_EN[1] = 0x0
2262 12:26:32.821663 LP4Y_EN = 0x0
2263 12:26:32.821769 WORK_FSP = 0x0
2264 12:26:32.824895 WL = 0x4
2265 12:26:32.824988 RL = 0x4
2266 12:26:32.828262 BL = 0x2
2267 12:26:32.828358 RPST = 0x0
2268 12:26:32.831425 RD_PRE = 0x0
2269 12:26:32.831523 WR_PRE = 0x1
2270 12:26:32.834662 WR_PST = 0x0
2271 12:26:32.834765 DBI_WR = 0x0
2272 12:26:32.838645 DBI_RD = 0x0
2273 12:26:32.838745 OTF = 0x1
2274 12:26:32.841400 ===================================
2275 12:26:32.844756 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 12:26:32.851694 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 12:26:32.855006 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 12:26:32.858339 ===================================
2279 12:26:32.861847 LPDDR4 DRAM CONFIGURATION
2280 12:26:32.865294 ===================================
2281 12:26:32.865426 EX_ROW_EN[0] = 0x10
2282 12:26:32.868440 EX_ROW_EN[1] = 0x0
2283 12:26:32.868526 LP4Y_EN = 0x0
2284 12:26:32.871872 WORK_FSP = 0x0
2285 12:26:32.871994 WL = 0x4
2286 12:26:32.875265 RL = 0x4
2287 12:26:32.875396 BL = 0x2
2288 12:26:32.878696 RPST = 0x0
2289 12:26:32.878812 RD_PRE = 0x0
2290 12:26:32.882006 WR_PRE = 0x1
2291 12:26:32.882103 WR_PST = 0x0
2292 12:26:32.885364 DBI_WR = 0x0
2293 12:26:32.885480 DBI_RD = 0x0
2294 12:26:32.888792 OTF = 0x1
2295 12:26:32.892209 ===================================
2296 12:26:32.898243 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 12:26:32.898353 ==
2298 12:26:32.902371 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 12:26:32.905565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 12:26:32.905657 ==
2301 12:26:32.908409 [Duty_Offset_Calibration]
2302 12:26:32.908491 B0:2 B1:1 CA:1
2303 12:26:32.908560
2304 12:26:32.911869 [DutyScan_Calibration_Flow] k_type=0
2305 12:26:32.922314
2306 12:26:32.922442 ==CLK 0==
2307 12:26:32.925838 Final CLK duty delay cell = 0
2308 12:26:32.929044 [0] MAX Duty = 5187%(X100), DQS PI = 24
2309 12:26:32.932355 [0] MIN Duty = 4875%(X100), DQS PI = 0
2310 12:26:32.932470 [0] AVG Duty = 5031%(X100)
2311 12:26:32.935697
2312 12:26:32.935792 CH0 CLK Duty spec in!! Max-Min= 312%
2313 12:26:32.942834 [DutyScan_Calibration_Flow] ====Done====
2314 12:26:32.942987
2315 12:26:32.946211 [DutyScan_Calibration_Flow] k_type=1
2316 12:26:32.961262
2317 12:26:32.961393 ==DQS 0 ==
2318 12:26:32.964105 Final DQS duty delay cell = -4
2319 12:26:32.967590 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2320 12:26:32.970996 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2321 12:26:32.974273 [-4] AVG Duty = 4969%(X100)
2322 12:26:32.974393
2323 12:26:32.974497 ==DQS 1 ==
2324 12:26:32.977591 Final DQS duty delay cell = 0
2325 12:26:32.981010 [0] MAX Duty = 5156%(X100), DQS PI = 0
2326 12:26:32.984500 [0] MIN Duty = 5031%(X100), DQS PI = 32
2327 12:26:32.987857 [0] AVG Duty = 5093%(X100)
2328 12:26:32.987944
2329 12:26:32.991107 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2330 12:26:32.991221
2331 12:26:32.994370 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2332 12:26:32.997777 [DutyScan_Calibration_Flow] ====Done====
2333 12:26:32.997896
2334 12:26:33.001177 [DutyScan_Calibration_Flow] k_type=3
2335 12:26:33.017967
2336 12:26:33.018097 ==DQM 0 ==
2337 12:26:33.020881 Final DQM duty delay cell = 0
2338 12:26:33.024307 [0] MAX Duty = 5156%(X100), DQS PI = 24
2339 12:26:33.027865 [0] MIN Duty = 4906%(X100), DQS PI = 58
2340 12:26:33.027980 [0] AVG Duty = 5031%(X100)
2341 12:26:33.031240
2342 12:26:33.031361 ==DQM 1 ==
2343 12:26:33.034781 Final DQM duty delay cell = 0
2344 12:26:33.037988 [0] MAX Duty = 5124%(X100), DQS PI = 8
2345 12:26:33.041205 [0] MIN Duty = 5031%(X100), DQS PI = 14
2346 12:26:33.041311 [0] AVG Duty = 5077%(X100)
2347 12:26:33.041397
2348 12:26:33.044564 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2349 12:26:33.047768
2350 12:26:33.051078 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2351 12:26:33.054584 [DutyScan_Calibration_Flow] ====Done====
2352 12:26:33.054699
2353 12:26:33.058067 [DutyScan_Calibration_Flow] k_type=2
2354 12:26:33.074037
2355 12:26:33.074208 ==DQ 0 ==
2356 12:26:33.077467 Final DQ duty delay cell = 0
2357 12:26:33.080839 [0] MAX Duty = 5062%(X100), DQS PI = 30
2358 12:26:33.084279 [0] MIN Duty = 4875%(X100), DQS PI = 62
2359 12:26:33.084416 [0] AVG Duty = 4968%(X100)
2360 12:26:33.084522
2361 12:26:33.087737 ==DQ 1 ==
2362 12:26:33.090658 Final DQ duty delay cell = 0
2363 12:26:33.094155 [0] MAX Duty = 5093%(X100), DQS PI = 26
2364 12:26:33.097309 [0] MIN Duty = 4938%(X100), DQS PI = 34
2365 12:26:33.097436 [0] AVG Duty = 5015%(X100)
2366 12:26:33.097541
2367 12:26:33.100742 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2368 12:26:33.104032
2369 12:26:33.107194 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2370 12:26:33.110514 [DutyScan_Calibration_Flow] ====Done====
2371 12:26:33.110641 ==
2372 12:26:33.113901 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 12:26:33.117594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 12:26:33.117722 ==
2375 12:26:33.120910 [Duty_Offset_Calibration]
2376 12:26:33.121032 B0:1 B1:0 CA:1
2377 12:26:33.121137
2378 12:26:33.124342 [DutyScan_Calibration_Flow] k_type=0
2379 12:26:33.133356
2380 12:26:33.133504 ==CLK 0==
2381 12:26:33.136802 Final CLK duty delay cell = -4
2382 12:26:33.140266 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2383 12:26:33.143661 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2384 12:26:33.146937 [-4] AVG Duty = 4969%(X100)
2385 12:26:33.147066
2386 12:26:33.150147 CH1 CLK Duty spec in!! Max-Min= 124%
2387 12:26:33.153384 [DutyScan_Calibration_Flow] ====Done====
2388 12:26:33.153506
2389 12:26:33.156566 [DutyScan_Calibration_Flow] k_type=1
2390 12:26:33.173473
2391 12:26:33.173640 ==DQS 0 ==
2392 12:26:33.176238 Final DQS duty delay cell = 0
2393 12:26:33.179817 [0] MAX Duty = 5094%(X100), DQS PI = 24
2394 12:26:33.183312 [0] MIN Duty = 4875%(X100), DQS PI = 0
2395 12:26:33.183482 [0] AVG Duty = 4984%(X100)
2396 12:26:33.186783
2397 12:26:33.186906 ==DQS 1 ==
2398 12:26:33.189713 Final DQS duty delay cell = 0
2399 12:26:33.193214 [0] MAX Duty = 5187%(X100), DQS PI = 18
2400 12:26:33.196539 [0] MIN Duty = 4969%(X100), DQS PI = 10
2401 12:26:33.196658 [0] AVG Duty = 5078%(X100)
2402 12:26:33.196793
2403 12:26:33.203429 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2404 12:26:33.203592
2405 12:26:33.206813 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2406 12:26:33.209943 [DutyScan_Calibration_Flow] ====Done====
2407 12:26:33.210073
2408 12:26:33.213028 [DutyScan_Calibration_Flow] k_type=3
2409 12:26:33.229740
2410 12:26:33.229924 ==DQM 0 ==
2411 12:26:33.233248 Final DQM duty delay cell = 0
2412 12:26:33.236677 [0] MAX Duty = 5156%(X100), DQS PI = 6
2413 12:26:33.240052 [0] MIN Duty = 5031%(X100), DQS PI = 0
2414 12:26:33.240202 [0] AVG Duty = 5093%(X100)
2415 12:26:33.240351
2416 12:26:33.242907 ==DQM 1 ==
2417 12:26:33.246481 Final DQM duty delay cell = 0
2418 12:26:33.249833 [0] MAX Duty = 5062%(X100), DQS PI = 26
2419 12:26:33.253178 [0] MIN Duty = 4907%(X100), DQS PI = 36
2420 12:26:33.253312 [0] AVG Duty = 4984%(X100)
2421 12:26:33.253434
2422 12:26:33.256486 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2423 12:26:33.259691
2424 12:26:33.263602 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2425 12:26:33.266316 [DutyScan_Calibration_Flow] ====Done====
2426 12:26:33.266448
2427 12:26:33.269516 [DutyScan_Calibration_Flow] k_type=2
2428 12:26:33.285341
2429 12:26:33.285489 ==DQ 0 ==
2430 12:26:33.288719 Final DQ duty delay cell = -4
2431 12:26:33.292209 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2432 12:26:33.295725 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2433 12:26:33.299114 [-4] AVG Duty = 4984%(X100)
2434 12:26:33.299216
2435 12:26:33.299321 ==DQ 1 ==
2436 12:26:33.301842 Final DQ duty delay cell = 0
2437 12:26:33.305366 [0] MAX Duty = 5125%(X100), DQS PI = 20
2438 12:26:33.308837 [0] MIN Duty = 4969%(X100), DQS PI = 12
2439 12:26:33.308954 [0] AVG Duty = 5047%(X100)
2440 12:26:33.312240
2441 12:26:33.315613 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2442 12:26:33.315730
2443 12:26:33.319184 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2444 12:26:33.322280 [DutyScan_Calibration_Flow] ====Done====
2445 12:26:33.325439 nWR fixed to 30
2446 12:26:33.325541 [ModeRegInit_LP4] CH0 RK0
2447 12:26:33.329123 [ModeRegInit_LP4] CH0 RK1
2448 12:26:33.332768 [ModeRegInit_LP4] CH1 RK0
2449 12:26:33.332895 [ModeRegInit_LP4] CH1 RK1
2450 12:26:33.335306 match AC timing 7
2451 12:26:33.339229 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 12:26:33.342060 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 12:26:33.348911 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 12:26:33.352382 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 12:26:33.359303 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 12:26:33.359474 ==
2457 12:26:33.362475 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 12:26:33.365871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 12:26:33.365970 ==
2460 12:26:33.372507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 12:26:33.375671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 12:26:33.385477 [CA 0] Center 39 (8~70) winsize 63
2463 12:26:33.388784 [CA 1] Center 39 (8~70) winsize 63
2464 12:26:33.392195 [CA 2] Center 35 (5~66) winsize 62
2465 12:26:33.395527 [CA 3] Center 34 (4~65) winsize 62
2466 12:26:33.399070 [CA 4] Center 33 (3~64) winsize 62
2467 12:26:33.402483 [CA 5] Center 32 (3~62) winsize 60
2468 12:26:33.402607
2469 12:26:33.405980 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2470 12:26:33.406092
2471 12:26:33.408690 [CATrainingPosCal] consider 1 rank data
2472 12:26:33.412112 u2DelayCellTimex100 = 270/100 ps
2473 12:26:33.415690 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2474 12:26:33.419075 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2475 12:26:33.425968 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2476 12:26:33.429252 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2477 12:26:33.432668 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2478 12:26:33.435335 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2479 12:26:33.435460
2480 12:26:33.438837 CA PerBit enable=1, Macro0, CA PI delay=32
2481 12:26:33.438925
2482 12:26:33.442250 [CBTSetCACLKResult] CA Dly = 32
2483 12:26:33.442334 CS Dly: 6 (0~37)
2484 12:26:33.442400 ==
2485 12:26:33.445734 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 12:26:33.452682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 12:26:33.452819 ==
2488 12:26:33.455384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 12:26:33.462339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2490 12:26:33.471552 [CA 0] Center 38 (8~69) winsize 62
2491 12:26:33.474728 [CA 1] Center 38 (8~69) winsize 62
2492 12:26:33.478397 [CA 2] Center 35 (4~66) winsize 63
2493 12:26:33.481207 [CA 3] Center 34 (4~65) winsize 62
2494 12:26:33.484581 [CA 4] Center 33 (3~63) winsize 61
2495 12:26:33.488215 [CA 5] Center 32 (3~62) winsize 60
2496 12:26:33.488313
2497 12:26:33.491624 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2498 12:26:33.491711
2499 12:26:33.494403 [CATrainingPosCal] consider 2 rank data
2500 12:26:33.497787 u2DelayCellTimex100 = 270/100 ps
2501 12:26:33.501104 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2502 12:26:33.504520 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2503 12:26:33.511222 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2504 12:26:33.514703 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2505 12:26:33.518072 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2506 12:26:33.521377 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2507 12:26:33.521497
2508 12:26:33.524843 CA PerBit enable=1, Macro0, CA PI delay=32
2509 12:26:33.524937
2510 12:26:33.528305 [CBTSetCACLKResult] CA Dly = 32
2511 12:26:33.528392 CS Dly: 6 (0~38)
2512 12:26:33.528462
2513 12:26:33.531513 ----->DramcWriteLeveling(PI) begin...
2514 12:26:33.534398 ==
2515 12:26:33.537778 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:26:33.541212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:26:33.541339 ==
2518 12:26:33.544547 Write leveling (Byte 0): 34 => 34
2519 12:26:33.547963 Write leveling (Byte 1): 30 => 30
2520 12:26:33.551227 DramcWriteLeveling(PI) end<-----
2521 12:26:33.551320
2522 12:26:33.551423 ==
2523 12:26:33.554651 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 12:26:33.558062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 12:26:33.558164 ==
2526 12:26:33.561566 [Gating] SW mode calibration
2527 12:26:33.568037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 12:26:33.571225 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 12:26:33.577963 0 15 0 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
2530 12:26:33.581705 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2531 12:26:33.585045 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:26:33.591588 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 12:26:33.594980 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 12:26:33.598390 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 12:26:33.605038 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
2536 12:26:33.608520 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
2537 12:26:33.611921 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2538 12:26:33.618305 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:26:33.621774 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:26:33.625273 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 12:26:33.628700 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 12:26:33.635205 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 12:26:33.638692 1 0 24 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
2544 12:26:33.642239 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2545 12:26:33.648751 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2546 12:26:33.652096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:26:33.654888 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:26:33.662086 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:26:33.664911 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 12:26:33.668460 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 12:26:33.675306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:26:33.678590 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 12:26:33.681805 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 12:26:33.688958 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:26:33.692090 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:26:33.695358 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:26:33.702114 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:26:33.705374 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:26:33.708737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:26:33.712121 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:26:33.718927 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:26:33.722448 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:26:33.725284 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:26:33.732198 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:26:33.735534 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:26:33.738860 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:26:33.745789 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 12:26:33.749148 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 12:26:33.752465 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 12:26:33.755750 Total UI for P1: 0, mck2ui 16
2571 12:26:33.758978 best dqsien dly found for B0: ( 1, 3, 26)
2572 12:26:33.765674 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 12:26:33.765803 Total UI for P1: 0, mck2ui 16
2574 12:26:33.768443 best dqsien dly found for B1: ( 1, 4, 0)
2575 12:26:33.775388 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2576 12:26:33.778882 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 12:26:33.778982
2578 12:26:33.782247 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2579 12:26:33.785628 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 12:26:33.788769 [Gating] SW calibration Done
2581 12:26:33.788865 ==
2582 12:26:33.792021 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 12:26:33.795262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 12:26:33.795363 ==
2585 12:26:33.795434 RX Vref Scan: 0
2586 12:26:33.798574
2587 12:26:33.798667 RX Vref 0 -> 0, step: 1
2588 12:26:33.798758
2589 12:26:33.801867 RX Delay -40 -> 252, step: 8
2590 12:26:33.805719 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2591 12:26:33.808970 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2592 12:26:33.815124 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2593 12:26:33.818712 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2594 12:26:33.822320 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2595 12:26:33.825849 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2596 12:26:33.829168 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2597 12:26:33.836089 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2598 12:26:33.838778 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2599 12:26:33.842714 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2600 12:26:33.845418 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2601 12:26:33.848888 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2602 12:26:33.855721 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2603 12:26:33.858835 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2604 12:26:33.862088 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2605 12:26:33.865858 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2606 12:26:33.865983 ==
2607 12:26:33.869123 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 12:26:33.872479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 12:26:33.875915 ==
2610 12:26:33.876018 DQS Delay:
2611 12:26:33.876089 DQS0 = 0, DQS1 = 0
2612 12:26:33.879304 DQM Delay:
2613 12:26:33.879417 DQM0 = 121, DQM1 = 113
2614 12:26:33.882112 DQ Delay:
2615 12:26:33.885448 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2616 12:26:33.888981 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2617 12:26:33.892281 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2618 12:26:33.896102 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2619 12:26:33.896204
2620 12:26:33.896274
2621 12:26:33.896351 ==
2622 12:26:33.899357 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 12:26:33.902464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 12:26:33.902590 ==
2625 12:26:33.902688
2626 12:26:33.902808
2627 12:26:33.905813 TX Vref Scan disable
2628 12:26:33.908861 == TX Byte 0 ==
2629 12:26:33.912745 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2630 12:26:33.916024 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2631 12:26:33.919234 == TX Byte 1 ==
2632 12:26:33.922590 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2633 12:26:33.925986 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2634 12:26:33.926101 ==
2635 12:26:33.929411 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 12:26:33.932812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 12:26:33.935460 ==
2638 12:26:33.946110 TX Vref=22, minBit 0, minWin=24, winSum=400
2639 12:26:33.949540 TX Vref=24, minBit 3, minWin=25, winSum=413
2640 12:26:33.953054 TX Vref=26, minBit 3, minWin=25, winSum=414
2641 12:26:33.956402 TX Vref=28, minBit 8, minWin=25, winSum=418
2642 12:26:33.959221 TX Vref=30, minBit 12, minWin=25, winSum=422
2643 12:26:33.966032 TX Vref=32, minBit 10, minWin=25, winSum=418
2644 12:26:33.969383 [TxChooseVref] Worse bit 12, Min win 25, Win sum 422, Final Vref 30
2645 12:26:33.969481
2646 12:26:33.972771 Final TX Range 1 Vref 30
2647 12:26:33.972870
2648 12:26:33.972939 ==
2649 12:26:33.976119 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 12:26:33.979500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 12:26:33.979590 ==
2652 12:26:33.979658
2653 12:26:33.982904
2654 12:26:33.983006 TX Vref Scan disable
2655 12:26:33.986209 == TX Byte 0 ==
2656 12:26:33.989688 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2657 12:26:33.993171 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2658 12:26:33.996778 == TX Byte 1 ==
2659 12:26:33.999512 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2660 12:26:34.003336 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2661 12:26:34.003434
2662 12:26:34.006527 [DATLAT]
2663 12:26:34.006620 Freq=1200, CH0 RK0
2664 12:26:34.006690
2665 12:26:34.009730 DATLAT Default: 0xd
2666 12:26:34.009820 0, 0xFFFF, sum = 0
2667 12:26:34.013034 1, 0xFFFF, sum = 0
2668 12:26:34.013127 2, 0xFFFF, sum = 0
2669 12:26:34.016126 3, 0xFFFF, sum = 0
2670 12:26:34.016217 4, 0xFFFF, sum = 0
2671 12:26:34.020049 5, 0xFFFF, sum = 0
2672 12:26:34.020142 6, 0xFFFF, sum = 0
2673 12:26:34.023096 7, 0xFFFF, sum = 0
2674 12:26:34.023215 8, 0xFFFF, sum = 0
2675 12:26:34.026507 9, 0xFFFF, sum = 0
2676 12:26:34.029919 10, 0xFFFF, sum = 0
2677 12:26:34.030011 11, 0xFFFF, sum = 0
2678 12:26:34.033350 12, 0x0, sum = 1
2679 12:26:34.033470 13, 0x0, sum = 2
2680 12:26:34.033571 14, 0x0, sum = 3
2681 12:26:34.036900 15, 0x0, sum = 4
2682 12:26:34.036991 best_step = 13
2683 12:26:34.037060
2684 12:26:34.037123 ==
2685 12:26:34.040290 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:26:34.046243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:26:34.046383 ==
2688 12:26:34.046466 RX Vref Scan: 1
2689 12:26:34.046533
2690 12:26:34.050151 Set Vref Range= 32 -> 127
2691 12:26:34.050272
2692 12:26:34.053491 RX Vref 32 -> 127, step: 1
2693 12:26:34.053621
2694 12:26:34.056955 RX Delay -13 -> 252, step: 4
2695 12:26:34.057081
2696 12:26:34.059518 Set Vref, RX VrefLevel [Byte0]: 32
2697 12:26:34.063076 [Byte1]: 32
2698 12:26:34.063198
2699 12:26:34.066386 Set Vref, RX VrefLevel [Byte0]: 33
2700 12:26:34.069891 [Byte1]: 33
2701 12:26:34.070019
2702 12:26:34.073242 Set Vref, RX VrefLevel [Byte0]: 34
2703 12:26:34.076480 [Byte1]: 34
2704 12:26:34.080400
2705 12:26:34.080493 Set Vref, RX VrefLevel [Byte0]: 35
2706 12:26:34.083776 [Byte1]: 35
2707 12:26:34.088411
2708 12:26:34.088506 Set Vref, RX VrefLevel [Byte0]: 36
2709 12:26:34.091888 [Byte1]: 36
2710 12:26:34.095978
2711 12:26:34.096066 Set Vref, RX VrefLevel [Byte0]: 37
2712 12:26:34.099397 [Byte1]: 37
2713 12:26:34.104233
2714 12:26:34.104340 Set Vref, RX VrefLevel [Byte0]: 38
2715 12:26:34.107738 [Byte1]: 38
2716 12:26:34.111765
2717 12:26:34.111873 Set Vref, RX VrefLevel [Byte0]: 39
2718 12:26:34.115372 [Byte1]: 39
2719 12:26:34.119693
2720 12:26:34.119793 Set Vref, RX VrefLevel [Byte0]: 40
2721 12:26:34.122925 [Byte1]: 40
2722 12:26:34.127580
2723 12:26:34.127675 Set Vref, RX VrefLevel [Byte0]: 41
2724 12:26:34.130742 [Byte1]: 41
2725 12:26:34.135945
2726 12:26:34.136046 Set Vref, RX VrefLevel [Byte0]: 42
2727 12:26:34.138797 [Byte1]: 42
2728 12:26:34.143555
2729 12:26:34.143660 Set Vref, RX VrefLevel [Byte0]: 43
2730 12:26:34.146872 [Byte1]: 43
2731 12:26:34.151797
2732 12:26:34.151905 Set Vref, RX VrefLevel [Byte0]: 44
2733 12:26:34.154431 [Byte1]: 44
2734 12:26:34.159314
2735 12:26:34.159424 Set Vref, RX VrefLevel [Byte0]: 45
2736 12:26:34.162986 [Byte1]: 45
2737 12:26:34.167201
2738 12:26:34.167339 Set Vref, RX VrefLevel [Byte0]: 46
2739 12:26:34.170590 [Byte1]: 46
2740 12:26:34.174770
2741 12:26:34.174891 Set Vref, RX VrefLevel [Byte0]: 47
2742 12:26:34.178239 [Byte1]: 47
2743 12:26:34.182916
2744 12:26:34.183029 Set Vref, RX VrefLevel [Byte0]: 48
2745 12:26:34.186376 [Byte1]: 48
2746 12:26:34.190976
2747 12:26:34.191071 Set Vref, RX VrefLevel [Byte0]: 49
2748 12:26:34.194268 [Byte1]: 49
2749 12:26:34.199123
2750 12:26:34.199274 Set Vref, RX VrefLevel [Byte0]: 50
2751 12:26:34.201860 [Byte1]: 50
2752 12:26:34.206810
2753 12:26:34.206908 Set Vref, RX VrefLevel [Byte0]: 51
2754 12:26:34.210233 [Byte1]: 51
2755 12:26:34.214349
2756 12:26:34.214451 Set Vref, RX VrefLevel [Byte0]: 52
2757 12:26:34.217818 [Byte1]: 52
2758 12:26:34.222234
2759 12:26:34.222342 Set Vref, RX VrefLevel [Byte0]: 53
2760 12:26:34.225535 [Byte1]: 53
2761 12:26:34.230090
2762 12:26:34.230185 Set Vref, RX VrefLevel [Byte0]: 54
2763 12:26:34.233935 [Byte1]: 54
2764 12:26:34.238045
2765 12:26:34.238145 Set Vref, RX VrefLevel [Byte0]: 55
2766 12:26:34.241346 [Byte1]: 55
2767 12:26:34.245783
2768 12:26:34.245880 Set Vref, RX VrefLevel [Byte0]: 56
2769 12:26:34.249156 [Byte1]: 56
2770 12:26:34.253889
2771 12:26:34.253989 Set Vref, RX VrefLevel [Byte0]: 57
2772 12:26:34.257323 [Byte1]: 57
2773 12:26:34.262077
2774 12:26:34.262173 Set Vref, RX VrefLevel [Byte0]: 58
2775 12:26:34.264873 [Byte1]: 58
2776 12:26:34.269704
2777 12:26:34.269805 Set Vref, RX VrefLevel [Byte0]: 59
2778 12:26:34.273165 [Byte1]: 59
2779 12:26:34.277973
2780 12:26:34.278071 Set Vref, RX VrefLevel [Byte0]: 60
2781 12:26:34.280813 [Byte1]: 60
2782 12:26:34.285625
2783 12:26:34.285720 Set Vref, RX VrefLevel [Byte0]: 61
2784 12:26:34.288996 [Byte1]: 61
2785 12:26:34.293707
2786 12:26:34.293841 Set Vref, RX VrefLevel [Byte0]: 62
2787 12:26:34.296373 [Byte1]: 62
2788 12:26:34.301512
2789 12:26:34.301638 Set Vref, RX VrefLevel [Byte0]: 63
2790 12:26:34.304396 [Byte1]: 63
2791 12:26:34.309291
2792 12:26:34.309387 Set Vref, RX VrefLevel [Byte0]: 64
2793 12:26:34.312740 [Byte1]: 64
2794 12:26:34.316921
2795 12:26:34.317015 Set Vref, RX VrefLevel [Byte0]: 65
2796 12:26:34.320362 [Byte1]: 65
2797 12:26:34.325053
2798 12:26:34.325153 Set Vref, RX VrefLevel [Byte0]: 66
2799 12:26:34.328459 [Byte1]: 66
2800 12:26:34.333195
2801 12:26:34.333298 Set Vref, RX VrefLevel [Byte0]: 67
2802 12:26:34.336439 [Byte1]: 67
2803 12:26:34.340823
2804 12:26:34.340936 Set Vref, RX VrefLevel [Byte0]: 68
2805 12:26:34.344338 [Byte1]: 68
2806 12:26:34.348939
2807 12:26:34.349076 Set Vref, RX VrefLevel [Byte0]: 69
2808 12:26:34.352204 [Byte1]: 69
2809 12:26:34.356574
2810 12:26:34.360039 Final RX Vref Byte 0 = 55 to rank0
2811 12:26:34.360130 Final RX Vref Byte 1 = 48 to rank0
2812 12:26:34.363424 Final RX Vref Byte 0 = 55 to rank1
2813 12:26:34.366930 Final RX Vref Byte 1 = 48 to rank1==
2814 12:26:34.369580 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 12:26:34.376558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 12:26:34.376681 ==
2817 12:26:34.376752 DQS Delay:
2818 12:26:34.376833 DQS0 = 0, DQS1 = 0
2819 12:26:34.380050 DQM Delay:
2820 12:26:34.380128 DQM0 = 120, DQM1 = 111
2821 12:26:34.383398 DQ Delay:
2822 12:26:34.386891 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2823 12:26:34.389739 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2824 12:26:34.393141 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
2825 12:26:34.396370 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2826 12:26:34.396464
2827 12:26:34.396533
2828 12:26:34.403477 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2829 12:26:34.406841 CH0 RK0: MR19=404, MR18=150E
2830 12:26:34.413550 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2831 12:26:34.413674
2832 12:26:34.417080 ----->DramcWriteLeveling(PI) begin...
2833 12:26:34.417174 ==
2834 12:26:34.420428 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 12:26:34.423155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 12:26:34.426510 ==
2837 12:26:34.426605 Write leveling (Byte 0): 34 => 34
2838 12:26:34.429748 Write leveling (Byte 1): 30 => 30
2839 12:26:34.433746 DramcWriteLeveling(PI) end<-----
2840 12:26:34.433844
2841 12:26:34.433916 ==
2842 12:26:34.436574 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 12:26:34.443218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 12:26:34.443341 ==
2845 12:26:34.443421 [Gating] SW mode calibration
2846 12:26:34.453476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 12:26:34.456782 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 12:26:34.459889 0 15 0 | B1->B0 | 3232 2e2e | 0 1 | (0 0) (0 0)
2849 12:26:34.467062 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 12:26:34.470292 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 12:26:34.473745 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 12:26:34.479911 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 12:26:34.483305 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 12:26:34.486895 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2855 12:26:34.493121 0 15 28 | B1->B0 | 2e2e 2c2c | 1 0 | (1 1) (0 0)
2856 12:26:34.496574 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2857 12:26:34.500048 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 12:26:34.507054 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 12:26:34.510389 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 12:26:34.513638 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 12:26:34.520351 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 12:26:34.523762 1 0 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
2863 12:26:34.526542 1 0 28 | B1->B0 | 3a3a 3a3a | 1 0 | (0 0) (0 0)
2864 12:26:34.533480 1 1 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
2865 12:26:34.536751 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 12:26:34.540290 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 12:26:34.543792 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 12:26:34.549918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 12:26:34.553237 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 12:26:34.556473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2871 12:26:34.563523 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2872 12:26:34.566759 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2873 12:26:34.569946 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:26:34.576888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:26:34.580230 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:26:34.583333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:26:34.590283 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:26:34.593746 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:26:34.597168 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:26:34.603484 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:26:34.606922 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:26:34.610218 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:26:34.613492 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:26:34.620549 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:26:34.623843 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:26:34.626944 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:26:34.633847 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2888 12:26:34.637285 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2889 12:26:34.640616 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 12:26:34.644041 Total UI for P1: 0, mck2ui 16
2891 12:26:34.647369 best dqsien dly found for B0: ( 1, 3, 30)
2892 12:26:34.650294 Total UI for P1: 0, mck2ui 16
2893 12:26:34.653772 best dqsien dly found for B1: ( 1, 3, 30)
2894 12:26:34.657157 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2895 12:26:34.660644 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2896 12:26:34.660751
2897 12:26:34.667395 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2898 12:26:34.670549 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2899 12:26:34.670705 [Gating] SW calibration Done
2900 12:26:34.673601 ==
2901 12:26:34.677186 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 12:26:34.680321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 12:26:34.680432 ==
2904 12:26:34.680541 RX Vref Scan: 0
2905 12:26:34.680652
2906 12:26:34.683758 RX Vref 0 -> 0, step: 1
2907 12:26:34.683863
2908 12:26:34.687050 RX Delay -40 -> 252, step: 8
2909 12:26:34.690323 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2910 12:26:34.693744 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2911 12:26:34.697249 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2912 12:26:34.704216 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2913 12:26:34.707090 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2914 12:26:34.710493 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2915 12:26:34.713975 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2916 12:26:34.717392 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2917 12:26:34.724001 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2918 12:26:34.727434 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2919 12:26:34.730786 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2920 12:26:34.733923 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2921 12:26:34.737260 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2922 12:26:34.743966 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2923 12:26:34.747469 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2924 12:26:34.750279 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2925 12:26:34.750385 ==
2926 12:26:34.753716 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 12:26:34.757221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 12:26:34.757328 ==
2929 12:26:34.760634 DQS Delay:
2930 12:26:34.760761 DQS0 = 0, DQS1 = 0
2931 12:26:34.764094 DQM Delay:
2932 12:26:34.764195 DQM0 = 122, DQM1 = 112
2933 12:26:34.764316 DQ Delay:
2934 12:26:34.766940 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2935 12:26:34.773821 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2936 12:26:34.777114 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2937 12:26:34.780429 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2938 12:26:34.780538
2939 12:26:34.780645
2940 12:26:34.780747 ==
2941 12:26:34.783860 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 12:26:34.787058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 12:26:34.787165 ==
2944 12:26:34.787268
2945 12:26:34.787380
2946 12:26:34.790279 TX Vref Scan disable
2947 12:26:34.794155 == TX Byte 0 ==
2948 12:26:34.797444 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2949 12:26:34.800820 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2950 12:26:34.804291 == TX Byte 1 ==
2951 12:26:34.807126 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2952 12:26:34.810704 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2953 12:26:34.810809 ==
2954 12:26:34.814021 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 12:26:34.817407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 12:26:34.817520 ==
2957 12:26:34.830920 TX Vref=22, minBit 1, minWin=25, winSum=412
2958 12:26:34.834159 TX Vref=24, minBit 1, minWin=25, winSum=420
2959 12:26:34.837718 TX Vref=26, minBit 13, minWin=25, winSum=422
2960 12:26:34.840466 TX Vref=28, minBit 0, minWin=26, winSum=428
2961 12:26:34.843824 TX Vref=30, minBit 3, minWin=26, winSum=431
2962 12:26:34.850894 TX Vref=32, minBit 0, minWin=26, winSum=426
2963 12:26:34.853685 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 30
2964 12:26:34.853792
2965 12:26:34.857205 Final TX Range 1 Vref 30
2966 12:26:34.857310
2967 12:26:34.857420 ==
2968 12:26:34.860638 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 12:26:34.864030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 12:26:34.864150 ==
2971 12:26:34.864268
2972 12:26:34.867247
2973 12:26:34.867370 TX Vref Scan disable
2974 12:26:34.870806 == TX Byte 0 ==
2975 12:26:34.874206 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2976 12:26:34.877678 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2977 12:26:34.881046 == TX Byte 1 ==
2978 12:26:34.884328 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2979 12:26:34.887147 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2980 12:26:34.887256
2981 12:26:34.890609 [DATLAT]
2982 12:26:34.890704 Freq=1200, CH0 RK1
2983 12:26:34.890798
2984 12:26:34.893908 DATLAT Default: 0xd
2985 12:26:34.894015 0, 0xFFFF, sum = 0
2986 12:26:34.897157 1, 0xFFFF, sum = 0
2987 12:26:34.897267 2, 0xFFFF, sum = 0
2988 12:26:34.900859 3, 0xFFFF, sum = 0
2989 12:26:34.900978 4, 0xFFFF, sum = 0
2990 12:26:34.903982 5, 0xFFFF, sum = 0
2991 12:26:34.904064 6, 0xFFFF, sum = 0
2992 12:26:34.907295 7, 0xFFFF, sum = 0
2993 12:26:34.907419 8, 0xFFFF, sum = 0
2994 12:26:34.910774 9, 0xFFFF, sum = 0
2995 12:26:34.914194 10, 0xFFFF, sum = 0
2996 12:26:34.914304 11, 0xFFFF, sum = 0
2997 12:26:34.917645 12, 0x0, sum = 1
2998 12:26:34.917751 13, 0x0, sum = 2
2999 12:26:34.917854 14, 0x0, sum = 3
3000 12:26:34.921067 15, 0x0, sum = 4
3001 12:26:34.921157 best_step = 13
3002 12:26:34.921224
3003 12:26:34.921286 ==
3004 12:26:34.924498 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 12:26:34.930792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 12:26:34.930899 ==
3007 12:26:34.930995 RX Vref Scan: 0
3008 12:26:34.931089
3009 12:26:34.934095 RX Vref 0 -> 0, step: 1
3010 12:26:34.934199
3011 12:26:34.937924 RX Delay -13 -> 252, step: 4
3012 12:26:34.941029 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3013 12:26:34.944367 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3014 12:26:34.951125 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3015 12:26:34.954425 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3016 12:26:34.957814 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3017 12:26:34.961221 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3018 12:26:34.964700 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3019 12:26:34.968199 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3020 12:26:34.974279 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3021 12:26:34.977803 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3022 12:26:34.981251 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3023 12:26:34.984720 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3024 12:26:34.988069 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3025 12:26:34.994832 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3026 12:26:34.998228 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3027 12:26:35.001739 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3028 12:26:35.001847 ==
3029 12:26:35.005029 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 12:26:35.007781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 12:26:35.007888 ==
3032 12:26:35.011555 DQS Delay:
3033 12:26:35.011637 DQS0 = 0, DQS1 = 0
3034 12:26:35.014646 DQM Delay:
3035 12:26:35.014733 DQM0 = 121, DQM1 = 109
3036 12:26:35.017921 DQ Delay:
3037 12:26:35.021291 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3038 12:26:35.024861 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3039 12:26:35.028266 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3040 12:26:35.031079 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3041 12:26:35.031190
3042 12:26:35.031294
3043 12:26:35.038072 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3044 12:26:35.041309 CH0 RK1: MR19=403, MR18=DEE
3045 12:26:35.048247 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3046 12:26:35.051471 [RxdqsGatingPostProcess] freq 1200
3047 12:26:35.054773 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 12:26:35.058017 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 12:26:35.061309 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 12:26:35.064703 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 12:26:35.068361 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 12:26:35.071697 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 12:26:35.075056 best DQS1 dly(2T, 0.5T) = (0, 11)
3054 12:26:35.078543 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 12:26:35.081158 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3056 12:26:35.084700 Pre-setting of DQS Precalculation
3057 12:26:35.088074 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 12:26:35.088182 ==
3059 12:26:35.091308 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 12:26:35.097956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 12:26:35.098070 ==
3062 12:26:35.101362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 12:26:35.108239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3064 12:26:35.116989 [CA 0] Center 37 (7~68) winsize 62
3065 12:26:35.120454 [CA 1] Center 37 (7~68) winsize 62
3066 12:26:35.123679 [CA 2] Center 35 (5~65) winsize 61
3067 12:26:35.126910 [CA 3] Center 34 (4~64) winsize 61
3068 12:26:35.130182 [CA 4] Center 34 (4~64) winsize 61
3069 12:26:35.133572 [CA 5] Center 33 (3~63) winsize 61
3070 12:26:35.133659
3071 12:26:35.137003 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3072 12:26:35.137115
3073 12:26:35.140480 [CATrainingPosCal] consider 1 rank data
3074 12:26:35.143276 u2DelayCellTimex100 = 270/100 ps
3075 12:26:35.147500 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 12:26:35.150674 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 12:26:35.153984 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3078 12:26:35.157422 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3079 12:26:35.163942 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 12:26:35.167179 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3081 12:26:35.167295
3082 12:26:35.170323 CA PerBit enable=1, Macro0, CA PI delay=33
3083 12:26:35.170428
3084 12:26:35.173760 [CBTSetCACLKResult] CA Dly = 33
3085 12:26:35.173870 CS Dly: 8 (0~39)
3086 12:26:35.173992 ==
3087 12:26:35.177755 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 12:26:35.184314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 12:26:35.184425 ==
3090 12:26:35.187080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 12:26:35.193945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3092 12:26:35.202478 [CA 0] Center 37 (7~68) winsize 62
3093 12:26:35.205857 [CA 1] Center 37 (7~68) winsize 62
3094 12:26:35.209418 [CA 2] Center 35 (5~65) winsize 61
3095 12:26:35.212191 [CA 3] Center 34 (4~65) winsize 62
3096 12:26:35.215662 [CA 4] Center 34 (4~65) winsize 62
3097 12:26:35.219023 [CA 5] Center 34 (4~64) winsize 61
3098 12:26:35.219135
3099 12:26:35.222290 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3100 12:26:35.222402
3101 12:26:35.225858 [CATrainingPosCal] consider 2 rank data
3102 12:26:35.229259 u2DelayCellTimex100 = 270/100 ps
3103 12:26:35.232460 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3104 12:26:35.235850 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 12:26:35.242126 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3106 12:26:35.245795 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 12:26:35.249143 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 12:26:35.252462 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3109 12:26:35.252549
3110 12:26:35.255918 CA PerBit enable=1, Macro0, CA PI delay=33
3111 12:26:35.256004
3112 12:26:35.259270 [CBTSetCACLKResult] CA Dly = 33
3113 12:26:35.259387 CS Dly: 9 (0~41)
3114 12:26:35.259456
3115 12:26:35.262788 ----->DramcWriteLeveling(PI) begin...
3116 12:26:35.262875 ==
3117 12:26:35.266074 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 12:26:35.272609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 12:26:35.272704 ==
3120 12:26:35.276018 Write leveling (Byte 0): 25 => 25
3121 12:26:35.279252 Write leveling (Byte 1): 27 => 27
3122 12:26:35.279367 DramcWriteLeveling(PI) end<-----
3123 12:26:35.282479
3124 12:26:35.282564 ==
3125 12:26:35.286296 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 12:26:35.289432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 12:26:35.289545 ==
3128 12:26:35.292931 [Gating] SW mode calibration
3129 12:26:35.299068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 12:26:35.302521 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 12:26:35.309316 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3132 12:26:35.312720 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 12:26:35.316073 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 12:26:35.322974 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 12:26:35.326119 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 12:26:35.329457 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 12:26:35.335652 0 15 24 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 1)
3138 12:26:35.339554 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3139 12:26:35.342996 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 12:26:35.349257 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 12:26:35.352713 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 12:26:35.356025 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 12:26:35.359482 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 12:26:35.366241 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3145 12:26:35.369821 1 0 24 | B1->B0 | 3434 4444 | 1 1 | (0 0) (0 0)
3146 12:26:35.373101 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 12:26:35.379994 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 12:26:35.383401 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 12:26:35.386674 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 12:26:35.393051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 12:26:35.396173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 12:26:35.399879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 12:26:35.406741 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3154 12:26:35.410029 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 12:26:35.412915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:26:35.416320 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:26:35.423115 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:26:35.426451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:26:35.429780 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:26:35.436550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:26:35.439963 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:26:35.443287 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:26:35.450036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:26:35.453695 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:26:35.457078 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:26:35.463299 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:26:35.466652 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:26:35.470099 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:26:35.477076 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3170 12:26:35.480292 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 12:26:35.483577 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 12:26:35.486478 Total UI for P1: 0, mck2ui 16
3173 12:26:35.489870 best dqsien dly found for B0: ( 1, 3, 26)
3174 12:26:35.493106 Total UI for P1: 0, mck2ui 16
3175 12:26:35.496509 best dqsien dly found for B1: ( 1, 3, 26)
3176 12:26:35.499833 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3177 12:26:35.503507 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3178 12:26:35.503618
3179 12:26:35.506565 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3180 12:26:35.513106 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3181 12:26:35.513222 [Gating] SW calibration Done
3182 12:26:35.513329 ==
3183 12:26:35.516293 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 12:26:35.523208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 12:26:35.523319 ==
3186 12:26:35.523475 RX Vref Scan: 0
3187 12:26:35.523579
3188 12:26:35.526536 RX Vref 0 -> 0, step: 1
3189 12:26:35.526617
3190 12:26:35.529973 RX Delay -40 -> 252, step: 8
3191 12:26:35.533357 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 12:26:35.536695 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 12:26:35.540090 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3194 12:26:35.546476 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3195 12:26:35.549791 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3196 12:26:35.553097 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3197 12:26:35.556570 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3198 12:26:35.559942 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3199 12:26:35.563463 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3200 12:26:35.570221 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3201 12:26:35.573575 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 12:26:35.576363 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3203 12:26:35.579881 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 12:26:35.583473 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3205 12:26:35.590066 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3206 12:26:35.593477 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3207 12:26:35.593555 ==
3208 12:26:35.596721 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 12:26:35.600078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 12:26:35.600156 ==
3211 12:26:35.603655 DQS Delay:
3212 12:26:35.603735 DQS0 = 0, DQS1 = 0
3213 12:26:35.603799 DQM Delay:
3214 12:26:35.606381 DQM0 = 120, DQM1 = 116
3215 12:26:35.606499 DQ Delay:
3216 12:26:35.609771 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3217 12:26:35.613705 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3218 12:26:35.620066 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3219 12:26:35.623371 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3220 12:26:35.623496
3221 12:26:35.623593
3222 12:26:35.623698 ==
3223 12:26:35.626788 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 12:26:35.630131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 12:26:35.630260 ==
3226 12:26:35.630368
3227 12:26:35.630474
3228 12:26:35.633503 TX Vref Scan disable
3229 12:26:35.633626 == TX Byte 0 ==
3230 12:26:35.640275 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3231 12:26:35.643590 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3232 12:26:35.643674 == TX Byte 1 ==
3233 12:26:35.649894 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3234 12:26:35.653329 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3235 12:26:35.653412 ==
3236 12:26:35.656556 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 12:26:35.660329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 12:26:35.660442 ==
3239 12:26:35.672721 TX Vref=22, minBit 9, minWin=24, winSum=410
3240 12:26:35.676044 TX Vref=24, minBit 1, minWin=25, winSum=418
3241 12:26:35.679518 TX Vref=26, minBit 9, minWin=25, winSum=424
3242 12:26:35.683137 TX Vref=28, minBit 9, minWin=25, winSum=424
3243 12:26:35.685896 TX Vref=30, minBit 9, minWin=26, winSum=433
3244 12:26:35.689918 TX Vref=32, minBit 2, minWin=26, winSum=428
3245 12:26:35.696067 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3246 12:26:35.696165
3247 12:26:35.699446 Final TX Range 1 Vref 30
3248 12:26:35.699536
3249 12:26:35.699606 ==
3250 12:26:35.702795 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 12:26:35.706192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 12:26:35.706286 ==
3253 12:26:35.706355
3254 12:26:35.706419
3255 12:26:35.709641 TX Vref Scan disable
3256 12:26:35.713064 == TX Byte 0 ==
3257 12:26:35.716268 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3258 12:26:35.719730 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3259 12:26:35.723004 == TX Byte 1 ==
3260 12:26:35.726302 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3261 12:26:35.729575 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3262 12:26:35.729670
3263 12:26:35.732798 [DATLAT]
3264 12:26:35.732891 Freq=1200, CH1 RK0
3265 12:26:35.732963
3266 12:26:35.736591 DATLAT Default: 0xd
3267 12:26:35.736711 0, 0xFFFF, sum = 0
3268 12:26:35.739470 1, 0xFFFF, sum = 0
3269 12:26:35.739556 2, 0xFFFF, sum = 0
3270 12:26:35.742906 3, 0xFFFF, sum = 0
3271 12:26:35.743016 4, 0xFFFF, sum = 0
3272 12:26:35.746257 5, 0xFFFF, sum = 0
3273 12:26:35.746375 6, 0xFFFF, sum = 0
3274 12:26:35.749746 7, 0xFFFF, sum = 0
3275 12:26:35.749861 8, 0xFFFF, sum = 0
3276 12:26:35.753106 9, 0xFFFF, sum = 0
3277 12:26:35.753219 10, 0xFFFF, sum = 0
3278 12:26:35.756671 11, 0xFFFF, sum = 0
3279 12:26:35.756778 12, 0x0, sum = 1
3280 12:26:35.760055 13, 0x0, sum = 2
3281 12:26:35.760190 14, 0x0, sum = 3
3282 12:26:35.763421 15, 0x0, sum = 4
3283 12:26:35.763537 best_step = 13
3284 12:26:35.763637
3285 12:26:35.763734 ==
3286 12:26:35.766648 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 12:26:35.773320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 12:26:35.773449 ==
3289 12:26:35.773551 RX Vref Scan: 1
3290 12:26:35.773647
3291 12:26:35.776818 Set Vref Range= 32 -> 127
3292 12:26:35.776933
3293 12:26:35.780120 RX Vref 32 -> 127, step: 1
3294 12:26:35.780230
3295 12:26:35.780325 RX Delay -5 -> 252, step: 4
3296 12:26:35.780422
3297 12:26:35.783646 Set Vref, RX VrefLevel [Byte0]: 32
3298 12:26:35.786470 [Byte1]: 32
3299 12:26:35.790736
3300 12:26:35.790850 Set Vref, RX VrefLevel [Byte0]: 33
3301 12:26:35.794072 [Byte1]: 33
3302 12:26:35.798788
3303 12:26:35.798901 Set Vref, RX VrefLevel [Byte0]: 34
3304 12:26:35.802004 [Byte1]: 34
3305 12:26:35.806678
3306 12:26:35.806800 Set Vref, RX VrefLevel [Byte0]: 35
3307 12:26:35.810107 [Byte1]: 35
3308 12:26:35.814202
3309 12:26:35.814314 Set Vref, RX VrefLevel [Byte0]: 36
3310 12:26:35.817510 [Byte1]: 36
3311 12:26:35.822155
3312 12:26:35.822269 Set Vref, RX VrefLevel [Byte0]: 37
3313 12:26:35.825688 [Byte1]: 37
3314 12:26:35.829806
3315 12:26:35.829921 Set Vref, RX VrefLevel [Byte0]: 38
3316 12:26:35.833121 [Byte1]: 38
3317 12:26:35.837589
3318 12:26:35.837703 Set Vref, RX VrefLevel [Byte0]: 39
3319 12:26:35.841480 [Byte1]: 39
3320 12:26:35.845505
3321 12:26:35.845625 Set Vref, RX VrefLevel [Byte0]: 40
3322 12:26:35.848898 [Byte1]: 40
3323 12:26:35.853723
3324 12:26:35.853840 Set Vref, RX VrefLevel [Byte0]: 41
3325 12:26:35.857063 [Byte1]: 41
3326 12:26:35.861211
3327 12:26:35.861330 Set Vref, RX VrefLevel [Byte0]: 42
3328 12:26:35.864580 [Byte1]: 42
3329 12:26:35.869433
3330 12:26:35.869560 Set Vref, RX VrefLevel [Byte0]: 43
3331 12:26:35.872805 [Byte1]: 43
3332 12:26:35.877305
3333 12:26:35.877422 Set Vref, RX VrefLevel [Byte0]: 44
3334 12:26:35.880700 [Byte1]: 44
3335 12:26:35.884702
3336 12:26:35.884811 Set Vref, RX VrefLevel [Byte0]: 45
3337 12:26:35.888158 [Byte1]: 45
3338 12:26:35.893104
3339 12:26:35.893224 Set Vref, RX VrefLevel [Byte0]: 46
3340 12:26:35.895919 [Byte1]: 46
3341 12:26:35.900706
3342 12:26:35.900818 Set Vref, RX VrefLevel [Byte0]: 47
3343 12:26:35.904148 [Byte1]: 47
3344 12:26:35.908694
3345 12:26:35.908808 Set Vref, RX VrefLevel [Byte0]: 48
3346 12:26:35.911906 [Byte1]: 48
3347 12:26:35.916554
3348 12:26:35.916671 Set Vref, RX VrefLevel [Byte0]: 49
3349 12:26:35.920080 [Byte1]: 49
3350 12:26:35.924211
3351 12:26:35.924321 Set Vref, RX VrefLevel [Byte0]: 50
3352 12:26:35.927445 [Byte1]: 50
3353 12:26:35.932226
3354 12:26:35.932336 Set Vref, RX VrefLevel [Byte0]: 51
3355 12:26:35.935696 [Byte1]: 51
3356 12:26:35.939790
3357 12:26:35.939899 Set Vref, RX VrefLevel [Byte0]: 52
3358 12:26:35.942994 [Byte1]: 52
3359 12:26:35.947980
3360 12:26:35.948094 Set Vref, RX VrefLevel [Byte0]: 53
3361 12:26:35.951282 [Byte1]: 53
3362 12:26:35.955780
3363 12:26:35.955892 Set Vref, RX VrefLevel [Byte0]: 54
3364 12:26:35.959117 [Byte1]: 54
3365 12:26:35.963288
3366 12:26:35.963404 Set Vref, RX VrefLevel [Byte0]: 55
3367 12:26:35.966673 [Byte1]: 55
3368 12:26:35.971450
3369 12:26:35.974271 Set Vref, RX VrefLevel [Byte0]: 56
3370 12:26:35.974380 [Byte1]: 56
3371 12:26:35.979054
3372 12:26:35.979168 Set Vref, RX VrefLevel [Byte0]: 57
3373 12:26:35.982210 [Byte1]: 57
3374 12:26:35.986882
3375 12:26:35.986999 Set Vref, RX VrefLevel [Byte0]: 58
3376 12:26:35.990275 [Byte1]: 58
3377 12:26:35.995030
3378 12:26:35.995150 Set Vref, RX VrefLevel [Byte0]: 59
3379 12:26:35.998403 [Byte1]: 59
3380 12:26:36.002535
3381 12:26:36.002642 Set Vref, RX VrefLevel [Byte0]: 60
3382 12:26:36.006115 [Byte1]: 60
3383 12:26:36.010924
3384 12:26:36.011025 Set Vref, RX VrefLevel [Byte0]: 61
3385 12:26:36.013671 [Byte1]: 61
3386 12:26:36.018165
3387 12:26:36.018296 Set Vref, RX VrefLevel [Byte0]: 62
3388 12:26:36.021443 [Byte1]: 62
3389 12:26:36.026107
3390 12:26:36.026235 Set Vref, RX VrefLevel [Byte0]: 63
3391 12:26:36.029399 [Byte1]: 63
3392 12:26:36.033972
3393 12:26:36.034094 Set Vref, RX VrefLevel [Byte0]: 64
3394 12:26:36.037441 [Byte1]: 64
3395 12:26:36.041680
3396 12:26:36.041798 Set Vref, RX VrefLevel [Byte0]: 65
3397 12:26:36.045188 [Byte1]: 65
3398 12:26:36.049840
3399 12:26:36.049927 Set Vref, RX VrefLevel [Byte0]: 66
3400 12:26:36.053079 [Byte1]: 66
3401 12:26:36.057528
3402 12:26:36.057664 Set Vref, RX VrefLevel [Byte0]: 67
3403 12:26:36.060832 [Byte1]: 67
3404 12:26:36.065317
3405 12:26:36.065442 Set Vref, RX VrefLevel [Byte0]: 68
3406 12:26:36.068754 [Byte1]: 68
3407 12:26:36.073476
3408 12:26:36.073594 Set Vref, RX VrefLevel [Byte0]: 69
3409 12:26:36.076952 [Byte1]: 69
3410 12:26:36.080996
3411 12:26:36.081109 Set Vref, RX VrefLevel [Byte0]: 70
3412 12:26:36.084424 [Byte1]: 70
3413 12:26:36.089114
3414 12:26:36.089222 Final RX Vref Byte 0 = 51 to rank0
3415 12:26:36.092373 Final RX Vref Byte 1 = 49 to rank0
3416 12:26:36.095747 Final RX Vref Byte 0 = 51 to rank1
3417 12:26:36.099182 Final RX Vref Byte 1 = 49 to rank1==
3418 12:26:36.102550 Dram Type= 6, Freq= 0, CH_1, rank 0
3419 12:26:36.108794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 12:26:36.108886 ==
3421 12:26:36.108957 DQS Delay:
3422 12:26:36.109021 DQS0 = 0, DQS1 = 0
3423 12:26:36.112357 DQM Delay:
3424 12:26:36.112431 DQM0 = 119, DQM1 = 116
3425 12:26:36.115856 DQ Delay:
3426 12:26:36.118771 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =114
3427 12:26:36.122559 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3428 12:26:36.125695 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3429 12:26:36.128952 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3430 12:26:36.129068
3431 12:26:36.129181
3432 12:26:36.135547 [DQSOSCAuto] RK0, (LSB)MR18= 0x12, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3433 12:26:36.138969 CH1 RK0: MR19=404, MR18=12
3434 12:26:36.146011 CH1_RK0: MR19=0x404, MR18=0x12, DQSOSC=403, MR23=63, INC=40, DEC=26
3435 12:26:36.146102
3436 12:26:36.148811 ----->DramcWriteLeveling(PI) begin...
3437 12:26:36.148936 ==
3438 12:26:36.152220 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 12:26:36.155448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 12:26:36.155542 ==
3441 12:26:36.158812 Write leveling (Byte 0): 26 => 26
3442 12:26:36.162833 Write leveling (Byte 1): 28 => 28
3443 12:26:36.165909 DramcWriteLeveling(PI) end<-----
3444 12:26:36.166015
3445 12:26:36.166117 ==
3446 12:26:36.169200 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 12:26:36.172368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 12:26:36.175743 ==
3449 12:26:36.175864 [Gating] SW mode calibration
3450 12:26:36.182491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3451 12:26:36.188748 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3452 12:26:36.192192 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 12:26:36.198862 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 12:26:36.202214 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 12:26:36.205491 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 12:26:36.212204 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 12:26:36.215503 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3458 12:26:36.218938 0 15 24 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
3459 12:26:36.225845 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3460 12:26:36.229332 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 12:26:36.231965 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 12:26:36.239034 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 12:26:36.242271 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 12:26:36.245544 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 12:26:36.252470 1 0 20 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
3466 12:26:36.255250 1 0 24 | B1->B0 | 3f3f 2525 | 0 0 | (1 1) (0 0)
3467 12:26:36.258595 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 12:26:36.261977 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 12:26:36.268949 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 12:26:36.272091 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 12:26:36.275319 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 12:26:36.281939 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:26:36.285230 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3474 12:26:36.288597 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3475 12:26:36.295401 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3476 12:26:36.298311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:26:36.301697 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:26:36.308835 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:26:36.312052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:26:36.315420 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:26:36.321826 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:26:36.325250 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:26:36.328611 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:26:36.334826 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:26:36.338276 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:26:36.341440 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:26:36.348549 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:26:36.351758 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:26:36.355192 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3490 12:26:36.361509 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3491 12:26:36.364838 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3492 12:26:36.368225 Total UI for P1: 0, mck2ui 16
3493 12:26:36.371790 best dqsien dly found for B1: ( 1, 3, 22)
3494 12:26:36.375046 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 12:26:36.378233 Total UI for P1: 0, mck2ui 16
3496 12:26:36.381566 best dqsien dly found for B0: ( 1, 3, 28)
3497 12:26:36.384734 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3498 12:26:36.388103 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3499 12:26:36.388198
3500 12:26:36.394737 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3501 12:26:36.398022 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3502 12:26:36.401650 [Gating] SW calibration Done
3503 12:26:36.401735 ==
3504 12:26:36.404311 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 12:26:36.407711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 12:26:36.407827 ==
3507 12:26:36.407927 RX Vref Scan: 0
3508 12:26:36.408024
3509 12:26:36.411112 RX Vref 0 -> 0, step: 1
3510 12:26:36.411223
3511 12:26:36.414470 RX Delay -40 -> 252, step: 8
3512 12:26:36.417563 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3513 12:26:36.421452 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3514 12:26:36.427780 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3515 12:26:36.431106 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3516 12:26:36.434516 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3517 12:26:36.438017 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3518 12:26:36.440810 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3519 12:26:36.447593 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3520 12:26:36.450929 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3521 12:26:36.454165 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3522 12:26:36.457313 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3523 12:26:36.460817 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3524 12:26:36.467689 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3525 12:26:36.471028 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3526 12:26:36.474451 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3527 12:26:36.477844 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3528 12:26:36.477976 ==
3529 12:26:36.481174 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 12:26:36.487547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 12:26:36.487653 ==
3532 12:26:36.487742 DQS Delay:
3533 12:26:36.487809 DQS0 = 0, DQS1 = 0
3534 12:26:36.490740 DQM Delay:
3535 12:26:36.490848 DQM0 = 120, DQM1 = 118
3536 12:26:36.494110 DQ Delay:
3537 12:26:36.497425 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =115
3538 12:26:36.500871 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3539 12:26:36.504323 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3540 12:26:36.507190 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3541 12:26:36.507310
3542 12:26:36.507403
3543 12:26:36.507491 ==
3544 12:26:36.510710 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 12:26:36.514162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 12:26:36.517526 ==
3547 12:26:36.517642
3548 12:26:36.517747
3549 12:26:36.517814 TX Vref Scan disable
3550 12:26:36.520901 == TX Byte 0 ==
3551 12:26:36.524241 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3552 12:26:36.527425 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3553 12:26:36.530711 == TX Byte 1 ==
3554 12:26:36.534009 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 12:26:36.537475 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 12:26:36.537603 ==
3557 12:26:36.541016 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 12:26:36.547117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 12:26:36.547251 ==
3560 12:26:36.557908 TX Vref=22, minBit 10, minWin=25, winSum=418
3561 12:26:36.560998 TX Vref=24, minBit 0, minWin=26, winSum=424
3562 12:26:36.564782 TX Vref=26, minBit 0, minWin=26, winSum=430
3563 12:26:36.567669 TX Vref=28, minBit 8, minWin=26, winSum=431
3564 12:26:36.571223 TX Vref=30, minBit 9, minWin=26, winSum=434
3565 12:26:36.578099 TX Vref=32, minBit 9, minWin=26, winSum=434
3566 12:26:36.580849 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3567 12:26:36.581022
3568 12:26:36.584354 Final TX Range 1 Vref 30
3569 12:26:36.584479
3570 12:26:36.584576 ==
3571 12:26:36.587781 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 12:26:36.590973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 12:26:36.591103 ==
3574 12:26:36.594235
3575 12:26:36.594347
3576 12:26:36.594417 TX Vref Scan disable
3577 12:26:36.597680 == TX Byte 0 ==
3578 12:26:36.600923 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 12:26:36.604290 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 12:26:36.607773 == TX Byte 1 ==
3581 12:26:36.611207 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3582 12:26:36.614667 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3583 12:26:36.617453
3584 12:26:36.617566 [DATLAT]
3585 12:26:36.617666 Freq=1200, CH1 RK1
3586 12:26:36.617762
3587 12:26:36.621327 DATLAT Default: 0xd
3588 12:26:36.621435 0, 0xFFFF, sum = 0
3589 12:26:36.624100 1, 0xFFFF, sum = 0
3590 12:26:36.624267 2, 0xFFFF, sum = 0
3591 12:26:36.627504 3, 0xFFFF, sum = 0
3592 12:26:36.630822 4, 0xFFFF, sum = 0
3593 12:26:36.630935 5, 0xFFFF, sum = 0
3594 12:26:36.634212 6, 0xFFFF, sum = 0
3595 12:26:36.634323 7, 0xFFFF, sum = 0
3596 12:26:36.637420 8, 0xFFFF, sum = 0
3597 12:26:36.637536 9, 0xFFFF, sum = 0
3598 12:26:36.640688 10, 0xFFFF, sum = 0
3599 12:26:36.640796 11, 0xFFFF, sum = 0
3600 12:26:36.644693 12, 0x0, sum = 1
3601 12:26:36.644835 13, 0x0, sum = 2
3602 12:26:36.647455 14, 0x0, sum = 3
3603 12:26:36.647604 15, 0x0, sum = 4
3604 12:26:36.647706 best_step = 13
3605 12:26:36.650872
3606 12:26:36.651009 ==
3607 12:26:36.654397 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 12:26:36.657776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 12:26:36.657897 ==
3610 12:26:36.657997 RX Vref Scan: 0
3611 12:26:36.658106
3612 12:26:36.660950 RX Vref 0 -> 0, step: 1
3613 12:26:36.661059
3614 12:26:36.664369 RX Delay -5 -> 252, step: 4
3615 12:26:36.667488 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3616 12:26:36.674183 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3617 12:26:36.677579 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3618 12:26:36.680943 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3619 12:26:36.684423 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3620 12:26:36.687788 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3621 12:26:36.694049 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3622 12:26:36.697405 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3623 12:26:36.700485 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3624 12:26:36.704012 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3625 12:26:36.707499 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3626 12:26:36.714204 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3627 12:26:36.716970 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3628 12:26:36.720417 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3629 12:26:36.723881 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3630 12:26:36.727308 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3631 12:26:36.730712 ==
3632 12:26:36.734143 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 12:26:36.737471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 12:26:36.737597 ==
3635 12:26:36.737698 DQS Delay:
3636 12:26:36.740297 DQS0 = 0, DQS1 = 0
3637 12:26:36.740401 DQM Delay:
3638 12:26:36.743652 DQM0 = 120, DQM1 = 116
3639 12:26:36.743745 DQ Delay:
3640 12:26:36.747011 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3641 12:26:36.750223 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =118
3642 12:26:36.754146 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3643 12:26:36.756911 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3644 12:26:36.757026
3645 12:26:36.757125
3646 12:26:36.767026 [DQSOSCAuto] RK1, (LSB)MR18= 0x15f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 401 ps
3647 12:26:36.770175 CH1 RK1: MR19=403, MR18=15F2
3648 12:26:36.774055 CH1_RK1: MR19=0x403, MR18=0x15F2, DQSOSC=401, MR23=63, INC=40, DEC=27
3649 12:26:36.777227 [RxdqsGatingPostProcess] freq 1200
3650 12:26:36.784050 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3651 12:26:36.787460 best DQS0 dly(2T, 0.5T) = (0, 11)
3652 12:26:36.790226 best DQS1 dly(2T, 0.5T) = (0, 11)
3653 12:26:36.793673 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3654 12:26:36.796950 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3655 12:26:36.800333 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 12:26:36.803772 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 12:26:36.807071 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 12:26:36.810223 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 12:26:36.810344 Pre-setting of DQS Precalculation
3660 12:26:36.816703 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3661 12:26:36.823690 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3662 12:26:36.830465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3663 12:26:36.830573
3664 12:26:36.830648
3665 12:26:36.833970 [Calibration Summary] 2400 Mbps
3666 12:26:36.836717 CH 0, Rank 0
3667 12:26:36.836796 SW Impedance : PASS
3668 12:26:36.840145 DUTY Scan : NO K
3669 12:26:36.843351 ZQ Calibration : PASS
3670 12:26:36.843446 Jitter Meter : NO K
3671 12:26:36.846711 CBT Training : PASS
3672 12:26:36.850128 Write leveling : PASS
3673 12:26:36.850244 RX DQS gating : PASS
3674 12:26:36.853473 RX DQ/DQS(RDDQC) : PASS
3675 12:26:36.853556 TX DQ/DQS : PASS
3676 12:26:36.856774 RX DATLAT : PASS
3677 12:26:36.860133 RX DQ/DQS(Engine): PASS
3678 12:26:36.860219 TX OE : NO K
3679 12:26:36.863564 All Pass.
3680 12:26:36.863659
3681 12:26:36.863731 CH 0, Rank 1
3682 12:26:36.867059 SW Impedance : PASS
3683 12:26:36.867162 DUTY Scan : NO K
3684 12:26:36.870302 ZQ Calibration : PASS
3685 12:26:36.873654 Jitter Meter : NO K
3686 12:26:36.873757 CBT Training : PASS
3687 12:26:36.876754 Write leveling : PASS
3688 12:26:36.880096 RX DQS gating : PASS
3689 12:26:36.880192 RX DQ/DQS(RDDQC) : PASS
3690 12:26:36.883223 TX DQ/DQS : PASS
3691 12:26:36.886547 RX DATLAT : PASS
3692 12:26:36.886661 RX DQ/DQS(Engine): PASS
3693 12:26:36.889840 TX OE : NO K
3694 12:26:36.889959 All Pass.
3695 12:26:36.890066
3696 12:26:36.893291 CH 1, Rank 0
3697 12:26:36.893405 SW Impedance : PASS
3698 12:26:36.896782 DUTY Scan : NO K
3699 12:26:36.900152 ZQ Calibration : PASS
3700 12:26:36.900258 Jitter Meter : NO K
3701 12:26:36.903572 CBT Training : PASS
3702 12:26:36.906354 Write leveling : PASS
3703 12:26:36.906443 RX DQS gating : PASS
3704 12:26:36.909788 RX DQ/DQS(RDDQC) : PASS
3705 12:26:36.909894 TX DQ/DQS : PASS
3706 12:26:36.913122 RX DATLAT : PASS
3707 12:26:36.916480 RX DQ/DQS(Engine): PASS
3708 12:26:36.916578 TX OE : NO K
3709 12:26:36.919757 All Pass.
3710 12:26:36.919846
3711 12:26:36.919914 CH 1, Rank 1
3712 12:26:36.923090 SW Impedance : PASS
3713 12:26:36.923200 DUTY Scan : NO K
3714 12:26:36.926491 ZQ Calibration : PASS
3715 12:26:36.929736 Jitter Meter : NO K
3716 12:26:36.929822 CBT Training : PASS
3717 12:26:36.933241 Write leveling : PASS
3718 12:26:36.936661 RX DQS gating : PASS
3719 12:26:36.936759 RX DQ/DQS(RDDQC) : PASS
3720 12:26:36.940140 TX DQ/DQS : PASS
3721 12:26:36.942916 RX DATLAT : PASS
3722 12:26:36.942992 RX DQ/DQS(Engine): PASS
3723 12:26:36.946138 TX OE : NO K
3724 12:26:36.946226 All Pass.
3725 12:26:36.946292
3726 12:26:36.950154 DramC Write-DBI off
3727 12:26:36.952868 PER_BANK_REFRESH: Hybrid Mode
3728 12:26:36.952963 TX_TRACKING: ON
3729 12:26:36.963081 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3730 12:26:36.966552 [FAST_K] Save calibration result to emmc
3731 12:26:36.969956 dramc_set_vcore_voltage set vcore to 650000
3732 12:26:36.973404 Read voltage for 600, 5
3733 12:26:36.973527 Vio18 = 0
3734 12:26:36.973632 Vcore = 650000
3735 12:26:36.976162 Vdram = 0
3736 12:26:36.976259 Vddq = 0
3737 12:26:36.976353 Vmddr = 0
3738 12:26:36.982815 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3739 12:26:36.986113 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3740 12:26:36.990041 MEM_TYPE=3, freq_sel=19
3741 12:26:36.993195 sv_algorithm_assistance_LP4_1600
3742 12:26:36.996423 ============ PULL DRAM RESETB DOWN ============
3743 12:26:36.999925 ========== PULL DRAM RESETB DOWN end =========
3744 12:26:37.006216 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3745 12:26:37.009706 ===================================
3746 12:26:37.009806 LPDDR4 DRAM CONFIGURATION
3747 12:26:37.013098 ===================================
3748 12:26:37.016640 EX_ROW_EN[0] = 0x0
3749 12:26:37.019506 EX_ROW_EN[1] = 0x0
3750 12:26:37.019589 LP4Y_EN = 0x0
3751 12:26:37.022792 WORK_FSP = 0x0
3752 12:26:37.022890 WL = 0x2
3753 12:26:37.026568 RL = 0x2
3754 12:26:37.026661 BL = 0x2
3755 12:26:37.029794 RPST = 0x0
3756 12:26:37.029889 RD_PRE = 0x0
3757 12:26:37.033061 WR_PRE = 0x1
3758 12:26:37.033151 WR_PST = 0x0
3759 12:26:37.036441 DBI_WR = 0x0
3760 12:26:37.036521 DBI_RD = 0x0
3761 12:26:37.039850 OTF = 0x1
3762 12:26:37.043343 ===================================
3763 12:26:37.046162 ===================================
3764 12:26:37.046275 ANA top config
3765 12:26:37.049512 ===================================
3766 12:26:37.052762 DLL_ASYNC_EN = 0
3767 12:26:37.056092 ALL_SLAVE_EN = 1
3768 12:26:37.056182 NEW_RANK_MODE = 1
3769 12:26:37.059644 DLL_IDLE_MODE = 1
3770 12:26:37.063093 LP45_APHY_COMB_EN = 1
3771 12:26:37.065891 TX_ODT_DIS = 1
3772 12:26:37.069810 NEW_8X_MODE = 1
3773 12:26:37.072694 ===================================
3774 12:26:37.075968 ===================================
3775 12:26:37.076118 data_rate = 1200
3776 12:26:37.079485 CKR = 1
3777 12:26:37.082973 DQ_P2S_RATIO = 8
3778 12:26:37.086455 ===================================
3779 12:26:37.089803 CA_P2S_RATIO = 8
3780 12:26:37.093105 DQ_CA_OPEN = 0
3781 12:26:37.096311 DQ_SEMI_OPEN = 0
3782 12:26:37.096478 CA_SEMI_OPEN = 0
3783 12:26:37.099522 CA_FULL_RATE = 0
3784 12:26:37.102819 DQ_CKDIV4_EN = 1
3785 12:26:37.106111 CA_CKDIV4_EN = 1
3786 12:26:37.109662 CA_PREDIV_EN = 0
3787 12:26:37.113019 PH8_DLY = 0
3788 12:26:37.113145 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3789 12:26:37.115888 DQ_AAMCK_DIV = 4
3790 12:26:37.119382 CA_AAMCK_DIV = 4
3791 12:26:37.122925 CA_ADMCK_DIV = 4
3792 12:26:37.126112 DQ_TRACK_CA_EN = 0
3793 12:26:37.129365 CA_PICK = 600
3794 12:26:37.132770 CA_MCKIO = 600
3795 12:26:37.132879 MCKIO_SEMI = 0
3796 12:26:37.136061 PLL_FREQ = 2288
3797 12:26:37.139193 DQ_UI_PI_RATIO = 32
3798 12:26:37.142692 CA_UI_PI_RATIO = 0
3799 12:26:37.145970 ===================================
3800 12:26:37.149405 ===================================
3801 12:26:37.152861 memory_type:LPDDR4
3802 12:26:37.152948 GP_NUM : 10
3803 12:26:37.156152 SRAM_EN : 1
3804 12:26:37.156242 MD32_EN : 0
3805 12:26:37.159439 ===================================
3806 12:26:37.162865 [ANA_INIT] >>>>>>>>>>>>>>
3807 12:26:37.165687 <<<<<< [CONFIGURE PHASE]: ANA_TX
3808 12:26:37.169161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3809 12:26:37.172473 ===================================
3810 12:26:37.175699 data_rate = 1200,PCW = 0X5800
3811 12:26:37.179457 ===================================
3812 12:26:37.182244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3813 12:26:37.189185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 12:26:37.192688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 12:26:37.198993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3816 12:26:37.202327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3817 12:26:37.205515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3818 12:26:37.205630 [ANA_INIT] flow start
3819 12:26:37.209335 [ANA_INIT] PLL >>>>>>>>
3820 12:26:37.212534 [ANA_INIT] PLL <<<<<<<<
3821 12:26:37.212644 [ANA_INIT] MIDPI >>>>>>>>
3822 12:26:37.215776 [ANA_INIT] MIDPI <<<<<<<<
3823 12:26:37.219275 [ANA_INIT] DLL >>>>>>>>
3824 12:26:37.219378 [ANA_INIT] flow end
3825 12:26:37.225565 ============ LP4 DIFF to SE enter ============
3826 12:26:37.229047 ============ LP4 DIFF to SE exit ============
3827 12:26:37.232366 [ANA_INIT] <<<<<<<<<<<<<
3828 12:26:37.235664 [Flow] Enable top DCM control >>>>>
3829 12:26:37.239051 [Flow] Enable top DCM control <<<<<
3830 12:26:37.239159 Enable DLL master slave shuffle
3831 12:26:37.245565 ==============================================================
3832 12:26:37.248942 Gating Mode config
3833 12:26:37.252286 ==============================================================
3834 12:26:37.255796 Config description:
3835 12:26:37.265425 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3836 12:26:37.272249 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3837 12:26:37.275085 SELPH_MODE 0: By rank 1: By Phase
3838 12:26:37.281695 ==============================================================
3839 12:26:37.284898 GAT_TRACK_EN = 1
3840 12:26:37.288821 RX_GATING_MODE = 2
3841 12:26:37.292216 RX_GATING_TRACK_MODE = 2
3842 12:26:37.295091 SELPH_MODE = 1
3843 12:26:37.295211 PICG_EARLY_EN = 1
3844 12:26:37.298557 VALID_LAT_VALUE = 1
3845 12:26:37.305157 ==============================================================
3846 12:26:37.308249 Enter into Gating configuration >>>>
3847 12:26:37.312102 Exit from Gating configuration <<<<
3848 12:26:37.315267 Enter into DVFS_PRE_config >>>>>
3849 12:26:37.324918 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3850 12:26:37.328463 Exit from DVFS_PRE_config <<<<<
3851 12:26:37.331818 Enter into PICG configuration >>>>
3852 12:26:37.335218 Exit from PICG configuration <<<<
3853 12:26:37.338615 [RX_INPUT] configuration >>>>>
3854 12:26:37.341763 [RX_INPUT] configuration <<<<<
3855 12:26:37.344975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3856 12:26:37.351952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3857 12:26:37.358867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 12:26:37.364972 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 12:26:37.371776 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 12:26:37.375208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 12:26:37.382033 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3862 12:26:37.384856 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3863 12:26:37.388163 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3864 12:26:37.391496 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3865 12:26:37.398407 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3866 12:26:37.401272 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 12:26:37.404733 ===================================
3868 12:26:37.408086 LPDDR4 DRAM CONFIGURATION
3869 12:26:37.411432 ===================================
3870 12:26:37.411524 EX_ROW_EN[0] = 0x0
3871 12:26:37.414758 EX_ROW_EN[1] = 0x0
3872 12:26:37.414838 LP4Y_EN = 0x0
3873 12:26:37.417964 WORK_FSP = 0x0
3874 12:26:37.418050 WL = 0x2
3875 12:26:37.421292 RL = 0x2
3876 12:26:37.421373 BL = 0x2
3877 12:26:37.424661 RPST = 0x0
3878 12:26:37.424738 RD_PRE = 0x0
3879 12:26:37.427871 WR_PRE = 0x1
3880 12:26:37.427990 WR_PST = 0x0
3881 12:26:37.431013 DBI_WR = 0x0
3882 12:26:37.434344 DBI_RD = 0x0
3883 12:26:37.434460 OTF = 0x1
3884 12:26:37.437737 ===================================
3885 12:26:37.441338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3886 12:26:37.444730 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3887 12:26:37.451240 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 12:26:37.454467 ===================================
3889 12:26:37.457702 LPDDR4 DRAM CONFIGURATION
3890 12:26:37.461524 ===================================
3891 12:26:37.461637 EX_ROW_EN[0] = 0x10
3892 12:26:37.464650 EX_ROW_EN[1] = 0x0
3893 12:26:37.464759 LP4Y_EN = 0x0
3894 12:26:37.468076 WORK_FSP = 0x0
3895 12:26:37.468186 WL = 0x2
3896 12:26:37.470842 RL = 0x2
3897 12:26:37.470956 BL = 0x2
3898 12:26:37.474312 RPST = 0x0
3899 12:26:37.474424 RD_PRE = 0x0
3900 12:26:37.477790 WR_PRE = 0x1
3901 12:26:37.477903 WR_PST = 0x0
3902 12:26:37.481262 DBI_WR = 0x0
3903 12:26:37.481371 DBI_RD = 0x0
3904 12:26:37.484697 OTF = 0x1
3905 12:26:37.487484 ===================================
3906 12:26:37.494444 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3907 12:26:37.497795 nWR fixed to 30
3908 12:26:37.501091 [ModeRegInit_LP4] CH0 RK0
3909 12:26:37.501203 [ModeRegInit_LP4] CH0 RK1
3910 12:26:37.504487 [ModeRegInit_LP4] CH1 RK0
3911 12:26:37.507287 [ModeRegInit_LP4] CH1 RK1
3912 12:26:37.507390 match AC timing 17
3913 12:26:37.514148 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3914 12:26:37.517417 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3915 12:26:37.520800 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3916 12:26:37.527200 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3917 12:26:37.530651 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3918 12:26:37.530736 ==
3919 12:26:37.534046 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 12:26:37.537180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 12:26:37.537293 ==
3922 12:26:37.543943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 12:26:37.550747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3924 12:26:37.554202 [CA 0] Center 35 (5~66) winsize 62
3925 12:26:37.557536 [CA 1] Center 35 (5~66) winsize 62
3926 12:26:37.561006 [CA 2] Center 33 (3~64) winsize 62
3927 12:26:37.564144 [CA 3] Center 33 (2~64) winsize 63
3928 12:26:37.567309 [CA 4] Center 33 (2~64) winsize 63
3929 12:26:37.570512 [CA 5] Center 32 (2~63) winsize 62
3930 12:26:37.570626
3931 12:26:37.573887 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3932 12:26:37.574004
3933 12:26:37.577146 [CATrainingPosCal] consider 1 rank data
3934 12:26:37.580519 u2DelayCellTimex100 = 270/100 ps
3935 12:26:37.583911 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3936 12:26:37.587381 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3937 12:26:37.590817 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3938 12:26:37.594215 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3939 12:26:37.597671 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3940 12:26:37.600347 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3941 12:26:37.604151
3942 12:26:37.606992 CA PerBit enable=1, Macro0, CA PI delay=32
3943 12:26:37.607113
3944 12:26:37.610413 [CBTSetCACLKResult] CA Dly = 32
3945 12:26:37.610498 CS Dly: 4 (0~35)
3946 12:26:37.610590 ==
3947 12:26:37.613811 Dram Type= 6, Freq= 0, CH_0, rank 1
3948 12:26:37.617329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 12:26:37.617443 ==
3950 12:26:37.623846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 12:26:37.630544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3952 12:26:37.633813 [CA 0] Center 35 (5~66) winsize 62
3953 12:26:37.637134 [CA 1] Center 35 (5~66) winsize 62
3954 12:26:37.640410 [CA 2] Center 34 (3~65) winsize 63
3955 12:26:37.643636 [CA 3] Center 33 (2~64) winsize 63
3956 12:26:37.647013 [CA 4] Center 32 (2~63) winsize 62
3957 12:26:37.650457 [CA 5] Center 32 (2~63) winsize 62
3958 12:26:37.650573
3959 12:26:37.653828 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3960 12:26:37.653917
3961 12:26:37.657322 [CATrainingPosCal] consider 2 rank data
3962 12:26:37.660105 u2DelayCellTimex100 = 270/100 ps
3963 12:26:37.663663 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3964 12:26:37.666959 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3965 12:26:37.670196 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3966 12:26:37.673992 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3967 12:26:37.677285 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3968 12:26:37.683817 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3969 12:26:37.683912
3970 12:26:37.687060 CA PerBit enable=1, Macro0, CA PI delay=32
3971 12:26:37.687181
3972 12:26:37.690394 [CBTSetCACLKResult] CA Dly = 32
3973 12:26:37.690479 CS Dly: 4 (0~35)
3974 12:26:37.690548
3975 12:26:37.693826 ----->DramcWriteLeveling(PI) begin...
3976 12:26:37.693940 ==
3977 12:26:37.697283 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 12:26:37.703487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 12:26:37.703584 ==
3980 12:26:37.706840 Write leveling (Byte 0): 36 => 36
3981 12:26:37.706965 Write leveling (Byte 1): 32 => 32
3982 12:26:37.710132 DramcWriteLeveling(PI) end<-----
3983 12:26:37.710250
3984 12:26:37.710355 ==
3985 12:26:37.713438 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 12:26:37.720415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 12:26:37.720507 ==
3988 12:26:37.723259 [Gating] SW mode calibration
3989 12:26:37.730352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3990 12:26:37.733876 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3991 12:26:37.740585 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 12:26:37.743685 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 12:26:37.747137 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 12:26:37.750354 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3995 12:26:37.756865 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
3996 12:26:37.760366 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 12:26:37.763947 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 12:26:37.770134 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 12:26:37.773361 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 12:26:37.776633 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 12:26:37.783414 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 12:26:37.786766 0 10 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
4003 12:26:37.790104 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4004 12:26:37.796525 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:26:37.799916 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 12:26:37.803387 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 12:26:37.809660 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 12:26:37.812998 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 12:26:37.816349 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 12:26:37.823554 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4011 12:26:37.826866 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:26:37.829780 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:26:37.836248 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:26:37.839668 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:26:37.843153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:26:37.849634 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:26:37.852996 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:26:37.856313 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:26:37.863478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:26:37.866168 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:26:37.869821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:26:37.876653 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:26:37.880009 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:26:37.883278 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:26:37.886682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:26:37.893390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4027 12:26:37.896772 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4028 12:26:37.899999 Total UI for P1: 0, mck2ui 16
4029 12:26:37.902737 best dqsien dly found for B0: ( 0, 13, 12)
4030 12:26:37.906006 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 12:26:37.909420 Total UI for P1: 0, mck2ui 16
4032 12:26:37.912912 best dqsien dly found for B1: ( 0, 13, 16)
4033 12:26:37.916389 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4034 12:26:37.922988 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4035 12:26:37.923107
4036 12:26:37.926353 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4037 12:26:37.929821 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4038 12:26:37.933185 [Gating] SW calibration Done
4039 12:26:37.933294 ==
4040 12:26:37.936493 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 12:26:37.939717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 12:26:37.939827 ==
4043 12:26:37.939935 RX Vref Scan: 0
4044 12:26:37.943111
4045 12:26:37.943220 RX Vref 0 -> 0, step: 1
4046 12:26:37.943343
4047 12:26:37.946513 RX Delay -230 -> 252, step: 16
4048 12:26:37.949293 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4049 12:26:37.956067 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4050 12:26:37.959416 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4051 12:26:37.963199 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4052 12:26:37.966409 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4053 12:26:37.969920 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4054 12:26:37.976179 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4055 12:26:37.979674 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4056 12:26:37.983145 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4057 12:26:37.986331 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4058 12:26:37.992667 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4059 12:26:37.996003 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4060 12:26:37.999211 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4061 12:26:38.002483 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4062 12:26:38.009689 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4063 12:26:38.013170 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4064 12:26:38.013264 ==
4065 12:26:38.015985 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 12:26:38.019462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 12:26:38.019556 ==
4068 12:26:38.019626 DQS Delay:
4069 12:26:38.022956 DQS0 = 0, DQS1 = 0
4070 12:26:38.023043 DQM Delay:
4071 12:26:38.026335 DQM0 = 51, DQM1 = 46
4072 12:26:38.026448 DQ Delay:
4073 12:26:38.029686 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4074 12:26:38.032832 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4075 12:26:38.036291 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4076 12:26:38.039834 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4077 12:26:38.039932
4078 12:26:38.040011
4079 12:26:38.040075 ==
4080 12:26:38.043183 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 12:26:38.046056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 12:26:38.046140 ==
4083 12:26:38.049370
4084 12:26:38.049446
4085 12:26:38.049509 TX Vref Scan disable
4086 12:26:38.052935 == TX Byte 0 ==
4087 12:26:38.056328 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4088 12:26:38.059756 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4089 12:26:38.062883 == TX Byte 1 ==
4090 12:26:38.066127 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4091 12:26:38.069503 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4092 12:26:38.072772 ==
4093 12:26:38.072873 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 12:26:38.079687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 12:26:38.079814 ==
4096 12:26:38.079913
4097 12:26:38.080006
4098 12:26:38.082466 TX Vref Scan disable
4099 12:26:38.082564 == TX Byte 0 ==
4100 12:26:38.089239 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4101 12:26:38.092512 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4102 12:26:38.092623 == TX Byte 1 ==
4103 12:26:38.099492 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4104 12:26:38.102959 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4105 12:26:38.103073
4106 12:26:38.103175 [DATLAT]
4107 12:26:38.105699 Freq=600, CH0 RK0
4108 12:26:38.105788
4109 12:26:38.105857 DATLAT Default: 0x9
4110 12:26:38.109686 0, 0xFFFF, sum = 0
4111 12:26:38.109776 1, 0xFFFF, sum = 0
4112 12:26:38.112912 2, 0xFFFF, sum = 0
4113 12:26:38.113001 3, 0xFFFF, sum = 0
4114 12:26:38.116181 4, 0xFFFF, sum = 0
4115 12:26:38.116269 5, 0xFFFF, sum = 0
4116 12:26:38.119696 6, 0xFFFF, sum = 0
4117 12:26:38.122380 7, 0xFFFF, sum = 0
4118 12:26:38.122497 8, 0x0, sum = 1
4119 12:26:38.122610 9, 0x0, sum = 2
4120 12:26:38.125802 10, 0x0, sum = 3
4121 12:26:38.125916 11, 0x0, sum = 4
4122 12:26:38.129310 best_step = 9
4123 12:26:38.129433
4124 12:26:38.129532 ==
4125 12:26:38.132703 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 12:26:38.136176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 12:26:38.136277 ==
4128 12:26:38.139238 RX Vref Scan: 1
4129 12:26:38.139352
4130 12:26:38.139448 RX Vref 0 -> 0, step: 1
4131 12:26:38.139539
4132 12:26:38.142521 RX Delay -163 -> 252, step: 8
4133 12:26:38.142624
4134 12:26:38.145984 Set Vref, RX VrefLevel [Byte0]: 55
4135 12:26:38.149236 [Byte1]: 48
4136 12:26:38.153289
4137 12:26:38.153375 Final RX Vref Byte 0 = 55 to rank0
4138 12:26:38.156040 Final RX Vref Byte 1 = 48 to rank0
4139 12:26:38.159541 Final RX Vref Byte 0 = 55 to rank1
4140 12:26:38.162932 Final RX Vref Byte 1 = 48 to rank1==
4141 12:26:38.166289 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 12:26:38.172968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 12:26:38.173074 ==
4144 12:26:38.173144 DQS Delay:
4145 12:26:38.176287 DQS0 = 0, DQS1 = 0
4146 12:26:38.176398 DQM Delay:
4147 12:26:38.176494 DQM0 = 52, DQM1 = 46
4148 12:26:38.179403 DQ Delay:
4149 12:26:38.182630 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4150 12:26:38.185954 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4151 12:26:38.189331 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4152 12:26:38.192794 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4153 12:26:38.192908
4154 12:26:38.193014
4155 12:26:38.199443 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4156 12:26:38.202837 CH0 RK0: MR19=808, MR18=6D5F
4157 12:26:38.209084 CH0_RK0: MR19=0x808, MR18=0x6D5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4158 12:26:38.209192
4159 12:26:38.212462 ----->DramcWriteLeveling(PI) begin...
4160 12:26:38.212543 ==
4161 12:26:38.215791 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 12:26:38.219038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 12:26:38.219175 ==
4164 12:26:38.222354 Write leveling (Byte 0): 34 => 34
4165 12:26:38.225808 Write leveling (Byte 1): 32 => 32
4166 12:26:38.229281 DramcWriteLeveling(PI) end<-----
4167 12:26:38.229374
4168 12:26:38.229441 ==
4169 12:26:38.232797 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 12:26:38.236092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 12:26:38.236174 ==
4172 12:26:38.238973 [Gating] SW mode calibration
4173 12:26:38.246090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4174 12:26:38.252648 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4175 12:26:38.255854 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 12:26:38.262055 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 12:26:38.265431 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 12:26:38.268972 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 1)
4179 12:26:38.275789 0 9 16 | B1->B0 | 2929 2727 | 1 0 | (1 0) (0 0)
4180 12:26:38.279035 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 12:26:38.282390 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 12:26:38.288989 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 12:26:38.292466 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 12:26:38.295215 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 12:26:38.298691 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 12:26:38.305310 0 10 12 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
4187 12:26:38.308910 0 10 16 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
4188 12:26:38.312312 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 12:26:38.318986 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 12:26:38.322136 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:26:38.325453 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 12:26:38.332175 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:26:38.335627 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 12:26:38.338319 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 12:26:38.345261 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:26:38.348722 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:26:38.352146 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:26:38.358535 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:26:38.361933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:26:38.365337 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:26:38.372172 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:26:38.374923 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:26:38.378456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:26:38.385105 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:26:38.388340 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:26:38.391611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:26:38.398045 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:26:38.401663 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:26:38.405062 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:26:38.411832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:26:38.415318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 12:26:38.418028 Total UI for P1: 0, mck2ui 16
4213 12:26:38.421557 best dqsien dly found for B0: ( 0, 13, 14)
4214 12:26:38.424890 Total UI for P1: 0, mck2ui 16
4215 12:26:38.428079 best dqsien dly found for B1: ( 0, 13, 14)
4216 12:26:38.431895 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4217 12:26:38.435120 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4218 12:26:38.435234
4219 12:26:38.438440 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 12:26:38.441814 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4221 12:26:38.445266 [Gating] SW calibration Done
4222 12:26:38.445379 ==
4223 12:26:38.448681 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 12:26:38.451415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 12:26:38.451531 ==
4226 12:26:38.454905 RX Vref Scan: 0
4227 12:26:38.455024
4228 12:26:38.458432 RX Vref 0 -> 0, step: 1
4229 12:26:38.458514
4230 12:26:38.458627 RX Delay -230 -> 252, step: 16
4231 12:26:38.464954 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4232 12:26:38.468234 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4233 12:26:38.471572 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4234 12:26:38.475060 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4235 12:26:38.482086 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4236 12:26:38.485543 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4237 12:26:38.488928 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4238 12:26:38.492166 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4239 12:26:38.495363 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4240 12:26:38.501703 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4241 12:26:38.505079 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4242 12:26:38.508280 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4243 12:26:38.512147 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4244 12:26:38.518339 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4245 12:26:38.521868 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4246 12:26:38.525397 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4247 12:26:38.525509 ==
4248 12:26:38.528172 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 12:26:38.531711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 12:26:38.534964 ==
4251 12:26:38.535084 DQS Delay:
4252 12:26:38.535186 DQS0 = 0, DQS1 = 0
4253 12:26:38.538270 DQM Delay:
4254 12:26:38.538378 DQM0 = 51, DQM1 = 43
4255 12:26:38.541530 DQ Delay:
4256 12:26:38.541618 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4257 12:26:38.544755 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4258 12:26:38.547967 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4259 12:26:38.551272 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4260 12:26:38.551400
4261 12:26:38.554742
4262 12:26:38.554828 ==
4263 12:26:38.558064 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 12:26:38.561478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 12:26:38.561586 ==
4266 12:26:38.561657
4267 12:26:38.561720
4268 12:26:38.564976 TX Vref Scan disable
4269 12:26:38.565069 == TX Byte 0 ==
4270 12:26:38.571545 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4271 12:26:38.574605 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4272 12:26:38.574707 == TX Byte 1 ==
4273 12:26:38.581123 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4274 12:26:38.584604 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4275 12:26:38.584714 ==
4276 12:26:38.588139 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 12:26:38.591540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 12:26:38.591619 ==
4279 12:26:38.591685
4280 12:26:38.591746
4281 12:26:38.595473 TX Vref Scan disable
4282 12:26:38.597904 == TX Byte 0 ==
4283 12:26:38.601182 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4284 12:26:38.604410 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4285 12:26:38.608325 == TX Byte 1 ==
4286 12:26:38.611461 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 12:26:38.614795 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 12:26:38.614915
4289 12:26:38.617967 [DATLAT]
4290 12:26:38.618060 Freq=600, CH0 RK1
4291 12:26:38.618151
4292 12:26:38.621394 DATLAT Default: 0x9
4293 12:26:38.621510 0, 0xFFFF, sum = 0
4294 12:26:38.624640 1, 0xFFFF, sum = 0
4295 12:26:38.624753 2, 0xFFFF, sum = 0
4296 12:26:38.628156 3, 0xFFFF, sum = 0
4297 12:26:38.628265 4, 0xFFFF, sum = 0
4298 12:26:38.630968 5, 0xFFFF, sum = 0
4299 12:26:38.631090 6, 0xFFFF, sum = 0
4300 12:26:38.634557 7, 0xFFFF, sum = 0
4301 12:26:38.634673 8, 0x0, sum = 1
4302 12:26:38.638076 9, 0x0, sum = 2
4303 12:26:38.638202 10, 0x0, sum = 3
4304 12:26:38.641416 11, 0x0, sum = 4
4305 12:26:38.641530 best_step = 9
4306 12:26:38.641634
4307 12:26:38.641725 ==
4308 12:26:38.644566 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 12:26:38.651264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 12:26:38.651395 ==
4311 12:26:38.651500 RX Vref Scan: 0
4312 12:26:38.651593
4313 12:26:38.654559 RX Vref 0 -> 0, step: 1
4314 12:26:38.654677
4315 12:26:38.657810 RX Delay -163 -> 252, step: 8
4316 12:26:38.661299 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4317 12:26:38.664675 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4318 12:26:38.670995 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4319 12:26:38.674371 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4320 12:26:38.677743 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4321 12:26:38.681043 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4322 12:26:38.684224 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4323 12:26:38.690904 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4324 12:26:38.694335 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4325 12:26:38.697839 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4326 12:26:38.701247 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4327 12:26:38.704531 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4328 12:26:38.710969 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4329 12:26:38.714332 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4330 12:26:38.717507 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4331 12:26:38.720877 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4332 12:26:38.720992 ==
4333 12:26:38.724156 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 12:26:38.731013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 12:26:38.731128 ==
4336 12:26:38.731230 DQS Delay:
4337 12:26:38.733895 DQS0 = 0, DQS1 = 0
4338 12:26:38.734010 DQM Delay:
4339 12:26:38.734108 DQM0 = 53, DQM1 = 46
4340 12:26:38.737369 DQ Delay:
4341 12:26:38.740706 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4342 12:26:38.744157 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4343 12:26:38.747514 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4344 12:26:38.750978 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4345 12:26:38.751078
4346 12:26:38.751147
4347 12:26:38.757344 [DQSOSCAuto] RK1, (LSB)MR18= 0x6121, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4348 12:26:38.760652 CH0 RK1: MR19=808, MR18=6121
4349 12:26:38.767277 CH0_RK1: MR19=0x808, MR18=0x6121, DQSOSC=391, MR23=63, INC=171, DEC=114
4350 12:26:38.770713 [RxdqsGatingPostProcess] freq 600
4351 12:26:38.774183 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 12:26:38.777011 Pre-setting of DQS Precalculation
4353 12:26:38.783664 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 12:26:38.783800 ==
4355 12:26:38.787032 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 12:26:38.790494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 12:26:38.790614 ==
4358 12:26:38.797217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 12:26:38.803365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4360 12:26:38.806844 [CA 0] Center 35 (5~66) winsize 62
4361 12:26:38.810332 [CA 1] Center 36 (5~67) winsize 63
4362 12:26:38.813713 [CA 2] Center 34 (4~65) winsize 62
4363 12:26:38.816929 [CA 3] Center 34 (4~65) winsize 62
4364 12:26:38.820080 [CA 4] Center 34 (4~65) winsize 62
4365 12:26:38.823907 [CA 5] Center 33 (3~64) winsize 62
4366 12:26:38.824037
4367 12:26:38.826567 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4368 12:26:38.826684
4369 12:26:38.830566 [CATrainingPosCal] consider 1 rank data
4370 12:26:38.833288 u2DelayCellTimex100 = 270/100 ps
4371 12:26:38.836768 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 12:26:38.840334 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4373 12:26:38.843776 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 12:26:38.846626 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 12:26:38.850104 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 12:26:38.853639 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4377 12:26:38.853727
4378 12:26:38.859702 CA PerBit enable=1, Macro0, CA PI delay=33
4379 12:26:38.859797
4380 12:26:38.859868 [CBTSetCACLKResult] CA Dly = 33
4381 12:26:38.863561 CS Dly: 5 (0~36)
4382 12:26:38.863649 ==
4383 12:26:38.866859 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 12:26:38.869674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 12:26:38.869790 ==
4386 12:26:38.876434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 12:26:38.883417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4388 12:26:38.886819 [CA 0] Center 36 (5~67) winsize 63
4389 12:26:38.889983 [CA 1] Center 36 (5~67) winsize 63
4390 12:26:38.893409 [CA 2] Center 34 (4~65) winsize 62
4391 12:26:38.896829 [CA 3] Center 34 (4~65) winsize 62
4392 12:26:38.899999 [CA 4] Center 34 (4~65) winsize 62
4393 12:26:38.903494 [CA 5] Center 34 (3~65) winsize 63
4394 12:26:38.903603
4395 12:26:38.906836 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4396 12:26:38.906944
4397 12:26:38.909660 [CATrainingPosCal] consider 2 rank data
4398 12:26:38.913128 u2DelayCellTimex100 = 270/100 ps
4399 12:26:38.916660 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 12:26:38.919912 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4401 12:26:38.923085 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 12:26:38.926299 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 12:26:38.929637 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 12:26:38.936185 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 12:26:38.936310
4406 12:26:38.939577 CA PerBit enable=1, Macro0, CA PI delay=33
4407 12:26:38.939659
4408 12:26:38.943009 [CBTSetCACLKResult] CA Dly = 33
4409 12:26:38.943126 CS Dly: 6 (0~39)
4410 12:26:38.943226
4411 12:26:38.946466 ----->DramcWriteLeveling(PI) begin...
4412 12:26:38.946587 ==
4413 12:26:38.949965 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 12:26:38.953481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 12:26:38.956213 ==
4416 12:26:38.956299 Write leveling (Byte 0): 28 => 28
4417 12:26:38.959745 Write leveling (Byte 1): 32 => 32
4418 12:26:38.963095 DramcWriteLeveling(PI) end<-----
4419 12:26:38.963221
4420 12:26:38.963319 ==
4421 12:26:38.966453 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 12:26:38.973033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 12:26:38.973136 ==
4424 12:26:38.976307 [Gating] SW mode calibration
4425 12:26:38.982455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 12:26:38.985910 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 12:26:38.992765 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 12:26:38.996161 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 12:26:38.999086 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4430 12:26:39.005723 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (1 0) (0 0)
4431 12:26:39.008952 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4432 12:26:39.012988 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:26:39.015788 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 12:26:39.022646 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 12:26:39.026113 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 12:26:39.029358 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 12:26:39.036067 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 12:26:39.039423 0 10 12 | B1->B0 | 3c3c 3939 | 0 1 | (1 1) (0 0)
4439 12:26:39.042652 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:26:39.048869 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:26:39.052386 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 12:26:39.055788 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 12:26:39.062013 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:26:39.065432 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 12:26:39.068876 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4446 12:26:39.075388 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4447 12:26:39.078650 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:26:39.082550 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:26:39.089099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:26:39.091966 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:26:39.095358 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:26:39.102165 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:26:39.105712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:26:39.109026 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:26:39.115677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:26:39.118835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:26:39.122167 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:26:39.128936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:26:39.132369 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:26:39.135738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:26:39.142274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:26:39.145586 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 12:26:39.148991 Total UI for P1: 0, mck2ui 16
4464 12:26:39.152337 best dqsien dly found for B0: ( 0, 13, 10)
4465 12:26:39.155863 Total UI for P1: 0, mck2ui 16
4466 12:26:39.158526 best dqsien dly found for B1: ( 0, 13, 10)
4467 12:26:39.161884 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4468 12:26:39.165233 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4469 12:26:39.165349
4470 12:26:39.168737 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4471 12:26:39.172271 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4472 12:26:39.175705 [Gating] SW calibration Done
4473 12:26:39.175791 ==
4474 12:26:39.179051 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 12:26:39.181870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 12:26:39.181961 ==
4477 12:26:39.185056 RX Vref Scan: 0
4478 12:26:39.185140
4479 12:26:39.188464 RX Vref 0 -> 0, step: 1
4480 12:26:39.188573
4481 12:26:39.188672 RX Delay -230 -> 252, step: 16
4482 12:26:39.195740 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4483 12:26:39.199111 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4484 12:26:39.201871 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4485 12:26:39.205901 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4486 12:26:39.212206 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4487 12:26:39.215758 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4488 12:26:39.218986 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4489 12:26:39.221989 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4490 12:26:39.225342 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4491 12:26:39.232261 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4492 12:26:39.235722 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4493 12:26:39.238556 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4494 12:26:39.241984 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4495 12:26:39.245318 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4496 12:26:39.251815 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4497 12:26:39.255110 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4498 12:26:39.255203 ==
4499 12:26:39.258397 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 12:26:39.261892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 12:26:39.261980 ==
4502 12:26:39.265411 DQS Delay:
4503 12:26:39.265499 DQS0 = 0, DQS1 = 0
4504 12:26:39.268841 DQM Delay:
4505 12:26:39.268934 DQM0 = 50, DQM1 = 50
4506 12:26:39.269002 DQ Delay:
4507 12:26:39.272322 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4508 12:26:39.275078 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4509 12:26:39.278584 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4510 12:26:39.282083 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4511 12:26:39.282173
4512 12:26:39.282241
4513 12:26:39.282305 ==
4514 12:26:39.285243 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 12:26:39.291715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 12:26:39.291816 ==
4517 12:26:39.291886
4518 12:26:39.291951
4519 12:26:39.292012 TX Vref Scan disable
4520 12:26:39.295662 == TX Byte 0 ==
4521 12:26:39.298935 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4522 12:26:39.302152 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4523 12:26:39.305409 == TX Byte 1 ==
4524 12:26:39.308908 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4525 12:26:39.315910 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4526 12:26:39.316002 ==
4527 12:26:39.319334 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 12:26:39.322618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 12:26:39.322701 ==
4530 12:26:39.322777
4531 12:26:39.322841
4532 12:26:39.325377 TX Vref Scan disable
4533 12:26:39.328800 == TX Byte 0 ==
4534 12:26:39.332406 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4535 12:26:39.335769 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4536 12:26:39.335855 == TX Byte 1 ==
4537 12:26:39.342084 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4538 12:26:39.345528 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4539 12:26:39.345638
4540 12:26:39.345748 [DATLAT]
4541 12:26:39.348816 Freq=600, CH1 RK0
4542 12:26:39.348922
4543 12:26:39.349034 DATLAT Default: 0x9
4544 12:26:39.352171 0, 0xFFFF, sum = 0
4545 12:26:39.352262 1, 0xFFFF, sum = 0
4546 12:26:39.355463 2, 0xFFFF, sum = 0
4547 12:26:39.355559 3, 0xFFFF, sum = 0
4548 12:26:39.359217 4, 0xFFFF, sum = 0
4549 12:26:39.362491 5, 0xFFFF, sum = 0
4550 12:26:39.362579 6, 0xFFFF, sum = 0
4551 12:26:39.365918 7, 0xFFFF, sum = 0
4552 12:26:39.366004 8, 0x0, sum = 1
4553 12:26:39.366083 9, 0x0, sum = 2
4554 12:26:39.369197 10, 0x0, sum = 3
4555 12:26:39.369282 11, 0x0, sum = 4
4556 12:26:39.371966 best_step = 9
4557 12:26:39.372108
4558 12:26:39.372233 ==
4559 12:26:39.375365 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 12:26:39.378836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 12:26:39.378919 ==
4562 12:26:39.382283 RX Vref Scan: 1
4563 12:26:39.382375
4564 12:26:39.382456 RX Vref 0 -> 0, step: 1
4565 12:26:39.382517
4566 12:26:39.385782 RX Delay -163 -> 252, step: 8
4567 12:26:39.385883
4568 12:26:39.388674 Set Vref, RX VrefLevel [Byte0]: 51
4569 12:26:39.392146 [Byte1]: 49
4570 12:26:39.396279
4571 12:26:39.396379 Final RX Vref Byte 0 = 51 to rank0
4572 12:26:39.399466 Final RX Vref Byte 1 = 49 to rank0
4573 12:26:39.403034 Final RX Vref Byte 0 = 51 to rank1
4574 12:26:39.406356 Final RX Vref Byte 1 = 49 to rank1==
4575 12:26:39.409638 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 12:26:39.416203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 12:26:39.416366 ==
4578 12:26:39.416502 DQS Delay:
4579 12:26:39.416626 DQS0 = 0, DQS1 = 0
4580 12:26:39.419652 DQM Delay:
4581 12:26:39.419795 DQM0 = 48, DQM1 = 45
4582 12:26:39.422461 DQ Delay:
4583 12:26:39.425993 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4584 12:26:39.429483 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4585 12:26:39.429628 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4586 12:26:39.435983 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4587 12:26:39.436082
4588 12:26:39.436175
4589 12:26:39.442709 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
4590 12:26:39.446110 CH1 RK0: MR19=808, MR18=4A6F
4591 12:26:39.452334 CH1_RK0: MR19=0x808, MR18=0x4A6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4592 12:26:39.452433
4593 12:26:39.455645 ----->DramcWriteLeveling(PI) begin...
4594 12:26:39.455756 ==
4595 12:26:39.459530 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 12:26:39.462793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 12:26:39.462910 ==
4598 12:26:39.466045 Write leveling (Byte 0): 30 => 30
4599 12:26:39.469351 Write leveling (Byte 1): 33 => 33
4600 12:26:39.472726 DramcWriteLeveling(PI) end<-----
4601 12:26:39.472855
4602 12:26:39.472952 ==
4603 12:26:39.476166 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 12:26:39.478984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 12:26:39.479118 ==
4606 12:26:39.482342 [Gating] SW mode calibration
4607 12:26:39.489217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 12:26:39.496099 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 12:26:39.499493 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 12:26:39.502197 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 12:26:39.508989 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
4612 12:26:39.512200 0 9 12 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (1 1)
4613 12:26:39.515595 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
4614 12:26:39.522535 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 12:26:39.525755 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 12:26:39.529049 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 12:26:39.535752 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 12:26:39.539258 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 12:26:39.542685 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 12:26:39.549413 0 10 12 | B1->B0 | 3a3a 3636 | 0 0 | (1 1) (0 0)
4621 12:26:39.552209 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:26:39.555651 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:26:39.562175 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 12:26:39.565980 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 12:26:39.569269 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 12:26:39.575656 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 12:26:39.578835 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 12:26:39.582293 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:26:39.589381 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:26:39.592051 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:26:39.595555 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:26:39.602573 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:26:39.605881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:26:39.609187 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:26:39.612500 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:26:39.618746 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:26:39.622139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:26:39.625301 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:26:39.632395 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:26:39.635444 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:26:39.638636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:26:39.645454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:26:39.648889 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:26:39.652036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4645 12:26:39.658824 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 12:26:39.662334 Total UI for P1: 0, mck2ui 16
4647 12:26:39.665812 best dqsien dly found for B0: ( 0, 13, 12)
4648 12:26:39.665897 Total UI for P1: 0, mck2ui 16
4649 12:26:39.672149 best dqsien dly found for B1: ( 0, 13, 12)
4650 12:26:39.675411 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4651 12:26:39.678465 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4652 12:26:39.678555
4653 12:26:39.682435 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 12:26:39.685679 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4655 12:26:39.688987 [Gating] SW calibration Done
4656 12:26:39.689068 ==
4657 12:26:39.692406 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 12:26:39.695235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 12:26:39.695319 ==
4660 12:26:39.698780 RX Vref Scan: 0
4661 12:26:39.698860
4662 12:26:39.698926 RX Vref 0 -> 0, step: 1
4663 12:26:39.698992
4664 12:26:39.702193 RX Delay -230 -> 252, step: 16
4665 12:26:39.708367 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4666 12:26:39.711734 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4667 12:26:39.715029 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4668 12:26:39.718554 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4669 12:26:39.721939 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4670 12:26:39.728774 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4671 12:26:39.732083 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4672 12:26:39.735137 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4673 12:26:39.738885 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4674 12:26:39.745251 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4675 12:26:39.748453 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4676 12:26:39.751967 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4677 12:26:39.755303 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4678 12:26:39.761897 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4679 12:26:39.765352 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4680 12:26:39.768757 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4681 12:26:39.768876 ==
4682 12:26:39.771461 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 12:26:39.774869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 12:26:39.774995 ==
4685 12:26:39.778167 DQS Delay:
4686 12:26:39.778284 DQS0 = 0, DQS1 = 0
4687 12:26:39.781350 DQM Delay:
4688 12:26:39.781466 DQM0 = 50, DQM1 = 47
4689 12:26:39.781565 DQ Delay:
4690 12:26:39.785241 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4691 12:26:39.788525 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4692 12:26:39.791835 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4693 12:26:39.795038 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4694 12:26:39.795160
4695 12:26:39.795257
4696 12:26:39.798443 ==
4697 12:26:39.798521 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 12:26:39.805401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 12:26:39.805511 ==
4700 12:26:39.805611
4701 12:26:39.805712
4702 12:26:39.807922 TX Vref Scan disable
4703 12:26:39.807998 == TX Byte 0 ==
4704 12:26:39.811494 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 12:26:39.818391 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 12:26:39.818510 == TX Byte 1 ==
4707 12:26:39.821797 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4708 12:26:39.828180 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4709 12:26:39.828274 ==
4710 12:26:39.831706 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 12:26:39.835026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 12:26:39.835120 ==
4713 12:26:39.835190
4714 12:26:39.835254
4715 12:26:39.838327 TX Vref Scan disable
4716 12:26:39.841753 == TX Byte 0 ==
4717 12:26:39.845083 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4718 12:26:39.848134 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4719 12:26:39.851402 == TX Byte 1 ==
4720 12:26:39.854625 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4721 12:26:39.858113 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4722 12:26:39.858226
4723 12:26:39.861457 [DATLAT]
4724 12:26:39.861539 Freq=600, CH1 RK1
4725 12:26:39.861614
4726 12:26:39.864730 DATLAT Default: 0x9
4727 12:26:39.864813 0, 0xFFFF, sum = 0
4728 12:26:39.868184 1, 0xFFFF, sum = 0
4729 12:26:39.868270 2, 0xFFFF, sum = 0
4730 12:26:39.870978 3, 0xFFFF, sum = 0
4731 12:26:39.871098 4, 0xFFFF, sum = 0
4732 12:26:39.874394 5, 0xFFFF, sum = 0
4733 12:26:39.874489 6, 0xFFFF, sum = 0
4734 12:26:39.877859 7, 0xFFFF, sum = 0
4735 12:26:39.877978 8, 0x0, sum = 1
4736 12:26:39.881278 9, 0x0, sum = 2
4737 12:26:39.881375 10, 0x0, sum = 3
4738 12:26:39.884675 11, 0x0, sum = 4
4739 12:26:39.884768 best_step = 9
4740 12:26:39.884839
4741 12:26:39.884913 ==
4742 12:26:39.887726 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 12:26:39.891542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 12:26:39.894182 ==
4745 12:26:39.894268 RX Vref Scan: 0
4746 12:26:39.894342
4747 12:26:39.898121 RX Vref 0 -> 0, step: 1
4748 12:26:39.898236
4749 12:26:39.901246 RX Delay -163 -> 252, step: 8
4750 12:26:39.904555 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4751 12:26:39.908169 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4752 12:26:39.914285 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4753 12:26:39.917813 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4754 12:26:39.921232 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4755 12:26:39.924558 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4756 12:26:39.927474 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4757 12:26:39.934275 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4758 12:26:39.937741 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4759 12:26:39.941068 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4760 12:26:39.944475 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4761 12:26:39.947837 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4762 12:26:39.954524 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4763 12:26:39.957750 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4764 12:26:39.960928 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4765 12:26:39.964460 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4766 12:26:39.964583 ==
4767 12:26:39.967215 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 12:26:39.973896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 12:26:39.973993 ==
4770 12:26:39.974062 DQS Delay:
4771 12:26:39.977177 DQS0 = 0, DQS1 = 0
4772 12:26:39.977264 DQM Delay:
4773 12:26:39.977332 DQM0 = 48, DQM1 = 45
4774 12:26:39.980773 DQ Delay:
4775 12:26:39.984160 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4776 12:26:39.987571 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4777 12:26:39.991010 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4778 12:26:39.994330 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4779 12:26:39.994417
4780 12:26:39.994486
4781 12:26:40.000647 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4782 12:26:40.004057 CH1 RK1: MR19=808, MR18=6E25
4783 12:26:40.010569 CH1_RK1: MR19=0x808, MR18=0x6E25, DQSOSC=389, MR23=63, INC=173, DEC=115
4784 12:26:40.013889 [RxdqsGatingPostProcess] freq 600
4785 12:26:40.017276 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4786 12:26:40.020780 Pre-setting of DQS Precalculation
4787 12:26:40.027662 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4788 12:26:40.033750 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4789 12:26:40.040799 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4790 12:26:40.040992
4791 12:26:40.041110
4792 12:26:40.044154 [Calibration Summary] 1200 Mbps
4793 12:26:40.044279 CH 0, Rank 0
4794 12:26:40.047534 SW Impedance : PASS
4795 12:26:40.050775 DUTY Scan : NO K
4796 12:26:40.050858 ZQ Calibration : PASS
4797 12:26:40.054188 Jitter Meter : NO K
4798 12:26:40.057658 CBT Training : PASS
4799 12:26:40.057778 Write leveling : PASS
4800 12:26:40.061012 RX DQS gating : PASS
4801 12:26:40.064287 RX DQ/DQS(RDDQC) : PASS
4802 12:26:40.064387 TX DQ/DQS : PASS
4803 12:26:40.067425 RX DATLAT : PASS
4804 12:26:40.067544 RX DQ/DQS(Engine): PASS
4805 12:26:40.070314 TX OE : NO K
4806 12:26:40.070452 All Pass.
4807 12:26:40.070550
4808 12:26:40.073674 CH 0, Rank 1
4809 12:26:40.076944 SW Impedance : PASS
4810 12:26:40.077078 DUTY Scan : NO K
4811 12:26:40.080844 ZQ Calibration : PASS
4812 12:26:40.080938 Jitter Meter : NO K
4813 12:26:40.084205 CBT Training : PASS
4814 12:26:40.086981 Write leveling : PASS
4815 12:26:40.087070 RX DQS gating : PASS
4816 12:26:40.090446 RX DQ/DQS(RDDQC) : PASS
4817 12:26:40.093891 TX DQ/DQS : PASS
4818 12:26:40.093979 RX DATLAT : PASS
4819 12:26:40.097252 RX DQ/DQS(Engine): PASS
4820 12:26:40.100676 TX OE : NO K
4821 12:26:40.100766 All Pass.
4822 12:26:40.100835
4823 12:26:40.100899 CH 1, Rank 0
4824 12:26:40.103965 SW Impedance : PASS
4825 12:26:40.107287 DUTY Scan : NO K
4826 12:26:40.107395 ZQ Calibration : PASS
4827 12:26:40.110549 Jitter Meter : NO K
4828 12:26:40.113555 CBT Training : PASS
4829 12:26:40.113643 Write leveling : PASS
4830 12:26:40.116933 RX DQS gating : PASS
4831 12:26:40.120472 RX DQ/DQS(RDDQC) : PASS
4832 12:26:40.120560 TX DQ/DQS : PASS
4833 12:26:40.123869 RX DATLAT : PASS
4834 12:26:40.126604 RX DQ/DQS(Engine): PASS
4835 12:26:40.126717 TX OE : NO K
4836 12:26:40.126825 All Pass.
4837 12:26:40.130009
4838 12:26:40.130088 CH 1, Rank 1
4839 12:26:40.133365 SW Impedance : PASS
4840 12:26:40.133452 DUTY Scan : NO K
4841 12:26:40.136731 ZQ Calibration : PASS
4842 12:26:40.140121 Jitter Meter : NO K
4843 12:26:40.140245 CBT Training : PASS
4844 12:26:40.143553 Write leveling : PASS
4845 12:26:40.143651 RX DQS gating : PASS
4846 12:26:40.147009 RX DQ/DQS(RDDQC) : PASS
4847 12:26:40.149815 TX DQ/DQS : PASS
4848 12:26:40.149947 RX DATLAT : PASS
4849 12:26:40.153131 RX DQ/DQS(Engine): PASS
4850 12:26:40.156484 TX OE : NO K
4851 12:26:40.156606 All Pass.
4852 12:26:40.156707
4853 12:26:40.159992 DramC Write-DBI off
4854 12:26:40.160105 PER_BANK_REFRESH: Hybrid Mode
4855 12:26:40.163476 TX_TRACKING: ON
4856 12:26:40.173363 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4857 12:26:40.176692 [FAST_K] Save calibration result to emmc
4858 12:26:40.180134 dramc_set_vcore_voltage set vcore to 662500
4859 12:26:40.180251 Read voltage for 933, 3
4860 12:26:40.182823 Vio18 = 0
4861 12:26:40.182974 Vcore = 662500
4862 12:26:40.183086 Vdram = 0
4863 12:26:40.186075 Vddq = 0
4864 12:26:40.186183 Vmddr = 0
4865 12:26:40.189938 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4866 12:26:40.196171 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4867 12:26:40.199719 MEM_TYPE=3, freq_sel=17
4868 12:26:40.203155 sv_algorithm_assistance_LP4_1600
4869 12:26:40.206493 ============ PULL DRAM RESETB DOWN ============
4870 12:26:40.209191 ========== PULL DRAM RESETB DOWN end =========
4871 12:26:40.216060 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4872 12:26:40.219333 ===================================
4873 12:26:40.219453 LPDDR4 DRAM CONFIGURATION
4874 12:26:40.222655 ===================================
4875 12:26:40.225905 EX_ROW_EN[0] = 0x0
4876 12:26:40.229091 EX_ROW_EN[1] = 0x0
4877 12:26:40.229199 LP4Y_EN = 0x0
4878 12:26:40.232406 WORK_FSP = 0x0
4879 12:26:40.232513 WL = 0x3
4880 12:26:40.235721 RL = 0x3
4881 12:26:40.235824 BL = 0x2
4882 12:26:40.239110 RPST = 0x0
4883 12:26:40.239214 RD_PRE = 0x0
4884 12:26:40.242706 WR_PRE = 0x1
4885 12:26:40.242820 WR_PST = 0x0
4886 12:26:40.246034 DBI_WR = 0x0
4887 12:26:40.246153 DBI_RD = 0x0
4888 12:26:40.249488 OTF = 0x1
4889 12:26:40.252178 ===================================
4890 12:26:40.255774 ===================================
4891 12:26:40.255890 ANA top config
4892 12:26:40.259080 ===================================
4893 12:26:40.262504 DLL_ASYNC_EN = 0
4894 12:26:40.266011 ALL_SLAVE_EN = 1
4895 12:26:40.266124 NEW_RANK_MODE = 1
4896 12:26:40.269448 DLL_IDLE_MODE = 1
4897 12:26:40.272167 LP45_APHY_COMB_EN = 1
4898 12:26:40.275754 TX_ODT_DIS = 1
4899 12:26:40.279111 NEW_8X_MODE = 1
4900 12:26:40.282186 ===================================
4901 12:26:40.285955 ===================================
4902 12:26:40.286043 data_rate = 1866
4903 12:26:40.289326 CKR = 1
4904 12:26:40.292005 DQ_P2S_RATIO = 8
4905 12:26:40.295283 ===================================
4906 12:26:40.298852 CA_P2S_RATIO = 8
4907 12:26:40.302331 DQ_CA_OPEN = 0
4908 12:26:40.305794 DQ_SEMI_OPEN = 0
4909 12:26:40.305915 CA_SEMI_OPEN = 0
4910 12:26:40.308558 CA_FULL_RATE = 0
4911 12:26:40.312468 DQ_CKDIV4_EN = 1
4912 12:26:40.315182 CA_CKDIV4_EN = 1
4913 12:26:40.318739 CA_PREDIV_EN = 0
4914 12:26:40.322228 PH8_DLY = 0
4915 12:26:40.322320 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4916 12:26:40.325359 DQ_AAMCK_DIV = 4
4917 12:26:40.328703 CA_AAMCK_DIV = 4
4918 12:26:40.331942 CA_ADMCK_DIV = 4
4919 12:26:40.335241 DQ_TRACK_CA_EN = 0
4920 12:26:40.338629 CA_PICK = 933
4921 12:26:40.342136 CA_MCKIO = 933
4922 12:26:40.342222 MCKIO_SEMI = 0
4923 12:26:40.345546 PLL_FREQ = 3732
4924 12:26:40.348955 DQ_UI_PI_RATIO = 32
4925 12:26:40.352388 CA_UI_PI_RATIO = 0
4926 12:26:40.355118 ===================================
4927 12:26:40.358381 ===================================
4928 12:26:40.361832 memory_type:LPDDR4
4929 12:26:40.361944 GP_NUM : 10
4930 12:26:40.365263 SRAM_EN : 1
4931 12:26:40.368817 MD32_EN : 0
4932 12:26:40.371567 ===================================
4933 12:26:40.371687 [ANA_INIT] >>>>>>>>>>>>>>
4934 12:26:40.374990 <<<<<< [CONFIGURE PHASE]: ANA_TX
4935 12:26:40.378591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4936 12:26:40.381396 ===================================
4937 12:26:40.384654 data_rate = 1866,PCW = 0X8f00
4938 12:26:40.388578 ===================================
4939 12:26:40.391791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4940 12:26:40.398351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 12:26:40.401502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 12:26:40.408392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4943 12:26:40.411914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4944 12:26:40.414680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4945 12:26:40.414792 [ANA_INIT] flow start
4946 12:26:40.418027 [ANA_INIT] PLL >>>>>>>>
4947 12:26:40.421548 [ANA_INIT] PLL <<<<<<<<
4948 12:26:40.421659 [ANA_INIT] MIDPI >>>>>>>>
4949 12:26:40.425189 [ANA_INIT] MIDPI <<<<<<<<
4950 12:26:40.427958 [ANA_INIT] DLL >>>>>>>>
4951 12:26:40.428045 [ANA_INIT] flow end
4952 12:26:40.434722 ============ LP4 DIFF to SE enter ============
4953 12:26:40.437891 ============ LP4 DIFF to SE exit ============
4954 12:26:40.441238 [ANA_INIT] <<<<<<<<<<<<<
4955 12:26:40.444479 [Flow] Enable top DCM control >>>>>
4956 12:26:40.447863 [Flow] Enable top DCM control <<<<<
4957 12:26:40.447974 Enable DLL master slave shuffle
4958 12:26:40.454309 ==============================================================
4959 12:26:40.457784 Gating Mode config
4960 12:26:40.461335 ==============================================================
4961 12:26:40.464877 Config description:
4962 12:26:40.474483 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4963 12:26:40.481418 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4964 12:26:40.484160 SELPH_MODE 0: By rank 1: By Phase
4965 12:26:40.491105 ==============================================================
4966 12:26:40.494486 GAT_TRACK_EN = 1
4967 12:26:40.497844 RX_GATING_MODE = 2
4968 12:26:40.501240 RX_GATING_TRACK_MODE = 2
4969 12:26:40.504625 SELPH_MODE = 1
4970 12:26:40.504712 PICG_EARLY_EN = 1
4971 12:26:40.507978 VALID_LAT_VALUE = 1
4972 12:26:40.514373 ==============================================================
4973 12:26:40.517904 Enter into Gating configuration >>>>
4974 12:26:40.521111 Exit from Gating configuration <<<<
4975 12:26:40.524480 Enter into DVFS_PRE_config >>>>>
4976 12:26:40.534284 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4977 12:26:40.537873 Exit from DVFS_PRE_config <<<<<
4978 12:26:40.541303 Enter into PICG configuration >>>>
4979 12:26:40.544604 Exit from PICG configuration <<<<
4980 12:26:40.547929 [RX_INPUT] configuration >>>>>
4981 12:26:40.551010 [RX_INPUT] configuration <<<<<
4982 12:26:40.554452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4983 12:26:40.561228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4984 12:26:40.567315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 12:26:40.574327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 12:26:40.581184 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 12:26:40.583974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 12:26:40.590787 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4989 12:26:40.594347 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4990 12:26:40.597773 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4991 12:26:40.600932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4992 12:26:40.607099 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4993 12:26:40.610435 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 12:26:40.614322 ===================================
4995 12:26:40.617653 LPDDR4 DRAM CONFIGURATION
4996 12:26:40.621054 ===================================
4997 12:26:40.621140 EX_ROW_EN[0] = 0x0
4998 12:26:40.624317 EX_ROW_EN[1] = 0x0
4999 12:26:40.624402 LP4Y_EN = 0x0
5000 12:26:40.627768 WORK_FSP = 0x0
5001 12:26:40.627854 WL = 0x3
5002 12:26:40.631229 RL = 0x3
5003 12:26:40.631314 BL = 0x2
5004 12:26:40.634060 RPST = 0x0
5005 12:26:40.634170 RD_PRE = 0x0
5006 12:26:40.637578 WR_PRE = 0x1
5007 12:26:40.637682 WR_PST = 0x0
5008 12:26:40.641084 DBI_WR = 0x0
5009 12:26:40.644476 DBI_RD = 0x0
5010 12:26:40.644551 OTF = 0x1
5011 12:26:40.647830 ===================================
5012 12:26:40.650505 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5013 12:26:40.653772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5014 12:26:40.660905 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 12:26:40.663719 ===================================
5016 12:26:40.667593 LPDDR4 DRAM CONFIGURATION
5017 12:26:40.670384 ===================================
5018 12:26:40.670470 EX_ROW_EN[0] = 0x10
5019 12:26:40.673716 EX_ROW_EN[1] = 0x0
5020 12:26:40.673800 LP4Y_EN = 0x0
5021 12:26:40.677263 WORK_FSP = 0x0
5022 12:26:40.677350 WL = 0x3
5023 12:26:40.680726 RL = 0x3
5024 12:26:40.680812 BL = 0x2
5025 12:26:40.683664 RPST = 0x0
5026 12:26:40.683745 RD_PRE = 0x0
5027 12:26:40.687214 WR_PRE = 0x1
5028 12:26:40.687322 WR_PST = 0x0
5029 12:26:40.690638 DBI_WR = 0x0
5030 12:26:40.690721 DBI_RD = 0x0
5031 12:26:40.693454 OTF = 0x1
5032 12:26:40.697012 ===================================
5033 12:26:40.703809 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5034 12:26:40.707168 nWR fixed to 30
5035 12:26:40.710034 [ModeRegInit_LP4] CH0 RK0
5036 12:26:40.710157 [ModeRegInit_LP4] CH0 RK1
5037 12:26:40.713446 [ModeRegInit_LP4] CH1 RK0
5038 12:26:40.716725 [ModeRegInit_LP4] CH1 RK1
5039 12:26:40.716811 match AC timing 9
5040 12:26:40.723422 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5041 12:26:40.726704 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5042 12:26:40.730543 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5043 12:26:40.736968 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5044 12:26:40.740382 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5045 12:26:40.740468 ==
5046 12:26:40.743763 Dram Type= 6, Freq= 0, CH_0, rank 0
5047 12:26:40.747246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5048 12:26:40.747336 ==
5049 12:26:40.753705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5050 12:26:40.760296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5051 12:26:40.763689 [CA 0] Center 37 (6~68) winsize 63
5052 12:26:40.766782 [CA 1] Center 37 (7~68) winsize 62
5053 12:26:40.770219 [CA 2] Center 34 (4~65) winsize 62
5054 12:26:40.773546 [CA 3] Center 34 (3~65) winsize 63
5055 12:26:40.776949 [CA 4] Center 33 (3~64) winsize 62
5056 12:26:40.780436 [CA 5] Center 32 (2~62) winsize 61
5057 12:26:40.780550
5058 12:26:40.783185 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5059 12:26:40.783268
5060 12:26:40.786688 [CATrainingPosCal] consider 1 rank data
5061 12:26:40.790163 u2DelayCellTimex100 = 270/100 ps
5062 12:26:40.793106 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5063 12:26:40.796517 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5064 12:26:40.799984 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5065 12:26:40.803394 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5066 12:26:40.806894 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5067 12:26:40.810282 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5068 12:26:40.813722
5069 12:26:40.816530 CA PerBit enable=1, Macro0, CA PI delay=32
5070 12:26:40.816649
5071 12:26:40.819955 [CBTSetCACLKResult] CA Dly = 32
5072 12:26:40.820038 CS Dly: 5 (0~36)
5073 12:26:40.820104 ==
5074 12:26:40.823232 Dram Type= 6, Freq= 0, CH_0, rank 1
5075 12:26:40.826807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 12:26:40.826891 ==
5077 12:26:40.833366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 12:26:40.840345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5079 12:26:40.843064 [CA 0] Center 37 (7~68) winsize 62
5080 12:26:40.846713 [CA 1] Center 37 (7~68) winsize 62
5081 12:26:40.850101 [CA 2] Center 34 (4~65) winsize 62
5082 12:26:40.853753 [CA 3] Center 34 (3~65) winsize 63
5083 12:26:40.856548 [CA 4] Center 32 (2~63) winsize 62
5084 12:26:40.859747 [CA 5] Center 32 (2~63) winsize 62
5085 12:26:40.859889
5086 12:26:40.863053 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5087 12:26:40.863172
5088 12:26:40.866313 [CATrainingPosCal] consider 2 rank data
5089 12:26:40.870283 u2DelayCellTimex100 = 270/100 ps
5090 12:26:40.873452 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5091 12:26:40.876764 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5092 12:26:40.880099 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5093 12:26:40.883508 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5094 12:26:40.886334 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5095 12:26:40.893360 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5096 12:26:40.893503
5097 12:26:40.896185 CA PerBit enable=1, Macro0, CA PI delay=32
5098 12:26:40.896295
5099 12:26:40.899672 [CBTSetCACLKResult] CA Dly = 32
5100 12:26:40.899799 CS Dly: 5 (0~37)
5101 12:26:40.899915
5102 12:26:40.903154 ----->DramcWriteLeveling(PI) begin...
5103 12:26:40.903263 ==
5104 12:26:40.906501 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 12:26:40.912917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 12:26:40.913003 ==
5107 12:26:40.916195 Write leveling (Byte 0): 33 => 33
5108 12:26:40.916271 Write leveling (Byte 1): 30 => 30
5109 12:26:40.919769 DramcWriteLeveling(PI) end<-----
5110 12:26:40.919853
5111 12:26:40.923081 ==
5112 12:26:40.923209 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 12:26:40.929888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 12:26:40.930024 ==
5115 12:26:40.932536 [Gating] SW mode calibration
5116 12:26:40.939872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5117 12:26:40.942618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5118 12:26:40.949543 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5119 12:26:40.952920 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 12:26:40.956429 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 12:26:40.962615 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 12:26:40.966044 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 12:26:40.969451 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 12:26:40.975937 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5125 12:26:40.979252 0 14 28 | B1->B0 | 3434 2525 | 0 0 | (1 0) (0 0)
5126 12:26:40.982470 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5127 12:26:40.989318 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 12:26:40.992714 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 12:26:40.996052 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 12:26:41.002300 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 12:26:41.005962 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 12:26:41.009457 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5133 12:26:41.012900 0 15 28 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
5134 12:26:41.018950 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5135 12:26:41.022477 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 12:26:41.026016 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 12:26:41.032327 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 12:26:41.035819 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 12:26:41.039107 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 12:26:41.045825 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 12:26:41.049216 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5142 12:26:41.052718 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 12:26:41.059094 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:26:41.062553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:26:41.066124 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:26:41.072479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:26:41.075728 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:26:41.079130 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:26:41.085955 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:26:41.089295 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:26:41.092616 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:26:41.099277 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:26:41.102188 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:26:41.105686 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:26:41.112196 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:26:41.115767 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:26:41.118618 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5158 12:26:41.122012 Total UI for P1: 0, mck2ui 16
5159 12:26:41.125521 best dqsien dly found for B0: ( 1, 2, 26)
5160 12:26:41.131851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5161 12:26:41.135428 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 12:26:41.138873 Total UI for P1: 0, mck2ui 16
5163 12:26:41.142201 best dqsien dly found for B1: ( 1, 2, 30)
5164 12:26:41.145008 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5165 12:26:41.148355 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5166 12:26:41.148440
5167 12:26:41.151712 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5168 12:26:41.155436 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5169 12:26:41.158856 [Gating] SW calibration Done
5170 12:26:41.158941 ==
5171 12:26:41.161556 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 12:26:41.165177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 12:26:41.165263 ==
5174 12:26:41.168511 RX Vref Scan: 0
5175 12:26:41.168597
5176 12:26:41.171987 RX Vref 0 -> 0, step: 1
5177 12:26:41.172082
5178 12:26:41.172180 RX Delay -80 -> 252, step: 8
5179 12:26:41.178790 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5180 12:26:41.182174 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5181 12:26:41.185428 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5182 12:26:41.188772 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5183 12:26:41.192078 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5184 12:26:41.195400 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5185 12:26:41.201447 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5186 12:26:41.204907 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5187 12:26:41.208259 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5188 12:26:41.211683 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5189 12:26:41.215164 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5190 12:26:41.221475 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5191 12:26:41.224712 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5192 12:26:41.228181 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5193 12:26:41.231759 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5194 12:26:41.235085 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5195 12:26:41.235215 ==
5196 12:26:41.237946 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 12:26:41.244879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 12:26:41.244999 ==
5199 12:26:41.245108 DQS Delay:
5200 12:26:41.248170 DQS0 = 0, DQS1 = 0
5201 12:26:41.248278 DQM Delay:
5202 12:26:41.251495 DQM0 = 104, DQM1 = 95
5203 12:26:41.251604 DQ Delay:
5204 12:26:41.254869 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5205 12:26:41.258324 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5206 12:26:41.261620 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5207 12:26:41.264969 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5208 12:26:41.265081
5209 12:26:41.265183
5210 12:26:41.265291 ==
5211 12:26:41.268349 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 12:26:41.271871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 12:26:41.271982 ==
5214 12:26:41.272088
5215 12:26:41.272190
5216 12:26:41.274772 TX Vref Scan disable
5217 12:26:41.278316 == TX Byte 0 ==
5218 12:26:41.281768 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5219 12:26:41.284545 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5220 12:26:41.288012 == TX Byte 1 ==
5221 12:26:41.291372 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5222 12:26:41.294668 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5223 12:26:41.294774 ==
5224 12:26:41.298119 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 12:26:41.305010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 12:26:41.305134 ==
5227 12:26:41.305235
5228 12:26:41.305341
5229 12:26:41.305449 TX Vref Scan disable
5230 12:26:41.308878 == TX Byte 0 ==
5231 12:26:41.312121 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5232 12:26:41.318235 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5233 12:26:41.318346 == TX Byte 1 ==
5234 12:26:41.321670 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5235 12:26:41.328498 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5236 12:26:41.328610
5237 12:26:41.328710 [DATLAT]
5238 12:26:41.328818 Freq=933, CH0 RK0
5239 12:26:41.328924
5240 12:26:41.331811 DATLAT Default: 0xd
5241 12:26:41.331916 0, 0xFFFF, sum = 0
5242 12:26:41.335361 1, 0xFFFF, sum = 0
5243 12:26:41.335464 2, 0xFFFF, sum = 0
5244 12:26:41.338224 3, 0xFFFF, sum = 0
5245 12:26:41.341714 4, 0xFFFF, sum = 0
5246 12:26:41.341822 5, 0xFFFF, sum = 0
5247 12:26:41.345159 6, 0xFFFF, sum = 0
5248 12:26:41.345269 7, 0xFFFF, sum = 0
5249 12:26:41.348800 8, 0xFFFF, sum = 0
5250 12:26:41.348909 9, 0xFFFF, sum = 0
5251 12:26:41.351571 10, 0x0, sum = 1
5252 12:26:41.351679 11, 0x0, sum = 2
5253 12:26:41.355028 12, 0x0, sum = 3
5254 12:26:41.355134 13, 0x0, sum = 4
5255 12:26:41.355247 best_step = 11
5256 12:26:41.355354
5257 12:26:41.358330 ==
5258 12:26:41.361808 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:26:41.365126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:26:41.365240 ==
5261 12:26:41.365336 RX Vref Scan: 1
5262 12:26:41.365447
5263 12:26:41.368384 RX Vref 0 -> 0, step: 1
5264 12:26:41.368495
5265 12:26:41.371685 RX Delay -53 -> 252, step: 4
5266 12:26:41.371797
5267 12:26:41.375124 Set Vref, RX VrefLevel [Byte0]: 55
5268 12:26:41.378716 [Byte1]: 48
5269 12:26:41.378829
5270 12:26:41.382105 Final RX Vref Byte 0 = 55 to rank0
5271 12:26:41.384960 Final RX Vref Byte 1 = 48 to rank0
5272 12:26:41.388405 Final RX Vref Byte 0 = 55 to rank1
5273 12:26:41.391718 Final RX Vref Byte 1 = 48 to rank1==
5274 12:26:41.395095 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 12:26:41.398383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 12:26:41.398469 ==
5277 12:26:41.401708 DQS Delay:
5278 12:26:41.401793 DQS0 = 0, DQS1 = 0
5279 12:26:41.405096 DQM Delay:
5280 12:26:41.405181 DQM0 = 104, DQM1 = 94
5281 12:26:41.408386 DQ Delay:
5282 12:26:41.411783 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5283 12:26:41.415175 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5284 12:26:41.417962 DQ8 =84, DQ9 =86, DQ10 =94, DQ11 =88
5285 12:26:41.421828 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5286 12:26:41.421913
5287 12:26:41.421981
5288 12:26:41.428178 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5289 12:26:41.431775 CH0 RK0: MR19=505, MR18=3129
5290 12:26:41.438424 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5291 12:26:41.438509
5292 12:26:41.441962 ----->DramcWriteLeveling(PI) begin...
5293 12:26:41.442042 ==
5294 12:26:41.444664 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 12:26:41.448198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 12:26:41.448280 ==
5297 12:26:41.451772 Write leveling (Byte 0): 32 => 32
5298 12:26:41.455174 Write leveling (Byte 1): 29 => 29
5299 12:26:41.457973 DramcWriteLeveling(PI) end<-----
5300 12:26:41.458048
5301 12:26:41.458114 ==
5302 12:26:41.461403 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 12:26:41.464945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 12:26:41.465025 ==
5305 12:26:41.468290 [Gating] SW mode calibration
5306 12:26:41.475025 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 12:26:41.481665 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 12:26:41.485115 0 14 0 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5309 12:26:41.491322 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 12:26:41.494863 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 12:26:41.498409 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 12:26:41.505011 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 12:26:41.508204 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 12:26:41.511453 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5315 12:26:41.514745 0 14 28 | B1->B0 | 2727 2d2d | 0 1 | (0 0) (1 0)
5316 12:26:41.521500 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:26:41.524967 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 12:26:41.528258 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 12:26:41.534471 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 12:26:41.537993 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 12:26:41.541445 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 12:26:41.547678 0 15 24 | B1->B0 | 2727 2423 | 0 1 | (0 0) (0 0)
5323 12:26:41.551225 0 15 28 | B1->B0 | 3a3a 3939 | 0 1 | (0 0) (0 0)
5324 12:26:41.554793 1 0 0 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
5325 12:26:41.561696 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 12:26:41.564414 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 12:26:41.567891 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:26:41.574842 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 12:26:41.577741 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 12:26:41.581129 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5331 12:26:41.588309 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 12:26:41.591652 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5333 12:26:41.594408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:26:41.601415 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:26:41.604785 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:26:41.607655 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:26:41.614456 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:26:41.617622 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:26:41.621541 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:26:41.624837 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:26:41.631344 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:26:41.634681 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:26:41.638097 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:26:41.644273 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:26:41.647753 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:26:41.651293 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 12:26:41.657561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5348 12:26:41.661138 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 12:26:41.664639 Total UI for P1: 0, mck2ui 16
5350 12:26:41.668085 best dqsien dly found for B0: ( 1, 2, 26)
5351 12:26:41.670816 Total UI for P1: 0, mck2ui 16
5352 12:26:41.674187 best dqsien dly found for B1: ( 1, 2, 28)
5353 12:26:41.677696 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5354 12:26:41.681021 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5355 12:26:41.681126
5356 12:26:41.684389 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5357 12:26:41.687800 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5358 12:26:41.691252 [Gating] SW calibration Done
5359 12:26:41.691347 ==
5360 12:26:41.694716 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 12:26:41.698018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 12:26:41.701392 ==
5363 12:26:41.701478 RX Vref Scan: 0
5364 12:26:41.701546
5365 12:26:41.704946 RX Vref 0 -> 0, step: 1
5366 12:26:41.705031
5367 12:26:41.705099 RX Delay -80 -> 252, step: 8
5368 12:26:41.711235 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5369 12:26:41.714851 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5370 12:26:41.718297 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5371 12:26:41.721101 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5372 12:26:41.724935 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5373 12:26:41.731568 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5374 12:26:41.734893 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5375 12:26:41.738050 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5376 12:26:41.741427 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5377 12:26:41.744693 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5378 12:26:41.748078 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5379 12:26:41.754803 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5380 12:26:41.758238 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5381 12:26:41.761126 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5382 12:26:41.764703 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5383 12:26:41.768165 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5384 12:26:41.768243 ==
5385 12:26:41.770975 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 12:26:41.778034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 12:26:41.778153 ==
5388 12:26:41.778249 DQS Delay:
5389 12:26:41.778348 DQS0 = 0, DQS1 = 0
5390 12:26:41.781587 DQM Delay:
5391 12:26:41.781689 DQM0 = 104, DQM1 = 92
5392 12:26:41.784997 DQ Delay:
5393 12:26:41.787710 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5394 12:26:41.791066 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5395 12:26:41.794342 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5396 12:26:41.797898 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5397 12:26:41.797998
5398 12:26:41.798091
5399 12:26:41.798180 ==
5400 12:26:41.801302 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 12:26:41.804509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 12:26:41.804584 ==
5403 12:26:41.804662
5404 12:26:41.804722
5405 12:26:41.807857 TX Vref Scan disable
5406 12:26:41.811227 == TX Byte 0 ==
5407 12:26:41.814771 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5408 12:26:41.817773 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5409 12:26:41.821211 == TX Byte 1 ==
5410 12:26:41.824676 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5411 12:26:41.828076 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5412 12:26:41.828152 ==
5413 12:26:41.831491 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 12:26:41.834208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 12:26:41.834281 ==
5416 12:26:41.837513
5417 12:26:41.837584
5418 12:26:41.837646 TX Vref Scan disable
5419 12:26:41.841320 == TX Byte 0 ==
5420 12:26:41.844666 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5421 12:26:41.851057 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5422 12:26:41.851161 == TX Byte 1 ==
5423 12:26:41.854555 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5424 12:26:41.861205 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5425 12:26:41.861314
5426 12:26:41.861408 [DATLAT]
5427 12:26:41.861499 Freq=933, CH0 RK1
5428 12:26:41.861588
5429 12:26:41.864756 DATLAT Default: 0xb
5430 12:26:41.864849 0, 0xFFFF, sum = 0
5431 12:26:41.867481 1, 0xFFFF, sum = 0
5432 12:26:41.867553 2, 0xFFFF, sum = 0
5433 12:26:41.870926 3, 0xFFFF, sum = 0
5434 12:26:41.871025 4, 0xFFFF, sum = 0
5435 12:26:41.874378 5, 0xFFFF, sum = 0
5436 12:26:41.877915 6, 0xFFFF, sum = 0
5437 12:26:41.878022 7, 0xFFFF, sum = 0
5438 12:26:41.880834 8, 0xFFFF, sum = 0
5439 12:26:41.880912 9, 0xFFFF, sum = 0
5440 12:26:41.884521 10, 0x0, sum = 1
5441 12:26:41.884594 11, 0x0, sum = 2
5442 12:26:41.884657 12, 0x0, sum = 3
5443 12:26:41.888013 13, 0x0, sum = 4
5444 12:26:41.888103 best_step = 11
5445 12:26:41.888171
5446 12:26:41.890666 ==
5447 12:26:41.894591 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 12:26:41.897851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 12:26:41.897937 ==
5450 12:26:41.898005 RX Vref Scan: 0
5451 12:26:41.898069
5452 12:26:41.901165 RX Vref 0 -> 0, step: 1
5453 12:26:41.901250
5454 12:26:41.903982 RX Delay -53 -> 252, step: 4
5455 12:26:41.907305 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5456 12:26:41.913921 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5457 12:26:41.917399 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5458 12:26:41.920885 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5459 12:26:41.924386 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5460 12:26:41.927192 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5461 12:26:41.934125 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5462 12:26:41.937711 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5463 12:26:41.940498 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5464 12:26:41.943942 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5465 12:26:41.947276 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5466 12:26:41.950660 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5467 12:26:41.957308 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5468 12:26:41.960558 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5469 12:26:41.964005 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5470 12:26:41.967195 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5471 12:26:41.967276 ==
5472 12:26:41.970461 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 12:26:41.977340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 12:26:41.977429 ==
5475 12:26:41.977498 DQS Delay:
5476 12:26:41.980810 DQS0 = 0, DQS1 = 0
5477 12:26:41.980895 DQM Delay:
5478 12:26:41.980963 DQM0 = 104, DQM1 = 94
5479 12:26:41.983762 DQ Delay:
5480 12:26:41.987267 DQ0 =102, DQ1 =108, DQ2 =100, DQ3 =102
5481 12:26:41.990754 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5482 12:26:41.993610 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5483 12:26:41.997505 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5484 12:26:41.997618
5485 12:26:41.997715
5486 12:26:42.004100 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5487 12:26:42.007356 CH0 RK1: MR19=505, MR18=2A02
5488 12:26:42.013676 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5489 12:26:42.017049 [RxdqsGatingPostProcess] freq 933
5490 12:26:42.023805 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 12:26:42.027217 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 12:26:42.027302 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 12:26:42.030767 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 12:26:42.034144 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 12:26:42.037013 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 12:26:42.040510 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 12:26:42.043965 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 12:26:42.046948 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 12:26:42.050216 Pre-setting of DQS Precalculation
5500 12:26:42.057227 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 12:26:42.057350 ==
5502 12:26:42.060640 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 12:26:42.063465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 12:26:42.063576 ==
5505 12:26:42.070173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 12:26:42.073521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5507 12:26:42.077497 [CA 0] Center 36 (6~67) winsize 62
5508 12:26:42.080847 [CA 1] Center 36 (6~67) winsize 62
5509 12:26:42.084277 [CA 2] Center 34 (4~65) winsize 62
5510 12:26:42.087798 [CA 3] Center 34 (4~65) winsize 62
5511 12:26:42.091239 [CA 4] Center 34 (4~64) winsize 61
5512 12:26:42.094731 [CA 5] Center 33 (3~64) winsize 62
5513 12:26:42.094836
5514 12:26:42.097691 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5515 12:26:42.097798
5516 12:26:42.101068 [CATrainingPosCal] consider 1 rank data
5517 12:26:42.104522 u2DelayCellTimex100 = 270/100 ps
5518 12:26:42.107248 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5519 12:26:42.114397 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 12:26:42.117164 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5521 12:26:42.120689 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5522 12:26:42.124080 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 12:26:42.127301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5524 12:26:42.127390
5525 12:26:42.130795 CA PerBit enable=1, Macro0, CA PI delay=33
5526 12:26:42.130903
5527 12:26:42.134147 [CBTSetCACLKResult] CA Dly = 33
5528 12:26:42.136987 CS Dly: 7 (0~38)
5529 12:26:42.137090 ==
5530 12:26:42.140404 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 12:26:42.143938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 12:26:42.144049 ==
5533 12:26:42.150249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 12:26:42.153632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5535 12:26:42.157851 [CA 0] Center 36 (6~67) winsize 62
5536 12:26:42.161262 [CA 1] Center 37 (7~68) winsize 62
5537 12:26:42.164663 [CA 2] Center 35 (4~66) winsize 63
5538 12:26:42.167853 [CA 3] Center 34 (4~65) winsize 62
5539 12:26:42.171227 [CA 4] Center 34 (4~65) winsize 62
5540 12:26:42.174517 [CA 5] Center 34 (4~64) winsize 61
5541 12:26:42.174622
5542 12:26:42.177957 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5543 12:26:42.178068
5544 12:26:42.181305 [CATrainingPosCal] consider 2 rank data
5545 12:26:42.184617 u2DelayCellTimex100 = 270/100 ps
5546 12:26:42.187851 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5547 12:26:42.190742 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5548 12:26:42.197665 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5549 12:26:42.201051 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5550 12:26:42.203942 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5551 12:26:42.207375 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5552 12:26:42.207486
5553 12:26:42.210997 CA PerBit enable=1, Macro0, CA PI delay=34
5554 12:26:42.211104
5555 12:26:42.213854 [CBTSetCACLKResult] CA Dly = 34
5556 12:26:42.213964 CS Dly: 8 (0~40)
5557 12:26:42.217196
5558 12:26:42.220952 ----->DramcWriteLeveling(PI) begin...
5559 12:26:42.221035 ==
5560 12:26:42.224078 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 12:26:42.227502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 12:26:42.227589 ==
5563 12:26:42.230895 Write leveling (Byte 0): 27 => 27
5564 12:26:42.234167 Write leveling (Byte 1): 27 => 27
5565 12:26:42.237450 DramcWriteLeveling(PI) end<-----
5566 12:26:42.237539
5567 12:26:42.237608 ==
5568 12:26:42.240901 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 12:26:42.243917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 12:26:42.244003 ==
5571 12:26:42.247381 [Gating] SW mode calibration
5572 12:26:42.253826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 12:26:42.260768 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 12:26:42.263767 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:26:42.267208 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 12:26:42.274020 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 12:26:42.277310 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 12:26:42.280707 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 12:26:42.283939 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5580 12:26:42.290349 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5581 12:26:42.293721 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5582 12:26:42.297289 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:26:42.304127 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 12:26:42.306915 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 12:26:42.310445 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 12:26:42.317320 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 12:26:42.320174 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 12:26:42.323446 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
5589 12:26:42.330366 0 15 28 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5590 12:26:42.333714 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:26:42.337018 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:26:42.343655 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 12:26:42.347127 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 12:26:42.349916 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 12:26:42.356896 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 12:26:42.360381 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5597 12:26:42.363790 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:26:42.370105 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:26:42.373432 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:26:42.376804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:26:42.383448 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:26:42.386792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:26:42.390187 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:26:42.396762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:26:42.400038 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:26:42.403552 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:26:42.406984 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:26:42.413923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:26:42.417272 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:26:42.420750 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:26:42.426968 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:26:42.429969 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5613 12:26:42.433361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:26:42.436784 Total UI for P1: 0, mck2ui 16
5615 12:26:42.440110 best dqsien dly found for B0: ( 1, 2, 24)
5616 12:26:42.443511 Total UI for P1: 0, mck2ui 16
5617 12:26:42.446782 best dqsien dly found for B1: ( 1, 2, 24)
5618 12:26:42.450188 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5619 12:26:42.453753 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5620 12:26:42.453871
5621 12:26:42.459990 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5622 12:26:42.463546 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5623 12:26:42.467066 [Gating] SW calibration Done
5624 12:26:42.467152 ==
5625 12:26:42.470456 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 12:26:42.473451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 12:26:42.473548 ==
5628 12:26:42.473638 RX Vref Scan: 0
5629 12:26:42.473729
5630 12:26:42.476799 RX Vref 0 -> 0, step: 1
5631 12:26:42.476868
5632 12:26:42.480343 RX Delay -80 -> 252, step: 8
5633 12:26:42.483562 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5634 12:26:42.486884 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5635 12:26:42.493719 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5636 12:26:42.496365 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5637 12:26:42.500006 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5638 12:26:42.503312 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5639 12:26:42.506460 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5640 12:26:42.509969 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5641 12:26:42.513594 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5642 12:26:42.519965 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5643 12:26:42.523448 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5644 12:26:42.526256 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5645 12:26:42.529681 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5646 12:26:42.533075 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5647 12:26:42.539775 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5648 12:26:42.543303 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5649 12:26:42.543417 ==
5650 12:26:42.546776 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 12:26:42.550050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 12:26:42.550139 ==
5653 12:26:42.552904 DQS Delay:
5654 12:26:42.552990 DQS0 = 0, DQS1 = 0
5655 12:26:42.553076 DQM Delay:
5656 12:26:42.556124 DQM0 = 102, DQM1 = 98
5657 12:26:42.556211 DQ Delay:
5658 12:26:42.559693 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5659 12:26:42.563137 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5660 12:26:42.566743 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5661 12:26:42.569475 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5662 12:26:42.569562
5663 12:26:42.573034
5664 12:26:42.573120 ==
5665 12:26:42.576615 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 12:26:42.580030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 12:26:42.580133 ==
5668 12:26:42.580220
5669 12:26:42.580301
5670 12:26:42.582816 TX Vref Scan disable
5671 12:26:42.582889 == TX Byte 0 ==
5672 12:26:42.589677 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5673 12:26:42.593027 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5674 12:26:42.593114 == TX Byte 1 ==
5675 12:26:42.599651 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 12:26:42.603038 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 12:26:42.603156 ==
5678 12:26:42.605876 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 12:26:42.609215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 12:26:42.609298 ==
5681 12:26:42.609365
5682 12:26:42.609424
5683 12:26:42.613270 TX Vref Scan disable
5684 12:26:42.616478 == TX Byte 0 ==
5685 12:26:42.619266 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5686 12:26:42.622775 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5687 12:26:42.626197 == TX Byte 1 ==
5688 12:26:42.629748 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5689 12:26:42.632477 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5690 12:26:42.632555
5691 12:26:42.635931 [DATLAT]
5692 12:26:42.636031 Freq=933, CH1 RK0
5693 12:26:42.636125
5694 12:26:42.639257 DATLAT Default: 0xd
5695 12:26:42.639390 0, 0xFFFF, sum = 0
5696 12:26:42.642816 1, 0xFFFF, sum = 0
5697 12:26:42.642891 2, 0xFFFF, sum = 0
5698 12:26:42.646218 3, 0xFFFF, sum = 0
5699 12:26:42.646292 4, 0xFFFF, sum = 0
5700 12:26:42.649646 5, 0xFFFF, sum = 0
5701 12:26:42.649741 6, 0xFFFF, sum = 0
5702 12:26:42.652379 7, 0xFFFF, sum = 0
5703 12:26:42.652455 8, 0xFFFF, sum = 0
5704 12:26:42.655770 9, 0xFFFF, sum = 0
5705 12:26:42.655844 10, 0x0, sum = 1
5706 12:26:42.659222 11, 0x0, sum = 2
5707 12:26:42.659331 12, 0x0, sum = 3
5708 12:26:42.662604 13, 0x0, sum = 4
5709 12:26:42.662706 best_step = 11
5710 12:26:42.662797
5711 12:26:42.662885 ==
5712 12:26:42.666248 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 12:26:42.669056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 12:26:42.672637 ==
5715 12:26:42.672711 RX Vref Scan: 1
5716 12:26:42.672774
5717 12:26:42.676047 RX Vref 0 -> 0, step: 1
5718 12:26:42.676146
5719 12:26:42.678908 RX Delay -45 -> 252, step: 4
5720 12:26:42.679014
5721 12:26:42.682455 Set Vref, RX VrefLevel [Byte0]: 51
5722 12:26:42.685947 [Byte1]: 49
5723 12:26:42.686047
5724 12:26:42.688824 Final RX Vref Byte 0 = 51 to rank0
5725 12:26:42.692369 Final RX Vref Byte 1 = 49 to rank0
5726 12:26:42.695717 Final RX Vref Byte 0 = 51 to rank1
5727 12:26:42.699055 Final RX Vref Byte 1 = 49 to rank1==
5728 12:26:42.702233 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 12:26:42.705493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 12:26:42.705598 ==
5731 12:26:42.708840 DQS Delay:
5732 12:26:42.708941 DQS0 = 0, DQS1 = 0
5733 12:26:42.709046 DQM Delay:
5734 12:26:42.712224 DQM0 = 103, DQM1 = 99
5735 12:26:42.712326 DQ Delay:
5736 12:26:42.715518 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =100
5737 12:26:42.719012 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5738 12:26:42.722324 DQ8 =88, DQ9 =92, DQ10 =98, DQ11 =94
5739 12:26:42.725751 DQ12 =106, DQ13 =104, DQ14 =108, DQ15 =108
5740 12:26:42.725873
5741 12:26:42.728523
5742 12:26:42.734944 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5743 12:26:42.738468 CH1 RK0: MR19=505, MR18=162E
5744 12:26:42.745245 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5745 12:26:42.745390
5746 12:26:42.748641 ----->DramcWriteLeveling(PI) begin...
5747 12:26:42.748724 ==
5748 12:26:42.751514 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 12:26:42.755211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 12:26:42.755318 ==
5751 12:26:42.758715 Write leveling (Byte 0): 27 => 27
5752 12:26:42.762030 Write leveling (Byte 1): 28 => 28
5753 12:26:42.765282 DramcWriteLeveling(PI) end<-----
5754 12:26:42.765389
5755 12:26:42.765491 ==
5756 12:26:42.768693 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 12:26:42.772008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 12:26:42.772091 ==
5759 12:26:42.774767 [Gating] SW mode calibration
5760 12:26:42.781784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5761 12:26:42.788126 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5762 12:26:42.791716 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 12:26:42.794612 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 12:26:42.801664 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 12:26:42.805082 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 12:26:42.807778 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 12:26:42.815044 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5768 12:26:42.817759 0 14 24 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 1)
5769 12:26:42.821218 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5770 12:26:42.828068 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:26:42.831367 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 12:26:42.834374 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 12:26:42.841341 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 12:26:42.844767 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 12:26:42.848036 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 12:26:42.854964 0 15 24 | B1->B0 | 3737 2e2d | 0 1 | (0 0) (0 0)
5777 12:26:42.857840 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5778 12:26:42.861340 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:26:42.867982 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 12:26:42.871292 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:26:42.874159 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 12:26:42.880990 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 12:26:42.884431 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 12:26:42.887701 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5785 12:26:42.894616 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5786 12:26:42.897396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:26:42.900915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:26:42.907762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:26:42.911313 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:26:42.914073 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:26:42.921192 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:26:42.924474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:26:42.927765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:26:42.930664 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:26:42.937635 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:26:42.940844 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:26:42.944343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:26:42.950723 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:26:42.954036 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5800 12:26:42.957415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5801 12:26:42.964316 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 12:26:42.967166 Total UI for P1: 0, mck2ui 16
5803 12:26:42.970561 best dqsien dly found for B0: ( 1, 2, 24)
5804 12:26:42.973952 Total UI for P1: 0, mck2ui 16
5805 12:26:42.977419 best dqsien dly found for B1: ( 1, 2, 22)
5806 12:26:42.980851 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5807 12:26:42.984143 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5808 12:26:42.984252
5809 12:26:42.987509 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5810 12:26:42.990792 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5811 12:26:42.993790 [Gating] SW calibration Done
5812 12:26:42.993895 ==
5813 12:26:42.997221 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 12:26:43.000748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 12:26:43.000852 ==
5816 12:26:43.004276 RX Vref Scan: 0
5817 12:26:43.004378
5818 12:26:43.004481 RX Vref 0 -> 0, step: 1
5819 12:26:43.004584
5820 12:26:43.007102 RX Delay -80 -> 252, step: 8
5821 12:26:43.014129 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5822 12:26:43.017652 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5823 12:26:43.020430 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5824 12:26:43.023728 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5825 12:26:43.026898 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5826 12:26:43.030295 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5827 12:26:43.037062 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5828 12:26:43.040332 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5829 12:26:43.043492 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5830 12:26:43.047337 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5831 12:26:43.050108 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5832 12:26:43.053533 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5833 12:26:43.060105 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5834 12:26:43.063645 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5835 12:26:43.067225 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5836 12:26:43.070033 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5837 12:26:43.070137 ==
5838 12:26:43.073567 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 12:26:43.079982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 12:26:43.080095 ==
5841 12:26:43.080204 DQS Delay:
5842 12:26:43.080307 DQS0 = 0, DQS1 = 0
5843 12:26:43.083418 DQM Delay:
5844 12:26:43.083526 DQM0 = 102, DQM1 = 98
5845 12:26:43.086742 DQ Delay:
5846 12:26:43.090188 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5847 12:26:43.093448 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5848 12:26:43.096974 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5849 12:26:43.100395 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5850 12:26:43.100499
5851 12:26:43.100602
5852 12:26:43.100702 ==
5853 12:26:43.103213 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 12:26:43.106759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 12:26:43.106866 ==
5856 12:26:43.106968
5857 12:26:43.107069
5858 12:26:43.110118 TX Vref Scan disable
5859 12:26:43.113595 == TX Byte 0 ==
5860 12:26:43.116420 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5861 12:26:43.119991 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5862 12:26:43.123414 == TX Byte 1 ==
5863 12:26:43.126940 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5864 12:26:43.129791 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5865 12:26:43.129874 ==
5866 12:26:43.133205 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 12:26:43.136559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 12:26:43.139846 ==
5869 12:26:43.139931
5870 12:26:43.139998
5871 12:26:43.140061 TX Vref Scan disable
5872 12:26:43.143279 == TX Byte 0 ==
5873 12:26:43.146507 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5874 12:26:43.153177 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5875 12:26:43.153263 == TX Byte 1 ==
5876 12:26:43.156473 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 12:26:43.162971 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 12:26:43.163056
5879 12:26:43.163123 [DATLAT]
5880 12:26:43.163186 Freq=933, CH1 RK1
5881 12:26:43.163246
5882 12:26:43.166518 DATLAT Default: 0xb
5883 12:26:43.166630 0, 0xFFFF, sum = 0
5884 12:26:43.169831 1, 0xFFFF, sum = 0
5885 12:26:43.169917 2, 0xFFFF, sum = 0
5886 12:26:43.173218 3, 0xFFFF, sum = 0
5887 12:26:43.176758 4, 0xFFFF, sum = 0
5888 12:26:43.176842 5, 0xFFFF, sum = 0
5889 12:26:43.179772 6, 0xFFFF, sum = 0
5890 12:26:43.179856 7, 0xFFFF, sum = 0
5891 12:26:43.183223 8, 0xFFFF, sum = 0
5892 12:26:43.183355 9, 0xFFFF, sum = 0
5893 12:26:43.186719 10, 0x0, sum = 1
5894 12:26:43.186803 11, 0x0, sum = 2
5895 12:26:43.190124 12, 0x0, sum = 3
5896 12:26:43.190252 13, 0x0, sum = 4
5897 12:26:43.190351 best_step = 11
5898 12:26:43.190460
5899 12:26:43.192940 ==
5900 12:26:43.196315 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 12:26:43.199819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 12:26:43.199899 ==
5903 12:26:43.199978 RX Vref Scan: 0
5904 12:26:43.200038
5905 12:26:43.202962 RX Vref 0 -> 0, step: 1
5906 12:26:43.203035
5907 12:26:43.206441 RX Delay -45 -> 252, step: 4
5908 12:26:43.209934 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5909 12:26:43.216339 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5910 12:26:43.219720 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5911 12:26:43.223151 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5912 12:26:43.226597 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5913 12:26:43.229408 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5914 12:26:43.236354 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5915 12:26:43.239788 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5916 12:26:43.243221 iDelay=199, Bit 8, Center 88 (3 ~ 174) 172
5917 12:26:43.245905 iDelay=199, Bit 9, Center 90 (3 ~ 178) 176
5918 12:26:43.249973 iDelay=199, Bit 10, Center 102 (19 ~ 186) 168
5919 12:26:43.253039 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5920 12:26:43.259771 iDelay=199, Bit 12, Center 110 (23 ~ 198) 176
5921 12:26:43.263020 iDelay=199, Bit 13, Center 104 (23 ~ 186) 164
5922 12:26:43.266231 iDelay=199, Bit 14, Center 106 (27 ~ 186) 160
5923 12:26:43.269350 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5924 12:26:43.269448 ==
5925 12:26:43.272632 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 12:26:43.279519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 12:26:43.279622 ==
5928 12:26:43.279723 DQS Delay:
5929 12:26:43.283054 DQS0 = 0, DQS1 = 0
5930 12:26:43.283137 DQM Delay:
5931 12:26:43.285917 DQM0 = 104, DQM1 = 100
5932 12:26:43.286040 DQ Delay:
5933 12:26:43.289365 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5934 12:26:43.292937 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5935 12:26:43.296177 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =92
5936 12:26:43.299490 DQ12 =110, DQ13 =104, DQ14 =106, DQ15 =108
5937 12:26:43.299591
5938 12:26:43.299672
5939 12:26:43.309388 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5940 12:26:43.309513 CH1 RK1: MR19=505, MR18=2E01
5941 12:26:43.316016 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5942 12:26:43.319447 [RxdqsGatingPostProcess] freq 933
5943 12:26:43.325683 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5944 12:26:43.329148 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 12:26:43.332634 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 12:26:43.335539 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 12:26:43.339089 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 12:26:43.339189 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 12:26:43.342468 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 12:26:43.345801 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 12:26:43.349260 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 12:26:43.352786 Pre-setting of DQS Precalculation
5953 12:26:43.358932 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5954 12:26:43.365662 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5955 12:26:43.372855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5956 12:26:43.372940
5957 12:26:43.373006
5958 12:26:43.376040 [Calibration Summary] 1866 Mbps
5959 12:26:43.376125 CH 0, Rank 0
5960 12:26:43.379222 SW Impedance : PASS
5961 12:26:43.382328 DUTY Scan : NO K
5962 12:26:43.382433 ZQ Calibration : PASS
5963 12:26:43.385663 Jitter Meter : NO K
5964 12:26:43.389217 CBT Training : PASS
5965 12:26:43.389322 Write leveling : PASS
5966 12:26:43.392689 RX DQS gating : PASS
5967 12:26:43.396187 RX DQ/DQS(RDDQC) : PASS
5968 12:26:43.396291 TX DQ/DQS : PASS
5969 12:26:43.399011 RX DATLAT : PASS
5970 12:26:43.399109 RX DQ/DQS(Engine): PASS
5971 12:26:43.402502 TX OE : NO K
5972 12:26:43.402604 All Pass.
5973 12:26:43.402706
5974 12:26:43.405849 CH 0, Rank 1
5975 12:26:43.405950 SW Impedance : PASS
5976 12:26:43.409393 DUTY Scan : NO K
5977 12:26:43.412790 ZQ Calibration : PASS
5978 12:26:43.412866 Jitter Meter : NO K
5979 12:26:43.416148 CBT Training : PASS
5980 12:26:43.419417 Write leveling : PASS
5981 12:26:43.419494 RX DQS gating : PASS
5982 12:26:43.422742 RX DQ/DQS(RDDQC) : PASS
5983 12:26:43.426111 TX DQ/DQS : PASS
5984 12:26:43.426214 RX DATLAT : PASS
5985 12:26:43.428954 RX DQ/DQS(Engine): PASS
5986 12:26:43.432379 TX OE : NO K
5987 12:26:43.432541 All Pass.
5988 12:26:43.432642
5989 12:26:43.432787 CH 1, Rank 0
5990 12:26:43.435779 SW Impedance : PASS
5991 12:26:43.439256 DUTY Scan : NO K
5992 12:26:43.439382 ZQ Calibration : PASS
5993 12:26:43.442192 Jitter Meter : NO K
5994 12:26:43.445736 CBT Training : PASS
5995 12:26:43.445859 Write leveling : PASS
5996 12:26:43.449211 RX DQS gating : PASS
5997 12:26:43.449328 RX DQ/DQS(RDDQC) : PASS
5998 12:26:43.452614 TX DQ/DQS : PASS
5999 12:26:43.455473 RX DATLAT : PASS
6000 12:26:43.455566 RX DQ/DQS(Engine): PASS
6001 12:26:43.458993 TX OE : NO K
6002 12:26:43.459084 All Pass.
6003 12:26:43.459153
6004 12:26:43.462328 CH 1, Rank 1
6005 12:26:43.462419 SW Impedance : PASS
6006 12:26:43.465811 DUTY Scan : NO K
6007 12:26:43.469160 ZQ Calibration : PASS
6008 12:26:43.469279 Jitter Meter : NO K
6009 12:26:43.472499 CBT Training : PASS
6010 12:26:43.475650 Write leveling : PASS
6011 12:26:43.475758 RX DQS gating : PASS
6012 12:26:43.479101 RX DQ/DQS(RDDQC) : PASS
6013 12:26:43.482481 TX DQ/DQS : PASS
6014 12:26:43.482588 RX DATLAT : PASS
6015 12:26:43.485817 RX DQ/DQS(Engine): PASS
6016 12:26:43.489022 TX OE : NO K
6017 12:26:43.489105 All Pass.
6018 12:26:43.489182
6019 12:26:43.489245 DramC Write-DBI off
6020 12:26:43.492281 PER_BANK_REFRESH: Hybrid Mode
6021 12:26:43.495730 TX_TRACKING: ON
6022 12:26:43.501983 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6023 12:26:43.505473 [FAST_K] Save calibration result to emmc
6024 12:26:43.512252 dramc_set_vcore_voltage set vcore to 650000
6025 12:26:43.512348 Read voltage for 400, 6
6026 12:26:43.515038 Vio18 = 0
6027 12:26:43.515143 Vcore = 650000
6028 12:26:43.515249 Vdram = 0
6029 12:26:43.518549 Vddq = 0
6030 12:26:43.518643 Vmddr = 0
6031 12:26:43.521832 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6032 12:26:43.528807 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6033 12:26:43.531990 MEM_TYPE=3, freq_sel=20
6034 12:26:43.532099 sv_algorithm_assistance_LP4_800
6035 12:26:43.538325 ============ PULL DRAM RESETB DOWN ============
6036 12:26:43.541824 ========== PULL DRAM RESETB DOWN end =========
6037 12:26:43.545254 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6038 12:26:43.548765 ===================================
6039 12:26:43.552333 LPDDR4 DRAM CONFIGURATION
6040 12:26:43.554936 ===================================
6041 12:26:43.558326 EX_ROW_EN[0] = 0x0
6042 12:26:43.558440 EX_ROW_EN[1] = 0x0
6043 12:26:43.561760 LP4Y_EN = 0x0
6044 12:26:43.561866 WORK_FSP = 0x0
6045 12:26:43.565236 WL = 0x2
6046 12:26:43.565349 RL = 0x2
6047 12:26:43.568658 BL = 0x2
6048 12:26:43.568739 RPST = 0x0
6049 12:26:43.572025 RD_PRE = 0x0
6050 12:26:43.572102 WR_PRE = 0x1
6051 12:26:43.575411 WR_PST = 0x0
6052 12:26:43.575485 DBI_WR = 0x0
6053 12:26:43.578716 DBI_RD = 0x0
6054 12:26:43.578823 OTF = 0x1
6055 12:26:43.581474 ===================================
6056 12:26:43.585362 ===================================
6057 12:26:43.588699 ANA top config
6058 12:26:43.592065 ===================================
6059 12:26:43.595230 DLL_ASYNC_EN = 0
6060 12:26:43.595345 ALL_SLAVE_EN = 1
6061 12:26:43.598530 NEW_RANK_MODE = 1
6062 12:26:43.601907 DLL_IDLE_MODE = 1
6063 12:26:43.604871 LP45_APHY_COMB_EN = 1
6064 12:26:43.608229 TX_ODT_DIS = 1
6065 12:26:43.608304 NEW_8X_MODE = 1
6066 12:26:43.611700 ===================================
6067 12:26:43.615139 ===================================
6068 12:26:43.618324 data_rate = 800
6069 12:26:43.621700 CKR = 1
6070 12:26:43.625066 DQ_P2S_RATIO = 4
6071 12:26:43.628422 ===================================
6072 12:26:43.631252 CA_P2S_RATIO = 4
6073 12:26:43.634732 DQ_CA_OPEN = 0
6074 12:26:43.634814 DQ_SEMI_OPEN = 1
6075 12:26:43.637925 CA_SEMI_OPEN = 1
6076 12:26:43.641517 CA_FULL_RATE = 0
6077 12:26:43.645073 DQ_CKDIV4_EN = 0
6078 12:26:43.647843 CA_CKDIV4_EN = 1
6079 12:26:43.651314 CA_PREDIV_EN = 0
6080 12:26:43.651403 PH8_DLY = 0
6081 12:26:43.654852 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6082 12:26:43.658228 DQ_AAMCK_DIV = 0
6083 12:26:43.661744 CA_AAMCK_DIV = 0
6084 12:26:43.664533 CA_ADMCK_DIV = 4
6085 12:26:43.664609 DQ_TRACK_CA_EN = 0
6086 12:26:43.668108 CA_PICK = 800
6087 12:26:43.671570 CA_MCKIO = 400
6088 12:26:43.675121 MCKIO_SEMI = 400
6089 12:26:43.678320 PLL_FREQ = 3016
6090 12:26:43.681693 DQ_UI_PI_RATIO = 32
6091 12:26:43.684453 CA_UI_PI_RATIO = 32
6092 12:26:43.687913 ===================================
6093 12:26:43.691171 ===================================
6094 12:26:43.691277 memory_type:LPDDR4
6095 12:26:43.694506 GP_NUM : 10
6096 12:26:43.697797 SRAM_EN : 1
6097 12:26:43.697905 MD32_EN : 0
6098 12:26:43.701118 ===================================
6099 12:26:43.705090 [ANA_INIT] >>>>>>>>>>>>>>
6100 12:26:43.708395 <<<<<< [CONFIGURE PHASE]: ANA_TX
6101 12:26:43.711248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6102 12:26:43.714760 ===================================
6103 12:26:43.718254 data_rate = 800,PCW = 0X7400
6104 12:26:43.721138 ===================================
6105 12:26:43.724953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6106 12:26:43.728202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 12:26:43.740996 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 12:26:43.744845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6109 12:26:43.747594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6110 12:26:43.751107 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6111 12:26:43.754632 [ANA_INIT] flow start
6112 12:26:43.758185 [ANA_INIT] PLL >>>>>>>>
6113 12:26:43.758294 [ANA_INIT] PLL <<<<<<<<
6114 12:26:43.760974 [ANA_INIT] MIDPI >>>>>>>>
6115 12:26:43.764356 [ANA_INIT] MIDPI <<<<<<<<
6116 12:26:43.764477 [ANA_INIT] DLL >>>>>>>>
6117 12:26:43.767739 [ANA_INIT] flow end
6118 12:26:43.771203 ============ LP4 DIFF to SE enter ============
6119 12:26:43.774730 ============ LP4 DIFF to SE exit ============
6120 12:26:43.777473 [ANA_INIT] <<<<<<<<<<<<<
6121 12:26:43.781381 [Flow] Enable top DCM control >>>>>
6122 12:26:43.784853 [Flow] Enable top DCM control <<<<<
6123 12:26:43.787636 Enable DLL master slave shuffle
6124 12:26:43.794629 ==============================================================
6125 12:26:43.794716 Gating Mode config
6126 12:26:43.801309 ==============================================================
6127 12:26:43.801389 Config description:
6128 12:26:43.811104 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6129 12:26:43.817364 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6130 12:26:43.824372 SELPH_MODE 0: By rank 1: By Phase
6131 12:26:43.827746 ==============================================================
6132 12:26:43.831200 GAT_TRACK_EN = 0
6133 12:26:43.834444 RX_GATING_MODE = 2
6134 12:26:43.837843 RX_GATING_TRACK_MODE = 2
6135 12:26:43.841230 SELPH_MODE = 1
6136 12:26:43.843975 PICG_EARLY_EN = 1
6137 12:26:43.847475 VALID_LAT_VALUE = 1
6138 12:26:43.854176 ==============================================================
6139 12:26:43.857775 Enter into Gating configuration >>>>
6140 12:26:43.860574 Exit from Gating configuration <<<<
6141 12:26:43.860661 Enter into DVFS_PRE_config >>>>>
6142 12:26:43.874220 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6143 12:26:43.876931 Exit from DVFS_PRE_config <<<<<
6144 12:26:43.880444 Enter into PICG configuration >>>>
6145 12:26:43.883953 Exit from PICG configuration <<<<
6146 12:26:43.884046 [RX_INPUT] configuration >>>>>
6147 12:26:43.887322 [RX_INPUT] configuration <<<<<
6148 12:26:43.894237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6149 12:26:43.897087 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6150 12:26:43.904074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 12:26:43.910766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 12:26:43.917090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 12:26:43.923571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 12:26:43.927016 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6155 12:26:43.930547 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6156 12:26:43.936785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6157 12:26:43.940197 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6158 12:26:43.943999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6159 12:26:43.947235 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 12:26:43.950736 ===================================
6161 12:26:43.953469 LPDDR4 DRAM CONFIGURATION
6162 12:26:43.956857 ===================================
6163 12:26:43.960333 EX_ROW_EN[0] = 0x0
6164 12:26:43.960431 EX_ROW_EN[1] = 0x0
6165 12:26:43.963919 LP4Y_EN = 0x0
6166 12:26:43.964024 WORK_FSP = 0x0
6167 12:26:43.967250 WL = 0x2
6168 12:26:43.967364 RL = 0x2
6169 12:26:43.970094 BL = 0x2
6170 12:26:43.970204 RPST = 0x0
6171 12:26:43.973551 RD_PRE = 0x0
6172 12:26:43.973668 WR_PRE = 0x1
6173 12:26:43.977058 WR_PST = 0x0
6174 12:26:43.980541 DBI_WR = 0x0
6175 12:26:43.980639 DBI_RD = 0x0
6176 12:26:43.983406 OTF = 0x1
6177 12:26:43.986919 ===================================
6178 12:26:43.990395 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6179 12:26:43.993672 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6180 12:26:43.997073 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 12:26:43.999889 ===================================
6182 12:26:44.003439 LPDDR4 DRAM CONFIGURATION
6183 12:26:44.006940 ===================================
6184 12:26:44.009819 EX_ROW_EN[0] = 0x10
6185 12:26:44.009901 EX_ROW_EN[1] = 0x0
6186 12:26:44.013332 LP4Y_EN = 0x0
6187 12:26:44.013446 WORK_FSP = 0x0
6188 12:26:44.016526 WL = 0x2
6189 12:26:44.016608 RL = 0x2
6190 12:26:44.020015 BL = 0x2
6191 12:26:44.020097 RPST = 0x0
6192 12:26:44.023258 RD_PRE = 0x0
6193 12:26:44.023388 WR_PRE = 0x1
6194 12:26:44.026666 WR_PST = 0x0
6195 12:26:44.026748 DBI_WR = 0x0
6196 12:26:44.029940 DBI_RD = 0x0
6197 12:26:44.033317 OTF = 0x1
6198 12:26:44.033399 ===================================
6199 12:26:44.039672 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6200 12:26:44.045237 nWR fixed to 30
6201 12:26:44.048682 [ModeRegInit_LP4] CH0 RK0
6202 12:26:44.048812 [ModeRegInit_LP4] CH0 RK1
6203 12:26:44.051848 [ModeRegInit_LP4] CH1 RK0
6204 12:26:44.055340 [ModeRegInit_LP4] CH1 RK1
6205 12:26:44.055425 match AC timing 19
6206 12:26:44.061692 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6207 12:26:44.065111 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6208 12:26:44.068667 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6209 12:26:44.074901 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6210 12:26:44.078305 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6211 12:26:44.078431 ==
6212 12:26:44.081811 Dram Type= 6, Freq= 0, CH_0, rank 0
6213 12:26:44.084617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 12:26:44.084749 ==
6215 12:26:44.091697 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 12:26:44.098293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6217 12:26:44.101720 [CA 0] Center 36 (8~64) winsize 57
6218 12:26:44.104665 [CA 1] Center 36 (8~64) winsize 57
6219 12:26:44.104788 [CA 2] Center 36 (8~64) winsize 57
6220 12:26:44.108150 [CA 3] Center 36 (8~64) winsize 57
6221 12:26:44.111829 [CA 4] Center 36 (8~64) winsize 57
6222 12:26:44.115246 [CA 5] Center 36 (8~64) winsize 57
6223 12:26:44.115358
6224 12:26:44.118604 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6225 12:26:44.118686
6226 12:26:44.124895 [CATrainingPosCal] consider 1 rank data
6227 12:26:44.125004 u2DelayCellTimex100 = 270/100 ps
6228 12:26:44.128116 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 12:26:44.134755 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:26:44.138099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:26:44.141338 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:26:44.144784 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:26:44.148297 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:26:44.148416
6235 12:26:44.151732 CA PerBit enable=1, Macro0, CA PI delay=36
6236 12:26:44.151848
6237 12:26:44.155211 [CBTSetCACLKResult] CA Dly = 36
6238 12:26:44.158370 CS Dly: 1 (0~32)
6239 12:26:44.158462 ==
6240 12:26:44.161868 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 12:26:44.164614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 12:26:44.164733 ==
6243 12:26:44.171264 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 12:26:44.174855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6245 12:26:44.178259 [CA 0] Center 36 (8~64) winsize 57
6246 12:26:44.181109 [CA 1] Center 36 (8~64) winsize 57
6247 12:26:44.184600 [CA 2] Center 36 (8~64) winsize 57
6248 12:26:44.188035 [CA 3] Center 36 (8~64) winsize 57
6249 12:26:44.191388 [CA 4] Center 36 (8~64) winsize 57
6250 12:26:44.195006 [CA 5] Center 36 (8~64) winsize 57
6251 12:26:44.195121
6252 12:26:44.197809 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6253 12:26:44.197915
6254 12:26:44.201206 [CATrainingPosCal] consider 2 rank data
6255 12:26:44.204675 u2DelayCellTimex100 = 270/100 ps
6256 12:26:44.208143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:26:44.211711 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:26:44.214469 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:26:44.217941 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:26:44.224276 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:26:44.227884 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 12:26:44.227998
6263 12:26:44.231402 CA PerBit enable=1, Macro0, CA PI delay=36
6264 12:26:44.231516
6265 12:26:44.234518 [CBTSetCACLKResult] CA Dly = 36
6266 12:26:44.234623 CS Dly: 1 (0~32)
6267 12:26:44.234719
6268 12:26:44.237982 ----->DramcWriteLeveling(PI) begin...
6269 12:26:44.238094 ==
6270 12:26:44.241368 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 12:26:44.248032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 12:26:44.248145 ==
6273 12:26:44.251574 Write leveling (Byte 0): 40 => 8
6274 12:26:44.251654 Write leveling (Byte 1): 40 => 8
6275 12:26:44.254330 DramcWriteLeveling(PI) end<-----
6276 12:26:44.254434
6277 12:26:44.254501 ==
6278 12:26:44.257893 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 12:26:44.264553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 12:26:44.264665 ==
6281 12:26:44.267869 [Gating] SW mode calibration
6282 12:26:44.274647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6283 12:26:44.277962 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6284 12:26:44.284616 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 12:26:44.287942 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 12:26:44.291351 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 12:26:44.297710 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 12:26:44.301244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 12:26:44.304140 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 12:26:44.311049 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 12:26:44.314660 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 12:26:44.317314 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 12:26:44.320657 Total UI for P1: 0, mck2ui 16
6294 12:26:44.324255 best dqsien dly found for B0: ( 0, 14, 24)
6295 12:26:44.327697 Total UI for P1: 0, mck2ui 16
6296 12:26:44.331213 best dqsien dly found for B1: ( 0, 14, 24)
6297 12:26:44.333985 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6298 12:26:44.337453 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6299 12:26:44.337561
6300 12:26:44.340916 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 12:26:44.347638 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 12:26:44.347724 [Gating] SW calibration Done
6303 12:26:44.347792 ==
6304 12:26:44.350870 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 12:26:44.357527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 12:26:44.357646 ==
6307 12:26:44.357745 RX Vref Scan: 0
6308 12:26:44.357841
6309 12:26:44.360995 RX Vref 0 -> 0, step: 1
6310 12:26:44.361102
6311 12:26:44.364675 RX Delay -410 -> 252, step: 16
6312 12:26:44.367333 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6313 12:26:44.370880 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6314 12:26:44.377745 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6315 12:26:44.381247 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6316 12:26:44.384666 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6317 12:26:44.387837 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6318 12:26:44.391159 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6319 12:26:44.397551 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6320 12:26:44.400952 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6321 12:26:44.404462 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6322 12:26:44.407334 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6323 12:26:44.414280 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6324 12:26:44.417792 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6325 12:26:44.421247 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6326 12:26:44.427448 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6327 12:26:44.430895 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6328 12:26:44.430988 ==
6329 12:26:44.433756 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 12:26:44.437254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 12:26:44.437332 ==
6332 12:26:44.440530 DQS Delay:
6333 12:26:44.440610 DQS0 = 27, DQS1 = 35
6334 12:26:44.444072 DQM Delay:
6335 12:26:44.444172 DQM0 = 11, DQM1 = 11
6336 12:26:44.444264 DQ Delay:
6337 12:26:44.447422 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6338 12:26:44.450881 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6339 12:26:44.453650 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6340 12:26:44.457507 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6341 12:26:44.457617
6342 12:26:44.457683
6343 12:26:44.457743 ==
6344 12:26:44.460809 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 12:26:44.463841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 12:26:44.467206 ==
6347 12:26:44.467288
6348 12:26:44.467364
6349 12:26:44.467426 TX Vref Scan disable
6350 12:26:44.470716 == TX Byte 0 ==
6351 12:26:44.474091 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 12:26:44.477462 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 12:26:44.480694 == TX Byte 1 ==
6354 12:26:44.483984 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 12:26:44.487464 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 12:26:44.487553 ==
6357 12:26:44.490208 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 12:26:44.497271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 12:26:44.497392 ==
6360 12:26:44.497491
6361 12:26:44.497594
6362 12:26:44.497686 TX Vref Scan disable
6363 12:26:44.500618 == TX Byte 0 ==
6364 12:26:44.504087 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 12:26:44.506985 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 12:26:44.510367 == TX Byte 1 ==
6367 12:26:44.513171 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 12:26:44.516484 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 12:26:44.516564
6370 12:26:44.519873 [DATLAT]
6371 12:26:44.519945 Freq=400, CH0 RK0
6372 12:26:44.520009
6373 12:26:44.523466 DATLAT Default: 0xf
6374 12:26:44.523571 0, 0xFFFF, sum = 0
6375 12:26:44.526940 1, 0xFFFF, sum = 0
6376 12:26:44.527017 2, 0xFFFF, sum = 0
6377 12:26:44.529855 3, 0xFFFF, sum = 0
6378 12:26:44.529930 4, 0xFFFF, sum = 0
6379 12:26:44.533346 5, 0xFFFF, sum = 0
6380 12:26:44.533425 6, 0xFFFF, sum = 0
6381 12:26:44.536806 7, 0xFFFF, sum = 0
6382 12:26:44.536887 8, 0xFFFF, sum = 0
6383 12:26:44.540300 9, 0xFFFF, sum = 0
6384 12:26:44.540375 10, 0xFFFF, sum = 0
6385 12:26:44.543151 11, 0xFFFF, sum = 0
6386 12:26:44.546629 12, 0xFFFF, sum = 0
6387 12:26:44.546701 13, 0x0, sum = 1
6388 12:26:44.546764 14, 0x0, sum = 2
6389 12:26:44.550053 15, 0x0, sum = 3
6390 12:26:44.550129 16, 0x0, sum = 4
6391 12:26:44.553522 best_step = 14
6392 12:26:44.553599
6393 12:26:44.553663 ==
6394 12:26:44.556889 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 12:26:44.560184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 12:26:44.560262 ==
6397 12:26:44.563432 RX Vref Scan: 1
6398 12:26:44.563550
6399 12:26:44.563661 RX Vref 0 -> 0, step: 1
6400 12:26:44.563759
6401 12:26:44.566804 RX Delay -311 -> 252, step: 8
6402 12:26:44.566912
6403 12:26:44.569653 Set Vref, RX VrefLevel [Byte0]: 55
6404 12:26:44.573306 [Byte1]: 48
6405 12:26:44.578192
6406 12:26:44.578296 Final RX Vref Byte 0 = 55 to rank0
6407 12:26:44.581645 Final RX Vref Byte 1 = 48 to rank0
6408 12:26:44.584896 Final RX Vref Byte 0 = 55 to rank1
6409 12:26:44.588146 Final RX Vref Byte 1 = 48 to rank1==
6410 12:26:44.591467 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 12:26:44.598079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 12:26:44.598191 ==
6413 12:26:44.598287 DQS Delay:
6414 12:26:44.601422 DQS0 = 28, DQS1 = 36
6415 12:26:44.601532 DQM Delay:
6416 12:26:44.601632 DQM0 = 11, DQM1 = 12
6417 12:26:44.604749 DQ Delay:
6418 12:26:44.607999 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6419 12:26:44.608103 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6420 12:26:44.611169 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6421 12:26:44.614665 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6422 12:26:44.614781
6423 12:26:44.618137
6424 12:26:44.624437 [DQSOSCAuto] RK0, (LSB)MR18= 0xceba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6425 12:26:44.627742 CH0 RK0: MR19=C0C, MR18=CEBA
6426 12:26:44.634875 CH0_RK0: MR19=0xC0C, MR18=0xCEBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6427 12:26:44.634984 ==
6428 12:26:44.637705 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 12:26:44.641101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 12:26:44.641214 ==
6431 12:26:44.644601 [Gating] SW mode calibration
6432 12:26:44.651012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 12:26:44.657725 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6434 12:26:44.661178 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 12:26:44.664507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 12:26:44.671140 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 12:26:44.674525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 12:26:44.677988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 12:26:44.680807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 12:26:44.687642 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 12:26:44.691132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 12:26:44.694638 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 12:26:44.697920 Total UI for P1: 0, mck2ui 16
6444 12:26:44.701064 best dqsien dly found for B0: ( 0, 14, 24)
6445 12:26:44.704253 Total UI for P1: 0, mck2ui 16
6446 12:26:44.707703 best dqsien dly found for B1: ( 0, 14, 24)
6447 12:26:44.711056 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6448 12:26:44.717317 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6449 12:26:44.717429
6450 12:26:44.720504 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 12:26:44.724116 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 12:26:44.727685 [Gating] SW calibration Done
6453 12:26:44.727792 ==
6454 12:26:44.731107 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 12:26:44.733958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 12:26:44.734068 ==
6457 12:26:44.734168 RX Vref Scan: 0
6458 12:26:44.737447
6459 12:26:44.737551 RX Vref 0 -> 0, step: 1
6460 12:26:44.737654
6461 12:26:44.740902 RX Delay -410 -> 252, step: 16
6462 12:26:44.744429 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6463 12:26:44.750812 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6464 12:26:44.754307 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6465 12:26:44.757171 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6466 12:26:44.760739 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6467 12:26:44.767681 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6468 12:26:44.771095 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6469 12:26:44.774471 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6470 12:26:44.777225 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6471 12:26:44.780476 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6472 12:26:44.787618 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6473 12:26:44.791122 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6474 12:26:44.793828 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6475 12:26:44.800710 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6476 12:26:44.804056 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6477 12:26:44.807481 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6478 12:26:44.807594 ==
6479 12:26:44.810835 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 12:26:44.814038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 12:26:44.817339 ==
6482 12:26:44.817422 DQS Delay:
6483 12:26:44.817488 DQS0 = 19, DQS1 = 35
6484 12:26:44.820721 DQM Delay:
6485 12:26:44.820820 DQM0 = 6, DQM1 = 11
6486 12:26:44.823942 DQ Delay:
6487 12:26:44.824040 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6488 12:26:44.827173 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6489 12:26:44.830558 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6490 12:26:44.833930 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6491 12:26:44.834030
6492 12:26:44.834127
6493 12:26:44.834220 ==
6494 12:26:44.837349 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 12:26:44.843841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 12:26:44.843925 ==
6497 12:26:44.844028
6498 12:26:44.844119
6499 12:26:44.844196 TX Vref Scan disable
6500 12:26:44.847487 == TX Byte 0 ==
6501 12:26:44.850912 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6502 12:26:44.853656 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6503 12:26:44.857180 == TX Byte 1 ==
6504 12:26:44.860785 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6505 12:26:44.864233 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6506 12:26:44.864330 ==
6507 12:26:44.867098 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 12:26:44.873999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 12:26:44.874139 ==
6510 12:26:44.874265
6511 12:26:44.874385
6512 12:26:44.874507 TX Vref Scan disable
6513 12:26:44.877381 == TX Byte 0 ==
6514 12:26:44.880709 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6515 12:26:44.884008 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6516 12:26:44.887175 == TX Byte 1 ==
6517 12:26:44.890332 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6518 12:26:44.893888 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6519 12:26:44.893982
6520 12:26:44.896785 [DATLAT]
6521 12:26:44.896883 Freq=400, CH0 RK1
6522 12:26:44.896978
6523 12:26:44.900373 DATLAT Default: 0xe
6524 12:26:44.900479 0, 0xFFFF, sum = 0
6525 12:26:44.903879 1, 0xFFFF, sum = 0
6526 12:26:44.903970 2, 0xFFFF, sum = 0
6527 12:26:44.906697 3, 0xFFFF, sum = 0
6528 12:26:44.906775 4, 0xFFFF, sum = 0
6529 12:26:44.910099 5, 0xFFFF, sum = 0
6530 12:26:44.910207 6, 0xFFFF, sum = 0
6531 12:26:44.913592 7, 0xFFFF, sum = 0
6532 12:26:44.916934 8, 0xFFFF, sum = 0
6533 12:26:44.917057 9, 0xFFFF, sum = 0
6534 12:26:44.920378 10, 0xFFFF, sum = 0
6535 12:26:44.920502 11, 0xFFFF, sum = 0
6536 12:26:44.923508 12, 0xFFFF, sum = 0
6537 12:26:44.923634 13, 0x0, sum = 1
6538 12:26:44.926692 14, 0x0, sum = 2
6539 12:26:44.926800 15, 0x0, sum = 3
6540 12:26:44.930100 16, 0x0, sum = 4
6541 12:26:44.930210 best_step = 14
6542 12:26:44.930312
6543 12:26:44.930402 ==
6544 12:26:44.933375 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 12:26:44.936617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 12:26:44.936727 ==
6547 12:26:44.940366 RX Vref Scan: 0
6548 12:26:44.940483
6549 12:26:44.943822 RX Vref 0 -> 0, step: 1
6550 12:26:44.943946
6551 12:26:44.944042 RX Delay -311 -> 252, step: 8
6552 12:26:44.952193 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6553 12:26:44.955557 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6554 12:26:44.958997 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6555 12:26:44.961979 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6556 12:26:44.969040 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6557 12:26:44.971771 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6558 12:26:44.975358 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6559 12:26:44.978995 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6560 12:26:44.985115 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6561 12:26:44.988409 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6562 12:26:44.992329 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6563 12:26:44.995641 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6564 12:26:45.001873 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6565 12:26:45.005003 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6566 12:26:45.008485 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6567 12:26:45.015328 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6568 12:26:45.015420 ==
6569 12:26:45.018828 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 12:26:45.021637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 12:26:45.021714 ==
6572 12:26:45.021779 DQS Delay:
6573 12:26:45.024867 DQS0 = 24, DQS1 = 32
6574 12:26:45.024952 DQM Delay:
6575 12:26:45.028297 DQM0 = 8, DQM1 = 10
6576 12:26:45.028382 DQ Delay:
6577 12:26:45.031655 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6578 12:26:45.035064 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6579 12:26:45.038674 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6580 12:26:45.042068 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6581 12:26:45.042156
6582 12:26:45.042225
6583 12:26:45.048612 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6584 12:26:45.051950 CH0 RK1: MR19=C0C, MR18=B959
6585 12:26:45.058722 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6586 12:26:45.062024 [RxdqsGatingPostProcess] freq 400
6587 12:26:45.064822 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6588 12:26:45.068337 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 12:26:45.071898 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 12:26:45.074719 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 12:26:45.078263 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 12:26:45.081675 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 12:26:45.085159 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 12:26:45.087889 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 12:26:45.091283 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 12:26:45.094730 Pre-setting of DQS Precalculation
6597 12:26:45.098268 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6598 12:26:45.101382 ==
6599 12:26:45.101491 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 12:26:45.108113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 12:26:45.108219 ==
6602 12:26:45.111518 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 12:26:45.117790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6604 12:26:45.121404 [CA 0] Center 36 (8~64) winsize 57
6605 12:26:45.124858 [CA 1] Center 36 (8~64) winsize 57
6606 12:26:45.128382 [CA 2] Center 36 (8~64) winsize 57
6607 12:26:45.131021 [CA 3] Center 36 (8~64) winsize 57
6608 12:26:45.134468 [CA 4] Center 36 (8~64) winsize 57
6609 12:26:45.137792 [CA 5] Center 36 (8~64) winsize 57
6610 12:26:45.137904
6611 12:26:45.141193 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6612 12:26:45.141298
6613 12:26:45.144929 [CATrainingPosCal] consider 1 rank data
6614 12:26:45.147783 u2DelayCellTimex100 = 270/100 ps
6615 12:26:45.151255 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 12:26:45.154729 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:26:45.157993 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:26:45.161349 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:26:45.164621 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:26:45.171492 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:26:45.171606
6622 12:26:45.174403 CA PerBit enable=1, Macro0, CA PI delay=36
6623 12:26:45.174506
6624 12:26:45.177912 [CBTSetCACLKResult] CA Dly = 36
6625 12:26:45.178018 CS Dly: 1 (0~32)
6626 12:26:45.178113 ==
6627 12:26:45.181389 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 12:26:45.184154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 12:26:45.187707 ==
6630 12:26:45.191127 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 12:26:45.197841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6632 12:26:45.201144 [CA 0] Center 36 (8~64) winsize 57
6633 12:26:45.204510 [CA 1] Center 36 (8~64) winsize 57
6634 12:26:45.207756 [CA 2] Center 36 (8~64) winsize 57
6635 12:26:45.211083 [CA 3] Center 36 (8~64) winsize 57
6636 12:26:45.214636 [CA 4] Center 36 (8~64) winsize 57
6637 12:26:45.217370 [CA 5] Center 36 (8~64) winsize 57
6638 12:26:45.217455
6639 12:26:45.220876 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6640 12:26:45.220992
6641 12:26:45.224252 [CATrainingPosCal] consider 2 rank data
6642 12:26:45.227823 u2DelayCellTimex100 = 270/100 ps
6643 12:26:45.231115 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:26:45.233882 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:26:45.237408 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:26:45.240839 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:26:45.244245 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:26:45.247441 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 12:26:45.247553
6650 12:26:45.250568 CA PerBit enable=1, Macro0, CA PI delay=36
6651 12:26:45.253855
6652 12:26:45.253966 [CBTSetCACLKResult] CA Dly = 36
6653 12:26:45.257343 CS Dly: 1 (0~32)
6654 12:26:45.257454
6655 12:26:45.260928 ----->DramcWriteLeveling(PI) begin...
6656 12:26:45.261041 ==
6657 12:26:45.264313 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 12:26:45.267745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 12:26:45.267862 ==
6660 12:26:45.270897 Write leveling (Byte 0): 40 => 8
6661 12:26:45.274396 Write leveling (Byte 1): 40 => 8
6662 12:26:45.277317 DramcWriteLeveling(PI) end<-----
6663 12:26:45.277429
6664 12:26:45.277526 ==
6665 12:26:45.280764 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 12:26:45.284212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 12:26:45.284312 ==
6668 12:26:45.287672 [Gating] SW mode calibration
6669 12:26:45.293828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6670 12:26:45.300680 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6671 12:26:45.304193 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 12:26:45.310799 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 12:26:45.314106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 12:26:45.317381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 12:26:45.323779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 12:26:45.327378 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 12:26:45.330719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 12:26:45.337105 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 12:26:45.340596 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 12:26:45.343432 Total UI for P1: 0, mck2ui 16
6681 12:26:45.346971 best dqsien dly found for B0: ( 0, 14, 24)
6682 12:26:45.350539 Total UI for P1: 0, mck2ui 16
6683 12:26:45.353379 best dqsien dly found for B1: ( 0, 14, 24)
6684 12:26:45.356708 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6685 12:26:45.359852 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6686 12:26:45.359947
6687 12:26:45.363806 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 12:26:45.367178 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 12:26:45.370667 [Gating] SW calibration Done
6690 12:26:45.370750 ==
6691 12:26:45.373243 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 12:26:45.377114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 12:26:45.377197 ==
6694 12:26:45.379846 RX Vref Scan: 0
6695 12:26:45.379937
6696 12:26:45.383218 RX Vref 0 -> 0, step: 1
6697 12:26:45.383334
6698 12:26:45.386782 RX Delay -410 -> 252, step: 16
6699 12:26:45.390331 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6700 12:26:45.393221 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6701 12:26:45.396684 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6702 12:26:45.402902 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6703 12:26:45.406519 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6704 12:26:45.410051 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6705 12:26:45.413382 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6706 12:26:45.419988 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6707 12:26:45.423182 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6708 12:26:45.426445 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6709 12:26:45.429861 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6710 12:26:45.436150 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6711 12:26:45.439711 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6712 12:26:45.443194 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6713 12:26:45.446718 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6714 12:26:45.452891 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6715 12:26:45.452988 ==
6716 12:26:45.456565 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 12:26:45.460119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 12:26:45.460207 ==
6719 12:26:45.460277 DQS Delay:
6720 12:26:45.462836 DQS0 = 35, DQS1 = 35
6721 12:26:45.462923 DQM Delay:
6722 12:26:45.466122 DQM0 = 18, DQM1 = 13
6723 12:26:45.466207 DQ Delay:
6724 12:26:45.469590 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6725 12:26:45.473263 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6726 12:26:45.476508 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6727 12:26:45.479770 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6728 12:26:45.479849
6729 12:26:45.479913
6730 12:26:45.479974 ==
6731 12:26:45.482990 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 12:26:45.486401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 12:26:45.486488 ==
6734 12:26:45.489718
6735 12:26:45.489803
6736 12:26:45.489870 TX Vref Scan disable
6737 12:26:45.492561 == TX Byte 0 ==
6738 12:26:45.496064 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 12:26:45.499588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 12:26:45.503110 == TX Byte 1 ==
6741 12:26:45.505878 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 12:26:45.509335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 12:26:45.509429 ==
6744 12:26:45.512885 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 12:26:45.515721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 12:26:45.519146 ==
6747 12:26:45.519231
6748 12:26:45.519299
6749 12:26:45.519372 TX Vref Scan disable
6750 12:26:45.522682 == TX Byte 0 ==
6751 12:26:45.526063 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 12:26:45.529356 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 12:26:45.532759 == TX Byte 1 ==
6754 12:26:45.536093 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 12:26:45.538976 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 12:26:45.539061
6757 12:26:45.542477 [DATLAT]
6758 12:26:45.542561 Freq=400, CH1 RK0
6759 12:26:45.542628
6760 12:26:45.545873 DATLAT Default: 0xf
6761 12:26:45.545957 0, 0xFFFF, sum = 0
6762 12:26:45.549340 1, 0xFFFF, sum = 0
6763 12:26:45.549427 2, 0xFFFF, sum = 0
6764 12:26:45.552790 3, 0xFFFF, sum = 0
6765 12:26:45.552887 4, 0xFFFF, sum = 0
6766 12:26:45.555671 5, 0xFFFF, sum = 0
6767 12:26:45.555757 6, 0xFFFF, sum = 0
6768 12:26:45.559138 7, 0xFFFF, sum = 0
6769 12:26:45.559225 8, 0xFFFF, sum = 0
6770 12:26:45.562796 9, 0xFFFF, sum = 0
6771 12:26:45.562883 10, 0xFFFF, sum = 0
6772 12:26:45.565558 11, 0xFFFF, sum = 0
6773 12:26:45.565644 12, 0xFFFF, sum = 0
6774 12:26:45.569133 13, 0x0, sum = 1
6775 12:26:45.569222 14, 0x0, sum = 2
6776 12:26:45.572568 15, 0x0, sum = 3
6777 12:26:45.572661 16, 0x0, sum = 4
6778 12:26:45.575979 best_step = 14
6779 12:26:45.576063
6780 12:26:45.576131 ==
6781 12:26:45.579201 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 12:26:45.582539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 12:26:45.582665 ==
6784 12:26:45.585824 RX Vref Scan: 1
6785 12:26:45.585979
6786 12:26:45.586077 RX Vref 0 -> 0, step: 1
6787 12:26:45.586189
6788 12:26:45.589111 RX Delay -311 -> 252, step: 8
6789 12:26:45.589224
6790 12:26:45.592500 Set Vref, RX VrefLevel [Byte0]: 51
6791 12:26:45.595652 [Byte1]: 49
6792 12:26:45.600317
6793 12:26:45.600462 Final RX Vref Byte 0 = 51 to rank0
6794 12:26:45.603180 Final RX Vref Byte 1 = 49 to rank0
6795 12:26:45.606796 Final RX Vref Byte 0 = 51 to rank1
6796 12:26:45.610178 Final RX Vref Byte 1 = 49 to rank1==
6797 12:26:45.613153 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 12:26:45.620208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 12:26:45.620354 ==
6800 12:26:45.620453 DQS Delay:
6801 12:26:45.623054 DQS0 = 32, DQS1 = 32
6802 12:26:45.623160 DQM Delay:
6803 12:26:45.623258 DQM0 = 14, DQM1 = 12
6804 12:26:45.626415 DQ Delay:
6805 12:26:45.630395 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6806 12:26:45.630484 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6807 12:26:45.633695 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6808 12:26:45.636980 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6809 12:26:45.637088
6810 12:26:45.640360
6811 12:26:45.646439 [DQSOSCAuto] RK0, (LSB)MR18= 0x91c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6812 12:26:45.649916 CH1 RK0: MR19=C0C, MR18=91C9
6813 12:26:45.656995 CH1_RK0: MR19=0xC0C, MR18=0x91C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6814 12:26:45.657130 ==
6815 12:26:45.659879 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 12:26:45.663320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 12:26:45.663428 ==
6818 12:26:45.666239 [Gating] SW mode calibration
6819 12:26:45.673135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6820 12:26:45.679518 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6821 12:26:45.683030 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 12:26:45.686475 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 12:26:45.692937 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 12:26:45.696346 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 12:26:45.699721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 12:26:45.706156 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 12:26:45.709451 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 12:26:45.712796 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 12:26:45.719730 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 12:26:45.719826 Total UI for P1: 0, mck2ui 16
6831 12:26:45.722544 best dqsien dly found for B0: ( 0, 14, 24)
6832 12:26:45.725987 Total UI for P1: 0, mck2ui 16
6833 12:26:45.729588 best dqsien dly found for B1: ( 0, 14, 24)
6834 12:26:45.735810 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6835 12:26:45.739036 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6836 12:26:45.739151
6837 12:26:45.742796 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 12:26:45.745846 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 12:26:45.749191 [Gating] SW calibration Done
6840 12:26:45.749299 ==
6841 12:26:45.752639 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 12:26:45.756057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 12:26:45.756165 ==
6844 12:26:45.759450 RX Vref Scan: 0
6845 12:26:45.759565
6846 12:26:45.759666 RX Vref 0 -> 0, step: 1
6847 12:26:45.759766
6848 12:26:45.762297 RX Delay -410 -> 252, step: 16
6849 12:26:45.769420 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6850 12:26:45.772251 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6851 12:26:45.775658 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6852 12:26:45.779139 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6853 12:26:45.782694 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6854 12:26:45.789233 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6855 12:26:45.792679 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6856 12:26:45.795864 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6857 12:26:45.799098 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6858 12:26:45.805638 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6859 12:26:45.809010 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6860 12:26:45.812394 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6861 12:26:45.815651 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6862 12:26:45.822498 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6863 12:26:45.825958 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6864 12:26:45.829407 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6865 12:26:45.829494 ==
6866 12:26:45.832311 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 12:26:45.838829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 12:26:45.838911 ==
6869 12:26:45.838975 DQS Delay:
6870 12:26:45.842234 DQS0 = 27, DQS1 = 35
6871 12:26:45.842334 DQM Delay:
6872 12:26:45.842428 DQM0 = 11, DQM1 = 15
6873 12:26:45.845656 DQ Delay:
6874 12:26:45.848871 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6875 12:26:45.848948 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6876 12:26:45.852211 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6877 12:26:45.855432 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6878 12:26:45.855517
6879 12:26:45.858758
6880 12:26:45.858842 ==
6881 12:26:45.862049 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 12:26:45.865845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 12:26:45.865930 ==
6884 12:26:45.865997
6885 12:26:45.866059
6886 12:26:45.869212 TX Vref Scan disable
6887 12:26:45.869297 == TX Byte 0 ==
6888 12:26:45.871986 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6889 12:26:45.878862 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6890 12:26:45.878945 == TX Byte 1 ==
6891 12:26:45.882341 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6892 12:26:45.889097 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6893 12:26:45.889217 ==
6894 12:26:45.891837 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 12:26:45.895271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 12:26:45.895379 ==
6897 12:26:45.895446
6898 12:26:45.895508
6899 12:26:45.898813 TX Vref Scan disable
6900 12:26:45.898896 == TX Byte 0 ==
6901 12:26:45.902225 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6902 12:26:45.908810 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6903 12:26:45.908923 == TX Byte 1 ==
6904 12:26:45.912120 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6905 12:26:45.918662 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6906 12:26:45.918746
6907 12:26:45.918812 [DATLAT]
6908 12:26:45.918873 Freq=400, CH1 RK1
6909 12:26:45.918936
6910 12:26:45.922114 DATLAT Default: 0xe
6911 12:26:45.922197 0, 0xFFFF, sum = 0
6912 12:26:45.925319 1, 0xFFFF, sum = 0
6913 12:26:45.928500 2, 0xFFFF, sum = 0
6914 12:26:45.928584 3, 0xFFFF, sum = 0
6915 12:26:45.931935 4, 0xFFFF, sum = 0
6916 12:26:45.932019 5, 0xFFFF, sum = 0
6917 12:26:45.935480 6, 0xFFFF, sum = 0
6918 12:26:45.935565 7, 0xFFFF, sum = 0
6919 12:26:45.938376 8, 0xFFFF, sum = 0
6920 12:26:45.938461 9, 0xFFFF, sum = 0
6921 12:26:45.941911 10, 0xFFFF, sum = 0
6922 12:26:45.941996 11, 0xFFFF, sum = 0
6923 12:26:45.945398 12, 0xFFFF, sum = 0
6924 12:26:45.945500 13, 0x0, sum = 1
6925 12:26:45.948665 14, 0x0, sum = 2
6926 12:26:45.948763 15, 0x0, sum = 3
6927 12:26:45.951979 16, 0x0, sum = 4
6928 12:26:45.952094 best_step = 14
6929 12:26:45.952162
6930 12:26:45.952223 ==
6931 12:26:45.955510 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 12:26:45.958329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 12:26:45.961873 ==
6934 12:26:45.961959 RX Vref Scan: 0
6935 12:26:45.962046
6936 12:26:45.965406 RX Vref 0 -> 0, step: 1
6937 12:26:45.965516
6938 12:26:45.968729 RX Delay -311 -> 252, step: 8
6939 12:26:45.972161 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6940 12:26:45.978766 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6941 12:26:45.981635 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6942 12:26:45.985033 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6943 12:26:45.988449 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6944 12:26:45.994848 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6945 12:26:45.998329 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6946 12:26:46.001748 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6947 12:26:46.005320 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6948 12:26:46.011790 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6949 12:26:46.015137 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6950 12:26:46.018514 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6951 12:26:46.021781 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6952 12:26:46.028348 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6953 12:26:46.031734 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6954 12:26:46.035004 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6955 12:26:46.035117 ==
6956 12:26:46.038298 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 12:26:46.044702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 12:26:46.044818 ==
6959 12:26:46.044927 DQS Delay:
6960 12:26:46.048281 DQS0 = 28, DQS1 = 32
6961 12:26:46.048390 DQM Delay:
6962 12:26:46.048493 DQM0 = 11, DQM1 = 12
6963 12:26:46.051839 DQ Delay:
6964 12:26:46.055147 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6965 12:26:46.055301 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6966 12:26:46.057889 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6967 12:26:46.061423 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6968 12:26:46.061537
6969 12:26:46.064820
6970 12:26:46.071146 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6971 12:26:46.074421 CH1 RK1: MR19=C0C, MR18=C455
6972 12:26:46.081178 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
6973 12:26:46.084849 [RxdqsGatingPostProcess] freq 400
6974 12:26:46.087652 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6975 12:26:46.091075 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 12:26:46.094569 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 12:26:46.098118 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 12:26:46.100928 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 12:26:46.104610 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 12:26:46.108142 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 12:26:46.111014 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 12:26:46.114626 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 12:26:46.118008 Pre-setting of DQS Precalculation
6984 12:26:46.121614 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6985 12:26:46.127875 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6986 12:26:46.134664 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6987 12:26:46.137820
6988 12:26:46.137915
6989 12:26:46.137985 [Calibration Summary] 800 Mbps
6990 12:26:46.141055 CH 0, Rank 0
6991 12:26:46.141174 SW Impedance : PASS
6992 12:26:46.144381 DUTY Scan : NO K
6993 12:26:46.147881 ZQ Calibration : PASS
6994 12:26:46.147962 Jitter Meter : NO K
6995 12:26:46.151297 CBT Training : PASS
6996 12:26:46.154810 Write leveling : PASS
6997 12:26:46.154893 RX DQS gating : PASS
6998 12:26:46.157614 RX DQ/DQS(RDDQC) : PASS
6999 12:26:46.161508 TX DQ/DQS : PASS
7000 12:26:46.161621 RX DATLAT : PASS
7001 12:26:46.164327 RX DQ/DQS(Engine): PASS
7002 12:26:46.167834 TX OE : NO K
7003 12:26:46.167945 All Pass.
7004 12:26:46.168042
7005 12:26:46.168138 CH 0, Rank 1
7006 12:26:46.171355 SW Impedance : PASS
7007 12:26:46.174829 DUTY Scan : NO K
7008 12:26:46.174952 ZQ Calibration : PASS
7009 12:26:46.177606 Jitter Meter : NO K
7010 12:26:46.177713 CBT Training : PASS
7011 12:26:46.180875 Write leveling : NO K
7012 12:26:46.184286 RX DQS gating : PASS
7013 12:26:46.184404 RX DQ/DQS(RDDQC) : PASS
7014 12:26:46.187536 TX DQ/DQS : PASS
7015 12:26:46.191602 RX DATLAT : PASS
7016 12:26:46.191722 RX DQ/DQS(Engine): PASS
7017 12:26:46.194286 TX OE : NO K
7018 12:26:46.194404 All Pass.
7019 12:26:46.194510
7020 12:26:46.197780 CH 1, Rank 0
7021 12:26:46.197904 SW Impedance : PASS
7022 12:26:46.201287 DUTY Scan : NO K
7023 12:26:46.204732 ZQ Calibration : PASS
7024 12:26:46.204847 Jitter Meter : NO K
7025 12:26:46.207702 CBT Training : PASS
7026 12:26:46.211213 Write leveling : PASS
7027 12:26:46.211299 RX DQS gating : PASS
7028 12:26:46.214074 RX DQ/DQS(RDDQC) : PASS
7029 12:26:46.217638 TX DQ/DQS : PASS
7030 12:26:46.217736 RX DATLAT : PASS
7031 12:26:46.221052 RX DQ/DQS(Engine): PASS
7032 12:26:46.224473 TX OE : NO K
7033 12:26:46.224594 All Pass.
7034 12:26:46.224705
7035 12:26:46.224810 CH 1, Rank 1
7036 12:26:46.228024 SW Impedance : PASS
7037 12:26:46.230864 DUTY Scan : NO K
7038 12:26:46.230970 ZQ Calibration : PASS
7039 12:26:46.234350 Jitter Meter : NO K
7040 12:26:46.234460 CBT Training : PASS
7041 12:26:46.237797 Write leveling : NO K
7042 12:26:46.241230 RX DQS gating : PASS
7043 12:26:46.241330 RX DQ/DQS(RDDQC) : PASS
7044 12:26:46.244432 TX DQ/DQS : PASS
7045 12:26:46.247773 RX DATLAT : PASS
7046 12:26:46.247892 RX DQ/DQS(Engine): PASS
7047 12:26:46.251055 TX OE : NO K
7048 12:26:46.251163 All Pass.
7049 12:26:46.251258
7050 12:26:46.254351 DramC Write-DBI off
7051 12:26:46.257543 PER_BANK_REFRESH: Hybrid Mode
7052 12:26:46.257622 TX_TRACKING: ON
7053 12:26:46.267686 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7054 12:26:46.271059 [FAST_K] Save calibration result to emmc
7055 12:26:46.274628 dramc_set_vcore_voltage set vcore to 725000
7056 12:26:46.277502 Read voltage for 1600, 0
7057 12:26:46.277623 Vio18 = 0
7058 12:26:46.277730 Vcore = 725000
7059 12:26:46.281037 Vdram = 0
7060 12:26:46.281151 Vddq = 0
7061 12:26:46.281260 Vmddr = 0
7062 12:26:46.287878 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7063 12:26:46.290755 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7064 12:26:46.293964 MEM_TYPE=3, freq_sel=13
7065 12:26:46.297302 sv_algorithm_assistance_LP4_3733
7066 12:26:46.300651 ============ PULL DRAM RESETB DOWN ============
7067 12:26:46.304073 ========== PULL DRAM RESETB DOWN end =========
7068 12:26:46.310402 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7069 12:26:46.314077 ===================================
7070 12:26:46.317584 LPDDR4 DRAM CONFIGURATION
7071 12:26:46.321124 ===================================
7072 12:26:46.321221 EX_ROW_EN[0] = 0x0
7073 12:26:46.324274 EX_ROW_EN[1] = 0x0
7074 12:26:46.324369 LP4Y_EN = 0x0
7075 12:26:46.327615 WORK_FSP = 0x1
7076 12:26:46.327702 WL = 0x5
7077 12:26:46.331082 RL = 0x5
7078 12:26:46.331177 BL = 0x2
7079 12:26:46.333978 RPST = 0x0
7080 12:26:46.334057 RD_PRE = 0x0
7081 12:26:46.337382 WR_PRE = 0x1
7082 12:26:46.337462 WR_PST = 0x1
7083 12:26:46.341010 DBI_WR = 0x0
7084 12:26:46.341117 DBI_RD = 0x0
7085 12:26:46.343903 OTF = 0x1
7086 12:26:46.347249 ===================================
7087 12:26:46.350705 ===================================
7088 12:26:46.350802 ANA top config
7089 12:26:46.353678 ===================================
7090 12:26:46.357716 DLL_ASYNC_EN = 0
7091 12:26:46.360856 ALL_SLAVE_EN = 0
7092 12:26:46.364227 NEW_RANK_MODE = 1
7093 12:26:46.364335 DLL_IDLE_MODE = 1
7094 12:26:46.366891 LP45_APHY_COMB_EN = 1
7095 12:26:46.370645 TX_ODT_DIS = 0
7096 12:26:46.373481 NEW_8X_MODE = 1
7097 12:26:46.376726 ===================================
7098 12:26:46.380403 ===================================
7099 12:26:46.383795 data_rate = 3200
7100 12:26:46.383904 CKR = 1
7101 12:26:46.387314 DQ_P2S_RATIO = 8
7102 12:26:46.390224 ===================================
7103 12:26:46.393605 CA_P2S_RATIO = 8
7104 12:26:46.396943 DQ_CA_OPEN = 0
7105 12:26:46.400261 DQ_SEMI_OPEN = 0
7106 12:26:46.403694 CA_SEMI_OPEN = 0
7107 12:26:46.403805 CA_FULL_RATE = 0
7108 12:26:46.407063 DQ_CKDIV4_EN = 0
7109 12:26:46.410365 CA_CKDIV4_EN = 0
7110 12:26:46.413867 CA_PREDIV_EN = 0
7111 12:26:46.417220 PH8_DLY = 12
7112 12:26:46.420838 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7113 12:26:46.420951 DQ_AAMCK_DIV = 4
7114 12:26:46.423635 CA_AAMCK_DIV = 4
7115 12:26:46.427186 CA_ADMCK_DIV = 4
7116 12:26:46.430667 DQ_TRACK_CA_EN = 0
7117 12:26:46.433947 CA_PICK = 1600
7118 12:26:46.437333 CA_MCKIO = 1600
7119 12:26:46.440158 MCKIO_SEMI = 0
7120 12:26:46.440252 PLL_FREQ = 3068
7121 12:26:46.443675 DQ_UI_PI_RATIO = 32
7122 12:26:46.447176 CA_UI_PI_RATIO = 0
7123 12:26:46.450753 ===================================
7124 12:26:46.453507 ===================================
7125 12:26:46.456999 memory_type:LPDDR4
7126 12:26:46.460470 GP_NUM : 10
7127 12:26:46.460548 SRAM_EN : 1
7128 12:26:46.463314 MD32_EN : 0
7129 12:26:46.466717 ===================================
7130 12:26:46.466802 [ANA_INIT] >>>>>>>>>>>>>>
7131 12:26:46.470091 <<<<<< [CONFIGURE PHASE]: ANA_TX
7132 12:26:46.473445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7133 12:26:46.476861 ===================================
7134 12:26:46.480204 data_rate = 3200,PCW = 0X7600
7135 12:26:46.483651 ===================================
7136 12:26:46.487176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7137 12:26:46.493508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 12:26:46.496821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 12:26:46.503504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7140 12:26:46.506859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7141 12:26:46.510197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7142 12:26:46.513607 [ANA_INIT] flow start
7143 12:26:46.513699 [ANA_INIT] PLL >>>>>>>>
7144 12:26:46.517051 [ANA_INIT] PLL <<<<<<<<
7145 12:26:46.519854 [ANA_INIT] MIDPI >>>>>>>>
7146 12:26:46.519949 [ANA_INIT] MIDPI <<<<<<<<
7147 12:26:46.523466 [ANA_INIT] DLL >>>>>>>>
7148 12:26:46.527022 [ANA_INIT] DLL <<<<<<<<
7149 12:26:46.527109 [ANA_INIT] flow end
7150 12:26:46.533252 ============ LP4 DIFF to SE enter ============
7151 12:26:46.536582 ============ LP4 DIFF to SE exit ============
7152 12:26:46.536674 [ANA_INIT] <<<<<<<<<<<<<
7153 12:26:46.540138 [Flow] Enable top DCM control >>>>>
7154 12:26:46.543658 [Flow] Enable top DCM control <<<<<
7155 12:26:46.546582 Enable DLL master slave shuffle
7156 12:26:46.552981 ==============================================================
7157 12:26:46.556390 Gating Mode config
7158 12:26:46.559808 ==============================================================
7159 12:26:46.563267 Config description:
7160 12:26:46.573600 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7161 12:26:46.579730 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7162 12:26:46.583007 SELPH_MODE 0: By rank 1: By Phase
7163 12:26:46.589769 ==============================================================
7164 12:26:46.593272 GAT_TRACK_EN = 1
7165 12:26:46.596180 RX_GATING_MODE = 2
7166 12:26:46.599701 RX_GATING_TRACK_MODE = 2
7167 12:26:46.599796 SELPH_MODE = 1
7168 12:26:46.602969 PICG_EARLY_EN = 1
7169 12:26:46.606345 VALID_LAT_VALUE = 1
7170 12:26:46.613117 ==============================================================
7171 12:26:46.616324 Enter into Gating configuration >>>>
7172 12:26:46.618991 Exit from Gating configuration <<<<
7173 12:26:46.622973 Enter into DVFS_PRE_config >>>>>
7174 12:26:46.632482 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7175 12:26:46.636064 Exit from DVFS_PRE_config <<<<<
7176 12:26:46.639458 Enter into PICG configuration >>>>
7177 12:26:46.642865 Exit from PICG configuration <<<<
7178 12:26:46.646271 [RX_INPUT] configuration >>>>>
7179 12:26:46.649075 [RX_INPUT] configuration <<<<<
7180 12:26:46.652665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7181 12:26:46.659002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7182 12:26:46.665951 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 12:26:46.672274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 12:26:46.679192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 12:26:46.685356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 12:26:46.688864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7187 12:26:46.692113 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7188 12:26:46.695460 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7189 12:26:46.698988 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7190 12:26:46.705304 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7191 12:26:46.708754 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 12:26:46.712150 ===================================
7193 12:26:46.715564 LPDDR4 DRAM CONFIGURATION
7194 12:26:46.718404 ===================================
7195 12:26:46.718495 EX_ROW_EN[0] = 0x0
7196 12:26:46.721861 EX_ROW_EN[1] = 0x0
7197 12:26:46.721970 LP4Y_EN = 0x0
7198 12:26:46.725298 WORK_FSP = 0x1
7199 12:26:46.725377 WL = 0x5
7200 12:26:46.728835 RL = 0x5
7201 12:26:46.728950 BL = 0x2
7202 12:26:46.731741 RPST = 0x0
7203 12:26:46.735058 RD_PRE = 0x0
7204 12:26:46.735156 WR_PRE = 0x1
7205 12:26:46.738592 WR_PST = 0x1
7206 12:26:46.738679 DBI_WR = 0x0
7207 12:26:46.741998 DBI_RD = 0x0
7208 12:26:46.742112 OTF = 0x1
7209 12:26:46.745428 ===================================
7210 12:26:46.748886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7211 12:26:46.752282 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7212 12:26:46.758738 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 12:26:46.762200 ===================================
7214 12:26:46.764984 LPDDR4 DRAM CONFIGURATION
7215 12:26:46.768444 ===================================
7216 12:26:46.768528 EX_ROW_EN[0] = 0x10
7217 12:26:46.771950 EX_ROW_EN[1] = 0x0
7218 12:26:46.772034 LP4Y_EN = 0x0
7219 12:26:46.775475 WORK_FSP = 0x1
7220 12:26:46.775558 WL = 0x5
7221 12:26:46.778209 RL = 0x5
7222 12:26:46.778292 BL = 0x2
7223 12:26:46.781627 RPST = 0x0
7224 12:26:46.781711 RD_PRE = 0x0
7225 12:26:46.785196 WR_PRE = 0x1
7226 12:26:46.785282 WR_PST = 0x1
7227 12:26:46.788490 DBI_WR = 0x0
7228 12:26:46.788574 DBI_RD = 0x0
7229 12:26:46.791980 OTF = 0x1
7230 12:26:46.794813 ===================================
7231 12:26:46.801884 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7232 12:26:46.801993 ==
7233 12:26:46.805120 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 12:26:46.808677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7235 12:26:46.808781 ==
7236 12:26:46.811509 [Duty_Offset_Calibration]
7237 12:26:46.811612 B0:2 B1:1 CA:1
7238 12:26:46.811703
7239 12:26:46.814932 [DutyScan_Calibration_Flow] k_type=0
7240 12:26:46.826159
7241 12:26:46.826246 ==CLK 0==
7242 12:26:46.829637 Final CLK duty delay cell = 0
7243 12:26:46.833086 [0] MAX Duty = 5156%(X100), DQS PI = 22
7244 12:26:46.835848 [0] MIN Duty = 4876%(X100), DQS PI = 48
7245 12:26:46.835963 [0] AVG Duty = 5016%(X100)
7246 12:26:46.839514
7247 12:26:46.842951 CH0 CLK Duty spec in!! Max-Min= 280%
7248 12:26:46.845830 [DutyScan_Calibration_Flow] ====Done====
7249 12:26:46.845979
7250 12:26:46.849151 [DutyScan_Calibration_Flow] k_type=1
7251 12:26:46.865674
7252 12:26:46.865780 ==DQS 0 ==
7253 12:26:46.868518 Final DQS duty delay cell = -4
7254 12:26:46.872058 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7255 12:26:46.875491 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7256 12:26:46.878985 [-4] AVG Duty = 4891%(X100)
7257 12:26:46.879106
7258 12:26:46.879212 ==DQS 1 ==
7259 12:26:46.881831 Final DQS duty delay cell = 0
7260 12:26:46.885336 [0] MAX Duty = 5187%(X100), DQS PI = 20
7261 12:26:46.888903 [0] MIN Duty = 5062%(X100), DQS PI = 34
7262 12:26:46.891755 [0] AVG Duty = 5124%(X100)
7263 12:26:46.891848
7264 12:26:46.895059 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7265 12:26:46.895144
7266 12:26:46.898479 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7267 12:26:46.902036 [DutyScan_Calibration_Flow] ====Done====
7268 12:26:46.902121
7269 12:26:46.905567 [DutyScan_Calibration_Flow] k_type=3
7270 12:26:46.922287
7271 12:26:46.922427 ==DQM 0 ==
7272 12:26:46.925124 Final DQM duty delay cell = 0
7273 12:26:46.928500 [0] MAX Duty = 5218%(X100), DQS PI = 32
7274 12:26:46.931849 [0] MIN Duty = 4907%(X100), DQS PI = 0
7275 12:26:46.931930 [0] AVG Duty = 5062%(X100)
7276 12:26:46.935224
7277 12:26:46.935304 ==DQM 1 ==
7278 12:26:46.938502 Final DQM duty delay cell = -4
7279 12:26:46.942069 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7280 12:26:46.945621 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7281 12:26:46.948479 [-4] AVG Duty = 4922%(X100)
7282 12:26:46.948564
7283 12:26:46.951935 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7284 12:26:46.952019
7285 12:26:46.955482 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7286 12:26:46.958837 [DutyScan_Calibration_Flow] ====Done====
7287 12:26:46.958921
7288 12:26:46.962354 [DutyScan_Calibration_Flow] k_type=2
7289 12:26:46.979868
7290 12:26:46.979958 ==DQ 0 ==
7291 12:26:46.982682 Final DQ duty delay cell = 0
7292 12:26:46.986257 [0] MAX Duty = 5062%(X100), DQS PI = 24
7293 12:26:46.989775 [0] MIN Duty = 4907%(X100), DQS PI = 0
7294 12:26:46.989864 [0] AVG Duty = 4984%(X100)
7295 12:26:46.989930
7296 12:26:46.993055 ==DQ 1 ==
7297 12:26:46.995831 Final DQ duty delay cell = 0
7298 12:26:46.999395 [0] MAX Duty = 5125%(X100), DQS PI = 4
7299 12:26:47.002616 [0] MIN Duty = 4938%(X100), DQS PI = 34
7300 12:26:47.002736 [0] AVG Duty = 5031%(X100)
7301 12:26:47.002804
7302 12:26:47.006058 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7303 12:26:47.009706
7304 12:26:47.012331 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7305 12:26:47.016035 [DutyScan_Calibration_Flow] ====Done====
7306 12:26:47.016116 ==
7307 12:26:47.019421 Dram Type= 6, Freq= 0, CH_1, rank 0
7308 12:26:47.022986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 12:26:47.023082 ==
7310 12:26:47.025739 [Duty_Offset_Calibration]
7311 12:26:47.025837 B0:1 B1:0 CA:1
7312 12:26:47.025904
7313 12:26:47.029132 [DutyScan_Calibration_Flow] k_type=0
7314 12:26:47.038675
7315 12:26:47.038762 ==CLK 0==
7316 12:26:47.041941 Final CLK duty delay cell = -4
7317 12:26:47.045210 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7318 12:26:47.048660 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7319 12:26:47.052352 [-4] AVG Duty = 4938%(X100)
7320 12:26:47.052435
7321 12:26:47.055202 CH1 CLK Duty spec in!! Max-Min= 124%
7322 12:26:47.058707 [DutyScan_Calibration_Flow] ====Done====
7323 12:26:47.058788
7324 12:26:47.061536 [DutyScan_Calibration_Flow] k_type=1
7325 12:26:47.079080
7326 12:26:47.079166 ==DQS 0 ==
7327 12:26:47.081871 Final DQS duty delay cell = 0
7328 12:26:47.085311 [0] MAX Duty = 5094%(X100), DQS PI = 18
7329 12:26:47.088942 [0] MIN Duty = 4875%(X100), DQS PI = 0
7330 12:26:47.089029 [0] AVG Duty = 4984%(X100)
7331 12:26:47.092564
7332 12:26:47.092648 ==DQS 1 ==
7333 12:26:47.095254 Final DQS duty delay cell = 0
7334 12:26:47.098761 [0] MAX Duty = 5249%(X100), DQS PI = 16
7335 12:26:47.102347 [0] MIN Duty = 4969%(X100), DQS PI = 8
7336 12:26:47.102431 [0] AVG Duty = 5109%(X100)
7337 12:26:47.105178
7338 12:26:47.108590 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7339 12:26:47.108673
7340 12:26:47.112187 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7341 12:26:47.114971 [DutyScan_Calibration_Flow] ====Done====
7342 12:26:47.115053
7343 12:26:47.118429 [DutyScan_Calibration_Flow] k_type=3
7344 12:26:47.135503
7345 12:26:47.135595 ==DQM 0 ==
7346 12:26:47.138804 Final DQM duty delay cell = 0
7347 12:26:47.142165 [0] MAX Duty = 5218%(X100), DQS PI = 18
7348 12:26:47.145426 [0] MIN Duty = 5000%(X100), DQS PI = 48
7349 12:26:47.148953 [0] AVG Duty = 5109%(X100)
7350 12:26:47.149039
7351 12:26:47.149105 ==DQM 1 ==
7352 12:26:47.152196 Final DQM duty delay cell = 0
7353 12:26:47.155439 [0] MAX Duty = 5093%(X100), DQS PI = 18
7354 12:26:47.158931 [0] MIN Duty = 4907%(X100), DQS PI = 52
7355 12:26:47.162471 [0] AVG Duty = 5000%(X100)
7356 12:26:47.162553
7357 12:26:47.165896 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7358 12:26:47.165974
7359 12:26:47.168639 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7360 12:26:47.172129 [DutyScan_Calibration_Flow] ====Done====
7361 12:26:47.172208
7362 12:26:47.175614 [DutyScan_Calibration_Flow] k_type=2
7363 12:26:47.192259
7364 12:26:47.192349 ==DQ 0 ==
7365 12:26:47.195130 Final DQ duty delay cell = -4
7366 12:26:47.198538 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7367 12:26:47.202103 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7368 12:26:47.204880 [-4] AVG Duty = 4968%(X100)
7369 12:26:47.204956
7370 12:26:47.205019 ==DQ 1 ==
7371 12:26:47.208258 Final DQ duty delay cell = 0
7372 12:26:47.211807 [0] MAX Duty = 5124%(X100), DQS PI = 18
7373 12:26:47.215087 [0] MIN Duty = 4938%(X100), DQS PI = 8
7374 12:26:47.217903 [0] AVG Duty = 5031%(X100)
7375 12:26:47.217982
7376 12:26:47.221387 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7377 12:26:47.221468
7378 12:26:47.224990 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7379 12:26:47.227875 [DutyScan_Calibration_Flow] ====Done====
7380 12:26:47.231189 nWR fixed to 30
7381 12:26:47.234502 [ModeRegInit_LP4] CH0 RK0
7382 12:26:47.234582 [ModeRegInit_LP4] CH0 RK1
7383 12:26:47.238162 [ModeRegInit_LP4] CH1 RK0
7384 12:26:47.241604 [ModeRegInit_LP4] CH1 RK1
7385 12:26:47.241686 match AC timing 5
7386 12:26:47.248191 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7387 12:26:47.251602 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7388 12:26:47.254963 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7389 12:26:47.261601 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7390 12:26:47.265042 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7391 12:26:47.265129 [MiockJmeterHQA]
7392 12:26:47.265197
7393 12:26:47.268421 [DramcMiockJmeter] u1RxGatingPI = 0
7394 12:26:47.271857 0 : 4363, 4138
7395 12:26:47.271945 4 : 4252, 4027
7396 12:26:47.274739 8 : 4363, 4138
7397 12:26:47.274838 12 : 4363, 4138
7398 12:26:47.274907 16 : 4249, 4024
7399 12:26:47.278086 20 : 4363, 4137
7400 12:26:47.278170 24 : 4252, 4026
7401 12:26:47.281669 28 : 4252, 4027
7402 12:26:47.281754 32 : 4255, 4030
7403 12:26:47.285017 36 : 4253, 4026
7404 12:26:47.285102 40 : 4363, 4138
7405 12:26:47.285171 44 : 4253, 4026
7406 12:26:47.288526 48 : 4363, 4137
7407 12:26:47.288613 52 : 4253, 4027
7408 12:26:47.291260 56 : 4253, 4026
7409 12:26:47.291372 60 : 4252, 4027
7410 12:26:47.294779 64 : 4363, 4137
7411 12:26:47.294864 68 : 4250, 4026
7412 12:26:47.298291 72 : 4360, 4138
7413 12:26:47.298376 76 : 4253, 4027
7414 12:26:47.298443 80 : 4250, 4027
7415 12:26:47.301852 84 : 4250, 4027
7416 12:26:47.301935 88 : 4250, 335
7417 12:26:47.304663 92 : 4252, 0
7418 12:26:47.304747 96 : 4360, 0
7419 12:26:47.304815 100 : 4363, 0
7420 12:26:47.308185 104 : 4252, 0
7421 12:26:47.308270 108 : 4250, 0
7422 12:26:47.311651 112 : 4249, 0
7423 12:26:47.311735 116 : 4253, 0
7424 12:26:47.311802 120 : 4363, 0
7425 12:26:47.315027 124 : 4249, 0
7426 12:26:47.315110 128 : 4250, 0
7427 12:26:47.317822 132 : 4250, 0
7428 12:26:47.317906 136 : 4360, 0
7429 12:26:47.317974 140 : 4361, 0
7430 12:26:47.321147 144 : 4250, 0
7431 12:26:47.321232 148 : 4250, 0
7432 12:26:47.321300 152 : 4249, 0
7433 12:26:47.325109 156 : 4250, 0
7434 12:26:47.325193 160 : 4250, 0
7435 12:26:47.327820 164 : 4249, 0
7436 12:26:47.327904 168 : 4250, 0
7437 12:26:47.327971 172 : 4361, 0
7438 12:26:47.331190 176 : 4249, 0
7439 12:26:47.331276 180 : 4250, 0
7440 12:26:47.334663 184 : 4250, 0
7441 12:26:47.334748 188 : 4360, 0
7442 12:26:47.334815 192 : 4360, 0
7443 12:26:47.338121 196 : 4250, 0
7444 12:26:47.338222 200 : 4250, 0
7445 12:26:47.341541 204 : 4249, 1399
7446 12:26:47.341625 208 : 4360, 4129
7447 12:26:47.344361 212 : 4363, 4138
7448 12:26:47.344445 216 : 4249, 4027
7449 12:26:47.347871 220 : 4363, 4140
7450 12:26:47.347954 224 : 4360, 4138
7451 12:26:47.348022 228 : 4250, 4027
7452 12:26:47.351361 232 : 4250, 4027
7453 12:26:47.351460 236 : 4250, 4026
7454 12:26:47.354590 240 : 4250, 4027
7455 12:26:47.354691 244 : 4250, 4027
7456 12:26:47.357743 248 : 4250, 4026
7457 12:26:47.357858 252 : 4250, 4026
7458 12:26:47.360855 256 : 4250, 4027
7459 12:26:47.360978 260 : 4360, 4138
7460 12:26:47.364168 264 : 4361, 4137
7461 12:26:47.364292 268 : 4248, 4024
7462 12:26:47.367491 272 : 4361, 4137
7463 12:26:47.367576 276 : 4360, 4138
7464 12:26:47.370957 280 : 4250, 4027
7465 12:26:47.371129 284 : 4250, 4027
7466 12:26:47.371265 288 : 4250, 4026
7467 12:26:47.374241 292 : 4250, 4027
7468 12:26:47.374348 296 : 4250, 4027
7469 12:26:47.377630 300 : 4250, 4027
7470 12:26:47.377733 304 : 4250, 4026
7471 12:26:47.380956 308 : 4250, 4005
7472 12:26:47.381100 312 : 4360, 2399
7473 12:26:47.384511 316 : 4361, 18
7474 12:26:47.384614
7475 12:26:47.384704 MIOCK jitter meter ch=0
7476 12:26:47.384792
7477 12:26:47.388099 1T = (316-88) = 228 dly cells
7478 12:26:47.394335 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7479 12:26:47.394424 ==
7480 12:26:47.397658 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 12:26:47.401185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7482 12:26:47.401271 ==
7483 12:26:47.407521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7484 12:26:47.410971 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7485 12:26:47.414648 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7486 12:26:47.420904 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7487 12:26:47.430697 [CA 0] Center 43 (13~74) winsize 62
7488 12:26:47.434120 [CA 1] Center 43 (12~74) winsize 63
7489 12:26:47.437600 [CA 2] Center 38 (9~68) winsize 60
7490 12:26:47.440498 [CA 3] Center 38 (8~68) winsize 61
7491 12:26:47.444024 [CA 4] Center 37 (7~67) winsize 61
7492 12:26:47.447198 [CA 5] Center 36 (7~65) winsize 59
7493 12:26:47.447304
7494 12:26:47.450783 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7495 12:26:47.450886
7496 12:26:47.453737 [CATrainingPosCal] consider 1 rank data
7497 12:26:47.457295 u2DelayCellTimex100 = 285/100 ps
7498 12:26:47.464169 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7499 12:26:47.467467 CA1 delay=43 (12~74),Diff = 7 PI (23 cell)
7500 12:26:47.470649 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7501 12:26:47.473884 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7502 12:26:47.477131 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7503 12:26:47.480485 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7504 12:26:47.480594
7505 12:26:47.483748 CA PerBit enable=1, Macro0, CA PI delay=36
7506 12:26:47.483826
7507 12:26:47.487101 [CBTSetCACLKResult] CA Dly = 36
7508 12:26:47.490529 CS Dly: 9 (0~40)
7509 12:26:47.493971 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7510 12:26:47.497402 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7511 12:26:47.497484 ==
7512 12:26:47.500067 Dram Type= 6, Freq= 0, CH_0, rank 1
7513 12:26:47.503528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 12:26:47.507067 ==
7515 12:26:47.510534 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 12:26:47.513374 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 12:26:47.520292 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 12:26:47.523823 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 12:26:47.534098 [CA 0] Center 42 (12~73) winsize 62
7520 12:26:47.537380 [CA 1] Center 42 (12~73) winsize 62
7521 12:26:47.540589 [CA 2] Center 38 (8~68) winsize 61
7522 12:26:47.543829 [CA 3] Center 37 (8~67) winsize 60
7523 12:26:47.547420 [CA 4] Center 36 (6~66) winsize 61
7524 12:26:47.550827 [CA 5] Center 35 (5~65) winsize 61
7525 12:26:47.550916
7526 12:26:47.554094 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 12:26:47.554170
7528 12:26:47.556939 [CATrainingPosCal] consider 2 rank data
7529 12:26:47.560396 u2DelayCellTimex100 = 285/100 ps
7530 12:26:47.563890 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7531 12:26:47.570753 CA1 delay=42 (12~73),Diff = 6 PI (20 cell)
7532 12:26:47.573531 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7533 12:26:47.576941 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7534 12:26:47.580216 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7535 12:26:47.583428 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7536 12:26:47.583515
7537 12:26:47.587352 CA PerBit enable=1, Macro0, CA PI delay=36
7538 12:26:47.587468
7539 12:26:47.590619 [CBTSetCACLKResult] CA Dly = 36
7540 12:26:47.593964 CS Dly: 10 (0~42)
7541 12:26:47.596694 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 12:26:47.599986 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 12:26:47.600104
7544 12:26:47.603398 ----->DramcWriteLeveling(PI) begin...
7545 12:26:47.603485 ==
7546 12:26:47.606810 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 12:26:47.613717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 12:26:47.613804 ==
7549 12:26:47.616670 Write leveling (Byte 0): 36 => 36
7550 12:26:47.616755 Write leveling (Byte 1): 29 => 29
7551 12:26:47.620126 DramcWriteLeveling(PI) end<-----
7552 12:26:47.620212
7553 12:26:47.620280 ==
7554 12:26:47.623670 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 12:26:47.630047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 12:26:47.630134 ==
7557 12:26:47.633702 [Gating] SW mode calibration
7558 12:26:47.640108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7559 12:26:47.643509 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7560 12:26:47.650040 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 12:26:47.653477 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 12:26:47.656907 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7563 12:26:47.662917 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7564 12:26:47.666484 1 4 16 | B1->B0 | 2323 3535 | 1 0 | (1 1) (0 0)
7565 12:26:47.669799 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7566 12:26:47.676556 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7567 12:26:47.679938 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7568 12:26:47.683322 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7569 12:26:47.689736 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 12:26:47.693003 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
7571 12:26:47.696363 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7572 12:26:47.703200 1 5 16 | B1->B0 | 3333 2827 | 0 1 | (0 1) (1 0)
7573 12:26:47.706737 1 5 20 | B1->B0 | 2424 2b2a | 0 1 | (0 1) (0 0)
7574 12:26:47.709442 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7575 12:26:47.716461 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7576 12:26:47.719341 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7577 12:26:47.722827 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7578 12:26:47.726423 1 6 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7579 12:26:47.732853 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7580 12:26:47.736312 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7581 12:26:47.739707 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (0 0)
7582 12:26:47.746048 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 12:26:47.749408 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 12:26:47.752803 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 12:26:47.759558 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 12:26:47.762977 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 12:26:47.766329 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 12:26:47.772555 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7589 12:26:47.775885 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 12:26:47.779286 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 12:26:47.785676 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 12:26:47.789027 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 12:26:47.792401 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 12:26:47.799075 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 12:26:47.802282 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 12:26:47.805705 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:26:47.812360 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 12:26:47.815707 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:26:47.819124 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:26:47.825663 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:26:47.829232 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:26:47.832103 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 12:26:47.839241 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 12:26:47.842789 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7605 12:26:47.845717 Total UI for P1: 0, mck2ui 16
7606 12:26:47.849413 best dqsien dly found for B0: ( 1, 9, 10)
7607 12:26:47.852581 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 12:26:47.858791 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 12:26:47.858875 Total UI for P1: 0, mck2ui 16
7610 12:26:47.862201 best dqsien dly found for B1: ( 1, 9, 20)
7611 12:26:47.868944 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7612 12:26:47.872290 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7613 12:26:47.872373
7614 12:26:47.875590 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7615 12:26:47.878698 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7616 12:26:47.882446 [Gating] SW calibration Done
7617 12:26:47.882529 ==
7618 12:26:47.885871 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 12:26:47.888716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 12:26:47.888800 ==
7621 12:26:47.892199 RX Vref Scan: 0
7622 12:26:47.892312
7623 12:26:47.892409 RX Vref 0 -> 0, step: 1
7624 12:26:47.892499
7625 12:26:47.895605 RX Delay 0 -> 252, step: 8
7626 12:26:47.898983 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7627 12:26:47.905568 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7628 12:26:47.908818 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7629 12:26:47.912169 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7630 12:26:47.915528 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7631 12:26:47.918957 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7632 12:26:47.925720 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7633 12:26:47.928550 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7634 12:26:47.932128 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7635 12:26:47.935570 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7636 12:26:47.938421 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7637 12:26:47.945336 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7638 12:26:47.948752 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7639 12:26:47.951443 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7640 12:26:47.954894 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7641 12:26:47.958332 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7642 12:26:47.958428 ==
7643 12:26:47.961861 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:26:47.968125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:26:47.968279 ==
7646 12:26:47.968385 DQS Delay:
7647 12:26:47.971554 DQS0 = 0, DQS1 = 0
7648 12:26:47.971695 DQM Delay:
7649 12:26:47.974833 DQM0 = 137, DQM1 = 131
7650 12:26:47.974914 DQ Delay:
7651 12:26:47.978273 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7652 12:26:47.981757 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7653 12:26:47.984891 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7654 12:26:47.988157 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7655 12:26:47.988276
7656 12:26:47.988384
7657 12:26:47.988483 ==
7658 12:26:47.991863 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 12:26:47.998185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 12:26:47.998296 ==
7661 12:26:47.998400
7662 12:26:47.998498
7663 12:26:47.998595 TX Vref Scan disable
7664 12:26:48.001698 == TX Byte 0 ==
7665 12:26:48.005085 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7666 12:26:48.011811 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7667 12:26:48.011893 == TX Byte 1 ==
7668 12:26:48.015226 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7669 12:26:48.021912 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7670 12:26:48.022008 ==
7671 12:26:48.024646 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 12:26:48.028066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 12:26:48.028179 ==
7674 12:26:48.039902
7675 12:26:48.043377 TX Vref early break, caculate TX vref
7676 12:26:48.046215 TX Vref=16, minBit 0, minWin=23, winSum=379
7677 12:26:48.049615 TX Vref=18, minBit 0, minWin=23, winSum=387
7678 12:26:48.053174 TX Vref=20, minBit 0, minWin=24, winSum=399
7679 12:26:48.056688 TX Vref=22, minBit 0, minWin=25, winSum=410
7680 12:26:48.060185 TX Vref=24, minBit 0, minWin=25, winSum=419
7681 12:26:48.066230 TX Vref=26, minBit 0, minWin=25, winSum=422
7682 12:26:48.069724 TX Vref=28, minBit 0, minWin=25, winSum=424
7683 12:26:48.073212 TX Vref=30, minBit 4, minWin=24, winSum=409
7684 12:26:48.076785 TX Vref=32, minBit 0, minWin=23, winSum=399
7685 12:26:48.082751 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
7686 12:26:48.082864
7687 12:26:48.086190 Final TX Range 0 Vref 28
7688 12:26:48.086271
7689 12:26:48.086342 ==
7690 12:26:48.089756 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 12:26:48.092952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 12:26:48.093067 ==
7693 12:26:48.093168
7694 12:26:48.093264
7695 12:26:48.096390 TX Vref Scan disable
7696 12:26:48.099627 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7697 12:26:48.102907 == TX Byte 0 ==
7698 12:26:48.106739 u2DelayCellOfst[0]=10 cells (3 PI)
7699 12:26:48.109516 u2DelayCellOfst[1]=13 cells (4 PI)
7700 12:26:48.113024 u2DelayCellOfst[2]=10 cells (3 PI)
7701 12:26:48.116365 u2DelayCellOfst[3]=10 cells (3 PI)
7702 12:26:48.119678 u2DelayCellOfst[4]=6 cells (2 PI)
7703 12:26:48.119764 u2DelayCellOfst[5]=0 cells (0 PI)
7704 12:26:48.123043 u2DelayCellOfst[6]=17 cells (5 PI)
7705 12:26:48.126313 u2DelayCellOfst[7]=17 cells (5 PI)
7706 12:26:48.132931 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7707 12:26:48.136232 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7708 12:26:48.136312 == TX Byte 1 ==
7709 12:26:48.139663 u2DelayCellOfst[8]=0 cells (0 PI)
7710 12:26:48.143185 u2DelayCellOfst[9]=0 cells (0 PI)
7711 12:26:48.146110 u2DelayCellOfst[10]=10 cells (3 PI)
7712 12:26:48.149674 u2DelayCellOfst[11]=6 cells (2 PI)
7713 12:26:48.152587 u2DelayCellOfst[12]=13 cells (4 PI)
7714 12:26:48.155937 u2DelayCellOfst[13]=10 cells (3 PI)
7715 12:26:48.159254 u2DelayCellOfst[14]=13 cells (4 PI)
7716 12:26:48.162807 u2DelayCellOfst[15]=10 cells (3 PI)
7717 12:26:48.166227 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7718 12:26:48.169640 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7719 12:26:48.172549 DramC Write-DBI on
7720 12:26:48.172651 ==
7721 12:26:48.176021 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 12:26:48.179533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 12:26:48.179621 ==
7724 12:26:48.179689
7725 12:26:48.179754
7726 12:26:48.183093 TX Vref Scan disable
7727 12:26:48.186426 == TX Byte 0 ==
7728 12:26:48.189646 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7729 12:26:48.193150 == TX Byte 1 ==
7730 12:26:48.195971 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7731 12:26:48.196059 DramC Write-DBI off
7732 12:26:48.196127
7733 12:26:48.199409 [DATLAT]
7734 12:26:48.199509 Freq=1600, CH0 RK0
7735 12:26:48.199595
7736 12:26:48.202968 DATLAT Default: 0xf
7737 12:26:48.203049 0, 0xFFFF, sum = 0
7738 12:26:48.206348 1, 0xFFFF, sum = 0
7739 12:26:48.206433 2, 0xFFFF, sum = 0
7740 12:26:48.209505 3, 0xFFFF, sum = 0
7741 12:26:48.209585 4, 0xFFFF, sum = 0
7742 12:26:48.212638 5, 0xFFFF, sum = 0
7743 12:26:48.212736 6, 0xFFFF, sum = 0
7744 12:26:48.216104 7, 0xFFFF, sum = 0
7745 12:26:48.216193 8, 0xFFFF, sum = 0
7746 12:26:48.219006 9, 0xFFFF, sum = 0
7747 12:26:48.223022 10, 0xFFFF, sum = 0
7748 12:26:48.223117 11, 0xFFFF, sum = 0
7749 12:26:48.225783 12, 0xFFFF, sum = 0
7750 12:26:48.225868 13, 0xFFFF, sum = 0
7751 12:26:48.229190 14, 0x0, sum = 1
7752 12:26:48.229276 15, 0x0, sum = 2
7753 12:26:48.232539 16, 0x0, sum = 3
7754 12:26:48.232621 17, 0x0, sum = 4
7755 12:26:48.232731 best_step = 15
7756 12:26:48.232832
7757 12:26:48.235777 ==
7758 12:26:48.238960 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 12:26:48.242394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 12:26:48.242483 ==
7761 12:26:48.242570 RX Vref Scan: 1
7762 12:26:48.242665
7763 12:26:48.245553 Set Vref Range= 24 -> 127
7764 12:26:48.245644
7765 12:26:48.248953 RX Vref 24 -> 127, step: 1
7766 12:26:48.249047
7767 12:26:48.252330 RX Delay 27 -> 252, step: 4
7768 12:26:48.252414
7769 12:26:48.255869 Set Vref, RX VrefLevel [Byte0]: 24
7770 12:26:48.259310 [Byte1]: 24
7771 12:26:48.259403
7772 12:26:48.262074 Set Vref, RX VrefLevel [Byte0]: 25
7773 12:26:48.265610 [Byte1]: 25
7774 12:26:48.265697
7775 12:26:48.269126 Set Vref, RX VrefLevel [Byte0]: 26
7776 12:26:48.272487 [Byte1]: 26
7777 12:26:48.276001
7778 12:26:48.276083 Set Vref, RX VrefLevel [Byte0]: 27
7779 12:26:48.278796 [Byte1]: 27
7780 12:26:48.283010
7781 12:26:48.283093 Set Vref, RX VrefLevel [Byte0]: 28
7782 12:26:48.286515 [Byte1]: 28
7783 12:26:48.290625
7784 12:26:48.290720 Set Vref, RX VrefLevel [Byte0]: 29
7785 12:26:48.293929 [Byte1]: 29
7786 12:26:48.298533
7787 12:26:48.298635 Set Vref, RX VrefLevel [Byte0]: 30
7788 12:26:48.301967 [Byte1]: 30
7789 12:26:48.306171
7790 12:26:48.306253 Set Vref, RX VrefLevel [Byte0]: 31
7791 12:26:48.308928 [Byte1]: 31
7792 12:26:48.313119
7793 12:26:48.313201 Set Vref, RX VrefLevel [Byte0]: 32
7794 12:26:48.316644 [Byte1]: 32
7795 12:26:48.320599
7796 12:26:48.320731 Set Vref, RX VrefLevel [Byte0]: 33
7797 12:26:48.324001 [Byte1]: 33
7798 12:26:48.328113
7799 12:26:48.328197 Set Vref, RX VrefLevel [Byte0]: 34
7800 12:26:48.331604 [Byte1]: 34
7801 12:26:48.336182
7802 12:26:48.336280 Set Vref, RX VrefLevel [Byte0]: 35
7803 12:26:48.339631 [Byte1]: 35
7804 12:26:48.343453
7805 12:26:48.343528 Set Vref, RX VrefLevel [Byte0]: 36
7806 12:26:48.346919 [Byte1]: 36
7807 12:26:48.350957
7808 12:26:48.351070 Set Vref, RX VrefLevel [Byte0]: 37
7809 12:26:48.354345 [Byte1]: 37
7810 12:26:48.358807
7811 12:26:48.358952 Set Vref, RX VrefLevel [Byte0]: 38
7812 12:26:48.362221 [Byte1]: 38
7813 12:26:48.365896
7814 12:26:48.366008 Set Vref, RX VrefLevel [Byte0]: 39
7815 12:26:48.369237 [Byte1]: 39
7816 12:26:48.373456
7817 12:26:48.373542 Set Vref, RX VrefLevel [Byte0]: 40
7818 12:26:48.376764 [Byte1]: 40
7819 12:26:48.381566
7820 12:26:48.381652 Set Vref, RX VrefLevel [Byte0]: 41
7821 12:26:48.384404 [Byte1]: 41
7822 12:26:48.388472
7823 12:26:48.388562 Set Vref, RX VrefLevel [Byte0]: 42
7824 12:26:48.391967 [Byte1]: 42
7825 12:26:48.396175
7826 12:26:48.396258 Set Vref, RX VrefLevel [Byte0]: 43
7827 12:26:48.399702 [Byte1]: 43
7828 12:26:48.403766
7829 12:26:48.403848 Set Vref, RX VrefLevel [Byte0]: 44
7830 12:26:48.407091 [Byte1]: 44
7831 12:26:48.411052
7832 12:26:48.411134 Set Vref, RX VrefLevel [Byte0]: 45
7833 12:26:48.414604 [Byte1]: 45
7834 12:26:48.418644
7835 12:26:48.418722 Set Vref, RX VrefLevel [Byte0]: 46
7836 12:26:48.422352 [Byte1]: 46
7837 12:26:48.426195
7838 12:26:48.426294 Set Vref, RX VrefLevel [Byte0]: 47
7839 12:26:48.429382 [Byte1]: 47
7840 12:26:48.433799
7841 12:26:48.433881 Set Vref, RX VrefLevel [Byte0]: 48
7842 12:26:48.437327 [Byte1]: 48
7843 12:26:48.441539
7844 12:26:48.441619 Set Vref, RX VrefLevel [Byte0]: 49
7845 12:26:48.444900 [Byte1]: 49
7846 12:26:48.448858
7847 12:26:48.448952 Set Vref, RX VrefLevel [Byte0]: 50
7848 12:26:48.452254 [Byte1]: 50
7849 12:26:48.456243
7850 12:26:48.456333 Set Vref, RX VrefLevel [Byte0]: 51
7851 12:26:48.459632 [Byte1]: 51
7852 12:26:48.464437
7853 12:26:48.464518 Set Vref, RX VrefLevel [Byte0]: 52
7854 12:26:48.467164 [Byte1]: 52
7855 12:26:48.471392
7856 12:26:48.471481 Set Vref, RX VrefLevel [Byte0]: 53
7857 12:26:48.474901 [Byte1]: 53
7858 12:26:48.479076
7859 12:26:48.479167 Set Vref, RX VrefLevel [Byte0]: 54
7860 12:26:48.482675 [Byte1]: 54
7861 12:26:48.486818
7862 12:26:48.486897 Set Vref, RX VrefLevel [Byte0]: 55
7863 12:26:48.489740 [Byte1]: 55
7864 12:26:48.494461
7865 12:26:48.494567 Set Vref, RX VrefLevel [Byte0]: 56
7866 12:26:48.497095 [Byte1]: 56
7867 12:26:48.502027
7868 12:26:48.502124 Set Vref, RX VrefLevel [Byte0]: 57
7869 12:26:48.504849 [Byte1]: 57
7870 12:26:48.509049
7871 12:26:48.509130 Set Vref, RX VrefLevel [Byte0]: 58
7872 12:26:48.512271 [Byte1]: 58
7873 12:26:48.516838
7874 12:26:48.516924 Set Vref, RX VrefLevel [Byte0]: 59
7875 12:26:48.520302 [Byte1]: 59
7876 12:26:48.524699
7877 12:26:48.524783 Set Vref, RX VrefLevel [Byte0]: 60
7878 12:26:48.527453 [Byte1]: 60
7879 12:26:48.532167
7880 12:26:48.532282 Set Vref, RX VrefLevel [Byte0]: 61
7881 12:26:48.535570 [Byte1]: 61
7882 12:26:48.539531
7883 12:26:48.539614 Set Vref, RX VrefLevel [Byte0]: 62
7884 12:26:48.542668 [Byte1]: 62
7885 12:26:48.547196
7886 12:26:48.547305 Set Vref, RX VrefLevel [Byte0]: 63
7887 12:26:48.550477 [Byte1]: 63
7888 12:26:48.554490
7889 12:26:48.554576 Set Vref, RX VrefLevel [Byte0]: 64
7890 12:26:48.557835 [Byte1]: 64
7891 12:26:48.561852
7892 12:26:48.561936 Set Vref, RX VrefLevel [Byte0]: 65
7893 12:26:48.565219 [Byte1]: 65
7894 12:26:48.569883
7895 12:26:48.569968 Set Vref, RX VrefLevel [Byte0]: 66
7896 12:26:48.572701 [Byte1]: 66
7897 12:26:48.576867
7898 12:26:48.576951 Set Vref, RX VrefLevel [Byte0]: 67
7899 12:26:48.580500 [Byte1]: 67
7900 12:26:48.584621
7901 12:26:48.584729 Set Vref, RX VrefLevel [Byte0]: 68
7902 12:26:48.588210 [Byte1]: 68
7903 12:26:48.592373
7904 12:26:48.592505 Set Vref, RX VrefLevel [Byte0]: 69
7905 12:26:48.595228 [Byte1]: 69
7906 12:26:48.599484
7907 12:26:48.599601 Set Vref, RX VrefLevel [Byte0]: 70
7908 12:26:48.602925 [Byte1]: 70
7909 12:26:48.607085
7910 12:26:48.607193 Set Vref, RX VrefLevel [Byte0]: 71
7911 12:26:48.610621 [Byte1]: 71
7912 12:26:48.614776
7913 12:26:48.614899 Set Vref, RX VrefLevel [Byte0]: 72
7914 12:26:48.617745 [Byte1]: 72
7915 12:26:48.622353
7916 12:26:48.622462 Set Vref, RX VrefLevel [Byte0]: 73
7917 12:26:48.628664 [Byte1]: 73
7918 12:26:48.628780
7919 12:26:48.632146 Final RX Vref Byte 0 = 58 to rank0
7920 12:26:48.634938 Final RX Vref Byte 1 = 64 to rank0
7921 12:26:48.638438 Final RX Vref Byte 0 = 58 to rank1
7922 12:26:48.642067 Final RX Vref Byte 1 = 64 to rank1==
7923 12:26:48.644955 Dram Type= 6, Freq= 0, CH_0, rank 0
7924 12:26:48.648274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7925 12:26:48.648360 ==
7926 12:26:48.648427 DQS Delay:
7927 12:26:48.651607 DQS0 = 0, DQS1 = 0
7928 12:26:48.651692 DQM Delay:
7929 12:26:48.654850 DQM0 = 134, DQM1 = 128
7930 12:26:48.654935 DQ Delay:
7931 12:26:48.658240 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7932 12:26:48.661627 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140
7933 12:26:48.664881 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7934 12:26:48.668181 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7935 12:26:48.668265
7936 12:26:48.668332
7937 12:26:48.671543
7938 12:26:48.671627 [DramC_TX_OE_Calibration] TA2
7939 12:26:48.674790 Original DQ_B0 (3 6) =30, OEN = 27
7940 12:26:48.678174 Original DQ_B1 (3 6) =30, OEN = 27
7941 12:26:48.681681 24, 0x0, End_B0=24 End_B1=24
7942 12:26:48.685281 25, 0x0, End_B0=25 End_B1=25
7943 12:26:48.687915 26, 0x0, End_B0=26 End_B1=26
7944 12:26:48.688005 27, 0x0, End_B0=27 End_B1=27
7945 12:26:48.691345 28, 0x0, End_B0=28 End_B1=28
7946 12:26:48.694855 29, 0x0, End_B0=29 End_B1=29
7947 12:26:48.698265 30, 0x0, End_B0=30 End_B1=30
7948 12:26:48.701826 31, 0x4141, End_B0=30 End_B1=30
7949 12:26:48.701914 Byte0 end_step=30 best_step=27
7950 12:26:48.704648 Byte1 end_step=30 best_step=27
7951 12:26:48.708107 Byte0 TX OE(2T, 0.5T) = (3, 3)
7952 12:26:48.711621 Byte1 TX OE(2T, 0.5T) = (3, 3)
7953 12:26:48.711707
7954 12:26:48.711774
7955 12:26:48.717927 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7956 12:26:48.721387 CH0 RK0: MR19=303, MR18=2420
7957 12:26:48.728201 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7958 12:26:48.728288
7959 12:26:48.730897 ----->DramcWriteLeveling(PI) begin...
7960 12:26:48.730984 ==
7961 12:26:48.734445 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 12:26:48.737992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 12:26:48.741447 ==
7964 12:26:48.741534 Write leveling (Byte 0): 37 => 37
7965 12:26:48.744304 Write leveling (Byte 1): 24 => 24
7966 12:26:48.747859 DramcWriteLeveling(PI) end<-----
7967 12:26:48.747967
7968 12:26:48.748064 ==
7969 12:26:48.751355 Dram Type= 6, Freq= 0, CH_0, rank 1
7970 12:26:48.758104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 12:26:48.758192 ==
7972 12:26:48.761361 [Gating] SW mode calibration
7973 12:26:48.768154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7974 12:26:48.770889 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7975 12:26:48.777655 1 4 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7976 12:26:48.781073 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7977 12:26:48.784452 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 12:26:48.788039 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7979 12:26:48.794893 1 4 16 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (1 1)
7980 12:26:48.797754 1 4 20 | B1->B0 | 3434 3433 | 1 1 | (1 1) (1 1)
7981 12:26:48.801187 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7982 12:26:48.807518 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7983 12:26:48.811015 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 12:26:48.814467 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7985 12:26:48.820772 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7986 12:26:48.824301 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
7987 12:26:48.827965 1 5 16 | B1->B0 | 2c2c 2827 | 0 1 | (0 0) (0 0)
7988 12:26:48.834107 1 5 20 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7989 12:26:48.837434 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7990 12:26:48.840925 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7991 12:26:48.847842 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7992 12:26:48.850816 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7993 12:26:48.854113 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7994 12:26:48.860960 1 6 12 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
7995 12:26:48.864408 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 12:26:48.867709 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7997 12:26:48.874239 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 12:26:48.877445 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 12:26:48.880866 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 12:26:48.887735 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 12:26:48.890326 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 12:26:48.894017 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 12:26:48.900807 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8004 12:26:48.904136 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:26:48.907574 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:26:48.913737 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:26:48.917292 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:26:48.920806 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:26:48.926954 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:26:48.930579 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:26:48.934020 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:26:48.940735 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:26:48.944202 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:26:48.947657 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:26:48.950343 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 12:26:48.956853 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 12:26:48.960364 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8018 12:26:48.963939 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8019 12:26:48.970831 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8020 12:26:48.973688 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 12:26:48.977064 Total UI for P1: 0, mck2ui 16
8022 12:26:48.980412 best dqsien dly found for B0: ( 1, 9, 14)
8023 12:26:48.983722 Total UI for P1: 0, mck2ui 16
8024 12:26:48.987103 best dqsien dly found for B1: ( 1, 9, 12)
8025 12:26:48.990522 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8026 12:26:48.993805 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8027 12:26:48.993904
8028 12:26:48.997174 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8029 12:26:49.000631 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8030 12:26:49.003795 [Gating] SW calibration Done
8031 12:26:49.003874 ==
8032 12:26:49.007136 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 12:26:49.013328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 12:26:49.013409 ==
8035 12:26:49.013484 RX Vref Scan: 0
8036 12:26:49.013552
8037 12:26:49.017005 RX Vref 0 -> 0, step: 1
8038 12:26:49.017083
8039 12:26:49.020348 RX Delay 0 -> 252, step: 8
8040 12:26:49.023148 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8041 12:26:49.026623 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8042 12:26:49.030157 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8043 12:26:49.033768 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8044 12:26:49.039920 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8045 12:26:49.043426 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8046 12:26:49.046857 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8047 12:26:49.050233 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8048 12:26:49.053799 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8049 12:26:49.060076 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8050 12:26:49.063466 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8051 12:26:49.066882 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8052 12:26:49.070501 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8053 12:26:49.073887 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8054 12:26:49.080001 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8055 12:26:49.083456 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8056 12:26:49.083541 ==
8057 12:26:49.086904 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 12:26:49.090205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 12:26:49.090288 ==
8060 12:26:49.093401 DQS Delay:
8061 12:26:49.093486 DQS0 = 0, DQS1 = 0
8062 12:26:49.093553 DQM Delay:
8063 12:26:49.096851 DQM0 = 137, DQM1 = 130
8064 12:26:49.096935 DQ Delay:
8065 12:26:49.100313 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8066 12:26:49.103840 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8067 12:26:49.107132 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =123
8068 12:26:49.113462 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8069 12:26:49.113547
8070 12:26:49.113613
8071 12:26:49.113675 ==
8072 12:26:49.117218 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 12:26:49.119947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 12:26:49.120059 ==
8075 12:26:49.120158
8076 12:26:49.120250
8077 12:26:49.123277 TX Vref Scan disable
8078 12:26:49.123375 == TX Byte 0 ==
8079 12:26:49.130110 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8080 12:26:49.133610 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8081 12:26:49.133719 == TX Byte 1 ==
8082 12:26:49.140044 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8083 12:26:49.143548 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8084 12:26:49.143662 ==
8085 12:26:49.146976 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 12:26:49.149784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 12:26:49.149895 ==
8088 12:26:49.165559
8089 12:26:49.169067 TX Vref early break, caculate TX vref
8090 12:26:49.171897 TX Vref=16, minBit 1, minWin=23, winSum=387
8091 12:26:49.175293 TX Vref=18, minBit 4, minWin=23, winSum=394
8092 12:26:49.178874 TX Vref=20, minBit 0, minWin=24, winSum=401
8093 12:26:49.182315 TX Vref=22, minBit 3, minWin=24, winSum=410
8094 12:26:49.185487 TX Vref=24, minBit 1, minWin=25, winSum=416
8095 12:26:49.191735 TX Vref=26, minBit 4, minWin=25, winSum=427
8096 12:26:49.195275 TX Vref=28, minBit 0, minWin=25, winSum=424
8097 12:26:49.198630 TX Vref=30, minBit 3, minWin=25, winSum=417
8098 12:26:49.201954 TX Vref=32, minBit 0, minWin=25, winSum=411
8099 12:26:49.205226 TX Vref=34, minBit 0, minWin=24, winSum=400
8100 12:26:49.211834 [TxChooseVref] Worse bit 4, Min win 25, Win sum 427, Final Vref 26
8101 12:26:49.211921
8102 12:26:49.215623 Final TX Range 0 Vref 26
8103 12:26:49.215709
8104 12:26:49.215777 ==
8105 12:26:49.218249 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 12:26:49.221490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 12:26:49.221577 ==
8108 12:26:49.221645
8109 12:26:49.221709
8110 12:26:49.225204 TX Vref Scan disable
8111 12:26:49.231666 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8112 12:26:49.231752 == TX Byte 0 ==
8113 12:26:49.234860 u2DelayCellOfst[0]=13 cells (4 PI)
8114 12:26:49.238451 u2DelayCellOfst[1]=17 cells (5 PI)
8115 12:26:49.242041 u2DelayCellOfst[2]=10 cells (3 PI)
8116 12:26:49.244838 u2DelayCellOfst[3]=10 cells (3 PI)
8117 12:26:49.248399 u2DelayCellOfst[4]=10 cells (3 PI)
8118 12:26:49.251769 u2DelayCellOfst[5]=0 cells (0 PI)
8119 12:26:49.254513 u2DelayCellOfst[6]=17 cells (5 PI)
8120 12:26:49.257881 u2DelayCellOfst[7]=17 cells (5 PI)
8121 12:26:49.261227 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8122 12:26:49.264582 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8123 12:26:49.268015 == TX Byte 1 ==
8124 12:26:49.271390 u2DelayCellOfst[8]=3 cells (1 PI)
8125 12:26:49.271464 u2DelayCellOfst[9]=0 cells (0 PI)
8126 12:26:49.274954 u2DelayCellOfst[10]=6 cells (2 PI)
8127 12:26:49.278447 u2DelayCellOfst[11]=3 cells (1 PI)
8128 12:26:49.281998 u2DelayCellOfst[12]=10 cells (3 PI)
8129 12:26:49.284668 u2DelayCellOfst[13]=10 cells (3 PI)
8130 12:26:49.288228 u2DelayCellOfst[14]=13 cells (4 PI)
8131 12:26:49.291558 u2DelayCellOfst[15]=10 cells (3 PI)
8132 12:26:49.294865 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8133 12:26:49.301779 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8134 12:26:49.301893 DramC Write-DBI on
8135 12:26:49.301988 ==
8136 12:26:49.304561 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 12:26:49.311425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 12:26:49.311503 ==
8139 12:26:49.311607
8140 12:26:49.311673
8141 12:26:49.311732 TX Vref Scan disable
8142 12:26:49.315286 == TX Byte 0 ==
8143 12:26:49.318599 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8144 12:26:49.322035 == TX Byte 1 ==
8145 12:26:49.325357 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8146 12:26:49.328724 DramC Write-DBI off
8147 12:26:49.328799
8148 12:26:49.328863 [DATLAT]
8149 12:26:49.328923 Freq=1600, CH0 RK1
8150 12:26:49.328982
8151 12:26:49.331980 DATLAT Default: 0xf
8152 12:26:49.332054 0, 0xFFFF, sum = 0
8153 12:26:49.335139 1, 0xFFFF, sum = 0
8154 12:26:49.338222 2, 0xFFFF, sum = 0
8155 12:26:49.338301 3, 0xFFFF, sum = 0
8156 12:26:49.341989 4, 0xFFFF, sum = 0
8157 12:26:49.342069 5, 0xFFFF, sum = 0
8158 12:26:49.344789 6, 0xFFFF, sum = 0
8159 12:26:49.344866 7, 0xFFFF, sum = 0
8160 12:26:49.348406 8, 0xFFFF, sum = 0
8161 12:26:49.348530 9, 0xFFFF, sum = 0
8162 12:26:49.351890 10, 0xFFFF, sum = 0
8163 12:26:49.352003 11, 0xFFFF, sum = 0
8164 12:26:49.355391 12, 0xFFFF, sum = 0
8165 12:26:49.355469 13, 0xFFFF, sum = 0
8166 12:26:49.358160 14, 0x0, sum = 1
8167 12:26:49.358238 15, 0x0, sum = 2
8168 12:26:49.361658 16, 0x0, sum = 3
8169 12:26:49.361737 17, 0x0, sum = 4
8170 12:26:49.365020 best_step = 15
8171 12:26:49.365122
8172 12:26:49.365215 ==
8173 12:26:49.368289 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 12:26:49.371712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 12:26:49.371792 ==
8176 12:26:49.371857 RX Vref Scan: 0
8177 12:26:49.374620
8178 12:26:49.374695 RX Vref 0 -> 0, step: 1
8179 12:26:49.374760
8180 12:26:49.377969 RX Delay 19 -> 252, step: 4
8181 12:26:49.381510 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8182 12:26:49.388413 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8183 12:26:49.391332 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8184 12:26:49.394664 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8185 12:26:49.398110 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8186 12:26:49.401413 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8187 12:26:49.408476 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8188 12:26:49.411243 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8189 12:26:49.414631 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8190 12:26:49.418233 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8191 12:26:49.421652 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8192 12:26:49.428027 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8193 12:26:49.431314 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8194 12:26:49.434597 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8195 12:26:49.438042 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8196 12:26:49.441321 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8197 12:26:49.441425 ==
8198 12:26:49.445244 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 12:26:49.451619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 12:26:49.451699 ==
8201 12:26:49.451766 DQS Delay:
8202 12:26:49.455155 DQS0 = 0, DQS1 = 0
8203 12:26:49.455256 DQM Delay:
8204 12:26:49.455366 DQM0 = 134, DQM1 = 127
8205 12:26:49.458008 DQ Delay:
8206 12:26:49.461625 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8207 12:26:49.465162 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8208 12:26:49.468068 DQ8 =120, DQ9 =116, DQ10 =130, DQ11 =118
8209 12:26:49.471402 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8210 12:26:49.471478
8211 12:26:49.471543
8212 12:26:49.471604
8213 12:26:49.474572 [DramC_TX_OE_Calibration] TA2
8214 12:26:49.477838 Original DQ_B0 (3 6) =30, OEN = 27
8215 12:26:49.481714 Original DQ_B1 (3 6) =30, OEN = 27
8216 12:26:49.484509 24, 0x0, End_B0=24 End_B1=24
8217 12:26:49.488005 25, 0x0, End_B0=25 End_B1=25
8218 12:26:49.488085 26, 0x0, End_B0=26 End_B1=26
8219 12:26:49.491455 27, 0x0, End_B0=27 End_B1=27
8220 12:26:49.494886 28, 0x0, End_B0=28 End_B1=28
8221 12:26:49.497802 29, 0x0, End_B0=29 End_B1=29
8222 12:26:49.497881 30, 0x0, End_B0=30 End_B1=30
8223 12:26:49.501206 31, 0x4141, End_B0=30 End_B1=30
8224 12:26:49.504588 Byte0 end_step=30 best_step=27
8225 12:26:49.507974 Byte1 end_step=30 best_step=27
8226 12:26:49.511408 Byte0 TX OE(2T, 0.5T) = (3, 3)
8227 12:26:49.514783 Byte1 TX OE(2T, 0.5T) = (3, 3)
8228 12:26:49.514857
8229 12:26:49.514923
8230 12:26:49.521030 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8231 12:26:49.524570 CH0 RK1: MR19=303, MR18=2109
8232 12:26:49.531238 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8233 12:26:49.534536 [RxdqsGatingPostProcess] freq 1600
8234 12:26:49.538165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8235 12:26:49.540815 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 12:26:49.544125 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 12:26:49.548101 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 12:26:49.551231 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 12:26:49.554673 best DQS0 dly(2T, 0.5T) = (1, 1)
8240 12:26:49.557918 best DQS1 dly(2T, 0.5T) = (1, 1)
8241 12:26:49.561317 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8242 12:26:49.564205 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8243 12:26:49.567706 Pre-setting of DQS Precalculation
8244 12:26:49.571270 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8245 12:26:49.571388 ==
8246 12:26:49.574721 Dram Type= 6, Freq= 0, CH_1, rank 0
8247 12:26:49.578164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 12:26:49.580867 ==
8249 12:26:49.584295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8250 12:26:49.587706 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8251 12:26:49.594639 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8252 12:26:49.601040 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8253 12:26:49.607849 [CA 0] Center 41 (12~71) winsize 60
8254 12:26:49.611156 [CA 1] Center 41 (12~71) winsize 60
8255 12:26:49.615222 [CA 2] Center 38 (9~68) winsize 60
8256 12:26:49.618533 [CA 3] Center 38 (9~67) winsize 59
8257 12:26:49.621337 [CA 4] Center 37 (8~67) winsize 60
8258 12:26:49.624903 [CA 5] Center 37 (8~66) winsize 59
8259 12:26:49.624991
8260 12:26:49.628317 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8261 12:26:49.628420
8262 12:26:49.631271 [CATrainingPosCal] consider 1 rank data
8263 12:26:49.634692 u2DelayCellTimex100 = 285/100 ps
8264 12:26:49.638194 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8265 12:26:49.644899 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8266 12:26:49.648122 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8267 12:26:49.651421 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8268 12:26:49.654959 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8269 12:26:49.658347 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8270 12:26:49.658461
8271 12:26:49.661744 CA PerBit enable=1, Macro0, CA PI delay=37
8272 12:26:49.661847
8273 12:26:49.664968 [CBTSetCACLKResult] CA Dly = 37
8274 12:26:49.665070 CS Dly: 10 (0~41)
8275 12:26:49.671143 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8276 12:26:49.674886 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8277 12:26:49.674960 ==
8278 12:26:49.678414 Dram Type= 6, Freq= 0, CH_1, rank 1
8279 12:26:49.681259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 12:26:49.681331 ==
8281 12:26:49.688095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8282 12:26:49.691470 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8283 12:26:49.698093 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8284 12:26:49.701382 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8285 12:26:49.711189 [CA 0] Center 42 (12~72) winsize 61
8286 12:26:49.714658 [CA 1] Center 42 (12~72) winsize 61
8287 12:26:49.718005 [CA 2] Center 38 (9~68) winsize 60
8288 12:26:49.721293 [CA 3] Center 38 (8~68) winsize 61
8289 12:26:49.724611 [CA 4] Center 38 (8~68) winsize 61
8290 12:26:49.728143 [CA 5] Center 37 (8~67) winsize 60
8291 12:26:49.728229
8292 12:26:49.730908 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8293 12:26:49.731016
8294 12:26:49.734282 [CATrainingPosCal] consider 2 rank data
8295 12:26:49.737755 u2DelayCellTimex100 = 285/100 ps
8296 12:26:49.741239 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8297 12:26:49.748006 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8298 12:26:49.750789 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8299 12:26:49.754179 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8300 12:26:49.757895 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8301 12:26:49.761176 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8302 12:26:49.761258
8303 12:26:49.764490 CA PerBit enable=1, Macro0, CA PI delay=37
8304 12:26:49.764572
8305 12:26:49.767803 [CBTSetCACLKResult] CA Dly = 37
8306 12:26:49.771028 CS Dly: 12 (0~45)
8307 12:26:49.774195 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8308 12:26:49.777751 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8309 12:26:49.777833
8310 12:26:49.781218 ----->DramcWriteLeveling(PI) begin...
8311 12:26:49.781310 ==
8312 12:26:49.784071 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 12:26:49.790873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 12:26:49.790956 ==
8315 12:26:49.794262 Write leveling (Byte 0): 25 => 25
8316 12:26:49.794343 Write leveling (Byte 1): 28 => 28
8317 12:26:49.797698 DramcWriteLeveling(PI) end<-----
8318 12:26:49.797779
8319 12:26:49.797844 ==
8320 12:26:49.800498 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 12:26:49.807127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 12:26:49.807209 ==
8323 12:26:49.810576 [Gating] SW mode calibration
8324 12:26:49.817571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8325 12:26:49.820413 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8326 12:26:49.827575 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 12:26:49.830950 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 12:26:49.833712 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8329 12:26:49.840728 1 4 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8330 12:26:49.844271 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 12:26:49.847011 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 12:26:49.854076 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 12:26:49.857599 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 12:26:49.860414 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 12:26:49.867125 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 12:26:49.870432 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8337 12:26:49.873862 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8338 12:26:49.880616 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 12:26:49.884062 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 12:26:49.886945 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 12:26:49.890509 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 12:26:49.897470 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:26:49.900841 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:26:49.903564 1 6 8 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
8345 12:26:49.910741 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8346 12:26:49.913529 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:26:49.917105 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 12:26:49.923431 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 12:26:49.926989 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 12:26:49.930426 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 12:26:49.937162 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:26:49.940496 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8353 12:26:49.943425 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8354 12:26:49.950427 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:26:49.953811 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:26:49.956632 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:26:49.963702 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:26:49.966401 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:26:49.969916 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:26:49.976633 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:26:49.980045 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:26:49.983296 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:26:49.989959 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:26:49.993282 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:26:49.996588 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:26:50.002889 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:26:50.006296 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 12:26:50.009766 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8369 12:26:50.016108 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8370 12:26:50.019302 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 12:26:50.022870 Total UI for P1: 0, mck2ui 16
8372 12:26:50.026351 best dqsien dly found for B0: ( 1, 9, 10)
8373 12:26:50.029991 Total UI for P1: 0, mck2ui 16
8374 12:26:50.032598 best dqsien dly found for B1: ( 1, 9, 10)
8375 12:26:50.035967 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8376 12:26:50.039251 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8377 12:26:50.039373
8378 12:26:50.043230 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8379 12:26:50.046608 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8380 12:26:50.049935 [Gating] SW calibration Done
8381 12:26:50.050018 ==
8382 12:26:50.052772 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 12:26:50.056384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 12:26:50.059248 ==
8385 12:26:50.059338 RX Vref Scan: 0
8386 12:26:50.059420
8387 12:26:50.062638 RX Vref 0 -> 0, step: 1
8388 12:26:50.062746
8389 12:26:50.062842 RX Delay 0 -> 252, step: 8
8390 12:26:50.069543 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8391 12:26:50.072867 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8392 12:26:50.076399 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8393 12:26:50.079801 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8394 12:26:50.082581 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8395 12:26:50.089451 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8396 12:26:50.093164 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8397 12:26:50.096457 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8398 12:26:50.099745 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8399 12:26:50.103043 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8400 12:26:50.109391 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8401 12:26:50.112858 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8402 12:26:50.116351 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8403 12:26:50.119310 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8404 12:26:50.122840 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8405 12:26:50.129495 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8406 12:26:50.129657 ==
8407 12:26:50.132289 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 12:26:50.135839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 12:26:50.136000 ==
8410 12:26:50.136108 DQS Delay:
8411 12:26:50.139303 DQS0 = 0, DQS1 = 0
8412 12:26:50.139436 DQM Delay:
8413 12:26:50.143002 DQM0 = 137, DQM1 = 133
8414 12:26:50.143141 DQ Delay:
8415 12:26:50.145640 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8416 12:26:50.149728 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8417 12:26:50.153006 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8418 12:26:50.156369 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8419 12:26:50.156854
8420 12:26:50.159833
8421 12:26:50.160225 ==
8422 12:26:50.162563 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 12:26:50.166069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 12:26:50.166656 ==
8425 12:26:50.167159
8426 12:26:50.167598
8427 12:26:50.169465 TX Vref Scan disable
8428 12:26:50.169937 == TX Byte 0 ==
8429 12:26:50.176270 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8430 12:26:50.179591 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8431 12:26:50.180030 == TX Byte 1 ==
8432 12:26:50.183200 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8433 12:26:50.189271 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8434 12:26:50.189852 ==
8435 12:26:50.192998 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 12:26:50.196395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 12:26:50.196863 ==
8438 12:26:50.209265
8439 12:26:50.212465 TX Vref early break, caculate TX vref
8440 12:26:50.215596 TX Vref=16, minBit 6, minWin=22, winSum=378
8441 12:26:50.219068 TX Vref=18, minBit 1, minWin=23, winSum=388
8442 12:26:50.222611 TX Vref=20, minBit 6, minWin=23, winSum=396
8443 12:26:50.226204 TX Vref=22, minBit 0, minWin=25, winSum=409
8444 12:26:50.228956 TX Vref=24, minBit 0, minWin=25, winSum=414
8445 12:26:50.235575 TX Vref=26, minBit 0, minWin=26, winSum=423
8446 12:26:50.239238 TX Vref=28, minBit 0, minWin=26, winSum=429
8447 12:26:50.242508 TX Vref=30, minBit 0, minWin=25, winSum=421
8448 12:26:50.245519 TX Vref=32, minBit 0, minWin=24, winSum=413
8449 12:26:50.248975 TX Vref=34, minBit 0, minWin=24, winSum=402
8450 12:26:50.255249 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8451 12:26:50.255382
8452 12:26:50.258569 Final TX Range 0 Vref 28
8453 12:26:50.258702
8454 12:26:50.258769 ==
8455 12:26:50.261921 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 12:26:50.265194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 12:26:50.265278 ==
8458 12:26:50.265345
8459 12:26:50.265407
8460 12:26:50.268624 TX Vref Scan disable
8461 12:26:50.275260 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8462 12:26:50.275384 == TX Byte 0 ==
8463 12:26:50.278176 u2DelayCellOfst[0]=17 cells (5 PI)
8464 12:26:50.281603 u2DelayCellOfst[1]=10 cells (3 PI)
8465 12:26:50.285101 u2DelayCellOfst[2]=0 cells (0 PI)
8466 12:26:50.288618 u2DelayCellOfst[3]=6 cells (2 PI)
8467 12:26:50.291352 u2DelayCellOfst[4]=10 cells (3 PI)
8468 12:26:50.294791 u2DelayCellOfst[5]=17 cells (5 PI)
8469 12:26:50.298342 u2DelayCellOfst[6]=17 cells (5 PI)
8470 12:26:50.301964 u2DelayCellOfst[7]=3 cells (1 PI)
8471 12:26:50.305273 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8472 12:26:50.308667 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8473 12:26:50.312004 == TX Byte 1 ==
8474 12:26:50.312080 u2DelayCellOfst[8]=0 cells (0 PI)
8475 12:26:50.314646 u2DelayCellOfst[9]=3 cells (1 PI)
8476 12:26:50.318642 u2DelayCellOfst[10]=13 cells (4 PI)
8477 12:26:50.321829 u2DelayCellOfst[11]=6 cells (2 PI)
8478 12:26:50.324960 u2DelayCellOfst[12]=17 cells (5 PI)
8479 12:26:50.328209 u2DelayCellOfst[13]=17 cells (5 PI)
8480 12:26:50.331639 u2DelayCellOfst[14]=17 cells (5 PI)
8481 12:26:50.335090 u2DelayCellOfst[15]=17 cells (5 PI)
8482 12:26:50.338551 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8483 12:26:50.344651 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8484 12:26:50.344733 DramC Write-DBI on
8485 12:26:50.344800 ==
8486 12:26:50.348118 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 12:26:50.351597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 12:26:50.355087 ==
8489 12:26:50.355178
8490 12:26:50.355274
8491 12:26:50.355394 TX Vref Scan disable
8492 12:26:50.358473 == TX Byte 0 ==
8493 12:26:50.361230 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8494 12:26:50.364523 == TX Byte 1 ==
8495 12:26:50.367871 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8496 12:26:50.371199 DramC Write-DBI off
8497 12:26:50.371305
8498 12:26:50.371413 [DATLAT]
8499 12:26:50.371480 Freq=1600, CH1 RK0
8500 12:26:50.371548
8501 12:26:50.375196 DATLAT Default: 0xf
8502 12:26:50.375297 0, 0xFFFF, sum = 0
8503 12:26:50.377943 1, 0xFFFF, sum = 0
8504 12:26:50.378019 2, 0xFFFF, sum = 0
8505 12:26:50.381534 3, 0xFFFF, sum = 0
8506 12:26:50.385001 4, 0xFFFF, sum = 0
8507 12:26:50.385089 5, 0xFFFF, sum = 0
8508 12:26:50.388422 6, 0xFFFF, sum = 0
8509 12:26:50.388525 7, 0xFFFF, sum = 0
8510 12:26:50.391278 8, 0xFFFF, sum = 0
8511 12:26:50.391404 9, 0xFFFF, sum = 0
8512 12:26:50.394796 10, 0xFFFF, sum = 0
8513 12:26:50.394896 11, 0xFFFF, sum = 0
8514 12:26:50.398112 12, 0xFFFF, sum = 0
8515 12:26:50.398197 13, 0xFFFF, sum = 0
8516 12:26:50.401764 14, 0x0, sum = 1
8517 12:26:50.401848 15, 0x0, sum = 2
8518 12:26:50.404462 16, 0x0, sum = 3
8519 12:26:50.404546 17, 0x0, sum = 4
8520 12:26:50.407860 best_step = 15
8521 12:26:50.407943
8522 12:26:50.408009 ==
8523 12:26:50.411405 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 12:26:50.414746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 12:26:50.414855 ==
8526 12:26:50.414923 RX Vref Scan: 1
8527 12:26:50.418178
8528 12:26:50.418261 Set Vref Range= 24 -> 127
8529 12:26:50.418328
8530 12:26:50.421485 RX Vref 24 -> 127, step: 1
8531 12:26:50.421568
8532 12:26:50.424643 RX Delay 27 -> 252, step: 4
8533 12:26:50.424726
8534 12:26:50.427971 Set Vref, RX VrefLevel [Byte0]: 24
8535 12:26:50.431705 [Byte1]: 24
8536 12:26:50.431787
8537 12:26:50.435070 Set Vref, RX VrefLevel [Byte0]: 25
8538 12:26:50.438357 [Byte1]: 25
8539 12:26:50.438440
8540 12:26:50.441766 Set Vref, RX VrefLevel [Byte0]: 26
8541 12:26:50.444494 [Byte1]: 26
8542 12:26:50.448510
8543 12:26:50.448592 Set Vref, RX VrefLevel [Byte0]: 27
8544 12:26:50.451847 [Byte1]: 27
8545 12:26:50.455987
8546 12:26:50.456069 Set Vref, RX VrefLevel [Byte0]: 28
8547 12:26:50.459569 [Byte1]: 28
8548 12:26:50.463661
8549 12:26:50.463770 Set Vref, RX VrefLevel [Byte0]: 29
8550 12:26:50.466374 [Byte1]: 29
8551 12:26:50.471073
8552 12:26:50.471157 Set Vref, RX VrefLevel [Byte0]: 30
8553 12:26:50.474380 [Byte1]: 30
8554 12:26:50.478340
8555 12:26:50.478423 Set Vref, RX VrefLevel [Byte0]: 31
8556 12:26:50.481786 [Byte1]: 31
8557 12:26:50.486153
8558 12:26:50.486234 Set Vref, RX VrefLevel [Byte0]: 32
8559 12:26:50.489618 [Byte1]: 32
8560 12:26:50.493939
8561 12:26:50.494022 Set Vref, RX VrefLevel [Byte0]: 33
8562 12:26:50.497140 [Byte1]: 33
8563 12:26:50.501285
8564 12:26:50.501367 Set Vref, RX VrefLevel [Byte0]: 34
8565 12:26:50.504015 [Byte1]: 34
8566 12:26:50.509008
8567 12:26:50.509091 Set Vref, RX VrefLevel [Byte0]: 35
8568 12:26:50.511863 [Byte1]: 35
8569 12:26:50.515830
8570 12:26:50.515912 Set Vref, RX VrefLevel [Byte0]: 36
8571 12:26:50.519773 [Byte1]: 36
8572 12:26:50.523410
8573 12:26:50.523492 Set Vref, RX VrefLevel [Byte0]: 37
8574 12:26:50.526747 [Byte1]: 37
8575 12:26:50.531317
8576 12:26:50.531437 Set Vref, RX VrefLevel [Byte0]: 38
8577 12:26:50.534581 [Byte1]: 38
8578 12:26:50.539040
8579 12:26:50.539123 Set Vref, RX VrefLevel [Byte0]: 39
8580 12:26:50.541804 [Byte1]: 39
8581 12:26:50.546358
8582 12:26:50.546440 Set Vref, RX VrefLevel [Byte0]: 40
8583 12:26:50.549763 [Byte1]: 40
8584 12:26:50.553711
8585 12:26:50.553793 Set Vref, RX VrefLevel [Byte0]: 41
8586 12:26:50.557032 [Byte1]: 41
8587 12:26:50.561248
8588 12:26:50.561324 Set Vref, RX VrefLevel [Byte0]: 42
8589 12:26:50.564722 [Byte1]: 42
8590 12:26:50.568873
8591 12:26:50.568949 Set Vref, RX VrefLevel [Byte0]: 43
8592 12:26:50.572441 [Byte1]: 43
8593 12:26:50.576730
8594 12:26:50.576803 Set Vref, RX VrefLevel [Byte0]: 44
8595 12:26:50.580005 [Byte1]: 44
8596 12:26:50.583951
8597 12:26:50.584030 Set Vref, RX VrefLevel [Byte0]: 45
8598 12:26:50.587202 [Byte1]: 45
8599 12:26:50.591310
8600 12:26:50.591421 Set Vref, RX VrefLevel [Byte0]: 46
8601 12:26:50.594796 [Byte1]: 46
8602 12:26:50.598979
8603 12:26:50.599059 Set Vref, RX VrefLevel [Byte0]: 47
8604 12:26:50.602413 [Byte1]: 47
8605 12:26:50.606608
8606 12:26:50.606680 Set Vref, RX VrefLevel [Byte0]: 48
8607 12:26:50.610141 [Byte1]: 48
8608 12:26:50.614371
8609 12:26:50.614441 Set Vref, RX VrefLevel [Byte0]: 49
8610 12:26:50.617161 [Byte1]: 49
8611 12:26:50.621369
8612 12:26:50.621445 Set Vref, RX VrefLevel [Byte0]: 50
8613 12:26:50.624661 [Byte1]: 50
8614 12:26:50.628749
8615 12:26:50.628823 Set Vref, RX VrefLevel [Byte0]: 51
8616 12:26:50.632313 [Byte1]: 51
8617 12:26:50.636834
8618 12:26:50.636913 Set Vref, RX VrefLevel [Byte0]: 52
8619 12:26:50.640216 [Byte1]: 52
8620 12:26:50.644167
8621 12:26:50.644243 Set Vref, RX VrefLevel [Byte0]: 53
8622 12:26:50.647355 [Byte1]: 53
8623 12:26:50.651550
8624 12:26:50.651627 Set Vref, RX VrefLevel [Byte0]: 54
8625 12:26:50.655018 [Byte1]: 54
8626 12:26:50.658993
8627 12:26:50.659066 Set Vref, RX VrefLevel [Byte0]: 55
8628 12:26:50.662860 [Byte1]: 55
8629 12:26:50.667110
8630 12:26:50.667207 Set Vref, RX VrefLevel [Byte0]: 56
8631 12:26:50.669821 [Byte1]: 56
8632 12:26:50.674162
8633 12:26:50.674269 Set Vref, RX VrefLevel [Byte0]: 57
8634 12:26:50.677465 [Byte1]: 57
8635 12:26:50.681661
8636 12:26:50.681743 Set Vref, RX VrefLevel [Byte0]: 58
8637 12:26:50.685065 [Byte1]: 58
8638 12:26:50.689654
8639 12:26:50.689750 Set Vref, RX VrefLevel [Byte0]: 59
8640 12:26:50.692996 [Byte1]: 59
8641 12:26:50.696949
8642 12:26:50.697056 Set Vref, RX VrefLevel [Byte0]: 60
8643 12:26:50.700025 [Byte1]: 60
8644 12:26:50.704160
8645 12:26:50.704235 Set Vref, RX VrefLevel [Byte0]: 61
8646 12:26:50.707761 [Byte1]: 61
8647 12:26:50.711885
8648 12:26:50.711970 Set Vref, RX VrefLevel [Byte0]: 62
8649 12:26:50.715276 [Byte1]: 62
8650 12:26:50.719521
8651 12:26:50.719605 Set Vref, RX VrefLevel [Byte0]: 63
8652 12:26:50.722826 [Byte1]: 63
8653 12:26:50.727039
8654 12:26:50.727121 Set Vref, RX VrefLevel [Byte0]: 64
8655 12:26:50.730427 [Byte1]: 64
8656 12:26:50.734807
8657 12:26:50.734902 Set Vref, RX VrefLevel [Byte0]: 65
8658 12:26:50.738323 [Byte1]: 65
8659 12:26:50.742100
8660 12:26:50.742217 Set Vref, RX VrefLevel [Byte0]: 66
8661 12:26:50.745368 [Byte1]: 66
8662 12:26:50.750151
8663 12:26:50.750274 Set Vref, RX VrefLevel [Byte0]: 67
8664 12:26:50.753394 [Byte1]: 67
8665 12:26:50.757607
8666 12:26:50.757759 Set Vref, RX VrefLevel [Byte0]: 68
8667 12:26:50.760369 [Byte1]: 68
8668 12:26:50.764546
8669 12:26:50.764723 Set Vref, RX VrefLevel [Byte0]: 69
8670 12:26:50.767983 [Byte1]: 69
8671 12:26:50.772633
8672 12:26:50.772876 Set Vref, RX VrefLevel [Byte0]: 70
8673 12:26:50.776150 [Byte1]: 70
8674 12:26:50.780314
8675 12:26:50.780618 Set Vref, RX VrefLevel [Byte0]: 71
8676 12:26:50.783171 [Byte1]: 71
8677 12:26:50.787247
8678 12:26:50.787715 Set Vref, RX VrefLevel [Byte0]: 72
8679 12:26:50.790743 [Byte1]: 72
8680 12:26:50.795415
8681 12:26:50.795843 Set Vref, RX VrefLevel [Byte0]: 73
8682 12:26:50.798357 [Byte1]: 73
8683 12:26:50.802535
8684 12:26:50.802960 Set Vref, RX VrefLevel [Byte0]: 74
8685 12:26:50.805908 [Byte1]: 74
8686 12:26:50.809950
8687 12:26:50.810378 Set Vref, RX VrefLevel [Byte0]: 75
8688 12:26:50.813340 [Byte1]: 75
8689 12:26:50.817555
8690 12:26:50.817982 Final RX Vref Byte 0 = 57 to rank0
8691 12:26:50.821024 Final RX Vref Byte 1 = 56 to rank0
8692 12:26:50.824434 Final RX Vref Byte 0 = 57 to rank1
8693 12:26:50.827899 Final RX Vref Byte 1 = 56 to rank1==
8694 12:26:50.831403 Dram Type= 6, Freq= 0, CH_1, rank 0
8695 12:26:50.837886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8696 12:26:50.838319 ==
8697 12:26:50.838662 DQS Delay:
8698 12:26:50.838980 DQS0 = 0, DQS1 = 0
8699 12:26:50.840855 DQM Delay:
8700 12:26:50.841280 DQM0 = 134, DQM1 = 131
8701 12:26:50.844411 DQ Delay:
8702 12:26:50.847687 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8703 12:26:50.850983 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8704 12:26:50.854365 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8705 12:26:50.857618 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8706 12:26:50.858099
8707 12:26:50.858487
8708 12:26:50.858824
8709 12:26:50.860939 [DramC_TX_OE_Calibration] TA2
8710 12:26:50.864162 Original DQ_B0 (3 6) =30, OEN = 27
8711 12:26:50.867636 Original DQ_B1 (3 6) =30, OEN = 27
8712 12:26:50.871139 24, 0x0, End_B0=24 End_B1=24
8713 12:26:50.871663 25, 0x0, End_B0=25 End_B1=25
8714 12:26:50.874516 26, 0x0, End_B0=26 End_B1=26
8715 12:26:50.877952 27, 0x0, End_B0=27 End_B1=27
8716 12:26:50.881193 28, 0x0, End_B0=28 End_B1=28
8717 12:26:50.881628 29, 0x0, End_B0=29 End_B1=29
8718 12:26:50.884623 30, 0x0, End_B0=30 End_B1=30
8719 12:26:50.887440 31, 0x4141, End_B0=30 End_B1=30
8720 12:26:50.890992 Byte0 end_step=30 best_step=27
8721 12:26:50.894354 Byte1 end_step=30 best_step=27
8722 12:26:50.897918 Byte0 TX OE(2T, 0.5T) = (3, 3)
8723 12:26:50.898148 Byte1 TX OE(2T, 0.5T) = (3, 3)
8724 12:26:50.898332
8725 12:26:50.898504
8726 12:26:50.907666 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8727 12:26:50.911130 CH1 RK0: MR19=303, MR18=1826
8728 12:26:50.917484 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8729 12:26:50.917717
8730 12:26:50.920934 ----->DramcWriteLeveling(PI) begin...
8731 12:26:50.921168 ==
8732 12:26:50.924289 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 12:26:50.927526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 12:26:50.927892 ==
8735 12:26:50.931054 Write leveling (Byte 0): 25 => 25
8736 12:26:50.934468 Write leveling (Byte 1): 29 => 29
8737 12:26:50.937800 DramcWriteLeveling(PI) end<-----
8738 12:26:50.938232
8739 12:26:50.938575 ==
8740 12:26:50.941289 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 12:26:50.944721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 12:26:50.945153 ==
8743 12:26:50.947517 [Gating] SW mode calibration
8744 12:26:50.954455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8745 12:26:50.960914 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8746 12:26:50.964248 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 12:26:50.967469 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 12:26:50.974682 1 4 8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
8749 12:26:50.978259 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8750 12:26:50.981092 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 12:26:50.987662 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 12:26:50.991072 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 12:26:50.994398 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 12:26:51.001425 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 12:26:51.004224 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8756 12:26:51.007644 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (1 0) (1 1)
8757 12:26:51.011207 1 5 12 | B1->B0 | 2626 3030 | 0 0 | (0 0) (1 0)
8758 12:26:51.023217 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 12:26:51.023307 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 12:26:51.023887 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 12:26:51.030443 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 12:26:51.033821 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 12:26:51.037329 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 12:26:51.043897 1 6 8 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
8765 12:26:51.047442 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 12:26:51.050846 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 12:26:51.057182 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 12:26:51.060612 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 12:26:51.064036 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 12:26:51.070580 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 12:26:51.073682 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8772 12:26:51.077639 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8773 12:26:51.083709 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8774 12:26:51.087109 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8775 12:26:51.090901 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:26:51.097764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:26:51.100664 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:26:51.103912 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:26:51.110205 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:26:51.113718 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:26:51.117242 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:26:51.123969 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:26:51.127317 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:26:51.130291 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:26:51.137120 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:26:51.140748 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:26:51.144112 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8788 12:26:51.147455 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8789 12:26:51.153842 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8790 12:26:51.157280 Total UI for P1: 0, mck2ui 16
8791 12:26:51.160783 best dqsien dly found for B1: ( 1, 9, 6)
8792 12:26:51.163524 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 12:26:51.167086 Total UI for P1: 0, mck2ui 16
8794 12:26:51.170385 best dqsien dly found for B0: ( 1, 9, 10)
8795 12:26:51.173416 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8796 12:26:51.176797 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8797 12:26:51.176909
8798 12:26:51.180064 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8799 12:26:51.186702 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8800 12:26:51.186818 [Gating] SW calibration Done
8801 12:26:51.186913 ==
8802 12:26:51.190076 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 12:26:51.196134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 12:26:51.196223 ==
8805 12:26:51.196292 RX Vref Scan: 0
8806 12:26:51.196355
8807 12:26:51.199316 RX Vref 0 -> 0, step: 1
8808 12:26:51.199435
8809 12:26:51.202661 RX Delay 0 -> 252, step: 8
8810 12:26:51.206158 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8811 12:26:51.209545 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8812 12:26:51.212941 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8813 12:26:51.220001 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8814 12:26:51.222554 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8815 12:26:51.226202 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8816 12:26:51.229530 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8817 12:26:51.233043 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8818 12:26:51.239258 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8819 12:26:51.242730 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8820 12:26:51.246024 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8821 12:26:51.249332 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8822 12:26:51.252686 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8823 12:26:51.259481 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8824 12:26:51.262857 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8825 12:26:51.265700 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8826 12:26:51.265803 ==
8827 12:26:51.269177 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 12:26:51.272593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 12:26:51.272695 ==
8830 12:26:51.276034 DQS Delay:
8831 12:26:51.276109 DQS0 = 0, DQS1 = 0
8832 12:26:51.279258 DQM Delay:
8833 12:26:51.279392 DQM0 = 136, DQM1 = 133
8834 12:26:51.282485 DQ Delay:
8835 12:26:51.285652 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8836 12:26:51.288872 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8837 12:26:51.292229 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8838 12:26:51.295320 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8839 12:26:51.295463
8840 12:26:51.295544
8841 12:26:51.295608 ==
8842 12:26:51.298859 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 12:26:51.302188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 12:26:51.302279 ==
8845 12:26:51.302346
8846 12:26:51.302409
8847 12:26:51.305502 TX Vref Scan disable
8848 12:26:51.308865 == TX Byte 0 ==
8849 12:26:51.312374 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8850 12:26:51.315844 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8851 12:26:51.318621 == TX Byte 1 ==
8852 12:26:51.322615 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8853 12:26:51.325499 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8854 12:26:51.325583 ==
8855 12:26:51.328966 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 12:26:51.335772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 12:26:51.335864 ==
8858 12:26:51.348290
8859 12:26:51.351608 TX Vref early break, caculate TX vref
8860 12:26:51.354243 TX Vref=16, minBit 0, minWin=23, winSum=384
8861 12:26:51.358067 TX Vref=18, minBit 0, minWin=24, winSum=395
8862 12:26:51.361356 TX Vref=20, minBit 0, minWin=24, winSum=397
8863 12:26:51.364606 TX Vref=22, minBit 0, minWin=25, winSum=410
8864 12:26:51.368005 TX Vref=24, minBit 0, minWin=25, winSum=420
8865 12:26:51.374241 TX Vref=26, minBit 0, minWin=25, winSum=424
8866 12:26:51.377703 TX Vref=28, minBit 0, minWin=26, winSum=425
8867 12:26:51.381185 TX Vref=30, minBit 0, minWin=25, winSum=418
8868 12:26:51.384557 TX Vref=32, minBit 0, minWin=25, winSum=413
8869 12:26:51.387766 TX Vref=34, minBit 0, minWin=24, winSum=404
8870 12:26:51.390930 TX Vref=36, minBit 0, minWin=23, winSum=393
8871 12:26:51.397383 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8872 12:26:51.397468
8873 12:26:51.400740 Final TX Range 0 Vref 28
8874 12:26:51.400823
8875 12:26:51.400889 ==
8876 12:26:51.404409 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 12:26:51.407775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 12:26:51.407854 ==
8879 12:26:51.410570
8880 12:26:51.410640
8881 12:26:51.410701 TX Vref Scan disable
8882 12:26:51.417373 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8883 12:26:51.417452 == TX Byte 0 ==
8884 12:26:51.420862 u2DelayCellOfst[0]=17 cells (5 PI)
8885 12:26:51.424319 u2DelayCellOfst[1]=10 cells (3 PI)
8886 12:26:51.427725 u2DelayCellOfst[2]=0 cells (0 PI)
8887 12:26:51.431196 u2DelayCellOfst[3]=6 cells (2 PI)
8888 12:26:51.433958 u2DelayCellOfst[4]=10 cells (3 PI)
8889 12:26:51.437339 u2DelayCellOfst[5]=17 cells (5 PI)
8890 12:26:51.440758 u2DelayCellOfst[6]=17 cells (5 PI)
8891 12:26:51.444258 u2DelayCellOfst[7]=6 cells (2 PI)
8892 12:26:51.447763 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8893 12:26:51.450460 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8894 12:26:51.453966 == TX Byte 1 ==
8895 12:26:51.457548 u2DelayCellOfst[8]=0 cells (0 PI)
8896 12:26:51.460345 u2DelayCellOfst[9]=3 cells (1 PI)
8897 12:26:51.460432 u2DelayCellOfst[10]=10 cells (3 PI)
8898 12:26:51.463640 u2DelayCellOfst[11]=6 cells (2 PI)
8899 12:26:51.467031 u2DelayCellOfst[12]=13 cells (4 PI)
8900 12:26:51.470429 u2DelayCellOfst[13]=17 cells (5 PI)
8901 12:26:51.474220 u2DelayCellOfst[14]=17 cells (5 PI)
8902 12:26:51.477156 u2DelayCellOfst[15]=17 cells (5 PI)
8903 12:26:51.484165 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8904 12:26:51.486999 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8905 12:26:51.487085 DramC Write-DBI on
8906 12:26:51.487152 ==
8907 12:26:51.490325 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 12:26:51.497111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 12:26:51.497195 ==
8910 12:26:51.497261
8911 12:26:51.497320
8912 12:26:51.497393 TX Vref Scan disable
8913 12:26:51.500940 == TX Byte 0 ==
8914 12:26:51.504782 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8915 12:26:51.508011 == TX Byte 1 ==
8916 12:26:51.511165 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8917 12:26:51.514425 DramC Write-DBI off
8918 12:26:51.514507
8919 12:26:51.514575 [DATLAT]
8920 12:26:51.514635 Freq=1600, CH1 RK1
8921 12:26:51.514694
8922 12:26:51.517655 DATLAT Default: 0xf
8923 12:26:51.517741 0, 0xFFFF, sum = 0
8924 12:26:51.521208 1, 0xFFFF, sum = 0
8925 12:26:51.524576 2, 0xFFFF, sum = 0
8926 12:26:51.524662 3, 0xFFFF, sum = 0
8927 12:26:51.527963 4, 0xFFFF, sum = 0
8928 12:26:51.528048 5, 0xFFFF, sum = 0
8929 12:26:51.531272 6, 0xFFFF, sum = 0
8930 12:26:51.531391 7, 0xFFFF, sum = 0
8931 12:26:51.534113 8, 0xFFFF, sum = 0
8932 12:26:51.534187 9, 0xFFFF, sum = 0
8933 12:26:51.537590 10, 0xFFFF, sum = 0
8934 12:26:51.537670 11, 0xFFFF, sum = 0
8935 12:26:51.541084 12, 0xFFFF, sum = 0
8936 12:26:51.541167 13, 0xFFFF, sum = 0
8937 12:26:51.544292 14, 0x0, sum = 1
8938 12:26:51.544396 15, 0x0, sum = 2
8939 12:26:51.547826 16, 0x0, sum = 3
8940 12:26:51.547923 17, 0x0, sum = 4
8941 12:26:51.550695 best_step = 15
8942 12:26:51.550766
8943 12:26:51.550846 ==
8944 12:26:51.554144 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 12:26:51.557719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 12:26:51.557793 ==
8947 12:26:51.557855 RX Vref Scan: 0
8948 12:26:51.561190
8949 12:26:51.561261 RX Vref 0 -> 0, step: 1
8950 12:26:51.561323
8951 12:26:51.564810 RX Delay 19 -> 252, step: 4
8952 12:26:51.567484 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8953 12:26:51.574275 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8954 12:26:51.577649 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8955 12:26:51.580782 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8956 12:26:51.584216 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8957 12:26:51.587832 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8958 12:26:51.590563 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8959 12:26:51.597469 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8960 12:26:51.600918 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8961 12:26:51.604349 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8962 12:26:51.607703 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8963 12:26:51.610973 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8964 12:26:51.617540 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8965 12:26:51.620707 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8966 12:26:51.624063 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8967 12:26:51.627310 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8968 12:26:51.627433 ==
8969 12:26:51.630737 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 12:26:51.637582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 12:26:51.637687 ==
8972 12:26:51.637786 DQS Delay:
8973 12:26:51.641242 DQS0 = 0, DQS1 = 0
8974 12:26:51.641326 DQM Delay:
8975 12:26:51.641392 DQM0 = 133, DQM1 = 130
8976 12:26:51.644050 DQ Delay:
8977 12:26:51.647305 DQ0 =138, DQ1 =128, DQ2 =120, DQ3 =130
8978 12:26:51.650698 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8979 12:26:51.654301 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8980 12:26:51.657831 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8981 12:26:51.657907
8982 12:26:51.657970
8983 12:26:51.658043
8984 12:26:51.660585 [DramC_TX_OE_Calibration] TA2
8985 12:26:51.663968 Original DQ_B0 (3 6) =30, OEN = 27
8986 12:26:51.667508 Original DQ_B1 (3 6) =30, OEN = 27
8987 12:26:51.670962 24, 0x0, End_B0=24 End_B1=24
8988 12:26:51.671067 25, 0x0, End_B0=25 End_B1=25
8989 12:26:51.673836 26, 0x0, End_B0=26 End_B1=26
8990 12:26:51.677041 27, 0x0, End_B0=27 End_B1=27
8991 12:26:51.680365 28, 0x0, End_B0=28 End_B1=28
8992 12:26:51.684393 29, 0x0, End_B0=29 End_B1=29
8993 12:26:51.684514 30, 0x0, End_B0=30 End_B1=30
8994 12:26:51.687063 31, 0x4141, End_B0=30 End_B1=30
8995 12:26:51.690408 Byte0 end_step=30 best_step=27
8996 12:26:51.693946 Byte1 end_step=30 best_step=27
8997 12:26:51.697372 Byte0 TX OE(2T, 0.5T) = (3, 3)
8998 12:26:51.700921 Byte1 TX OE(2T, 0.5T) = (3, 3)
8999 12:26:51.701011
9000 12:26:51.701078
9001 12:26:51.707085 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9002 12:26:51.710608 CH1 RK1: MR19=303, MR18=2207
9003 12:26:51.716880 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9004 12:26:51.720311 [RxdqsGatingPostProcess] freq 1600
9005 12:26:51.723656 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9006 12:26:51.726816 best DQS0 dly(2T, 0.5T) = (1, 1)
9007 12:26:51.730812 best DQS1 dly(2T, 0.5T) = (1, 1)
9008 12:26:51.733484 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9009 12:26:51.736891 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9010 12:26:51.740625 best DQS0 dly(2T, 0.5T) = (1, 1)
9011 12:26:51.743941 best DQS1 dly(2T, 0.5T) = (1, 1)
9012 12:26:51.747510 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9013 12:26:51.750314 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9014 12:26:51.753677 Pre-setting of DQS Precalculation
9015 12:26:51.757027 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9016 12:26:51.763766 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9017 12:26:51.773643 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9018 12:26:51.773731
9019 12:26:51.773797
9020 12:26:51.773856 [Calibration Summary] 3200 Mbps
9021 12:26:51.777182 CH 0, Rank 0
9022 12:26:51.777265 SW Impedance : PASS
9023 12:26:51.780613 DUTY Scan : NO K
9024 12:26:51.783946 ZQ Calibration : PASS
9025 12:26:51.784029 Jitter Meter : NO K
9026 12:26:51.787275 CBT Training : PASS
9027 12:26:51.790690 Write leveling : PASS
9028 12:26:51.790772 RX DQS gating : PASS
9029 12:26:51.793350 RX DQ/DQS(RDDQC) : PASS
9030 12:26:51.797259 TX DQ/DQS : PASS
9031 12:26:51.797344 RX DATLAT : PASS
9032 12:26:51.800168 RX DQ/DQS(Engine): PASS
9033 12:26:51.803750 TX OE : PASS
9034 12:26:51.803839 All Pass.
9035 12:26:51.803942
9036 12:26:51.804002 CH 0, Rank 1
9037 12:26:51.807077 SW Impedance : PASS
9038 12:26:51.810497 DUTY Scan : NO K
9039 12:26:51.810580 ZQ Calibration : PASS
9040 12:26:51.813277 Jitter Meter : NO K
9041 12:26:51.816808 CBT Training : PASS
9042 12:26:51.816906 Write leveling : PASS
9043 12:26:51.820053 RX DQS gating : PASS
9044 12:26:51.823425 RX DQ/DQS(RDDQC) : PASS
9045 12:26:51.823508 TX DQ/DQS : PASS
9046 12:26:51.826886 RX DATLAT : PASS
9047 12:26:51.830180 RX DQ/DQS(Engine): PASS
9048 12:26:51.830288 TX OE : PASS
9049 12:26:51.830383 All Pass.
9050 12:26:51.832900
9051 12:26:51.832983 CH 1, Rank 0
9052 12:26:51.836162 SW Impedance : PASS
9053 12:26:51.836243 DUTY Scan : NO K
9054 12:26:51.840066 ZQ Calibration : PASS
9055 12:26:51.840174 Jitter Meter : NO K
9056 12:26:51.842791 CBT Training : PASS
9057 12:26:51.846123 Write leveling : PASS
9058 12:26:51.846206 RX DQS gating : PASS
9059 12:26:51.850052 RX DQ/DQS(RDDQC) : PASS
9060 12:26:51.853275 TX DQ/DQS : PASS
9061 12:26:51.853391 RX DATLAT : PASS
9062 12:26:51.856677 RX DQ/DQS(Engine): PASS
9063 12:26:51.859992 TX OE : PASS
9064 12:26:51.860075 All Pass.
9065 12:26:51.860140
9066 12:26:51.860200 CH 1, Rank 1
9067 12:26:51.862761 SW Impedance : PASS
9068 12:26:51.866312 DUTY Scan : NO K
9069 12:26:51.866394 ZQ Calibration : PASS
9070 12:26:51.869800 Jitter Meter : NO K
9071 12:26:51.872695 CBT Training : PASS
9072 12:26:51.872777 Write leveling : PASS
9073 12:26:51.876072 RX DQS gating : PASS
9074 12:26:51.879517 RX DQ/DQS(RDDQC) : PASS
9075 12:26:51.879599 TX DQ/DQS : PASS
9076 12:26:51.883100 RX DATLAT : PASS
9077 12:26:51.886423 RX DQ/DQS(Engine): PASS
9078 12:26:51.886505 TX OE : PASS
9079 12:26:51.886571 All Pass.
9080 12:26:51.886630
9081 12:26:51.889684 DramC Write-DBI on
9082 12:26:51.892942 PER_BANK_REFRESH: Hybrid Mode
9083 12:26:51.893025 TX_TRACKING: ON
9084 12:26:51.902980 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9085 12:26:51.909867 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9086 12:26:51.919671 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 12:26:51.922945 [FAST_K] Save calibration result to emmc
9088 12:26:51.923028 sync common calibartion params.
9089 12:26:51.926432 sync cbt_mode0:1, 1:1
9090 12:26:51.929906 dram_init: ddr_geometry: 2
9091 12:26:51.929988 dram_init: ddr_geometry: 2
9092 12:26:51.932801 dram_init: ddr_geometry: 2
9093 12:26:51.936334 0:dram_rank_size:100000000
9094 12:26:51.939674 1:dram_rank_size:100000000
9095 12:26:51.942970 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9096 12:26:51.946242 DFS_SHUFFLE_HW_MODE: ON
9097 12:26:51.949419 dramc_set_vcore_voltage set vcore to 725000
9098 12:26:51.952950 Read voltage for 1600, 0
9099 12:26:51.953028 Vio18 = 0
9100 12:26:51.956299 Vcore = 725000
9101 12:26:51.956381 Vdram = 0
9102 12:26:51.956447 Vddq = 0
9103 12:26:51.956507 Vmddr = 0
9104 12:26:51.959759 switch to 3200 Mbps bootup
9105 12:26:51.963140 [DramcRunTimeConfig]
9106 12:26:51.963247 PHYPLL
9107 12:26:51.966406 DPM_CONTROL_AFTERK: ON
9108 12:26:51.966489 PER_BANK_REFRESH: ON
9109 12:26:51.969869 REFRESH_OVERHEAD_REDUCTION: ON
9110 12:26:51.972881 CMD_PICG_NEW_MODE: OFF
9111 12:26:51.972964 XRTWTW_NEW_MODE: ON
9112 12:26:51.976046 XRTRTR_NEW_MODE: ON
9113 12:26:51.976178 TX_TRACKING: ON
9114 12:26:51.979733 RDSEL_TRACKING: OFF
9115 12:26:51.979827 DQS Precalculation for DVFS: ON
9116 12:26:51.983010 RX_TRACKING: OFF
9117 12:26:51.983097 HW_GATING DBG: ON
9118 12:26:51.986386 ZQCS_ENABLE_LP4: ON
9119 12:26:51.989909 RX_PICG_NEW_MODE: ON
9120 12:26:51.990012 TX_PICG_NEW_MODE: ON
9121 12:26:51.992802 ENABLE_RX_DCM_DPHY: ON
9122 12:26:51.996166 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9123 12:26:51.996297 DUMMY_READ_FOR_TRACKING: OFF
9124 12:26:51.999275 !!! SPM_CONTROL_AFTERK: OFF
9125 12:26:52.002690 !!! SPM could not control APHY
9126 12:26:52.006058 IMPEDANCE_TRACKING: ON
9127 12:26:52.006199 TEMP_SENSOR: ON
9128 12:26:52.009516 HW_SAVE_FOR_SR: OFF
9129 12:26:52.009669 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9130 12:26:52.016376 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9131 12:26:52.016550 Read ODT Tracking: ON
9132 12:26:52.019977 Refresh Rate DeBounce: ON
9133 12:26:52.022779 DFS_NO_QUEUE_FLUSH: ON
9134 12:26:52.026253 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9135 12:26:52.026540 ENABLE_DFS_RUNTIME_MRW: OFF
9136 12:26:52.029706 DDR_RESERVE_NEW_MODE: ON
9137 12:26:52.032622 MR_CBT_SWITCH_FREQ: ON
9138 12:26:52.032890 =========================
9139 12:26:52.052803 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9140 12:26:52.055860 dram_init: ddr_geometry: 2
9141 12:26:52.074244 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9142 12:26:52.077369 dram_init: dram init end (result: 0)
9143 12:26:52.084393 DRAM-K: Full calibration passed in 24463 msecs
9144 12:26:52.087777 MRC: failed to locate region type 0.
9145 12:26:52.088183 DRAM rank0 size:0x100000000,
9146 12:26:52.090594 DRAM rank1 size=0x100000000
9147 12:26:52.100449 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9148 12:26:52.107259 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9149 12:26:52.113856 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9150 12:26:52.120238 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9151 12:26:52.123475 DRAM rank0 size:0x100000000,
9152 12:26:52.127125 DRAM rank1 size=0x100000000
9153 12:26:52.127208 CBMEM:
9154 12:26:52.130370 IMD: root @ 0xfffff000 254 entries.
9155 12:26:52.133862 IMD: root @ 0xffffec00 62 entries.
9156 12:26:52.136732 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9157 12:26:52.140166 WARNING: RO_VPD is uninitialized or empty.
9158 12:26:52.146435 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9159 12:26:52.154064 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9160 12:26:52.166763 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9161 12:26:52.178086 BS: romstage times (exec / console): total (unknown) / 23997 ms
9162 12:26:52.178171
9163 12:26:52.178237
9164 12:26:52.188031 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9165 12:26:52.191461 ARM64: Exception handlers installed.
9166 12:26:52.194708 ARM64: Testing exception
9167 12:26:52.198125 ARM64: Done test exception
9168 12:26:52.198209 Enumerating buses...
9169 12:26:52.201509 Show all devs... Before device enumeration.
9170 12:26:52.204359 Root Device: enabled 1
9171 12:26:52.207968 CPU_CLUSTER: 0: enabled 1
9172 12:26:52.208050 CPU: 00: enabled 1
9173 12:26:52.211363 Compare with tree...
9174 12:26:52.211448 Root Device: enabled 1
9175 12:26:52.214641 CPU_CLUSTER: 0: enabled 1
9176 12:26:52.218106 CPU: 00: enabled 1
9177 12:26:52.218206 Root Device scanning...
9178 12:26:52.221464 scan_static_bus for Root Device
9179 12:26:52.224194 CPU_CLUSTER: 0 enabled
9180 12:26:52.228058 scan_static_bus for Root Device done
9181 12:26:52.230842 scan_bus: bus Root Device finished in 8 msecs
9182 12:26:52.230925 done
9183 12:26:52.237578 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9184 12:26:52.241085 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9185 12:26:52.247444 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9186 12:26:52.250901 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9187 12:26:52.254349 Allocating resources...
9188 12:26:52.257850 Reading resources...
9189 12:26:52.260575 Root Device read_resources bus 0 link: 0
9190 12:26:52.260658 DRAM rank0 size:0x100000000,
9191 12:26:52.263914 DRAM rank1 size=0x100000000
9192 12:26:52.267309 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9193 12:26:52.270876 CPU: 00 missing read_resources
9194 12:26:52.277727 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9195 12:26:52.280815 Root Device read_resources bus 0 link: 0 done
9196 12:26:52.280898 Done reading resources.
9197 12:26:52.287602 Show resources in subtree (Root Device)...After reading.
9198 12:26:52.290885 Root Device child on link 0 CPU_CLUSTER: 0
9199 12:26:52.294129 CPU_CLUSTER: 0 child on link 0 CPU: 00
9200 12:26:52.303735 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9201 12:26:52.303825 CPU: 00
9202 12:26:52.307138 Root Device assign_resources, bus 0 link: 0
9203 12:26:52.310605 CPU_CLUSTER: 0 missing set_resources
9204 12:26:52.317403 Root Device assign_resources, bus 0 link: 0 done
9205 12:26:52.317492 Done setting resources.
9206 12:26:52.323964 Show resources in subtree (Root Device)...After assigning values.
9207 12:26:52.327294 Root Device child on link 0 CPU_CLUSTER: 0
9208 12:26:52.330672 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 12:26:52.340774 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 12:26:52.340858 CPU: 00
9211 12:26:52.344116 Done allocating resources.
9212 12:26:52.346825 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9213 12:26:52.350280 Enabling resources...
9214 12:26:52.350355 done.
9215 12:26:52.357108 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9216 12:26:52.357192 Initializing devices...
9217 12:26:52.360563 Root Device init
9218 12:26:52.360646 init hardware done!
9219 12:26:52.364108 0x00000018: ctrlr->caps
9220 12:26:52.367383 52.000 MHz: ctrlr->f_max
9221 12:26:52.367483 0.400 MHz: ctrlr->f_min
9222 12:26:52.370133 0x40ff8080: ctrlr->voltages
9223 12:26:52.370223 sclk: 390625
9224 12:26:52.373642 Bus Width = 1
9225 12:26:52.373725 sclk: 390625
9226 12:26:52.377123 Bus Width = 1
9227 12:26:52.377206 Early init status = 3
9228 12:26:52.383465 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9229 12:26:52.386925 in-header: 03 fc 00 00 01 00 00 00
9230 12:26:52.387007 in-data: 00
9231 12:26:52.393504 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9232 12:26:52.396935 in-header: 03 fd 00 00 00 00 00 00
9233 12:26:52.400238 in-data:
9234 12:26:52.403367 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9235 12:26:52.407288 in-header: 03 fc 00 00 01 00 00 00
9236 12:26:52.410747 in-data: 00
9237 12:26:52.413481 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9238 12:26:52.419049 in-header: 03 fd 00 00 00 00 00 00
9239 12:26:52.422458 in-data:
9240 12:26:52.425304 [SSUSB] Setting up USB HOST controller...
9241 12:26:52.428538 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9242 12:26:52.431862 [SSUSB] phy power-on done.
9243 12:26:52.435163 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9244 12:26:52.441861 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9245 12:26:52.445229 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9246 12:26:52.452122 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9247 12:26:52.458577 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9248 12:26:52.465364 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9249 12:26:52.471737 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9250 12:26:52.478761 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9251 12:26:52.482219 SPM: binary array size = 0x9dc
9252 12:26:52.485134 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9253 12:26:52.492077 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9254 12:26:52.498319 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9255 12:26:52.501646 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9256 12:26:52.508455 configure_display: Starting display init
9257 12:26:52.542141 anx7625_power_on_init: Init interface.
9258 12:26:52.545492 anx7625_disable_pd_protocol: Disabled PD feature.
9259 12:26:52.548908 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9260 12:26:52.576713 anx7625_start_dp_work: Secure OCM version=00
9261 12:26:52.579458 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9262 12:26:52.594329 sp_tx_get_edid_block: EDID Block = 1
9263 12:26:52.696866 Extracted contents:
9264 12:26:52.700312 header: 00 ff ff ff ff ff ff 00
9265 12:26:52.703715 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9266 12:26:52.707174 version: 01 04
9267 12:26:52.710068 basic params: 95 1f 11 78 0a
9268 12:26:52.713520 chroma info: 76 90 94 55 54 90 27 21 50 54
9269 12:26:52.716612 established: 00 00 00
9270 12:26:52.723290 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9271 12:26:52.726722 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9272 12:26:52.733392 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9273 12:26:52.740113 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9274 12:26:52.747134 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9275 12:26:52.750528 extensions: 00
9276 12:26:52.750615 checksum: fb
9277 12:26:52.750716
9278 12:26:52.753284 Manufacturer: IVO Model 57d Serial Number 0
9279 12:26:52.756928 Made week 0 of 2020
9280 12:26:52.757034 EDID version: 1.4
9281 12:26:52.760405 Digital display
9282 12:26:52.763227 6 bits per primary color channel
9283 12:26:52.763351 DisplayPort interface
9284 12:26:52.766764 Maximum image size: 31 cm x 17 cm
9285 12:26:52.770180 Gamma: 220%
9286 12:26:52.770263 Check DPMS levels
9287 12:26:52.772929 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9288 12:26:52.779893 First detailed timing is preferred timing
9289 12:26:52.780050 Established timings supported:
9290 12:26:52.783587 Standard timings supported:
9291 12:26:52.786323 Detailed timings
9292 12:26:52.789759 Hex of detail: 383680a07038204018303c0035ae10000019
9293 12:26:52.793305 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9294 12:26:52.799876 0780 0798 07c8 0820 hborder 0
9295 12:26:52.803505 0438 043b 0447 0458 vborder 0
9296 12:26:52.806826 -hsync -vsync
9297 12:26:52.806924 Did detailed timing
9298 12:26:52.810277 Hex of detail: 000000000000000000000000000000000000
9299 12:26:52.813116 Manufacturer-specified data, tag 0
9300 12:26:52.820252 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9301 12:26:52.820338 ASCII string: InfoVision
9302 12:26:52.826287 Hex of detail: 000000fe00523134304e574635205248200a
9303 12:26:52.829685 ASCII string: R140NWF5 RH
9304 12:26:52.829803 Checksum
9305 12:26:52.829897 Checksum: 0xfb (valid)
9306 12:26:52.836285 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9307 12:26:52.839703 DSI data_rate: 832800000 bps
9308 12:26:52.843202 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9309 12:26:52.849501 anx7625_parse_edid: pixelclock(138800).
9310 12:26:52.853060 hactive(1920), hsync(48), hfp(24), hbp(88)
9311 12:26:52.856405 vactive(1080), vsync(12), vfp(3), vbp(17)
9312 12:26:52.859735 anx7625_dsi_config: config dsi.
9313 12:26:52.866291 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9314 12:26:52.879718 anx7625_dsi_config: success to config DSI
9315 12:26:52.882385 anx7625_dp_start: MIPI phy setup OK.
9316 12:26:52.885985 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9317 12:26:52.889451 mtk_ddp_mode_set invalid vrefresh 60
9318 12:26:52.892880 main_disp_path_setup
9319 12:26:52.892966 ovl_layer_smi_id_en
9320 12:26:52.896316 ovl_layer_smi_id_en
9321 12:26:52.896405 ccorr_config
9322 12:26:52.896501 aal_config
9323 12:26:52.899199 gamma_config
9324 12:26:52.899280 postmask_config
9325 12:26:52.902863 dither_config
9326 12:26:52.905670 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9327 12:26:52.912325 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9328 12:26:52.915893 Root Device init finished in 552 msecs
9329 12:26:52.915978 CPU_CLUSTER: 0 init
9330 12:26:52.926040 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9331 12:26:52.929504 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9332 12:26:52.932788 APU_MBOX 0x190000b0 = 0x10001
9333 12:26:52.935524 APU_MBOX 0x190001b0 = 0x10001
9334 12:26:52.938915 APU_MBOX 0x190005b0 = 0x10001
9335 12:26:52.942305 APU_MBOX 0x190006b0 = 0x10001
9336 12:26:52.945669 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9337 12:26:52.958374 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9338 12:26:52.970703 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9339 12:26:52.977418 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9340 12:26:52.989153 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9341 12:26:52.998165 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9342 12:26:53.001218 CPU_CLUSTER: 0 init finished in 81 msecs
9343 12:26:53.004718 Devices initialized
9344 12:26:53.008167 Show all devs... After init.
9345 12:26:53.008254 Root Device: enabled 1
9346 12:26:53.011865 CPU_CLUSTER: 0: enabled 1
9347 12:26:53.014685 CPU: 00: enabled 1
9348 12:26:53.018604 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9349 12:26:53.021472 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9350 12:26:53.025022 ELOG: NV offset 0x57f000 size 0x1000
9351 12:26:53.031413 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9352 12:26:53.038381 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9353 12:26:53.041773 ELOG: Event(17) added with size 13 at 2023-06-06 12:26:41 UTC
9354 12:26:53.044476 out: cmd=0x121: 03 db 21 01 00 00 00 00
9355 12:26:53.048533 in-header: 03 d7 00 00 2c 00 00 00
9356 12:26:53.061296 in-data: 88 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 12:26:53.068037 ELOG: Event(A1) added with size 10 at 2023-06-06 12:26:41 UTC
9358 12:26:53.075082 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9359 12:26:53.081648 ELOG: Event(A0) added with size 9 at 2023-06-06 12:26:41 UTC
9360 12:26:53.085046 elog_add_boot_reason: Logged dev mode boot
9361 12:26:53.088563 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9362 12:26:53.091518 Finalize devices...
9363 12:26:53.091618 Devices finalized
9364 12:26:53.097922 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9365 12:26:53.101322 Writing coreboot table at 0xffe64000
9366 12:26:53.104748 0. 000000000010a000-0000000000113fff: RAMSTAGE
9367 12:26:53.108276 1. 0000000040000000-00000000400fffff: RAM
9368 12:26:53.111779 2. 0000000040100000-000000004032afff: RAMSTAGE
9369 12:26:53.118165 3. 000000004032b000-00000000545fffff: RAM
9370 12:26:53.121601 4. 0000000054600000-000000005465ffff: BL31
9371 12:26:53.124741 5. 0000000054660000-00000000ffe63fff: RAM
9372 12:26:53.128137 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9373 12:26:53.134492 7. 0000000100000000-000000023fffffff: RAM
9374 12:26:53.134608 Passing 5 GPIOs to payload:
9375 12:26:53.141734 NAME | PORT | POLARITY | VALUE
9376 12:26:53.144500 EC in RW | 0x000000aa | low | undefined
9377 12:26:53.151229 EC interrupt | 0x00000005 | low | undefined
9378 12:26:53.154512 TPM interrupt | 0x000000ab | high | undefined
9379 12:26:53.157892 SD card detect | 0x00000011 | high | undefined
9380 12:26:53.164322 speaker enable | 0x00000093 | high | undefined
9381 12:26:53.167937 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9382 12:26:53.171423 in-header: 03 f9 00 00 02 00 00 00
9383 12:26:53.171527 in-data: 02 00
9384 12:26:53.174246 ADC[4]: Raw value=904726 ID=7
9385 12:26:53.177592 ADC[3]: Raw value=213441 ID=1
9386 12:26:53.177718 RAM Code: 0x71
9387 12:26:53.181167 ADC[6]: Raw value=75701 ID=0
9388 12:26:53.184370 ADC[5]: Raw value=213072 ID=1
9389 12:26:53.184521 SKU Code: 0x1
9390 12:26:53.191081 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9391 12:26:53.194570 coreboot table: 964 bytes.
9392 12:26:53.197915 IMD ROOT 0. 0xfffff000 0x00001000
9393 12:26:53.200841 IMD SMALL 1. 0xffffe000 0x00001000
9394 12:26:53.204291 RO MCACHE 2. 0xffffc000 0x00001104
9395 12:26:53.207891 CONSOLE 3. 0xfff7c000 0x00080000
9396 12:26:53.211470 FMAP 4. 0xfff7b000 0x00000452
9397 12:26:53.214339 TIME STAMP 5. 0xfff7a000 0x00000910
9398 12:26:53.217846 VBOOT WORK 6. 0xfff66000 0x00014000
9399 12:26:53.221374 RAMOOPS 7. 0xffe66000 0x00100000
9400 12:26:53.224298 COREBOOT 8. 0xffe64000 0x00002000
9401 12:26:53.224408 IMD small region:
9402 12:26:53.227868 IMD ROOT 0. 0xffffec00 0x00000400
9403 12:26:53.230743 VPD 1. 0xffffeba0 0x0000004c
9404 12:26:53.234327 MMC STATUS 2. 0xffffeb80 0x00000004
9405 12:26:53.240746 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9406 12:26:53.240843 Probing TPM: done!
9407 12:26:53.247945 Connected to device vid:did:rid of 1ae0:0028:00
9408 12:26:53.258155 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9409 12:26:53.261610 Initialized TPM device CR50 revision 0
9410 12:26:53.261735 Checking cr50 for pending updates
9411 12:26:53.267898 Reading cr50 TPM mode
9412 12:26:53.276295 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9413 12:26:53.283132 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9414 12:26:53.323322 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9415 12:26:53.326301 Checking segment from ROM address 0x40100000
9416 12:26:53.329689 Checking segment from ROM address 0x4010001c
9417 12:26:53.336488 Loading segment from ROM address 0x40100000
9418 12:26:53.336588 code (compression=0)
9419 12:26:53.343377 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9420 12:26:53.353177 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9421 12:26:53.353265 it's not compressed!
9422 12:26:53.360094 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9423 12:26:53.363416 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9424 12:26:53.383473 Loading segment from ROM address 0x4010001c
9425 12:26:53.383598 Entry Point 0x80000000
9426 12:26:53.387024 Loaded segments
9427 12:26:53.390489 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9428 12:26:53.396759 Jumping to boot code at 0x80000000(0xffe64000)
9429 12:26:53.403437 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9430 12:26:53.410143 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9431 12:26:53.418152 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9432 12:26:53.421589 Checking segment from ROM address 0x40100000
9433 12:26:53.424432 Checking segment from ROM address 0x4010001c
9434 12:26:53.431600 Loading segment from ROM address 0x40100000
9435 12:26:53.431687 code (compression=1)
9436 12:26:53.437805 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9437 12:26:53.447775 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9438 12:26:53.447870 using LZMA
9439 12:26:53.456318 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9440 12:26:53.462813 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9441 12:26:53.466368 Loading segment from ROM address 0x4010001c
9442 12:26:53.466454 Entry Point 0x54601000
9443 12:26:53.469844 Loaded segments
9444 12:26:53.473195 NOTICE: MT8192 bl31_setup
9445 12:26:53.479706 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9446 12:26:53.483180 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9447 12:26:53.486563 WARNING: region 0:
9448 12:26:53.490032 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 12:26:53.490123 WARNING: region 1:
9450 12:26:53.496348 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9451 12:26:53.499891 WARNING: region 2:
9452 12:26:53.503540 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9453 12:26:53.506846 WARNING: region 3:
9454 12:26:53.510116 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 12:26:53.513275 WARNING: region 4:
9456 12:26:53.516679 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 12:26:53.519912 WARNING: region 5:
9458 12:26:53.523143 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 12:26:53.526419 WARNING: region 6:
9460 12:26:53.529896 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 12:26:53.529992 WARNING: region 7:
9462 12:26:53.536438 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 12:26:53.543096 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9464 12:26:53.546594 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9465 12:26:53.550214 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9466 12:26:53.556652 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9467 12:26:53.560227 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9468 12:26:53.563819 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9469 12:26:53.570289 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9470 12:26:53.573154 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9471 12:26:53.577123 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9472 12:26:53.583314 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9473 12:26:53.586632 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9474 12:26:53.589998 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9475 12:26:53.597055 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9476 12:26:53.600444 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9477 12:26:53.606877 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9478 12:26:53.610469 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9479 12:26:53.613794 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9480 12:26:53.620667 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9481 12:26:53.624056 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9482 12:26:53.627302 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9483 12:26:53.633947 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9484 12:26:53.637208 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9485 12:26:53.643983 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9486 12:26:53.647438 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9487 12:26:53.650224 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9488 12:26:53.657315 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9489 12:26:53.660266 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9490 12:26:53.666965 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9491 12:26:53.670656 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9492 12:26:53.674179 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9493 12:26:53.680544 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9494 12:26:53.683973 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9495 12:26:53.687393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9496 12:26:53.693594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9497 12:26:53.696973 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9498 12:26:53.699985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9499 12:26:53.703520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9500 12:26:53.710433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9501 12:26:53.713293 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9502 12:26:53.716771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9503 12:26:53.720239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9504 12:26:53.727248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9505 12:26:53.730633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9506 12:26:53.733814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9507 12:26:53.736963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9508 12:26:53.743781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9509 12:26:53.747172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9510 12:26:53.750486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9511 12:26:53.756683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9512 12:26:53.760282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9513 12:26:53.763912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9514 12:26:53.770196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9515 12:26:53.773824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9516 12:26:53.780233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9517 12:26:53.783802 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9518 12:26:53.790185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9519 12:26:53.793762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9520 12:26:53.796631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9521 12:26:53.804018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9522 12:26:53.806809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9523 12:26:53.813716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9524 12:26:53.817178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9525 12:26:53.823479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9526 12:26:53.826863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9527 12:26:53.830367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9528 12:26:53.836700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9529 12:26:53.840184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9530 12:26:53.846703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9531 12:26:53.850003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9532 12:26:53.857253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9533 12:26:53.860434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9534 12:26:53.863848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9535 12:26:53.870178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9536 12:26:53.873772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9537 12:26:53.880331 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9538 12:26:53.883927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9539 12:26:53.890075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9540 12:26:53.893669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9541 12:26:53.900708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9542 12:26:53.903623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9543 12:26:53.907170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9544 12:26:53.913960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9545 12:26:53.917331 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9546 12:26:53.924019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9547 12:26:53.927526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9548 12:26:53.930978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9549 12:26:53.937332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9550 12:26:53.940950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9551 12:26:53.947172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9552 12:26:53.950483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9553 12:26:53.957271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9554 12:26:53.960491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9555 12:26:53.963756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9556 12:26:53.970348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9557 12:26:53.973753 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9558 12:26:53.980674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9559 12:26:53.984346 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9560 12:26:53.987133 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9561 12:26:53.990647 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9562 12:26:53.996964 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9563 12:26:54.000426 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9564 12:26:54.003949 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9565 12:26:54.010999 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9566 12:26:54.014350 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9567 12:26:54.020692 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9568 12:26:54.024095 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9569 12:26:54.027466 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9570 12:26:54.034360 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9571 12:26:54.037782 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9572 12:26:54.044001 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9573 12:26:54.047499 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9574 12:26:54.050848 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9575 12:26:54.057772 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9576 12:26:54.061253 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9577 12:26:54.064610 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9578 12:26:54.070835 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9579 12:26:54.074128 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9580 12:26:54.078147 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9581 12:26:54.084478 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9582 12:26:54.088018 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9583 12:26:54.090924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9584 12:26:54.094508 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9585 12:26:54.100907 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9586 12:26:54.104387 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9587 12:26:54.107988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9588 12:26:54.114294 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9589 12:26:54.117896 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9590 12:26:54.121421 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9591 12:26:54.127632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9592 12:26:54.131152 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9593 12:26:54.137686 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9594 12:26:54.141085 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9595 12:26:54.144428 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9596 12:26:54.151466 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9597 12:26:54.154302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9598 12:26:54.161226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9599 12:26:54.164602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9600 12:26:54.168055 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9601 12:26:54.174223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9602 12:26:54.177602 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9603 12:26:54.180998 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9604 12:26:54.187726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9605 12:26:54.191289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9606 12:26:54.197773 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9607 12:26:54.201162 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9608 12:26:54.204817 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9609 12:26:54.211111 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9610 12:26:54.214691 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9611 12:26:54.221093 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9612 12:26:54.224685 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9613 12:26:54.227495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9614 12:26:54.234168 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9615 12:26:54.237585 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9616 12:26:54.241092 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9617 12:26:54.247340 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9618 12:26:54.250808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9619 12:26:54.257599 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9620 12:26:54.261019 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9621 12:26:54.264244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9622 12:26:54.270620 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9623 12:26:54.274143 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9624 12:26:54.280817 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9625 12:26:54.284139 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9626 12:26:54.287463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9627 12:26:54.293709 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9628 12:26:54.297226 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9629 12:26:54.303637 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9630 12:26:54.307002 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9631 12:26:54.310632 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9632 12:26:54.316928 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9633 12:26:54.320472 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9634 12:26:54.326882 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9635 12:26:54.330474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9636 12:26:54.334183 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9637 12:26:54.340406 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9638 12:26:54.343713 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9639 12:26:54.350090 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9640 12:26:54.353759 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9641 12:26:54.357092 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9642 12:26:54.363253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9643 12:26:54.366653 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9644 12:26:54.373400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9645 12:26:54.376920 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9646 12:26:54.379821 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9647 12:26:54.386657 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9648 12:26:54.390100 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9649 12:26:54.393447 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9650 12:26:54.400180 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9651 12:26:54.403628 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9652 12:26:54.410111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9653 12:26:54.413630 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9654 12:26:54.419928 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9655 12:26:54.423468 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9656 12:26:54.426307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9657 12:26:54.433322 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9658 12:26:54.436888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9659 12:26:54.443215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9660 12:26:54.446572 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9661 12:26:54.449943 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9662 12:26:54.456241 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9663 12:26:54.459931 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9664 12:26:54.466014 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9665 12:26:54.469592 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9666 12:26:54.476615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9667 12:26:54.479942 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9668 12:26:54.483190 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9669 12:26:54.489562 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9670 12:26:54.493013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9671 12:26:54.499613 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9672 12:26:54.502899 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9673 12:26:54.506196 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9674 12:26:54.512966 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9675 12:26:54.516358 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9676 12:26:54.522720 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9677 12:26:54.526226 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9678 12:26:54.533172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9679 12:26:54.535893 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9680 12:26:54.539380 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9681 12:26:54.545772 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9682 12:26:54.549323 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9683 12:26:54.555963 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9684 12:26:54.559368 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9685 12:26:54.562912 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9686 12:26:54.569150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9687 12:26:54.572471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9688 12:26:54.579406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9689 12:26:54.582864 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9690 12:26:54.589577 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9691 12:26:54.592365 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9692 12:26:54.595859 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9693 12:26:54.599310 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9694 12:26:54.605552 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9695 12:26:54.609348 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9696 12:26:54.612641 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9697 12:26:54.616100 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9698 12:26:54.622828 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9699 12:26:54.626248 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9700 12:26:54.632717 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9701 12:26:54.636213 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9702 12:26:54.639126 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9703 12:26:54.646126 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9704 12:26:54.649388 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9705 12:26:54.652321 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9706 12:26:54.659127 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9707 12:26:54.662708 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9708 12:26:54.665427 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9709 12:26:54.672205 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9710 12:26:54.675522 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9711 12:26:54.679124 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9712 12:26:54.685527 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9713 12:26:54.688868 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9714 12:26:54.695823 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9715 12:26:54.698630 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9716 12:26:54.702282 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9717 12:26:54.708577 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9718 12:26:54.711999 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9719 12:26:54.719067 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9720 12:26:54.721885 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9721 12:26:54.725088 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9722 12:26:54.731813 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9723 12:26:54.735797 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9724 12:26:54.738719 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9725 12:26:54.745091 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9726 12:26:54.748692 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9727 12:26:54.752198 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9728 12:26:54.758628 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9729 12:26:54.761959 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9730 12:26:54.768934 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9731 12:26:54.771817 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9732 12:26:54.775209 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9733 12:26:54.778611 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9734 12:26:54.781880 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9735 12:26:54.788785 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9736 12:26:54.792110 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9737 12:26:54.795475 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9738 12:26:54.798816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9739 12:26:54.805290 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9740 12:26:54.808157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9741 12:26:54.811711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9742 12:26:54.815235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9743 12:26:54.822100 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9744 12:26:54.825297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9745 12:26:54.828495 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9746 12:26:54.835048 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9747 12:26:54.838374 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9748 12:26:54.845345 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9749 12:26:54.848229 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9750 12:26:54.851652 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9751 12:26:54.858592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9752 12:26:54.861435 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9753 12:26:54.868607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9754 12:26:54.871500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9755 12:26:54.875073 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9756 12:26:54.882057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9757 12:26:54.884861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9758 12:26:54.892060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9759 12:26:54.894883 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9760 12:26:54.898254 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9761 12:26:54.904905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9762 12:26:54.908388 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9763 12:26:54.914907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9764 12:26:54.918509 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9765 12:26:54.924920 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9766 12:26:54.928283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9767 12:26:54.931583 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9768 12:26:54.937830 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9769 12:26:54.941748 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9770 12:26:54.947892 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9771 12:26:54.951270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9772 12:26:54.954871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9773 12:26:54.961379 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9774 12:26:54.964958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9775 12:26:54.971681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9776 12:26:54.974473 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9777 12:26:54.978071 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9778 12:26:54.984349 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9779 12:26:54.987920 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9780 12:26:54.994813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9781 12:26:54.997949 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9782 12:26:55.004272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9783 12:26:55.007590 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9784 12:26:55.011447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9785 12:26:55.017856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9786 12:26:55.021301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9787 12:26:55.024818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9788 12:26:55.031500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9789 12:26:55.034208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9790 12:26:55.040970 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9791 12:26:55.044365 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9792 12:26:55.047806 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9793 12:26:55.054354 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9794 12:26:55.057753 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9795 12:26:55.064575 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9796 12:26:55.068100 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9797 12:26:55.074295 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9798 12:26:55.077687 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9799 12:26:55.081115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9800 12:26:55.087290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9801 12:26:55.090857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9802 12:26:55.097872 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9803 12:26:55.100665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9804 12:26:55.104006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9805 12:26:55.111193 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9806 12:26:55.114632 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9807 12:26:55.120552 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9808 12:26:55.124227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9809 12:26:55.127737 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9810 12:26:55.134084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9811 12:26:55.137463 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9812 12:26:55.144400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9813 12:26:55.147730 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9814 12:26:55.154348 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9815 12:26:55.157596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9816 12:26:55.160779 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9817 12:26:55.167617 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9818 12:26:55.171089 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9819 12:26:55.177372 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9820 12:26:55.180683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9821 12:26:55.184112 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9822 12:26:55.190545 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9823 12:26:55.193997 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9824 12:26:55.201037 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9825 12:26:55.204513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9826 12:26:55.210817 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9827 12:26:55.214105 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9828 12:26:55.217292 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9829 12:26:55.224392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9830 12:26:55.227622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9831 12:26:55.234395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9832 12:26:55.237873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9833 12:26:55.244136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9834 12:26:55.247612 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9835 12:26:55.251143 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9836 12:26:55.257162 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9837 12:26:55.260516 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9838 12:26:55.267759 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9839 12:26:55.270999 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9840 12:26:55.277146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9841 12:26:55.280765 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9842 12:26:55.284100 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9843 12:26:55.290711 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9844 12:26:55.294220 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9845 12:26:55.300926 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9846 12:26:55.303736 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9847 12:26:55.310542 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9848 12:26:55.314088 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9849 12:26:55.316859 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9850 12:26:55.323847 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9851 12:26:55.326945 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9852 12:26:55.333739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9853 12:26:55.337051 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9854 12:26:55.343890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9855 12:26:55.347264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9856 12:26:55.350201 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9857 12:26:55.357184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9858 12:26:55.360014 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9859 12:26:55.366708 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9860 12:26:55.370728 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9861 12:26:55.377095 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9862 12:26:55.380382 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9863 12:26:55.386625 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9864 12:26:55.390065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9865 12:26:55.393364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9866 12:26:55.400318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9867 12:26:55.403225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9868 12:26:55.410067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9869 12:26:55.413590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9870 12:26:55.419875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9871 12:26:55.423206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9872 12:26:55.430315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9873 12:26:55.433789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9874 12:26:55.440013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9875 12:26:55.443299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9876 12:26:55.450126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9877 12:26:55.452880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9878 12:26:55.456235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9879 12:26:55.463228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9880 12:26:55.466085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9881 12:26:55.472642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9882 12:26:55.476456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9883 12:26:55.482821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9884 12:26:55.485994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9885 12:26:55.492505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9886 12:26:55.495980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9887 12:26:55.502748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9888 12:26:55.506261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9889 12:26:55.512624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9890 12:26:55.515961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9891 12:26:55.522844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9892 12:26:55.526223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9893 12:26:55.532512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9894 12:26:55.536000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9895 12:26:55.542511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9896 12:26:55.546438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9897 12:26:55.552999 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9898 12:26:55.553100 INFO: [APUAPC] vio 0
9899 12:26:55.559767 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9900 12:26:55.563202 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9901 12:26:55.566032 INFO: [APUAPC] D0_APC_0: 0x400510
9902 12:26:55.569587 INFO: [APUAPC] D0_APC_1: 0x0
9903 12:26:55.573071 INFO: [APUAPC] D0_APC_2: 0x1540
9904 12:26:55.576553 INFO: [APUAPC] D0_APC_3: 0x0
9905 12:26:55.579764 INFO: [APUAPC] D1_APC_0: 0xffffffff
9906 12:26:55.582455 INFO: [APUAPC] D1_APC_1: 0xffffffff
9907 12:26:55.586424 INFO: [APUAPC] D1_APC_2: 0x3fffff
9908 12:26:55.589724 INFO: [APUAPC] D1_APC_3: 0x0
9909 12:26:55.592950 INFO: [APUAPC] D2_APC_0: 0xffffffff
9910 12:26:55.596097 INFO: [APUAPC] D2_APC_1: 0xffffffff
9911 12:26:55.599419 INFO: [APUAPC] D2_APC_2: 0x3fffff
9912 12:26:55.602668 INFO: [APUAPC] D2_APC_3: 0x0
9913 12:26:55.606019 INFO: [APUAPC] D3_APC_0: 0xffffffff
9914 12:26:55.609311 INFO: [APUAPC] D3_APC_1: 0xffffffff
9915 12:26:55.612843 INFO: [APUAPC] D3_APC_2: 0x3fffff
9916 12:26:55.616279 INFO: [APUAPC] D3_APC_3: 0x0
9917 12:26:55.619744 INFO: [APUAPC] D4_APC_0: 0xffffffff
9918 12:26:55.623117 INFO: [APUAPC] D4_APC_1: 0xffffffff
9919 12:26:55.625905 INFO: [APUAPC] D4_APC_2: 0x3fffff
9920 12:26:55.625982 INFO: [APUAPC] D4_APC_3: 0x0
9921 12:26:55.629297 INFO: [APUAPC] D5_APC_0: 0xffffffff
9922 12:26:55.636208 INFO: [APUAPC] D5_APC_1: 0xffffffff
9923 12:26:55.639082 INFO: [APUAPC] D5_APC_2: 0x3fffff
9924 12:26:55.639157 INFO: [APUAPC] D5_APC_3: 0x0
9925 12:26:55.642508 INFO: [APUAPC] D6_APC_0: 0xffffffff
9926 12:26:55.645849 INFO: [APUAPC] D6_APC_1: 0xffffffff
9927 12:26:55.649116 INFO: [APUAPC] D6_APC_2: 0x3fffff
9928 12:26:55.652775 INFO: [APUAPC] D6_APC_3: 0x0
9929 12:26:55.656161 INFO: [APUAPC] D7_APC_0: 0xffffffff
9930 12:26:55.659332 INFO: [APUAPC] D7_APC_1: 0xffffffff
9931 12:26:55.662607 INFO: [APUAPC] D7_APC_2: 0x3fffff
9932 12:26:55.666332 INFO: [APUAPC] D7_APC_3: 0x0
9933 12:26:55.669790 INFO: [APUAPC] D8_APC_0: 0xffffffff
9934 12:26:55.672738 INFO: [APUAPC] D8_APC_1: 0xffffffff
9935 12:26:55.676225 INFO: [APUAPC] D8_APC_2: 0x3fffff
9936 12:26:55.679718 INFO: [APUAPC] D8_APC_3: 0x0
9937 12:26:55.682376 INFO: [APUAPC] D9_APC_0: 0xffffffff
9938 12:26:55.686339 INFO: [APUAPC] D9_APC_1: 0xffffffff
9939 12:26:55.689141 INFO: [APUAPC] D9_APC_2: 0x3fffff
9940 12:26:55.692657 INFO: [APUAPC] D9_APC_3: 0x0
9941 12:26:55.695989 INFO: [APUAPC] D10_APC_0: 0xffffffff
9942 12:26:55.699304 INFO: [APUAPC] D10_APC_1: 0xffffffff
9943 12:26:55.702733 INFO: [APUAPC] D10_APC_2: 0x3fffff
9944 12:26:55.706158 INFO: [APUAPC] D10_APC_3: 0x0
9945 12:26:55.709491 INFO: [APUAPC] D11_APC_0: 0xffffffff
9946 12:26:55.712289 INFO: [APUAPC] D11_APC_1: 0xffffffff
9947 12:26:55.715704 INFO: [APUAPC] D11_APC_2: 0x3fffff
9948 12:26:55.719079 INFO: [APUAPC] D11_APC_3: 0x0
9949 12:26:55.722597 INFO: [APUAPC] D12_APC_0: 0xffffffff
9950 12:26:55.726136 INFO: [APUAPC] D12_APC_1: 0xffffffff
9951 12:26:55.728934 INFO: [APUAPC] D12_APC_2: 0x3fffff
9952 12:26:55.732438 INFO: [APUAPC] D12_APC_3: 0x0
9953 12:26:55.735713 INFO: [APUAPC] D13_APC_0: 0xffffffff
9954 12:26:55.739295 INFO: [APUAPC] D13_APC_1: 0xffffffff
9955 12:26:55.742898 INFO: [APUAPC] D13_APC_2: 0x3fffff
9956 12:26:55.746204 INFO: [APUAPC] D13_APC_3: 0x0
9957 12:26:55.749097 INFO: [APUAPC] D14_APC_0: 0xffffffff
9958 12:26:55.752660 INFO: [APUAPC] D14_APC_1: 0xffffffff
9959 12:26:55.755978 INFO: [APUAPC] D14_APC_2: 0x3fffff
9960 12:26:55.759227 INFO: [APUAPC] D14_APC_3: 0x0
9961 12:26:55.762699 INFO: [APUAPC] D15_APC_0: 0xffffffff
9962 12:26:55.766066 INFO: [APUAPC] D15_APC_1: 0xffffffff
9963 12:26:55.769402 INFO: [APUAPC] D15_APC_2: 0x3fffff
9964 12:26:55.772500 INFO: [APUAPC] D15_APC_3: 0x0
9965 12:26:55.775726 INFO: [APUAPC] APC_CON: 0x4
9966 12:26:55.779266 INFO: [NOCDAPC] D0_APC_0: 0x0
9967 12:26:55.782715 INFO: [NOCDAPC] D0_APC_1: 0x0
9968 12:26:55.782800 INFO: [NOCDAPC] D1_APC_0: 0x0
9969 12:26:55.786026 INFO: [NOCDAPC] D1_APC_1: 0xfff
9970 12:26:55.789331 INFO: [NOCDAPC] D2_APC_0: 0x0
9971 12:26:55.792729 INFO: [NOCDAPC] D2_APC_1: 0xfff
9972 12:26:55.796150 INFO: [NOCDAPC] D3_APC_0: 0x0
9973 12:26:55.799541 INFO: [NOCDAPC] D3_APC_1: 0xfff
9974 12:26:55.802900 INFO: [NOCDAPC] D4_APC_0: 0x0
9975 12:26:55.805803 INFO: [NOCDAPC] D4_APC_1: 0xfff
9976 12:26:55.808960 INFO: [NOCDAPC] D5_APC_0: 0x0
9977 12:26:55.812258 INFO: [NOCDAPC] D5_APC_1: 0xfff
9978 12:26:55.815501 INFO: [NOCDAPC] D6_APC_0: 0x0
9979 12:26:55.818814 INFO: [NOCDAPC] D6_APC_1: 0xfff
9980 12:26:55.818897 INFO: [NOCDAPC] D7_APC_0: 0x0
9981 12:26:55.822112 INFO: [NOCDAPC] D7_APC_1: 0xfff
9982 12:26:55.825664 INFO: [NOCDAPC] D8_APC_0: 0x0
9983 12:26:55.829068 INFO: [NOCDAPC] D8_APC_1: 0xfff
9984 12:26:55.832651 INFO: [NOCDAPC] D9_APC_0: 0x0
9985 12:26:55.836100 INFO: [NOCDAPC] D9_APC_1: 0xfff
9986 12:26:55.838784 INFO: [NOCDAPC] D10_APC_0: 0x0
9987 12:26:55.842194 INFO: [NOCDAPC] D10_APC_1: 0xfff
9988 12:26:55.845568 INFO: [NOCDAPC] D11_APC_0: 0x0
9989 12:26:55.849005 INFO: [NOCDAPC] D11_APC_1: 0xfff
9990 12:26:55.852425 INFO: [NOCDAPC] D12_APC_0: 0x0
9991 12:26:55.855908 INFO: [NOCDAPC] D12_APC_1: 0xfff
9992 12:26:55.855985 INFO: [NOCDAPC] D13_APC_0: 0x0
9993 12:26:55.858770 INFO: [NOCDAPC] D13_APC_1: 0xfff
9994 12:26:55.862136 INFO: [NOCDAPC] D14_APC_0: 0x0
9995 12:26:55.865594 INFO: [NOCDAPC] D14_APC_1: 0xfff
9996 12:26:55.868839 INFO: [NOCDAPC] D15_APC_0: 0x0
9997 12:26:55.872105 INFO: [NOCDAPC] D15_APC_1: 0xfff
9998 12:26:55.875494 INFO: [NOCDAPC] APC_CON: 0x4
9999 12:26:55.878748 INFO: [APUAPC] set_apusys_apc done
10000 12:26:55.882643 INFO: [DEVAPC] devapc_init done
10001 12:26:55.886033 INFO: GICv3 without legacy support detected.
10002 12:26:55.888869 INFO: ARM GICv3 driver initialized in EL3
10003 12:26:55.892311 INFO: Maximum SPI INTID supported: 639
10004 12:26:55.898985 INFO: BL31: Initializing runtime services
10005 12:26:55.902465 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10006 12:26:55.905973 INFO: SPM: enable CPC mode
10007 12:26:55.912153 INFO: mcdi ready for mcusys-off-idle and system suspend
10008 12:26:55.915320 INFO: BL31: Preparing for EL3 exit to normal world
10009 12:26:55.919294 INFO: Entry point address = 0x80000000
10010 12:26:55.922481 INFO: SPSR = 0x8
10011 12:26:55.927867
10012 12:26:55.927941
10013 12:26:55.928005
10014 12:26:55.931336 Starting depthcharge on Spherion...
10015 12:26:55.931422
10016 12:26:55.931485 Wipe memory regions:
10017 12:26:55.931544
10018 12:26:55.932164 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10019 12:26:55.932269 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10020 12:26:55.932353 Setting prompt string to ['asurada:']
10021 12:26:55.932430 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10022 12:26:55.934200 [0x00000040000000, 0x00000054600000)
10023 12:26:56.056714
10024 12:26:56.056889 [0x00000054660000, 0x00000080000000)
10025 12:26:56.317733
10026 12:26:56.318586 [0x000000821a7280, 0x000000ffe64000)
10027 12:26:57.062087
10028 12:26:57.062237 [0x00000100000000, 0x00000240000000)
10029 12:26:58.952335
10030 12:26:58.955640 Initializing XHCI USB controller at 0x11200000.
10031 12:26:59.993915
10032 12:26:59.996673 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10033 12:26:59.996774
10034 12:26:59.996857
10035 12:26:59.996932
10036 12:26:59.997208 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 12:27:00.097511 asurada: tftpboot 192.168.201.1 10605759/tftp-deploy-yx_sj7lb/kernel/image.itb 10605759/tftp-deploy-yx_sj7lb/kernel/cmdline
10039 12:27:00.097680 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 12:27:00.097772 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10041 12:27:00.101661 tftpboot 192.168.201.1 10605759/tftp-deploy-yx_sj7lb/kernel/image.itp-deploy-yx_sj7lb/kernel/cmdline
10042 12:27:00.101748
10043 12:27:00.101814 Waiting for link
10044 12:27:00.262273
10045 12:27:00.262413 R8152: Initializing
10046 12:27:00.262490
10047 12:27:00.265598 Version 9 (ocp_data = 6010)
10048 12:27:00.265693
10049 12:27:00.269073 R8152: Done initializing
10050 12:27:00.269156
10051 12:27:00.269222 Adding net device
10052 12:27:02.215207
10053 12:27:02.215406 done.
10054 12:27:02.215476
10055 12:27:02.215538 MAC: 00:e0:4c:78:7a:aa
10056 12:27:02.215599
10057 12:27:02.218262 Sending DHCP discover... done.
10058 12:27:02.218346
10059 12:27:12.097749 Waiting for reply... done.
10060 12:27:12.097918
10061 12:27:12.098018 Sending DHCP request... done.
10062 12:27:12.100935
10063 12:27:12.108157 Waiting for reply... done.
10064 12:27:12.108240
10065 12:27:12.108306 My ip is 192.168.201.12
10066 12:27:12.108367
10067 12:27:12.111811 The DHCP server ip is 192.168.201.1
10068 12:27:12.111895
10069 12:27:12.118061 TFTP server IP predefined by user: 192.168.201.1
10070 12:27:12.118146
10071 12:27:12.124637 Bootfile predefined by user: 10605759/tftp-deploy-yx_sj7lb/kernel/image.itb
10072 12:27:12.124721
10073 12:27:12.124787 Sending tftp read request... done.
10074 12:27:12.127891
10075 12:27:12.131771 Waiting for the transfer...
10076 12:27:12.131856
10077 12:27:12.381421 00000000 ################################################################
10078 12:27:12.381603
10079 12:27:12.639023 00080000 ################################################################
10080 12:27:12.639172
10081 12:27:12.895255 00100000 ################################################################
10082 12:27:12.895424
10083 12:27:13.171450 00180000 ################################################################
10084 12:27:13.171629
10085 12:27:13.445670 00200000 ################################################################
10086 12:27:13.445858
10087 12:27:13.704770 00280000 ################################################################
10088 12:27:13.704934
10089 12:27:13.988542 00300000 ################################################################
10090 12:27:13.988727
10091 12:27:14.242360 00380000 ################################################################
10092 12:27:14.242514
10093 12:27:14.526118 00400000 ################################################################
10094 12:27:14.526307
10095 12:27:14.829777 00480000 ################################################################
10096 12:27:14.829934
10097 12:27:15.092976 00500000 ################################################################
10098 12:27:15.093129
10099 12:27:15.348814 00580000 ################################################################
10100 12:27:15.348997
10101 12:27:15.597231 00600000 ################################################################
10102 12:27:15.597415
10103 12:27:15.857211 00680000 ################################################################
10104 12:27:15.857394
10105 12:27:16.115365 00700000 ################################################################
10106 12:27:16.115540
10107 12:27:16.388054 00780000 ################################################################
10108 12:27:16.388207
10109 12:27:16.643458 00800000 ################################################################
10110 12:27:16.643613
10111 12:27:16.905610 00880000 ################################################################
10112 12:27:16.905797
10113 12:27:17.248538 00900000 ################################################################
10114 12:27:17.248707
10115 12:27:17.586589 00980000 ################################################################
10116 12:27:17.586760
10117 12:27:17.909675 00a00000 ################################################################
10118 12:27:17.909837
10119 12:27:18.237571 00a80000 ################################################################
10120 12:27:18.237723
10121 12:27:18.503040 00b00000 ################################################################
10122 12:27:18.503216
10123 12:27:18.827288 00b80000 ################################################################
10124 12:27:18.827451
10125 12:27:19.133761 00c00000 ################################################################
10126 12:27:19.133946
10127 12:27:19.416859 00c80000 ################################################################
10128 12:27:19.417013
10129 12:27:19.683734 00d00000 ################################################################
10130 12:27:19.683902
10131 12:27:19.961152 00d80000 ################################################################
10132 12:27:19.961333
10133 12:27:20.250251 00e00000 ################################################################
10134 12:27:20.250425
10135 12:27:20.544118 00e80000 ################################################################
10136 12:27:20.544304
10137 12:27:20.820852 00f00000 ################################################################
10138 12:27:20.821013
10139 12:27:21.075160 00f80000 ################################################################
10140 12:27:21.075312
10141 12:27:21.352002 01000000 ################################################################
10142 12:27:21.352155
10143 12:27:21.631063 01080000 ################################################################
10144 12:27:21.631219
10145 12:27:21.898703 01100000 ################################################################
10146 12:27:21.898892
10147 12:27:22.149467 01180000 ################################################################
10148 12:27:22.149631
10149 12:27:22.424521 01200000 ################################################################
10150 12:27:22.424676
10151 12:27:22.703186 01280000 ################################################################
10152 12:27:22.703409
10153 12:27:22.979472 01300000 ################################################################
10154 12:27:22.979627
10155 12:27:23.228651 01380000 ################################################################
10156 12:27:23.228811
10157 12:27:23.511246 01400000 ################################################################
10158 12:27:23.511447
10159 12:27:23.801238 01480000 ################################################################
10160 12:27:23.801401
10161 12:27:24.091078 01500000 ################################################################
10162 12:27:24.091280
10163 12:27:24.367035 01580000 ################################################################
10164 12:27:24.367217
10165 12:27:24.632365 01600000 ################################################################
10166 12:27:24.632517
10167 12:27:24.901634 01680000 ################################################################
10168 12:27:24.901799
10169 12:27:25.180428 01700000 ################################################################
10170 12:27:25.180563
10171 12:27:25.437453 01780000 ################################################################
10172 12:27:25.437601
10173 12:27:25.694298 01800000 ################################################################
10174 12:27:25.694426
10175 12:27:25.952178 01880000 ################################################################
10176 12:27:25.952339
10177 12:27:26.213314 01900000 ################################################################
10178 12:27:26.213452
10179 12:27:26.471202 01980000 ################################################################
10180 12:27:26.471400
10181 12:27:26.724120 01a00000 ################################################################
10182 12:27:26.724274
10183 12:27:26.968526 01a80000 ################################################################
10184 12:27:26.968688
10185 12:27:27.228826 01b00000 ################################################################
10186 12:27:27.228988
10187 12:27:27.508746 01b80000 ################################################################
10188 12:27:27.508893
10189 12:27:27.769443 01c00000 ################################################################
10190 12:27:27.769680
10191 12:27:28.019175 01c80000 ################################################################
10192 12:27:28.019405
10193 12:27:28.262133 01d00000 ################################################################
10194 12:27:28.262288
10195 12:27:28.509160 01d80000 ################################################################
10196 12:27:28.509313
10197 12:27:28.750769 01e00000 ################################################################
10198 12:27:28.750916
10199 12:27:28.998322 01e80000 ################################################################
10200 12:27:28.998477
10201 12:27:29.240123 01f00000 ################################################################
10202 12:27:29.240280
10203 12:27:29.493709 01f80000 ################################################################
10204 12:27:29.493862
10205 12:27:29.753746 02000000 ################################################################
10206 12:27:29.753924
10207 12:27:29.996130 02080000 ################################################################
10208 12:27:29.996284
10209 12:27:30.238512 02100000 ################################################################
10210 12:27:30.238667
10211 12:27:30.499295 02180000 ################################################################
10212 12:27:30.499489
10213 12:27:30.756281 02200000 ################################################################
10214 12:27:30.756437
10215 12:27:30.997441 02280000 ################################################################
10216 12:27:30.997598
10217 12:27:31.237511 02300000 ################################################################
10218 12:27:31.237664
10219 12:27:31.484418 02380000 ################################################################
10220 12:27:31.484576
10221 12:27:31.730843 02400000 ################################################################
10222 12:27:31.731029
10223 12:27:31.980459 02480000 ################################################################
10224 12:27:31.980620
10225 12:27:32.231124 02500000 ################################################################
10226 12:27:32.231307
10227 12:27:32.485032 02580000 ################################################################
10228 12:27:32.485182
10229 12:27:32.751755 02600000 ################################################################
10230 12:27:32.751906
10231 12:27:32.995304 02680000 ################################################################
10232 12:27:32.995468
10233 12:27:33.242953 02700000 ################################################################
10234 12:27:33.243111
10235 12:27:33.486333 02780000 ################################################################
10236 12:27:33.486527
10237 12:27:33.728529 02800000 ################################################################
10238 12:27:33.728688
10239 12:27:33.976571 02880000 ################################################################
10240 12:27:33.976728
10241 12:27:34.227522 02900000 ################################################################
10242 12:27:34.227677
10243 12:27:34.479600 02980000 ################################################################
10244 12:27:34.479755
10245 12:27:34.732732 02a00000 ################################################################
10246 12:27:34.732884
10247 12:27:34.991900 02a80000 ################################################################
10248 12:27:34.992086
10249 12:27:35.235962 02b00000 ################################################################
10250 12:27:35.236101
10251 12:27:35.485560 02b80000 ################################################################
10252 12:27:35.485715
10253 12:27:35.726669 02c00000 ################################################################
10254 12:27:35.726821
10255 12:27:35.973439 02c80000 ################################################################
10256 12:27:35.973636
10257 12:27:36.231880 02d00000 ################################################################
10258 12:27:36.232033
10259 12:27:36.490459 02d80000 ################################################################
10260 12:27:36.490619
10261 12:27:36.731949 02e00000 ################################################################
10262 12:27:36.732122
10263 12:27:36.973579 02e80000 ################################################################
10264 12:27:36.973732
10265 12:27:37.220467 02f00000 ################################################################
10266 12:27:37.220610
10267 12:27:37.430833 02f80000 ######################################################## done.
10268 12:27:37.430982
10269 12:27:37.433921 The bootfile was 50260586 bytes long.
10270 12:27:37.434007
10271 12:27:37.437557 Sending tftp read request... done.
10272 12:27:37.437643
10273 12:27:37.440753 Waiting for the transfer...
10274 12:27:37.440838
10275 12:27:37.440905 00000000 # done.
10276 12:27:37.440971
10277 12:27:37.450893 Command line loaded dynamically from TFTP file: 10605759/tftp-deploy-yx_sj7lb/kernel/cmdline
10278 12:27:37.450984
10279 12:27:37.460954 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10280 12:27:37.461042
10281 12:27:37.461110 Loading FIT.
10282 12:27:37.461173
10283 12:27:37.464177 Image ramdisk-1 has 40124880 bytes.
10284 12:27:37.464262
10285 12:27:37.467451 Image fdt-1 has 46924 bytes.
10286 12:27:37.467535
10287 12:27:37.470701 Image kernel-1 has 10086749 bytes.
10288 12:27:37.470786
10289 12:27:37.480334 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10290 12:27:37.480423
10291 12:27:37.497571 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10292 12:27:37.497662
10293 12:27:37.503669 Choosing best match conf-1 for compat google,spherion-rev2.
10294 12:27:37.503754
10295 12:27:37.511687 Connected to device vid:did:rid of 1ae0:0028:00
10296 12:27:37.519590
10297 12:27:37.522895 tpm_get_response: command 0x17b, return code 0x0
10298 12:27:37.522980
10299 12:27:37.526689 ec_init: CrosEC protocol v3 supported (256, 248)
10300 12:27:37.530405
10301 12:27:37.533434 tpm_cleanup: add release locality here.
10302 12:27:37.533539
10303 12:27:37.533636 Shutting down all USB controllers.
10304 12:27:37.536991
10305 12:27:37.537094 Removing current net device
10306 12:27:37.537187
10307 12:27:37.543710 Exiting depthcharge with code 4 at timestamp: 70896485
10308 12:27:37.543788
10309 12:27:37.546896 LZMA decompressing kernel-1 to 0x821a6718
10310 12:27:37.546996
10311 12:27:37.549863 LZMA decompressing kernel-1 to 0x40000000
10312 12:27:38.816945
10313 12:27:38.817128 jumping to kernel
10314 12:27:38.817844 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10315 12:27:38.817981 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10316 12:27:38.818087 Setting prompt string to ['Linux version [0-9]']
10317 12:27:38.818189 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10318 12:27:38.818287 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10319 12:27:38.898240
10320 12:27:38.901839 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10321 12:27:38.905144 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10322 12:27:38.905237 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10323 12:27:38.905325 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10324 12:27:38.905403 Using line separator: #'\n'#
10325 12:27:38.905465 No login prompt set.
10326 12:27:38.905527 Parsing kernel messages
10327 12:27:38.905584 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10328 12:27:38.905684 [login-action] Waiting for messages, (timeout 00:03:42)
10329 12:27:38.925160 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10330 12:27:38.928136 [ 0.000000] random: crng init done
10331 12:27:38.931258 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10332 12:27:38.934891 [ 0.000000] efi: UEFI not found.
10333 12:27:38.944538 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10334 12:27:38.951746 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10335 12:27:38.960984 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10336 12:27:38.971320 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10337 12:27:38.978141 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10338 12:27:38.981112 [ 0.000000] printk: bootconsole [mtk8250] enabled
10339 12:27:38.989975 [ 0.000000] NUMA: No NUMA configuration found
10340 12:27:38.996885 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10341 12:27:39.003622 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10342 12:27:39.003712 [ 0.000000] Zone ranges:
10343 12:27:39.009881 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10344 12:27:39.013031 [ 0.000000] DMA32 empty
10345 12:27:39.019774 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10346 12:27:39.022844 [ 0.000000] Movable zone start for each node
10347 12:27:39.026561 [ 0.000000] Early memory node ranges
10348 12:27:39.032543 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10349 12:27:39.039256 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10350 12:27:39.045767 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10351 12:27:39.052883 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10352 12:27:39.059430 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10353 12:27:39.065689 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10354 12:27:39.122820 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10355 12:27:39.128961 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10356 12:27:39.135592 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10357 12:27:39.138789 [ 0.000000] psci: probing for conduit method from DT.
10358 12:27:39.145465 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10359 12:27:39.149145 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10360 12:27:39.155607 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10361 12:27:39.158801 [ 0.000000] psci: SMC Calling Convention v1.2
10362 12:27:39.165275 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10363 12:27:39.168545 [ 0.000000] Detected VIPT I-cache on CPU0
10364 12:27:39.175483 [ 0.000000] CPU features: detected: GIC system register CPU interface
10365 12:27:39.181947 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10366 12:27:39.188439 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10367 12:27:39.195298 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10368 12:27:39.201677 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10369 12:27:39.211591 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10370 12:27:39.214830 [ 0.000000] alternatives: applying boot alternatives
10371 12:27:39.221568 [ 0.000000] Fallback order for Node 0: 0
10372 12:27:39.228468 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10373 12:27:39.231605 [ 0.000000] Policy zone: Normal
10374 12:27:39.241869 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10375 12:27:39.251613 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10376 12:27:39.264186 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10377 12:27:39.274638 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10378 12:27:39.280960 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10379 12:27:39.284320 <6>[ 0.000000] software IO TLB: area num 8.
10380 12:27:39.340858 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10381 12:27:39.490406 <6>[ 0.000000] Memory: 7933756K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419012K reserved, 32768K cma-reserved)
10382 12:27:39.496896 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10383 12:27:39.503594 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10384 12:27:39.506714 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10385 12:27:39.513565 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10386 12:27:39.519987 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10387 12:27:39.523149 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10388 12:27:39.533366 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10389 12:27:39.540058 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10390 12:27:39.546219 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10391 12:27:39.553049 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10392 12:27:39.556126 <6>[ 0.000000] GICv3: 608 SPIs implemented
10393 12:27:39.559798 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10394 12:27:39.566467 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10395 12:27:39.569565 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10396 12:27:39.575972 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10397 12:27:39.589183 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10398 12:27:39.602812 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10399 12:27:39.609292 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10400 12:27:39.616921 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10401 12:27:39.630114 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10402 12:27:39.636941 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10403 12:27:39.643295 <6>[ 0.009176] Console: colour dummy device 80x25
10404 12:27:39.652995 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10405 12:27:39.659808 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10406 12:27:39.663521 <6>[ 0.029248] LSM: Security Framework initializing
10407 12:27:39.669660 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 12:27:39.679716 <6>[ 0.042034] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 12:27:39.689601 <6>[ 0.051508] cblist_init_generic: Setting adjustable number of callback queues.
10410 12:27:39.692854 <6>[ 0.059008] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 12:27:39.699316 <6>[ 0.065347] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 12:27:39.705741 <6>[ 0.071793] rcu: Hierarchical SRCU implementation.
10413 12:27:39.712184 <6>[ 0.076838] rcu: Max phase no-delay instances is 1000.
10414 12:27:39.718804 <6>[ 0.083853] EFI services will not be available.
10415 12:27:39.722451 <6>[ 0.088824] smp: Bringing up secondary CPUs ...
10416 12:27:39.730262 <6>[ 0.093908] Detected VIPT I-cache on CPU1
10417 12:27:39.736987 <6>[ 0.093981] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10418 12:27:39.743314 <6>[ 0.094012] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10419 12:27:39.746670 <6>[ 0.094345] Detected VIPT I-cache on CPU2
10420 12:27:39.753482 <6>[ 0.094394] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10421 12:27:39.763826 <6>[ 0.094408] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10422 12:27:39.766739 <6>[ 0.094666] Detected VIPT I-cache on CPU3
10423 12:27:39.773799 <6>[ 0.094713] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10424 12:27:39.780289 <6>[ 0.094727] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10425 12:27:39.783417 <6>[ 0.095034] CPU features: detected: Spectre-v4
10426 12:27:39.790067 <6>[ 0.095041] CPU features: detected: Spectre-BHB
10427 12:27:39.792875 <6>[ 0.095047] Detected PIPT I-cache on CPU4
10428 12:27:39.799960 <6>[ 0.095105] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10429 12:27:39.806464 <6>[ 0.095121] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10430 12:27:39.812909 <6>[ 0.095417] Detected PIPT I-cache on CPU5
10431 12:27:39.819393 <6>[ 0.095481] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10432 12:27:39.825888 <6>[ 0.095498] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10433 12:27:39.829721 <6>[ 0.095779] Detected PIPT I-cache on CPU6
10434 12:27:39.835924 <6>[ 0.095843] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10435 12:27:39.842847 <6>[ 0.095859] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10436 12:27:39.849343 <6>[ 0.096156] Detected PIPT I-cache on CPU7
10437 12:27:39.855885 <6>[ 0.096220] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10438 12:27:39.863042 <6>[ 0.096237] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10439 12:27:39.866182 <6>[ 0.096284] smp: Brought up 1 node, 8 CPUs
10440 12:27:39.872897 <6>[ 0.237647] SMP: Total of 8 processors activated.
10441 12:27:39.876015 <6>[ 0.242568] CPU features: detected: 32-bit EL0 Support
10442 12:27:39.885885 <6>[ 0.247965] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10443 12:27:39.892809 <6>[ 0.256819] CPU features: detected: Common not Private translations
10444 12:27:39.899265 <6>[ 0.263295] CPU features: detected: CRC32 instructions
10445 12:27:39.902299 <6>[ 0.268647] CPU features: detected: RCpc load-acquire (LDAPR)
10446 12:27:39.908865 <6>[ 0.274643] CPU features: detected: LSE atomic instructions
10447 12:27:39.915883 <6>[ 0.280424] CPU features: detected: Privileged Access Never
10448 12:27:39.922611 <6>[ 0.286204] CPU features: detected: RAS Extension Support
10449 12:27:39.929055 <6>[ 0.291813] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10450 12:27:39.932198 <6>[ 0.299034] CPU: All CPU(s) started at EL2
10451 12:27:39.939120 <6>[ 0.303377] alternatives: applying system-wide alternatives
10452 12:27:39.947982 <6>[ 0.314084] devtmpfs: initialized
10453 12:27:39.963520 <6>[ 0.322930] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10454 12:27:39.970157 <6>[ 0.332889] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10455 12:27:39.976583 <6>[ 0.340950] pinctrl core: initialized pinctrl subsystem
10456 12:27:39.980514 <6>[ 0.347608] DMI not present or invalid.
10457 12:27:39.986709 <6>[ 0.352019] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10458 12:27:39.996495 <6>[ 0.358889] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10459 12:27:40.003184 <6>[ 0.366466] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10460 12:27:40.013004 <6>[ 0.374679] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10461 12:27:40.016497 <6>[ 0.382924] audit: initializing netlink subsys (disabled)
10462 12:27:40.026273 <5>[ 0.388619] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10463 12:27:40.032925 <6>[ 0.389324] thermal_sys: Registered thermal governor 'step_wise'
10464 12:27:40.040034 <6>[ 0.396586] thermal_sys: Registered thermal governor 'power_allocator'
10465 12:27:40.043225 <6>[ 0.402841] cpuidle: using governor menu
10466 12:27:40.049401 <6>[ 0.413804] NET: Registered PF_QIPCRTR protocol family
10467 12:27:40.056103 <6>[ 0.419281] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10468 12:27:40.059671 <6>[ 0.426381] ASID allocator initialised with 32768 entries
10469 12:27:40.067181 <6>[ 0.432952] Serial: AMBA PL011 UART driver
10470 12:27:40.075421 <4>[ 0.441612] Trying to register duplicate clock ID: 134
10471 12:27:40.129625 <6>[ 0.498654] KASLR enabled
10472 12:27:40.143278 <6>[ 0.506350] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10473 12:27:40.149713 <6>[ 0.513358] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10474 12:27:40.156569 <6>[ 0.519847] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10475 12:27:40.163463 <6>[ 0.526849] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10476 12:27:40.169724 <6>[ 0.533334] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10477 12:27:40.176546 <6>[ 0.540337] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10478 12:27:40.183020 <6>[ 0.546821] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10479 12:27:40.190034 <6>[ 0.553822] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10480 12:27:40.193142 <6>[ 0.561298] ACPI: Interpreter disabled.
10481 12:27:40.201408 <6>[ 0.567708] iommu: Default domain type: Translated
10482 12:27:40.208306 <6>[ 0.572819] iommu: DMA domain TLB invalidation policy: strict mode
10483 12:27:40.211259 <5>[ 0.579479] SCSI subsystem initialized
10484 12:27:40.217560 <6>[ 0.583713] usbcore: registered new interface driver usbfs
10485 12:27:40.224352 <6>[ 0.589444] usbcore: registered new interface driver hub
10486 12:27:40.227522 <6>[ 0.594999] usbcore: registered new device driver usb
10487 12:27:40.234823 <6>[ 0.601103] pps_core: LinuxPPS API ver. 1 registered
10488 12:27:40.244619 <6>[ 0.606296] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10489 12:27:40.247881 <6>[ 0.615640] PTP clock support registered
10490 12:27:40.251095 <6>[ 0.619878] EDAC MC: Ver: 3.0.0
10491 12:27:40.258618 <6>[ 0.625053] FPGA manager framework
10492 12:27:40.262441 <6>[ 0.628729] Advanced Linux Sound Architecture Driver Initialized.
10493 12:27:40.266214 <6>[ 0.635493] vgaarb: loaded
10494 12:27:40.272668 <6>[ 0.638654] clocksource: Switched to clocksource arch_sys_counter
10495 12:27:40.278920 <5>[ 0.645103] VFS: Disk quotas dquot_6.6.0
10496 12:27:40.285943 <6>[ 0.649293] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10497 12:27:40.289179 <6>[ 0.656485] pnp: PnP ACPI: disabled
10498 12:27:40.297052 <6>[ 0.663194] NET: Registered PF_INET protocol family
10499 12:27:40.307003 <6>[ 0.668795] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10500 12:27:40.318115 <6>[ 0.681100] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10501 12:27:40.327956 <6>[ 0.689917] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10502 12:27:40.334436 <6>[ 0.697889] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10503 12:27:40.341277 <6>[ 0.706589] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10504 12:27:40.353630 <6>[ 0.716325] TCP: Hash tables configured (established 65536 bind 65536)
10505 12:27:40.360218 <6>[ 0.723188] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10506 12:27:40.366493 <6>[ 0.730387] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 12:27:40.373551 <6>[ 0.738084] NET: Registered PF_UNIX/PF_LOCAL protocol family
10508 12:27:40.380005 <6>[ 0.744245] RPC: Registered named UNIX socket transport module.
10509 12:27:40.383117 <6>[ 0.750402] RPC: Registered udp transport module.
10510 12:27:40.389790 <6>[ 0.755337] RPC: Registered tcp transport module.
10511 12:27:40.396921 <6>[ 0.760267] RPC: Registered tcp NFSv4.1 backchannel transport module.
10512 12:27:40.400151 <6>[ 0.766932] PCI: CLS 0 bytes, default 64
10513 12:27:40.403285 <6>[ 0.771313] Unpacking initramfs...
10514 12:27:40.413599 <6>[ 0.775102] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10515 12:27:40.419209 <6>[ 0.783712] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10516 12:27:40.426012 <6>[ 0.792542] kvm [1]: IPA Size Limit: 40 bits
10517 12:27:40.429832 <6>[ 0.797069] kvm [1]: GICv3: no GICV resource entry
10518 12:27:40.436427 <6>[ 0.802090] kvm [1]: disabling GICv2 emulation
10519 12:27:40.442563 <6>[ 0.806771] kvm [1]: GIC system register CPU interface enabled
10520 12:27:40.446228 <6>[ 0.812934] kvm [1]: vgic interrupt IRQ18
10521 12:27:40.452656 <6>[ 0.817286] kvm [1]: VHE mode initialized successfully
10522 12:27:40.455938 <5>[ 0.823692] Initialise system trusted keyrings
10523 12:27:40.462693 <6>[ 0.828502] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10524 12:27:40.471907 <6>[ 0.838471] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10525 12:27:40.478892 <5>[ 0.844849] NFS: Registering the id_resolver key type
10526 12:27:40.482148 <5>[ 0.850151] Key type id_resolver registered
10527 12:27:40.488403 <5>[ 0.854566] Key type id_legacy registered
10528 12:27:40.495485 <6>[ 0.858858] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10529 12:27:40.502122 <6>[ 0.865783] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10530 12:27:40.508441 <6>[ 0.873480] 9p: Installing v9fs 9p2000 file system support
10531 12:27:40.544628 <5>[ 0.910850] Key type asymmetric registered
10532 12:27:40.547815 <5>[ 0.915181] Asymmetric key parser 'x509' registered
10533 12:27:40.557638 <6>[ 0.920314] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10534 12:27:40.560734 <6>[ 0.927929] io scheduler mq-deadline registered
10535 12:27:40.564563 <6>[ 0.932690] io scheduler kyber registered
10536 12:27:40.583121 <6>[ 0.949336] EINJ: ACPI disabled.
10537 12:27:40.614648 <4>[ 0.974244] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 12:27:40.624766 <4>[ 0.984834] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 12:27:40.639489 <6>[ 1.005284] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10540 12:27:40.647017 <6>[ 1.013114] printk: console [ttyS0] disabled
10541 12:27:40.675313 <6>[ 1.037766] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10542 12:27:40.682127 <6>[ 1.047239] printk: console [ttyS0] enabled
10543 12:27:40.685255 <6>[ 1.047239] printk: console [ttyS0] enabled
10544 12:27:40.691957 <6>[ 1.056132] printk: bootconsole [mtk8250] disabled
10545 12:27:40.695134 <6>[ 1.056132] printk: bootconsole [mtk8250] disabled
10546 12:27:40.701937 <6>[ 1.067305] SuperH (H)SCI(F) driver initialized
10547 12:27:40.704949 <6>[ 1.072584] msm_serial: driver initialized
10548 12:27:40.719277 <6>[ 1.081441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10549 12:27:40.728682 <6>[ 1.089994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10550 12:27:40.735626 <6>[ 1.098535] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10551 12:27:40.745602 <6>[ 1.107165] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10552 12:27:40.755427 <6>[ 1.115871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10553 12:27:40.762002 <6>[ 1.124594] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10554 12:27:40.772075 <6>[ 1.133138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10555 12:27:40.778577 <6>[ 1.141944] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10556 12:27:40.788178 <6>[ 1.150491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10557 12:27:40.799822 <6>[ 1.165937] loop: module loaded
10558 12:27:40.806930 <6>[ 1.171974] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10559 12:27:40.829239 <4>[ 1.195366] mtk-pmic-keys: Failed to locate of_node [id: -1]
10560 12:27:40.835977 <6>[ 1.202146] megasas: 07.719.03.00-rc1
10561 12:27:40.846038 <6>[ 1.211684] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10562 12:27:40.856446 <6>[ 1.222008] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10563 12:27:40.873286 <6>[ 1.238925] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10564 12:27:40.929994 <6>[ 1.289329] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10565 12:27:42.019449 <6>[ 2.385400] Freeing initrd memory: 39180K
10566 12:27:42.029600 <6>[ 2.395807] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10567 12:27:42.040471 <6>[ 2.406717] tun: Universal TUN/TAP device driver, 1.6
10568 12:27:42.043964 <6>[ 2.412753] thunder_xcv, ver 1.0
10569 12:27:42.047563 <6>[ 2.416260] thunder_bgx, ver 1.0
10570 12:27:42.050515 <6>[ 2.419753] nicpf, ver 1.0
10571 12:27:42.060775 <6>[ 2.423747] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10572 12:27:42.064038 <6>[ 2.431224] hns3: Copyright (c) 2017 Huawei Corporation.
10573 12:27:42.067838 <6>[ 2.436809] hclge is initializing
10574 12:27:42.074165 <6>[ 2.440389] e1000: Intel(R) PRO/1000 Network Driver
10575 12:27:42.081176 <6>[ 2.445518] e1000: Copyright (c) 1999-2006 Intel Corporation.
10576 12:27:42.084307 <6>[ 2.451529] e1000e: Intel(R) PRO/1000 Network Driver
10577 12:27:42.090559 <6>[ 2.456744] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10578 12:27:42.097686 <6>[ 2.462929] igb: Intel(R) Gigabit Ethernet Network Driver
10579 12:27:42.104198 <6>[ 2.468578] igb: Copyright (c) 2007-2014 Intel Corporation.
10580 12:27:42.110583 <6>[ 2.474417] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10581 12:27:42.117478 <6>[ 2.480935] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10582 12:27:42.120602 <6>[ 2.487390] sky2: driver version 1.30
10583 12:27:42.127410 <6>[ 2.492359] VFIO - User Level meta-driver version: 0.3
10584 12:27:42.134223 <6>[ 2.500534] usbcore: registered new interface driver usb-storage
10585 12:27:42.140785 <6>[ 2.506982] usbcore: registered new device driver onboard-usb-hub
10586 12:27:42.149925 <6>[ 2.516033] mt6397-rtc mt6359-rtc: registered as rtc0
10587 12:27:42.160229 <6>[ 2.521500] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:27:30 UTC (1686054450)
10588 12:27:42.162769 <6>[ 2.531059] i2c_dev: i2c /dev entries driver
10589 12:27:42.179377 <6>[ 2.542598] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10590 12:27:42.186482 <6>[ 2.552751] sdhci: Secure Digital Host Controller Interface driver
10591 12:27:42.193389 <6>[ 2.559189] sdhci: Copyright(c) Pierre Ossman
10592 12:27:42.199677 <6>[ 2.564576] Synopsys Designware Multimedia Card Interface Driver
10593 12:27:42.202981 <6>[ 2.571200] mmc0: CQHCI version 5.10
10594 12:27:42.209177 <6>[ 2.571715] sdhci-pltfm: SDHCI platform and OF driver helper
10595 12:27:42.216327 <6>[ 2.583051] ledtrig-cpu: registered to indicate activity on CPUs
10596 12:27:42.227207 <6>[ 2.590348] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10597 12:27:42.230388 <6>[ 2.597730] usbcore: registered new interface driver usbhid
10598 12:27:42.237168 <6>[ 2.603563] usbhid: USB HID core driver
10599 12:27:42.243852 <6>[ 2.607813] spi_master spi0: will run message pump with realtime priority
10600 12:27:42.287662 <6>[ 2.647470] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10601 12:27:42.306956 <6>[ 2.663033] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10602 12:27:42.310625 <6>[ 2.676592] mmc0: Command Queue Engine enabled
10603 12:27:42.317165 <6>[ 2.681344] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10604 12:27:42.323593 <6>[ 2.688529] cros-ec-spi spi0.0: Chrome EC device registered
10605 12:27:42.326987 <6>[ 2.688786] mmcblk0: mmc0:0001 DA4128 116 GiB
10606 12:27:42.337918 <6>[ 2.703958] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10607 12:27:42.345238 <6>[ 2.711370] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10608 12:27:42.351837 <6>[ 2.717326] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10609 12:27:42.358621 <6>[ 2.723459] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10610 12:27:42.368321 <6>[ 2.731323] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10611 12:27:42.376659 <6>[ 2.742773] NET: Registered PF_PACKET protocol family
10612 12:27:42.383076 <6>[ 2.748223] 9pnet: Installing 9P2000 support
10613 12:27:42.386174 <5>[ 2.752816] Key type dns_resolver registered
10614 12:27:42.390137 <6>[ 2.757937] registered taskstats version 1
10615 12:27:42.396796 <5>[ 2.762339] Loading compiled-in X.509 certificates
10616 12:27:42.429786 <4>[ 2.789429] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 12:27:42.439435 <4>[ 2.800122] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 12:27:42.449858 <3>[ 2.812732] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10619 12:27:42.462051 <6>[ 2.828192] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10620 12:27:42.468530 <6>[ 2.834968] xhci-mtk 11200000.usb: xHCI Host Controller
10621 12:27:42.475700 <6>[ 2.840466] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10622 12:27:42.485809 <6>[ 2.848323] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10623 12:27:42.492369 <6>[ 2.857777] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10624 12:27:42.498615 <6>[ 2.863881] xhci-mtk 11200000.usb: xHCI Host Controller
10625 12:27:42.505297 <6>[ 2.869515] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10626 12:27:42.512599 <6>[ 2.877189] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10627 12:27:42.519295 <6>[ 2.885085] hub 1-0:1.0: USB hub found
10628 12:27:42.522367 <6>[ 2.889118] hub 1-0:1.0: 1 port detected
10629 12:27:42.532181 <6>[ 2.893483] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10630 12:27:42.535353 <6>[ 2.902103] hub 2-0:1.0: USB hub found
10631 12:27:42.538820 <6>[ 2.906119] hub 2-0:1.0: 1 port detected
10632 12:27:42.547142 <6>[ 2.913218] mtk-msdc 11f70000.mmc: Got CD GPIO
10633 12:27:42.563975 <6>[ 2.926845] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10634 12:27:42.570418 <6>[ 2.934877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10635 12:27:42.580784 <4>[ 2.942845] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10636 12:27:42.590837 <6>[ 2.952502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10637 12:27:42.597720 <6>[ 2.960582] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10638 12:27:42.604177 <6>[ 2.968606] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10639 12:27:42.614403 <6>[ 2.976531] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10640 12:27:42.620498 <6>[ 2.984352] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10641 12:27:42.630600 <6>[ 2.992179] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10642 12:27:42.640204 <6>[ 3.002899] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10643 12:27:42.646811 <6>[ 3.011272] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10644 12:27:42.657007 <6>[ 3.019615] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10645 12:27:42.666662 <6>[ 3.027958] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10646 12:27:42.673169 <6>[ 3.036305] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10647 12:27:42.683221 <6>[ 3.044647] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10648 12:27:42.689778 <6>[ 3.052990] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10649 12:27:42.699813 <6>[ 3.061332] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10650 12:27:42.706088 <6>[ 3.069675] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10651 12:27:42.716618 <6>[ 3.078017] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10652 12:27:42.723038 <6>[ 3.086360] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10653 12:27:42.733138 <6>[ 3.094704] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10654 12:27:42.739427 <6>[ 3.103048] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10655 12:27:42.749666 <6>[ 3.111392] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10656 12:27:42.756118 <6>[ 3.119738] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10657 12:27:42.762517 <6>[ 3.128628] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10658 12:27:42.770071 <6>[ 3.136036] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10659 12:27:42.776662 <6>[ 3.143081] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10660 12:27:42.783813 <6>[ 3.150185] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10661 12:27:42.794582 <6>[ 3.157471] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10662 12:27:42.801592 <6>[ 3.164370] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10663 12:27:42.811148 <6>[ 3.173512] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10664 12:27:42.821017 <6>[ 3.182640] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10665 12:27:42.831496 <6>[ 3.191947] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10666 12:27:42.841146 <6>[ 3.201422] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10667 12:27:42.848257 <6>[ 3.210896] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10668 12:27:42.857593 <6>[ 3.220023] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10669 12:27:42.867618 <6>[ 3.229498] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10670 12:27:42.877772 <6>[ 3.238628] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10671 12:27:42.887514 <6>[ 3.247968] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10672 12:27:42.897312 <6>[ 3.258135] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10673 12:27:42.907397 <6>[ 3.270101] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10674 12:27:42.928176 <6>[ 3.290929] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10675 12:27:42.955635 <6>[ 3.321504] hub 2-1:1.0: USB hub found
10676 12:27:42.958384 <6>[ 3.325908] hub 2-1:1.0: 3 ports detected
10677 12:27:43.080112 <6>[ 3.442923] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10678 12:27:43.233715 <6>[ 3.600361] hub 1-1:1.0: USB hub found
10679 12:27:43.237144 <6>[ 3.604796] hub 1-1:1.0: 4 ports detected
10680 12:27:43.316258 <6>[ 3.679043] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10681 12:27:43.559518 <6>[ 3.922926] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10682 12:27:43.692819 <6>[ 4.059210] hub 1-1.4:1.0: USB hub found
10683 12:27:43.696103 <6>[ 4.063868] hub 1-1.4:1.0: 2 ports detected
10684 12:27:43.995263 <6>[ 4.358927] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10685 12:27:44.187246 <6>[ 4.550928] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10686 12:27:55.192594 <6>[ 15.563502] ALSA device list:
10687 12:27:55.198908 <6>[ 15.566758] No soundcards found.
10688 12:27:55.211459 <6>[ 15.579160] Freeing unused kernel memory: 8384K
10689 12:27:55.214489 <6>[ 15.584072] Run /init as init process
10690 12:27:55.244522 <6>[ 15.612815] NET: Registered PF_INET6 protocol family
10691 12:27:55.251249 <6>[ 15.619368] Segment Routing with IPv6
10692 12:27:55.254467 <6>[ 15.623361] In-situ OAM (IOAM) with IPv6
10693 12:27:55.289687 <30>[ 15.637986] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10694 12:27:55.292857 <30>[ 15.661984] systemd[1]: Detected architecture arm64.
10695 12:27:55.296144
10696 12:27:55.299385 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10697 12:27:55.299476
10698 12:27:55.315229 <30>[ 15.683085] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10699 12:27:55.463194 <30>[ 15.828063] systemd[1]: Queued start job for default target Graphical Interface.
10700 12:27:55.504192 <30>[ 15.872446] systemd[1]: Created slice system-getty.slice.
10701 12:27:55.511132 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10702 12:27:55.527606 <30>[ 15.895557] systemd[1]: Created slice system-modprobe.slice.
10703 12:27:55.533934 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10704 12:27:55.551774 <30>[ 15.920078] systemd[1]: Created slice system-serial\x2dgetty.slice.
10705 12:27:55.562135 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10706 12:27:55.575736 <30>[ 15.943429] systemd[1]: Created slice User and Session Slice.
10707 12:27:55.582444 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10708 12:27:55.602595 <30>[ 15.967481] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10709 12:27:55.613011 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10710 12:27:55.631182 <30>[ 15.995416] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10711 12:27:55.637452 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10712 12:27:55.658120 <30>[ 16.019056] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10713 12:27:55.665187 <30>[ 16.031101] systemd[1]: Reached target Local Encrypted Volumes.
10714 12:27:55.671172 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10715 12:27:55.687444 <30>[ 16.055301] systemd[1]: Reached target Paths.
10716 12:27:55.690931 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10717 12:27:55.707666 <30>[ 16.074978] systemd[1]: Reached target Remote File Systems.
10718 12:27:55.713758 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10719 12:27:55.732004 <30>[ 16.099206] systemd[1]: Reached target Slices.
10720 12:27:55.738281 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10721 12:27:55.751435 <30>[ 16.118988] systemd[1]: Reached target Swap.
10722 12:27:55.754553 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10723 12:27:55.774702 <30>[ 16.139296] systemd[1]: Listening on initctl Compatibility Named Pipe.
10724 12:27:55.782011 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10725 12:27:55.788142 <30>[ 16.154037] systemd[1]: Listening on Journal Audit Socket.
10726 12:27:55.794733 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10727 12:27:55.807881 <30>[ 16.175243] systemd[1]: Listening on Journal Socket (/dev/log).
10728 12:27:55.814325 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10729 12:27:55.832279 <30>[ 16.199707] systemd[1]: Listening on Journal Socket.
10730 12:27:55.838530 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10731 12:27:55.855435 <30>[ 16.219362] systemd[1]: Listening on Network Service Netlink Socket.
10732 12:27:55.861542 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10733 12:27:55.876647 <30>[ 16.243714] systemd[1]: Listening on udev Control Socket.
10734 12:27:55.882196 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10735 12:27:55.899477 <30>[ 16.267647] systemd[1]: Listening on udev Kernel Socket.
10736 12:27:55.906397 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10737 12:27:55.943258 <30>[ 16.311230] systemd[1]: Mounting Huge Pages File System...
10738 12:27:55.950262 Mounting [0;1;39mHuge Pages File System[0m...
10739 12:27:55.964860 <30>[ 16.332979] systemd[1]: Mounting POSIX Message Queue File System...
10740 12:27:55.972270 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10741 12:27:56.023431 <30>[ 16.391212] systemd[1]: Mounting Kernel Debug File System...
10742 12:27:56.030368 Mounting [0;1;39mKernel Debug File System[0m...
10743 12:27:56.046964 <30>[ 16.411267] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10744 12:27:56.057653 <30>[ 16.422116] systemd[1]: Starting Create list of static device nodes for the current kernel...
10745 12:27:56.064286 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10746 12:27:56.099671 <30>[ 16.467393] systemd[1]: Starting Load Kernel Module configfs...
10747 12:27:56.106519 Starting [0;1;39mLoad Kernel Module configfs[0m...
10748 12:27:56.121041 <30>[ 16.489065] systemd[1]: Starting Load Kernel Module drm...
10749 12:27:56.127584 Starting [0;1;39mLoad Kernel Module drm[0m...
10750 12:27:56.147075 <30>[ 16.511062] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10751 12:27:56.175517 <30>[ 16.543528] systemd[1]: Starting Journal Service...
10752 12:27:56.178692 Starting [0;1;39mJournal Service[0m...
10753 12:27:56.197775 <30>[ 16.565618] systemd[1]: Starting Load Kernel Modules...
10754 12:27:56.204220 Starting [0;1;39mLoad Kernel Modules[0m...
10755 12:27:56.225194 <30>[ 16.589596] systemd[1]: Starting Remount Root and Kernel File Systems...
10756 12:27:56.231143 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10757 12:27:56.246096 <30>[ 16.613645] systemd[1]: Starting Coldplug All udev Devices...
10758 12:27:56.252244 Starting [0;1;39mColdplug All udev Devices[0m...
10759 12:27:56.269611 <30>[ 16.637600] systemd[1]: Mounted Huge Pages File System.
10760 12:27:56.276653 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10761 12:27:56.292026 <30>[ 16.659526] systemd[1]: Started Journal Service.
10762 12:27:56.298290 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10763 12:27:56.313387 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10764 12:27:56.328105 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10765 12:27:56.347482 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10766 12:27:56.365108 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10767 12:27:56.380946 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10768 12:27:56.396472 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10769 12:27:56.420036 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10770 12:27:56.439795 See 'systemctl status systemd-remount-fs.service' for details.
10771 12:27:56.496284 Mounting [0;1;39mKernel Configuration File System[0m...
10772 12:27:56.513524 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10773 12:27:56.531422 <46>[ 16.895995] systemd-journald[174]: Received client request to flush runtime journal.
10774 12:27:56.539796 Starting [0;1;39mLoad/Save Random Seed[0m...
10775 12:27:56.558438 Starting [0;1;39mApply Kernel Variables[0m...
10776 12:27:56.578418 Starting [0;1;39mCreate System Users[0m...
10777 12:27:56.593336 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10778 12:27:56.616055 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10779 12:27:56.628566 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10780 12:27:56.644355 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10781 12:27:56.660376 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10782 12:27:56.676460 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10783 12:27:56.720104 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10784 12:27:56.744043 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10785 12:27:56.755968 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10786 12:27:56.771228 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10787 12:27:56.807954 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10788 12:27:56.830993 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10789 12:27:56.847673 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10790 12:27:56.868048 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10791 12:27:56.936339 Starting [0;1;39mNetwork Service[0m...
10792 12:27:56.962183 Starting [0;1;39mNetwork Time Synchronization[0m...
10793 12:27:56.978310 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10794 12:27:57.016860 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10795 12:27:57.037315 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10796 12:27:57.055273 <6>[ 17.419443] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10797 12:27:57.070570 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10798 12:27:57.073599 <6>[ 17.442765] remoteproc remoteproc0: scp is available
10799 12:27:57.083002 <6>[ 17.450592] remoteproc remoteproc0: powering up scp
10800 12:27:57.093025 <3>[ 17.454505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 12:27:57.099816 <6>[ 17.455943] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10802 12:27:57.105995 <6>[ 17.455978] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10803 12:27:57.112759 <3>[ 17.479156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 12:27:57.127597 <3>[ 17.492021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10805 12:27:57.134186 <6>[ 17.492642] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10806 12:27:57.144162 <3>[ 17.503800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 12:27:57.150856 <6>[ 17.508375] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10808 12:27:57.157267 <4>[ 17.508981] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10809 12:27:57.167560 <4>[ 17.509144] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10810 12:27:57.174221 <3>[ 17.516241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 12:27:57.184048 <6>[ 17.524886] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10812 12:27:57.187248 <6>[ 17.527348] mc: Linux media interface: v0.10
10813 12:27:57.193794 <6>[ 17.530089] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10814 12:27:57.204440 <3>[ 17.532057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 12:27:57.210412 <6>[ 17.567404] videodev: Linux video capture interface: v2.00
10816 12:27:57.217285 <3>[ 17.568473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 12:27:57.224153 <6>[ 17.580976] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10818 12:27:57.233535 <3>[ 17.582425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 12:27:57.240786 <3>[ 17.585990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 12:27:57.250062 <6>[ 17.590796] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10821 12:27:57.257226 <6>[ 17.590798] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10822 12:27:57.263422 <3>[ 17.607568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 12:27:57.270460 <6>[ 17.614222] remoteproc remoteproc0: remote processor scp is now up
10824 12:27:57.280143 <4>[ 17.618265] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10825 12:27:57.289977 <4>[ 17.618279] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10826 12:27:57.297303 <3>[ 17.622754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 12:27:57.307135 <6>[ 17.627871] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10828 12:27:57.313570 <4>[ 17.638522] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10829 12:27:57.320581 <4>[ 17.638522] Fallback method does not support PEC.
10830 12:27:57.327678 <3>[ 17.644818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 12:27:57.334869 <6>[ 17.660273] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10832 12:27:57.341997 <3>[ 17.661627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10833 12:27:57.348623 <6>[ 17.670194] pci_bus 0000:00: root bus resource [bus 00-ff]
10834 12:27:57.355533 <3>[ 17.671033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 12:27:57.362319 <6>[ 17.674747] r8152 2-1.3:1.0 eth0: v1.12.13
10836 12:27:57.366033 <6>[ 17.674935] usbcore: registered new interface driver r8152
10837 12:27:57.376133 <3>[ 17.678939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 12:27:57.382220 <6>[ 17.679996] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10839 12:27:57.392508 <6>[ 17.681456] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10840 12:27:57.398758 <6>[ 17.692579] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10841 12:27:57.408427 <3>[ 17.700657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 12:27:57.418759 <6>[ 17.707520] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10843 12:27:57.425164 <3>[ 17.707679] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 12:27:57.434997 <3>[ 17.708472] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10845 12:27:57.441236 <3>[ 17.715601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 12:27:57.448357 <6>[ 17.721372] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10847 12:27:57.459179 <6>[ 17.723989] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10848 12:27:57.465924 <6>[ 17.724515] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10849 12:27:57.477223 <3>[ 17.730125] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10850 12:27:57.483636 <3>[ 17.731847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 12:27:57.490961 <6>[ 17.734486] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10852 12:27:57.501070 <3>[ 17.740289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 12:27:57.504565 <6>[ 17.740976] usbcore: registered new interface driver cdc_ether
10854 12:27:57.511240 <6>[ 17.748665] pci 0000:00:00.0: supports D1 D2
10855 12:27:57.514895 <6>[ 17.758166] Bluetooth: Core ver 2.22
10856 12:27:57.521261 <6>[ 17.765413] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10857 12:27:57.528098 <6>[ 17.772487] NET: Registered PF_BLUETOOTH protocol family
10858 12:27:57.531755 <6>[ 17.772740] usbcore: registered new interface driver r8153_ecm
10859 12:27:57.541870 <6>[ 17.782323] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10860 12:27:57.548146 <6>[ 17.790344] Bluetooth: HCI device and connection manager initialized
10861 12:27:57.552057 <6>[ 17.790378] Bluetooth: HCI socket layer initialized
10862 12:27:57.559098 <6>[ 17.791039] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10863 12:27:57.566091 <6>[ 17.792278] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10864 12:27:57.579193 <6>[ 17.793523] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10865 12:27:57.586172 <6>[ 17.793696] usbcore: registered new interface driver uvcvideo
10866 12:27:57.589186 <6>[ 17.799496] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10867 12:27:57.595983 <6>[ 17.806950] Bluetooth: L2CAP socket layer initialized
10868 12:27:57.602653 <6>[ 17.814950] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10869 12:27:57.609154 <6>[ 17.821359] Bluetooth: SCO socket layer initialized
10870 12:27:57.616488 <6>[ 17.822213] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10871 12:27:57.623110 <6>[ 17.831432] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10872 12:27:57.630184 <3>[ 17.837303] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10873 12:27:57.637361 <3>[ 17.843620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 12:27:57.647541 <3>[ 17.844399] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 12:27:57.654008 <6>[ 17.848551] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10876 12:27:57.661599 <6>[ 17.848685] pci 0000:01:00.0: supports D1 D2
10877 12:27:57.668135 <3>[ 17.865801] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 12:27:57.674991 <6>[ 17.872937] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10879 12:27:57.681194 <6>[ 17.880036] usbcore: registered new interface driver btusb
10880 12:27:57.691163 <4>[ 17.880678] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10881 12:27:57.698050 <3>[ 17.880687] Bluetooth: hci0: Failed to load firmware file (-2)
10882 12:27:57.704821 <3>[ 17.880691] Bluetooth: hci0: Failed to set up firmware (-2)
10883 12:27:57.714430 <4>[ 17.880694] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10884 12:27:57.721118 <6>[ 17.894877] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10885 12:27:57.730760 <3>[ 17.903137] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 12:27:57.737643 <6>[ 17.906050] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10887 12:27:57.748028 <3>[ 17.935652] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 12:27:57.754314 <6>[ 17.939120] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10889 12:27:57.761309 <6>[ 17.939136] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10890 12:27:57.770891 <6>[ 18.135545] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10891 12:27:57.777306 <6>[ 18.135562] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10892 12:27:57.783938 <6>[ 18.135579] pci 0000:00:00.0: PCI bridge to [bus 01]
10893 12:27:57.790891 <6>[ 18.135587] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10894 12:27:57.800480 Startin<6>[ 18.164983] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10895 12:27:57.807262 g [0;1;39mLoad/<6>[ 18.173535] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10896 12:27:57.813929 Save Screen …o<6>[ 18.180826] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10897 12:27:57.817026 f leds:white:kbd_backlight[0m...
10898 12:27:57.833354 <5>[ 18.198624] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10899 12:27:57.853964 <5>[ 18.219070] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10900 12:27:57.860418 <4>[ 18.225965] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10901 12:27:57.867739 <6>[ 18.234864] cfg80211: failed to load regulatory.db
10902 12:27:57.879880 Starting [0;1;39mNetwork Name Resolution[0m...
10903 12:27:57.896644 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10904 12:27:57.915368 <6>[ 18.280163] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10905 12:27:57.921816 <6>[ 18.287690] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10906 12:27:57.928139 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10907 12:27:57.948464 [[0;32m OK [<6>[ 18.314446] mt7921e 0000:01:00.0: ASIC revision: 79610010
10908 12:27:57.951608 0m] Found device [0;1;39m/dev/ttyS0[0m.
10909 12:27:57.999232 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10910 12:27:58.053351 <4>[ 18.414877] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10911 12:27:58.140522 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10912 12:27:58.156743 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10913 12:27:58.172221 <4>[ 18.533941] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10914 12:27:58.179172 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10915 12:27:58.195724 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10916 12:27:58.218755 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10917 12:27:58.234874 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10918 12:27:58.255087 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10919 12:27:58.275319 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10920 12:27:58.292018 <4>[ 18.653610] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10921 12:27:58.298987 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10922 12:27:58.316398 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10923 12:27:58.331828 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10924 12:27:58.347399 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10925 12:27:58.366361 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10926 12:27:58.412156 <4>[ 18.773297] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10927 12:27:58.418429 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10928 12:27:58.446882 Starting [0;1;39mUser Login Management[0m...
10929 12:27:58.465420 Starting [0;1;39mPermit User Sessions[0m...
10930 12:27:58.483131 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10931 12:27:58.499370 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10932 12:27:58.521797 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10933 12:27:58.534730 <4>[ 18.896101] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 12:27:58.587830 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10935 12:27:58.605884 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10936 12:27:58.623584 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10937 12:27:58.643270 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10938 12:27:58.663760 [[0;32m OK [0m] Reached targ<4>[ 19.023176] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10939 12:27:58.666693 et [0;1;39mMulti-User System[0m.
10940 12:27:58.680814 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10941 12:27:58.739086 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10942 12:27:58.763033 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10943 12:27:58.784328 <4>[ 19.145709] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10944 12:27:58.800782
10945 12:27:58.800941
10946 12:27:58.804451 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10947 12:27:58.804535
10948 12:27:58.807663 debian-bullseye-arm64 login: root (automatic login)
10949 12:27:58.807748
10950 12:27:58.807815
10951 12:27:58.826622 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
10952 12:27:58.826708
10953 12:27:58.832939 The programs included with the Debian GNU/Linux system are free software;
10954 12:27:58.839887 the exact distribution terms for each program are described in the
10955 12:27:58.842950 individual files in /usr/share/doc/*/copyright.
10956 12:27:58.843035
10957 12:27:58.849581 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10958 12:27:58.852634 permitted by applicable law.
10959 12:27:58.852980 Matched prompt #10: / #
10961 12:27:58.853189 Setting prompt string to ['/ #']
10962 12:27:58.853283 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10964 12:27:58.853479 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10965 12:27:58.853566 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
10966 12:27:58.853636 Setting prompt string to ['/ #']
10967 12:27:58.853698 Forcing a shell prompt, looking for ['/ #']
10969 12:27:58.903921 / #
10970 12:27:58.904040 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10971 12:27:58.904121 Waiting using forced prompt support (timeout 00:02:30)
10972 12:27:58.947489 <4>[ 19.269479] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 12:27:58.947592
10974 12:27:58.947858 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10975 12:27:58.947958 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10976 12:27:58.948054 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10977 12:27:58.948141 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10978 12:27:58.948226 end: 2 depthcharge-action (duration 00:01:38) [common]
10979 12:27:58.948314 start: 3 lava-test-retry (timeout 00:08:00) [common]
10980 12:27:58.948399 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
10981 12:27:58.948469 Using namespace: common
10983 12:27:59.048869 / # #
10984 12:27:59.049034 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10985 12:27:59.049166 <6>[ 19.337994] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10986 12:27:59.049239 <6>[ 19.345979] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10987 12:27:59.049304 #<4>[ 19.392903] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10988 12:27:59.053772
10989 12:27:59.054040 Using /lava-10605759
10991 12:27:59.154426 / # export SHELL=/bin/sh
10992 12:27:59.154650 export SHELL=/bin/sh<4>[ 19.512626] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 12:27:59.159491
10995 12:27:59.260033 / # . /lava-10605759/environment
10996 12:27:59.262013 . /lava-10605759/environment<3>[ 19.630686] mt7921e 0000:01:00.0: hardware init failed
10997 12:27:59.262101
10999 12:27:59.404073 / # /lava-10605759/bin/lava-test-runner /lava-10605759/0
11000 12:27:59.404243 Test shell timeout: 10s (minimum of the action and connection timeout)
11001 12:27:59.409478 /lava-10605759/bin/lava-test-runner /lava-10605759/0
11002 12:27:59.431537 + export TESTRUN_ID=0_v4l2-compliance-uvc
11003 12:27:59.434672 + cd /lava-10605759/0/tests/0_v4l2-compliance-uvc
11004 12:27:59.434769 + cat uuid
11005 12:27:59.438149 + UUID=10605759_1.5.2.3.1
11006 12:27:59.438230 + set +x
11007 12:27:59.444850 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10605759_1.5.2.3.1>
11008 12:27:59.445113 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10605759_1.5.2.3.1
11009 12:27:59.445191 Starting test lava.0_v4l2-compliance-uvc (10605759_1.5.2.3.1)
11010 12:27:59.445280 Skipping test definition patterns.
11011 12:27:59.447697 + /usr/bin/v4l2-parser.sh -d uvcvideo
11012 12:27:59.454560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11013 12:27:59.454648 device: /dev/video0
11014 12:27:59.454884 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11016 12:28:03.522995 <4>[ 23.891677] ------------[ cut here ]------------
11017 12:28:03.529110 <4>[ 23.896571] get_vaddr_frames() cannot follow VM_IO mapping
11018 12:28:03.539211 <4>[ 23.896714] WARNING: CPU: 6 PID: 305 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11019 12:28:03.589246 <4>[ 23.914816] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb btintel btmtk btrtl btbcm mtk_vcodec_enc mtk_vcodec_common mtk_vpu uvcvideo v4l2_mem2mem r8153_ecm videobuf2_vmalloc videobuf2_dma_contig bluetooth videobuf2_memops videobuf2_v4l2 cdc_ether ecdh_generic ecc videobuf2_common usbnet cros_ec_rpmsg elan_i2c videodev rfkill crct10dif_ce mc elants_i2c r8152 pcie_mediatek_gen3 cros_ec_chardev sbs_battery hid_google_hammer cros_ec_typec hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11020 12:28:03.595521 <4>[ 23.964204] CPU: 6 PID: 305 Comm: v4l2-compliance Not tainted 6.1.31 #1
11021 12:28:03.602551 <4>[ 23.971071] Hardware name: Google Spherion (rev0 - 3) (DT)
11022 12:28:03.608739 <4>[ 23.976805] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11023 12:28:03.615319 <4>[ 23.984017] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11024 12:28:03.622008 <4>[ 23.990114] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11025 12:28:03.625672 <4>[ 23.996209] sp : ffff8000091ab810
11026 12:28:03.632492 <4>[ 23.999773] x29: ffff8000091ab810 x28: ffffa49b79f39000 x27: ffffa49b79f35238
11027 12:28:03.641805 <4>[ 24.007162] x26: 0000000000000000 x25: ffffa49b79f394c0 x24: ffff6a1240808538
11028 12:28:03.648574 <4>[ 24.014550] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11029 12:28:03.655551 <4>[ 24.021938] x20: 00000000fffffff2 x19: ffff6a124ce89000 x18: fffffffffffe9518
11030 12:28:03.661677 <4>[ 24.029326] x17: 0000000000000000 x16: ffffa49ba4a8bb60 x15: 0000000000000038
11031 12:28:03.672048 <4>[ 24.036713] x14: ffffa49ba71c34a8 x13: 0000000000000636 x12: 0000000000000212
11032 12:28:03.678102 <4>[ 24.044101] x11: fffffffffffe9518 x10: fffffffffffe94e0 x9 : 00000000fffff212
11033 12:28:03.684710 <4>[ 24.051489] x8 : ffffa49ba71c34a8 x7 : ffffa49ba721b4a8 x6 : 00000000000018d8
11034 12:28:03.691450 <4>[ 24.058875] x5 : ffff6a137ef90a18 x4 : 00000000fffff212 x3 : ffffc577d848d000
11035 12:28:03.697959 <4>[ 24.066262] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff6a1243de6740
11036 12:28:03.701864 <4>[ 24.073651] Call trace:
11037 12:28:03.708259 <4>[ 24.076346] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11038 12:28:03.714924 <4>[ 24.082096] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11039 12:28:03.721279 <4>[ 24.088102] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11040 12:28:03.727956 <4>[ 24.094631] __prepare_userptr+0x280/0x410 [videobuf2_common]
11041 12:28:03.731176 <4>[ 24.100640] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11042 12:28:03.737879 <4>[ 24.106302] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11043 12:28:03.744582 <4>[ 24.111964] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11044 12:28:03.747711 <4>[ 24.116853] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11045 12:28:03.751089 <4>[ 24.121921] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11046 12:28:03.757953 <4>[ 24.126804] v4l_qbuf+0x48/0x60 [videodev]
11047 12:28:03.761095 <4>[ 24.131224] __video_do_ioctl+0x184/0x3d0 [videodev]
11048 12:28:03.768035 <4>[ 24.136475] video_usercopy+0x358/0x680 [videodev]
11049 12:28:03.771209 <4>[ 24.141552] video_ioctl2+0x18/0x30 [videodev]
11050 12:28:03.778243 <4>[ 24.146280] v4l2_ioctl+0x40/0x60 [videodev]
11051 12:28:03.781283 <4>[ 24.150836] __arm64_sys_ioctl+0xa8/0xf0
11052 12:28:03.784465 <4>[ 24.155017] invoke_syscall+0x48/0x114
11053 12:28:03.791422 <4>[ 24.159026] el0_svc_common.constprop.0+0x44/0xec
11054 12:28:03.794496 <4>[ 24.163984] do_el0_svc+0x2c/0xd0
11055 12:28:03.798132 <4>[ 24.167552] el0_svc+0x2c/0x84
11056 12:28:03.801450 <4>[ 24.170867] el0t_64_sync_handler+0xb8/0xc0
11057 12:28:03.804671 <4>[ 24.175301] el0t_64_sync+0x18c/0x190
11058 12:28:03.811031 <4>[ 24.179216] ---[ end trace 0000000000000000 ]---
11059 12:28:06.233166 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11060 12:28:06.242909 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11061 12:28:06.247843
11062 12:28:06.260806 Compliance test for uvcvideo device /dev/video0:
11063 12:28:06.267654
11064 12:28:06.277066 Driver Info:
11065 12:28:06.285923 Driver name : uvcvideo
11066 12:28:06.299806 Card type : HD User Facing: HD User Facing
11067 12:28:06.308721 Bus info : usb-11200000.usb-1.4.1
11068 12:28:06.314902 Driver version : 6.1.31
11069 12:28:06.324064 Capabilities : 0x84a00001
11070 12:28:06.337406 Metadata Capture
11071 12:28:06.348047 Streaming
11072 12:28:06.358653 Extended Pix Format
11073 12:28:06.369259 Device Capabilities
11074 12:28:06.379642 Device Caps : 0x04200001
11075 12:28:06.392483 Streaming
11076 12:28:06.402380 Extended Pix Format
11077 12:28:06.413011 Media Driver Info:
11078 12:28:06.423357 Driver name : uvcvideo
11079 12:28:06.436570 Model : HD User Facing: HD User Facing
11080 12:28:06.444028 Serial : 200901010001
11081 12:28:06.457288 Bus info : usb-11200000.usb-1.4.1
11082 12:28:06.463405 Media version : 6.1.31
11083 12:28:06.476576 Hardware revision: 0x00009758 (38744)
11084 12:28:06.483554 Driver version : 6.1.31
11085 12:28:06.492992 Interface Info:
11086 12:28:06.506592 <LAVA_SIGNAL_TESTSET START Interface-Info>
11087 12:28:06.506715 ID : 0x03000002
11088 12:28:06.506966 Received signal: <TESTSET> START Interface-Info
11089 12:28:06.507042 Starting test_set Interface-Info
11090 12:28:06.515904 Type : V4L Video
11091 12:28:06.525650 Entity Info:
11092 12:28:06.531674 <LAVA_SIGNAL_TESTSET STOP>
11093 12:28:06.531958 Received signal: <TESTSET> STOP
11094 12:28:06.532032 Closing test_set Interface-Info
11095 12:28:06.541225 <LAVA_SIGNAL_TESTSET START Entity-Info>
11096 12:28:06.541482 Received signal: <TESTSET> START Entity-Info
11097 12:28:06.541554 Starting test_set Entity-Info
11098 12:28:06.544767 ID : 0x00000001 (1)
11099 12:28:06.554741 Name : HD User Facing: HD User Facing
11100 12:28:06.561380 Function : V4L2 I/O
11101 12:28:06.572424 Flags : default
11102 12:28:06.581946 Pad 0x01000007 : 0: Sink
11103 12:28:06.602725 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11104 12:28:06.602857
11105 12:28:06.613320 Required ioctls:
11106 12:28:06.620244 <LAVA_SIGNAL_TESTSET STOP>
11107 12:28:06.620522 Received signal: <TESTSET> STOP
11108 12:28:06.620600 Closing test_set Entity-Info
11109 12:28:06.629868 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11110 12:28:06.630214 Received signal: <TESTSET> START Required-ioctls
11111 12:28:06.630294 Starting test_set Required-ioctls
11112 12:28:06.632985 test MC information (see 'Media Driver Info' above): OK
11113 12:28:06.655934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11114 12:28:06.656292 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11116 12:28:06.659022 test VIDIOC_QUERYCAP: OK
11117 12:28:06.675738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11118 12:28:06.676099 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11120 12:28:06.678991 test invalid ioctls: OK
11121 12:28:06.700199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11122 12:28:06.700389
11123 12:28:06.700680 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11125 12:28:06.709233 Allow for multiple opens:
11126 12:28:06.715610 <LAVA_SIGNAL_TESTSET STOP>
11127 12:28:06.715903 Received signal: <TESTSET> STOP
11128 12:28:06.716005 Closing test_set Required-ioctls
11129 12:28:06.725000 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11130 12:28:06.725292 Received signal: <TESTSET> START Allow-for-multiple-opens
11131 12:28:06.725399 Starting test_set Allow-for-multiple-opens
11132 12:28:06.728142 test second /dev/video0 open: OK
11133 12:28:06.748442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11134 12:28:06.748782 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11136 12:28:06.751529 test VIDIOC_QUERYCAP: OK
11137 12:28:06.771868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11138 12:28:06.772211 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11140 12:28:06.775464 test VIDIOC_G/S_PRIORITY: OK
11141 12:28:06.796412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11142 12:28:06.796760 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11144 12:28:06.799634 test for unlimited opens: OK
11145 12:28:06.819893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11146 12:28:06.820031
11147 12:28:06.820313 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11149 12:28:06.830812 Debug ioctls:
11150 12:28:06.837511 <LAVA_SIGNAL_TESTSET STOP>
11151 12:28:06.837803 Received signal: <TESTSET> STOP
11152 12:28:06.837910 Closing test_set Allow-for-multiple-opens
11153 12:28:06.846496 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11154 12:28:06.846794 Received signal: <TESTSET> START Debug-ioctls
11155 12:28:06.846901 Starting test_set Debug-ioctls
11156 12:28:06.849319 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11157 12:28:06.871247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11158 12:28:06.871607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11160 12:28:06.877923 test VIDIOC_LOG_STATUS: OK (Not Supported)
11161 12:28:06.896058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11162 12:28:06.896197
11163 12:28:06.896476 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11165 12:28:06.905982 Input ioctls:
11166 12:28:06.912950 <LAVA_SIGNAL_TESTSET STOP>
11167 12:28:06.913245 Received signal: <TESTSET> STOP
11168 12:28:06.913354 Closing test_set Debug-ioctls
11169 12:28:06.922518 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11170 12:28:06.922815 Received signal: <TESTSET> START Input-ioctls
11171 12:28:06.922924 Starting test_set Input-ioctls
11172 12:28:06.925678 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11173 12:28:06.951030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11174 12:28:06.951357 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11176 12:28:06.954642 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11177 12:28:06.971916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11178 12:28:06.972233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11180 12:28:06.978264 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11181 12:28:06.995930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11182 12:28:06.996241 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11184 12:28:06.999466 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11185 12:28:07.020409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11186 12:28:07.020739 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11188 12:28:07.024280 test VIDIOC_G/S/ENUMINPUT: OK
11189 12:28:07.045091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11190 12:28:07.045401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11192 12:28:07.048175 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11193 12:28:07.070827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11194 12:28:07.071177 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11196 12:28:07.073730 Inputs: 1 Audio Inputs: 0 Tuners: 0
11197 12:28:07.081048
11198 12:28:07.097376 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11199 12:28:07.118808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11200 12:28:07.119133 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11202 12:28:07.125715 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11203 12:28:07.143470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11204 12:28:07.143783 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11206 12:28:07.150354 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11207 12:28:07.168538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11208 12:28:07.168950 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11210 12:28:07.172112 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11211 12:28:07.192684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11212 12:28:07.193000 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11214 12:28:07.199024 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11215 12:28:07.215939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11216 12:28:07.216067
11217 12:28:07.216340 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11219 12:28:07.235590 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11220 12:28:07.256680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11221 12:28:07.257004 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11223 12:28:07.262781 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11224 12:28:07.284643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11225 12:28:07.284958 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11227 12:28:07.288408 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11228 12:28:07.305154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11229 12:28:07.305449 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11231 12:28:07.308934 test VIDIOC_G/S_EDID: OK (Not Supported)
11232 12:28:07.328041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11233 12:28:07.328174
11234 12:28:07.328446 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11236 12:28:07.337807 Control ioctls (Input 0):
11237 12:28:07.344876 <LAVA_SIGNAL_TESTSET STOP>
11238 12:28:07.345172 Received signal: <TESTSET> STOP
11239 12:28:07.345277 Closing test_set Input-ioctls
11240 12:28:07.353833 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11241 12:28:07.354102 Received signal: <TESTSET> START Control-ioctls-Input-0
11242 12:28:07.354178 Starting test_set Control-ioctls-Input-0
11243 12:28:07.357054 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11244 12:28:07.379558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11245 12:28:07.379663 test VIDIOC_QUERYCTRL: OK
11246 12:28:07.379905 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11248 12:28:07.400447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11249 12:28:07.400711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11251 12:28:07.403460 test VIDIOC_G/S_CTRL: OK
11252 12:28:07.424318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11253 12:28:07.424634 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11255 12:28:07.427210 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11256 12:28:07.448034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11257 12:28:07.448324 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11259 12:28:07.454889 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11260 12:28:07.474970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11261 12:28:07.475258 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11263 12:28:07.478553 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11264 12:28:07.497116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11265 12:28:07.497402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11267 12:28:07.500232 Standard Controls: 16 Private Controls: 0
11268 12:28:07.506843
11269 12:28:07.517436 Format ioctls (Input 0):
11270 12:28:07.524877 <LAVA_SIGNAL_TESTSET STOP>
11271 12:28:07.525160 Received signal: <TESTSET> STOP
11272 12:28:07.525234 Closing test_set Control-ioctls-Input-0
11273 12:28:07.533895 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11274 12:28:07.534151 Received signal: <TESTSET> START Format-ioctls-Input-0
11275 12:28:07.534234 Starting test_set Format-ioctls-Input-0
11276 12:28:07.537471 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11277 12:28:07.560727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11278 12:28:07.561024 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11280 12:28:07.563722 test VIDIOC_G/S_PARM: OK
11281 12:28:07.582476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11282 12:28:07.582747 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11284 12:28:07.585613 test VIDIOC_G_FBUF: OK (Not Supported)
11285 12:28:07.603734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11286 12:28:07.604012 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11288 12:28:07.606935 test VIDIOC_G_FMT: OK
11289 12:28:07.628199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11290 12:28:07.628493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11292 12:28:07.631404 test VIDIOC_TRY_FMT: OK
11293 12:28:07.650872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11294 12:28:07.651141 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11296 12:28:07.657060 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11297 12:28:07.660615 test VIDIOC_S_FMT: OK
11298 12:28:07.683622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11299 12:28:07.683903 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11301 12:28:07.686722 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11302 12:28:07.707402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11303 12:28:07.707682 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11305 12:28:07.711088 test Cropping: OK (Not Supported)
11306 12:28:07.731471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11307 12:28:07.731750 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11309 12:28:07.734702 test Composing: OK (Not Supported)
11310 12:28:07.754598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11311 12:28:07.754885 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11313 12:28:07.758310 test Scaling: OK (Not Supported)
11314 12:28:07.778840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11315 12:28:07.778983
11316 12:28:07.779273 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11318 12:28:07.788849 Codec ioctls (Input 0):
11319 12:28:07.796569 <LAVA_SIGNAL_TESTSET STOP>
11320 12:28:07.796865 Received signal: <TESTSET> STOP
11321 12:28:07.796970 Closing test_set Format-ioctls-Input-0
11322 12:28:07.806254 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11323 12:28:07.806536 Received signal: <TESTSET> START Codec-ioctls-Input-0
11324 12:28:07.806611 Starting test_set Codec-ioctls-Input-0
11325 12:28:07.809382 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11326 12:28:07.831060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11327 12:28:07.831380 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11329 12:28:07.837385 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11330 12:28:07.856109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11331 12:28:07.856415 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11333 12:28:07.863026 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11334 12:28:07.882261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11335 12:28:07.882394
11336 12:28:07.882721 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11338 12:28:07.892302 Buffer ioctls (Input 0):
11339 12:28:07.898942 <LAVA_SIGNAL_TESTSET STOP>
11340 12:28:07.899255 Received signal: <TESTSET> STOP
11341 12:28:07.899400 Closing test_set Codec-ioctls-Input-0
11342 12:28:07.908147 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11343 12:28:07.908443 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11344 12:28:07.908547 Starting test_set Buffer-ioctls-Input-0
11345 12:28:07.911625 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11346 12:28:07.935784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11347 12:28:07.935906 test VIDIOC_EXPBUF: OK
11348 12:28:07.936152 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11350 12:28:07.956288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11351 12:28:07.956575 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11353 12:28:07.959283 test Requests: OK (Not Supported)
11354 12:28:07.980807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11355 12:28:07.980904
11356 12:28:07.981142 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11358 12:28:07.992005 Test input 0:
11359 12:28:08.002733
11360 12:28:08.012950 Streaming ioctls:
11361 12:28:08.020056 <LAVA_SIGNAL_TESTSET STOP>
11362 12:28:08.020317 Received signal: <TESTSET> STOP
11363 12:28:08.020389 Closing test_set Buffer-ioctls-Input-0
11364 12:28:08.029063 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11365 12:28:08.029321 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11366 12:28:08.029393 Starting test_set Streaming-ioctls_Test-input-0
11367 12:28:08.032081 test read/write: OK (Not Supported)
11368 12:28:08.052543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11369 12:28:08.052868 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11371 12:28:08.055629 test blocking wait: OK
11372 12:28:08.077065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11373 12:28:08.077347 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11375 12:28:08.087212 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11376 12:28:08.087321 test MMAP (no poll): FAIL
11377 12:28:08.111187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11378 12:28:08.111563 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11380 12:28:08.120762 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11381 12:28:08.120864 test MMAP (select): FAIL
11382 12:28:08.144840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11383 12:28:08.145129 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11385 12:28:08.154762 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11386 12:28:08.154866 test MMAP (epoll): FAIL
11387 12:28:08.179080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11388 12:28:08.179207
11389 12:28:08.179471 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11391 12:28:08.192296
11392 12:28:08.347092
11393 12:28:08.353110 test USERPTR (no poll): OK
11394 12:28:08.375939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11395 12:28:08.376092
11396 12:28:08.376319 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11398 12:28:08.386641
11399 12:28:08.541215
11400 12:28:08.548052 test USERPTR (select): OK
11401 12:28:08.571479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11402 12:28:08.571799 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11404 12:28:08.577942 test DMABUF: Cannot test, specify --expbuf-device
11405 12:28:08.581382
11406 12:28:08.599220 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11407 12:28:08.602523 <LAVA_TEST_RUNNER EXIT>
11408 12:28:08.602838 ok: lava_test_shell seems to have completed
11409 12:28:08.602920 Marking unfinished test run as failed
11411 12:28:08.603892 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11412 12:28:08.604048 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11413 12:28:08.604164 end: 3 lava-test-retry (duration 00:00:10) [common]
11414 12:28:08.604250 start: 4 finalize (timeout 00:07:50) [common]
11415 12:28:08.604341 start: 4.1 power-off (timeout 00:00:30) [common]
11416 12:28:08.604547 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11417 12:28:08.683982 >> Command sent successfully.
11418 12:28:08.686782 Returned 0 in 0 seconds
11419 12:28:08.787160 end: 4.1 power-off (duration 00:00:00) [common]
11421 12:28:08.787518 start: 4.2 read-feedback (timeout 00:07:50) [common]
11422 12:28:08.787775 Listened to connection for namespace 'common' for up to 1s
11423 12:28:09.788716 Finalising connection for namespace 'common'
11424 12:28:09.788883 Disconnecting from shell: Finalise
11425 12:28:09.788971 / #
11426 12:28:09.889259 end: 4.2 read-feedback (duration 00:00:01) [common]
11427 12:28:09.889434 end: 4 finalize (duration 00:00:01) [common]
11428 12:28:09.889550 Cleaning after the job
11429 12:28:09.889651 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/ramdisk
11430 12:28:09.894176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/kernel
11431 12:28:09.905789 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/dtb
11432 12:28:09.905994 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605759/tftp-deploy-yx_sj7lb/modules
11433 12:28:09.912123 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605759
11434 12:28:09.968877 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605759
11435 12:28:09.969054 Job finished correctly