Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 12:25:18.554686 lava-dispatcher, installed at version: 2023.05.1
2 12:25:18.554946 start: 0 validate
3 12:25:18.555116 Start time: 2023-06-06 12:25:18.555108+00:00 (UTC)
4 12:25:18.555295 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:25:18.555458 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:25:18.848912 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:25:18.849149 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:25:19.130589 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:25:19.130817 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:25:51.489376 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:25:51.489610 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:25:52.068335 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:25:52.068556 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:25:52.356392 validate duration: 33.80
16 12:25:52.356655 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:25:52.356760 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:25:52.356848 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:25:52.356969 Not decompressing ramdisk as can be used compressed.
20 12:25:52.357055 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 12:25:52.357121 saving as /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/ramdisk/initrd.cpio.gz
22 12:25:52.357209 total size: 4665395 (4MB)
23 12:25:58.678406 progress 0% (0MB)
24 12:25:58.679992 progress 5% (0MB)
25 12:25:58.681319 progress 10% (0MB)
26 12:25:58.682626 progress 15% (0MB)
27 12:25:58.683938 progress 20% (0MB)
28 12:25:58.685231 progress 25% (1MB)
29 12:25:58.686541 progress 30% (1MB)
30 12:25:58.687860 progress 35% (1MB)
31 12:25:58.689154 progress 40% (1MB)
32 12:25:58.690774 progress 45% (2MB)
33 12:25:58.692265 progress 50% (2MB)
34 12:25:58.693686 progress 55% (2MB)
35 12:25:58.695058 progress 60% (2MB)
36 12:25:58.696405 progress 65% (2MB)
37 12:25:58.697772 progress 70% (3MB)
38 12:25:58.699115 progress 75% (3MB)
39 12:25:58.700483 progress 80% (3MB)
40 12:25:58.701978 progress 85% (3MB)
41 12:25:58.703342 progress 90% (4MB)
42 12:25:58.704638 progress 95% (4MB)
43 12:25:58.705972 progress 100% (4MB)
44 12:25:58.706134 4MB downloaded in 6.35s (0.70MB/s)
45 12:25:58.706319 end: 1.1.1 http-download (duration 00:00:06) [common]
47 12:25:58.706716 end: 1.1 download-retry (duration 00:00:06) [common]
48 12:25:58.706846 start: 1.2 download-retry (timeout 00:09:54) [common]
49 12:25:58.706938 start: 1.2.1 http-download (timeout 00:09:54) [common]
50 12:25:58.707086 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:25:58.707166 saving as /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/kernel/Image
52 12:25:58.707257 total size: 45746688 (43MB)
53 12:25:58.707348 No compression specified
54 12:25:58.989995 progress 0% (0MB)
55 12:25:59.002748 progress 5% (2MB)
56 12:25:59.016269 progress 10% (4MB)
57 12:25:59.029336 progress 15% (6MB)
58 12:25:59.042042 progress 20% (8MB)
59 12:25:59.054728 progress 25% (10MB)
60 12:25:59.067340 progress 30% (13MB)
61 12:25:59.079887 progress 35% (15MB)
62 12:25:59.092070 progress 40% (17MB)
63 12:25:59.104523 progress 45% (19MB)
64 12:25:59.117068 progress 50% (21MB)
65 12:25:59.129439 progress 55% (24MB)
66 12:25:59.142386 progress 60% (26MB)
67 12:25:59.154893 progress 65% (28MB)
68 12:25:59.167342 progress 70% (30MB)
69 12:25:59.179849 progress 75% (32MB)
70 12:25:59.191939 progress 80% (34MB)
71 12:25:59.204904 progress 85% (37MB)
72 12:25:59.217330 progress 90% (39MB)
73 12:25:59.229972 progress 95% (41MB)
74 12:25:59.242873 progress 100% (43MB)
75 12:25:59.243064 43MB downloaded in 0.54s (81.42MB/s)
76 12:25:59.243344 end: 1.2.1 http-download (duration 00:00:01) [common]
78 12:25:59.243828 end: 1.2 download-retry (duration 00:00:01) [common]
79 12:25:59.243950 start: 1.3 download-retry (timeout 00:09:53) [common]
80 12:25:59.244094 start: 1.3.1 http-download (timeout 00:09:53) [common]
81 12:25:59.244271 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:25:59.244392 saving as /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/dtb/mt8192-asurada-spherion-r0.dtb
83 12:25:59.244489 total size: 46924 (0MB)
84 12:25:59.244587 No compression specified
85 12:25:59.246732 progress 69% (0MB)
86 12:25:59.247115 progress 100% (0MB)
87 12:25:59.247323 0MB downloaded in 0.00s (15.81MB/s)
88 12:25:59.247560 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:25:59.248014 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:25:59.248175 start: 1.4 download-retry (timeout 00:09:53) [common]
92 12:25:59.248329 start: 1.4.1 http-download (timeout 00:09:53) [common]
93 12:25:59.248483 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 12:25:59.248582 saving as /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/nfsrootfs/full.rootfs.tar
95 12:25:59.248711 total size: 125267308 (119MB)
96 12:25:59.248833 Using unxz to decompress xz
97 12:25:59.253361 progress 0% (0MB)
98 12:25:59.580926 progress 5% (6MB)
99 12:25:59.914117 progress 10% (11MB)
100 12:26:00.251937 progress 15% (17MB)
101 12:26:00.444648 progress 20% (23MB)
102 12:26:00.626071 progress 25% (29MB)
103 12:26:00.985639 progress 30% (35MB)
104 12:26:01.359463 progress 35% (41MB)
105 12:26:01.760795 progress 40% (47MB)
106 12:26:02.143435 progress 45% (53MB)
107 12:26:02.543379 progress 50% (59MB)
108 12:26:02.917297 progress 55% (65MB)
109 12:26:03.310570 progress 60% (71MB)
110 12:26:03.684378 progress 65% (77MB)
111 12:26:04.060046 progress 70% (83MB)
112 12:26:04.452810 progress 75% (89MB)
113 12:26:04.887461 progress 80% (95MB)
114 12:26:05.324470 progress 85% (101MB)
115 12:26:05.561129 progress 90% (107MB)
116 12:26:05.897137 progress 95% (113MB)
117 12:26:06.278115 progress 100% (119MB)
118 12:26:06.284367 119MB downloaded in 7.04s (16.98MB/s)
119 12:26:06.284724 end: 1.4.1 http-download (duration 00:00:07) [common]
121 12:26:06.285161 end: 1.4 download-retry (duration 00:00:07) [common]
122 12:26:06.285297 start: 1.5 download-retry (timeout 00:09:46) [common]
123 12:26:06.285435 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 12:26:06.285628 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:26:06.285736 saving as /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/modules/modules.tar
126 12:26:06.285841 total size: 8539116 (8MB)
127 12:26:06.285947 Using unxz to decompress xz
128 12:26:06.584059 progress 0% (0MB)
129 12:26:06.606915 progress 5% (0MB)
130 12:26:06.633526 progress 10% (0MB)
131 12:26:06.658066 progress 15% (1MB)
132 12:26:06.686333 progress 20% (1MB)
133 12:26:06.712394 progress 25% (2MB)
134 12:26:06.738866 progress 30% (2MB)
135 12:26:06.765947 progress 35% (2MB)
136 12:26:06.791301 progress 40% (3MB)
137 12:26:06.815928 progress 45% (3MB)
138 12:26:06.844399 progress 50% (4MB)
139 12:26:06.870799 progress 55% (4MB)
140 12:26:06.897483 progress 60% (4MB)
141 12:26:06.924662 progress 65% (5MB)
142 12:26:06.951029 progress 70% (5MB)
143 12:26:06.979196 progress 75% (6MB)
144 12:26:07.011454 progress 80% (6MB)
145 12:26:07.035479 progress 85% (6MB)
146 12:26:07.061254 progress 90% (7MB)
147 12:26:07.086248 progress 95% (7MB)
148 12:26:07.112016 progress 100% (8MB)
149 12:26:07.117776 8MB downloaded in 0.83s (9.79MB/s)
150 12:26:07.118139 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:26:07.118576 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:26:07.118720 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
154 12:26:07.118871 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
155 12:26:09.552729 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n
156 12:26:09.552968 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:26:09.553119 start: 1.6.2 lava-overlay (timeout 00:09:43) [common]
158 12:26:09.553343 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z
159 12:26:09.553527 makedir: /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin
160 12:26:09.553670 makedir: /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/tests
161 12:26:09.553819 makedir: /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/results
162 12:26:09.553974 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-add-keys
163 12:26:09.554183 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-add-sources
164 12:26:09.554376 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-background-process-start
165 12:26:09.554554 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-background-process-stop
166 12:26:09.554744 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-common-functions
167 12:26:09.555240 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-echo-ipv4
168 12:26:09.555414 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-install-packages
169 12:26:09.555577 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-installed-packages
170 12:26:09.555747 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-os-build
171 12:26:09.555909 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-probe-channel
172 12:26:09.556070 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-probe-ip
173 12:26:09.556230 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-target-ip
174 12:26:09.556385 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-target-mac
175 12:26:09.556546 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-target-storage
176 12:26:09.556705 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-case
177 12:26:09.556865 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-event
178 12:26:09.557022 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-feedback
179 12:26:09.557182 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-raise
180 12:26:09.557339 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-reference
181 12:26:09.557500 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-runner
182 12:26:09.557662 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-set
183 12:26:09.557825 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-test-shell
184 12:26:09.557997 Updating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-install-packages (oe)
185 12:26:09.558189 Updating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/bin/lava-installed-packages (oe)
186 12:26:09.558350 Creating /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/environment
187 12:26:09.558482 LAVA metadata
188 12:26:09.558582 - LAVA_JOB_ID=10605797
189 12:26:09.558680 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:26:09.558821 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:43) [common]
191 12:26:09.558915 skipped lava-vland-overlay
192 12:26:09.559027 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:26:09.559138 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:43) [common]
194 12:26:09.559233 skipped lava-multinode-overlay
195 12:26:09.559342 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:26:09.559458 start: 1.6.2.3 test-definition (timeout 00:09:43) [common]
197 12:26:09.559565 Loading test definitions
198 12:26:09.559695 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:43) [common]
199 12:26:09.559801 Using /lava-10605797 at stage 0
200 12:26:09.560231 uuid=10605797_1.6.2.3.1 testdef=None
201 12:26:09.560356 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:26:09.560474 start: 1.6.2.3.2 test-overlay (timeout 00:09:43) [common]
203 12:26:09.561209 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:26:09.561575 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:43) [common]
206 12:26:09.562446 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:26:09.562841 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:43) [common]
209 12:26:09.563524 runner path: /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/0/tests/0_dmesg test_uuid 10605797_1.6.2.3.1
210 12:26:09.563720 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:26:09.564096 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:43) [common]
213 12:26:09.564210 Using /lava-10605797 at stage 1
214 12:26:09.564644 uuid=10605797_1.6.2.3.5 testdef=None
215 12:26:09.564764 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 12:26:09.564887 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
217 12:26:09.565602 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 12:26:09.565920 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
220 12:26:09.566710 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 12:26:09.567058 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
223 12:26:09.567999 runner path: /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/1/tests/1_bootrr test_uuid 10605797_1.6.2.3.5
224 12:26:09.568193 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 12:26:09.568545 Creating lava-test-runner.conf files
227 12:26:09.568648 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/0 for stage 0
228 12:26:09.568775 - 0_dmesg
229 12:26:09.568887 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605797/lava-overlay-ds38xk_z/lava-10605797/1 for stage 1
230 12:26:09.569016 - 1_bootrr
231 12:26:09.569147 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 12:26:09.569267 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
233 12:26:09.578418 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 12:26:09.578563 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:43) [common]
235 12:26:09.578683 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 12:26:09.578802 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 12:26:09.578930 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:43) [common]
238 12:26:09.699963 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 12:26:09.700376 start: 1.6.4 extract-modules (timeout 00:09:43) [common]
240 12:26:09.700540 extracting modules file /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n
241 12:26:09.955691 extracting modules file /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605797/extract-overlay-ramdisk-82cx7ko3/ramdisk
242 12:26:10.192350 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 12:26:10.192541 start: 1.6.5 apply-overlay-tftp (timeout 00:09:42) [common]
244 12:26:10.192663 [common] Applying overlay to NFS
245 12:26:10.192737 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605797/compress-overlay-el29xz94/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n
246 12:26:10.201241 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 12:26:10.201377 start: 1.6.6 configure-preseed-file (timeout 00:09:42) [common]
248 12:26:10.201494 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 12:26:10.201600 start: 1.6.7 compress-ramdisk (timeout 00:09:42) [common]
250 12:26:10.201686 Building ramdisk /var/lib/lava/dispatcher/tmp/10605797/extract-overlay-ramdisk-82cx7ko3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605797/extract-overlay-ramdisk-82cx7ko3/ramdisk
251 12:26:10.488874 >> 117807 blocks
252 12:26:12.458022 rename /var/lib/lava/dispatcher/tmp/10605797/extract-overlay-ramdisk-82cx7ko3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/ramdisk/ramdisk.cpio.gz
253 12:26:12.458463 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 12:26:12.458589 start: 1.6.8 prepare-kernel (timeout 00:09:40) [common]
255 12:26:12.458728 start: 1.6.8.1 prepare-fit (timeout 00:09:40) [common]
256 12:26:12.458902 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/kernel/Image'
257 12:26:25.249885 Returned 0 in 12 seconds
258 12:26:25.350554 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/kernel/image.itb
259 12:26:27.182644 output: FIT description: Kernel Image image with one or more FDT blobs
260 12:26:27.183052 output: Created: Tue Jun 6 13:26:26 2023
261 12:26:27.183131 output: Image 0 (kernel-1)
262 12:26:27.183199 output: Description:
263 12:26:27.183263 output: Created: Tue Jun 6 13:26:26 2023
264 12:26:27.183327 output: Type: Kernel Image
265 12:26:27.183389 output: Compression: lzma compressed
266 12:26:27.183452 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
267 12:26:27.183514 output: Architecture: AArch64
268 12:26:27.183574 output: OS: Linux
269 12:26:27.183629 output: Load Address: 0x00000000
270 12:26:27.183686 output: Entry Point: 0x00000000
271 12:26:27.183744 output: Hash algo: crc32
272 12:26:27.183799 output: Hash value: a26c3f91
273 12:26:27.183853 output: Image 1 (fdt-1)
274 12:26:27.183906 output: Description: mt8192-asurada-spherion-r0
275 12:26:27.183960 output: Created: Tue Jun 6 13:26:26 2023
276 12:26:27.184014 output: Type: Flat Device Tree
277 12:26:27.184067 output: Compression: uncompressed
278 12:26:27.184121 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 12:26:27.184174 output: Architecture: AArch64
280 12:26:27.184228 output: Hash algo: crc32
281 12:26:27.184280 output: Hash value: 1df858fa
282 12:26:27.184334 output: Image 2 (ramdisk-1)
283 12:26:27.184386 output: Description: unavailable
284 12:26:27.184439 output: Created: Tue Jun 6 13:26:26 2023
285 12:26:27.184493 output: Type: RAMDisk Image
286 12:26:27.184546 output: Compression: Unknown Compression
287 12:26:27.184598 output: Data Size: 17643449 Bytes = 17229.93 KiB = 16.83 MiB
288 12:26:27.184651 output: Architecture: AArch64
289 12:26:27.184704 output: OS: Linux
290 12:26:27.184756 output: Load Address: unavailable
291 12:26:27.184809 output: Entry Point: unavailable
292 12:26:27.184861 output: Hash algo: crc32
293 12:26:27.184914 output: Hash value: 1146bad9
294 12:26:27.184967 output: Default Configuration: 'conf-1'
295 12:26:27.185019 output: Configuration 0 (conf-1)
296 12:26:27.185071 output: Description: mt8192-asurada-spherion-r0
297 12:26:27.185124 output: Kernel: kernel-1
298 12:26:27.185177 output: Init Ramdisk: ramdisk-1
299 12:26:27.185229 output: FDT: fdt-1
300 12:26:27.185282 output: Loadables: kernel-1
301 12:26:27.185335 output:
302 12:26:27.185546 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
303 12:26:27.185647 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
304 12:26:27.185752 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
305 12:26:27.185847 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:25) [common]
306 12:26:27.185924 No LXC device requested
307 12:26:27.186003 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 12:26:27.186091 start: 1.8 deploy-device-env (timeout 00:09:25) [common]
309 12:26:27.186170 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 12:26:27.186238 Checking files for TFTP limit of 4294967296 bytes.
311 12:26:27.186719 end: 1 tftp-deploy (duration 00:00:35) [common]
312 12:26:27.186831 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 12:26:27.186961 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 12:26:27.187083 substitutions:
315 12:26:27.187150 - {DTB}: 10605797/tftp-deploy-r9s28fa7/dtb/mt8192-asurada-spherion-r0.dtb
316 12:26:27.187216 - {INITRD}: 10605797/tftp-deploy-r9s28fa7/ramdisk/ramdisk.cpio.gz
317 12:26:27.187275 - {KERNEL}: 10605797/tftp-deploy-r9s28fa7/kernel/Image
318 12:26:27.187333 - {LAVA_MAC}: None
319 12:26:27.187390 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n
320 12:26:27.187447 - {NFS_SERVER_IP}: 192.168.201.1
321 12:26:27.187503 - {PRESEED_CONFIG}: None
322 12:26:27.187582 - {PRESEED_LOCAL}: None
323 12:26:27.187637 - {RAMDISK}: 10605797/tftp-deploy-r9s28fa7/ramdisk/ramdisk.cpio.gz
324 12:26:27.187692 - {ROOT_PART}: None
325 12:26:27.187745 - {ROOT}: None
326 12:26:27.187799 - {SERVER_IP}: 192.168.201.1
327 12:26:27.187851 - {TEE}: None
328 12:26:27.187905 Parsed boot commands:
329 12:26:27.187957 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 12:26:27.188131 Parsed boot commands: tftpboot 192.168.201.1 10605797/tftp-deploy-r9s28fa7/kernel/image.itb 10605797/tftp-deploy-r9s28fa7/kernel/cmdline
331 12:26:27.188221 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 12:26:27.188306 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 12:26:27.188400 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 12:26:27.188486 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 12:26:27.188556 Not connected, no need to disconnect.
336 12:26:27.188629 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 12:26:27.188713 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 12:26:27.188780 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
339 12:26:27.192114 Setting prompt string to ['lava-test: # ']
340 12:26:27.192493 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 12:26:27.192637 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 12:26:27.192770 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 12:26:27.192890 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 12:26:27.193215 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 12:26:32.329518 >> Command sent successfully.
346 12:26:32.332318 Returned 0 in 5 seconds
347 12:26:32.433001 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 12:26:32.434870 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 12:26:32.435394 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 12:26:32.435876 Setting prompt string to 'Starting depthcharge on Spherion...'
352 12:26:32.436234 Changing prompt to 'Starting depthcharge on Spherion...'
353 12:26:32.436632 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 12:26:32.438268 [Enter `^Ec?' for help]
355 12:26:32.605728
356 12:26:32.605891
357 12:26:32.605966 F0: 102B 0000
358 12:26:32.606031
359 12:26:32.606092 F3: 1001 0000 [0200]
360 12:26:32.606153
361 12:26:32.609346 F3: 1001 0000
362 12:26:32.609431
363 12:26:32.609498 F7: 102D 0000
364 12:26:32.609562
365 12:26:32.612504 F1: 0000 0000
366 12:26:32.612589
367 12:26:32.612656 V0: 0000 0000 [0001]
368 12:26:32.612722
369 12:26:32.615634 00: 0007 8000
370 12:26:32.615800
371 12:26:32.615900 01: 0000 0000
372 12:26:32.615967
373 12:26:32.616029 BP: 0C00 0209 [0000]
374 12:26:32.619411
375 12:26:32.619495 G0: 1182 0000
376 12:26:32.619562
377 12:26:32.619623 EC: 0000 0021 [4000]
378 12:26:32.622694
379 12:26:32.622778 S7: 0000 0000 [0000]
380 12:26:32.622868
381 12:26:32.626419 CC: 0000 0000 [0001]
382 12:26:32.626502
383 12:26:32.626583 T0: 0000 0040 [010F]
384 12:26:32.626647
385 12:26:32.626708 Jump to BL
386 12:26:32.626767
387 12:26:32.652848
388 12:26:32.652936
389 12:26:32.653003
390 12:26:32.659556 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 12:26:32.662523 ARM64: Exception handlers installed.
392 12:26:32.666709 ARM64: Testing exception
393 12:26:32.669708 ARM64: Done test exception
394 12:26:32.676708 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 12:26:32.686425 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 12:26:32.693102 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 12:26:32.703422 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 12:26:32.709677 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 12:26:32.720078 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 12:26:32.730735 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 12:26:32.737228 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 12:26:32.755651 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 12:26:32.758861 WDT: Last reset was cold boot
404 12:26:32.761850 SPI1(PAD0) initialized at 2873684 Hz
405 12:26:32.765787 SPI5(PAD0) initialized at 992727 Hz
406 12:26:32.768595 VBOOT: Loading verstage.
407 12:26:32.775062 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 12:26:32.778575 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 12:26:32.781599 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 12:26:32.785191 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 12:26:32.792608 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 12:26:32.799626 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 12:26:32.810051 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 12:26:32.810305
415 12:26:32.810469
416 12:26:32.820402 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 12:26:32.823599 ARM64: Exception handlers installed.
418 12:26:32.826737 ARM64: Testing exception
419 12:26:32.826957 ARM64: Done test exception
420 12:26:32.834589 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 12:26:32.838176 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:26:32.851377 Probing TPM: . done!
423 12:26:32.851623 TPM ready after 0 ms
424 12:26:32.858095 Connected to device vid:did:rid of 1ae0:0028:00
425 12:26:32.865149 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 12:26:32.906331 Initialized TPM device CR50 revision 0
427 12:26:32.918198 tlcl_send_startup: Startup return code is 0
428 12:26:32.918435 TPM: setup succeeded
429 12:26:32.929109 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 12:26:32.938321 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 12:26:32.950356 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 12:26:32.959213 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 12:26:32.962434 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 12:26:32.966286 in-header: 03 07 00 00 08 00 00 00
435 12:26:32.969584 in-data: aa e4 47 04 13 02 00 00
436 12:26:32.972867 Chrome EC: UHEPI supported
437 12:26:32.979774 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 12:26:32.983347 in-header: 03 9d 00 00 08 00 00 00
439 12:26:32.986923 in-data: 10 20 20 08 00 00 00 00
440 12:26:32.987124 Phase 1
441 12:26:32.990723 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 12:26:32.997878 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 12:26:33.005444 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 12:26:33.005677 Recovery requested (1009000e)
445 12:26:33.014612 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 12:26:33.019389 tlcl_extend: response is 0
447 12:26:33.027955 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 12:26:33.032864 tlcl_extend: response is 0
449 12:26:33.039800 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 12:26:33.060694 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 12:26:33.067841 BS: bootblock times (exec / console): total (unknown) / 149 ms
452 12:26:33.068098
453 12:26:33.068255
454 12:26:33.078675 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 12:26:33.078924 ARM64: Exception handlers installed.
456 12:26:33.082401 ARM64: Testing exception
457 12:26:33.085598 ARM64: Done test exception
458 12:26:33.106330 pmic_efuse_setting: Set efuses in 11 msecs
459 12:26:33.109342 pmwrap_interface_init: Select PMIF_VLD_RDY
460 12:26:33.116700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 12:26:33.120309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 12:26:33.123975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 12:26:33.131475 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 12:26:33.135380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 12:26:33.138888 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 12:26:33.142694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 12:26:33.149631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 12:26:33.152825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 12:26:33.156539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 12:26:33.162995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 12:26:33.166153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 12:26:33.173170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 12:26:33.176308 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 12:26:33.182755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 12:26:33.189231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 12:26:33.196246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 12:26:33.199155 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 12:26:33.206157 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 12:26:33.213647 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 12:26:33.217128 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 12:26:33.224131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 12:26:33.227703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 12:26:33.234330 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 12:26:33.237918 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 12:26:33.244859 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 12:26:33.251898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 12:26:33.255689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 12:26:33.258863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 12:26:33.265141 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 12:26:33.268889 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 12:26:33.276510 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 12:26:33.279674 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 12:26:33.283512 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 12:26:33.291226 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 12:26:33.294394 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 12:26:33.301396 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 12:26:33.304688 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 12:26:33.307720 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 12:26:33.314735 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 12:26:33.317664 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 12:26:33.321226 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 12:26:33.328044 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 12:26:33.331205 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 12:26:33.334675 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 12:26:33.341138 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 12:26:33.344598 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 12:26:33.347948 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 12:26:33.350960 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 12:26:33.358030 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 12:26:33.361231 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 12:26:33.367607 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 12:26:33.377828 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 12:26:33.380963 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 12:26:33.391202 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 12:26:33.397593 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 12:26:33.404527 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 12:26:33.407650 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 12:26:33.410770 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 12:26:33.418111 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
520 12:26:33.425145 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 12:26:33.428176 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 12:26:33.434664 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 12:26:33.442799 [RTC]rtc_get_frequency_meter,154: input=15, output=794
524 12:26:33.446293 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 12:26:33.452710 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 12:26:33.456311 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 12:26:33.459943 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 12:26:33.463228 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 12:26:33.466271 ADC[4]: Raw value=895930 ID=7
530 12:26:33.469414 ADC[3]: Raw value=213440 ID=1
531 12:26:33.472653 RAM Code: 0x71
532 12:26:33.476354 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 12:26:33.479625 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 12:26:33.489656 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 12:26:33.496623 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 12:26:33.499784 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 12:26:33.509304 in-header: 03 07 00 00 08 00 00 00
538 12:26:33.513032 in-data: aa e4 47 04 13 02 00 00
539 12:26:33.516848 Chrome EC: UHEPI supported
540 12:26:33.524229 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 12:26:33.527780 in-header: 03 95 00 00 08 00 00 00
542 12:26:33.527900 in-data: 18 20 20 08 00 00 00 00
543 12:26:33.531326 MRC: failed to locate region type 0.
544 12:26:33.538537 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 12:26:33.542256 DRAM-K: Running full calibration
546 12:26:33.549242 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 12:26:33.549392 header.status = 0x0
548 12:26:33.553035 header.version = 0x6 (expected: 0x6)
549 12:26:33.556771 header.size = 0xd00 (expected: 0xd00)
550 12:26:33.556877 header.flags = 0x0
551 12:26:33.563890 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 12:26:33.583102 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
553 12:26:33.590127 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 12:26:33.593857 dram_init: ddr_geometry: 2
555 12:26:33.593965 [EMI] MDL number = 2
556 12:26:33.596871 [EMI] Get MDL freq = 0
557 12:26:33.596958 dram_init: ddr_type: 0
558 12:26:33.600635 is_discrete_lpddr4: 1
559 12:26:33.603718 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 12:26:33.603805
561 12:26:33.603872
562 12:26:33.606992 [Bian_co] ETT version 0.0.0.1
563 12:26:33.610362 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 12:26:33.610484
565 12:26:33.613983 dramc_set_vcore_voltage set vcore to 650000
566 12:26:33.617758 Read voltage for 800, 4
567 12:26:33.617889 Vio18 = 0
568 12:26:33.621536 Vcore = 650000
569 12:26:33.621621 Vdram = 0
570 12:26:33.621708 Vddq = 0
571 12:26:33.621827 Vmddr = 0
572 12:26:33.625262 dram_init: config_dvfs: 1
573 12:26:33.628886 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 12:26:33.635989 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 12:26:33.638734 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 12:26:33.642332 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 12:26:33.645904 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 12:26:33.648889 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 12:26:33.652494 MEM_TYPE=3, freq_sel=18
580 12:26:34.717203 sv_algorithm_assistance_LP4_1600
581 12:26:34.730524 ============ PULL DRAM RESETB DOWN ============
582 12:26:34.730701 ========== PULL DRAM RESETB DOWN end =========
583 12:26:34.730834 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 12:26:34.730954 ===================================
585 12:26:34.731046 LPDDR4 DRAM CONFIGURATION
586 12:26:34.731182 ===================================
587 12:26:34.731304 EX_ROW_EN[0] = 0x0
588 12:26:34.731409 EX_ROW_EN[1] = 0x0
589 12:26:34.731516 LP4Y_EN = 0x0
590 12:26:34.731610 WORK_FSP = 0x0
591 12:26:34.731706 WL = 0x2
592 12:26:34.731801 RL = 0x2
593 12:26:34.731923 BL = 0x2
594 12:26:34.732025 RPST = 0x0
595 12:26:34.732115 RD_PRE = 0x0
596 12:26:34.732215 WR_PRE = 0x1
597 12:26:34.732314 WR_PST = 0x0
598 12:26:34.732418 DBI_WR = 0x0
599 12:26:34.732518 DBI_RD = 0x0
600 12:26:34.732608 OTF = 0x1
601 12:26:34.732698 ===================================
602 12:26:34.732819 ===================================
603 12:26:34.732894 ANA top config
604 12:26:34.732953 ===================================
605 12:26:34.733024 DLL_ASYNC_EN = 0
606 12:26:34.733088 ALL_SLAVE_EN = 1
607 12:26:34.733165 NEW_RANK_MODE = 1
608 12:26:34.733257 DLL_IDLE_MODE = 1
609 12:26:34.733358 LP45_APHY_COMB_EN = 1
610 12:26:34.733447 TX_ODT_DIS = 1
611 12:26:34.733534 NEW_8X_MODE = 1
612 12:26:34.733641 ===================================
613 12:26:34.733736 ===================================
614 12:26:34.733831 data_rate = 1600
615 12:26:34.733924 CKR = 1
616 12:26:34.734018 DQ_P2S_RATIO = 8
617 12:26:34.734109 ===================================
618 12:26:34.734199 CA_P2S_RATIO = 8
619 12:26:34.734285 DQ_CA_OPEN = 0
620 12:26:34.734373 DQ_SEMI_OPEN = 0
621 12:26:34.734463 CA_SEMI_OPEN = 0
622 12:26:34.734559 CA_FULL_RATE = 0
623 12:26:34.734649 DQ_CKDIV4_EN = 1
624 12:26:34.734765 CA_CKDIV4_EN = 1
625 12:26:34.734876 CA_PREDIV_EN = 0
626 12:26:34.734934 PH8_DLY = 0
627 12:26:34.734989 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 12:26:34.735043 DQ_AAMCK_DIV = 4
629 12:26:34.735106 CA_AAMCK_DIV = 4
630 12:26:34.735161 CA_ADMCK_DIV = 4
631 12:26:34.735215 DQ_TRACK_CA_EN = 0
632 12:26:34.735269 CA_PICK = 800
633 12:26:34.735324 CA_MCKIO = 800
634 12:26:34.735434 MCKIO_SEMI = 0
635 12:26:34.735490 PLL_FREQ = 3068
636 12:26:34.735620 DQ_UI_PI_RATIO = 32
637 12:26:34.735749 CA_UI_PI_RATIO = 0
638 12:26:34.735836 ===================================
639 12:26:34.735914 ===================================
640 12:26:34.736002 memory_type:LPDDR4
641 12:26:34.736087 GP_NUM : 10
642 12:26:34.736201 SRAM_EN : 1
643 12:26:34.736258 MD32_EN : 0
644 12:26:34.736313 ===================================
645 12:26:34.736369 [ANA_INIT] >>>>>>>>>>>>>>
646 12:26:34.736444 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 12:26:34.736533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 12:26:34.736620 ===================================
649 12:26:34.736752 data_rate = 1600,PCW = 0X7600
650 12:26:34.736863 ===================================
651 12:26:34.736940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 12:26:34.737092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 12:26:34.737195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 12:26:34.737286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 12:26:34.737397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 12:26:34.737459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 12:26:34.737516 [ANA_INIT] flow start
658 12:26:34.737575 [ANA_INIT] PLL >>>>>>>>
659 12:26:34.737635 [ANA_INIT] PLL <<<<<<<<
660 12:26:34.737694 [ANA_INIT] MIDPI >>>>>>>>
661 12:26:34.737805 [ANA_INIT] MIDPI <<<<<<<<
662 12:26:34.737893 [ANA_INIT] DLL >>>>>>>>
663 12:26:34.737978 [ANA_INIT] flow end
664 12:26:34.738069 ============ LP4 DIFF to SE enter ============
665 12:26:34.738163 ============ LP4 DIFF to SE exit ============
666 12:26:34.738250 [ANA_INIT] <<<<<<<<<<<<<
667 12:26:34.738340 [Flow] Enable top DCM control >>>>>
668 12:26:34.738427 [Flow] Enable top DCM control <<<<<
669 12:26:34.738515 Enable DLL master slave shuffle
670 12:26:34.738611 ==============================================================
671 12:26:34.738708 Gating Mode config
672 12:26:34.738815 ==============================================================
673 12:26:34.738901 Config description:
674 12:26:34.738957 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 12:26:34.739019 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 12:26:34.739075 SELPH_MODE 0: By rank 1: By Phase
677 12:26:34.739130 ==============================================================
678 12:26:34.739211 GAT_TRACK_EN = 1
679 12:26:34.739305 RX_GATING_MODE = 2
680 12:26:34.739361 RX_GATING_TRACK_MODE = 2
681 12:26:34.739417 SELPH_MODE = 1
682 12:26:34.739472 PICG_EARLY_EN = 1
683 12:26:34.739534 VALID_LAT_VALUE = 1
684 12:26:34.739591 ==============================================================
685 12:26:34.739646 Enter into Gating configuration >>>>
686 12:26:34.739711 Exit from Gating configuration <<<<
687 12:26:34.739776 Enter into DVFS_PRE_config >>>>>
688 12:26:34.739865 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 12:26:34.739954 Exit from DVFS_PRE_config <<<<<
690 12:26:34.740030 Enter into PICG configuration >>>>
691 12:26:34.740116 Exit from PICG configuration <<<<
692 12:26:34.740199 [RX_INPUT] configuration >>>>>
693 12:26:34.740287 [RX_INPUT] configuration <<<<<
694 12:26:34.740396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 12:26:34.740689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 12:26:34.740837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 12:26:34.740944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 12:26:34.741050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 12:26:34.741159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 12:26:34.741249 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 12:26:34.741334 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 12:26:34.741419 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 12:26:34.741557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 12:26:34.741657 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 12:26:34.741744 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 12:26:34.741829 ===================================
707 12:26:34.741913 LPDDR4 DRAM CONFIGURATION
708 12:26:34.742001 ===================================
709 12:26:34.742138 EX_ROW_EN[0] = 0x0
710 12:26:34.742277 EX_ROW_EN[1] = 0x0
711 12:26:34.742363 LP4Y_EN = 0x0
712 12:26:34.742459 WORK_FSP = 0x0
713 12:26:34.742582 WL = 0x2
714 12:26:34.742681 RL = 0x2
715 12:26:34.742807 BL = 0x2
716 12:26:34.742940 RPST = 0x0
717 12:26:34.743054 RD_PRE = 0x0
718 12:26:34.743159 WR_PRE = 0x1
719 12:26:34.743309 WR_PST = 0x0
720 12:26:34.743435 DBI_WR = 0x0
721 12:26:34.743529 DBI_RD = 0x0
722 12:26:34.743625 OTF = 0x1
723 12:26:34.743713 ===================================
724 12:26:34.743833 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 12:26:34.743949 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 12:26:34.744066 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:26:34.744153 ===================================
728 12:26:34.744242 LPDDR4 DRAM CONFIGURATION
729 12:26:34.744329 ===================================
730 12:26:34.744415 EX_ROW_EN[0] = 0x10
731 12:26:34.744501 EX_ROW_EN[1] = 0x0
732 12:26:34.744592 LP4Y_EN = 0x0
733 12:26:34.744680 WORK_FSP = 0x0
734 12:26:34.744787 WL = 0x2
735 12:26:34.744875 RL = 0x2
736 12:26:34.744964 BL = 0x2
737 12:26:34.745049 RPST = 0x0
738 12:26:34.745137 RD_PRE = 0x0
739 12:26:34.745225 WR_PRE = 0x1
740 12:26:34.745316 WR_PST = 0x0
741 12:26:34.745403 DBI_WR = 0x0
742 12:26:34.745490 DBI_RD = 0x0
743 12:26:34.745580 OTF = 0x1
744 12:26:34.745668 ===================================
745 12:26:34.745758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 12:26:34.745849 nWR fixed to 40
747 12:26:34.745936 [ModeRegInit_LP4] CH0 RK0
748 12:26:34.746025 [ModeRegInit_LP4] CH0 RK1
749 12:26:34.746113 [ModeRegInit_LP4] CH1 RK0
750 12:26:34.746199 [ModeRegInit_LP4] CH1 RK1
751 12:26:34.746299 match AC timing 13
752 12:26:34.746386 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 12:26:34.746473 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 12:26:34.746567 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 12:26:34.746656 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 12:26:34.746759 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 12:26:34.746855 [EMI DOE] emi_dcm 0
758 12:26:34.746918 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 12:26:34.746980 ==
760 12:26:34.747044 Dram Type= 6, Freq= 0, CH_0, rank 0
761 12:26:34.747131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 12:26:34.747219 ==
763 12:26:34.747310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 12:26:34.747399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 12:26:34.747485 [CA 0] Center 38 (7~69) winsize 63
766 12:26:34.747571 [CA 1] Center 37 (7~68) winsize 62
767 12:26:34.747666 [CA 2] Center 35 (5~66) winsize 62
768 12:26:34.747757 [CA 3] Center 35 (5~66) winsize 62
769 12:26:34.747846 [CA 4] Center 34 (4~65) winsize 62
770 12:26:34.747933 [CA 5] Center 33 (3~64) winsize 62
771 12:26:34.748021
772 12:26:34.748108 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 12:26:34.748193
774 12:26:34.748283 [CATrainingPosCal] consider 1 rank data
775 12:26:34.748371 u2DelayCellTimex100 = 270/100 ps
776 12:26:34.748457 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
777 12:26:34.748542 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
778 12:26:34.748632 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
779 12:26:34.748725 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
780 12:26:34.748826 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
781 12:26:34.748917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
782 12:26:34.749005
783 12:26:34.749092 CA PerBit enable=1, Macro0, CA PI delay=33
784 12:26:34.749178
785 12:26:34.749265 [CBTSetCACLKResult] CA Dly = 33
786 12:26:34.749355 CS Dly: 6 (0~37)
787 12:26:34.749446 ==
788 12:26:34.749536 Dram Type= 6, Freq= 0, CH_0, rank 1
789 12:26:34.749625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 12:26:34.749713 ==
791 12:26:34.749801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 12:26:34.749889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 12:26:34.749990 [CA 0] Center 38 (7~69) winsize 63
794 12:26:34.750079 [CA 1] Center 37 (7~68) winsize 62
795 12:26:34.750166 [CA 2] Center 35 (5~66) winsize 62
796 12:26:34.750255 [CA 3] Center 35 (5~66) winsize 62
797 12:26:34.750341 [CA 4] Center 34 (4~65) winsize 62
798 12:26:34.750428 [CA 5] Center 34 (4~65) winsize 62
799 12:26:34.750519
800 12:26:34.750607 [CmdBusTrainingLP45] Vref(ca) range 1: 32
801 12:26:34.750694
802 12:26:34.750797 [CATrainingPosCal] consider 2 rank data
803 12:26:34.750880 u2DelayCellTimex100 = 270/100 ps
804 12:26:34.750970 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 12:26:34.751061 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 12:26:34.751151 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 12:26:34.751237 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 12:26:34.751324 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 12:26:34.751412 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
810 12:26:34.751501
811 12:26:34.751586 CA PerBit enable=1, Macro0, CA PI delay=34
812 12:26:34.751676
813 12:26:34.751765 [CBTSetCACLKResult] CA Dly = 34
814 12:26:34.751850 CS Dly: 6 (0~37)
815 12:26:34.751941
816 12:26:34.752028 ----->DramcWriteLeveling(PI) begin...
817 12:26:34.752117 ==
818 12:26:34.752401 Dram Type= 6, Freq= 0, CH_0, rank 0
819 12:26:34.752499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 12:26:34.752597 ==
821 12:26:34.752686 Write leveling (Byte 0): 34 => 34
822 12:26:34.752777 Write leveling (Byte 1): 29 => 29
823 12:26:34.752867 DramcWriteLeveling(PI) end<-----
824 12:26:34.752955
825 12:26:34.753042 ==
826 12:26:34.753138 Dram Type= 6, Freq= 0, CH_0, rank 0
827 12:26:34.753226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 12:26:34.753312 ==
829 12:26:34.753404 [Gating] SW mode calibration
830 12:26:34.753492 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 12:26:34.753583 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 12:26:34.753670 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 12:26:34.753760 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
834 12:26:34.753846 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
835 12:26:34.753925 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 12:26:34.753993 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 12:26:34.754081 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 12:26:34.754167 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:26:34.754257 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:26:34.754344 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:26:34.754432 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:26:34.754524 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:26:34.754617 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:26:34.754708 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:26:34.754797 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:26:34.754887 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:26:34.754979 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:26:34.755065 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:26:34.755157 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 12:26:34.755244 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
851 12:26:34.755319 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:26:34.755405 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 12:26:34.755492 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:26:34.755582 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:26:34.755668 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:26:34.755760 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:26:34.755851 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:26:34.755938 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:26:34.756029 0 9 12 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
860 12:26:34.756118 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 12:26:34.756204 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 12:26:34.756307 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 12:26:34.756395 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 12:26:34.756485 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 12:26:34.756573 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 12:26:34.756663 0 10 8 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
867 12:26:34.756750 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
868 12:26:34.756843 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:26:34.756943 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:26:34.757034 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:26:34.757121 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:26:34.757208 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:26:34.757296 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:26:34.757389 0 11 8 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
875 12:26:34.757476 0 11 12 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0)
876 12:26:34.757569 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 12:26:34.757658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 12:26:34.757747 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 12:26:34.757834 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 12:26:34.757920 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 12:26:34.758004 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 12:26:34.758062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 12:26:34.758118 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
884 12:26:34.758185 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 12:26:34.758272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 12:26:34.758359 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 12:26:34.758445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 12:26:34.758539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 12:26:34.758630 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 12:26:34.758716 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 12:26:34.758803 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 12:26:34.758888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 12:26:34.758951 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 12:26:34.759007 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 12:26:34.759074 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 12:26:34.759136 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 12:26:34.759193 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 12:26:34.759249 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
899 12:26:34.759304 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:26:34.759358 Total UI for P1: 0, mck2ui 16
901 12:26:34.759416 best dqsien dly found for B0: ( 0, 14, 8)
902 12:26:34.759485 Total UI for P1: 0, mck2ui 16
903 12:26:34.759577 best dqsien dly found for B1: ( 0, 14, 10)
904 12:26:34.759664 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
905 12:26:34.759948 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
906 12:26:34.760040
907 12:26:34.760129 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
908 12:26:34.760219 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
909 12:26:34.760305 [Gating] SW calibration Done
910 12:26:34.760394 ==
911 12:26:34.760481 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:26:34.760570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:26:34.760659 ==
914 12:26:34.760745 RX Vref Scan: 0
915 12:26:34.760833
916 12:26:34.760923 RX Vref 0 -> 0, step: 1
917 12:26:34.761007
918 12:26:34.761110 RX Delay -130 -> 252, step: 16
919 12:26:34.763275 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
920 12:26:34.766255 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
921 12:26:34.773373 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
922 12:26:34.776608 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
923 12:26:34.779719 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
924 12:26:34.783392 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
925 12:26:34.786584 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
926 12:26:34.792880 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
927 12:26:34.796663 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
928 12:26:34.799732 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
929 12:26:34.802761 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
930 12:26:34.805965 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
931 12:26:34.812615 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
932 12:26:34.816125 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
933 12:26:34.819836 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
934 12:26:34.822854 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
935 12:26:34.823008 ==
936 12:26:34.826563 Dram Type= 6, Freq= 0, CH_0, rank 0
937 12:26:34.832629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 12:26:34.832749 ==
939 12:26:34.832858 DQS Delay:
940 12:26:34.836193 DQS0 = 0, DQS1 = 0
941 12:26:34.836303 DQM Delay:
942 12:26:34.836399 DQM0 = 82, DQM1 = 69
943 12:26:34.839236 DQ Delay:
944 12:26:34.842697 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
945 12:26:34.846318 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
946 12:26:34.849359 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
947 12:26:34.852969 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
948 12:26:34.853057
949 12:26:34.853131
950 12:26:34.853195 ==
951 12:26:34.856732 Dram Type= 6, Freq= 0, CH_0, rank 0
952 12:26:34.859945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 12:26:34.860026 ==
954 12:26:34.860094
955 12:26:34.860155
956 12:26:34.863018 TX Vref Scan disable
957 12:26:34.863115 == TX Byte 0 ==
958 12:26:34.869898 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
959 12:26:34.873094 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
960 12:26:34.873184 == TX Byte 1 ==
961 12:26:34.879376 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
962 12:26:34.883150 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
963 12:26:34.883265 ==
964 12:26:34.886218 Dram Type= 6, Freq= 0, CH_0, rank 0
965 12:26:34.889406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 12:26:34.889492 ==
967 12:26:34.904037 TX Vref=22, minBit 7, minWin=26, winSum=433
968 12:26:34.907125 TX Vref=24, minBit 0, minWin=27, winSum=438
969 12:26:34.910295 TX Vref=26, minBit 0, minWin=27, winSum=444
970 12:26:34.913887 TX Vref=28, minBit 0, minWin=27, winSum=444
971 12:26:34.917627 TX Vref=30, minBit 11, minWin=27, winSum=444
972 12:26:34.923828 TX Vref=32, minBit 4, minWin=27, winSum=441
973 12:26:34.927480 [TxChooseVref] Worse bit 0, Min win 27, Win sum 444, Final Vref 26
974 12:26:34.927600
975 12:26:34.930808 Final TX Range 1 Vref 26
976 12:26:34.930905
977 12:26:34.930981 ==
978 12:26:34.933790 Dram Type= 6, Freq= 0, CH_0, rank 0
979 12:26:34.937570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 12:26:34.937667 ==
981 12:26:34.940648
982 12:26:34.940752
983 12:26:34.940817 TX Vref Scan disable
984 12:26:34.944186 == TX Byte 0 ==
985 12:26:34.947191 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
986 12:26:34.953929 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
987 12:26:34.954014 == TX Byte 1 ==
988 12:26:34.957408 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
989 12:26:34.963960 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
990 12:26:34.964041
991 12:26:34.964108 [DATLAT]
992 12:26:34.964170 Freq=800, CH0 RK0
993 12:26:34.964246
994 12:26:34.967161 DATLAT Default: 0xa
995 12:26:34.967274 0, 0xFFFF, sum = 0
996 12:26:34.970682 1, 0xFFFF, sum = 0
997 12:26:34.973818 2, 0xFFFF, sum = 0
998 12:26:34.973908 3, 0xFFFF, sum = 0
999 12:26:34.977062 4, 0xFFFF, sum = 0
1000 12:26:34.977158 5, 0xFFFF, sum = 0
1001 12:26:34.980279 6, 0xFFFF, sum = 0
1002 12:26:34.980365 7, 0xFFFF, sum = 0
1003 12:26:34.984017 8, 0xFFFF, sum = 0
1004 12:26:34.984101 9, 0x0, sum = 1
1005 12:26:34.987194 10, 0x0, sum = 2
1006 12:26:34.987284 11, 0x0, sum = 3
1007 12:26:34.987351 12, 0x0, sum = 4
1008 12:26:34.990338 best_step = 10
1009 12:26:34.990412
1010 12:26:34.990482 ==
1011 12:26:34.993583 Dram Type= 6, Freq= 0, CH_0, rank 0
1012 12:26:34.996822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1013 12:26:34.996936 ==
1014 12:26:35.000063 RX Vref Scan: 1
1015 12:26:35.000165
1016 12:26:35.003781 Set Vref Range= 32 -> 127
1017 12:26:35.003869
1018 12:26:35.003937 RX Vref 32 -> 127, step: 1
1019 12:26:35.003999
1020 12:26:35.006783 RX Delay -111 -> 252, step: 8
1021 12:26:35.006899
1022 12:26:35.010435 Set Vref, RX VrefLevel [Byte0]: 32
1023 12:26:35.013611 [Byte1]: 32
1024 12:26:35.016733
1025 12:26:35.016825 Set Vref, RX VrefLevel [Byte0]: 33
1026 12:26:35.020276 [Byte1]: 33
1027 12:26:35.024751
1028 12:26:35.024842 Set Vref, RX VrefLevel [Byte0]: 34
1029 12:26:35.028007 [Byte1]: 34
1030 12:26:35.032020
1031 12:26:35.035348 Set Vref, RX VrefLevel [Byte0]: 35
1032 12:26:35.035487 [Byte1]: 35
1033 12:26:35.039918
1034 12:26:35.040046 Set Vref, RX VrefLevel [Byte0]: 36
1035 12:26:35.043105 [Byte1]: 36
1036 12:26:35.047496
1037 12:26:35.047613 Set Vref, RX VrefLevel [Byte0]: 37
1038 12:26:35.050508 [Byte1]: 37
1039 12:26:35.055310
1040 12:26:35.055429 Set Vref, RX VrefLevel [Byte0]: 38
1041 12:26:35.058099 [Byte1]: 38
1042 12:26:35.062776
1043 12:26:35.062900 Set Vref, RX VrefLevel [Byte0]: 39
1044 12:26:35.065710 [Byte1]: 39
1045 12:26:35.070758
1046 12:26:35.070887 Set Vref, RX VrefLevel [Byte0]: 40
1047 12:26:35.073601 [Byte1]: 40
1048 12:26:35.077723
1049 12:26:35.077833 Set Vref, RX VrefLevel [Byte0]: 41
1050 12:26:35.081389 [Byte1]: 41
1051 12:26:35.085779
1052 12:26:35.085899 Set Vref, RX VrefLevel [Byte0]: 42
1053 12:26:35.088987 [Byte1]: 42
1054 12:26:35.093488
1055 12:26:35.093599 Set Vref, RX VrefLevel [Byte0]: 43
1056 12:26:35.096642 [Byte1]: 43
1057 12:26:35.101169
1058 12:26:35.101273 Set Vref, RX VrefLevel [Byte0]: 44
1059 12:26:35.104330 [Byte1]: 44
1060 12:26:35.108626
1061 12:26:35.108770 Set Vref, RX VrefLevel [Byte0]: 45
1062 12:26:35.112314 [Byte1]: 45
1063 12:26:35.116761
1064 12:26:35.116863 Set Vref, RX VrefLevel [Byte0]: 46
1065 12:26:35.119909 [Byte1]: 46
1066 12:26:35.124187
1067 12:26:35.124301 Set Vref, RX VrefLevel [Byte0]: 47
1068 12:26:35.127176 [Byte1]: 47
1069 12:26:35.131518
1070 12:26:35.134627 Set Vref, RX VrefLevel [Byte0]: 48
1071 12:26:35.134756 [Byte1]: 48
1072 12:26:35.139222
1073 12:26:35.139311 Set Vref, RX VrefLevel [Byte0]: 49
1074 12:26:35.142498 [Byte1]: 49
1075 12:26:35.146585
1076 12:26:35.146694 Set Vref, RX VrefLevel [Byte0]: 50
1077 12:26:35.150119 [Byte1]: 50
1078 12:26:35.154362
1079 12:26:35.154451 Set Vref, RX VrefLevel [Byte0]: 51
1080 12:26:35.158087 [Byte1]: 51
1081 12:26:35.162368
1082 12:26:35.162455 Set Vref, RX VrefLevel [Byte0]: 52
1083 12:26:35.165247 [Byte1]: 52
1084 12:26:35.169725
1085 12:26:35.169816 Set Vref, RX VrefLevel [Byte0]: 53
1086 12:26:35.173390 [Byte1]: 53
1087 12:26:35.177674
1088 12:26:35.177762 Set Vref, RX VrefLevel [Byte0]: 54
1089 12:26:35.180722 [Byte1]: 54
1090 12:26:35.184956
1091 12:26:35.185041 Set Vref, RX VrefLevel [Byte0]: 55
1092 12:26:35.188154 [Byte1]: 55
1093 12:26:35.192633
1094 12:26:35.192746 Set Vref, RX VrefLevel [Byte0]: 56
1095 12:26:35.195818 [Byte1]: 56
1096 12:26:35.200233
1097 12:26:35.200321 Set Vref, RX VrefLevel [Byte0]: 57
1098 12:26:35.203397 [Byte1]: 57
1099 12:26:35.207745
1100 12:26:35.207865 Set Vref, RX VrefLevel [Byte0]: 58
1101 12:26:35.211006 [Byte1]: 58
1102 12:26:35.215511
1103 12:26:35.215622 Set Vref, RX VrefLevel [Byte0]: 59
1104 12:26:35.219160 [Byte1]: 59
1105 12:26:35.223069
1106 12:26:35.223184 Set Vref, RX VrefLevel [Byte0]: 60
1107 12:26:35.226794 [Byte1]: 60
1108 12:26:35.231087
1109 12:26:35.231198 Set Vref, RX VrefLevel [Byte0]: 61
1110 12:26:35.234161 [Byte1]: 61
1111 12:26:35.238702
1112 12:26:35.238848 Set Vref, RX VrefLevel [Byte0]: 62
1113 12:26:35.241738 [Byte1]: 62
1114 12:26:35.246356
1115 12:26:35.246468 Set Vref, RX VrefLevel [Byte0]: 63
1116 12:26:35.249678 [Byte1]: 63
1117 12:26:35.253631
1118 12:26:35.253738 Set Vref, RX VrefLevel [Byte0]: 64
1119 12:26:35.257160 [Byte1]: 64
1120 12:26:35.261597
1121 12:26:35.261684 Set Vref, RX VrefLevel [Byte0]: 65
1122 12:26:35.264611 [Byte1]: 65
1123 12:26:35.269456
1124 12:26:35.269579 Set Vref, RX VrefLevel [Byte0]: 66
1125 12:26:35.272470 [Byte1]: 66
1126 12:26:35.276529
1127 12:26:35.276641 Set Vref, RX VrefLevel [Byte0]: 67
1128 12:26:35.279923 [Byte1]: 67
1129 12:26:35.284131
1130 12:26:35.284254 Set Vref, RX VrefLevel [Byte0]: 68
1131 12:26:35.287713 [Byte1]: 68
1132 12:26:35.291822
1133 12:26:35.291935 Set Vref, RX VrefLevel [Byte0]: 69
1134 12:26:35.295606 [Byte1]: 69
1135 12:26:35.300014
1136 12:26:35.300127 Set Vref, RX VrefLevel [Byte0]: 70
1137 12:26:35.303161 [Byte1]: 70
1138 12:26:35.307104
1139 12:26:35.307191 Set Vref, RX VrefLevel [Byte0]: 71
1140 12:26:35.310919 [Byte1]: 71
1141 12:26:35.314695
1142 12:26:35.314801 Set Vref, RX VrefLevel [Byte0]: 72
1143 12:26:35.318356 [Byte1]: 72
1144 12:26:35.322653
1145 12:26:35.322763 Set Vref, RX VrefLevel [Byte0]: 73
1146 12:26:35.325780 [Byte1]: 73
1147 12:26:35.330118
1148 12:26:35.330244 Set Vref, RX VrefLevel [Byte0]: 74
1149 12:26:35.333758 [Byte1]: 74
1150 12:26:35.338163
1151 12:26:35.338268 Set Vref, RX VrefLevel [Byte0]: 75
1152 12:26:35.341396 [Byte1]: 75
1153 12:26:35.345648
1154 12:26:35.345760 Set Vref, RX VrefLevel [Byte0]: 76
1155 12:26:35.348968 [Byte1]: 76
1156 12:26:35.353209
1157 12:26:35.353290 Set Vref, RX VrefLevel [Byte0]: 77
1158 12:26:35.356812 [Byte1]: 77
1159 12:26:35.361177
1160 12:26:35.361281 Set Vref, RX VrefLevel [Byte0]: 78
1161 12:26:35.364282 [Byte1]: 78
1162 12:26:35.368451
1163 12:26:35.368579 Set Vref, RX VrefLevel [Byte0]: 79
1164 12:26:35.371477 [Byte1]: 79
1165 12:26:35.376306
1166 12:26:35.376418 Final RX Vref Byte 0 = 62 to rank0
1167 12:26:35.379408 Final RX Vref Byte 1 = 59 to rank0
1168 12:26:35.382877 Final RX Vref Byte 0 = 62 to rank1
1169 12:26:35.385804 Final RX Vref Byte 1 = 59 to rank1==
1170 12:26:35.389316 Dram Type= 6, Freq= 0, CH_0, rank 0
1171 12:26:35.395804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 12:26:35.395924 ==
1173 12:26:35.396023 DQS Delay:
1174 12:26:35.399393 DQS0 = 0, DQS1 = 0
1175 12:26:35.399470 DQM Delay:
1176 12:26:35.399538 DQM0 = 82, DQM1 = 68
1177 12:26:35.402496 DQ Delay:
1178 12:26:35.405503 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1179 12:26:35.409285 DQ4 =80, DQ5 =72, DQ6 =92, DQ7 =92
1180 12:26:35.412556 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1181 12:26:35.415708 DQ12 =72, DQ13 =76, DQ14 =76, DQ15 =76
1182 12:26:35.415786
1183 12:26:35.415853
1184 12:26:35.422060 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1185 12:26:35.425775 CH0 RK0: MR19=606, MR18=2929
1186 12:26:35.432029 CH0_RK0: MR19=0x606, MR18=0x2929, DQSOSC=399, MR23=63, INC=92, DEC=61
1187 12:26:35.432139
1188 12:26:35.435745 ----->DramcWriteLeveling(PI) begin...
1189 12:26:35.435855 ==
1190 12:26:35.438781 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 12:26:35.441993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 12:26:35.442096 ==
1193 12:26:35.445164 Write leveling (Byte 0): 31 => 31
1194 12:26:35.448969 Write leveling (Byte 1): 32 => 32
1195 12:26:35.452205 DramcWriteLeveling(PI) end<-----
1196 12:26:35.452313
1197 12:26:35.452423 ==
1198 12:26:35.455326 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 12:26:35.459090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 12:26:35.459188 ==
1201 12:26:35.462073 [Gating] SW mode calibration
1202 12:26:35.469011 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1203 12:26:35.475527 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1204 12:26:35.479013 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1205 12:26:35.485057 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 12:26:35.488723 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 12:26:35.492154 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:26:35.498804 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:26:35.501862 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:26:35.505567 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:26:35.511753 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:26:35.515527 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:26:35.518583 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:26:35.521799 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:26:35.528611 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:26:35.572675 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:26:35.573002 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:26:35.573090 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:26:35.573176 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:26:35.573242 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:26:35.573320 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:26:35.573697 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 12:26:35.573790 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:26:35.574038 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:26:35.574117 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:26:35.616672 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:26:35.617000 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:26:35.617076 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:26:35.617142 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1230 12:26:35.617216 0 9 8 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (1 1)
1231 12:26:35.617279 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1232 12:26:35.617783 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 12:26:35.617853 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 12:26:35.618091 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 12:26:35.618164 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 12:26:35.651655 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 12:26:35.652057 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1238 12:26:35.652142 0 10 8 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (1 0)
1239 12:26:35.652236 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:26:35.652326 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:26:35.652414 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:26:35.652513 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:26:35.652601 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:26:35.655342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:26:35.658583 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
1246 12:26:35.665626 0 11 8 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
1247 12:26:35.668754 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 12:26:35.671787 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 12:26:35.678647 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 12:26:35.682173 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 12:26:35.685257 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 12:26:35.689110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:26:35.696588 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 12:26:35.700218 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1255 12:26:35.703233 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 12:26:35.706808 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 12:26:35.713411 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 12:26:35.717357 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:26:35.720371 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:26:35.724109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:26:35.730370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:26:35.734045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:26:35.737041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:26:35.743921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:26:35.747145 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:26:35.750300 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:26:35.757086 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:26:35.760259 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:26:35.763501 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1270 12:26:35.770433 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1271 12:26:35.773354 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1272 12:26:35.777203 Total UI for P1: 0, mck2ui 16
1273 12:26:35.780258 best dqsien dly found for B0: ( 0, 14, 6)
1274 12:26:35.783471 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 12:26:35.786966 Total UI for P1: 0, mck2ui 16
1276 12:26:35.790086 best dqsien dly found for B1: ( 0, 14, 10)
1277 12:26:35.793297 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1278 12:26:35.797016 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1279 12:26:35.800209
1280 12:26:35.803279 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1281 12:26:35.806794 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1282 12:26:35.810104 [Gating] SW calibration Done
1283 12:26:35.810196 ==
1284 12:26:35.813631 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:26:35.816551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:26:35.816668 ==
1287 12:26:35.816773 RX Vref Scan: 0
1288 12:26:35.816879
1289 12:26:35.820065 RX Vref 0 -> 0, step: 1
1290 12:26:35.820160
1291 12:26:35.823080 RX Delay -130 -> 252, step: 16
1292 12:26:35.826477 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1293 12:26:35.829944 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1294 12:26:35.836679 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1295 12:26:35.839675 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1296 12:26:35.843235 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1297 12:26:35.846473 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1298 12:26:35.849684 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1299 12:26:35.856326 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1300 12:26:35.860105 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1301 12:26:35.863218 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1302 12:26:35.866395 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1303 12:26:35.869596 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1304 12:26:35.876607 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1305 12:26:35.879799 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1306 12:26:35.882935 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1307 12:26:35.886668 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1308 12:26:35.886750 ==
1309 12:26:35.889887 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 12:26:35.896247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 12:26:35.896340 ==
1312 12:26:35.896410 DQS Delay:
1313 12:26:35.900029 DQS0 = 0, DQS1 = 0
1314 12:26:35.900119 DQM Delay:
1315 12:26:35.900188 DQM0 = 79, DQM1 = 69
1316 12:26:35.903107 DQ Delay:
1317 12:26:35.906105 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1318 12:26:35.909860 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =101
1319 12:26:35.912974 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1320 12:26:35.916334 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1321 12:26:35.916427
1322 12:26:35.916501
1323 12:26:35.916568 ==
1324 12:26:35.919710 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 12:26:35.922597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 12:26:35.922700 ==
1327 12:26:35.922793
1328 12:26:35.922878
1329 12:26:35.926239 TX Vref Scan disable
1330 12:26:35.929332 == TX Byte 0 ==
1331 12:26:35.932821 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1332 12:26:35.935776 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1333 12:26:35.939278 == TX Byte 1 ==
1334 12:26:35.942812 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1335 12:26:35.945861 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1336 12:26:35.945972 ==
1337 12:26:35.949401 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 12:26:35.953046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 12:26:35.956193 ==
1340 12:26:35.966697 TX Vref=22, minBit 1, minWin=27, winSum=435
1341 12:26:35.969826 TX Vref=24, minBit 1, minWin=27, winSum=443
1342 12:26:35.973646 TX Vref=26, minBit 1, minWin=27, winSum=442
1343 12:26:35.976798 TX Vref=28, minBit 11, minWin=26, winSum=439
1344 12:26:35.979969 TX Vref=30, minBit 1, minWin=27, winSum=445
1345 12:26:35.986693 TX Vref=32, minBit 10, minWin=26, winSum=445
1346 12:26:35.989859 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 30
1347 12:26:35.989987
1348 12:26:35.993540 Final TX Range 1 Vref 30
1349 12:26:35.993655
1350 12:26:35.993759 ==
1351 12:26:35.996599 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 12:26:35.999743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 12:26:36.003506 ==
1354 12:26:36.003622
1355 12:26:36.003720
1356 12:26:36.003810 TX Vref Scan disable
1357 12:26:36.006626 == TX Byte 0 ==
1358 12:26:36.010439 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1359 12:26:36.013558 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1360 12:26:36.016687 == TX Byte 1 ==
1361 12:26:36.020339 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1362 12:26:36.026931 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1363 12:26:36.027033
1364 12:26:36.027099 [DATLAT]
1365 12:26:36.027160 Freq=800, CH0 RK1
1366 12:26:36.027220
1367 12:26:36.030005 DATLAT Default: 0xa
1368 12:26:36.030087 0, 0xFFFF, sum = 0
1369 12:26:36.033590 1, 0xFFFF, sum = 0
1370 12:26:36.033675 2, 0xFFFF, sum = 0
1371 12:26:36.036642 3, 0xFFFF, sum = 0
1372 12:26:36.040261 4, 0xFFFF, sum = 0
1373 12:26:36.040345 5, 0xFFFF, sum = 0
1374 12:26:36.043419 6, 0xFFFF, sum = 0
1375 12:26:36.043503 7, 0xFFFF, sum = 0
1376 12:26:36.046439 8, 0xFFFF, sum = 0
1377 12:26:36.046527 9, 0x0, sum = 1
1378 12:26:36.050107 10, 0x0, sum = 2
1379 12:26:36.050195 11, 0x0, sum = 3
1380 12:26:36.050261 12, 0x0, sum = 4
1381 12:26:36.053336 best_step = 10
1382 12:26:36.053419
1383 12:26:36.053484 ==
1384 12:26:36.056370 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 12:26:36.060093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 12:26:36.060214 ==
1387 12:26:36.062955 RX Vref Scan: 0
1388 12:26:36.063045
1389 12:26:36.063125 RX Vref 0 -> 0, step: 1
1390 12:26:36.066463
1391 12:26:36.066549 RX Delay -111 -> 252, step: 8
1392 12:26:36.073476 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1393 12:26:36.077246 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1394 12:26:36.080423 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1395 12:26:36.083597 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1396 12:26:36.087349 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1397 12:26:36.093690 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1398 12:26:36.096779 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1399 12:26:36.100480 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1400 12:26:36.103764 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1401 12:26:36.106880 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1402 12:26:36.113678 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1403 12:26:36.116872 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1404 12:26:36.120019 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1405 12:26:36.123334 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1406 12:26:36.129843 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1407 12:26:36.133362 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1408 12:26:36.133452 ==
1409 12:26:36.136300 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 12:26:36.139743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 12:26:36.139854 ==
1412 12:26:36.143383 DQS Delay:
1413 12:26:36.143467 DQS0 = 0, DQS1 = 0
1414 12:26:36.143532 DQM Delay:
1415 12:26:36.146346 DQM0 = 78, DQM1 = 71
1416 12:26:36.146428 DQ Delay:
1417 12:26:36.150113 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1418 12:26:36.153078 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1419 12:26:36.156650 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1420 12:26:36.159687 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1421 12:26:36.159770
1422 12:26:36.159835
1423 12:26:36.169530 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1424 12:26:36.169682 CH0 RK1: MR19=606, MR18=4B26
1425 12:26:36.176285 CH0_RK1: MR19=0x606, MR18=0x4B26, DQSOSC=391, MR23=63, INC=96, DEC=64
1426 12:26:36.179515 [RxdqsGatingPostProcess] freq 800
1427 12:26:36.186334 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1428 12:26:36.189990 Pre-setting of DQS Precalculation
1429 12:26:36.193112 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1430 12:26:36.193200 ==
1431 12:26:36.196315 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 12:26:36.203231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 12:26:36.203321 ==
1434 12:26:36.206359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 12:26:36.212502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 12:26:36.221987 [CA 0] Center 36 (6~66) winsize 61
1437 12:26:36.225180 [CA 1] Center 36 (6~67) winsize 62
1438 12:26:36.228954 [CA 2] Center 34 (5~64) winsize 60
1439 12:26:36.232291 [CA 3] Center 34 (4~64) winsize 61
1440 12:26:36.235545 [CA 4] Center 34 (4~64) winsize 61
1441 12:26:36.238683 [CA 5] Center 34 (4~64) winsize 61
1442 12:26:36.238799
1443 12:26:36.241617 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1444 12:26:36.241705
1445 12:26:36.245287 [CATrainingPosCal] consider 1 rank data
1446 12:26:36.248210 u2DelayCellTimex100 = 270/100 ps
1447 12:26:36.251802 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1448 12:26:36.258525 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1449 12:26:36.262153 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1450 12:26:36.265271 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1451 12:26:36.268344 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1452 12:26:36.272094 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1453 12:26:36.272189
1454 12:26:36.275192 CA PerBit enable=1, Macro0, CA PI delay=34
1455 12:26:36.275284
1456 12:26:36.278130 [CBTSetCACLKResult] CA Dly = 34
1457 12:26:36.278214 CS Dly: 5 (0~36)
1458 12:26:36.281696 ==
1459 12:26:36.284924 Dram Type= 6, Freq= 0, CH_1, rank 1
1460 12:26:36.288776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 12:26:36.288876 ==
1462 12:26:36.291799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 12:26:36.298178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 12:26:36.308068 [CA 0] Center 37 (7~67) winsize 61
1465 12:26:36.311148 [CA 1] Center 36 (6~67) winsize 62
1466 12:26:36.314884 [CA 2] Center 34 (4~65) winsize 62
1467 12:26:36.318068 [CA 3] Center 33 (3~64) winsize 62
1468 12:26:36.321170 [CA 4] Center 34 (4~65) winsize 62
1469 12:26:36.324969 [CA 5] Center 33 (3~64) winsize 62
1470 12:26:36.325081
1471 12:26:36.328120 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1472 12:26:36.328238
1473 12:26:36.331266 [CATrainingPosCal] consider 2 rank data
1474 12:26:36.334504 u2DelayCellTimex100 = 270/100 ps
1475 12:26:36.338231 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1476 12:26:36.344823 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 12:26:36.348740 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1478 12:26:36.352116 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1479 12:26:36.354974 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1480 12:26:36.358491 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1481 12:26:36.358603
1482 12:26:36.362075 CA PerBit enable=1, Macro0, CA PI delay=34
1483 12:26:36.362187
1484 12:26:36.365827 [CBTSetCACLKResult] CA Dly = 34
1485 12:26:36.365928 CS Dly: 6 (0~38)
1486 12:26:36.365999
1487 12:26:36.369329 ----->DramcWriteLeveling(PI) begin...
1488 12:26:36.369415 ==
1489 12:26:36.372924 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 12:26:36.376672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 12:26:36.376768 ==
1492 12:26:36.380461 Write leveling (Byte 0): 30 => 30
1493 12:26:36.383477 Write leveling (Byte 1): 30 => 30
1494 12:26:36.387122 DramcWriteLeveling(PI) end<-----
1495 12:26:36.387228
1496 12:26:36.387332 ==
1497 12:26:36.390117 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 12:26:36.393259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 12:26:36.393380 ==
1500 12:26:36.397027 [Gating] SW mode calibration
1501 12:26:36.403731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1502 12:26:36.410429 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1503 12:26:36.413471 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 12:26:36.416589 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 12:26:36.423519 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1506 12:26:36.426747 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:26:36.430508 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:26:36.436887 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:26:36.440233 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:26:36.444049 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:26:36.450683 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:26:36.453908 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:26:36.456801 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:26:36.463724 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:26:36.466658 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:26:36.470322 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:26:36.476845 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:26:36.479974 0 7 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1519 12:26:36.483692 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:26:36.489957 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1521 12:26:36.493275 0 8 8 | B1->B0 | 2323 2322 | 0 1 | (1 0) (1 0)
1522 12:26:36.496387 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:26:36.503242 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:26:36.506847 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:26:36.510006 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:26:36.516850 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:26:36.519991 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:26:36.523039 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:26:36.529698 0 9 8 | B1->B0 | 2727 2525 | 0 1 | (0 0) (0 0)
1530 12:26:36.533001 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 12:26:36.536737 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 12:26:36.543162 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 12:26:36.546384 0 9 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1534 12:26:36.549571 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 12:26:36.556148 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:26:36.559920 0 10 4 | B1->B0 | 3333 3434 | 0 0 | (0 1) (0 1)
1537 12:26:36.562804 0 10 8 | B1->B0 | 3030 2d2d | 1 1 | (1 0) (1 0)
1538 12:26:36.569260 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:26:36.572864 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:26:36.576085 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:26:36.579292 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:26:36.586172 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:26:36.589252 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:26:36.593070 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:26:36.599184 0 11 8 | B1->B0 | 3838 3939 | 1 0 | (0 0) (0 0)
1546 12:26:36.602882 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 12:26:36.605755 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 12:26:36.612529 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 12:26:36.615693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 12:26:36.619489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 12:26:36.625577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:26:36.629243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:26:36.632461 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1554 12:26:36.639129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 12:26:36.642288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:26:36.646002 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:26:36.652265 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:26:36.655506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:26:36.659115 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:26:36.665257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:26:36.668972 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:26:36.672532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:26:36.678857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:26:36.681719 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:26:36.685388 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:26:36.691848 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:26:36.694855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:26:36.698484 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1569 12:26:36.704656 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 12:26:36.708579 Total UI for P1: 0, mck2ui 16
1571 12:26:36.711558 best dqsien dly found for B0: ( 0, 14, 4)
1572 12:26:36.711651 Total UI for P1: 0, mck2ui 16
1573 12:26:36.718231 best dqsien dly found for B1: ( 0, 14, 4)
1574 12:26:36.721390 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1575 12:26:36.724580 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1576 12:26:36.724669
1577 12:26:36.728265 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1578 12:26:36.731424 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1579 12:26:36.734373 [Gating] SW calibration Done
1580 12:26:36.734451 ==
1581 12:26:36.738159 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:26:36.741296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:26:36.741383 ==
1584 12:26:36.744460 RX Vref Scan: 0
1585 12:26:36.744546
1586 12:26:36.744613 RX Vref 0 -> 0, step: 1
1587 12:26:36.744676
1588 12:26:36.747680 RX Delay -130 -> 252, step: 16
1589 12:26:36.754624 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1590 12:26:36.757877 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1591 12:26:36.760941 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1592 12:26:36.764608 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1593 12:26:36.767755 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1594 12:26:36.774640 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1595 12:26:36.777622 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1596 12:26:36.780623 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1597 12:26:36.784160 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1598 12:26:36.787669 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1599 12:26:36.794333 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1600 12:26:36.797923 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1601 12:26:36.800747 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1602 12:26:36.804281 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1603 12:26:36.807380 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1604 12:26:36.814376 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1605 12:26:36.814467 ==
1606 12:26:36.817492 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 12:26:36.820553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 12:26:36.820670 ==
1609 12:26:36.820775 DQS Delay:
1610 12:26:36.823876 DQS0 = 0, DQS1 = 0
1611 12:26:36.823986 DQM Delay:
1612 12:26:36.827073 DQM0 = 80, DQM1 = 70
1613 12:26:36.827176 DQ Delay:
1614 12:26:36.830743 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1615 12:26:36.833986 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1616 12:26:36.837133 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1617 12:26:36.840354 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1618 12:26:36.840463
1619 12:26:36.840566
1620 12:26:36.840665 ==
1621 12:26:36.844155 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 12:26:36.847339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 12:26:36.847434 ==
1624 12:26:36.850387
1625 12:26:36.850489
1626 12:26:36.850582 TX Vref Scan disable
1627 12:26:36.854087 == TX Byte 0 ==
1628 12:26:36.857193 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1629 12:26:36.860426 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1630 12:26:36.863552 == TX Byte 1 ==
1631 12:26:36.867143 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1632 12:26:36.870315 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1633 12:26:36.870426 ==
1634 12:26:36.873464 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 12:26:36.880274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 12:26:36.880361 ==
1637 12:26:36.892268 TX Vref=22, minBit 1, minWin=26, winSum=438
1638 12:26:36.895656 TX Vref=24, minBit 1, minWin=26, winSum=439
1639 12:26:36.898818 TX Vref=26, minBit 4, minWin=27, winSum=447
1640 12:26:36.902507 TX Vref=28, minBit 4, minWin=27, winSum=446
1641 12:26:36.905524 TX Vref=30, minBit 4, minWin=27, winSum=448
1642 12:26:36.912359 TX Vref=32, minBit 6, minWin=27, winSum=447
1643 12:26:36.915558 [TxChooseVref] Worse bit 4, Min win 27, Win sum 448, Final Vref 30
1644 12:26:36.915647
1645 12:26:36.918653 Final TX Range 1 Vref 30
1646 12:26:36.918758
1647 12:26:36.918866 ==
1648 12:26:36.922429 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 12:26:36.925317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 12:26:36.925409 ==
1651 12:26:36.929097
1652 12:26:36.929177
1653 12:26:36.929243 TX Vref Scan disable
1654 12:26:36.932133 == TX Byte 0 ==
1655 12:26:36.935838 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1656 12:26:36.938972 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1657 12:26:36.942076 == TX Byte 1 ==
1658 12:26:36.945789 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1659 12:26:36.952087 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1660 12:26:36.952171
1661 12:26:36.952249 [DATLAT]
1662 12:26:36.952314 Freq=800, CH1 RK0
1663 12:26:36.952374
1664 12:26:36.955250 DATLAT Default: 0xa
1665 12:26:36.955336 0, 0xFFFF, sum = 0
1666 12:26:36.959029 1, 0xFFFF, sum = 0
1667 12:26:36.959106 2, 0xFFFF, sum = 0
1668 12:26:36.962092 3, 0xFFFF, sum = 0
1669 12:26:36.965289 4, 0xFFFF, sum = 0
1670 12:26:36.965392 5, 0xFFFF, sum = 0
1671 12:26:36.968468 6, 0xFFFF, sum = 0
1672 12:26:36.968554 7, 0xFFFF, sum = 0
1673 12:26:36.971962 8, 0xFFFF, sum = 0
1674 12:26:36.972051 9, 0x0, sum = 1
1675 12:26:36.975236 10, 0x0, sum = 2
1676 12:26:36.975326 11, 0x0, sum = 3
1677 12:26:36.975395 12, 0x0, sum = 4
1678 12:26:36.978322 best_step = 10
1679 12:26:36.978404
1680 12:26:36.978471 ==
1681 12:26:36.982066 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 12:26:36.985127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 12:26:36.985216 ==
1684 12:26:36.988327 RX Vref Scan: 1
1685 12:26:36.988412
1686 12:26:36.991940 Set Vref Range= 32 -> 127
1687 12:26:36.992025
1688 12:26:36.992092 RX Vref 32 -> 127, step: 1
1689 12:26:36.992154
1690 12:26:36.994900 RX Delay -111 -> 252, step: 8
1691 12:26:36.994987
1692 12:26:36.998512 Set Vref, RX VrefLevel [Byte0]: 32
1693 12:26:37.001554 [Byte1]: 32
1694 12:26:37.005320
1695 12:26:37.005405 Set Vref, RX VrefLevel [Byte0]: 33
1696 12:26:37.008327 [Byte1]: 33
1697 12:26:37.012555
1698 12:26:37.012640 Set Vref, RX VrefLevel [Byte0]: 34
1699 12:26:37.016009 [Byte1]: 34
1700 12:26:37.020380
1701 12:26:37.020468 Set Vref, RX VrefLevel [Byte0]: 35
1702 12:26:37.023612 [Byte1]: 35
1703 12:26:37.028072
1704 12:26:37.028159 Set Vref, RX VrefLevel [Byte0]: 36
1705 12:26:37.031095 [Byte1]: 36
1706 12:26:37.035683
1707 12:26:37.035804 Set Vref, RX VrefLevel [Byte0]: 37
1708 12:26:37.038653 [Byte1]: 37
1709 12:26:37.042970
1710 12:26:37.043087 Set Vref, RX VrefLevel [Byte0]: 38
1711 12:26:37.046725 [Byte1]: 38
1712 12:26:37.050627
1713 12:26:37.050744 Set Vref, RX VrefLevel [Byte0]: 39
1714 12:26:37.054327 [Byte1]: 39
1715 12:26:37.058721
1716 12:26:37.058842 Set Vref, RX VrefLevel [Byte0]: 40
1717 12:26:37.061994 [Byte1]: 40
1718 12:26:37.066267
1719 12:26:37.066352 Set Vref, RX VrefLevel [Byte0]: 41
1720 12:26:37.069287 [Byte1]: 41
1721 12:26:37.073682
1722 12:26:37.073803 Set Vref, RX VrefLevel [Byte0]: 42
1723 12:26:37.077307 [Byte1]: 42
1724 12:26:37.081764
1725 12:26:37.081850 Set Vref, RX VrefLevel [Byte0]: 43
1726 12:26:37.084942 [Byte1]: 43
1727 12:26:37.089312
1728 12:26:37.089397 Set Vref, RX VrefLevel [Byte0]: 44
1729 12:26:37.092540 [Byte1]: 44
1730 12:26:37.096786
1731 12:26:37.096871 Set Vref, RX VrefLevel [Byte0]: 45
1732 12:26:37.100353 [Byte1]: 45
1733 12:26:37.104430
1734 12:26:37.104519 Set Vref, RX VrefLevel [Byte0]: 46
1735 12:26:37.107982 [Byte1]: 46
1736 12:26:37.112231
1737 12:26:37.112357 Set Vref, RX VrefLevel [Byte0]: 47
1738 12:26:37.115286 [Byte1]: 47
1739 12:26:37.119609
1740 12:26:37.119705 Set Vref, RX VrefLevel [Byte0]: 48
1741 12:26:37.123037 [Byte1]: 48
1742 12:26:37.127327
1743 12:26:37.127415 Set Vref, RX VrefLevel [Byte0]: 49
1744 12:26:37.130517 [Byte1]: 49
1745 12:26:37.134942
1746 12:26:37.135027 Set Vref, RX VrefLevel [Byte0]: 50
1747 12:26:37.138502 [Byte1]: 50
1748 12:26:37.142725
1749 12:26:37.142854 Set Vref, RX VrefLevel [Byte0]: 51
1750 12:26:37.145720 [Byte1]: 51
1751 12:26:37.150071
1752 12:26:37.150158 Set Vref, RX VrefLevel [Byte0]: 52
1753 12:26:37.153819 [Byte1]: 52
1754 12:26:37.158296
1755 12:26:37.158381 Set Vref, RX VrefLevel [Byte0]: 53
1756 12:26:37.161415 [Byte1]: 53
1757 12:26:37.165245
1758 12:26:37.165358 Set Vref, RX VrefLevel [Byte0]: 54
1759 12:26:37.169228 [Byte1]: 54
1760 12:26:37.173499
1761 12:26:37.173589 Set Vref, RX VrefLevel [Byte0]: 55
1762 12:26:37.176392 [Byte1]: 55
1763 12:26:37.180670
1764 12:26:37.180755 Set Vref, RX VrefLevel [Byte0]: 56
1765 12:26:37.184461 [Byte1]: 56
1766 12:26:37.188833
1767 12:26:37.188917 Set Vref, RX VrefLevel [Byte0]: 57
1768 12:26:37.191998 [Byte1]: 57
1769 12:26:37.196462
1770 12:26:37.196549 Set Vref, RX VrefLevel [Byte0]: 58
1771 12:26:37.199512 [Byte1]: 58
1772 12:26:37.204036
1773 12:26:37.204122 Set Vref, RX VrefLevel [Byte0]: 59
1774 12:26:37.207466 [Byte1]: 59
1775 12:26:37.211670
1776 12:26:37.211758 Set Vref, RX VrefLevel [Byte0]: 60
1777 12:26:37.214607 [Byte1]: 60
1778 12:26:37.219385
1779 12:26:37.219486 Set Vref, RX VrefLevel [Byte0]: 61
1780 12:26:37.222353 [Byte1]: 61
1781 12:26:37.226597
1782 12:26:37.226684 Set Vref, RX VrefLevel [Byte0]: 62
1783 12:26:37.230057 [Byte1]: 62
1784 12:26:37.234505
1785 12:26:37.234589 Set Vref, RX VrefLevel [Byte0]: 63
1786 12:26:37.237529 [Byte1]: 63
1787 12:26:37.241902
1788 12:26:37.241987 Set Vref, RX VrefLevel [Byte0]: 64
1789 12:26:37.245069 [Byte1]: 64
1790 12:26:37.249483
1791 12:26:37.249567 Set Vref, RX VrefLevel [Byte0]: 65
1792 12:26:37.253134 [Byte1]: 65
1793 12:26:37.257319
1794 12:26:37.257403 Set Vref, RX VrefLevel [Byte0]: 66
1795 12:26:37.260841 [Byte1]: 66
1796 12:26:37.265235
1797 12:26:37.265319 Set Vref, RX VrefLevel [Byte0]: 67
1798 12:26:37.268357 [Byte1]: 67
1799 12:26:37.272701
1800 12:26:37.272786 Set Vref, RX VrefLevel [Byte0]: 68
1801 12:26:37.275922 [Byte1]: 68
1802 12:26:37.280332
1803 12:26:37.280416 Set Vref, RX VrefLevel [Byte0]: 69
1804 12:26:37.283319 [Byte1]: 69
1805 12:26:37.287784
1806 12:26:37.287869 Set Vref, RX VrefLevel [Byte0]: 70
1807 12:26:37.291465 [Byte1]: 70
1808 12:26:37.295943
1809 12:26:37.296028 Set Vref, RX VrefLevel [Byte0]: 71
1810 12:26:37.299037 [Byte1]: 71
1811 12:26:37.303445
1812 12:26:37.303530 Set Vref, RX VrefLevel [Byte0]: 72
1813 12:26:37.306538 [Byte1]: 72
1814 12:26:37.310768
1815 12:26:37.310878 Set Vref, RX VrefLevel [Byte0]: 73
1816 12:26:37.314335 [Byte1]: 73
1817 12:26:37.318318
1818 12:26:37.318430 Set Vref, RX VrefLevel [Byte0]: 74
1819 12:26:37.321831 [Byte1]: 74
1820 12:26:37.326120
1821 12:26:37.326205 Set Vref, RX VrefLevel [Byte0]: 75
1822 12:26:37.329634 [Byte1]: 75
1823 12:26:37.333781
1824 12:26:37.333893 Set Vref, RX VrefLevel [Byte0]: 76
1825 12:26:37.337315 [Byte1]: 76
1826 12:26:37.341435
1827 12:26:37.341518 Set Vref, RX VrefLevel [Byte0]: 77
1828 12:26:37.344606 [Byte1]: 77
1829 12:26:37.349343
1830 12:26:37.349452 Final RX Vref Byte 0 = 59 to rank0
1831 12:26:37.352521 Final RX Vref Byte 1 = 56 to rank0
1832 12:26:37.355704 Final RX Vref Byte 0 = 59 to rank1
1833 12:26:37.359391 Final RX Vref Byte 1 = 56 to rank1==
1834 12:26:37.362463 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 12:26:37.369229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 12:26:37.369317 ==
1837 12:26:37.369385 DQS Delay:
1838 12:26:37.369446 DQS0 = 0, DQS1 = 0
1839 12:26:37.372802 DQM Delay:
1840 12:26:37.372911 DQM0 = 81, DQM1 = 71
1841 12:26:37.375918 DQ Delay:
1842 12:26:37.378987 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1843 12:26:37.379072 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1844 12:26:37.382135 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1845 12:26:37.388880 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1846 12:26:37.388989
1847 12:26:37.389082
1848 12:26:37.395831 [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1849 12:26:37.398998 CH1 RK0: MR19=606, MR18=101A
1850 12:26:37.405328 CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60
1851 12:26:37.405412
1852 12:26:37.408643 ----->DramcWriteLeveling(PI) begin...
1853 12:26:37.408753 ==
1854 12:26:37.412348 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 12:26:37.415452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 12:26:37.415536 ==
1857 12:26:37.418481 Write leveling (Byte 0): 28 => 28
1858 12:26:37.422276 Write leveling (Byte 1): 29 => 29
1859 12:26:37.425616 DramcWriteLeveling(PI) end<-----
1860 12:26:37.425734
1861 12:26:37.425828 ==
1862 12:26:37.428829 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 12:26:37.432080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 12:26:37.432167 ==
1865 12:26:37.435583 [Gating] SW mode calibration
1866 12:26:37.442171 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 12:26:37.448565 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 12:26:37.452147 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 12:26:37.455300 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1870 12:26:37.461556 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1871 12:26:37.465223 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:26:37.468393 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:26:37.475224 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:26:37.478218 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:26:37.481973 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:26:37.488249 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:26:37.491910 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:26:37.495167 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:26:37.501746 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:26:37.504757 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:26:37.508602 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:26:37.515102 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:26:37.518308 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:26:37.521402 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:26:37.528130 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1886 12:26:37.531212 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1887 12:26:37.534516 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:26:37.541334 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:26:37.544967 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:26:37.548011 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:26:37.554441 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:26:37.557832 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:26:37.561292 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1894 12:26:37.568232 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1895 12:26:37.571319 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 12:26:37.574273 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 12:26:37.580971 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 12:26:37.584541 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 12:26:37.587748 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 12:26:37.594497 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1901 12:26:37.597723 0 10 4 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
1902 12:26:37.600925 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1903 12:26:37.607744 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:26:37.610832 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:26:37.613985 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:26:37.620795 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:26:37.624008 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:26:37.627584 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1909 12:26:37.634367 0 11 4 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
1910 12:26:37.637645 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1911 12:26:37.640684 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 12:26:37.647369 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 12:26:37.650653 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 12:26:37.653634 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 12:26:37.660315 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 12:26:37.663904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 12:26:37.666928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1918 12:26:37.673490 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1919 12:26:37.677225 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:26:37.680267 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:26:37.687160 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:26:37.690422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:26:37.693519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:26:37.696648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:26:37.703311 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:26:37.707019 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:26:37.710203 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:26:37.716529 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:26:37.720291 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:26:37.723522 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:26:37.729838 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:26:37.733401 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:26:37.736384 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1934 12:26:37.743339 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 12:26:37.746390 Total UI for P1: 0, mck2ui 16
1936 12:26:37.750049 best dqsien dly found for B0: ( 0, 14, 4)
1937 12:26:37.750133 Total UI for P1: 0, mck2ui 16
1938 12:26:37.756784 best dqsien dly found for B1: ( 0, 14, 4)
1939 12:26:37.759754 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 12:26:37.763130 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1941 12:26:37.763214
1942 12:26:37.766551 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 12:26:37.770072 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 12:26:37.773024 [Gating] SW calibration Done
1945 12:26:37.773136 ==
1946 12:26:37.776492 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 12:26:37.779911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 12:26:37.779988 ==
1949 12:26:37.783017 RX Vref Scan: 0
1950 12:26:37.783091
1951 12:26:37.783161 RX Vref 0 -> 0, step: 1
1952 12:26:37.783222
1953 12:26:37.786072 RX Delay -130 -> 252, step: 16
1954 12:26:37.792871 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1955 12:26:37.796601 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1956 12:26:37.799736 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1957 12:26:37.802771 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1958 12:26:37.806472 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1959 12:26:37.809638 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1960 12:26:37.815998 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1961 12:26:37.819788 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1962 12:26:37.822908 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1963 12:26:37.826090 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1964 12:26:37.829171 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1965 12:26:37.836105 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1966 12:26:37.839689 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1967 12:26:37.842786 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1968 12:26:37.845814 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1969 12:26:37.852352 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1970 12:26:37.852427 ==
1971 12:26:37.856177 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 12:26:37.859411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 12:26:37.859494 ==
1974 12:26:37.859559 DQS Delay:
1975 12:26:37.862737 DQS0 = 0, DQS1 = 0
1976 12:26:37.862810 DQM Delay:
1977 12:26:37.866146 DQM0 = 78, DQM1 = 71
1978 12:26:37.866242 DQ Delay:
1979 12:26:37.868973 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1980 12:26:37.872520 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1981 12:26:37.876019 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1982 12:26:37.878877 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1983 12:26:37.878950
1984 12:26:37.879038
1985 12:26:37.879097 ==
1986 12:26:37.882341 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 12:26:37.885809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 12:26:37.885882 ==
1989 12:26:37.888857
1990 12:26:37.888953
1991 12:26:37.889049 TX Vref Scan disable
1992 12:26:37.892572 == TX Byte 0 ==
1993 12:26:37.895757 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 12:26:37.898884 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 12:26:37.902052 == TX Byte 1 ==
1996 12:26:37.905759 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 12:26:37.908787 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 12:26:37.908872 ==
1999 12:26:37.912297 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 12:26:37.918680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 12:26:37.918780 ==
2002 12:26:37.930722 TX Vref=22, minBit 0, minWin=27, winSum=448
2003 12:26:37.933874 TX Vref=24, minBit 5, minWin=27, winSum=450
2004 12:26:37.937115 TX Vref=26, minBit 1, minWin=27, winSum=454
2005 12:26:37.940738 TX Vref=28, minBit 5, minWin=27, winSum=458
2006 12:26:37.944130 TX Vref=30, minBit 0, minWin=28, winSum=459
2007 12:26:37.950727 TX Vref=32, minBit 1, minWin=27, winSum=458
2008 12:26:37.953661 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
2009 12:26:37.953735
2010 12:26:37.957353 Final TX Range 1 Vref 30
2011 12:26:37.957423
2012 12:26:37.957491 ==
2013 12:26:37.960546 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 12:26:37.963735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 12:26:37.966919 ==
2016 12:26:37.966997
2017 12:26:37.967059
2018 12:26:37.967118 TX Vref Scan disable
2019 12:26:37.970574 == TX Byte 0 ==
2020 12:26:37.974186 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2021 12:26:37.980882 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2022 12:26:37.980988 == TX Byte 1 ==
2023 12:26:37.984086 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 12:26:37.990586 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 12:26:37.990689
2026 12:26:37.990787 [DATLAT]
2027 12:26:37.990918 Freq=800, CH1 RK1
2028 12:26:37.991014
2029 12:26:37.993559 DATLAT Default: 0xa
2030 12:26:37.993671 0, 0xFFFF, sum = 0
2031 12:26:37.997148 1, 0xFFFF, sum = 0
2032 12:26:37.997229 2, 0xFFFF, sum = 0
2033 12:26:38.000680 3, 0xFFFF, sum = 0
2034 12:26:38.003933 4, 0xFFFF, sum = 0
2035 12:26:38.004018 5, 0xFFFF, sum = 0
2036 12:26:38.007082 6, 0xFFFF, sum = 0
2037 12:26:38.007192 7, 0xFFFF, sum = 0
2038 12:26:38.010146 8, 0xFFFF, sum = 0
2039 12:26:38.010245 9, 0x0, sum = 1
2040 12:26:38.013760 10, 0x0, sum = 2
2041 12:26:38.013871 11, 0x0, sum = 3
2042 12:26:38.013961 12, 0x0, sum = 4
2043 12:26:38.016881 best_step = 10
2044 12:26:38.016989
2045 12:26:38.017081 ==
2046 12:26:38.020382 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 12:26:38.023440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 12:26:38.023541 ==
2049 12:26:38.027241 RX Vref Scan: 0
2050 12:26:38.027337
2051 12:26:38.027425 RX Vref 0 -> 0, step: 1
2052 12:26:38.030572
2053 12:26:38.030665 RX Delay -111 -> 252, step: 8
2054 12:26:38.037755 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2055 12:26:38.040789 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2056 12:26:38.043874 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2057 12:26:38.047497 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2058 12:26:38.050672 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2059 12:26:38.057791 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2060 12:26:38.060895 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2061 12:26:38.064049 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2062 12:26:38.067652 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2063 12:26:38.070799 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2064 12:26:38.077812 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2065 12:26:38.080876 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2066 12:26:38.083945 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2067 12:26:38.087376 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2068 12:26:38.093628 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2069 12:26:38.097348 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2070 12:26:38.097852 ==
2071 12:26:38.100339 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 12:26:38.103815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 12:26:38.104304 ==
2074 12:26:38.106792 DQS Delay:
2075 12:26:38.107314 DQS0 = 0, DQS1 = 0
2076 12:26:38.107765 DQM Delay:
2077 12:26:38.110388 DQM0 = 77, DQM1 = 75
2078 12:26:38.110896 DQ Delay:
2079 12:26:38.113523 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2080 12:26:38.117297 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2081 12:26:38.120608 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2082 12:26:38.123712 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2083 12:26:38.124266
2084 12:26:38.124762
2085 12:26:38.133665 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2086 12:26:38.136610 CH1 RK1: MR19=606, MR18=1C35
2087 12:26:38.140309 CH1_RK1: MR19=0x606, MR18=0x1C35, DQSOSC=396, MR23=63, INC=94, DEC=62
2088 12:26:38.143482 [RxdqsGatingPostProcess] freq 800
2089 12:26:38.150446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 12:26:38.153604 Pre-setting of DQS Precalculation
2091 12:26:38.156782 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 12:26:38.163769 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 12:26:38.173712 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 12:26:38.174261
2095 12:26:38.174742
2096 12:26:38.176888 [Calibration Summary] 1600 Mbps
2097 12:26:38.177399 CH 0, Rank 0
2098 12:26:38.180019 SW Impedance : PASS
2099 12:26:38.180517 DUTY Scan : NO K
2100 12:26:38.183710 ZQ Calibration : PASS
2101 12:26:38.186808 Jitter Meter : NO K
2102 12:26:38.187347 CBT Training : PASS
2103 12:26:38.190043 Write leveling : PASS
2104 12:26:38.193585 RX DQS gating : PASS
2105 12:26:38.194074 RX DQ/DQS(RDDQC) : PASS
2106 12:26:38.196349 TX DQ/DQS : PASS
2107 12:26:38.196866 RX DATLAT : PASS
2108 12:26:38.199912 RX DQ/DQS(Engine): PASS
2109 12:26:38.203421 TX OE : NO K
2110 12:26:38.203913 All Pass.
2111 12:26:38.204363
2112 12:26:38.204805 CH 0, Rank 1
2113 12:26:38.206864 SW Impedance : PASS
2114 12:26:38.210277 DUTY Scan : NO K
2115 12:26:38.210882 ZQ Calibration : PASS
2116 12:26:38.213282 Jitter Meter : NO K
2117 12:26:38.216977 CBT Training : PASS
2118 12:26:38.217535 Write leveling : PASS
2119 12:26:38.219878 RX DQS gating : PASS
2120 12:26:38.223071 RX DQ/DQS(RDDQC) : PASS
2121 12:26:38.223576 TX DQ/DQS : PASS
2122 12:26:38.226153 RX DATLAT : PASS
2123 12:26:38.229721 RX DQ/DQS(Engine): PASS
2124 12:26:38.230217 TX OE : NO K
2125 12:26:38.233438 All Pass.
2126 12:26:38.233936
2127 12:26:38.234394 CH 1, Rank 0
2128 12:26:38.236402 SW Impedance : PASS
2129 12:26:38.237009 DUTY Scan : NO K
2130 12:26:38.239667 ZQ Calibration : PASS
2131 12:26:38.242858 Jitter Meter : NO K
2132 12:26:38.243360 CBT Training : PASS
2133 12:26:38.246685 Write leveling : PASS
2134 12:26:38.249851 RX DQS gating : PASS
2135 12:26:38.250411 RX DQ/DQS(RDDQC) : PASS
2136 12:26:38.253198 TX DQ/DQS : PASS
2137 12:26:38.253626 RX DATLAT : PASS
2138 12:26:38.256586 RX DQ/DQS(Engine): PASS
2139 12:26:38.259533 TX OE : NO K
2140 12:26:38.260251 All Pass.
2141 12:26:38.260918
2142 12:26:38.261553 CH 1, Rank 1
2143 12:26:38.263416 SW Impedance : PASS
2144 12:26:38.266492 DUTY Scan : NO K
2145 12:26:38.267406 ZQ Calibration : PASS
2146 12:26:38.269477 Jitter Meter : NO K
2147 12:26:38.272415 CBT Training : PASS
2148 12:26:38.272796 Write leveling : PASS
2149 12:26:38.276300 RX DQS gating : PASS
2150 12:26:38.279237 RX DQ/DQS(RDDQC) : PASS
2151 12:26:38.279537 TX DQ/DQS : PASS
2152 12:26:38.282318 RX DATLAT : PASS
2153 12:26:38.285582 RX DQ/DQS(Engine): PASS
2154 12:26:38.285810 TX OE : NO K
2155 12:26:38.289212 All Pass.
2156 12:26:38.289403
2157 12:26:38.289578 DramC Write-DBI off
2158 12:26:38.292357 PER_BANK_REFRESH: Hybrid Mode
2159 12:26:38.292512 TX_TRACKING: ON
2160 12:26:38.299543 [GetDramInforAfterCalByMRR] Vendor 6.
2161 12:26:38.302221 [GetDramInforAfterCalByMRR] Revision 606.
2162 12:26:38.305352 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 12:26:38.305458 MR0 0x3b3b
2164 12:26:38.305546 MR8 0x5151
2165 12:26:38.308901 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 12:26:38.312342
2167 12:26:38.312456 MR0 0x3b3b
2168 12:26:38.312557 MR8 0x5151
2169 12:26:38.315268 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 12:26:38.315357
2171 12:26:38.325244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 12:26:38.328874 [FAST_K] Save calibration result to emmc
2173 12:26:38.331856 [FAST_K] Save calibration result to emmc
2174 12:26:38.335661 dram_init: config_dvfs: 1
2175 12:26:38.338444 dramc_set_vcore_voltage set vcore to 662500
2176 12:26:38.342378 Read voltage for 1200, 2
2177 12:26:38.342491 Vio18 = 0
2178 12:26:38.342584 Vcore = 662500
2179 12:26:38.345483 Vdram = 0
2180 12:26:38.345587 Vddq = 0
2181 12:26:38.345689 Vmddr = 0
2182 12:26:38.352053 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 12:26:38.355330 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 12:26:38.358525 MEM_TYPE=3, freq_sel=15
2185 12:26:38.361641 sv_algorithm_assistance_LP4_1600
2186 12:26:38.365269 ============ PULL DRAM RESETB DOWN ============
2187 12:26:38.368362 ========== PULL DRAM RESETB DOWN end =========
2188 12:26:38.375043 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 12:26:38.378142 ===================================
2190 12:26:38.381940 LPDDR4 DRAM CONFIGURATION
2191 12:26:38.385088 ===================================
2192 12:26:38.385173 EX_ROW_EN[0] = 0x0
2193 12:26:38.388286 EX_ROW_EN[1] = 0x0
2194 12:26:38.388373 LP4Y_EN = 0x0
2195 12:26:38.391424 WORK_FSP = 0x0
2196 12:26:38.391560 WL = 0x4
2197 12:26:38.395373 RL = 0x4
2198 12:26:38.395458 BL = 0x2
2199 12:26:38.398586 RPST = 0x0
2200 12:26:38.398691 RD_PRE = 0x0
2201 12:26:38.401694 WR_PRE = 0x1
2202 12:26:38.401804 WR_PST = 0x0
2203 12:26:38.404920 DBI_WR = 0x0
2204 12:26:38.405033 DBI_RD = 0x0
2205 12:26:38.408131 OTF = 0x1
2206 12:26:38.411623 ===================================
2207 12:26:38.414563 ===================================
2208 12:26:38.414670 ANA top config
2209 12:26:38.418112 ===================================
2210 12:26:38.421545 DLL_ASYNC_EN = 0
2211 12:26:38.424972 ALL_SLAVE_EN = 0
2212 12:26:38.428025 NEW_RANK_MODE = 1
2213 12:26:38.431578 DLL_IDLE_MODE = 1
2214 12:26:38.431663 LP45_APHY_COMB_EN = 1
2215 12:26:38.434602 TX_ODT_DIS = 1
2216 12:26:38.438263 NEW_8X_MODE = 1
2217 12:26:38.441316 ===================================
2218 12:26:38.444443 ===================================
2219 12:26:38.448062 data_rate = 2400
2220 12:26:38.451162 CKR = 1
2221 12:26:38.451249 DQ_P2S_RATIO = 8
2222 12:26:38.454793 ===================================
2223 12:26:38.458004 CA_P2S_RATIO = 8
2224 12:26:38.461065 DQ_CA_OPEN = 0
2225 12:26:38.464248 DQ_SEMI_OPEN = 0
2226 12:26:38.467940 CA_SEMI_OPEN = 0
2227 12:26:38.471046 CA_FULL_RATE = 0
2228 12:26:38.471167 DQ_CKDIV4_EN = 0
2229 12:26:38.474458 CA_CKDIV4_EN = 0
2230 12:26:38.477465 CA_PREDIV_EN = 0
2231 12:26:38.481198 PH8_DLY = 17
2232 12:26:38.484272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 12:26:38.487387 DQ_AAMCK_DIV = 4
2234 12:26:38.487475 CA_AAMCK_DIV = 4
2235 12:26:38.490593 CA_ADMCK_DIV = 4
2236 12:26:38.494186 DQ_TRACK_CA_EN = 0
2237 12:26:38.497215 CA_PICK = 1200
2238 12:26:38.500978 CA_MCKIO = 1200
2239 12:26:38.504131 MCKIO_SEMI = 0
2240 12:26:38.507360 PLL_FREQ = 2366
2241 12:26:38.510491 DQ_UI_PI_RATIO = 32
2242 12:26:38.510571 CA_UI_PI_RATIO = 0
2243 12:26:38.514266 ===================================
2244 12:26:38.517826 ===================================
2245 12:26:38.520960 memory_type:LPDDR4
2246 12:26:38.524077 GP_NUM : 10
2247 12:26:38.524194 SRAM_EN : 1
2248 12:26:38.527635 MD32_EN : 0
2249 12:26:38.530371 ===================================
2250 12:26:38.534060 [ANA_INIT] >>>>>>>>>>>>>>
2251 12:26:38.534170 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 12:26:38.540772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 12:26:38.543832 ===================================
2254 12:26:38.543978 data_rate = 2400,PCW = 0X5b00
2255 12:26:38.547567 ===================================
2256 12:26:38.550481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 12:26:38.557127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 12:26:38.563989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 12:26:38.567196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 12:26:38.570081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 12:26:38.573862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 12:26:38.577027 [ANA_INIT] flow start
2263 12:26:38.577156 [ANA_INIT] PLL >>>>>>>>
2264 12:26:38.580147 [ANA_INIT] PLL <<<<<<<<
2265 12:26:38.583624 [ANA_INIT] MIDPI >>>>>>>>
2266 12:26:38.586723 [ANA_INIT] MIDPI <<<<<<<<
2267 12:26:38.586845 [ANA_INIT] DLL >>>>>>>>
2268 12:26:38.590608 [ANA_INIT] DLL <<<<<<<<
2269 12:26:38.593841 [ANA_INIT] flow end
2270 12:26:38.597082 ============ LP4 DIFF to SE enter ============
2271 12:26:38.600192 ============ LP4 DIFF to SE exit ============
2272 12:26:38.603387 [ANA_INIT] <<<<<<<<<<<<<
2273 12:26:38.607146 [Flow] Enable top DCM control >>>>>
2274 12:26:38.610327 [Flow] Enable top DCM control <<<<<
2275 12:26:38.613546 Enable DLL master slave shuffle
2276 12:26:38.616766 ==============================================================
2277 12:26:38.619990 Gating Mode config
2278 12:26:38.623409 ==============================================================
2279 12:26:38.626912 Config description:
2280 12:26:38.636828 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 12:26:38.643294 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 12:26:38.646282 SELPH_MODE 0: By rank 1: By Phase
2283 12:26:38.653017 ==============================================================
2284 12:26:38.656135 GAT_TRACK_EN = 1
2285 12:26:38.659867 RX_GATING_MODE = 2
2286 12:26:38.662707 RX_GATING_TRACK_MODE = 2
2287 12:26:38.666372 SELPH_MODE = 1
2288 12:26:38.669607 PICG_EARLY_EN = 1
2289 12:26:38.673058 VALID_LAT_VALUE = 1
2290 12:26:38.676355 ==============================================================
2291 12:26:38.679696 Enter into Gating configuration >>>>
2292 12:26:38.682803 Exit from Gating configuration <<<<
2293 12:26:38.686375 Enter into DVFS_PRE_config >>>>>
2294 12:26:38.699624 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 12:26:38.699749 Exit from DVFS_PRE_config <<<<<
2296 12:26:38.702692 Enter into PICG configuration >>>>
2297 12:26:38.705776 Exit from PICG configuration <<<<
2298 12:26:38.709586 [RX_INPUT] configuration >>>>>
2299 12:26:38.712763 [RX_INPUT] configuration <<<<<
2300 12:26:38.719191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 12:26:38.722335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 12:26:38.729245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 12:26:38.735917 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 12:26:38.742290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 12:26:38.749330 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 12:26:38.752238 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 12:26:38.755717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 12:26:38.758663 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 12:26:38.765901 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 12:26:38.769116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 12:26:38.772822 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 12:26:38.775708 ===================================
2313 12:26:38.778970 LPDDR4 DRAM CONFIGURATION
2314 12:26:38.782311 ===================================
2315 12:26:38.785139 EX_ROW_EN[0] = 0x0
2316 12:26:38.785235 EX_ROW_EN[1] = 0x0
2317 12:26:38.788844 LP4Y_EN = 0x0
2318 12:26:38.788937 WORK_FSP = 0x0
2319 12:26:38.791870 WL = 0x4
2320 12:26:38.791957 RL = 0x4
2321 12:26:38.795732 BL = 0x2
2322 12:26:38.795840 RPST = 0x0
2323 12:26:38.798835 RD_PRE = 0x0
2324 12:26:38.798917 WR_PRE = 0x1
2325 12:26:38.801944 WR_PST = 0x0
2326 12:26:38.802025 DBI_WR = 0x0
2327 12:26:38.805107 DBI_RD = 0x0
2328 12:26:38.805185 OTF = 0x1
2329 12:26:38.808674 ===================================
2330 12:26:38.815010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 12:26:38.818172 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 12:26:38.822031 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 12:26:38.825199 ===================================
2334 12:26:38.828202 LPDDR4 DRAM CONFIGURATION
2335 12:26:38.831530 ===================================
2336 12:26:38.835285 EX_ROW_EN[0] = 0x10
2337 12:26:38.835367 EX_ROW_EN[1] = 0x0
2338 12:26:38.838477 LP4Y_EN = 0x0
2339 12:26:38.838576 WORK_FSP = 0x0
2340 12:26:38.841554 WL = 0x4
2341 12:26:38.841641 RL = 0x4
2342 12:26:38.844897 BL = 0x2
2343 12:26:38.844988 RPST = 0x0
2344 12:26:38.847904 RD_PRE = 0x0
2345 12:26:38.847994 WR_PRE = 0x1
2346 12:26:38.851528 WR_PST = 0x0
2347 12:26:38.851653 DBI_WR = 0x0
2348 12:26:38.854725 DBI_RD = 0x0
2349 12:26:38.854854 OTF = 0x1
2350 12:26:38.857979 ===================================
2351 12:26:38.864568 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 12:26:38.864705 ==
2353 12:26:38.868244 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 12:26:38.874919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 12:26:38.875060 ==
2356 12:26:38.875136 [Duty_Offset_Calibration]
2357 12:26:38.877930 B0:2 B1:0 CA:3
2358 12:26:38.878026
2359 12:26:38.881062 [DutyScan_Calibration_Flow] k_type=0
2360 12:26:38.890040
2361 12:26:38.890184 ==CLK 0==
2362 12:26:38.893669 Final CLK duty delay cell = 0
2363 12:26:38.896618 [0] MAX Duty = 5062%(X100), DQS PI = 20
2364 12:26:38.899789 [0] MIN Duty = 4906%(X100), DQS PI = 54
2365 12:26:38.899898 [0] AVG Duty = 4984%(X100)
2366 12:26:38.903558
2367 12:26:38.906815 CH0 CLK Duty spec in!! Max-Min= 156%
2368 12:26:38.910002 [DutyScan_Calibration_Flow] ====Done====
2369 12:26:38.910138
2370 12:26:38.912992 [DutyScan_Calibration_Flow] k_type=1
2371 12:26:38.928897
2372 12:26:38.929059 ==DQS 0 ==
2373 12:26:38.932000 Final DQS duty delay cell = 0
2374 12:26:38.935205 [0] MAX Duty = 5062%(X100), DQS PI = 10
2375 12:26:38.938854 [0] MIN Duty = 4907%(X100), DQS PI = 44
2376 12:26:38.941894 [0] AVG Duty = 4984%(X100)
2377 12:26:38.942022
2378 12:26:38.942117 ==DQS 1 ==
2379 12:26:38.944959 Final DQS duty delay cell = -4
2380 12:26:38.948742 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2381 12:26:38.951820 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2382 12:26:38.954811 [-4] AVG Duty = 4938%(X100)
2383 12:26:38.954949
2384 12:26:38.958301 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2385 12:26:38.958410
2386 12:26:38.961787 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2387 12:26:38.965241 [DutyScan_Calibration_Flow] ====Done====
2388 12:26:38.965369
2389 12:26:38.968188 [DutyScan_Calibration_Flow] k_type=3
2390 12:26:38.985157
2391 12:26:38.985339 ==DQM 0 ==
2392 12:26:38.988762 Final DQM duty delay cell = 0
2393 12:26:38.991750 [0] MAX Duty = 5124%(X100), DQS PI = 28
2394 12:26:38.995378 [0] MIN Duty = 4876%(X100), DQS PI = 0
2395 12:26:38.995511 [0] AVG Duty = 5000%(X100)
2396 12:26:38.998292
2397 12:26:38.998416 ==DQM 1 ==
2398 12:26:39.001781 Final DQM duty delay cell = 0
2399 12:26:39.005564 [0] MAX Duty = 4969%(X100), DQS PI = 52
2400 12:26:39.008723 [0] MIN Duty = 4876%(X100), DQS PI = 8
2401 12:26:39.008873 [0] AVG Duty = 4922%(X100)
2402 12:26:39.011905
2403 12:26:39.014992 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2404 12:26:39.015123
2405 12:26:39.018605 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2406 12:26:39.021676 [DutyScan_Calibration_Flow] ====Done====
2407 12:26:39.021812
2408 12:26:39.024946 [DutyScan_Calibration_Flow] k_type=2
2409 12:26:39.040072
2410 12:26:39.040233 ==DQ 0 ==
2411 12:26:39.043204 Final DQ duty delay cell = -4
2412 12:26:39.046794 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2413 12:26:39.049927 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2414 12:26:39.053137 [-4] AVG Duty = 4969%(X100)
2415 12:26:39.053258
2416 12:26:39.053354 ==DQ 1 ==
2417 12:26:39.056765 Final DQ duty delay cell = -4
2418 12:26:39.059921 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2419 12:26:39.063632 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2420 12:26:39.066247 [-4] AVG Duty = 4938%(X100)
2421 12:26:39.066367
2422 12:26:39.069843 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2423 12:26:39.069955
2424 12:26:39.072762 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2425 12:26:39.076286 [DutyScan_Calibration_Flow] ====Done====
2426 12:26:39.076423 ==
2427 12:26:39.079975 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 12:26:39.083075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 12:26:39.083188 ==
2430 12:26:39.086085 [Duty_Offset_Calibration]
2431 12:26:39.089786 B0:1 B1:-2 CA:0
2432 12:26:39.089880
2433 12:26:39.092690 [DutyScan_Calibration_Flow] k_type=0
2434 12:26:39.100686
2435 12:26:39.100859 ==CLK 0==
2436 12:26:39.103786 Final CLK duty delay cell = 0
2437 12:26:39.107290 [0] MAX Duty = 5031%(X100), DQS PI = 18
2438 12:26:39.110949 [0] MIN Duty = 4875%(X100), DQS PI = 2
2439 12:26:39.111073 [0] AVG Duty = 4953%(X100)
2440 12:26:39.114214
2441 12:26:39.117365 CH1 CLK Duty spec in!! Max-Min= 156%
2442 12:26:39.120585 [DutyScan_Calibration_Flow] ====Done====
2443 12:26:39.120697
2444 12:26:39.123674 [DutyScan_Calibration_Flow] k_type=1
2445 12:26:39.139388
2446 12:26:39.139540 ==DQS 0 ==
2447 12:26:39.142554 Final DQS duty delay cell = -4
2448 12:26:39.145695 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2449 12:26:39.148841 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2450 12:26:39.152505 [-4] AVG Duty = 4969%(X100)
2451 12:26:39.152592
2452 12:26:39.152677 ==DQS 1 ==
2453 12:26:39.155583 Final DQS duty delay cell = 0
2454 12:26:39.158711 [0] MAX Duty = 5062%(X100), DQS PI = 0
2455 12:26:39.161962 [0] MIN Duty = 4875%(X100), DQS PI = 26
2456 12:26:39.165541 [0] AVG Duty = 4968%(X100)
2457 12:26:39.165665
2458 12:26:39.168514 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2459 12:26:39.168646
2460 12:26:39.172113 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2461 12:26:39.175064 [DutyScan_Calibration_Flow] ====Done====
2462 12:26:39.175187
2463 12:26:39.178511 [DutyScan_Calibration_Flow] k_type=3
2464 12:26:39.195681
2465 12:26:39.195846 ==DQM 0 ==
2466 12:26:39.199237 Final DQM duty delay cell = 0
2467 12:26:39.202375 [0] MAX Duty = 5031%(X100), DQS PI = 24
2468 12:26:39.206124 [0] MIN Duty = 4844%(X100), DQS PI = 54
2469 12:26:39.208949 [0] AVG Duty = 4937%(X100)
2470 12:26:39.209080
2471 12:26:39.209180 ==DQM 1 ==
2472 12:26:39.212503 Final DQM duty delay cell = 0
2473 12:26:39.215471 [0] MAX Duty = 5031%(X100), DQS PI = 36
2474 12:26:39.219282 [0] MIN Duty = 4907%(X100), DQS PI = 2
2475 12:26:39.222472 [0] AVG Duty = 4969%(X100)
2476 12:26:39.222609
2477 12:26:39.225479 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2478 12:26:39.225603
2479 12:26:39.228638 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 12:26:39.231840 [DutyScan_Calibration_Flow] ====Done====
2481 12:26:39.231927
2482 12:26:39.235584 [DutyScan_Calibration_Flow] k_type=2
2483 12:26:39.252114
2484 12:26:39.252294 ==DQ 0 ==
2485 12:26:39.255950 Final DQ duty delay cell = 0
2486 12:26:39.259147 [0] MAX Duty = 5062%(X100), DQS PI = 12
2487 12:26:39.262289 [0] MIN Duty = 4938%(X100), DQS PI = 54
2488 12:26:39.262377 [0] AVG Duty = 5000%(X100)
2489 12:26:39.265504
2490 12:26:39.265619 ==DQ 1 ==
2491 12:26:39.269169 Final DQ duty delay cell = 0
2492 12:26:39.272315 [0] MAX Duty = 5125%(X100), DQS PI = 36
2493 12:26:39.275225 [0] MIN Duty = 4969%(X100), DQS PI = 26
2494 12:26:39.275314 [0] AVG Duty = 5047%(X100)
2495 12:26:39.275384
2496 12:26:39.282263 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2497 12:26:39.282358
2498 12:26:39.285634 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2499 12:26:39.288510 [DutyScan_Calibration_Flow] ====Done====
2500 12:26:39.292264 nWR fixed to 30
2501 12:26:39.292353 [ModeRegInit_LP4] CH0 RK0
2502 12:26:39.295232 [ModeRegInit_LP4] CH0 RK1
2503 12:26:39.298921 [ModeRegInit_LP4] CH1 RK0
2504 12:26:39.301847 [ModeRegInit_LP4] CH1 RK1
2505 12:26:39.301936 match AC timing 7
2506 12:26:39.305586 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 12:26:39.311647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 12:26:39.315469 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 12:26:39.321801 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 12:26:39.324982 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 12:26:39.325074 ==
2512 12:26:39.328219 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 12:26:39.331907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:26:39.332027 ==
2515 12:26:39.338262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 12:26:39.344732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 12:26:39.352472 [CA 0] Center 40 (10~71) winsize 62
2518 12:26:39.355685 [CA 1] Center 39 (9~70) winsize 62
2519 12:26:39.358789 [CA 2] Center 36 (6~66) winsize 61
2520 12:26:39.362558 [CA 3] Center 35 (5~66) winsize 62
2521 12:26:39.366191 [CA 4] Center 34 (4~65) winsize 62
2522 12:26:39.368642 [CA 5] Center 33 (3~63) winsize 61
2523 12:26:39.368770
2524 12:26:39.372351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2525 12:26:39.372479
2526 12:26:39.375458 [CATrainingPosCal] consider 1 rank data
2527 12:26:39.378661 u2DelayCellTimex100 = 270/100 ps
2528 12:26:39.382473 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2529 12:26:39.388596 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 12:26:39.392139 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2531 12:26:39.395122 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 12:26:39.398702 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2533 12:26:39.402102 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2534 12:26:39.402190
2535 12:26:39.405538 CA PerBit enable=1, Macro0, CA PI delay=33
2536 12:26:39.405625
2537 12:26:39.408716 [CBTSetCACLKResult] CA Dly = 33
2538 12:26:39.412103 CS Dly: 7 (0~38)
2539 12:26:39.412191 ==
2540 12:26:39.415239 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 12:26:39.418728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 12:26:39.418844 ==
2543 12:26:39.425324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 12:26:39.428411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 12:26:39.438217 [CA 0] Center 40 (10~71) winsize 62
2546 12:26:39.441366 [CA 1] Center 40 (10~70) winsize 61
2547 12:26:39.445340 [CA 2] Center 35 (5~66) winsize 62
2548 12:26:39.448050 [CA 3] Center 35 (5~66) winsize 62
2549 12:26:39.452017 [CA 4] Center 34 (4~65) winsize 62
2550 12:26:39.455127 [CA 5] Center 33 (3~63) winsize 61
2551 12:26:39.455205
2552 12:26:39.458359 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2553 12:26:39.458436
2554 12:26:39.461540 [CATrainingPosCal] consider 2 rank data
2555 12:26:39.465247 u2DelayCellTimex100 = 270/100 ps
2556 12:26:39.468502 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2557 12:26:39.474730 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2558 12:26:39.478541 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2559 12:26:39.481777 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 12:26:39.484806 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2561 12:26:39.488497 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2562 12:26:39.488586
2563 12:26:39.491466 CA PerBit enable=1, Macro0, CA PI delay=33
2564 12:26:39.491554
2565 12:26:39.494936 [CBTSetCACLKResult] CA Dly = 33
2566 12:26:39.498391 CS Dly: 7 (0~39)
2567 12:26:39.498496
2568 12:26:39.501364 ----->DramcWriteLeveling(PI) begin...
2569 12:26:39.501461 ==
2570 12:26:39.504885 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 12:26:39.508215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 12:26:39.508310 ==
2573 12:26:39.511676 Write leveling (Byte 0): 31 => 31
2574 12:26:39.514611 Write leveling (Byte 1): 29 => 29
2575 12:26:39.517691 DramcWriteLeveling(PI) end<-----
2576 12:26:39.517782
2577 12:26:39.517851 ==
2578 12:26:39.521327 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 12:26:39.524244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 12:26:39.524359 ==
2581 12:26:39.528030 [Gating] SW mode calibration
2582 12:26:39.534138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 12:26:39.541317 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 12:26:39.544626 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 12:26:39.547678 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2586 12:26:39.553888 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 12:26:39.557754 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 12:26:39.560986 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 12:26:39.567350 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 12:26:39.571161 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 12:26:39.574200 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2592 12:26:39.581189 1 0 0 | B1->B0 | 3131 2626 | 0 1 | (0 0) (1 0)
2593 12:26:39.584247 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2594 12:26:39.587468 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 12:26:39.594261 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 12:26:39.597649 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 12:26:39.600672 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 12:26:39.607400 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 12:26:39.610417 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2600 12:26:39.614300 1 1 0 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
2601 12:26:39.620853 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2602 12:26:39.624180 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 12:26:39.627234 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 12:26:39.633885 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 12:26:39.637418 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 12:26:39.640705 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 12:26:39.646916 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 12:26:39.650628 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2609 12:26:39.653771 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:26:39.660574 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:26:39.663639 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:26:39.666778 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:26:39.673691 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:26:39.676831 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:26:39.680126 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:26:39.687049 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:26:39.690190 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:26:39.693381 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:26:39.700461 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:26:39.703355 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:26:39.706645 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:26:39.713203 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:26:39.716318 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:26:39.720135 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 12:26:39.723218 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 12:26:39.726369 Total UI for P1: 0, mck2ui 16
2627 12:26:39.729981 best dqsien dly found for B0: ( 1, 4, 0)
2628 12:26:39.736868 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 12:26:39.740207 Total UI for P1: 0, mck2ui 16
2630 12:26:39.743390 best dqsien dly found for B1: ( 1, 4, 2)
2631 12:26:39.746589 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2632 12:26:39.749646 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2633 12:26:39.749755
2634 12:26:39.753373 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 12:26:39.756512 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2636 12:26:39.759521 [Gating] SW calibration Done
2637 12:26:39.759664 ==
2638 12:26:39.762719 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 12:26:39.766476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 12:26:39.766590 ==
2641 12:26:39.769695 RX Vref Scan: 0
2642 12:26:39.769825
2643 12:26:39.769941 RX Vref 0 -> 0, step: 1
2644 12:26:39.770010
2645 12:26:39.772805 RX Delay -40 -> 252, step: 8
2646 12:26:39.779922 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2647 12:26:39.782634 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2648 12:26:39.786508 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2649 12:26:39.789613 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2650 12:26:39.792941 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2651 12:26:39.796171 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2652 12:26:39.802580 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2653 12:26:39.806121 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2654 12:26:39.809205 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2655 12:26:39.812734 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
2656 12:26:39.816223 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2657 12:26:39.822630 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2658 12:26:39.826205 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2659 12:26:39.829295 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2660 12:26:39.832974 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2661 12:26:39.836080 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2662 12:26:39.838975 ==
2663 12:26:39.842585 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 12:26:39.845607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 12:26:39.845700 ==
2666 12:26:39.845769 DQS Delay:
2667 12:26:39.849313 DQS0 = 0, DQS1 = 0
2668 12:26:39.849456 DQM Delay:
2669 12:26:39.852601 DQM0 = 112, DQM1 = 103
2670 12:26:39.852714 DQ Delay:
2671 12:26:39.855756 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2672 12:26:39.858898 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2673 12:26:39.862665 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
2674 12:26:39.865787 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2675 12:26:39.865914
2676 12:26:39.866014
2677 12:26:39.866110 ==
2678 12:26:39.868967 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 12:26:39.876084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 12:26:39.876218 ==
2681 12:26:39.876287
2682 12:26:39.876349
2683 12:26:39.876410 TX Vref Scan disable
2684 12:26:39.879293 == TX Byte 0 ==
2685 12:26:39.882515 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2686 12:26:39.888843 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2687 12:26:39.889000 == TX Byte 1 ==
2688 12:26:39.892656 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2689 12:26:39.899037 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2690 12:26:39.899194 ==
2691 12:26:39.902277 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 12:26:39.905422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 12:26:39.905524 ==
2694 12:26:39.917383 TX Vref=22, minBit 1, minWin=25, winSum=417
2695 12:26:39.920431 TX Vref=24, minBit 5, minWin=25, winSum=424
2696 12:26:39.923673 TX Vref=26, minBit 4, minWin=26, winSum=435
2697 12:26:39.927152 TX Vref=28, minBit 4, minWin=26, winSum=435
2698 12:26:39.930113 TX Vref=30, minBit 10, minWin=26, winSum=438
2699 12:26:39.936876 TX Vref=32, minBit 8, minWin=26, winSum=432
2700 12:26:39.940660 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
2701 12:26:39.940781
2702 12:26:39.943650 Final TX Range 1 Vref 30
2703 12:26:39.943745
2704 12:26:39.943816 ==
2705 12:26:39.946612 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 12:26:39.950223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 12:26:39.953148 ==
2708 12:26:39.953257
2709 12:26:39.953326
2710 12:26:39.953388 TX Vref Scan disable
2711 12:26:39.956775 == TX Byte 0 ==
2712 12:26:39.960627 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2713 12:26:39.967004 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2714 12:26:39.967158 == TX Byte 1 ==
2715 12:26:39.970021 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2716 12:26:39.976844 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2717 12:26:39.976973
2718 12:26:39.977044 [DATLAT]
2719 12:26:39.977107 Freq=1200, CH0 RK0
2720 12:26:39.977168
2721 12:26:39.980097 DATLAT Default: 0xd
2722 12:26:39.980241 0, 0xFFFF, sum = 0
2723 12:26:39.983776 1, 0xFFFF, sum = 0
2724 12:26:39.986962 2, 0xFFFF, sum = 0
2725 12:26:39.987081 3, 0xFFFF, sum = 0
2726 12:26:39.990162 4, 0xFFFF, sum = 0
2727 12:26:39.990263 5, 0xFFFF, sum = 0
2728 12:26:39.993281 6, 0xFFFF, sum = 0
2729 12:26:39.993382 7, 0xFFFF, sum = 0
2730 12:26:39.996574 8, 0xFFFF, sum = 0
2731 12:26:39.996673 9, 0xFFFF, sum = 0
2732 12:26:40.000301 10, 0xFFFF, sum = 0
2733 12:26:40.000400 11, 0xFFFF, sum = 0
2734 12:26:40.003463 12, 0x0, sum = 1
2735 12:26:40.003558 13, 0x0, sum = 2
2736 12:26:40.006561 14, 0x0, sum = 3
2737 12:26:40.006680 15, 0x0, sum = 4
2738 12:26:40.010380 best_step = 13
2739 12:26:40.010474
2740 12:26:40.010542 ==
2741 12:26:40.013525 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 12:26:40.016584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 12:26:40.016708 ==
2744 12:26:40.016813 RX Vref Scan: 1
2745 12:26:40.020053
2746 12:26:40.020194 Set Vref Range= 32 -> 127
2747 12:26:40.020312
2748 12:26:40.023366 RX Vref 32 -> 127, step: 1
2749 12:26:40.023473
2750 12:26:40.026464 RX Delay -29 -> 252, step: 4
2751 12:26:40.026579
2752 12:26:40.030157 Set Vref, RX VrefLevel [Byte0]: 32
2753 12:26:40.033179 [Byte1]: 32
2754 12:26:40.033308
2755 12:26:40.036657 Set Vref, RX VrefLevel [Byte0]: 33
2756 12:26:40.039567 [Byte1]: 33
2757 12:26:40.043899
2758 12:26:40.044048 Set Vref, RX VrefLevel [Byte0]: 34
2759 12:26:40.046814 [Byte1]: 34
2760 12:26:40.051685
2761 12:26:40.054601 Set Vref, RX VrefLevel [Byte0]: 35
2762 12:26:40.054733 [Byte1]: 35
2763 12:26:40.059275
2764 12:26:40.059399 Set Vref, RX VrefLevel [Byte0]: 36
2765 12:26:40.062731 [Byte1]: 36
2766 12:26:40.067697
2767 12:26:40.067821 Set Vref, RX VrefLevel [Byte0]: 37
2768 12:26:40.070732 [Byte1]: 37
2769 12:26:40.075169
2770 12:26:40.075282 Set Vref, RX VrefLevel [Byte0]: 38
2771 12:26:40.078688 [Byte1]: 38
2772 12:26:40.083265
2773 12:26:40.083392 Set Vref, RX VrefLevel [Byte0]: 39
2774 12:26:40.086336 [Byte1]: 39
2775 12:26:40.091619
2776 12:26:40.091804 Set Vref, RX VrefLevel [Byte0]: 40
2777 12:26:40.094640 [Byte1]: 40
2778 12:26:40.099057
2779 12:26:40.099193 Set Vref, RX VrefLevel [Byte0]: 41
2780 12:26:40.102749 [Byte1]: 41
2781 12:26:40.107116
2782 12:26:40.107217 Set Vref, RX VrefLevel [Byte0]: 42
2783 12:26:40.110231 [Byte1]: 42
2784 12:26:40.115292
2785 12:26:40.115403 Set Vref, RX VrefLevel [Byte0]: 43
2786 12:26:40.118338 [Byte1]: 43
2787 12:26:40.123336
2788 12:26:40.123450 Set Vref, RX VrefLevel [Byte0]: 44
2789 12:26:40.126557 [Byte1]: 44
2790 12:26:40.131076
2791 12:26:40.131227 Set Vref, RX VrefLevel [Byte0]: 45
2792 12:26:40.134293 [Byte1]: 45
2793 12:26:40.139304
2794 12:26:40.139442 Set Vref, RX VrefLevel [Byte0]: 46
2795 12:26:40.142342 [Byte1]: 46
2796 12:26:40.147102
2797 12:26:40.147222 Set Vref, RX VrefLevel [Byte0]: 47
2798 12:26:40.150558 [Byte1]: 47
2799 12:26:40.154930
2800 12:26:40.155068 Set Vref, RX VrefLevel [Byte0]: 48
2801 12:26:40.158546 [Byte1]: 48
2802 12:26:40.162793
2803 12:26:40.162948 Set Vref, RX VrefLevel [Byte0]: 49
2804 12:26:40.166330 [Byte1]: 49
2805 12:26:40.171121
2806 12:26:40.171261 Set Vref, RX VrefLevel [Byte0]: 50
2807 12:26:40.173995 [Byte1]: 50
2808 12:26:40.178990
2809 12:26:40.179166 Set Vref, RX VrefLevel [Byte0]: 51
2810 12:26:40.182098 [Byte1]: 51
2811 12:26:40.187148
2812 12:26:40.187304 Set Vref, RX VrefLevel [Byte0]: 52
2813 12:26:40.190244 [Byte1]: 52
2814 12:26:40.194724
2815 12:26:40.194896 Set Vref, RX VrefLevel [Byte0]: 53
2816 12:26:40.197938 [Byte1]: 53
2817 12:26:40.203075
2818 12:26:40.203191 Set Vref, RX VrefLevel [Byte0]: 54
2819 12:26:40.206123 [Byte1]: 54
2820 12:26:40.210595
2821 12:26:40.210707 Set Vref, RX VrefLevel [Byte0]: 55
2822 12:26:40.213770 [Byte1]: 55
2823 12:26:40.218760
2824 12:26:40.218873 Set Vref, RX VrefLevel [Byte0]: 56
2825 12:26:40.221935 [Byte1]: 56
2826 12:26:40.226967
2827 12:26:40.227054 Set Vref, RX VrefLevel [Byte0]: 57
2828 12:26:40.230005 [Byte1]: 57
2829 12:26:40.234448
2830 12:26:40.234568 Set Vref, RX VrefLevel [Byte0]: 58
2831 12:26:40.237662 [Byte1]: 58
2832 12:26:40.242512
2833 12:26:40.242625 Set Vref, RX VrefLevel [Byte0]: 59
2834 12:26:40.245783 [Byte1]: 59
2835 12:26:40.250744
2836 12:26:40.250861 Set Vref, RX VrefLevel [Byte0]: 60
2837 12:26:40.253831 [Byte1]: 60
2838 12:26:40.258269
2839 12:26:40.258422 Set Vref, RX VrefLevel [Byte0]: 61
2840 12:26:40.261943 [Byte1]: 61
2841 12:26:40.266794
2842 12:26:40.266945 Set Vref, RX VrefLevel [Byte0]: 62
2843 12:26:40.269801 [Byte1]: 62
2844 12:26:40.274554
2845 12:26:40.274704 Set Vref, RX VrefLevel [Byte0]: 63
2846 12:26:40.277687 [Byte1]: 63
2847 12:26:40.282469
2848 12:26:40.282655 Set Vref, RX VrefLevel [Byte0]: 64
2849 12:26:40.285611 [Byte1]: 64
2850 12:26:40.290069
2851 12:26:40.290246 Set Vref, RX VrefLevel [Byte0]: 65
2852 12:26:40.293825 [Byte1]: 65
2853 12:26:40.298132
2854 12:26:40.298275 Set Vref, RX VrefLevel [Byte0]: 66
2855 12:26:40.301511 [Byte1]: 66
2856 12:26:40.306611
2857 12:26:40.306754 Set Vref, RX VrefLevel [Byte0]: 67
2858 12:26:40.309751 [Byte1]: 67
2859 12:26:40.314014
2860 12:26:40.314164 Set Vref, RX VrefLevel [Byte0]: 68
2861 12:26:40.317741 [Byte1]: 68
2862 12:26:40.322180
2863 12:26:40.322322 Set Vref, RX VrefLevel [Byte0]: 69
2864 12:26:40.325380 [Byte1]: 69
2865 12:26:40.330379
2866 12:26:40.330496 Set Vref, RX VrefLevel [Byte0]: 70
2867 12:26:40.333484 [Byte1]: 70
2868 12:26:40.337926
2869 12:26:40.338042 Set Vref, RX VrefLevel [Byte0]: 71
2870 12:26:40.341267 [Byte1]: 71
2871 12:26:40.346120
2872 12:26:40.346230 Set Vref, RX VrefLevel [Byte0]: 72
2873 12:26:40.352331 [Byte1]: 72
2874 12:26:40.352418
2875 12:26:40.356266 Set Vref, RX VrefLevel [Byte0]: 73
2876 12:26:40.359034 [Byte1]: 73
2877 12:26:40.359120
2878 12:26:40.362122 Set Vref, RX VrefLevel [Byte0]: 74
2879 12:26:40.365735 [Byte1]: 74
2880 12:26:40.369690
2881 12:26:40.369797 Final RX Vref Byte 0 = 62 to rank0
2882 12:26:40.373418 Final RX Vref Byte 1 = 53 to rank0
2883 12:26:40.376728 Final RX Vref Byte 0 = 62 to rank1
2884 12:26:40.380294 Final RX Vref Byte 1 = 53 to rank1==
2885 12:26:40.383232 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 12:26:40.389957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 12:26:40.390069 ==
2888 12:26:40.390169 DQS Delay:
2889 12:26:40.393150 DQS0 = 0, DQS1 = 0
2890 12:26:40.393256 DQM Delay:
2891 12:26:40.393350 DQM0 = 112, DQM1 = 101
2892 12:26:40.396293 DQ Delay:
2893 12:26:40.399554 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2894 12:26:40.403248 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2895 12:26:40.406640 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2896 12:26:40.409654 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2897 12:26:40.409760
2898 12:26:40.409854
2899 12:26:40.419822 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2900 12:26:40.419930 CH0 RK0: MR19=303, MR18=FBFB
2901 12:26:40.426244 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2902 12:26:40.426357
2903 12:26:40.429475 ----->DramcWriteLeveling(PI) begin...
2904 12:26:40.429575 ==
2905 12:26:40.432671 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 12:26:40.439385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 12:26:40.439499 ==
2908 12:26:40.443106 Write leveling (Byte 0): 33 => 33
2909 12:26:40.443212 Write leveling (Byte 1): 31 => 31
2910 12:26:40.446277 DramcWriteLeveling(PI) end<-----
2911 12:26:40.446384
2912 12:26:40.446484 ==
2913 12:26:40.449247 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 12:26:40.456171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 12:26:40.456253 ==
2916 12:26:40.459303 [Gating] SW mode calibration
2917 12:26:40.466220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 12:26:40.469200 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 12:26:40.476001 0 15 0 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2920 12:26:40.479084 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 12:26:40.483025 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 12:26:40.489418 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 12:26:40.492319 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 12:26:40.495970 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 12:26:40.502787 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2926 12:26:40.505947 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
2927 12:26:40.508825 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2928 12:26:40.515794 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 12:26:40.518982 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 12:26:40.522182 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 12:26:40.529366 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 12:26:40.532552 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 12:26:40.535726 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2934 12:26:40.542276 1 0 28 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
2935 12:26:40.545520 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2936 12:26:40.548793 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 12:26:40.551909 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 12:26:40.558747 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 12:26:40.562023 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 12:26:40.565838 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 12:26:40.571812 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 12:26:40.575304 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2943 12:26:40.578395 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2944 12:26:40.585010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:26:40.588698 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:26:40.591859 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:26:40.598748 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:26:40.601782 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:26:40.605004 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:26:40.612158 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:26:40.615087 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:26:40.618069 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:26:40.624769 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:26:40.628540 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:26:40.631642 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:26:40.638603 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 12:26:40.641882 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2958 12:26:40.644784 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 12:26:40.651750 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 12:26:40.651830 Total UI for P1: 0, mck2ui 16
2961 12:26:40.658247 best dqsien dly found for B0: ( 1, 3, 26)
2962 12:26:40.658327 Total UI for P1: 0, mck2ui 16
2963 12:26:40.664720 best dqsien dly found for B1: ( 1, 3, 30)
2964 12:26:40.668473 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2965 12:26:40.671699 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2966 12:26:40.671773
2967 12:26:40.674783 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2968 12:26:40.677899 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2969 12:26:40.681579 [Gating] SW calibration Done
2970 12:26:40.681662 ==
2971 12:26:40.685070 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 12:26:40.688019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 12:26:40.688151 ==
2974 12:26:40.691666 RX Vref Scan: 0
2975 12:26:40.691818
2976 12:26:40.691936 RX Vref 0 -> 0, step: 1
2977 12:26:40.692038
2978 12:26:40.694980 RX Delay -40 -> 252, step: 8
2979 12:26:40.697890 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2980 12:26:40.704631 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2981 12:26:40.708337 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2982 12:26:40.711381 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2983 12:26:40.714549 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2984 12:26:40.717784 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2985 12:26:40.724627 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2986 12:26:40.727777 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2987 12:26:40.731457 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2988 12:26:40.734706 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2989 12:26:40.737780 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2990 12:26:40.744718 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2991 12:26:40.747836 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2992 12:26:40.751440 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2993 12:26:40.754509 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2994 12:26:40.757748 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2995 12:26:40.760810 ==
2996 12:26:40.761001 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 12:26:40.767586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 12:26:40.767731 ==
2999 12:26:40.767842 DQS Delay:
3000 12:26:40.771403 DQS0 = 0, DQS1 = 0
3001 12:26:40.771546 DQM Delay:
3002 12:26:40.774558 DQM0 = 112, DQM1 = 102
3003 12:26:40.774701 DQ Delay:
3004 12:26:40.777726 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3005 12:26:40.781420 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3006 12:26:40.784396 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3007 12:26:40.788049 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3008 12:26:40.788223
3009 12:26:40.788378
3010 12:26:40.788528 ==
3011 12:26:40.791042 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 12:26:40.794284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 12:26:40.798332 ==
3014 12:26:40.798506
3015 12:26:40.798664
3016 12:26:40.798839 TX Vref Scan disable
3017 12:26:40.800846 == TX Byte 0 ==
3018 12:26:40.804204 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3019 12:26:40.807690 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3020 12:26:40.811309 == TX Byte 1 ==
3021 12:26:40.814049 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3022 12:26:40.817804 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3023 12:26:40.821103 ==
3024 12:26:40.824120 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 12:26:40.827696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 12:26:40.828005 ==
3027 12:26:40.839012 TX Vref=22, minBit 8, minWin=26, winSum=428
3028 12:26:40.842039 TX Vref=24, minBit 2, minWin=26, winSum=429
3029 12:26:40.845885 TX Vref=26, minBit 1, minWin=27, winSum=439
3030 12:26:40.848996 TX Vref=28, minBit 0, minWin=27, winSum=440
3031 12:26:40.852077 TX Vref=30, minBit 1, minWin=27, winSum=440
3032 12:26:40.859101 TX Vref=32, minBit 1, minWin=27, winSum=441
3033 12:26:40.861958 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 32
3034 12:26:40.862468
3035 12:26:40.865096 Final TX Range 1 Vref 32
3036 12:26:40.865587
3037 12:26:40.866050 ==
3038 12:26:40.868830 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 12:26:40.871822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 12:26:40.875089 ==
3041 12:26:40.875581
3042 12:26:40.876031
3043 12:26:40.876508 TX Vref Scan disable
3044 12:26:40.878962 == TX Byte 0 ==
3045 12:26:40.882041 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3046 12:26:40.888315 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3047 12:26:40.888839 == TX Byte 1 ==
3048 12:26:40.891966 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3049 12:26:40.898203 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3050 12:26:40.898790
3051 12:26:40.899473 [DATLAT]
3052 12:26:40.900056 Freq=1200, CH0 RK1
3053 12:26:40.900629
3054 12:26:40.901962 DATLAT Default: 0xd
3055 12:26:40.904898 0, 0xFFFF, sum = 0
3056 12:26:40.905487 1, 0xFFFF, sum = 0
3057 12:26:40.908433 2, 0xFFFF, sum = 0
3058 12:26:40.908937 3, 0xFFFF, sum = 0
3059 12:26:40.911720 4, 0xFFFF, sum = 0
3060 12:26:40.912089 5, 0xFFFF, sum = 0
3061 12:26:40.915264 6, 0xFFFF, sum = 0
3062 12:26:40.915584 7, 0xFFFF, sum = 0
3063 12:26:40.918130 8, 0xFFFF, sum = 0
3064 12:26:40.918338 9, 0xFFFF, sum = 0
3065 12:26:40.921496 10, 0xFFFF, sum = 0
3066 12:26:40.921682 11, 0xFFFF, sum = 0
3067 12:26:40.925003 12, 0x0, sum = 1
3068 12:26:40.925190 13, 0x0, sum = 2
3069 12:26:40.927751 14, 0x0, sum = 3
3070 12:26:40.927908 15, 0x0, sum = 4
3071 12:26:40.931284 best_step = 13
3072 12:26:40.931441
3073 12:26:40.931547 ==
3074 12:26:40.934596 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 12:26:40.937681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 12:26:40.937820 ==
3077 12:26:40.941283 RX Vref Scan: 0
3078 12:26:40.941426
3079 12:26:40.941538 RX Vref 0 -> 0, step: 1
3080 12:26:40.941647
3081 12:26:40.944301 RX Delay -37 -> 252, step: 4
3082 12:26:40.951147 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3083 12:26:40.954322 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3084 12:26:40.958064 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3085 12:26:40.960987 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3086 12:26:40.964571 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3087 12:26:40.970791 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3088 12:26:40.973836 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3089 12:26:40.977595 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3090 12:26:40.980831 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3091 12:26:40.984074 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3092 12:26:40.990422 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3093 12:26:40.994048 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3094 12:26:40.997249 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3095 12:26:41.000930 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3096 12:26:41.004137 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3097 12:26:41.010407 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3098 12:26:41.010560 ==
3099 12:26:41.013955 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 12:26:41.016947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 12:26:41.017039 ==
3102 12:26:41.017119 DQS Delay:
3103 12:26:41.020648 DQS0 = 0, DQS1 = 0
3104 12:26:41.020744 DQM Delay:
3105 12:26:41.023986 DQM0 = 111, DQM1 = 101
3106 12:26:41.024083 DQ Delay:
3107 12:26:41.027233 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3108 12:26:41.030620 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3109 12:26:41.033626 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3110 12:26:41.037041 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3111 12:26:41.037170
3112 12:26:41.037267
3113 12:26:41.046915 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3114 12:26:41.050589 CH0 RK1: MR19=403, MR18=10F8
3115 12:26:41.056775 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3116 12:26:41.060549 [RxdqsGatingPostProcess] freq 1200
3117 12:26:41.063635 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3118 12:26:41.067137 best DQS0 dly(2T, 0.5T) = (0, 12)
3119 12:26:41.070585 best DQS1 dly(2T, 0.5T) = (0, 12)
3120 12:26:41.073965 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3121 12:26:41.076948 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3122 12:26:41.080581 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 12:26:41.083872 best DQS1 dly(2T, 0.5T) = (0, 11)
3124 12:26:41.086861 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 12:26:41.090027 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3126 12:26:41.093783 Pre-setting of DQS Precalculation
3127 12:26:41.096808 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3128 12:26:41.097330 ==
3129 12:26:41.099956 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 12:26:41.103265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 12:26:41.106911 ==
3132 12:26:41.110222 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 12:26:41.116826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3134 12:26:41.125051 [CA 0] Center 37 (7~67) winsize 61
3135 12:26:41.128491 [CA 1] Center 37 (7~68) winsize 62
3136 12:26:41.131439 [CA 2] Center 34 (4~64) winsize 61
3137 12:26:41.135126 [CA 3] Center 33 (3~64) winsize 62
3138 12:26:41.138511 [CA 4] Center 34 (4~64) winsize 61
3139 12:26:41.141413 [CA 5] Center 33 (3~63) winsize 61
3140 12:26:41.142042
3141 12:26:41.144727 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3142 12:26:41.145244
3143 12:26:41.148286 [CATrainingPosCal] consider 1 rank data
3144 12:26:41.151655 u2DelayCellTimex100 = 270/100 ps
3145 12:26:41.154761 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3146 12:26:41.161573 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 12:26:41.164687 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 12:26:41.168587 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 12:26:41.171390 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 12:26:41.174724 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3151 12:26:41.175248
3152 12:26:41.178073 CA PerBit enable=1, Macro0, CA PI delay=33
3153 12:26:41.178582
3154 12:26:41.181487 [CBTSetCACLKResult] CA Dly = 33
3155 12:26:41.182022 CS Dly: 5 (0~36)
3156 12:26:41.184867 ==
3157 12:26:41.188008 Dram Type= 6, Freq= 0, CH_1, rank 1
3158 12:26:41.191152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 12:26:41.191588 ==
3160 12:26:41.194894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3161 12:26:41.201089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3162 12:26:41.210778 [CA 0] Center 37 (7~67) winsize 61
3163 12:26:41.213758 [CA 1] Center 37 (7~68) winsize 62
3164 12:26:41.216963 [CA 2] Center 34 (4~65) winsize 62
3165 12:26:41.220868 [CA 3] Center 33 (3~64) winsize 62
3166 12:26:41.223815 [CA 4] Center 34 (4~65) winsize 62
3167 12:26:41.226868 [CA 5] Center 33 (3~63) winsize 61
3168 12:26:41.227393
3169 12:26:41.230531 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3170 12:26:41.231064
3171 12:26:41.233599 [CATrainingPosCal] consider 2 rank data
3172 12:26:41.237278 u2DelayCellTimex100 = 270/100 ps
3173 12:26:41.240747 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3174 12:26:41.246948 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3175 12:26:41.250311 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 12:26:41.253643 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3177 12:26:41.256537 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 12:26:41.260009 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3179 12:26:41.260605
3180 12:26:41.263513 CA PerBit enable=1, Macro0, CA PI delay=33
3181 12:26:41.264109
3182 12:26:41.266514 [CBTSetCACLKResult] CA Dly = 33
3183 12:26:41.270378 CS Dly: 7 (0~40)
3184 12:26:41.271000
3185 12:26:41.273214 ----->DramcWriteLeveling(PI) begin...
3186 12:26:41.273657 ==
3187 12:26:41.276633 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 12:26:41.279686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 12:26:41.280130 ==
3190 12:26:41.283686 Write leveling (Byte 0): 24 => 24
3191 12:26:41.286429 Write leveling (Byte 1): 28 => 28
3192 12:26:41.289635 DramcWriteLeveling(PI) end<-----
3193 12:26:41.290084
3194 12:26:41.290516 ==
3195 12:26:41.292858 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 12:26:41.296618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 12:26:41.297060 ==
3198 12:26:41.299864 [Gating] SW mode calibration
3199 12:26:41.306076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3200 12:26:41.312937 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3201 12:26:41.316193 0 15 0 | B1->B0 | 3232 302f | 1 1 | (1 1) (0 0)
3202 12:26:41.319372 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 12:26:41.325823 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 12:26:41.329543 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 12:26:41.332629 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 12:26:41.339197 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 12:26:41.342855 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 12:26:41.346252 0 15 28 | B1->B0 | 2d2d 3131 | 0 1 | (0 0) (0 0)
3209 12:26:41.352579 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 12:26:41.356253 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 12:26:41.359295 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 12:26:41.365829 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 12:26:41.369414 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 12:26:41.372881 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 12:26:41.379196 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3216 12:26:41.382670 1 0 28 | B1->B0 | 4242 3838 | 0 0 | (0 0) (0 0)
3217 12:26:41.386194 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3218 12:26:41.392530 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 12:26:41.396263 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 12:26:41.399285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 12:26:41.405820 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 12:26:41.409075 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 12:26:41.412676 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 12:26:41.418926 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3225 12:26:41.422866 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:26:41.425859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:26:41.432167 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:26:41.435633 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:26:41.438820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:26:41.442544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:26:41.448859 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:26:41.452458 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:26:41.455359 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:26:41.462277 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:26:41.465442 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:26:41.469112 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:26:41.475580 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:26:41.478590 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 12:26:41.482042 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 12:26:41.488505 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3241 12:26:41.492160 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 12:26:41.494989 Total UI for P1: 0, mck2ui 16
3243 12:26:41.498383 best dqsien dly found for B0: ( 1, 3, 28)
3244 12:26:41.501776 Total UI for P1: 0, mck2ui 16
3245 12:26:41.504888 best dqsien dly found for B1: ( 1, 3, 28)
3246 12:26:41.508646 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3247 12:26:41.511796 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3248 12:26:41.511952
3249 12:26:41.514754 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3250 12:26:41.518022 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3251 12:26:41.521761 [Gating] SW calibration Done
3252 12:26:41.521913 ==
3253 12:26:41.524840 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 12:26:41.531086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 12:26:41.531200 ==
3256 12:26:41.531287 RX Vref Scan: 0
3257 12:26:41.531377
3258 12:26:41.534286 RX Vref 0 -> 0, step: 1
3259 12:26:41.534411
3260 12:26:41.537984 RX Delay -40 -> 252, step: 8
3261 12:26:41.541088 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3262 12:26:41.544296 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3263 12:26:41.547856 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3264 12:26:41.554460 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3265 12:26:41.557993 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3266 12:26:41.560956 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3267 12:26:41.564574 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3268 12:26:41.567444 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3269 12:26:41.571145 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3270 12:26:41.577366 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3271 12:26:41.580897 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3272 12:26:41.584058 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3273 12:26:41.587568 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3274 12:26:41.591097 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3275 12:26:41.597638 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3276 12:26:41.601259 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3277 12:26:41.601362 ==
3278 12:26:41.604204 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 12:26:41.607788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 12:26:41.607896 ==
3281 12:26:41.610645 DQS Delay:
3282 12:26:41.610731 DQS0 = 0, DQS1 = 0
3283 12:26:41.610799 DQM Delay:
3284 12:26:41.614506 DQM0 = 112, DQM1 = 106
3285 12:26:41.614589 DQ Delay:
3286 12:26:41.617549 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =115
3287 12:26:41.621216 DQ4 =107, DQ5 =123, DQ6 =123, DQ7 =111
3288 12:26:41.624380 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3289 12:26:41.631195 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3290 12:26:41.631359
3291 12:26:41.631458
3292 12:26:41.631588 ==
3293 12:26:41.634370 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 12:26:41.637484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 12:26:41.637604 ==
3296 12:26:41.637714
3297 12:26:41.637808
3298 12:26:41.640688 TX Vref Scan disable
3299 12:26:41.640795 == TX Byte 0 ==
3300 12:26:41.647487 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3301 12:26:41.651065 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3302 12:26:41.651181 == TX Byte 1 ==
3303 12:26:41.657216 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3304 12:26:41.660959 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3305 12:26:41.661170 ==
3306 12:26:41.664139 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 12:26:41.667212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 12:26:41.667353 ==
3309 12:26:41.680358 TX Vref=22, minBit 8, minWin=24, winSum=407
3310 12:26:41.683461 TX Vref=24, minBit 8, minWin=25, winSum=413
3311 12:26:41.686740 TX Vref=26, minBit 9, minWin=25, winSum=420
3312 12:26:41.690301 TX Vref=28, minBit 9, minWin=25, winSum=421
3313 12:26:41.693254 TX Vref=30, minBit 9, minWin=25, winSum=424
3314 12:26:41.699818 TX Vref=32, minBit 9, minWin=25, winSum=419
3315 12:26:41.703474 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 30
3316 12:26:41.703585
3317 12:26:41.706440 Final TX Range 1 Vref 30
3318 12:26:41.706547
3319 12:26:41.706650 ==
3320 12:26:41.710005 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 12:26:41.713129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 12:26:41.716660 ==
3323 12:26:41.716768
3324 12:26:41.716871
3325 12:26:41.716971 TX Vref Scan disable
3326 12:26:41.719768 == TX Byte 0 ==
3327 12:26:41.723103 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3328 12:26:41.729890 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3329 12:26:41.730003 == TX Byte 1 ==
3330 12:26:41.733089 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3331 12:26:41.740120 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3332 12:26:41.740209
3333 12:26:41.740278 [DATLAT]
3334 12:26:41.740341 Freq=1200, CH1 RK0
3335 12:26:41.740402
3336 12:26:41.743228 DATLAT Default: 0xd
3337 12:26:41.746274 0, 0xFFFF, sum = 0
3338 12:26:41.746390 1, 0xFFFF, sum = 0
3339 12:26:41.750037 2, 0xFFFF, sum = 0
3340 12:26:41.750152 3, 0xFFFF, sum = 0
3341 12:26:41.753156 4, 0xFFFF, sum = 0
3342 12:26:41.753270 5, 0xFFFF, sum = 0
3343 12:26:41.756121 6, 0xFFFF, sum = 0
3344 12:26:41.756208 7, 0xFFFF, sum = 0
3345 12:26:41.759880 8, 0xFFFF, sum = 0
3346 12:26:41.759966 9, 0xFFFF, sum = 0
3347 12:26:41.762981 10, 0xFFFF, sum = 0
3348 12:26:41.763094 11, 0xFFFF, sum = 0
3349 12:26:41.766099 12, 0x0, sum = 1
3350 12:26:41.766211 13, 0x0, sum = 2
3351 12:26:41.769707 14, 0x0, sum = 3
3352 12:26:41.769820 15, 0x0, sum = 4
3353 12:26:41.772809 best_step = 13
3354 12:26:41.772893
3355 12:26:41.772958 ==
3356 12:26:41.775897 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 12:26:41.779372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 12:26:41.779457 ==
3359 12:26:41.782962 RX Vref Scan: 1
3360 12:26:41.783076
3361 12:26:41.783187 Set Vref Range= 32 -> 127
3362 12:26:41.783255
3363 12:26:41.785887 RX Vref 32 -> 127, step: 1
3364 12:26:41.785996
3365 12:26:41.789188 RX Delay -21 -> 252, step: 4
3366 12:26:41.789298
3367 12:26:41.792721 Set Vref, RX VrefLevel [Byte0]: 32
3368 12:26:41.795808 [Byte1]: 32
3369 12:26:41.795893
3370 12:26:41.799639 Set Vref, RX VrefLevel [Byte0]: 33
3371 12:26:41.802833 [Byte1]: 33
3372 12:26:41.806467
3373 12:26:41.806577 Set Vref, RX VrefLevel [Byte0]: 34
3374 12:26:41.809528 [Byte1]: 34
3375 12:26:41.814347
3376 12:26:41.814458 Set Vref, RX VrefLevel [Byte0]: 35
3377 12:26:41.817475 [Byte1]: 35
3378 12:26:41.822337
3379 12:26:41.822444 Set Vref, RX VrefLevel [Byte0]: 36
3380 12:26:41.826019 [Byte1]: 36
3381 12:26:41.830347
3382 12:26:41.830451 Set Vref, RX VrefLevel [Byte0]: 37
3383 12:26:41.833469 [Byte1]: 37
3384 12:26:41.838483
3385 12:26:41.838555 Set Vref, RX VrefLevel [Byte0]: 38
3386 12:26:41.841609 [Byte1]: 38
3387 12:26:41.845932
3388 12:26:41.846004 Set Vref, RX VrefLevel [Byte0]: 39
3389 12:26:41.849160 [Byte1]: 39
3390 12:26:41.854077
3391 12:26:41.854163 Set Vref, RX VrefLevel [Byte0]: 40
3392 12:26:41.857354 [Byte1]: 40
3393 12:26:41.862114
3394 12:26:41.862216 Set Vref, RX VrefLevel [Byte0]: 41
3395 12:26:41.865258 [Byte1]: 41
3396 12:26:41.869785
3397 12:26:41.872919 Set Vref, RX VrefLevel [Byte0]: 42
3398 12:26:41.873005 [Byte1]: 42
3399 12:26:41.877870
3400 12:26:41.877978 Set Vref, RX VrefLevel [Byte0]: 43
3401 12:26:41.881042 [Byte1]: 43
3402 12:26:41.885991
3403 12:26:41.886102 Set Vref, RX VrefLevel [Byte0]: 44
3404 12:26:41.889115 [Byte1]: 44
3405 12:26:41.893439
3406 12:26:41.893517 Set Vref, RX VrefLevel [Byte0]: 45
3407 12:26:41.897067 [Byte1]: 45
3408 12:26:41.901361
3409 12:26:41.901438 Set Vref, RX VrefLevel [Byte0]: 46
3410 12:26:41.904638 [Byte1]: 46
3411 12:26:41.909672
3412 12:26:41.909755 Set Vref, RX VrefLevel [Byte0]: 47
3413 12:26:41.912642 [Byte1]: 47
3414 12:26:41.917489
3415 12:26:41.917598 Set Vref, RX VrefLevel [Byte0]: 48
3416 12:26:41.920513 [Byte1]: 48
3417 12:26:41.925333
3418 12:26:41.925443 Set Vref, RX VrefLevel [Byte0]: 49
3419 12:26:41.928915 [Byte1]: 49
3420 12:26:41.933182
3421 12:26:41.933292 Set Vref, RX VrefLevel [Byte0]: 50
3422 12:26:41.936282 [Byte1]: 50
3423 12:26:41.941295
3424 12:26:41.941395 Set Vref, RX VrefLevel [Byte0]: 51
3425 12:26:41.944457 [Byte1]: 51
3426 12:26:41.949353
3427 12:26:41.949461 Set Vref, RX VrefLevel [Byte0]: 52
3428 12:26:41.952595 [Byte1]: 52
3429 12:26:41.956856
3430 12:26:41.956963 Set Vref, RX VrefLevel [Byte0]: 53
3431 12:26:41.960648 [Byte1]: 53
3432 12:26:41.964685
3433 12:26:41.964766 Set Vref, RX VrefLevel [Byte0]: 54
3434 12:26:41.968239 [Byte1]: 54
3435 12:26:41.972724
3436 12:26:41.972831 Set Vref, RX VrefLevel [Byte0]: 55
3437 12:26:41.976521 [Byte1]: 55
3438 12:26:41.980838
3439 12:26:41.980911 Set Vref, RX VrefLevel [Byte0]: 56
3440 12:26:41.984003 [Byte1]: 56
3441 12:26:41.988794
3442 12:26:41.988875 Set Vref, RX VrefLevel [Byte0]: 57
3443 12:26:41.991947 [Byte1]: 57
3444 12:26:41.996915
3445 12:26:41.996996 Set Vref, RX VrefLevel [Byte0]: 58
3446 12:26:41.999836 [Byte1]: 58
3447 12:26:42.004856
3448 12:26:42.004937 Set Vref, RX VrefLevel [Byte0]: 59
3449 12:26:42.008017 [Byte1]: 59
3450 12:26:42.012377
3451 12:26:42.012457 Set Vref, RX VrefLevel [Byte0]: 60
3452 12:26:42.016178 [Byte1]: 60
3453 12:26:42.020329
3454 12:26:42.020410 Set Vref, RX VrefLevel [Byte0]: 61
3455 12:26:42.023877 [Byte1]: 61
3456 12:26:42.028311
3457 12:26:42.028394 Set Vref, RX VrefLevel [Byte0]: 62
3458 12:26:42.031406 [Byte1]: 62
3459 12:26:42.036412
3460 12:26:42.036495 Set Vref, RX VrefLevel [Byte0]: 63
3461 12:26:42.039350 [Byte1]: 63
3462 12:26:42.044289
3463 12:26:42.044375 Set Vref, RX VrefLevel [Byte0]: 64
3464 12:26:42.047425 [Byte1]: 64
3465 12:26:42.051883
3466 12:26:42.051965 Final RX Vref Byte 0 = 54 to rank0
3467 12:26:42.055689 Final RX Vref Byte 1 = 46 to rank0
3468 12:26:42.058690 Final RX Vref Byte 0 = 54 to rank1
3469 12:26:42.062430 Final RX Vref Byte 1 = 46 to rank1==
3470 12:26:42.065614 Dram Type= 6, Freq= 0, CH_1, rank 0
3471 12:26:42.071552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 12:26:42.071637 ==
3473 12:26:42.071704 DQS Delay:
3474 12:26:42.075328 DQS0 = 0, DQS1 = 0
3475 12:26:42.075412 DQM Delay:
3476 12:26:42.078422 DQM0 = 113, DQM1 = 104
3477 12:26:42.078505 DQ Delay:
3478 12:26:42.081558 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =110
3479 12:26:42.085305 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3480 12:26:42.088525 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =98
3481 12:26:42.091589 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3482 12:26:42.091673
3483 12:26:42.091740
3484 12:26:42.101500 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3485 12:26:42.101611 CH1 RK0: MR19=303, MR18=F0F8
3486 12:26:42.108170 CH1_RK0: MR19=0x303, MR18=0xF0F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3487 12:26:42.108277
3488 12:26:42.111273 ----->DramcWriteLeveling(PI) begin...
3489 12:26:42.111357 ==
3490 12:26:42.114989 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 12:26:42.121556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 12:26:42.121640 ==
3493 12:26:42.124677 Write leveling (Byte 0): 24 => 24
3494 12:26:42.128224 Write leveling (Byte 1): 27 => 27
3495 12:26:42.128308 DramcWriteLeveling(PI) end<-----
3496 12:26:42.128375
3497 12:26:42.131081 ==
3498 12:26:42.134624 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 12:26:42.137757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 12:26:42.137841 ==
3501 12:26:42.140819 [Gating] SW mode calibration
3502 12:26:42.147680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3503 12:26:42.150766 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3504 12:26:42.157375 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 12:26:42.161108 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 12:26:42.164214 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 12:26:42.170991 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 12:26:42.173934 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 12:26:42.177083 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 12:26:42.184001 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
3511 12:26:42.187135 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3512 12:26:42.190965 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 12:26:42.197080 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 12:26:42.200709 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 12:26:42.203789 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 12:26:42.210865 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 12:26:42.213611 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3518 12:26:42.217299 1 0 24 | B1->B0 | 2d2d 4545 | 1 0 | (0 0) (0 0)
3519 12:26:42.223743 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 12:26:42.226951 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 12:26:42.230616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 12:26:42.236560 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 12:26:42.239991 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 12:26:42.243741 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 12:26:42.250004 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 12:26:42.253133 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3527 12:26:42.256869 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3528 12:26:42.263599 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:26:42.266699 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:26:42.269762 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:26:42.276516 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:26:42.279529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:26:42.336455 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:26:42.336887 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:26:42.337013 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:26:42.337142 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:26:42.337248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:26:42.337352 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:26:42.337463 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:26:42.337562 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:26:42.337668 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3542 12:26:42.337765 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3543 12:26:42.337872 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3544 12:26:42.337966 Total UI for P1: 0, mck2ui 16
3545 12:26:42.338077 best dqsien dly found for B0: ( 1, 3, 22)
3546 12:26:42.338968 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 12:26:42.342668 Total UI for P1: 0, mck2ui 16
3548 12:26:42.345582 best dqsien dly found for B1: ( 1, 3, 26)
3549 12:26:42.348891 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3550 12:26:42.352027 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3551 12:26:42.352357
3552 12:26:42.355680 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3553 12:26:42.362179 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3554 12:26:42.362533 [Gating] SW calibration Done
3555 12:26:42.362792 ==
3556 12:26:42.365353 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 12:26:42.371904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 12:26:42.372008 ==
3559 12:26:42.372080 RX Vref Scan: 0
3560 12:26:42.372220
3561 12:26:42.374972 RX Vref 0 -> 0, step: 1
3562 12:26:42.375072
3563 12:26:42.378639 RX Delay -40 -> 252, step: 8
3564 12:26:42.381747 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3565 12:26:42.384867 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3566 12:26:42.388757 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3567 12:26:42.395021 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3568 12:26:42.398036 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3569 12:26:42.401831 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3570 12:26:42.404998 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3571 12:26:42.408373 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3572 12:26:42.414668 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3573 12:26:42.418296 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3574 12:26:42.421468 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3575 12:26:42.424641 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3576 12:26:42.427970 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3577 12:26:42.434475 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3578 12:26:42.437743 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3579 12:26:42.440890 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3580 12:26:42.441077 ==
3581 12:26:42.444713 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 12:26:42.447734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 12:26:42.447997 ==
3584 12:26:42.451312 DQS Delay:
3585 12:26:42.451654 DQS0 = 0, DQS1 = 0
3586 12:26:42.454385 DQM Delay:
3587 12:26:42.454768 DQM0 = 110, DQM1 = 106
3588 12:26:42.458127 DQ Delay:
3589 12:26:42.461225 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3590 12:26:42.464452 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3591 12:26:42.468126 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3592 12:26:42.471350 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =115
3593 12:26:42.471774
3594 12:26:42.472108
3595 12:26:42.472425 ==
3596 12:26:42.474224 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 12:26:42.477366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 12:26:42.477968 ==
3599 12:26:42.478469
3600 12:26:42.478952
3601 12:26:42.481040 TX Vref Scan disable
3602 12:26:42.484135 == TX Byte 0 ==
3603 12:26:42.487656 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3604 12:26:42.490714 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3605 12:26:42.494499 == TX Byte 1 ==
3606 12:26:42.497576 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3607 12:26:42.500656 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3608 12:26:42.501085 ==
3609 12:26:42.503824 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 12:26:42.510364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 12:26:42.510796 ==
3612 12:26:42.521420 TX Vref=22, minBit 3, minWin=25, winSum=417
3613 12:26:42.524547 TX Vref=24, minBit 3, minWin=26, winSum=428
3614 12:26:42.527688 TX Vref=26, minBit 8, minWin=26, winSum=431
3615 12:26:42.530909 TX Vref=28, minBit 9, minWin=26, winSum=436
3616 12:26:42.533970 TX Vref=30, minBit 8, minWin=26, winSum=431
3617 12:26:42.541109 TX Vref=32, minBit 8, minWin=25, winSum=432
3618 12:26:42.543974 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3619 12:26:42.544403
3620 12:26:42.547621 Final TX Range 1 Vref 28
3621 12:26:42.548050
3622 12:26:42.548386 ==
3623 12:26:42.550688 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 12:26:42.553687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 12:26:42.557290 ==
3626 12:26:42.557714
3627 12:26:42.558051
3628 12:26:42.558364 TX Vref Scan disable
3629 12:26:42.560796 == TX Byte 0 ==
3630 12:26:42.564406 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3631 12:26:42.570381 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3632 12:26:42.570809 == TX Byte 1 ==
3633 12:26:42.574210 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3634 12:26:42.580331 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3635 12:26:42.580860
3636 12:26:42.581212 [DATLAT]
3637 12:26:42.581533 Freq=1200, CH1 RK1
3638 12:26:42.582025
3639 12:26:42.583996 DATLAT Default: 0xd
3640 12:26:42.587129 0, 0xFFFF, sum = 0
3641 12:26:42.587564 1, 0xFFFF, sum = 0
3642 12:26:42.590131 2, 0xFFFF, sum = 0
3643 12:26:42.590562 3, 0xFFFF, sum = 0
3644 12:26:42.593558 4, 0xFFFF, sum = 0
3645 12:26:42.593991 5, 0xFFFF, sum = 0
3646 12:26:42.597013 6, 0xFFFF, sum = 0
3647 12:26:42.597446 7, 0xFFFF, sum = 0
3648 12:26:42.600543 8, 0xFFFF, sum = 0
3649 12:26:42.600980 9, 0xFFFF, sum = 0
3650 12:26:42.603750 10, 0xFFFF, sum = 0
3651 12:26:42.604183 11, 0xFFFF, sum = 0
3652 12:26:42.606882 12, 0x0, sum = 1
3653 12:26:42.607318 13, 0x0, sum = 2
3654 12:26:42.610085 14, 0x0, sum = 3
3655 12:26:42.610519 15, 0x0, sum = 4
3656 12:26:42.613671 best_step = 13
3657 12:26:42.614321
3658 12:26:42.614878 ==
3659 12:26:42.617012 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 12:26:42.620081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 12:26:42.620620 ==
3662 12:26:42.623251 RX Vref Scan: 0
3663 12:26:42.623785
3664 12:26:42.624302 RX Vref 0 -> 0, step: 1
3665 12:26:42.624804
3666 12:26:42.626936 RX Delay -21 -> 252, step: 4
3667 12:26:42.633271 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3668 12:26:42.636461 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3669 12:26:42.640158 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3670 12:26:42.643366 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3671 12:26:42.649658 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3672 12:26:42.652954 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3673 12:26:42.656032 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3674 12:26:42.659593 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3675 12:26:42.663172 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3676 12:26:42.666125 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3677 12:26:42.672773 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3678 12:26:42.676054 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3679 12:26:42.679498 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3680 12:26:42.682606 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3681 12:26:42.689392 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3682 12:26:42.692449 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3683 12:26:42.693058 ==
3684 12:26:42.696009 Dram Type= 6, Freq= 0, CH_1, rank 1
3685 12:26:42.699115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3686 12:26:42.699632 ==
3687 12:26:42.702200 DQS Delay:
3688 12:26:42.702616 DQS0 = 0, DQS1 = 0
3689 12:26:42.703018 DQM Delay:
3690 12:26:42.706037 DQM0 = 111, DQM1 = 108
3691 12:26:42.706457 DQ Delay:
3692 12:26:42.709142 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3693 12:26:42.712943 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =108
3694 12:26:42.716057 DQ8 =94, DQ9 =98, DQ10 =110, DQ11 =100
3695 12:26:42.722820 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =116
3696 12:26:42.723286
3697 12:26:42.723620
3698 12:26:42.728819 [DQSOSCAuto] RK1, (LSB)MR18= 0xf706, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3699 12:26:42.732681 CH1 RK1: MR19=304, MR18=F706
3700 12:26:42.738990 CH1_RK1: MR19=0x304, MR18=0xF706, DQSOSC=407, MR23=63, INC=39, DEC=26
3701 12:26:42.742150 [RxdqsGatingPostProcess] freq 1200
3702 12:26:42.745841 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3703 12:26:42.749047 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 12:26:42.752111 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 12:26:42.755508 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 12:26:42.758869 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 12:26:42.761911 best DQS0 dly(2T, 0.5T) = (0, 11)
3708 12:26:42.765478 best DQS1 dly(2T, 0.5T) = (0, 11)
3709 12:26:42.768474 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3710 12:26:42.772081 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3711 12:26:42.774972 Pre-setting of DQS Precalculation
3712 12:26:42.778409 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3713 12:26:42.788108 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3714 12:26:42.794928 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3715 12:26:42.795385
3716 12:26:42.795726
3717 12:26:42.797906 [Calibration Summary] 2400 Mbps
3718 12:26:42.798462 CH 0, Rank 0
3719 12:26:42.801521 SW Impedance : PASS
3720 12:26:42.802073 DUTY Scan : NO K
3721 12:26:42.804531 ZQ Calibration : PASS
3722 12:26:42.808164 Jitter Meter : NO K
3723 12:26:42.808591 CBT Training : PASS
3724 12:26:42.811262 Write leveling : PASS
3725 12:26:42.814481 RX DQS gating : PASS
3726 12:26:42.815163 RX DQ/DQS(RDDQC) : PASS
3727 12:26:42.818084 TX DQ/DQS : PASS
3728 12:26:42.821373 RX DATLAT : PASS
3729 12:26:42.821944 RX DQ/DQS(Engine): PASS
3730 12:26:42.824533 TX OE : NO K
3731 12:26:42.824962 All Pass.
3732 12:26:42.825301
3733 12:26:42.827612 CH 0, Rank 1
3734 12:26:42.828037 SW Impedance : PASS
3735 12:26:42.831028 DUTY Scan : NO K
3736 12:26:42.834205 ZQ Calibration : PASS
3737 12:26:42.834910 Jitter Meter : NO K
3738 12:26:42.837298 CBT Training : PASS
3739 12:26:42.841164 Write leveling : PASS
3740 12:26:42.841591 RX DQS gating : PASS
3741 12:26:42.844207 RX DQ/DQS(RDDQC) : PASS
3742 12:26:42.847344 TX DQ/DQS : PASS
3743 12:26:42.847777 RX DATLAT : PASS
3744 12:26:42.850437 RX DQ/DQS(Engine): PASS
3745 12:26:42.854207 TX OE : NO K
3746 12:26:42.854765 All Pass.
3747 12:26:42.855295
3748 12:26:42.855759 CH 1, Rank 0
3749 12:26:42.857409 SW Impedance : PASS
3750 12:26:42.860640 DUTY Scan : NO K
3751 12:26:42.861063 ZQ Calibration : PASS
3752 12:26:42.863699 Jitter Meter : NO K
3753 12:26:42.867535 CBT Training : PASS
3754 12:26:42.867961 Write leveling : PASS
3755 12:26:42.870152 RX DQS gating : PASS
3756 12:26:42.873800 RX DQ/DQS(RDDQC) : PASS
3757 12:26:42.874219 TX DQ/DQS : PASS
3758 12:26:42.876880 RX DATLAT : PASS
3759 12:26:42.880457 RX DQ/DQS(Engine): PASS
3760 12:26:42.880979 TX OE : NO K
3761 12:26:42.881451 All Pass.
3762 12:26:42.883543
3763 12:26:42.883958 CH 1, Rank 1
3764 12:26:42.887158 SW Impedance : PASS
3765 12:26:42.887588 DUTY Scan : NO K
3766 12:26:42.889897 ZQ Calibration : PASS
3767 12:26:42.890405 Jitter Meter : NO K
3768 12:26:42.919790 CBT Training : PASS
3769 12:26:42.920284 Write leveling : PASS
3770 12:26:42.920648 RX DQS gating : PASS
3771 12:26:42.921009 RX DQ/DQS(RDDQC) : PASS
3772 12:26:42.921365 TX DQ/DQS : PASS
3773 12:26:42.921678 RX DATLAT : PASS
3774 12:26:42.922021 RX DQ/DQS(Engine): PASS
3775 12:26:42.922323 TX OE : NO K
3776 12:26:42.922820 All Pass.
3777 12:26:42.923330
3778 12:26:42.923641 DramC Write-DBI off
3779 12:26:42.923929 PER_BANK_REFRESH: Hybrid Mode
3780 12:26:42.924211 TX_TRACKING: ON
3781 12:26:42.926711 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3782 12:26:42.929800 [FAST_K] Save calibration result to emmc
3783 12:26:42.932849 dramc_set_vcore_voltage set vcore to 650000
3784 12:26:42.933377 Read voltage for 600, 5
3785 12:26:42.936621 Vio18 = 0
3786 12:26:42.937044 Vcore = 650000
3787 12:26:42.937380 Vdram = 0
3788 12:26:42.939557 Vddq = 0
3789 12:26:42.939974 Vmddr = 0
3790 12:26:42.946373 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3791 12:26:42.949534 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3792 12:26:42.953193 MEM_TYPE=3, freq_sel=19
3793 12:26:42.956427 sv_algorithm_assistance_LP4_1600
3794 12:26:42.959607 ============ PULL DRAM RESETB DOWN ============
3795 12:26:42.962589 ========== PULL DRAM RESETB DOWN end =========
3796 12:26:42.969638 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3797 12:26:42.972598 ===================================
3798 12:26:42.973034 LPDDR4 DRAM CONFIGURATION
3799 12:26:42.975683 ===================================
3800 12:26:42.979126 EX_ROW_EN[0] = 0x0
3801 12:26:42.982626 EX_ROW_EN[1] = 0x0
3802 12:26:42.983158 LP4Y_EN = 0x0
3803 12:26:42.985683 WORK_FSP = 0x0
3804 12:26:42.986108 WL = 0x2
3805 12:26:42.989226 RL = 0x2
3806 12:26:42.989823 BL = 0x2
3807 12:26:42.992177 RPST = 0x0
3808 12:26:42.992762 RD_PRE = 0x0
3809 12:26:42.995723 WR_PRE = 0x1
3810 12:26:42.996283 WR_PST = 0x0
3811 12:26:42.999246 DBI_WR = 0x0
3812 12:26:42.999769 DBI_RD = 0x0
3813 12:26:43.002171 OTF = 0x1
3814 12:26:43.005947 ===================================
3815 12:26:43.009055 ===================================
3816 12:26:43.009681 ANA top config
3817 12:26:43.012119 ===================================
3818 12:26:43.015719 DLL_ASYNC_EN = 0
3819 12:26:43.018783 ALL_SLAVE_EN = 1
3820 12:26:43.021808 NEW_RANK_MODE = 1
3821 12:26:43.022373 DLL_IDLE_MODE = 1
3822 12:26:43.025511 LP45_APHY_COMB_EN = 1
3823 12:26:43.028715 TX_ODT_DIS = 1
3824 12:26:43.031823 NEW_8X_MODE = 1
3825 12:26:43.035114 ===================================
3826 12:26:43.038768 ===================================
3827 12:26:43.041825 data_rate = 1200
3828 12:26:43.044996 CKR = 1
3829 12:26:43.045423 DQ_P2S_RATIO = 8
3830 12:26:43.048734 ===================================
3831 12:26:43.051867 CA_P2S_RATIO = 8
3832 12:26:43.055053 DQ_CA_OPEN = 0
3833 12:26:43.058152 DQ_SEMI_OPEN = 0
3834 12:26:43.061934 CA_SEMI_OPEN = 0
3835 12:26:43.062359 CA_FULL_RATE = 0
3836 12:26:43.065047 DQ_CKDIV4_EN = 1
3837 12:26:43.068259 CA_CKDIV4_EN = 1
3838 12:26:43.071402 CA_PREDIV_EN = 0
3839 12:26:43.074921 PH8_DLY = 0
3840 12:26:43.078151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3841 12:26:43.078600 DQ_AAMCK_DIV = 4
3842 12:26:43.081494 CA_AAMCK_DIV = 4
3843 12:26:43.085107 CA_ADMCK_DIV = 4
3844 12:26:43.088233 DQ_TRACK_CA_EN = 0
3845 12:26:43.091879 CA_PICK = 600
3846 12:26:43.094573 CA_MCKIO = 600
3847 12:26:43.098182 MCKIO_SEMI = 0
3848 12:26:43.101135 PLL_FREQ = 2288
3849 12:26:43.101558 DQ_UI_PI_RATIO = 32
3850 12:26:43.104652 CA_UI_PI_RATIO = 0
3851 12:26:43.107959 ===================================
3852 12:26:43.111591 ===================================
3853 12:26:43.114517 memory_type:LPDDR4
3854 12:26:43.117693 GP_NUM : 10
3855 12:26:43.118124 SRAM_EN : 1
3856 12:26:43.121415 MD32_EN : 0
3857 12:26:43.124356 ===================================
3858 12:26:43.124920 [ANA_INIT] >>>>>>>>>>>>>>
3859 12:26:43.128081 <<<<<< [CONFIGURE PHASE]: ANA_TX
3860 12:26:43.131075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3861 12:26:43.134581 ===================================
3862 12:26:43.137754 data_rate = 1200,PCW = 0X5800
3863 12:26:43.140984 ===================================
3864 12:26:43.144127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3865 12:26:43.150655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3866 12:26:43.157240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3867 12:26:43.161160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3868 12:26:43.164239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3869 12:26:43.167233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3870 12:26:43.170382 [ANA_INIT] flow start
3871 12:26:43.170924 [ANA_INIT] PLL >>>>>>>>
3872 12:26:43.174168 [ANA_INIT] PLL <<<<<<<<
3873 12:26:43.177350 [ANA_INIT] MIDPI >>>>>>>>
3874 12:26:43.180402 [ANA_INIT] MIDPI <<<<<<<<
3875 12:26:43.181027 [ANA_INIT] DLL >>>>>>>>
3876 12:26:43.184108 [ANA_INIT] flow end
3877 12:26:43.187170 ============ LP4 DIFF to SE enter ============
3878 12:26:43.190367 ============ LP4 DIFF to SE exit ============
3879 12:26:43.194004 [ANA_INIT] <<<<<<<<<<<<<
3880 12:26:43.197259 [Flow] Enable top DCM control >>>>>
3881 12:26:43.200252 [Flow] Enable top DCM control <<<<<
3882 12:26:43.203746 Enable DLL master slave shuffle
3883 12:26:43.210479 ==============================================================
3884 12:26:43.210985 Gating Mode config
3885 12:26:43.217100 ==============================================================
3886 12:26:43.217532 Config description:
3887 12:26:43.226474 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3888 12:26:43.233270 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3889 12:26:43.239537 SELPH_MODE 0: By rank 1: By Phase
3890 12:26:43.243287 ==============================================================
3891 12:26:43.246369 GAT_TRACK_EN = 1
3892 12:26:43.249435 RX_GATING_MODE = 2
3893 12:26:43.253225 RX_GATING_TRACK_MODE = 2
3894 12:26:43.256382 SELPH_MODE = 1
3895 12:26:43.259680 PICG_EARLY_EN = 1
3896 12:26:43.262513 VALID_LAT_VALUE = 1
3897 12:26:43.268934 ==============================================================
3898 12:26:43.272710 Enter into Gating configuration >>>>
3899 12:26:43.275749 Exit from Gating configuration <<<<
3900 12:26:43.278854 Enter into DVFS_PRE_config >>>>>
3901 12:26:43.288883 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3902 12:26:43.292092 Exit from DVFS_PRE_config <<<<<
3903 12:26:43.295235 Enter into PICG configuration >>>>
3904 12:26:43.299021 Exit from PICG configuration <<<<
3905 12:26:43.301965 [RX_INPUT] configuration >>>>>
3906 12:26:43.305180 [RX_INPUT] configuration <<<<<
3907 12:26:43.308939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3908 12:26:43.315433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3909 12:26:43.321784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 12:26:43.325279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 12:26:43.332080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 12:26:43.338200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 12:26:43.341702 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3914 12:26:43.348416 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3915 12:26:43.351624 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3916 12:26:43.354654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3917 12:26:43.358421 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3918 12:26:43.364744 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 12:26:43.368011 ===================================
3920 12:26:43.368109 LPDDR4 DRAM CONFIGURATION
3921 12:26:43.371847 ===================================
3922 12:26:43.374991 EX_ROW_EN[0] = 0x0
3923 12:26:43.378020 EX_ROW_EN[1] = 0x0
3924 12:26:43.378133 LP4Y_EN = 0x0
3925 12:26:43.381137 WORK_FSP = 0x0
3926 12:26:43.381285 WL = 0x2
3927 12:26:43.385218 RL = 0x2
3928 12:26:43.385342 BL = 0x2
3929 12:26:43.388165 RPST = 0x0
3930 12:26:43.388309 RD_PRE = 0x0
3931 12:26:43.391429 WR_PRE = 0x1
3932 12:26:43.391589 WR_PST = 0x0
3933 12:26:43.394593 DBI_WR = 0x0
3934 12:26:43.394747 DBI_RD = 0x0
3935 12:26:43.397768 OTF = 0x1
3936 12:26:43.401369 ===================================
3937 12:26:43.404523 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3938 12:26:43.407742 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3939 12:26:43.414561 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3940 12:26:43.417613 ===================================
3941 12:26:43.418004 LPDDR4 DRAM CONFIGURATION
3942 12:26:43.421148 ===================================
3943 12:26:43.424892 EX_ROW_EN[0] = 0x10
3944 12:26:43.427825 EX_ROW_EN[1] = 0x0
3945 12:26:43.428252 LP4Y_EN = 0x0
3946 12:26:43.431342 WORK_FSP = 0x0
3947 12:26:43.431765 WL = 0x2
3948 12:26:43.434430 RL = 0x2
3949 12:26:43.435065 BL = 0x2
3950 12:26:43.437476 RPST = 0x0
3951 12:26:43.438014 RD_PRE = 0x0
3952 12:26:43.441194 WR_PRE = 0x1
3953 12:26:43.441616 WR_PST = 0x0
3954 12:26:43.444172 DBI_WR = 0x0
3955 12:26:43.444615 DBI_RD = 0x0
3956 12:26:43.447821 OTF = 0x1
3957 12:26:43.450806 ===================================
3958 12:26:43.457286 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3959 12:26:43.460388 nWR fixed to 30
3960 12:26:43.464158 [ModeRegInit_LP4] CH0 RK0
3961 12:26:43.464671 [ModeRegInit_LP4] CH0 RK1
3962 12:26:43.467511 [ModeRegInit_LP4] CH1 RK0
3963 12:26:43.470532 [ModeRegInit_LP4] CH1 RK1
3964 12:26:43.471129 match AC timing 17
3965 12:26:43.477501 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3966 12:26:43.480597 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3967 12:26:43.484330 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3968 12:26:43.490857 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3969 12:26:43.493703 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3970 12:26:43.494128 ==
3971 12:26:43.496993 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 12:26:43.500754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 12:26:43.501321 ==
3974 12:26:43.507323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3975 12:26:43.513739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3976 12:26:43.517274 [CA 0] Center 37 (7~67) winsize 61
3977 12:26:43.520519 [CA 1] Center 37 (7~67) winsize 61
3978 12:26:43.523773 [CA 2] Center 35 (5~65) winsize 61
3979 12:26:43.526698 [CA 3] Center 35 (5~65) winsize 61
3980 12:26:43.530157 [CA 4] Center 34 (4~65) winsize 62
3981 12:26:43.533914 [CA 5] Center 34 (4~64) winsize 61
3982 12:26:43.534352
3983 12:26:43.536701 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3984 12:26:43.537220
3985 12:26:43.540121 [CATrainingPosCal] consider 1 rank data
3986 12:26:43.543459 u2DelayCellTimex100 = 270/100 ps
3987 12:26:43.546610 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3988 12:26:43.550084 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3989 12:26:43.553505 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3990 12:26:43.556329 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3991 12:26:43.562942 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3992 12:26:43.566513 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3993 12:26:43.566974
3994 12:26:43.570268 CA PerBit enable=1, Macro0, CA PI delay=34
3995 12:26:43.570798
3996 12:26:43.573129 [CBTSetCACLKResult] CA Dly = 34
3997 12:26:43.573551 CS Dly: 6 (0~37)
3998 12:26:43.573889 ==
3999 12:26:43.576485 Dram Type= 6, Freq= 0, CH_0, rank 1
4000 12:26:43.582656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 12:26:43.583129 ==
4002 12:26:43.586439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4003 12:26:43.592655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4004 12:26:43.595840 [CA 0] Center 37 (7~67) winsize 61
4005 12:26:43.599635 [CA 1] Center 36 (6~67) winsize 62
4006 12:26:43.602767 [CA 2] Center 35 (5~65) winsize 61
4007 12:26:43.606038 [CA 3] Center 35 (5~65) winsize 61
4008 12:26:43.609575 [CA 4] Center 34 (4~65) winsize 62
4009 12:26:43.612679 [CA 5] Center 34 (3~65) winsize 63
4010 12:26:43.613103
4011 12:26:43.615890 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4012 12:26:43.616314
4013 12:26:43.619004 [CATrainingPosCal] consider 2 rank data
4014 12:26:43.622520 u2DelayCellTimex100 = 270/100 ps
4015 12:26:43.625474 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4016 12:26:43.632417 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4017 12:26:43.635627 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4018 12:26:43.639481 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4019 12:26:43.642672 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4020 12:26:43.645634 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4021 12:26:43.646058
4022 12:26:43.649200 CA PerBit enable=1, Macro0, CA PI delay=34
4023 12:26:43.649754
4024 12:26:43.652585 [CBTSetCACLKResult] CA Dly = 34
4025 12:26:43.653009 CS Dly: 6 (0~37)
4026 12:26:43.655466
4027 12:26:43.659214 ----->DramcWriteLeveling(PI) begin...
4028 12:26:43.659756 ==
4029 12:26:43.661904 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 12:26:43.665514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 12:26:43.665944 ==
4032 12:26:43.669028 Write leveling (Byte 0): 33 => 33
4033 12:26:43.672288 Write leveling (Byte 1): 32 => 32
4034 12:26:43.675434 DramcWriteLeveling(PI) end<-----
4035 12:26:43.675874
4036 12:26:43.676212 ==
4037 12:26:43.678404 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 12:26:43.682377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 12:26:43.682808 ==
4040 12:26:43.685546 [Gating] SW mode calibration
4041 12:26:43.691863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4042 12:26:43.698959 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4043 12:26:43.702105 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 12:26:43.705566 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 12:26:43.712068 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 12:26:43.715282 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4047 12:26:43.718283 0 9 16 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
4048 12:26:43.725551 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 12:26:43.728723 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 12:26:43.731706 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 12:26:43.738196 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 12:26:43.741223 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 12:26:43.745286 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 12:26:43.751701 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4055 12:26:43.754665 0 10 16 | B1->B0 | 2d2d 3838 | 1 0 | (0 0) (0 0)
4056 12:26:43.757603 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 12:26:43.764336 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 12:26:43.767534 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 12:26:43.771077 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:26:43.777421 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 12:26:43.781000 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 12:26:43.784069 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 12:26:43.790390 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4064 12:26:43.794034 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:26:43.797218 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:26:43.803755 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:26:43.806698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:26:43.810452 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:26:43.816858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:26:43.820121 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:26:43.823256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:26:43.830135 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:26:43.833424 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:26:43.836463 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:26:43.842889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:26:43.846462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:26:43.849617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:26:43.855996 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4079 12:26:43.859360 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4080 12:26:43.862779 Total UI for P1: 0, mck2ui 16
4081 12:26:43.866290 best dqsien dly found for B0: ( 0, 13, 12)
4082 12:26:43.869188 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4083 12:26:43.876130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 12:26:43.876214 Total UI for P1: 0, mck2ui 16
4085 12:26:43.882362 best dqsien dly found for B1: ( 0, 13, 20)
4086 12:26:43.885964 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4087 12:26:43.889116 best DQS1 dly(MCK, UI, PI) = (0, 13, 20)
4088 12:26:43.889225
4089 12:26:43.892197 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4090 12:26:43.895372 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 20)
4091 12:26:43.898514 [Gating] SW calibration Done
4092 12:26:43.898622 ==
4093 12:26:43.902327 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 12:26:43.905318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 12:26:43.905428 ==
4096 12:26:43.908517 RX Vref Scan: 0
4097 12:26:43.908600
4098 12:26:43.912224 RX Vref 0 -> 0, step: 1
4099 12:26:43.912308
4100 12:26:43.912374 RX Delay -230 -> 252, step: 16
4101 12:26:43.918517 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4102 12:26:43.922255 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4103 12:26:43.925309 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4104 12:26:43.928458 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4105 12:26:43.935017 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4106 12:26:43.938750 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4107 12:26:43.941847 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4108 12:26:43.945027 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4109 12:26:43.951909 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4110 12:26:43.955087 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4111 12:26:43.958834 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4112 12:26:43.961779 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4113 12:26:43.965196 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4114 12:26:43.971917 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4115 12:26:43.974823 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4116 12:26:43.978469 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4117 12:26:43.978552 ==
4118 12:26:43.981443 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 12:26:43.987917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 12:26:43.988000 ==
4121 12:26:43.988065 DQS Delay:
4122 12:26:43.991298 DQS0 = 0, DQS1 = 0
4123 12:26:43.991416 DQM Delay:
4124 12:26:43.991485 DQM0 = 38, DQM1 = 30
4125 12:26:43.995083 DQ Delay:
4126 12:26:43.998044 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4127 12:26:44.001295 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4128 12:26:44.004524 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4129 12:26:44.008138 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4130 12:26:44.008233
4131 12:26:44.008308
4132 12:26:44.008378 ==
4133 12:26:44.011371 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 12:26:44.014606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 12:26:44.014710 ==
4136 12:26:44.014792
4137 12:26:44.014877
4138 12:26:44.017657 TX Vref Scan disable
4139 12:26:44.020848 == TX Byte 0 ==
4140 12:26:44.024417 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4141 12:26:44.027631 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4142 12:26:44.031239 == TX Byte 1 ==
4143 12:26:44.034428 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4144 12:26:44.037724 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4145 12:26:44.037900 ==
4146 12:26:44.040890 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 12:26:44.047134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 12:26:44.047381 ==
4149 12:26:44.047576
4150 12:26:44.047755
4151 12:26:44.047926 TX Vref Scan disable
4152 12:26:44.051592 == TX Byte 0 ==
4153 12:26:44.054638 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4154 12:26:44.061935 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4155 12:26:44.062464 == TX Byte 1 ==
4156 12:26:44.064780 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4157 12:26:44.071470 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4158 12:26:44.071913
4159 12:26:44.072353 [DATLAT]
4160 12:26:44.072871 Freq=600, CH0 RK0
4161 12:26:44.073379
4162 12:26:44.074607 DATLAT Default: 0x9
4163 12:26:44.078219 0, 0xFFFF, sum = 0
4164 12:26:44.078669 1, 0xFFFF, sum = 0
4165 12:26:44.081138 2, 0xFFFF, sum = 0
4166 12:26:44.081589 3, 0xFFFF, sum = 0
4167 12:26:44.084831 4, 0xFFFF, sum = 0
4168 12:26:44.085282 5, 0xFFFF, sum = 0
4169 12:26:44.087782 6, 0xFFFF, sum = 0
4170 12:26:44.088230 7, 0xFFFF, sum = 0
4171 12:26:44.091380 8, 0x0, sum = 1
4172 12:26:44.091877 9, 0x0, sum = 2
4173 12:26:44.094318 10, 0x0, sum = 3
4174 12:26:44.094901 11, 0x0, sum = 4
4175 12:26:44.095325 best_step = 9
4176 12:26:44.095733
4177 12:26:44.097705 ==
4178 12:26:44.100906 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 12:26:44.104049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 12:26:44.104493 ==
4181 12:26:44.104936 RX Vref Scan: 1
4182 12:26:44.105355
4183 12:26:44.107497 RX Vref 0 -> 0, step: 1
4184 12:26:44.107942
4185 12:26:44.110779 RX Delay -195 -> 252, step: 8
4186 12:26:44.111211
4187 12:26:44.113987 Set Vref, RX VrefLevel [Byte0]: 62
4188 12:26:44.116962 [Byte1]: 53
4189 12:26:44.120666
4190 12:26:44.121077 Final RX Vref Byte 0 = 62 to rank0
4191 12:26:44.123939 Final RX Vref Byte 1 = 53 to rank0
4192 12:26:44.126939 Final RX Vref Byte 0 = 62 to rank1
4193 12:26:44.130572 Final RX Vref Byte 1 = 53 to rank1==
4194 12:26:44.133641 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 12:26:44.140299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 12:26:44.140872 ==
4197 12:26:44.141335 DQS Delay:
4198 12:26:44.143940 DQS0 = 0, DQS1 = 0
4199 12:26:44.144380 DQM Delay:
4200 12:26:44.144822 DQM0 = 36, DQM1 = 29
4201 12:26:44.147089 DQ Delay:
4202 12:26:44.150218 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =28
4203 12:26:44.153705 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =48
4204 12:26:44.156944 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4205 12:26:44.159835 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4206 12:26:44.160394
4207 12:26:44.160874
4208 12:26:44.166894 [DQSOSCAuto] RK0, (LSB)MR18= 0x4241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4209 12:26:44.169939 CH0 RK0: MR19=808, MR18=4241
4210 12:26:44.176289 CH0_RK0: MR19=0x808, MR18=0x4241, DQSOSC=397, MR23=63, INC=166, DEC=110
4211 12:26:44.176846
4212 12:26:44.179991 ----->DramcWriteLeveling(PI) begin...
4213 12:26:44.180427 ==
4214 12:26:44.182981 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 12:26:44.186624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 12:26:44.187098 ==
4217 12:26:44.189812 Write leveling (Byte 0): 32 => 32
4218 12:26:44.192807 Write leveling (Byte 1): 31 => 31
4219 12:26:44.195932 DramcWriteLeveling(PI) end<-----
4220 12:26:44.196676
4221 12:26:44.197254 ==
4222 12:26:44.199556 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 12:26:44.206011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 12:26:44.206450 ==
4225 12:26:44.206797 [Gating] SW mode calibration
4226 12:26:44.215581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 12:26:44.219430 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4228 12:26:44.225459 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 12:26:44.228693 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 12:26:44.232275 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 12:26:44.235806 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 1)
4232 12:26:44.242124 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4233 12:26:44.245270 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 12:26:44.249073 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 12:26:44.255372 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 12:26:44.259190 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 12:26:44.262464 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 12:26:44.268672 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 12:26:44.272287 0 10 12 | B1->B0 | 2828 3535 | 0 0 | (1 1) (0 0)
4240 12:26:44.275560 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4241 12:26:44.281898 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 12:26:44.285545 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:26:44.288935 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 12:26:44.294985 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 12:26:44.298589 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 12:26:44.301645 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:26:44.308160 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4248 12:26:44.311462 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:26:44.314897 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:26:44.321707 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:26:44.324918 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:26:44.327890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:26:44.334739 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:26:44.338263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:26:44.341380 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:26:44.348196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:26:44.351389 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:26:44.354490 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:26:44.360891 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:26:44.364576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:26:44.367860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:26:44.374557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:26:44.377981 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4264 12:26:44.381145 Total UI for P1: 0, mck2ui 16
4265 12:26:44.384296 best dqsien dly found for B0: ( 0, 13, 10)
4266 12:26:44.387475 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 12:26:44.391137 Total UI for P1: 0, mck2ui 16
4268 12:26:44.394112 best dqsien dly found for B1: ( 0, 13, 14)
4269 12:26:44.397180 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4270 12:26:44.400707 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4271 12:26:44.404070
4272 12:26:44.407163 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4273 12:26:44.410731 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4274 12:26:44.413890 [Gating] SW calibration Done
4275 12:26:44.414317 ==
4276 12:26:44.417456 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 12:26:44.420766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 12:26:44.421199 ==
4279 12:26:44.423557 RX Vref Scan: 0
4280 12:26:44.423982
4281 12:26:44.424319 RX Vref 0 -> 0, step: 1
4282 12:26:44.424636
4283 12:26:44.426853 RX Delay -230 -> 252, step: 16
4284 12:26:44.430507 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4285 12:26:44.437166 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4286 12:26:44.440226 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4287 12:26:44.443511 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4288 12:26:44.447187 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4289 12:26:44.453505 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4290 12:26:44.456674 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4291 12:26:44.460373 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4292 12:26:44.463326 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4293 12:26:44.467488 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4294 12:26:44.473440 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4295 12:26:44.476919 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4296 12:26:44.480141 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4297 12:26:44.483210 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4298 12:26:44.490089 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4299 12:26:44.493330 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4300 12:26:44.493836 ==
4301 12:26:44.496535 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 12:26:44.499957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 12:26:44.500662 ==
4304 12:26:44.503181 DQS Delay:
4305 12:26:44.503753 DQS0 = 0, DQS1 = 0
4306 12:26:44.504240 DQM Delay:
4307 12:26:44.506664 DQM0 = 35, DQM1 = 27
4308 12:26:44.506977 DQ Delay:
4309 12:26:44.509658 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4310 12:26:44.513061 DQ4 =33, DQ5 =17, DQ6 =41, DQ7 =57
4311 12:26:44.516150 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4312 12:26:44.519467 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4313 12:26:44.519719
4314 12:26:44.519933
4315 12:26:44.520135 ==
4316 12:26:44.522582 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 12:26:44.529108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 12:26:44.529280 ==
4319 12:26:44.529399
4320 12:26:44.529503
4321 12:26:44.529597 TX Vref Scan disable
4322 12:26:44.533455 == TX Byte 0 ==
4323 12:26:44.536682 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4324 12:26:44.543398 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4325 12:26:44.543589 == TX Byte 1 ==
4326 12:26:44.546351 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4327 12:26:44.553262 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4328 12:26:44.553395 ==
4329 12:26:44.556442 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 12:26:44.559472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 12:26:44.559601 ==
4332 12:26:44.559675
4333 12:26:44.559752
4334 12:26:44.562602 TX Vref Scan disable
4335 12:26:44.566289 == TX Byte 0 ==
4336 12:26:44.569628 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4337 12:26:44.572748 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4338 12:26:44.575699 == TX Byte 1 ==
4339 12:26:44.578768 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4340 12:26:44.582766 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4341 12:26:44.583351
4342 12:26:44.585903 [DATLAT]
4343 12:26:44.586421 Freq=600, CH0 RK1
4344 12:26:44.586807
4345 12:26:44.589085 DATLAT Default: 0x9
4346 12:26:44.589549 0, 0xFFFF, sum = 0
4347 12:26:44.592878 1, 0xFFFF, sum = 0
4348 12:26:44.593701 2, 0xFFFF, sum = 0
4349 12:26:44.595972 3, 0xFFFF, sum = 0
4350 12:26:44.596436 4, 0xFFFF, sum = 0
4351 12:26:44.598966 5, 0xFFFF, sum = 0
4352 12:26:44.599418 6, 0xFFFF, sum = 0
4353 12:26:44.602116 7, 0xFFFF, sum = 0
4354 12:26:44.602577 8, 0x0, sum = 1
4355 12:26:44.605623 9, 0x0, sum = 2
4356 12:26:44.606119 10, 0x0, sum = 3
4357 12:26:44.609027 11, 0x0, sum = 4
4358 12:26:44.609758 best_step = 9
4359 12:26:44.610164
4360 12:26:44.610513 ==
4361 12:26:44.612503 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 12:26:44.615458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 12:26:44.618810 ==
4364 12:26:44.619091 RX Vref Scan: 0
4365 12:26:44.619289
4366 12:26:44.621859 RX Vref 0 -> 0, step: 1
4367 12:26:44.622109
4368 12:26:44.625380 RX Delay -195 -> 252, step: 8
4369 12:26:44.628407 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4370 12:26:44.634885 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4371 12:26:44.638570 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4372 12:26:44.641640 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4373 12:26:44.644819 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4374 12:26:44.647998 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4375 12:26:44.654789 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4376 12:26:44.657803 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4377 12:26:44.661079 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4378 12:26:44.664951 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4379 12:26:44.671207 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4380 12:26:44.674319 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4381 12:26:44.677625 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4382 12:26:44.681381 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4383 12:26:44.687561 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4384 12:26:44.690669 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4385 12:26:44.690787 ==
4386 12:26:44.694433 Dram Type= 6, Freq= 0, CH_0, rank 1
4387 12:26:44.697631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 12:26:44.697751 ==
4389 12:26:44.700891 DQS Delay:
4390 12:26:44.701009 DQS0 = 0, DQS1 = 0
4391 12:26:44.701102 DQM Delay:
4392 12:26:44.703969 DQM0 = 34, DQM1 = 27
4393 12:26:44.704100 DQ Delay:
4394 12:26:44.707157 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4395 12:26:44.710982 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4396 12:26:44.713785 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4397 12:26:44.717280 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4398 12:26:44.717358
4399 12:26:44.717423
4400 12:26:44.726804 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4401 12:26:44.730263 CH0 RK1: MR19=808, MR18=6F3E
4402 12:26:44.736971 CH0_RK1: MR19=0x808, MR18=0x6F3E, DQSOSC=389, MR23=63, INC=173, DEC=115
4403 12:26:44.737086 [RxdqsGatingPostProcess] freq 600
4404 12:26:44.743613 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4405 12:26:44.747597 Pre-setting of DQS Precalculation
4406 12:26:44.750604 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4407 12:26:44.753795 ==
4408 12:26:44.756860 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 12:26:44.760536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 12:26:44.761049 ==
4411 12:26:44.764192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4412 12:26:44.770503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4413 12:26:44.774270 [CA 0] Center 35 (5~66) winsize 62
4414 12:26:44.777292 [CA 1] Center 36 (6~66) winsize 61
4415 12:26:44.780343 [CA 2] Center 34 (4~65) winsize 62
4416 12:26:44.784240 [CA 3] Center 34 (3~65) winsize 63
4417 12:26:44.787056 [CA 4] Center 34 (4~65) winsize 62
4418 12:26:44.790243 [CA 5] Center 33 (3~64) winsize 62
4419 12:26:44.790603
4420 12:26:44.793921 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4421 12:26:44.794381
4422 12:26:44.796884 [CATrainingPosCal] consider 1 rank data
4423 12:26:44.800185 u2DelayCellTimex100 = 270/100 ps
4424 12:26:44.803377 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4425 12:26:44.810197 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4426 12:26:44.813436 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4427 12:26:44.816667 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4428 12:26:44.819784 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 12:26:44.823331 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 12:26:44.823583
4431 12:26:44.826663 CA PerBit enable=1, Macro0, CA PI delay=33
4432 12:26:44.826789
4433 12:26:44.829703 [CBTSetCACLKResult] CA Dly = 33
4434 12:26:44.832870 CS Dly: 5 (0~36)
4435 12:26:44.832955 ==
4436 12:26:44.836541 Dram Type= 6, Freq= 0, CH_1, rank 1
4437 12:26:44.839710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 12:26:44.839796 ==
4439 12:26:44.846167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4440 12:26:44.849656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4441 12:26:44.853904 [CA 0] Center 36 (6~66) winsize 61
4442 12:26:44.857030 [CA 1] Center 36 (6~67) winsize 62
4443 12:26:44.860229 [CA 2] Center 34 (4~65) winsize 62
4444 12:26:44.864207 [CA 3] Center 34 (3~65) winsize 63
4445 12:26:44.867297 [CA 4] Center 34 (4~65) winsize 62
4446 12:26:44.870798 [CA 5] Center 34 (3~65) winsize 63
4447 12:26:44.871073
4448 12:26:44.874009 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4449 12:26:44.874188
4450 12:26:44.877239 [CATrainingPosCal] consider 2 rank data
4451 12:26:44.880362 u2DelayCellTimex100 = 270/100 ps
4452 12:26:44.884159 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4453 12:26:44.890384 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4454 12:26:44.894235 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4455 12:26:44.897474 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4456 12:26:44.900615 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 12:26:44.903906 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4458 12:26:44.904479
4459 12:26:44.907019 CA PerBit enable=1, Macro0, CA PI delay=33
4460 12:26:44.907516
4461 12:26:44.910713 [CBTSetCACLKResult] CA Dly = 33
4462 12:26:44.913757 CS Dly: 5 (0~36)
4463 12:26:44.914224
4464 12:26:44.916869 ----->DramcWriteLeveling(PI) begin...
4465 12:26:44.917344 ==
4466 12:26:44.920600 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 12:26:44.923936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 12:26:44.924408 ==
4469 12:26:44.926763 Write leveling (Byte 0): 29 => 29
4470 12:26:44.930256 Write leveling (Byte 1): 29 => 29
4471 12:26:44.933633 DramcWriteLeveling(PI) end<-----
4472 12:26:44.934158
4473 12:26:44.934562 ==
4474 12:26:44.936663 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 12:26:44.940339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 12:26:44.940820 ==
4477 12:26:44.943208 [Gating] SW mode calibration
4478 12:26:44.949875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4479 12:26:44.956464 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4480 12:26:44.959735 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 12:26:44.965932 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 12:26:44.969754 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 12:26:44.972683 0 9 12 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 0)
4484 12:26:44.978631 0 9 16 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
4485 12:26:44.982200 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 12:26:44.985336 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 12:26:44.992326 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 12:26:44.995669 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 12:26:44.998621 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 12:26:45.004922 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 12:26:45.008784 0 10 12 | B1->B0 | 2d2d 2d2d | 0 0 | (0 0) (0 0)
4492 12:26:45.011780 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4493 12:26:45.018112 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 12:26:45.021316 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:26:45.024597 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:26:45.031695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 12:26:45.034455 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 12:26:45.038164 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 12:26:45.044601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4500 12:26:45.048171 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4501 12:26:45.051234 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:26:45.057577 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:26:45.060862 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:26:45.064429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:26:45.071161 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:26:45.074336 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:26:45.077717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:26:45.084551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:26:45.088156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:26:45.091297 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:26:45.097564 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:26:45.101147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:26:45.104233 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:26:45.111142 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:26:45.114127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:26:45.117329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4517 12:26:45.124215 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 12:26:45.124645 Total UI for P1: 0, mck2ui 16
4519 12:26:45.127339 best dqsien dly found for B0: ( 0, 13, 16)
4520 12:26:45.131144 Total UI for P1: 0, mck2ui 16
4521 12:26:45.134134 best dqsien dly found for B1: ( 0, 13, 18)
4522 12:26:45.140893 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4523 12:26:45.143880 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4524 12:26:45.144310
4525 12:26:45.147399 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4526 12:26:45.150414 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4527 12:26:45.153922 [Gating] SW calibration Done
4528 12:26:45.154381 ==
4529 12:26:45.157427 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 12:26:45.160436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 12:26:45.160864 ==
4532 12:26:45.164027 RX Vref Scan: 0
4533 12:26:45.164480
4534 12:26:45.164817 RX Vref 0 -> 0, step: 1
4535 12:26:45.165134
4536 12:26:45.166886 RX Delay -230 -> 252, step: 16
4537 12:26:45.170440 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4538 12:26:45.177031 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4539 12:26:45.180148 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4540 12:26:45.183361 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4541 12:26:45.186884 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4542 12:26:45.193091 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4543 12:26:45.196786 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4544 12:26:45.199939 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4545 12:26:45.203111 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4546 12:26:45.209887 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4547 12:26:45.213100 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4548 12:26:45.216267 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4549 12:26:45.219996 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4550 12:26:45.226297 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4551 12:26:45.229697 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4552 12:26:45.232644 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4553 12:26:45.232767 ==
4554 12:26:45.236473 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 12:26:45.239453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 12:26:45.242615 ==
4557 12:26:45.242769 DQS Delay:
4558 12:26:45.242896 DQS0 = 0, DQS1 = 0
4559 12:26:45.246477 DQM Delay:
4560 12:26:45.246643 DQM0 = 38, DQM1 = 28
4561 12:26:45.249059 DQ Delay:
4562 12:26:45.249189 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4563 12:26:45.252820 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4564 12:26:45.255693 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4565 12:26:45.259280 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4566 12:26:45.262516
4567 12:26:45.262718
4568 12:26:45.262917 ==
4569 12:26:45.265433 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 12:26:45.269062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 12:26:45.269220 ==
4572 12:26:45.269372
4573 12:26:45.269508
4574 12:26:45.272736 TX Vref Scan disable
4575 12:26:45.272925 == TX Byte 0 ==
4576 12:26:45.278745 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4577 12:26:45.282300 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4578 12:26:45.282446 == TX Byte 1 ==
4579 12:26:45.288508 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4580 12:26:45.292335 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4581 12:26:45.292493 ==
4582 12:26:45.295322 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 12:26:45.298405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 12:26:45.298546 ==
4585 12:26:45.298660
4586 12:26:45.302001
4587 12:26:45.302134 TX Vref Scan disable
4588 12:26:45.305526 == TX Byte 0 ==
4589 12:26:45.308296 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4590 12:26:45.315132 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4591 12:26:45.315359 == TX Byte 1 ==
4592 12:26:45.318340 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4593 12:26:45.325347 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4594 12:26:45.325565
4595 12:26:45.325739 [DATLAT]
4596 12:26:45.325899 Freq=600, CH1 RK0
4597 12:26:45.326055
4598 12:26:45.328557 DATLAT Default: 0x9
4599 12:26:45.331809 0, 0xFFFF, sum = 0
4600 12:26:45.332142 1, 0xFFFF, sum = 0
4601 12:26:45.334992 2, 0xFFFF, sum = 0
4602 12:26:45.335324 3, 0xFFFF, sum = 0
4603 12:26:45.338238 4, 0xFFFF, sum = 0
4604 12:26:45.338672 5, 0xFFFF, sum = 0
4605 12:26:45.342151 6, 0xFFFF, sum = 0
4606 12:26:45.342628 7, 0xFFFF, sum = 0
4607 12:26:45.345333 8, 0x0, sum = 1
4608 12:26:45.345828 9, 0x0, sum = 2
4609 12:26:45.348414 10, 0x0, sum = 3
4610 12:26:45.348892 11, 0x0, sum = 4
4611 12:26:45.349271 best_step = 9
4612 12:26:45.349619
4613 12:26:45.351637 ==
4614 12:26:45.354761 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 12:26:45.358251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 12:26:45.358918 ==
4617 12:26:45.359495 RX Vref Scan: 1
4618 12:26:45.360077
4619 12:26:45.361622 RX Vref 0 -> 0, step: 1
4620 12:26:45.362183
4621 12:26:45.364671 RX Delay -195 -> 252, step: 8
4622 12:26:45.365208
4623 12:26:45.368210 Set Vref, RX VrefLevel [Byte0]: 54
4624 12:26:45.371605 [Byte1]: 46
4625 12:26:45.372085
4626 12:26:45.374730 Final RX Vref Byte 0 = 54 to rank0
4627 12:26:45.378105 Final RX Vref Byte 1 = 46 to rank0
4628 12:26:45.381013 Final RX Vref Byte 0 = 54 to rank1
4629 12:26:45.384835 Final RX Vref Byte 1 = 46 to rank1==
4630 12:26:45.387749 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 12:26:45.394284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 12:26:45.394713 ==
4633 12:26:45.395115 DQS Delay:
4634 12:26:45.395432 DQS0 = 0, DQS1 = 0
4635 12:26:45.397912 DQM Delay:
4636 12:26:45.398335 DQM0 = 38, DQM1 = 29
4637 12:26:45.401076 DQ Delay:
4638 12:26:45.404275 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4639 12:26:45.407412 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4640 12:26:45.410917 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4641 12:26:45.414037 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =40
4642 12:26:45.414458
4643 12:26:45.414789
4644 12:26:45.421015 [DQSOSCAuto] RK0, (LSB)MR18= 0x2230, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4645 12:26:45.423962 CH1 RK0: MR19=808, MR18=2230
4646 12:26:45.430278 CH1_RK0: MR19=0x808, MR18=0x2230, DQSOSC=400, MR23=63, INC=163, DEC=109
4647 12:26:45.430702
4648 12:26:45.434112 ----->DramcWriteLeveling(PI) begin...
4649 12:26:45.434647 ==
4650 12:26:45.437306 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 12:26:45.440643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 12:26:45.441102 ==
4653 12:26:45.443634 Write leveling (Byte 0): 29 => 29
4654 12:26:45.447367 Write leveling (Byte 1): 28 => 28
4655 12:26:45.450525 DramcWriteLeveling(PI) end<-----
4656 12:26:45.451119
4657 12:26:45.451597 ==
4658 12:26:45.453804 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 12:26:45.456984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 12:26:45.460048 ==
4661 12:26:45.460471 [Gating] SW mode calibration
4662 12:26:45.470116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4663 12:26:45.473474 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4664 12:26:45.476351 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 12:26:45.483574 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 12:26:45.486360 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 12:26:45.489959 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 0)
4668 12:26:45.496169 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4669 12:26:45.499925 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 12:26:45.502949 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 12:26:45.509659 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 12:26:45.512678 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 12:26:45.515920 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 12:26:45.522574 0 10 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
4675 12:26:45.526352 0 10 12 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (1 1)
4676 12:26:45.529560 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4677 12:26:45.535928 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 12:26:45.538992 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:26:45.542701 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 12:26:45.549089 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 12:26:45.552357 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 12:26:45.556124 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 12:26:45.562488 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4684 12:26:45.565631 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:26:45.568926 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:26:45.575552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:26:45.578516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:26:45.581897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:26:45.588606 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:26:45.592134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:26:45.595668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:26:45.601552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:26:45.605358 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:26:45.608408 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:26:45.615331 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:26:45.618512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:26:45.621506 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:26:45.628301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:26:45.631522 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4700 12:26:45.634474 Total UI for P1: 0, mck2ui 16
4701 12:26:45.638263 best dqsien dly found for B0: ( 0, 13, 10)
4702 12:26:45.641463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 12:26:45.644606 Total UI for P1: 0, mck2ui 16
4704 12:26:45.648333 best dqsien dly found for B1: ( 0, 13, 14)
4705 12:26:45.651550 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4706 12:26:45.657612 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4707 12:26:45.658033
4708 12:26:45.661420 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4709 12:26:45.664620 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4710 12:26:45.667606 [Gating] SW calibration Done
4711 12:26:45.668032 ==
4712 12:26:45.671360 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 12:26:45.674067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 12:26:45.674629 ==
4715 12:26:45.677303 RX Vref Scan: 0
4716 12:26:45.677720
4717 12:26:45.678052 RX Vref 0 -> 0, step: 1
4718 12:26:45.678379
4719 12:26:45.680681 RX Delay -230 -> 252, step: 16
4720 12:26:45.684021 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4721 12:26:45.690673 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4722 12:26:45.694490 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4723 12:26:45.697346 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4724 12:26:45.701003 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4725 12:26:45.707129 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4726 12:26:45.710875 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4727 12:26:45.714119 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4728 12:26:45.716923 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4729 12:26:45.720540 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4730 12:26:45.727362 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4731 12:26:45.730346 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4732 12:26:45.733800 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4733 12:26:45.737131 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4734 12:26:45.743952 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4735 12:26:45.747022 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4736 12:26:45.747641 ==
4737 12:26:45.750090 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 12:26:45.753442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 12:26:45.753866 ==
4740 12:26:45.756538 DQS Delay:
4741 12:26:45.756957 DQS0 = 0, DQS1 = 0
4742 12:26:45.760169 DQM Delay:
4743 12:26:45.760588 DQM0 = 35, DQM1 = 27
4744 12:26:45.760923 DQ Delay:
4745 12:26:45.763369 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4746 12:26:45.766427 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4747 12:26:45.769694 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4748 12:26:45.772766 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4749 12:26:45.773180
4750 12:26:45.773538
4751 12:26:45.776083 ==
4752 12:26:45.779762 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 12:26:45.782633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 12:26:45.782923 ==
4755 12:26:45.783085
4756 12:26:45.783285
4757 12:26:45.786061 TX Vref Scan disable
4758 12:26:45.786281 == TX Byte 0 ==
4759 12:26:45.792484 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4760 12:26:45.796150 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4761 12:26:45.796352 == TX Byte 1 ==
4762 12:26:45.802776 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4763 12:26:45.805990 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4764 12:26:45.806192 ==
4765 12:26:45.809442 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 12:26:45.812461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 12:26:45.812667 ==
4768 12:26:45.812844
4769 12:26:45.813012
4770 12:26:45.816105 TX Vref Scan disable
4771 12:26:45.819298 == TX Byte 0 ==
4772 12:26:45.822399 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4773 12:26:45.825990 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4774 12:26:45.829169 == TX Byte 1 ==
4775 12:26:45.832435 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4776 12:26:45.835498 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4777 12:26:45.839223
4778 12:26:45.839574 [DATLAT]
4779 12:26:45.839821 Freq=600, CH1 RK1
4780 12:26:45.840048
4781 12:26:45.842109 DATLAT Default: 0x9
4782 12:26:45.842409 0, 0xFFFF, sum = 0
4783 12:26:45.845942 1, 0xFFFF, sum = 0
4784 12:26:45.846250 2, 0xFFFF, sum = 0
4785 12:26:45.849117 3, 0xFFFF, sum = 0
4786 12:26:45.849422 4, 0xFFFF, sum = 0
4787 12:26:45.852342 5, 0xFFFF, sum = 0
4788 12:26:45.855545 6, 0xFFFF, sum = 0
4789 12:26:45.855851 7, 0xFFFF, sum = 0
4790 12:26:45.856094 8, 0x0, sum = 1
4791 12:26:45.858742 9, 0x0, sum = 2
4792 12:26:45.859184 10, 0x0, sum = 3
4793 12:26:45.862578 11, 0x0, sum = 4
4794 12:26:45.863054 best_step = 9
4795 12:26:45.863375
4796 12:26:45.863666 ==
4797 12:26:45.865670 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 12:26:45.872472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 12:26:45.872863 ==
4800 12:26:45.873172 RX Vref Scan: 0
4801 12:26:45.873460
4802 12:26:45.875594 RX Vref 0 -> 0, step: 1
4803 12:26:45.875986
4804 12:26:45.878630 RX Delay -195 -> 252, step: 8
4805 12:26:45.881871 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4806 12:26:45.888908 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4807 12:26:45.892301 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4808 12:26:45.895153 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4809 12:26:45.898799 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4810 12:26:45.905544 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4811 12:26:45.908944 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4812 12:26:45.912159 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4813 12:26:45.915101 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4814 12:26:45.918574 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4815 12:26:45.924966 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4816 12:26:45.928814 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4817 12:26:45.931948 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4818 12:26:45.935053 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4819 12:26:45.941980 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4820 12:26:45.945138 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4821 12:26:45.945530 ==
4822 12:26:45.948208 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 12:26:45.951817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 12:26:45.952208 ==
4825 12:26:45.955035 DQS Delay:
4826 12:26:45.955422 DQS0 = 0, DQS1 = 0
4827 12:26:45.958122 DQM Delay:
4828 12:26:45.958511 DQM0 = 35, DQM1 = 31
4829 12:26:45.958821 DQ Delay:
4830 12:26:45.961365 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4831 12:26:45.965159 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =28
4832 12:26:45.968315 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4833 12:26:45.971302 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4834 12:26:45.971692
4835 12:26:45.972001
4836 12:26:45.981408 [DQSOSCAuto] RK1, (LSB)MR18= 0x3556, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4837 12:26:45.984540 CH1 RK1: MR19=808, MR18=3556
4838 12:26:45.991436 CH1_RK1: MR19=0x808, MR18=0x3556, DQSOSC=393, MR23=63, INC=169, DEC=113
4839 12:26:45.991830 [RxdqsGatingPostProcess] freq 600
4840 12:26:45.997727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4841 12:26:46.000924 Pre-setting of DQS Precalculation
4842 12:26:46.004141 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4843 12:26:46.013926 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4844 12:26:46.020512 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4845 12:26:46.020906
4846 12:26:46.021213
4847 12:26:46.023988 [Calibration Summary] 1200 Mbps
4848 12:26:46.024451 CH 0, Rank 0
4849 12:26:46.027363 SW Impedance : PASS
4850 12:26:46.030347 DUTY Scan : NO K
4851 12:26:46.031003 ZQ Calibration : PASS
4852 12:26:46.033976 Jitter Meter : NO K
4853 12:26:46.037152 CBT Training : PASS
4854 12:26:46.037540 Write leveling : PASS
4855 12:26:46.040231 RX DQS gating : PASS
4856 12:26:46.040623 RX DQ/DQS(RDDQC) : PASS
4857 12:26:46.044017 TX DQ/DQS : PASS
4858 12:26:46.046972 RX DATLAT : PASS
4859 12:26:46.047406 RX DQ/DQS(Engine): PASS
4860 12:26:46.050076 TX OE : NO K
4861 12:26:46.050466 All Pass.
4862 12:26:46.050778
4863 12:26:46.053132 CH 0, Rank 1
4864 12:26:46.053521 SW Impedance : PASS
4865 12:26:46.056889 DUTY Scan : NO K
4866 12:26:46.059907 ZQ Calibration : PASS
4867 12:26:46.060299 Jitter Meter : NO K
4868 12:26:46.063696 CBT Training : PASS
4869 12:26:46.066722 Write leveling : PASS
4870 12:26:46.067147 RX DQS gating : PASS
4871 12:26:46.069977 RX DQ/DQS(RDDQC) : PASS
4872 12:26:46.073117 TX DQ/DQS : PASS
4873 12:26:46.073627 RX DATLAT : PASS
4874 12:26:46.076369 RX DQ/DQS(Engine): PASS
4875 12:26:46.080066 TX OE : NO K
4876 12:26:46.080457 All Pass.
4877 12:26:46.080768
4878 12:26:46.081055 CH 1, Rank 0
4879 12:26:46.083198 SW Impedance : PASS
4880 12:26:46.086332 DUTY Scan : NO K
4881 12:26:46.086730 ZQ Calibration : PASS
4882 12:26:46.089962 Jitter Meter : NO K
4883 12:26:46.093050 CBT Training : PASS
4884 12:26:46.093563 Write leveling : PASS
4885 12:26:46.096292 RX DQS gating : PASS
4886 12:26:46.099773 RX DQ/DQS(RDDQC) : PASS
4887 12:26:46.100301 TX DQ/DQS : PASS
4888 12:26:46.102938 RX DATLAT : PASS
4889 12:26:46.106543 RX DQ/DQS(Engine): PASS
4890 12:26:46.106979 TX OE : NO K
4891 12:26:46.107295 All Pass.
4892 12:26:46.110193
4893 12:26:46.110589 CH 1, Rank 1
4894 12:26:46.113113 SW Impedance : PASS
4895 12:26:46.113539 DUTY Scan : NO K
4896 12:26:46.116468 ZQ Calibration : PASS
4897 12:26:46.119518 Jitter Meter : NO K
4898 12:26:46.119942 CBT Training : PASS
4899 12:26:46.122934 Write leveling : PASS
4900 12:26:46.123565 RX DQS gating : PASS
4901 12:26:46.126432 RX DQ/DQS(RDDQC) : PASS
4902 12:26:46.129334 TX DQ/DQS : PASS
4903 12:26:46.129762 RX DATLAT : PASS
4904 12:26:46.132917 RX DQ/DQS(Engine): PASS
4905 12:26:46.135732 TX OE : NO K
4906 12:26:46.136290 All Pass.
4907 12:26:46.136848
4908 12:26:46.139251 DramC Write-DBI off
4909 12:26:46.139756 PER_BANK_REFRESH: Hybrid Mode
4910 12:26:46.142337 TX_TRACKING: ON
4911 12:26:46.152677 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4912 12:26:46.155952 [FAST_K] Save calibration result to emmc
4913 12:26:46.158924 dramc_set_vcore_voltage set vcore to 662500
4914 12:26:46.159350 Read voltage for 933, 3
4915 12:26:46.162641 Vio18 = 0
4916 12:26:46.163121 Vcore = 662500
4917 12:26:46.163460 Vdram = 0
4918 12:26:46.165503 Vddq = 0
4919 12:26:46.165924 Vmddr = 0
4920 12:26:46.172180 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4921 12:26:46.175441 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4922 12:26:46.178634 MEM_TYPE=3, freq_sel=17
4923 12:26:46.181734 sv_algorithm_assistance_LP4_1600
4924 12:26:46.184868 ============ PULL DRAM RESETB DOWN ============
4925 12:26:46.188549 ========== PULL DRAM RESETB DOWN end =========
4926 12:26:46.194948 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4927 12:26:46.198204 ===================================
4928 12:26:46.201391 LPDDR4 DRAM CONFIGURATION
4929 12:26:46.204478 ===================================
4930 12:26:46.205055 EX_ROW_EN[0] = 0x0
4931 12:26:46.208407 EX_ROW_EN[1] = 0x0
4932 12:26:46.208982 LP4Y_EN = 0x0
4933 12:26:46.211537 WORK_FSP = 0x0
4934 12:26:46.212117 WL = 0x3
4935 12:26:46.214525 RL = 0x3
4936 12:26:46.215151 BL = 0x2
4937 12:26:46.218503 RPST = 0x0
4938 12:26:46.219246 RD_PRE = 0x0
4939 12:26:46.221236 WR_PRE = 0x1
4940 12:26:46.221904 WR_PST = 0x0
4941 12:26:46.224829 DBI_WR = 0x0
4942 12:26:46.225255 DBI_RD = 0x0
4943 12:26:46.228110 OTF = 0x1
4944 12:26:46.231017 ===================================
4945 12:26:46.234529 ===================================
4946 12:26:46.235006 ANA top config
4947 12:26:46.238034 ===================================
4948 12:26:46.241412 DLL_ASYNC_EN = 0
4949 12:26:46.244441 ALL_SLAVE_EN = 1
4950 12:26:46.248069 NEW_RANK_MODE = 1
4951 12:26:46.248608 DLL_IDLE_MODE = 1
4952 12:26:46.251388 LP45_APHY_COMB_EN = 1
4953 12:26:46.254380 TX_ODT_DIS = 1
4954 12:26:46.257259 NEW_8X_MODE = 1
4955 12:26:46.261191 ===================================
4956 12:26:46.264256 ===================================
4957 12:26:46.267338 data_rate = 1866
4958 12:26:46.270937 CKR = 1
4959 12:26:46.271401 DQ_P2S_RATIO = 8
4960 12:26:46.274024 ===================================
4961 12:26:46.277637 CA_P2S_RATIO = 8
4962 12:26:46.280835 DQ_CA_OPEN = 0
4963 12:26:46.284057 DQ_SEMI_OPEN = 0
4964 12:26:46.287314 CA_SEMI_OPEN = 0
4965 12:26:46.290888 CA_FULL_RATE = 0
4966 12:26:46.291437 DQ_CKDIV4_EN = 1
4967 12:26:46.294010 CA_CKDIV4_EN = 1
4968 12:26:46.297189 CA_PREDIV_EN = 0
4969 12:26:46.300351 PH8_DLY = 0
4970 12:26:46.304082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4971 12:26:46.307308 DQ_AAMCK_DIV = 4
4972 12:26:46.307769 CA_AAMCK_DIV = 4
4973 12:26:46.310483 CA_ADMCK_DIV = 4
4974 12:26:46.313524 DQ_TRACK_CA_EN = 0
4975 12:26:46.317276 CA_PICK = 933
4976 12:26:46.320217 CA_MCKIO = 933
4977 12:26:46.323380 MCKIO_SEMI = 0
4978 12:26:46.327111 PLL_FREQ = 3732
4979 12:26:46.330438 DQ_UI_PI_RATIO = 32
4980 12:26:46.330946 CA_UI_PI_RATIO = 0
4981 12:26:46.333719 ===================================
4982 12:26:46.336558 ===================================
4983 12:26:46.339901 memory_type:LPDDR4
4984 12:26:46.343461 GP_NUM : 10
4985 12:26:46.344140 SRAM_EN : 1
4986 12:26:46.346276 MD32_EN : 0
4987 12:26:46.349949 ===================================
4988 12:26:46.353530 [ANA_INIT] >>>>>>>>>>>>>>
4989 12:26:46.356344 <<<<<< [CONFIGURE PHASE]: ANA_TX
4990 12:26:46.359906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4991 12:26:46.362893 ===================================
4992 12:26:46.363317 data_rate = 1866,PCW = 0X8f00
4993 12:26:46.366899 ===================================
4994 12:26:46.369703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4995 12:26:46.376689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 12:26:46.382863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 12:26:46.386365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4998 12:26:46.389594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4999 12:26:46.392784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5000 12:26:46.395981 [ANA_INIT] flow start
5001 12:26:46.399660 [ANA_INIT] PLL >>>>>>>>
5002 12:26:46.400299 [ANA_INIT] PLL <<<<<<<<
5003 12:26:46.402932 [ANA_INIT] MIDPI >>>>>>>>
5004 12:26:46.405933 [ANA_INIT] MIDPI <<<<<<<<
5005 12:26:46.406559 [ANA_INIT] DLL >>>>>>>>
5006 12:26:46.409012 [ANA_INIT] flow end
5007 12:26:46.412886 ============ LP4 DIFF to SE enter ============
5008 12:26:46.415825 ============ LP4 DIFF to SE exit ============
5009 12:26:46.419104 [ANA_INIT] <<<<<<<<<<<<<
5010 12:26:46.422603 [Flow] Enable top DCM control >>>>>
5011 12:26:46.425728 [Flow] Enable top DCM control <<<<<
5012 12:26:46.429028 Enable DLL master slave shuffle
5013 12:26:46.435987 ==============================================================
5014 12:26:46.436410 Gating Mode config
5015 12:26:46.442509 ==============================================================
5016 12:26:46.445816 Config description:
5017 12:26:46.452333 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5018 12:26:46.458801 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5019 12:26:46.465162 SELPH_MODE 0: By rank 1: By Phase
5020 12:26:46.471800 ==============================================================
5021 12:26:46.474881 GAT_TRACK_EN = 1
5022 12:26:46.475315 RX_GATING_MODE = 2
5023 12:26:46.478607 RX_GATING_TRACK_MODE = 2
5024 12:26:46.481801 SELPH_MODE = 1
5025 12:26:46.484959 PICG_EARLY_EN = 1
5026 12:26:46.488096 VALID_LAT_VALUE = 1
5027 12:26:46.494893 ==============================================================
5028 12:26:46.498083 Enter into Gating configuration >>>>
5029 12:26:46.501619 Exit from Gating configuration <<<<
5030 12:26:46.504748 Enter into DVFS_PRE_config >>>>>
5031 12:26:46.514959 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5032 12:26:46.518012 Exit from DVFS_PRE_config <<<<<
5033 12:26:46.521149 Enter into PICG configuration >>>>
5034 12:26:46.524752 Exit from PICG configuration <<<<
5035 12:26:46.527818 [RX_INPUT] configuration >>>>>
5036 12:26:46.531190 [RX_INPUT] configuration <<<<<
5037 12:26:46.534825 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5038 12:26:46.540944 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5039 12:26:46.547804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 12:26:46.553910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 12:26:46.557364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 12:26:46.563785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 12:26:46.570933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5044 12:26:46.573753 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5045 12:26:46.577314 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5046 12:26:46.580385 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5047 12:26:46.587199 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5048 12:26:46.590238 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 12:26:46.593941 ===================================
5050 12:26:46.597011 LPDDR4 DRAM CONFIGURATION
5051 12:26:46.600418 ===================================
5052 12:26:46.600927 EX_ROW_EN[0] = 0x0
5053 12:26:46.603536 EX_ROW_EN[1] = 0x0
5054 12:26:46.603990 LP4Y_EN = 0x0
5055 12:26:46.606719 WORK_FSP = 0x0
5056 12:26:46.607320 WL = 0x3
5057 12:26:46.609958 RL = 0x3
5058 12:26:46.610413 BL = 0x2
5059 12:26:46.613625 RPST = 0x0
5060 12:26:46.616776 RD_PRE = 0x0
5061 12:26:46.617347 WR_PRE = 0x1
5062 12:26:46.619976 WR_PST = 0x0
5063 12:26:46.620439 DBI_WR = 0x0
5064 12:26:46.623221 DBI_RD = 0x0
5065 12:26:46.623870 OTF = 0x1
5066 12:26:46.626356 ===================================
5067 12:26:46.629916 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5068 12:26:46.636756 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5069 12:26:46.639953 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5070 12:26:46.643016 ===================================
5071 12:26:46.646083 LPDDR4 DRAM CONFIGURATION
5072 12:26:46.649809 ===================================
5073 12:26:46.650233 EX_ROW_EN[0] = 0x10
5074 12:26:46.652928 EX_ROW_EN[1] = 0x0
5075 12:26:46.653354 LP4Y_EN = 0x0
5076 12:26:46.656158 WORK_FSP = 0x0
5077 12:26:46.656587 WL = 0x3
5078 12:26:46.659939 RL = 0x3
5079 12:26:46.660364 BL = 0x2
5080 12:26:46.662784 RPST = 0x0
5081 12:26:46.666049 RD_PRE = 0x0
5082 12:26:46.666480 WR_PRE = 0x1
5083 12:26:46.669210 WR_PST = 0x0
5084 12:26:46.669645 DBI_WR = 0x0
5085 12:26:46.672599 DBI_RD = 0x0
5086 12:26:46.673029 OTF = 0x1
5087 12:26:46.676259 ===================================
5088 12:26:46.682754 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5089 12:26:46.686274 nWR fixed to 30
5090 12:26:46.690229 [ModeRegInit_LP4] CH0 RK0
5091 12:26:46.690821 [ModeRegInit_LP4] CH0 RK1
5092 12:26:46.693446 [ModeRegInit_LP4] CH1 RK0
5093 12:26:46.696322 [ModeRegInit_LP4] CH1 RK1
5094 12:26:46.696750 match AC timing 9
5095 12:26:46.702908 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5096 12:26:46.706005 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5097 12:26:46.709507 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5098 12:26:46.715858 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5099 12:26:46.719137 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5100 12:26:46.719564 ==
5101 12:26:46.723112 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 12:26:46.726107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 12:26:46.726539 ==
5104 12:26:46.732461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 12:26:46.739298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5106 12:26:46.742336 [CA 0] Center 38 (7~69) winsize 63
5107 12:26:46.746154 [CA 1] Center 38 (8~69) winsize 62
5108 12:26:46.749152 [CA 2] Center 35 (5~66) winsize 62
5109 12:26:46.752300 [CA 3] Center 34 (4~65) winsize 62
5110 12:26:46.755522 [CA 4] Center 34 (4~65) winsize 62
5111 12:26:46.758620 [CA 5] Center 33 (3~64) winsize 62
5112 12:26:46.759162
5113 12:26:46.762497 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5114 12:26:46.763094
5115 12:26:46.765620 [CATrainingPosCal] consider 1 rank data
5116 12:26:46.769034 u2DelayCellTimex100 = 270/100 ps
5117 12:26:46.771975 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5118 12:26:46.775608 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5119 12:26:46.778569 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5120 12:26:46.785487 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5121 12:26:46.788412 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5122 12:26:46.791942 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5123 12:26:46.792376
5124 12:26:46.795021 CA PerBit enable=1, Macro0, CA PI delay=33
5125 12:26:46.795457
5126 12:26:46.798748 [CBTSetCACLKResult] CA Dly = 33
5127 12:26:46.799240 CS Dly: 6 (0~37)
5128 12:26:46.799588 ==
5129 12:26:46.801675 Dram Type= 6, Freq= 0, CH_0, rank 1
5130 12:26:46.808213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 12:26:46.808785 ==
5132 12:26:46.811929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5133 12:26:46.818112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5134 12:26:46.821430 [CA 0] Center 38 (8~69) winsize 62
5135 12:26:46.825105 [CA 1] Center 38 (7~69) winsize 63
5136 12:26:46.828451 [CA 2] Center 35 (5~66) winsize 62
5137 12:26:46.831519 [CA 3] Center 35 (5~66) winsize 62
5138 12:26:46.834554 [CA 4] Center 34 (4~65) winsize 62
5139 12:26:46.838265 [CA 5] Center 34 (4~64) winsize 61
5140 12:26:46.838664
5141 12:26:46.841319 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5142 12:26:46.841745
5143 12:26:46.844468 [CATrainingPosCal] consider 2 rank data
5144 12:26:46.847601 u2DelayCellTimex100 = 270/100 ps
5145 12:26:46.851380 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5146 12:26:46.857707 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5147 12:26:46.860924 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5148 12:26:46.864056 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5149 12:26:46.867225 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5150 12:26:46.870913 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5151 12:26:46.871224
5152 12:26:46.873938 CA PerBit enable=1, Macro0, CA PI delay=34
5153 12:26:46.874322
5154 12:26:46.877679 [CBTSetCACLKResult] CA Dly = 34
5155 12:26:46.880800 CS Dly: 7 (0~39)
5156 12:26:46.881105
5157 12:26:46.883746 ----->DramcWriteLeveling(PI) begin...
5158 12:26:46.884060 ==
5159 12:26:46.887606 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 12:26:46.890738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 12:26:46.891108 ==
5162 12:26:46.893750 Write leveling (Byte 0): 31 => 31
5163 12:26:46.897154 Write leveling (Byte 1): 31 => 31
5164 12:26:46.900628 DramcWriteLeveling(PI) end<-----
5165 12:26:46.901024
5166 12:26:46.901362 ==
5167 12:26:46.903771 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 12:26:46.907589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 12:26:46.907893 ==
5170 12:26:46.910560 [Gating] SW mode calibration
5171 12:26:46.916924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5172 12:26:46.923906 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5173 12:26:46.927062 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5174 12:26:46.929995 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5175 12:26:46.937048 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 12:26:46.940195 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 12:26:46.943192 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 12:26:46.950020 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 12:26:46.953271 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 12:26:46.956404 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5181 12:26:46.963243 0 15 0 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
5182 12:26:46.966410 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5183 12:26:46.969581 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 12:26:46.976344 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 12:26:46.979374 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 12:26:46.986012 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 12:26:46.989447 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 12:26:46.992860 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 12:26:46.999232 1 0 0 | B1->B0 | 2928 3939 | 1 0 | (0 0) (0 0)
5190 12:26:47.002250 1 0 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5191 12:26:47.006099 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 12:26:47.012746 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 12:26:47.015829 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 12:26:47.019440 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 12:26:47.025443 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 12:26:47.029033 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 12:26:47.032190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5198 12:26:47.039065 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:26:47.042187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:26:47.045169 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:26:47.051899 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:26:47.055056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:26:47.058789 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:26:47.065095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:26:47.068193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:26:47.071957 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:26:47.078219 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:26:47.081343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:26:47.084991 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:26:47.091460 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:26:47.094825 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:26:47.097999 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5213 12:26:47.104542 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5214 12:26:47.104855 Total UI for P1: 0, mck2ui 16
5215 12:26:47.107759 best dqsien dly found for B0: ( 1, 2, 28)
5216 12:26:47.114852 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5217 12:26:47.117653 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 12:26:47.121369 Total UI for P1: 0, mck2ui 16
5219 12:26:47.124430 best dqsien dly found for B1: ( 1, 3, 4)
5220 12:26:47.128303 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5221 12:26:47.131333 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5222 12:26:47.131639
5223 12:26:47.134214 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5224 12:26:47.141110 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5225 12:26:47.141419 [Gating] SW calibration Done
5226 12:26:47.141668 ==
5227 12:26:47.144230 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 12:26:47.151105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 12:26:47.151413 ==
5230 12:26:47.151658 RX Vref Scan: 0
5231 12:26:47.151888
5232 12:26:47.154573 RX Vref 0 -> 0, step: 1
5233 12:26:47.154964
5234 12:26:47.157801 RX Delay -80 -> 252, step: 8
5235 12:26:47.161046 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5236 12:26:47.164121 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5237 12:26:47.167273 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5238 12:26:47.171187 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5239 12:26:47.177410 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5240 12:26:47.180578 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5241 12:26:47.184213 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5242 12:26:47.187153 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5243 12:26:47.190898 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5244 12:26:47.197051 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5245 12:26:47.200679 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5246 12:26:47.203711 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5247 12:26:47.206809 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5248 12:26:47.210540 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5249 12:26:47.217153 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5250 12:26:47.220029 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5251 12:26:47.220332 ==
5252 12:26:47.223599 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 12:26:47.226670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 12:26:47.227025 ==
5255 12:26:47.229938 DQS Delay:
5256 12:26:47.230278 DQS0 = 0, DQS1 = 0
5257 12:26:47.230668 DQM Delay:
5258 12:26:47.233655 DQM0 = 94, DQM1 = 83
5259 12:26:47.234012 DQ Delay:
5260 12:26:47.236764 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5261 12:26:47.239971 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5262 12:26:47.243691 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5263 12:26:47.246754 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5264 12:26:47.247157
5265 12:26:47.247518
5266 12:26:47.247786 ==
5267 12:26:47.249955 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 12:26:47.256358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 12:26:47.256758 ==
5270 12:26:47.257119
5271 12:26:47.257463
5272 12:26:47.257801 TX Vref Scan disable
5273 12:26:47.260263 == TX Byte 0 ==
5274 12:26:47.263372 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5275 12:26:47.269827 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5276 12:26:47.270158 == TX Byte 1 ==
5277 12:26:47.273532 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5278 12:26:47.279957 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5279 12:26:47.280334 ==
5280 12:26:47.283071 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 12:26:47.286878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 12:26:47.287484 ==
5283 12:26:47.288014
5284 12:26:47.288524
5285 12:26:47.290038 TX Vref Scan disable
5286 12:26:47.293207 == TX Byte 0 ==
5287 12:26:47.296309 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5288 12:26:47.299401 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5289 12:26:47.302801 == TX Byte 1 ==
5290 12:26:47.306423 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5291 12:26:47.309360 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5292 12:26:47.309746
5293 12:26:47.310050 [DATLAT]
5294 12:26:47.313034 Freq=933, CH0 RK0
5295 12:26:47.313571
5296 12:26:47.316040 DATLAT Default: 0xd
5297 12:26:47.316520 0, 0xFFFF, sum = 0
5298 12:26:47.319650 1, 0xFFFF, sum = 0
5299 12:26:47.320139 2, 0xFFFF, sum = 0
5300 12:26:47.322358 3, 0xFFFF, sum = 0
5301 12:26:47.322903 4, 0xFFFF, sum = 0
5302 12:26:47.326131 5, 0xFFFF, sum = 0
5303 12:26:47.326709 6, 0xFFFF, sum = 0
5304 12:26:47.329554 7, 0xFFFF, sum = 0
5305 12:26:47.329994 8, 0xFFFF, sum = 0
5306 12:26:47.332541 9, 0xFFFF, sum = 0
5307 12:26:47.332942 10, 0x0, sum = 1
5308 12:26:47.336109 11, 0x0, sum = 2
5309 12:26:47.336642 12, 0x0, sum = 3
5310 12:26:47.339751 13, 0x0, sum = 4
5311 12:26:47.340176 best_step = 11
5312 12:26:47.340504
5313 12:26:47.340940 ==
5314 12:26:47.342710 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 12:26:47.348876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 12:26:47.349538 ==
5317 12:26:47.350136 RX Vref Scan: 1
5318 12:26:47.350463
5319 12:26:47.351919 RX Vref 0 -> 0, step: 1
5320 12:26:47.352314
5321 12:26:47.355535 RX Delay -69 -> 252, step: 4
5322 12:26:47.356106
5323 12:26:47.358996 Set Vref, RX VrefLevel [Byte0]: 62
5324 12:26:47.362304 [Byte1]: 53
5325 12:26:47.362910
5326 12:26:47.365237 Final RX Vref Byte 0 = 62 to rank0
5327 12:26:47.368477 Final RX Vref Byte 1 = 53 to rank0
5328 12:26:47.371821 Final RX Vref Byte 0 = 62 to rank1
5329 12:26:47.375432 Final RX Vref Byte 1 = 53 to rank1==
5330 12:26:47.378705 Dram Type= 6, Freq= 0, CH_0, rank 0
5331 12:26:47.381684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 12:26:47.382225 ==
5333 12:26:47.385164 DQS Delay:
5334 12:26:47.385641 DQS0 = 0, DQS1 = 0
5335 12:26:47.388159 DQM Delay:
5336 12:26:47.388551 DQM0 = 95, DQM1 = 83
5337 12:26:47.388861 DQ Delay:
5338 12:26:47.391421 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5339 12:26:47.394454 DQ4 =96, DQ5 =86, DQ6 =102, DQ7 =106
5340 12:26:47.398205 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =76
5341 12:26:47.401229 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5342 12:26:47.401753
5343 12:26:47.404507
5344 12:26:47.411670 [DQSOSCAuto] RK0, (LSB)MR18= 0x100f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5345 12:26:47.414510 CH0 RK0: MR19=505, MR18=100F
5346 12:26:47.421293 CH0_RK0: MR19=0x505, MR18=0x100F, DQSOSC=416, MR23=63, INC=62, DEC=41
5347 12:26:47.421711
5348 12:26:47.424486 ----->DramcWriteLeveling(PI) begin...
5349 12:26:47.424965 ==
5350 12:26:47.428211 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 12:26:47.431228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 12:26:47.431614 ==
5353 12:26:47.434727 Write leveling (Byte 0): 33 => 33
5354 12:26:47.437906 Write leveling (Byte 1): 30 => 30
5355 12:26:47.441016 DramcWriteLeveling(PI) end<-----
5356 12:26:47.441416
5357 12:26:47.441720 ==
5358 12:26:47.444296 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 12:26:47.448070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 12:26:47.448491 ==
5361 12:26:47.451193 [Gating] SW mode calibration
5362 12:26:47.457415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5363 12:26:47.464272 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5364 12:26:47.467328 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5365 12:26:47.470966 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 12:26:47.477277 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 12:26:47.480517 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 12:26:47.484509 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 12:26:47.490888 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 12:26:47.494154 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5371 12:26:47.497197 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5372 12:26:47.504104 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5373 12:26:47.507416 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5374 12:26:47.510595 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 12:26:47.517435 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 12:26:47.520612 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 12:26:47.523482 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 12:26:47.530363 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 12:26:47.533631 0 15 28 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
5380 12:26:47.537031 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5381 12:26:47.543667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:26:47.546927 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 12:26:47.550056 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 12:26:47.556910 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 12:26:47.559993 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 12:26:47.563306 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 12:26:47.569596 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5388 12:26:47.573277 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5389 12:26:47.576185 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:26:47.583151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:26:47.586382 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:26:47.589484 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:26:47.595792 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:26:47.599528 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:26:47.602641 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:26:47.608807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:26:47.612065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:26:47.619082 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:26:47.622222 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:26:47.625184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:26:47.631976 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:26:47.635542 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5403 12:26:47.638577 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5404 12:26:47.645198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5405 12:26:47.645650 Total UI for P1: 0, mck2ui 16
5406 12:26:47.651834 best dqsien dly found for B0: ( 1, 2, 26)
5407 12:26:47.654888 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 12:26:47.658571 Total UI for P1: 0, mck2ui 16
5409 12:26:47.661744 best dqsien dly found for B1: ( 1, 2, 30)
5410 12:26:47.664877 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5411 12:26:47.668049 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5412 12:26:47.668474
5413 12:26:47.671678 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5414 12:26:47.674909 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5415 12:26:47.678332 [Gating] SW calibration Done
5416 12:26:47.678757 ==
5417 12:26:47.681465 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 12:26:47.684509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 12:26:47.688323 ==
5420 12:26:47.688747 RX Vref Scan: 0
5421 12:26:47.689082
5422 12:26:47.691338 RX Vref 0 -> 0, step: 1
5423 12:26:47.691762
5424 12:26:47.694608 RX Delay -80 -> 252, step: 8
5425 12:26:47.697783 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5426 12:26:47.700985 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5427 12:26:47.704659 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5428 12:26:47.707778 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5429 12:26:47.710779 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5430 12:26:47.717647 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5431 12:26:47.720844 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5432 12:26:47.723930 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5433 12:26:47.727633 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5434 12:26:47.730754 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5435 12:26:47.737472 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5436 12:26:47.740694 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5437 12:26:47.744169 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5438 12:26:47.747119 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5439 12:26:47.753526 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5440 12:26:47.757124 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5441 12:26:47.757549 ==
5442 12:26:47.760167 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 12:26:47.763920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 12:26:47.764344 ==
5445 12:26:47.764679 DQS Delay:
5446 12:26:47.766886 DQS0 = 0, DQS1 = 0
5447 12:26:47.767304 DQM Delay:
5448 12:26:47.770144 DQM0 = 94, DQM1 = 83
5449 12:26:47.770563 DQ Delay:
5450 12:26:47.773881 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5451 12:26:47.776957 DQ4 =91, DQ5 =79, DQ6 =107, DQ7 =107
5452 12:26:47.780089 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5453 12:26:47.783103 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5454 12:26:47.783562
5455 12:26:47.783901
5456 12:26:47.784212 ==
5457 12:26:47.786458 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 12:26:47.793330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 12:26:47.793756 ==
5460 12:26:47.794093
5461 12:26:47.794402
5462 12:26:47.794704 TX Vref Scan disable
5463 12:26:47.796585 == TX Byte 0 ==
5464 12:26:47.799925 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5465 12:26:47.806720 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5466 12:26:47.807242 == TX Byte 1 ==
5467 12:26:47.809963 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5468 12:26:47.816641 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5469 12:26:47.817065 ==
5470 12:26:47.819929 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 12:26:47.822958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 12:26:47.823411 ==
5473 12:26:47.823784
5474 12:26:47.824130
5475 12:26:47.826147 TX Vref Scan disable
5476 12:26:47.829941 == TX Byte 0 ==
5477 12:26:47.833495 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5478 12:26:47.836422 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5479 12:26:47.839467 == TX Byte 1 ==
5480 12:26:47.842967 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5481 12:26:47.846089 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5482 12:26:47.846567
5483 12:26:47.846976 [DATLAT]
5484 12:26:47.848984 Freq=933, CH0 RK1
5485 12:26:47.849447
5486 12:26:47.852717 DATLAT Default: 0xb
5487 12:26:47.853184 0, 0xFFFF, sum = 0
5488 12:26:47.855823 1, 0xFFFF, sum = 0
5489 12:26:47.856300 2, 0xFFFF, sum = 0
5490 12:26:47.859277 3, 0xFFFF, sum = 0
5491 12:26:47.859755 4, 0xFFFF, sum = 0
5492 12:26:47.862312 5, 0xFFFF, sum = 0
5493 12:26:47.862787 6, 0xFFFF, sum = 0
5494 12:26:47.866020 7, 0xFFFF, sum = 0
5495 12:26:47.866482 8, 0xFFFF, sum = 0
5496 12:26:47.869043 9, 0xFFFF, sum = 0
5497 12:26:47.869513 10, 0x0, sum = 1
5498 12:26:47.872143 11, 0x0, sum = 2
5499 12:26:47.872616 12, 0x0, sum = 3
5500 12:26:47.875622 13, 0x0, sum = 4
5501 12:26:47.876109 best_step = 11
5502 12:26:47.876521
5503 12:26:47.876873 ==
5504 12:26:47.878665 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 12:26:47.885700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 12:26:47.886175 ==
5507 12:26:47.886548 RX Vref Scan: 0
5508 12:26:47.886936
5509 12:26:47.888968 RX Vref 0 -> 0, step: 1
5510 12:26:47.889395
5511 12:26:47.891797 RX Delay -77 -> 252, step: 4
5512 12:26:47.895383 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5513 12:26:47.898367 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5514 12:26:47.905449 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5515 12:26:47.908477 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5516 12:26:47.911776 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5517 12:26:47.915546 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5518 12:26:47.918549 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5519 12:26:47.924696 iDelay=199, Bit 7, Center 100 (7 ~ 194) 188
5520 12:26:47.928559 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5521 12:26:47.931753 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5522 12:26:47.934980 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5523 12:26:47.938101 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5524 12:26:47.944972 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5525 12:26:47.947923 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5526 12:26:47.951603 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5527 12:26:47.954647 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5528 12:26:47.955131 ==
5529 12:26:47.958178 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 12:26:47.961185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 12:26:47.964744 ==
5532 12:26:47.965172 DQS Delay:
5533 12:26:47.965510 DQS0 = 0, DQS1 = 0
5534 12:26:47.968294 DQM Delay:
5535 12:26:47.968719 DQM0 = 92, DQM1 = 84
5536 12:26:47.971250 DQ Delay:
5537 12:26:47.974381 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5538 12:26:47.977618 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =100
5539 12:26:47.981337 DQ8 =78, DQ9 =68, DQ10 =86, DQ11 =78
5540 12:26:47.984157 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
5541 12:26:47.984622
5542 12:26:47.985018
5543 12:26:47.991121 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5544 12:26:47.994116 CH0 RK1: MR19=505, MR18=2F10
5545 12:26:48.000920 CH0_RK1: MR19=0x505, MR18=0x2F10, DQSOSC=407, MR23=63, INC=65, DEC=43
5546 12:26:48.003911 [RxdqsGatingPostProcess] freq 933
5547 12:26:48.007690 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5548 12:26:48.010801 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 12:26:48.013903 best DQS1 dly(2T, 0.5T) = (0, 11)
5550 12:26:48.017029 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 12:26:48.020270 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5552 12:26:48.023823 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 12:26:48.027069 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 12:26:48.030270 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 12:26:48.033957 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 12:26:48.037140 Pre-setting of DQS Precalculation
5557 12:26:48.040277 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5558 12:26:48.043374 ==
5559 12:26:48.046546 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 12:26:48.050632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 12:26:48.051289 ==
5562 12:26:48.053585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 12:26:48.059914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5564 12:26:48.064070 [CA 0] Center 37 (7~67) winsize 61
5565 12:26:48.066961 [CA 1] Center 37 (7~67) winsize 61
5566 12:26:48.070481 [CA 2] Center 34 (5~64) winsize 60
5567 12:26:48.074130 [CA 3] Center 34 (4~64) winsize 61
5568 12:26:48.077042 [CA 4] Center 34 (5~64) winsize 60
5569 12:26:48.080192 [CA 5] Center 34 (4~64) winsize 61
5570 12:26:48.080616
5571 12:26:48.083548 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5572 12:26:48.083975
5573 12:26:48.087105 [CATrainingPosCal] consider 1 rank data
5574 12:26:48.089994 u2DelayCellTimex100 = 270/100 ps
5575 12:26:48.093228 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5576 12:26:48.100170 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5577 12:26:48.103217 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5578 12:26:48.106247 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5579 12:26:48.109953 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5580 12:26:48.113069 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 12:26:48.113495
5582 12:26:48.116362 CA PerBit enable=1, Macro0, CA PI delay=34
5583 12:26:48.116737
5584 12:26:48.119376 [CBTSetCACLKResult] CA Dly = 34
5585 12:26:48.123085 CS Dly: 6 (0~37)
5586 12:26:48.123553 ==
5587 12:26:48.126244 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 12:26:48.129813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 12:26:48.130241 ==
5590 12:26:48.136130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5591 12:26:48.139285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5592 12:26:48.143639 [CA 0] Center 37 (7~68) winsize 62
5593 12:26:48.147057 [CA 1] Center 37 (7~68) winsize 62
5594 12:26:48.150280 [CA 2] Center 35 (5~65) winsize 61
5595 12:26:48.153237 [CA 3] Center 34 (4~64) winsize 61
5596 12:26:48.157101 [CA 4] Center 35 (5~65) winsize 61
5597 12:26:48.160368 [CA 5] Center 33 (3~64) winsize 62
5598 12:26:48.160961
5599 12:26:48.163201 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5600 12:26:48.163672
5601 12:26:48.167025 [CATrainingPosCal] consider 2 rank data
5602 12:26:48.169961 u2DelayCellTimex100 = 270/100 ps
5603 12:26:48.176308 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5604 12:26:48.179668 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5605 12:26:48.183485 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5606 12:26:48.186213 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5607 12:26:48.190047 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5608 12:26:48.193092 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5609 12:26:48.193651
5610 12:26:48.196502 CA PerBit enable=1, Macro0, CA PI delay=34
5611 12:26:48.196973
5612 12:26:48.199702 [CBTSetCACLKResult] CA Dly = 34
5613 12:26:48.202694 CS Dly: 6 (0~38)
5614 12:26:48.203233
5615 12:26:48.205879 ----->DramcWriteLeveling(PI) begin...
5616 12:26:48.206443 ==
5617 12:26:48.209545 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 12:26:48.212707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 12:26:48.213151 ==
5620 12:26:48.215824 Write leveling (Byte 0): 25 => 25
5621 12:26:48.219429 Write leveling (Byte 1): 29 => 29
5622 12:26:48.222533 DramcWriteLeveling(PI) end<-----
5623 12:26:48.223001
5624 12:26:48.223344 ==
5625 12:26:48.226151 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 12:26:48.229121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 12:26:48.229553 ==
5628 12:26:48.232879 [Gating] SW mode calibration
5629 12:26:48.239070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5630 12:26:48.246024 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5631 12:26:48.248943 0 14 0 | B1->B0 | 3232 3232 | 1 0 | (1 1) (1 1)
5632 12:26:48.255270 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 12:26:48.258396 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 12:26:48.262132 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 12:26:48.268533 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 12:26:48.272012 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 12:26:48.274973 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 12:26:48.282061 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (0 1)
5639 12:26:48.285221 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5640 12:26:48.288144 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 12:26:48.294943 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 12:26:48.298376 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 12:26:48.301361 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 12:26:48.308379 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 12:26:48.311485 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 12:26:48.314504 0 15 28 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5647 12:26:48.321436 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5648 12:26:48.324524 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 12:26:48.327921 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 12:26:48.334350 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 12:26:48.338125 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 12:26:48.341059 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 12:26:48.347351 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 12:26:48.350715 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5655 12:26:48.354157 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:26:48.360682 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:26:48.364185 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:26:48.367157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:26:48.373510 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:26:48.376816 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:26:48.380542 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:26:48.387219 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:26:48.390012 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:26:48.393379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:26:48.399703 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:26:48.403226 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:26:48.406969 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:26:48.413124 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:26:48.416412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:26:48.419930 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5671 12:26:48.426318 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 12:26:48.426788 Total UI for P1: 0, mck2ui 16
5673 12:26:48.433314 best dqsien dly found for B0: ( 1, 2, 28)
5674 12:26:48.433883 Total UI for P1: 0, mck2ui 16
5675 12:26:48.439653 best dqsien dly found for B1: ( 1, 2, 28)
5676 12:26:48.442629 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5677 12:26:48.446365 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5678 12:26:48.446904
5679 12:26:48.449591 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5680 12:26:48.452758 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5681 12:26:48.455969 [Gating] SW calibration Done
5682 12:26:48.456395 ==
5683 12:26:48.459262 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 12:26:48.462922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 12:26:48.463319 ==
5686 12:26:48.466127 RX Vref Scan: 0
5687 12:26:48.466596
5688 12:26:48.466979 RX Vref 0 -> 0, step: 1
5689 12:26:48.469306
5690 12:26:48.469770 RX Delay -80 -> 252, step: 8
5691 12:26:48.476283 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5692 12:26:48.479582 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5693 12:26:48.482410 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5694 12:26:48.485474 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5695 12:26:48.489176 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5696 12:26:48.492232 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5697 12:26:48.498745 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5698 12:26:48.502205 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5699 12:26:48.505645 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5700 12:26:48.508716 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5701 12:26:48.511783 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5702 12:26:48.518726 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5703 12:26:48.521866 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5704 12:26:48.525437 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5705 12:26:48.528626 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5706 12:26:48.534929 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5707 12:26:48.535411 ==
5708 12:26:48.538197 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 12:26:48.541831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 12:26:48.542324 ==
5711 12:26:48.542667 DQS Delay:
5712 12:26:48.544996 DQS0 = 0, DQS1 = 0
5713 12:26:48.545423 DQM Delay:
5714 12:26:48.548111 DQM0 = 94, DQM1 = 85
5715 12:26:48.548583 DQ Delay:
5716 12:26:48.551650 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5717 12:26:48.554677 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5718 12:26:48.557971 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5719 12:26:48.561167 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5720 12:26:48.561596
5721 12:26:48.561935
5722 12:26:48.562251 ==
5723 12:26:48.564997 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 12:26:48.568186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 12:26:48.568800 ==
5726 12:26:48.571214
5727 12:26:48.571643
5728 12:26:48.571984 TX Vref Scan disable
5729 12:26:48.574234 == TX Byte 0 ==
5730 12:26:48.577976 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5731 12:26:48.581030 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5732 12:26:48.584214 == TX Byte 1 ==
5733 12:26:48.587965 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5734 12:26:48.590657 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5735 12:26:48.594416 ==
5736 12:26:48.594927 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 12:26:48.601028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 12:26:48.601501 ==
5739 12:26:48.601872
5740 12:26:48.602218
5741 12:26:48.603969 TX Vref Scan disable
5742 12:26:48.604440 == TX Byte 0 ==
5743 12:26:48.610950 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5744 12:26:48.614011 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5745 12:26:48.614482 == TX Byte 1 ==
5746 12:26:48.620783 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 12:26:48.623919 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 12:26:48.624390
5749 12:26:48.624783 [DATLAT]
5750 12:26:48.627532 Freq=933, CH1 RK0
5751 12:26:48.628173
5752 12:26:48.628567 DATLAT Default: 0xd
5753 12:26:48.630621 0, 0xFFFF, sum = 0
5754 12:26:48.631275 1, 0xFFFF, sum = 0
5755 12:26:48.633892 2, 0xFFFF, sum = 0
5756 12:26:48.634378 3, 0xFFFF, sum = 0
5757 12:26:48.637035 4, 0xFFFF, sum = 0
5758 12:26:48.637465 5, 0xFFFF, sum = 0
5759 12:26:48.640174 6, 0xFFFF, sum = 0
5760 12:26:48.643883 7, 0xFFFF, sum = 0
5761 12:26:48.644396 8, 0xFFFF, sum = 0
5762 12:26:48.646902 9, 0xFFFF, sum = 0
5763 12:26:48.647408 10, 0x0, sum = 1
5764 12:26:48.649917 11, 0x0, sum = 2
5765 12:26:48.650528 12, 0x0, sum = 3
5766 12:26:48.651087 13, 0x0, sum = 4
5767 12:26:48.653605 best_step = 11
5768 12:26:48.654152
5769 12:26:48.654628 ==
5770 12:26:48.656665 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 12:26:48.659880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 12:26:48.660397 ==
5773 12:26:48.663623 RX Vref Scan: 1
5774 12:26:48.664046
5775 12:26:48.664379 RX Vref 0 -> 0, step: 1
5776 12:26:48.666809
5777 12:26:48.667295 RX Delay -69 -> 252, step: 4
5778 12:26:48.667684
5779 12:26:48.669779 Set Vref, RX VrefLevel [Byte0]: 54
5780 12:26:48.673093 [Byte1]: 46
5781 12:26:48.678117
5782 12:26:48.678698 Final RX Vref Byte 0 = 54 to rank0
5783 12:26:48.681264 Final RX Vref Byte 1 = 46 to rank0
5784 12:26:48.684667 Final RX Vref Byte 0 = 54 to rank1
5785 12:26:48.687654 Final RX Vref Byte 1 = 46 to rank1==
5786 12:26:48.691046 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 12:26:48.697765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 12:26:48.698234 ==
5789 12:26:48.698604 DQS Delay:
5790 12:26:48.700665 DQS0 = 0, DQS1 = 0
5791 12:26:48.701250 DQM Delay:
5792 12:26:48.701633 DQM0 = 95, DQM1 = 87
5793 12:26:48.704309 DQ Delay:
5794 12:26:48.707970 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5795 12:26:48.711097 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
5796 12:26:48.714089 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =82
5797 12:26:48.717642 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =94
5798 12:26:48.718078
5799 12:26:48.718410
5800 12:26:48.724439 [DQSOSCAuto] RK0, (LSB)MR18= 0x9, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5801 12:26:48.727233 CH1 RK0: MR19=505, MR18=9
5802 12:26:48.733909 CH1_RK0: MR19=0x505, MR18=0x9, DQSOSC=419, MR23=63, INC=61, DEC=41
5803 12:26:48.734467
5804 12:26:48.737675 ----->DramcWriteLeveling(PI) begin...
5805 12:26:48.738104 ==
5806 12:26:48.740775 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 12:26:48.743899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 12:26:48.744310 ==
5809 12:26:48.747131 Write leveling (Byte 0): 27 => 27
5810 12:26:48.750552 Write leveling (Byte 1): 29 => 29
5811 12:26:48.754173 DramcWriteLeveling(PI) end<-----
5812 12:26:48.754728
5813 12:26:48.755147 ==
5814 12:26:48.757060 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 12:26:48.760642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 12:26:48.761153 ==
5817 12:26:48.763767 [Gating] SW mode calibration
5818 12:26:48.770112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5819 12:26:48.776886 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5820 12:26:48.780068 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5821 12:26:48.786397 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 12:26:48.789746 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 12:26:48.793337 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 12:26:48.799658 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 12:26:48.803192 0 14 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5826 12:26:48.806132 0 14 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (1 0)
5827 12:26:48.812368 0 14 28 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (1 0)
5828 12:26:48.816102 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5829 12:26:48.819299 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 12:26:48.825662 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 12:26:48.829127 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 12:26:48.832402 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 12:26:48.838820 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5834 12:26:48.842499 0 15 24 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
5835 12:26:48.845550 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5836 12:26:48.852751 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 12:26:48.855908 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 12:26:48.859013 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 12:26:48.865429 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 12:26:48.868765 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 12:26:48.872403 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 12:26:48.878707 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5843 12:26:48.882079 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5844 12:26:48.885920 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:26:48.891854 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:26:48.895426 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:26:48.898534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:26:48.904811 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:26:48.908011 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:26:48.911686 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:26:48.918151 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:26:48.921131 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:26:48.924524 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:26:48.930952 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 12:26:48.934543 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 12:26:48.938184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 12:26:48.944257 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:26:48.947917 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5859 12:26:48.950943 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5860 12:26:48.954444 Total UI for P1: 0, mck2ui 16
5861 12:26:48.957642 best dqsien dly found for B0: ( 1, 2, 24)
5862 12:26:48.964508 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 12:26:48.965078 Total UI for P1: 0, mck2ui 16
5864 12:26:48.970907 best dqsien dly found for B1: ( 1, 2, 28)
5865 12:26:48.974463 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5866 12:26:48.977658 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5867 12:26:48.978232
5868 12:26:48.981006 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5869 12:26:48.983978 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5870 12:26:48.987583 [Gating] SW calibration Done
5871 12:26:48.988119 ==
5872 12:26:48.990619 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 12:26:48.993728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 12:26:48.994262 ==
5875 12:26:48.997402 RX Vref Scan: 0
5876 12:26:48.997895
5877 12:26:48.998375 RX Vref 0 -> 0, step: 1
5878 12:26:49.000549
5879 12:26:49.001028 RX Delay -80 -> 252, step: 8
5880 12:26:49.006907 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5881 12:26:49.009967 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5882 12:26:49.013716 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5883 12:26:49.016947 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5884 12:26:49.020882 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5885 12:26:49.023665 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5886 12:26:49.030159 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5887 12:26:49.033777 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5888 12:26:49.036627 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5889 12:26:49.040403 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5890 12:26:49.043254 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5891 12:26:49.050231 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5892 12:26:49.053382 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5893 12:26:49.056963 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5894 12:26:49.059914 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5895 12:26:49.063609 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5896 12:26:49.064088 ==
5897 12:26:49.066652 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 12:26:49.072990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 12:26:49.073469 ==
5900 12:26:49.073951 DQS Delay:
5901 12:26:49.076621 DQS0 = 0, DQS1 = 0
5902 12:26:49.077089 DQM Delay:
5903 12:26:49.077464 DQM0 = 93, DQM1 = 89
5904 12:26:49.079594 DQ Delay:
5905 12:26:49.082988 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =91
5906 12:26:49.086018 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5907 12:26:49.089744 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5908 12:26:49.092769 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5909 12:26:49.093201
5910 12:26:49.093561
5911 12:26:49.093878 ==
5912 12:26:49.095946 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 12:26:49.099654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 12:26:49.100105 ==
5915 12:26:49.100449
5916 12:26:49.100765
5917 12:26:49.102674 TX Vref Scan disable
5918 12:26:49.105886 == TX Byte 0 ==
5919 12:26:49.109302 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5920 12:26:49.112903 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5921 12:26:49.116138 == TX Byte 1 ==
5922 12:26:49.119267 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5923 12:26:49.122221 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5924 12:26:49.122657 ==
5925 12:26:49.126015 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 12:26:49.132566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 12:26:49.132997 ==
5928 12:26:49.133340
5929 12:26:49.133655
5930 12:26:49.133958 TX Vref Scan disable
5931 12:26:49.136077 == TX Byte 0 ==
5932 12:26:49.139541 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5933 12:26:49.146176 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5934 12:26:49.146608 == TX Byte 1 ==
5935 12:26:49.149142 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5936 12:26:49.155909 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5937 12:26:49.156330
5938 12:26:49.156662 [DATLAT]
5939 12:26:49.156973 Freq=933, CH1 RK1
5940 12:26:49.157272
5941 12:26:49.159051 DATLAT Default: 0xb
5942 12:26:49.159471 0, 0xFFFF, sum = 0
5943 12:26:49.162671 1, 0xFFFF, sum = 0
5944 12:26:49.163151 2, 0xFFFF, sum = 0
5945 12:26:49.165655 3, 0xFFFF, sum = 0
5946 12:26:49.169268 4, 0xFFFF, sum = 0
5947 12:26:49.169741 5, 0xFFFF, sum = 0
5948 12:26:49.172440 6, 0xFFFF, sum = 0
5949 12:26:49.172929 7, 0xFFFF, sum = 0
5950 12:26:49.175626 8, 0xFFFF, sum = 0
5951 12:26:49.176107 9, 0xFFFF, sum = 0
5952 12:26:49.178622 10, 0x0, sum = 1
5953 12:26:49.179104 11, 0x0, sum = 2
5954 12:26:49.182462 12, 0x0, sum = 3
5955 12:26:49.182955 13, 0x0, sum = 4
5956 12:26:49.183369 best_step = 11
5957 12:26:49.185431
5958 12:26:49.185847 ==
5959 12:26:49.188978 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 12:26:49.192029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 12:26:49.192631 ==
5962 12:26:49.193069 RX Vref Scan: 0
5963 12:26:49.193547
5964 12:26:49.195344 RX Vref 0 -> 0, step: 1
5965 12:26:49.195766
5966 12:26:49.198437 RX Delay -69 -> 252, step: 4
5967 12:26:49.205538 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5968 12:26:49.208730 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5969 12:26:49.211839 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5970 12:26:49.215391 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5971 12:26:49.218602 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5972 12:26:49.221654 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5973 12:26:49.228492 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5974 12:26:49.231578 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5975 12:26:49.234715 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5976 12:26:49.238290 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5977 12:26:49.241375 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5978 12:26:49.247902 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5979 12:26:49.251480 iDelay=203, Bit 12, Center 96 (7 ~ 186) 180
5980 12:26:49.255119 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5981 12:26:49.258180 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5982 12:26:49.261523 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5983 12:26:49.262022 ==
5984 12:26:49.264623 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 12:26:49.271229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 12:26:49.271725 ==
5987 12:26:49.272105 DQS Delay:
5988 12:26:49.274943 DQS0 = 0, DQS1 = 0
5989 12:26:49.275421 DQM Delay:
5990 12:26:49.278109 DQM0 = 91, DQM1 = 90
5991 12:26:49.278579 DQ Delay:
5992 12:26:49.281198 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5993 12:26:49.284320 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
5994 12:26:49.287744 DQ8 =76, DQ9 =80, DQ10 =94, DQ11 =84
5995 12:26:49.291339 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =94
5996 12:26:49.291765
5997 12:26:49.292105
5998 12:26:49.297634 [DQSOSCAuto] RK1, (LSB)MR18= 0xf24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5999 12:26:49.301078 CH1 RK1: MR19=505, MR18=F24
6000 12:26:49.307778 CH1_RK1: MR19=0x505, MR18=0xF24, DQSOSC=410, MR23=63, INC=64, DEC=42
6001 12:26:49.310560 [RxdqsGatingPostProcess] freq 933
6002 12:26:49.317673 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6003 12:26:49.318148 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 12:26:49.321000 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 12:26:49.324003 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 12:26:49.327078 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 12:26:49.330798 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 12:26:49.333915 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 12:26:49.337052 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 12:26:49.340777 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 12:26:49.343717 Pre-setting of DQS Precalculation
6012 12:26:49.350208 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6013 12:26:49.356786 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6014 12:26:49.363901 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6015 12:26:49.364519
6016 12:26:49.364969
6017 12:26:49.366904 [Calibration Summary] 1866 Mbps
6018 12:26:49.367380 CH 0, Rank 0
6019 12:26:49.370024 SW Impedance : PASS
6020 12:26:49.373856 DUTY Scan : NO K
6021 12:26:49.374455 ZQ Calibration : PASS
6022 12:26:49.376811 Jitter Meter : NO K
6023 12:26:49.380252 CBT Training : PASS
6024 12:26:49.380724 Write leveling : PASS
6025 12:26:49.383447 RX DQS gating : PASS
6026 12:26:49.386490 RX DQ/DQS(RDDQC) : PASS
6027 12:26:49.386992 TX DQ/DQS : PASS
6028 12:26:49.390106 RX DATLAT : PASS
6029 12:26:49.393208 RX DQ/DQS(Engine): PASS
6030 12:26:49.393683 TX OE : NO K
6031 12:26:49.394174 All Pass.
6032 12:26:49.396295
6033 12:26:49.396760 CH 0, Rank 1
6034 12:26:49.399990 SW Impedance : PASS
6035 12:26:49.400471 DUTY Scan : NO K
6036 12:26:49.402990 ZQ Calibration : PASS
6037 12:26:49.406096 Jitter Meter : NO K
6038 12:26:49.406566 CBT Training : PASS
6039 12:26:49.409837 Write leveling : PASS
6040 12:26:49.410386 RX DQS gating : PASS
6041 12:26:49.412917 RX DQ/DQS(RDDQC) : PASS
6042 12:26:49.416054 TX DQ/DQS : PASS
6043 12:26:49.416494 RX DATLAT : PASS
6044 12:26:49.419618 RX DQ/DQS(Engine): PASS
6045 12:26:49.422768 TX OE : NO K
6046 12:26:49.423442 All Pass.
6047 12:26:49.423788
6048 12:26:49.424128 CH 1, Rank 0
6049 12:26:49.426048 SW Impedance : PASS
6050 12:26:49.429016 DUTY Scan : NO K
6051 12:26:49.429445 ZQ Calibration : PASS
6052 12:26:49.432827 Jitter Meter : NO K
6053 12:26:49.435802 CBT Training : PASS
6054 12:26:49.436258 Write leveling : PASS
6055 12:26:49.438963 RX DQS gating : PASS
6056 12:26:49.442858 RX DQ/DQS(RDDQC) : PASS
6057 12:26:49.443290 TX DQ/DQS : PASS
6058 12:26:49.445816 RX DATLAT : PASS
6059 12:26:49.448980 RX DQ/DQS(Engine): PASS
6060 12:26:49.449412 TX OE : NO K
6061 12:26:49.452548 All Pass.
6062 12:26:49.452979
6063 12:26:49.453346 CH 1, Rank 1
6064 12:26:49.455390 SW Impedance : PASS
6065 12:26:49.455819 DUTY Scan : NO K
6066 12:26:49.459219 ZQ Calibration : PASS
6067 12:26:49.462103 Jitter Meter : NO K
6068 12:26:49.462558 CBT Training : PASS
6069 12:26:49.465645 Write leveling : PASS
6070 12:26:49.468714 RX DQS gating : PASS
6071 12:26:49.469142 RX DQ/DQS(RDDQC) : PASS
6072 12:26:49.472226 TX DQ/DQS : PASS
6073 12:26:49.475137 RX DATLAT : PASS
6074 12:26:49.475593 RX DQ/DQS(Engine): PASS
6075 12:26:49.478771 TX OE : NO K
6076 12:26:49.479303 All Pass.
6077 12:26:49.479647
6078 12:26:49.481689 DramC Write-DBI off
6079 12:26:49.485278 PER_BANK_REFRESH: Hybrid Mode
6080 12:26:49.485760 TX_TRACKING: ON
6081 12:26:49.495452 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6082 12:26:49.498330 [FAST_K] Save calibration result to emmc
6083 12:26:49.501523 dramc_set_vcore_voltage set vcore to 650000
6084 12:26:49.505245 Read voltage for 400, 6
6085 12:26:49.505677 Vio18 = 0
6086 12:26:49.506022 Vcore = 650000
6087 12:26:49.508455 Vdram = 0
6088 12:26:49.508885 Vddq = 0
6089 12:26:49.509227 Vmddr = 0
6090 12:26:49.514504 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6091 12:26:49.518192 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6092 12:26:49.521334 MEM_TYPE=3, freq_sel=20
6093 12:26:49.524535 sv_algorithm_assistance_LP4_800
6094 12:26:49.528204 ============ PULL DRAM RESETB DOWN ============
6095 12:26:49.531240 ========== PULL DRAM RESETB DOWN end =========
6096 12:26:49.538078 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6097 12:26:49.541179 ===================================
6098 12:26:49.544433 LPDDR4 DRAM CONFIGURATION
6099 12:26:49.547461 ===================================
6100 12:26:49.547890 EX_ROW_EN[0] = 0x0
6101 12:26:49.550621 EX_ROW_EN[1] = 0x0
6102 12:26:49.551092 LP4Y_EN = 0x0
6103 12:26:49.554403 WORK_FSP = 0x0
6104 12:26:49.554871 WL = 0x2
6105 12:26:49.557490 RL = 0x2
6106 12:26:49.557917 BL = 0x2
6107 12:26:49.560624 RPST = 0x0
6108 12:26:49.564030 RD_PRE = 0x0
6109 12:26:49.564453 WR_PRE = 0x1
6110 12:26:49.567293 WR_PST = 0x0
6111 12:26:49.567717 DBI_WR = 0x0
6112 12:26:49.570637 DBI_RD = 0x0
6113 12:26:49.571095 OTF = 0x1
6114 12:26:49.573630 ===================================
6115 12:26:49.577259 ===================================
6116 12:26:49.580337 ANA top config
6117 12:26:49.583490 ===================================
6118 12:26:49.583917 DLL_ASYNC_EN = 0
6119 12:26:49.586964 ALL_SLAVE_EN = 1
6120 12:26:49.590513 NEW_RANK_MODE = 1
6121 12:26:49.593827 DLL_IDLE_MODE = 1
6122 12:26:49.594393 LP45_APHY_COMB_EN = 1
6123 12:26:49.596616 TX_ODT_DIS = 1
6124 12:26:49.600380 NEW_8X_MODE = 1
6125 12:26:49.603347 ===================================
6126 12:26:49.606423 ===================================
6127 12:26:49.610117 data_rate = 800
6128 12:26:49.613305 CKR = 1
6129 12:26:49.616388 DQ_P2S_RATIO = 4
6130 12:26:49.620147 ===================================
6131 12:26:49.620618 CA_P2S_RATIO = 4
6132 12:26:49.623196 DQ_CA_OPEN = 0
6133 12:26:49.626261 DQ_SEMI_OPEN = 1
6134 12:26:49.629529 CA_SEMI_OPEN = 1
6135 12:26:49.633450 CA_FULL_RATE = 0
6136 12:26:49.636348 DQ_CKDIV4_EN = 0
6137 12:26:49.639355 CA_CKDIV4_EN = 1
6138 12:26:49.639802 CA_PREDIV_EN = 0
6139 12:26:49.643109 PH8_DLY = 0
6140 12:26:49.646189 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6141 12:26:49.649341 DQ_AAMCK_DIV = 0
6142 12:26:49.652480 CA_AAMCK_DIV = 0
6143 12:26:49.656310 CA_ADMCK_DIV = 4
6144 12:26:49.656730 DQ_TRACK_CA_EN = 0
6145 12:26:49.659367 CA_PICK = 800
6146 12:26:49.662551 CA_MCKIO = 400
6147 12:26:49.665664 MCKIO_SEMI = 400
6148 12:26:49.669386 PLL_FREQ = 3016
6149 12:26:49.672933 DQ_UI_PI_RATIO = 32
6150 12:26:49.676051 CA_UI_PI_RATIO = 32
6151 12:26:49.679318 ===================================
6152 12:26:49.682332 ===================================
6153 12:26:49.682898 memory_type:LPDDR4
6154 12:26:49.685850 GP_NUM : 10
6155 12:26:49.689312 SRAM_EN : 1
6156 12:26:49.689855 MD32_EN : 0
6157 12:26:49.692154 ===================================
6158 12:26:49.695607 [ANA_INIT] >>>>>>>>>>>>>>
6159 12:26:49.698998 <<<<<< [CONFIGURE PHASE]: ANA_TX
6160 12:26:49.701945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6161 12:26:49.705767 ===================================
6162 12:26:49.708553 data_rate = 800,PCW = 0X7400
6163 12:26:49.712246 ===================================
6164 12:26:49.715313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6165 12:26:49.718414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6166 12:26:49.732287 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 12:26:49.735489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6168 12:26:49.738552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6169 12:26:49.741578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6170 12:26:49.745329 [ANA_INIT] flow start
6171 12:26:49.748547 [ANA_INIT] PLL >>>>>>>>
6172 12:26:49.749085 [ANA_INIT] PLL <<<<<<<<
6173 12:26:49.751735 [ANA_INIT] MIDPI >>>>>>>>
6174 12:26:49.754814 [ANA_INIT] MIDPI <<<<<<<<
6175 12:26:49.755335 [ANA_INIT] DLL >>>>>>>>
6176 12:26:49.757975 [ANA_INIT] flow end
6177 12:26:49.762013 ============ LP4 DIFF to SE enter ============
6178 12:26:49.768231 ============ LP4 DIFF to SE exit ============
6179 12:26:49.768727 [ANA_INIT] <<<<<<<<<<<<<
6180 12:26:49.771200 [Flow] Enable top DCM control >>>>>
6181 12:26:49.775137 [Flow] Enable top DCM control <<<<<
6182 12:26:49.778766 Enable DLL master slave shuffle
6183 12:26:49.785132 ==============================================================
6184 12:26:49.785700 Gating Mode config
6185 12:26:49.791302 ==============================================================
6186 12:26:49.794764 Config description:
6187 12:26:49.804738 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6188 12:26:49.811211 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6189 12:26:49.814285 SELPH_MODE 0: By rank 1: By Phase
6190 12:26:49.821099 ==============================================================
6191 12:26:49.824146 GAT_TRACK_EN = 0
6192 12:26:49.827185 RX_GATING_MODE = 2
6193 12:26:49.827672 RX_GATING_TRACK_MODE = 2
6194 12:26:49.830727 SELPH_MODE = 1
6195 12:26:49.833874 PICG_EARLY_EN = 1
6196 12:26:49.837126 VALID_LAT_VALUE = 1
6197 12:26:49.843889 ==============================================================
6198 12:26:49.846951 Enter into Gating configuration >>>>
6199 12:26:49.850728 Exit from Gating configuration <<<<
6200 12:26:49.853929 Enter into DVFS_PRE_config >>>>>
6201 12:26:49.863958 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6202 12:26:49.866937 Exit from DVFS_PRE_config <<<<<
6203 12:26:49.870150 Enter into PICG configuration >>>>
6204 12:26:49.873316 Exit from PICG configuration <<<<
6205 12:26:49.877181 [RX_INPUT] configuration >>>>>
6206 12:26:49.880378 [RX_INPUT] configuration <<<<<
6207 12:26:49.884010 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6208 12:26:49.889983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6209 12:26:49.897148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 12:26:49.903421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 12:26:49.909698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 12:26:49.913385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 12:26:49.919777 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6214 12:26:49.922749 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6215 12:26:49.926401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6216 12:26:49.929538 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6217 12:26:49.936441 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6218 12:26:49.939430 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 12:26:49.942675 ===================================
6220 12:26:49.945800 LPDDR4 DRAM CONFIGURATION
6221 12:26:49.949551 ===================================
6222 12:26:49.949977 EX_ROW_EN[0] = 0x0
6223 12:26:49.952608 EX_ROW_EN[1] = 0x0
6224 12:26:49.953028 LP4Y_EN = 0x0
6225 12:26:49.955716 WORK_FSP = 0x0
6226 12:26:49.959378 WL = 0x2
6227 12:26:49.959795 RL = 0x2
6228 12:26:49.962563 BL = 0x2
6229 12:26:49.963054 RPST = 0x0
6230 12:26:49.965675 RD_PRE = 0x0
6231 12:26:49.966095 WR_PRE = 0x1
6232 12:26:49.968974 WR_PST = 0x0
6233 12:26:49.969551 DBI_WR = 0x0
6234 12:26:49.972220 DBI_RD = 0x0
6235 12:26:49.972719 OTF = 0x1
6236 12:26:49.975318 ===================================
6237 12:26:49.979197 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6238 12:26:49.985806 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6239 12:26:49.988609 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 12:26:49.991643 ===================================
6241 12:26:49.995428 LPDDR4 DRAM CONFIGURATION
6242 12:26:49.998894 ===================================
6243 12:26:49.999359 EX_ROW_EN[0] = 0x10
6244 12:26:50.001936 EX_ROW_EN[1] = 0x0
6245 12:26:50.004968 LP4Y_EN = 0x0
6246 12:26:50.005447 WORK_FSP = 0x0
6247 12:26:50.008452 WL = 0x2
6248 12:26:50.008988 RL = 0x2
6249 12:26:50.012079 BL = 0x2
6250 12:26:50.012502 RPST = 0x0
6251 12:26:50.014859 RD_PRE = 0x0
6252 12:26:50.015358 WR_PRE = 0x1
6253 12:26:50.018324 WR_PST = 0x0
6254 12:26:50.018982 DBI_WR = 0x0
6255 12:26:50.021868 DBI_RD = 0x0
6256 12:26:50.022291 OTF = 0x1
6257 12:26:50.024910 ===================================
6258 12:26:50.031339 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6259 12:26:50.035871 nWR fixed to 30
6260 12:26:50.038871 [ModeRegInit_LP4] CH0 RK0
6261 12:26:50.039304 [ModeRegInit_LP4] CH0 RK1
6262 12:26:50.042561 [ModeRegInit_LP4] CH1 RK0
6263 12:26:50.045644 [ModeRegInit_LP4] CH1 RK1
6264 12:26:50.046063 match AC timing 19
6265 12:26:50.052566 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6266 12:26:50.055657 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6267 12:26:50.058748 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6268 12:26:50.066111 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6269 12:26:50.068973 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6270 12:26:50.069542 ==
6271 12:26:50.072004 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 12:26:50.075225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 12:26:50.075697 ==
6274 12:26:50.082512 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 12:26:50.088394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6276 12:26:50.091936 [CA 0] Center 36 (8~64) winsize 57
6277 12:26:50.094870 [CA 1] Center 36 (8~64) winsize 57
6278 12:26:50.098655 [CA 2] Center 36 (8~64) winsize 57
6279 12:26:50.101892 [CA 3] Center 36 (8~64) winsize 57
6280 12:26:50.105038 [CA 4] Center 36 (8~64) winsize 57
6281 12:26:50.108387 [CA 5] Center 36 (8~64) winsize 57
6282 12:26:50.108867
6283 12:26:50.111792 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6284 12:26:50.112269
6285 12:26:50.114820 [CATrainingPosCal] consider 1 rank data
6286 12:26:50.118358 u2DelayCellTimex100 = 270/100 ps
6287 12:26:50.121332 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:26:50.124654 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 12:26:50.128266 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 12:26:50.131342 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 12:26:50.134635 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 12:26:50.137838 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 12:26:50.138306
6294 12:26:50.144494 CA PerBit enable=1, Macro0, CA PI delay=36
6295 12:26:50.145000
6296 12:26:50.145389 [CBTSetCACLKResult] CA Dly = 36
6297 12:26:50.147533 CS Dly: 1 (0~32)
6298 12:26:50.148008 ==
6299 12:26:50.151455 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 12:26:50.154342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 12:26:50.154814 ==
6302 12:26:50.161153 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6303 12:26:50.167581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6304 12:26:50.170693 [CA 0] Center 36 (8~64) winsize 57
6305 12:26:50.174476 [CA 1] Center 36 (8~64) winsize 57
6306 12:26:50.177564 [CA 2] Center 36 (8~64) winsize 57
6307 12:26:50.180984 [CA 3] Center 36 (8~64) winsize 57
6308 12:26:50.183989 [CA 4] Center 36 (8~64) winsize 57
6309 12:26:50.184584 [CA 5] Center 36 (8~64) winsize 57
6310 12:26:50.187426
6311 12:26:50.190642 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6312 12:26:50.191189
6313 12:26:50.194146 [CATrainingPosCal] consider 2 rank data
6314 12:26:50.197134 u2DelayCellTimex100 = 270/100 ps
6315 12:26:50.200455 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 12:26:50.203972 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 12:26:50.207492 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 12:26:50.210662 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 12:26:50.213835 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 12:26:50.216947 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 12:26:50.217436
6322 12:26:50.219793 CA PerBit enable=1, Macro0, CA PI delay=36
6323 12:26:50.223349
6324 12:26:50.223868 [CBTSetCACLKResult] CA Dly = 36
6325 12:26:50.226900 CS Dly: 1 (0~32)
6326 12:26:50.227387
6327 12:26:50.230262 ----->DramcWriteLeveling(PI) begin...
6328 12:26:50.230758 ==
6329 12:26:50.233306 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 12:26:50.236878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 12:26:50.237369 ==
6332 12:26:50.239738 Write leveling (Byte 0): 40 => 8
6333 12:26:50.243394 Write leveling (Byte 1): 40 => 8
6334 12:26:50.246201 DramcWriteLeveling(PI) end<-----
6335 12:26:50.246686
6336 12:26:50.247187 ==
6337 12:26:50.249917 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 12:26:50.252876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 12:26:50.256453 ==
6340 12:26:50.256894 [Gating] SW mode calibration
6341 12:26:50.266139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6342 12:26:50.269309 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6343 12:26:50.272590 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6344 12:26:50.279910 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 12:26:50.282722 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 12:26:50.285955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 12:26:50.292637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 12:26:50.295862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 12:26:50.298891 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 12:26:50.305948 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 12:26:50.309113 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 12:26:50.312258 Total UI for P1: 0, mck2ui 16
6353 12:26:50.315413 best dqsien dly found for B0: ( 0, 14, 24)
6354 12:26:50.318682 Total UI for P1: 0, mck2ui 16
6355 12:26:50.321848 best dqsien dly found for B1: ( 0, 14, 24)
6356 12:26:50.325481 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6357 12:26:50.328753 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6358 12:26:50.328988
6359 12:26:50.332154 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6360 12:26:50.338343 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 12:26:50.338687 [Gating] SW calibration Done
6362 12:26:50.339011 ==
6363 12:26:50.341747 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 12:26:50.348943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 12:26:50.349382 ==
6366 12:26:50.349648 RX Vref Scan: 0
6367 12:26:50.349883
6368 12:26:50.351554 RX Vref 0 -> 0, step: 1
6369 12:26:50.351871
6370 12:26:50.355295 RX Delay -410 -> 252, step: 16
6371 12:26:50.358313 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6372 12:26:50.361863 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6373 12:26:50.368468 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6374 12:26:50.371986 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6375 12:26:50.375103 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6376 12:26:50.378227 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6377 12:26:50.384829 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6378 12:26:50.388715 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6379 12:26:50.391623 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6380 12:26:50.394778 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6381 12:26:50.401868 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6382 12:26:50.404928 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6383 12:26:50.407987 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6384 12:26:50.414768 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6385 12:26:50.417937 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6386 12:26:50.420851 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6387 12:26:50.421318 ==
6388 12:26:50.424652 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 12:26:50.428082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 12:26:50.430987 ==
6391 12:26:50.431551 DQS Delay:
6392 12:26:50.431930 DQS0 = 59, DQS1 = 59
6393 12:26:50.434104 DQM Delay:
6394 12:26:50.434766 DQM0 = 18, DQM1 = 11
6395 12:26:50.437592 DQ Delay:
6396 12:26:50.440744 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6397 12:26:50.441399 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6398 12:26:50.443923 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6399 12:26:50.447577 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6400 12:26:50.448167
6401 12:26:50.450549
6402 12:26:50.451167 ==
6403 12:26:50.454227 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 12:26:50.457234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 12:26:50.457731 ==
6406 12:26:50.458202
6407 12:26:50.458807
6408 12:26:50.460908 TX Vref Scan disable
6409 12:26:50.461387 == TX Byte 0 ==
6410 12:26:50.463968 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 12:26:50.470637 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 12:26:50.471164 == TX Byte 1 ==
6413 12:26:50.473948 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 12:26:50.480170 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 12:26:50.480601 ==
6416 12:26:50.483430 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 12:26:50.486651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:26:50.487129 ==
6419 12:26:50.487475
6420 12:26:50.487790
6421 12:26:50.489919 TX Vref Scan disable
6422 12:26:50.490349 == TX Byte 0 ==
6423 12:26:50.496963 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 12:26:50.500411 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 12:26:50.500938 == TX Byte 1 ==
6426 12:26:50.506725 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 12:26:50.509758 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 12:26:50.510191
6429 12:26:50.510531 [DATLAT]
6430 12:26:50.513089 Freq=400, CH0 RK0
6431 12:26:50.513524
6432 12:26:50.513867 DATLAT Default: 0xf
6433 12:26:50.516938 0, 0xFFFF, sum = 0
6434 12:26:50.517477 1, 0xFFFF, sum = 0
6435 12:26:50.519960 2, 0xFFFF, sum = 0
6436 12:26:50.520419 3, 0xFFFF, sum = 0
6437 12:26:50.523155 4, 0xFFFF, sum = 0
6438 12:26:50.523593 5, 0xFFFF, sum = 0
6439 12:26:50.527106 6, 0xFFFF, sum = 0
6440 12:26:50.527658 7, 0xFFFF, sum = 0
6441 12:26:50.530143 8, 0xFFFF, sum = 0
6442 12:26:50.530582 9, 0xFFFF, sum = 0
6443 12:26:50.533196 10, 0xFFFF, sum = 0
6444 12:26:50.536414 11, 0xFFFF, sum = 0
6445 12:26:50.536960 12, 0xFFFF, sum = 0
6446 12:26:50.539890 13, 0x0, sum = 1
6447 12:26:50.540328 14, 0x0, sum = 2
6448 12:26:50.540675 15, 0x0, sum = 3
6449 12:26:50.543035 16, 0x0, sum = 4
6450 12:26:50.543473 best_step = 14
6451 12:26:50.543833
6452 12:26:50.546888 ==
6453 12:26:50.547433 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 12:26:50.553362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 12:26:50.553891 ==
6456 12:26:50.554236 RX Vref Scan: 1
6457 12:26:50.554557
6458 12:26:50.556087 RX Vref 0 -> 0, step: 1
6459 12:26:50.556515
6460 12:26:50.559611 RX Delay -359 -> 252, step: 8
6461 12:26:50.560043
6462 12:26:50.562493 Set Vref, RX VrefLevel [Byte0]: 62
6463 12:26:50.566348 [Byte1]: 53
6464 12:26:50.569742
6465 12:26:50.570279 Final RX Vref Byte 0 = 62 to rank0
6466 12:26:50.573188 Final RX Vref Byte 1 = 53 to rank0
6467 12:26:50.576142 Final RX Vref Byte 0 = 62 to rank1
6468 12:26:50.579696 Final RX Vref Byte 1 = 53 to rank1==
6469 12:26:50.582962 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 12:26:50.589480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 12:26:50.590034 ==
6472 12:26:50.590385 DQS Delay:
6473 12:26:50.593095 DQS0 = 60, DQS1 = 68
6474 12:26:50.593526 DQM Delay:
6475 12:26:50.593870 DQM0 = 15, DQM1 = 14
6476 12:26:50.596178 DQ Delay:
6477 12:26:50.599253 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =12
6478 12:26:50.603016 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6479 12:26:50.603492 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6480 12:26:50.609473 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6481 12:26:50.610040
6482 12:26:50.610419
6483 12:26:50.616157 [DQSOSCAuto] RK0, (LSB)MR18= 0x8685, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6484 12:26:50.619217 CH0 RK0: MR19=C0C, MR18=8685
6485 12:26:50.626154 CH0_RK0: MR19=0xC0C, MR18=0x8685, DQSOSC=393, MR23=63, INC=382, DEC=254
6486 12:26:50.626632 ==
6487 12:26:50.629338 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 12:26:50.632363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 12:26:50.632840 ==
6490 12:26:50.635580 [Gating] SW mode calibration
6491 12:26:50.642388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 12:26:50.648665 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6493 12:26:50.652442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 12:26:50.655430 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 12:26:50.661961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 12:26:50.665110 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 12:26:50.668599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 12:26:50.675395 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 12:26:50.678302 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 12:26:50.681738 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 12:26:50.688188 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 12:26:50.691832 Total UI for P1: 0, mck2ui 16
6503 12:26:50.695063 best dqsien dly found for B0: ( 0, 14, 24)
6504 12:26:50.698227 Total UI for P1: 0, mck2ui 16
6505 12:26:50.701958 best dqsien dly found for B1: ( 0, 14, 24)
6506 12:26:50.704549 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6507 12:26:50.707781 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6508 12:26:50.708273
6509 12:26:50.711416 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6510 12:26:50.714804 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 12:26:50.718068 [Gating] SW calibration Done
6512 12:26:50.718585 ==
6513 12:26:50.721030 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 12:26:50.724916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 12:26:50.725475 ==
6516 12:26:50.727966 RX Vref Scan: 0
6517 12:26:50.728419
6518 12:26:50.731110 RX Vref 0 -> 0, step: 1
6519 12:26:50.731578
6520 12:26:50.734287 RX Delay -410 -> 252, step: 16
6521 12:26:50.737421 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6522 12:26:50.741225 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 12:26:50.744163 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 12:26:50.750988 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 12:26:50.754083 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 12:26:50.757596 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6527 12:26:50.760571 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6528 12:26:50.767697 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6529 12:26:50.770355 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 12:26:50.773930 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 12:26:50.777068 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 12:26:50.783985 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6533 12:26:50.786948 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6534 12:26:50.790354 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6535 12:26:50.797135 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6536 12:26:50.800377 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6537 12:26:50.800953 ==
6538 12:26:50.803369 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 12:26:50.807108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 12:26:50.807663 ==
6541 12:26:50.810359 DQS Delay:
6542 12:26:50.811004 DQS0 = 59, DQS1 = 59
6543 12:26:50.813339 DQM Delay:
6544 12:26:50.813828 DQM0 = 16, DQM1 = 10
6545 12:26:50.814207 DQ Delay:
6546 12:26:50.816420 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6547 12:26:50.819634 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6548 12:26:50.823443 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6549 12:26:50.826675 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6550 12:26:50.827209
6551 12:26:50.827583
6552 12:26:50.827932 ==
6553 12:26:50.829854 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 12:26:50.836472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 12:26:50.837078 ==
6556 12:26:50.837464
6557 12:26:50.837813
6558 12:26:50.838145 TX Vref Scan disable
6559 12:26:50.839516 == TX Byte 0 ==
6560 12:26:50.842914 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6561 12:26:50.846483 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6562 12:26:50.849867 == TX Byte 1 ==
6563 12:26:50.852658 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6564 12:26:50.856495 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6565 12:26:50.859585 ==
6566 12:26:50.862579 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 12:26:50.866593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 12:26:50.867232 ==
6569 12:26:50.867618
6570 12:26:50.867965
6571 12:26:50.869484 TX Vref Scan disable
6572 12:26:50.869986 == TX Byte 0 ==
6573 12:26:50.872544 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6574 12:26:50.879303 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6575 12:26:50.879781 == TX Byte 1 ==
6576 12:26:50.882254 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6577 12:26:50.889044 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6578 12:26:50.889705
6579 12:26:50.890293 [DATLAT]
6580 12:26:50.890745 Freq=400, CH0 RK1
6581 12:26:50.891184
6582 12:26:50.892638 DATLAT Default: 0xe
6583 12:26:50.893223 0, 0xFFFF, sum = 0
6584 12:26:50.895535 1, 0xFFFF, sum = 0
6585 12:26:50.899120 2, 0xFFFF, sum = 0
6586 12:26:50.899732 3, 0xFFFF, sum = 0
6587 12:26:50.901962 4, 0xFFFF, sum = 0
6588 12:26:50.902585 5, 0xFFFF, sum = 0
6589 12:26:50.905392 6, 0xFFFF, sum = 0
6590 12:26:50.905873 7, 0xFFFF, sum = 0
6591 12:26:50.908499 8, 0xFFFF, sum = 0
6592 12:26:50.908980 9, 0xFFFF, sum = 0
6593 12:26:50.912334 10, 0xFFFF, sum = 0
6594 12:26:50.913113 11, 0xFFFF, sum = 0
6595 12:26:50.915460 12, 0xFFFF, sum = 0
6596 12:26:50.915942 13, 0x0, sum = 1
6597 12:26:50.918454 14, 0x0, sum = 2
6598 12:26:50.918972 15, 0x0, sum = 3
6599 12:26:50.922072 16, 0x0, sum = 4
6600 12:26:50.922554 best_step = 14
6601 12:26:50.923125
6602 12:26:50.923495 ==
6603 12:26:50.925218 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 12:26:50.932268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 12:26:50.932839 ==
6606 12:26:50.933221 RX Vref Scan: 0
6607 12:26:50.933571
6608 12:26:50.935409 RX Vref 0 -> 0, step: 1
6609 12:26:50.935983
6610 12:26:50.938635 RX Delay -359 -> 252, step: 8
6611 12:26:50.944990 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6612 12:26:50.948663 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6613 12:26:50.951906 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6614 12:26:50.955065 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6615 12:26:50.961819 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6616 12:26:50.965083 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6617 12:26:50.968521 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6618 12:26:50.971679 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6619 12:26:50.978111 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6620 12:26:50.981172 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6621 12:26:50.984548 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6622 12:26:50.988450 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6623 12:26:50.995049 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6624 12:26:50.998119 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6625 12:26:51.001110 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6626 12:26:51.004678 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6627 12:26:51.008232 ==
6628 12:26:51.011153 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 12:26:51.014780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 12:26:51.015392 ==
6631 12:26:51.015745 DQS Delay:
6632 12:26:51.017951 DQS0 = 60, DQS1 = 72
6633 12:26:51.018369 DQM Delay:
6634 12:26:51.020950 DQM0 = 12, DQM1 = 17
6635 12:26:51.021496 DQ Delay:
6636 12:26:51.024731 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6637 12:26:51.027866 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6638 12:26:51.031325 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6639 12:26:51.034234 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6640 12:26:51.034671
6641 12:26:51.035148
6642 12:26:51.041256 [DQSOSCAuto] RK1, (LSB)MR18= 0xc278, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6643 12:26:51.044308 CH0 RK1: MR19=C0C, MR18=C278
6644 12:26:51.050783 CH0_RK1: MR19=0xC0C, MR18=0xC278, DQSOSC=385, MR23=63, INC=398, DEC=265
6645 12:26:51.054677 [RxdqsGatingPostProcess] freq 400
6646 12:26:51.060800 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6647 12:26:51.061326 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 12:26:51.064154 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 12:26:51.067319 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 12:26:51.071021 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 12:26:51.074105 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 12:26:51.077250 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 12:26:51.080476 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 12:26:51.084224 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 12:26:51.087400 Pre-setting of DQS Precalculation
6656 12:26:51.093643 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6657 12:26:51.094068 ==
6658 12:26:51.097201 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 12:26:51.100190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 12:26:51.100618 ==
6661 12:26:51.107283 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 12:26:51.110308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6663 12:26:51.113927 [CA 0] Center 36 (8~64) winsize 57
6664 12:26:51.116606 [CA 1] Center 36 (8~64) winsize 57
6665 12:26:51.120284 [CA 2] Center 36 (8~64) winsize 57
6666 12:26:51.123302 [CA 3] Center 36 (8~64) winsize 57
6667 12:26:51.126425 [CA 4] Center 36 (8~64) winsize 57
6668 12:26:51.129690 [CA 5] Center 36 (8~64) winsize 57
6669 12:26:51.130118
6670 12:26:51.132787 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6671 12:26:51.133327
6672 12:26:51.139589 [CATrainingPosCal] consider 1 rank data
6673 12:26:51.140071 u2DelayCellTimex100 = 270/100 ps
6674 12:26:51.146086 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:26:51.149149 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 12:26:51.152287 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 12:26:51.156055 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 12:26:51.159312 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 12:26:51.162423 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 12:26:51.162877
6681 12:26:51.165608 CA PerBit enable=1, Macro0, CA PI delay=36
6682 12:26:51.166029
6683 12:26:51.169476 [CBTSetCACLKResult] CA Dly = 36
6684 12:26:51.172508 CS Dly: 1 (0~32)
6685 12:26:51.172995 ==
6686 12:26:51.175503 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 12:26:51.179309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 12:26:51.179733 ==
6689 12:26:51.185794 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6690 12:26:51.191853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6691 12:26:51.192367 [CA 0] Center 36 (8~64) winsize 57
6692 12:26:51.195653 [CA 1] Center 36 (8~64) winsize 57
6693 12:26:51.198739 [CA 2] Center 36 (8~64) winsize 57
6694 12:26:51.201986 [CA 3] Center 36 (8~64) winsize 57
6695 12:26:51.204954 [CA 4] Center 36 (8~64) winsize 57
6696 12:26:51.208494 [CA 5] Center 36 (8~64) winsize 57
6697 12:26:51.208914
6698 12:26:51.212046 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6699 12:26:51.212444
6700 12:26:51.218428 [CATrainingPosCal] consider 2 rank data
6701 12:26:51.218964 u2DelayCellTimex100 = 270/100 ps
6702 12:26:51.224885 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 12:26:51.228399 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 12:26:51.231355 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 12:26:51.234802 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 12:26:51.237945 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 12:26:51.241496 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 12:26:51.241938
6709 12:26:51.244651 CA PerBit enable=1, Macro0, CA PI delay=36
6710 12:26:51.245117
6711 12:26:51.247787 [CBTSetCACLKResult] CA Dly = 36
6712 12:26:51.251416 CS Dly: 1 (0~32)
6713 12:26:51.251857
6714 12:26:51.254677 ----->DramcWriteLeveling(PI) begin...
6715 12:26:51.255186 ==
6716 12:26:51.257935 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 12:26:51.261097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 12:26:51.261544 ==
6719 12:26:51.264346 Write leveling (Byte 0): 40 => 8
6720 12:26:51.268232 Write leveling (Byte 1): 40 => 8
6721 12:26:51.271142 DramcWriteLeveling(PI) end<-----
6722 12:26:51.271589
6723 12:26:51.272030 ==
6724 12:26:51.274143 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 12:26:51.278050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 12:26:51.278500 ==
6727 12:26:51.281156 [Gating] SW mode calibration
6728 12:26:51.287992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6729 12:26:51.294236 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6730 12:26:51.297290 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6731 12:26:51.301112 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 12:26:51.307399 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 12:26:51.310465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 12:26:51.314231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 12:26:51.320625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 12:26:51.323954 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 12:26:51.327406 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 12:26:51.333895 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 12:26:51.337308 Total UI for P1: 0, mck2ui 16
6740 12:26:51.340383 best dqsien dly found for B0: ( 0, 14, 24)
6741 12:26:51.344183 Total UI for P1: 0, mck2ui 16
6742 12:26:51.347199 best dqsien dly found for B1: ( 0, 14, 24)
6743 12:26:51.350353 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6744 12:26:51.353461 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6745 12:26:51.353903
6746 12:26:51.357209 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6747 12:26:51.360208 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 12:26:51.363388 [Gating] SW calibration Done
6749 12:26:51.363847 ==
6750 12:26:51.367167 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 12:26:51.370434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 12:26:51.371056 ==
6753 12:26:51.373565 RX Vref Scan: 0
6754 12:26:51.374026
6755 12:26:51.377035 RX Vref 0 -> 0, step: 1
6756 12:26:51.377597
6757 12:26:51.378053 RX Delay -410 -> 252, step: 16
6758 12:26:51.383547 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6759 12:26:51.386519 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6760 12:26:51.390266 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6761 12:26:51.396688 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6762 12:26:51.399772 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6763 12:26:51.403035 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6764 12:26:51.406858 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6765 12:26:51.413107 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6766 12:26:51.416650 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6767 12:26:51.419503 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6768 12:26:51.423324 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6769 12:26:51.429389 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6770 12:26:51.433114 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6771 12:26:51.436588 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6772 12:26:51.439635 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6773 12:26:51.446426 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6774 12:26:51.447068 ==
6775 12:26:51.449303 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 12:26:51.453030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 12:26:51.453656 ==
6778 12:26:51.454148 DQS Delay:
6779 12:26:51.456084 DQS0 = 51, DQS1 = 67
6780 12:26:51.456572 DQM Delay:
6781 12:26:51.459816 DQM0 = 13, DQM1 = 18
6782 12:26:51.460248 DQ Delay:
6783 12:26:51.462801 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6784 12:26:51.465840 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6785 12:26:51.469052 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6786 12:26:51.472738 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6787 12:26:51.473163
6788 12:26:51.473501
6789 12:26:51.473978 ==
6790 12:26:51.475949 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 12:26:51.478901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 12:26:51.479328 ==
6793 12:26:51.482748
6794 12:26:51.483212
6795 12:26:51.483553 TX Vref Scan disable
6796 12:26:51.485958 == TX Byte 0 ==
6797 12:26:51.488932 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 12:26:51.492600 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 12:26:51.495662 == TX Byte 1 ==
6800 12:26:51.498748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 12:26:51.501948 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 12:26:51.502374 ==
6803 12:26:51.505148 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 12:26:51.512187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:26:51.512650 ==
6806 12:26:51.512995
6807 12:26:51.513496
6808 12:26:51.514038 TX Vref Scan disable
6809 12:26:51.515238 == TX Byte 0 ==
6810 12:26:51.518409 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 12:26:51.522162 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 12:26:51.525234 == TX Byte 1 ==
6813 12:26:51.528457 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 12:26:51.531629 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 12:26:51.532057
6816 12:26:51.534924 [DATLAT]
6817 12:26:51.535377 Freq=400, CH1 RK0
6818 12:26:51.535713
6819 12:26:51.538327 DATLAT Default: 0xf
6820 12:26:51.538752 0, 0xFFFF, sum = 0
6821 12:26:51.541893 1, 0xFFFF, sum = 0
6822 12:26:51.542322 2, 0xFFFF, sum = 0
6823 12:26:51.544803 3, 0xFFFF, sum = 0
6824 12:26:51.545254 4, 0xFFFF, sum = 0
6825 12:26:51.548338 5, 0xFFFF, sum = 0
6826 12:26:51.548771 6, 0xFFFF, sum = 0
6827 12:26:51.551391 7, 0xFFFF, sum = 0
6828 12:26:51.551821 8, 0xFFFF, sum = 0
6829 12:26:51.555047 9, 0xFFFF, sum = 0
6830 12:26:51.555477 10, 0xFFFF, sum = 0
6831 12:26:51.558426 11, 0xFFFF, sum = 0
6832 12:26:51.561412 12, 0xFFFF, sum = 0
6833 12:26:51.561858 13, 0x0, sum = 1
6834 12:26:51.564560 14, 0x0, sum = 2
6835 12:26:51.564999 15, 0x0, sum = 3
6836 12:26:51.565403 16, 0x0, sum = 4
6837 12:26:51.568269 best_step = 14
6838 12:26:51.568694
6839 12:26:51.569033 ==
6840 12:26:51.571295 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 12:26:51.574445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 12:26:51.574916 ==
6843 12:26:51.577664 RX Vref Scan: 1
6844 12:26:51.578102
6845 12:26:51.581427 RX Vref 0 -> 0, step: 1
6846 12:26:51.581869
6847 12:26:51.582314 RX Delay -375 -> 252, step: 8
6848 12:26:51.582731
6849 12:26:51.584506 Set Vref, RX VrefLevel [Byte0]: 54
6850 12:26:51.587622 [Byte1]: 46
6851 12:26:51.593156
6852 12:26:51.593602 Final RX Vref Byte 0 = 54 to rank0
6853 12:26:51.596646 Final RX Vref Byte 1 = 46 to rank0
6854 12:26:51.599595 Final RX Vref Byte 0 = 54 to rank1
6855 12:26:51.603329 Final RX Vref Byte 1 = 46 to rank1==
6856 12:26:51.606571 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 12:26:51.612831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 12:26:51.613275 ==
6859 12:26:51.613718 DQS Delay:
6860 12:26:51.615983 DQS0 = 52, DQS1 = 68
6861 12:26:51.616425 DQM Delay:
6862 12:26:51.616868 DQM0 = 9, DQM1 = 13
6863 12:26:51.619723 DQ Delay:
6864 12:26:51.622918 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6865 12:26:51.625871 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6866 12:26:51.626606 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6867 12:26:51.629584 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6868 12:26:51.632666
6869 12:26:51.633174
6870 12:26:51.639662 [DQSOSCAuto] RK0, (LSB)MR18= 0x596c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6871 12:26:51.642605 CH1 RK0: MR19=C0C, MR18=596C
6872 12:26:51.649351 CH1_RK0: MR19=0xC0C, MR18=0x596C, DQSOSC=396, MR23=63, INC=376, DEC=251
6873 12:26:51.649885 ==
6874 12:26:51.652398 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 12:26:51.656051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 12:26:51.656479 ==
6877 12:26:51.659121 [Gating] SW mode calibration
6878 12:26:51.665478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6879 12:26:51.671859 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6880 12:26:51.675325 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6881 12:26:51.678932 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 12:26:51.685672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 12:26:51.688846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 12:26:51.692092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 12:26:51.698416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 12:26:51.702009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 12:26:51.705067 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 12:26:51.712165 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 12:26:51.712707 Total UI for P1: 0, mck2ui 16
6890 12:26:51.718412 best dqsien dly found for B0: ( 0, 14, 24)
6891 12:26:51.718927 Total UI for P1: 0, mck2ui 16
6892 12:26:51.725333 best dqsien dly found for B1: ( 0, 14, 24)
6893 12:26:51.728548 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6894 12:26:51.731495 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6895 12:26:51.731974
6896 12:26:51.735213 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6897 12:26:51.738323 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 12:26:51.741512 [Gating] SW calibration Done
6899 12:26:51.742082 ==
6900 12:26:51.744631 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 12:26:51.747834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 12:26:51.748312 ==
6903 12:26:51.751892 RX Vref Scan: 0
6904 12:26:51.752452
6905 12:26:51.754779 RX Vref 0 -> 0, step: 1
6906 12:26:51.755459
6907 12:26:51.756056 RX Delay -410 -> 252, step: 16
6908 12:26:51.761109 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6909 12:26:51.764931 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6910 12:26:51.767850 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6911 12:26:51.774703 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6912 12:26:51.777676 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6913 12:26:51.781025 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6914 12:26:51.784235 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6915 12:26:51.790882 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6916 12:26:51.794555 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6917 12:26:51.797477 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6918 12:26:51.800739 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6919 12:26:51.807302 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6920 12:26:51.810998 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6921 12:26:51.814189 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6922 12:26:51.817299 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6923 12:26:51.824110 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6924 12:26:51.824540 ==
6925 12:26:51.827353 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 12:26:51.830491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 12:26:51.831028 ==
6928 12:26:51.831413 DQS Delay:
6929 12:26:51.834213 DQS0 = 51, DQS1 = 59
6930 12:26:51.834684 DQM Delay:
6931 12:26:51.837150 DQM0 = 12, DQM1 = 12
6932 12:26:51.837618 DQ Delay:
6933 12:26:51.840559 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6934 12:26:51.844178 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6935 12:26:51.847262 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6936 12:26:51.850241 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6937 12:26:51.850713
6938 12:26:51.851163
6939 12:26:51.851518 ==
6940 12:26:51.853371 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 12:26:51.857045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 12:26:51.857526 ==
6943 12:26:51.860089
6944 12:26:51.860512
6945 12:26:51.860850 TX Vref Scan disable
6946 12:26:51.863240 == TX Byte 0 ==
6947 12:26:51.866871 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6948 12:26:51.869990 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6949 12:26:51.873434 == TX Byte 1 ==
6950 12:26:51.876510 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6951 12:26:51.880084 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6952 12:26:51.880574 ==
6953 12:26:51.882971 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 12:26:51.886502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 12:26:51.890138 ==
6956 12:26:51.890632
6957 12:26:51.891027
6958 12:26:51.891349 TX Vref Scan disable
6959 12:26:51.893166 == TX Byte 0 ==
6960 12:26:51.896266 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6961 12:26:51.899873 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6962 12:26:51.903009 == TX Byte 1 ==
6963 12:26:51.906360 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6964 12:26:51.909688 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6965 12:26:51.910286
6966 12:26:51.912958 [DATLAT]
6967 12:26:51.913380 Freq=400, CH1 RK1
6968 12:26:51.913753
6969 12:26:51.916134 DATLAT Default: 0xe
6970 12:26:51.916555 0, 0xFFFF, sum = 0
6971 12:26:51.919279 1, 0xFFFF, sum = 0
6972 12:26:51.919708 2, 0xFFFF, sum = 0
6973 12:26:51.922564 3, 0xFFFF, sum = 0
6974 12:26:51.923149 4, 0xFFFF, sum = 0
6975 12:26:51.926070 5, 0xFFFF, sum = 0
6976 12:26:51.926529 6, 0xFFFF, sum = 0
6977 12:26:51.929245 7, 0xFFFF, sum = 0
6978 12:26:51.929672 8, 0xFFFF, sum = 0
6979 12:26:51.932387 9, 0xFFFF, sum = 0
6980 12:26:51.932817 10, 0xFFFF, sum = 0
6981 12:26:51.935439 11, 0xFFFF, sum = 0
6982 12:26:51.939318 12, 0xFFFF, sum = 0
6983 12:26:51.939749 13, 0x0, sum = 1
6984 12:26:51.942151 14, 0x0, sum = 2
6985 12:26:51.942580 15, 0x0, sum = 3
6986 12:26:51.942964 16, 0x0, sum = 4
6987 12:26:51.945899 best_step = 14
6988 12:26:51.946316
6989 12:26:51.946645 ==
6990 12:26:51.949120 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 12:26:51.952261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 12:26:51.952687 ==
6993 12:26:51.955447 RX Vref Scan: 0
6994 12:26:51.955866
6995 12:26:51.956199 RX Vref 0 -> 0, step: 1
6996 12:26:51.958669
6997 12:26:51.959128 RX Delay -359 -> 252, step: 8
6998 12:26:51.967419 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6999 12:26:51.970575 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7000 12:26:51.974510 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7001 12:26:51.980782 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7002 12:26:51.983678 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7003 12:26:51.987332 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7004 12:26:51.990207 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7005 12:26:51.996831 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7006 12:26:52.000353 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7007 12:26:52.003412 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7008 12:26:52.006575 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
7009 12:26:52.013281 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7010 12:26:52.016707 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7011 12:26:52.020354 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7012 12:26:52.023350 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7013 12:26:52.030314 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7014 12:26:52.030738 ==
7015 12:26:52.033435 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 12:26:52.036563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 12:26:52.036989 ==
7018 12:26:52.037326 DQS Delay:
7019 12:26:52.040137 DQS0 = 60, DQS1 = 64
7020 12:26:52.040671 DQM Delay:
7021 12:26:52.042947 DQM0 = 13, DQM1 = 10
7022 12:26:52.043367 DQ Delay:
7023 12:26:52.046442 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7024 12:26:52.049641 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7025 12:26:52.053232 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7026 12:26:52.056361 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7027 12:26:52.056891
7028 12:26:52.057228
7029 12:26:52.066393 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7030 12:26:52.066982 CH1 RK1: MR19=C0C, MR18=75A5
7031 12:26:52.072609 CH1_RK1: MR19=0xC0C, MR18=0x75A5, DQSOSC=389, MR23=63, INC=390, DEC=260
7032 12:26:52.076302 [RxdqsGatingPostProcess] freq 400
7033 12:26:52.082723 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7034 12:26:52.086267 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 12:26:52.089373 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 12:26:52.092854 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 12:26:52.095939 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 12:26:52.099393 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 12:26:52.099963 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 12:26:52.102443 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 12:26:52.105940 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 12:26:52.108942 Pre-setting of DQS Precalculation
7043 12:26:52.115983 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7044 12:26:52.121994 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7045 12:26:52.129064 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7046 12:26:52.129586
7047 12:26:52.129934
7048 12:26:52.132200 [Calibration Summary] 800 Mbps
7049 12:26:52.135273 CH 0, Rank 0
7050 12:26:52.135740 SW Impedance : PASS
7051 12:26:52.139095 DUTY Scan : NO K
7052 12:26:52.142295 ZQ Calibration : PASS
7053 12:26:52.142891 Jitter Meter : NO K
7054 12:26:52.145424 CBT Training : PASS
7055 12:26:52.146074 Write leveling : PASS
7056 12:26:52.148443 RX DQS gating : PASS
7057 12:26:52.152066 RX DQ/DQS(RDDQC) : PASS
7058 12:26:52.152531 TX DQ/DQS : PASS
7059 12:26:52.155322 RX DATLAT : PASS
7060 12:26:52.158382 RX DQ/DQS(Engine): PASS
7061 12:26:52.158978 TX OE : NO K
7062 12:26:52.161555 All Pass.
7063 12:26:52.162105
7064 12:26:52.162578 CH 0, Rank 1
7065 12:26:52.164801 SW Impedance : PASS
7066 12:26:52.165390 DUTY Scan : NO K
7067 12:26:52.168693 ZQ Calibration : PASS
7068 12:26:52.171749 Jitter Meter : NO K
7069 12:26:52.172289 CBT Training : PASS
7070 12:26:52.174912 Write leveling : NO K
7071 12:26:52.178160 RX DQS gating : PASS
7072 12:26:52.178717 RX DQ/DQS(RDDQC) : PASS
7073 12:26:52.181307 TX DQ/DQS : PASS
7074 12:26:52.184459 RX DATLAT : PASS
7075 12:26:52.185017 RX DQ/DQS(Engine): PASS
7076 12:26:52.187789 TX OE : NO K
7077 12:26:52.188346 All Pass.
7078 12:26:52.188825
7079 12:26:52.191517 CH 1, Rank 0
7080 12:26:52.191944 SW Impedance : PASS
7081 12:26:52.194567 DUTY Scan : NO K
7082 12:26:52.198133 ZQ Calibration : PASS
7083 12:26:52.198596 Jitter Meter : NO K
7084 12:26:52.201062 CBT Training : PASS
7085 12:26:52.204499 Write leveling : PASS
7086 12:26:52.205014 RX DQS gating : PASS
7087 12:26:52.207882 RX DQ/DQS(RDDQC) : PASS
7088 12:26:52.211333 TX DQ/DQS : PASS
7089 12:26:52.211756 RX DATLAT : PASS
7090 12:26:52.214251 RX DQ/DQS(Engine): PASS
7091 12:26:52.217635 TX OE : NO K
7092 12:26:52.218058 All Pass.
7093 12:26:52.218391
7094 12:26:52.218700 CH 1, Rank 1
7095 12:26:52.220852 SW Impedance : PASS
7096 12:26:52.224541 DUTY Scan : NO K
7097 12:26:52.224976 ZQ Calibration : PASS
7098 12:26:52.227599 Jitter Meter : NO K
7099 12:26:52.231074 CBT Training : PASS
7100 12:26:52.231515 Write leveling : NO K
7101 12:26:52.234151 RX DQS gating : PASS
7102 12:26:52.234594 RX DQ/DQS(RDDQC) : PASS
7103 12:26:52.237668 TX DQ/DQS : PASS
7104 12:26:52.240573 RX DATLAT : PASS
7105 12:26:52.241017 RX DQ/DQS(Engine): PASS
7106 12:26:52.244283 TX OE : NO K
7107 12:26:52.244725 All Pass.
7108 12:26:52.245165
7109 12:26:52.247386 DramC Write-DBI off
7110 12:26:52.250595 PER_BANK_REFRESH: Hybrid Mode
7111 12:26:52.251086 TX_TRACKING: ON
7112 12:26:52.260467 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7113 12:26:52.264173 [FAST_K] Save calibration result to emmc
7114 12:26:52.267288 dramc_set_vcore_voltage set vcore to 725000
7115 12:26:52.270516 Read voltage for 1600, 0
7116 12:26:52.270983 Vio18 = 0
7117 12:26:52.273614 Vcore = 725000
7118 12:26:52.274053 Vdram = 0
7119 12:26:52.274492 Vddq = 0
7120 12:26:52.275037 Vmddr = 0
7121 12:26:52.279910 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7122 12:26:52.286818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7123 12:26:52.287305 MEM_TYPE=3, freq_sel=13
7124 12:26:52.290018 sv_algorithm_assistance_LP4_3733
7125 12:26:52.296748 ============ PULL DRAM RESETB DOWN ============
7126 12:26:52.299917 ========== PULL DRAM RESETB DOWN end =========
7127 12:26:52.303013 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7128 12:26:52.306094 ===================================
7129 12:26:52.309781 LPDDR4 DRAM CONFIGURATION
7130 12:26:52.312903 ===================================
7131 12:26:52.313341 EX_ROW_EN[0] = 0x0
7132 12:26:52.316243 EX_ROW_EN[1] = 0x0
7133 12:26:52.319743 LP4Y_EN = 0x0
7134 12:26:52.320193 WORK_FSP = 0x1
7135 12:26:52.322757 WL = 0x5
7136 12:26:52.323242 RL = 0x5
7137 12:26:52.326316 BL = 0x2
7138 12:26:52.326739 RPST = 0x0
7139 12:26:52.329080 RD_PRE = 0x0
7140 12:26:52.329551 WR_PRE = 0x1
7141 12:26:52.333002 WR_PST = 0x1
7142 12:26:52.333429 DBI_WR = 0x0
7143 12:26:52.335912 DBI_RD = 0x0
7144 12:26:52.336382 OTF = 0x1
7145 12:26:52.339634 ===================================
7146 12:26:52.342754 ===================================
7147 12:26:52.346251 ANA top config
7148 12:26:52.349388 ===================================
7149 12:26:52.352597 DLL_ASYNC_EN = 0
7150 12:26:52.353022 ALL_SLAVE_EN = 0
7151 12:26:52.355653 NEW_RANK_MODE = 1
7152 12:26:52.358952 DLL_IDLE_MODE = 1
7153 12:26:52.362608 LP45_APHY_COMB_EN = 1
7154 12:26:52.363063 TX_ODT_DIS = 0
7155 12:26:52.365723 NEW_8X_MODE = 1
7156 12:26:52.368861 ===================================
7157 12:26:52.372086 ===================================
7158 12:26:52.375811 data_rate = 3200
7159 12:26:52.378931 CKR = 1
7160 12:26:52.381973 DQ_P2S_RATIO = 8
7161 12:26:52.386036 ===================================
7162 12:26:52.389003 CA_P2S_RATIO = 8
7163 12:26:52.389433 DQ_CA_OPEN = 0
7164 12:26:52.391944 DQ_SEMI_OPEN = 0
7165 12:26:52.395803 CA_SEMI_OPEN = 0
7166 12:26:52.398868 CA_FULL_RATE = 0
7167 12:26:52.401973 DQ_CKDIV4_EN = 0
7168 12:26:52.405029 CA_CKDIV4_EN = 0
7169 12:26:52.408931 CA_PREDIV_EN = 0
7170 12:26:52.409354 PH8_DLY = 12
7171 12:26:52.412034 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7172 12:26:52.415310 DQ_AAMCK_DIV = 4
7173 12:26:52.418506 CA_AAMCK_DIV = 4
7174 12:26:52.421572 CA_ADMCK_DIV = 4
7175 12:26:52.425093 DQ_TRACK_CA_EN = 0
7176 12:26:52.425571 CA_PICK = 1600
7177 12:26:52.428357 CA_MCKIO = 1600
7178 12:26:52.431885 MCKIO_SEMI = 0
7179 12:26:52.435251 PLL_FREQ = 3068
7180 12:26:52.438059 DQ_UI_PI_RATIO = 32
7181 12:26:52.441855 CA_UI_PI_RATIO = 0
7182 12:26:52.444849 ===================================
7183 12:26:52.448375 ===================================
7184 12:26:52.451504 memory_type:LPDDR4
7185 12:26:52.451934 GP_NUM : 10
7186 12:26:52.455090 SRAM_EN : 1
7187 12:26:52.455521 MD32_EN : 0
7188 12:26:52.458047 ===================================
7189 12:26:52.461260 [ANA_INIT] >>>>>>>>>>>>>>
7190 12:26:52.464782 <<<<<< [CONFIGURE PHASE]: ANA_TX
7191 12:26:52.468222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7192 12:26:52.471377 ===================================
7193 12:26:52.474665 data_rate = 3200,PCW = 0X7600
7194 12:26:52.478366 ===================================
7195 12:26:52.481773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7196 12:26:52.487508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7197 12:26:52.491351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 12:26:52.497735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7199 12:26:52.500813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7200 12:26:52.504033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7201 12:26:52.504483 [ANA_INIT] flow start
7202 12:26:52.507668 [ANA_INIT] PLL >>>>>>>>
7203 12:26:52.510760 [ANA_INIT] PLL <<<<<<<<
7204 12:26:52.511244 [ANA_INIT] MIDPI >>>>>>>>
7205 12:26:52.514017 [ANA_INIT] MIDPI <<<<<<<<
7206 12:26:52.517928 [ANA_INIT] DLL >>>>>>>>
7207 12:26:52.518397 [ANA_INIT] DLL <<<<<<<<
7208 12:26:52.521028 [ANA_INIT] flow end
7209 12:26:52.524166 ============ LP4 DIFF to SE enter ============
7210 12:26:52.530806 ============ LP4 DIFF to SE exit ============
7211 12:26:52.531455 [ANA_INIT] <<<<<<<<<<<<<
7212 12:26:52.534304 [Flow] Enable top DCM control >>>>>
7213 12:26:52.537172 [Flow] Enable top DCM control <<<<<
7214 12:26:52.540868 Enable DLL master slave shuffle
7215 12:26:52.547090 ==============================================================
7216 12:26:52.547528 Gating Mode config
7217 12:26:52.553774 ==============================================================
7218 12:26:52.557411 Config description:
7219 12:26:52.567004 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7220 12:26:52.573868 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7221 12:26:52.577107 SELPH_MODE 0: By rank 1: By Phase
7222 12:26:52.583358 ==============================================================
7223 12:26:52.586585 GAT_TRACK_EN = 1
7224 12:26:52.590219 RX_GATING_MODE = 2
7225 12:26:52.590694 RX_GATING_TRACK_MODE = 2
7226 12:26:52.593264 SELPH_MODE = 1
7227 12:26:52.596513 PICG_EARLY_EN = 1
7228 12:26:52.600190 VALID_LAT_VALUE = 1
7229 12:26:52.606559 ==============================================================
7230 12:26:52.609666 Enter into Gating configuration >>>>
7231 12:26:52.612786 Exit from Gating configuration <<<<
7232 12:26:52.616117 Enter into DVFS_PRE_config >>>>>
7233 12:26:52.626237 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7234 12:26:52.629408 Exit from DVFS_PRE_config <<<<<
7235 12:26:52.633066 Enter into PICG configuration >>>>
7236 12:26:52.636215 Exit from PICG configuration <<<<
7237 12:26:52.639389 [RX_INPUT] configuration >>>>>
7238 12:26:52.642323 [RX_INPUT] configuration <<<<<
7239 12:26:52.645854 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7240 12:26:52.652416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7241 12:26:52.658994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 12:26:52.665782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 12:26:52.671738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 12:26:52.678771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 12:26:52.681934 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7246 12:26:52.685143 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7247 12:26:52.688333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7248 12:26:52.695175 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7249 12:26:52.698292 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7250 12:26:52.701260 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 12:26:52.704947 ===================================
7252 12:26:52.708065 LPDDR4 DRAM CONFIGURATION
7253 12:26:52.711213 ===================================
7254 12:26:52.714537 EX_ROW_EN[0] = 0x0
7255 12:26:52.715136 EX_ROW_EN[1] = 0x0
7256 12:26:52.718166 LP4Y_EN = 0x0
7257 12:26:52.718639 WORK_FSP = 0x1
7258 12:26:52.721303 WL = 0x5
7259 12:26:52.721860 RL = 0x5
7260 12:26:52.724517 BL = 0x2
7261 12:26:52.724992 RPST = 0x0
7262 12:26:52.727673 RD_PRE = 0x0
7263 12:26:52.728150 WR_PRE = 0x1
7264 12:26:52.731302 WR_PST = 0x1
7265 12:26:52.731797 DBI_WR = 0x0
7266 12:26:52.734857 DBI_RD = 0x0
7267 12:26:52.735338 OTF = 0x1
7268 12:26:52.737706 ===================================
7269 12:26:52.744568 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7270 12:26:52.747330 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7271 12:26:52.750983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 12:26:52.754454 ===================================
7273 12:26:52.757469 LPDDR4 DRAM CONFIGURATION
7274 12:26:52.760983 ===================================
7275 12:26:52.763825 EX_ROW_EN[0] = 0x10
7276 12:26:52.764296 EX_ROW_EN[1] = 0x0
7277 12:26:52.767497 LP4Y_EN = 0x0
7278 12:26:52.767988 WORK_FSP = 0x1
7279 12:26:52.770557 WL = 0x5
7280 12:26:52.771071 RL = 0x5
7281 12:26:52.774182 BL = 0x2
7282 12:26:52.774648 RPST = 0x0
7283 12:26:52.777084 RD_PRE = 0x0
7284 12:26:52.777555 WR_PRE = 0x1
7285 12:26:52.780467 WR_PST = 0x1
7286 12:26:52.780937 DBI_WR = 0x0
7287 12:26:52.783968 DBI_RD = 0x0
7288 12:26:52.784482 OTF = 0x1
7289 12:26:52.786810 ===================================
7290 12:26:52.793871 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7291 12:26:52.794445 ==
7292 12:26:52.797074 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 12:26:52.803638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 12:26:52.804186 ==
7295 12:26:52.804566 [Duty_Offset_Calibration]
7296 12:26:52.806740 B0:2 B1:0 CA:3
7297 12:26:52.807256
7298 12:26:52.810257 [DutyScan_Calibration_Flow] k_type=0
7299 12:26:52.819560
7300 12:26:52.820142 ==CLK 0==
7301 12:26:52.822884 Final CLK duty delay cell = 0
7302 12:26:52.826198 [0] MAX Duty = 5031%(X100), DQS PI = 12
7303 12:26:52.830023 [0] MIN Duty = 4907%(X100), DQS PI = 6
7304 12:26:52.830616 [0] AVG Duty = 4969%(X100)
7305 12:26:52.833055
7306 12:26:52.836177 CH0 CLK Duty spec in!! Max-Min= 124%
7307 12:26:52.839328 [DutyScan_Calibration_Flow] ====Done====
7308 12:26:52.839819
7309 12:26:52.842393 [DutyScan_Calibration_Flow] k_type=1
7310 12:26:52.859783
7311 12:26:52.860343 ==DQS 0 ==
7312 12:26:52.863015 Final DQS duty delay cell = 0
7313 12:26:52.866134 [0] MAX Duty = 5125%(X100), DQS PI = 30
7314 12:26:52.869763 [0] MIN Duty = 4875%(X100), DQS PI = 48
7315 12:26:52.873042 [0] AVG Duty = 5000%(X100)
7316 12:26:52.873513
7317 12:26:52.873883 ==DQS 1 ==
7318 12:26:52.876150 Final DQS duty delay cell = 0
7319 12:26:52.879225 [0] MAX Duty = 5156%(X100), DQS PI = 32
7320 12:26:52.882675 [0] MIN Duty = 5031%(X100), DQS PI = 12
7321 12:26:52.886083 [0] AVG Duty = 5093%(X100)
7322 12:26:52.886709
7323 12:26:52.889148 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7324 12:26:52.889619
7325 12:26:52.892806 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7326 12:26:52.896164 [DutyScan_Calibration_Flow] ====Done====
7327 12:26:52.896638
7328 12:26:52.898994 [DutyScan_Calibration_Flow] k_type=3
7329 12:26:52.917783
7330 12:26:52.918325 ==DQM 0 ==
7331 12:26:52.920833 Final DQM duty delay cell = 0
7332 12:26:52.924038 [0] MAX Duty = 5156%(X100), DQS PI = 32
7333 12:26:52.927695 [0] MIN Duty = 4875%(X100), DQS PI = 48
7334 12:26:52.930965 [0] AVG Duty = 5015%(X100)
7335 12:26:52.931698
7336 12:26:52.932091 ==DQM 1 ==
7337 12:26:52.933982 Final DQM duty delay cell = 4
7338 12:26:52.937242 [4] MAX Duty = 5187%(X100), DQS PI = 62
7339 12:26:52.940392 [4] MIN Duty = 5031%(X100), DQS PI = 14
7340 12:26:52.944099 [4] AVG Duty = 5109%(X100)
7341 12:26:52.944569
7342 12:26:52.947170 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7343 12:26:52.947644
7344 12:26:52.950408 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7345 12:26:52.954161 [DutyScan_Calibration_Flow] ====Done====
7346 12:26:52.954627
7347 12:26:52.957192 [DutyScan_Calibration_Flow] k_type=2
7348 12:26:52.974196
7349 12:26:52.974667 ==DQ 0 ==
7350 12:26:52.977070 Final DQ duty delay cell = -4
7351 12:26:52.980394 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7352 12:26:52.983637 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7353 12:26:52.987306 [-4] AVG Duty = 4938%(X100)
7354 12:26:52.987793
7355 12:26:52.988250 ==DQ 1 ==
7356 12:26:52.990425 Final DQ duty delay cell = 0
7357 12:26:52.993916 [0] MAX Duty = 5156%(X100), DQS PI = 60
7358 12:26:52.996927 [0] MIN Duty = 5000%(X100), DQS PI = 14
7359 12:26:53.000567 [0] AVG Duty = 5078%(X100)
7360 12:26:53.000990
7361 12:26:53.003650 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7362 12:26:53.004122
7363 12:26:53.006691 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7364 12:26:53.010349 [DutyScan_Calibration_Flow] ====Done====
7365 12:26:53.011008 ==
7366 12:26:53.013542 Dram Type= 6, Freq= 0, CH_1, rank 0
7367 12:26:53.016751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7368 12:26:53.017204 ==
7369 12:26:53.019947 [Duty_Offset_Calibration]
7370 12:26:53.020382 B0:1 B1:-2 CA:0
7371 12:26:53.020866
7372 12:26:53.023239 [DutyScan_Calibration_Flow] k_type=0
7373 12:26:53.034790
7374 12:26:53.035458 ==CLK 0==
7375 12:26:53.037985 Final CLK duty delay cell = 0
7376 12:26:53.041171 [0] MAX Duty = 5062%(X100), DQS PI = 20
7377 12:26:53.044744 [0] MIN Duty = 4844%(X100), DQS PI = 58
7378 12:26:53.047624 [0] AVG Duty = 4953%(X100)
7379 12:26:53.048122
7380 12:26:53.051431 CH1 CLK Duty spec in!! Max-Min= 218%
7381 12:26:53.054503 [DutyScan_Calibration_Flow] ====Done====
7382 12:26:53.055102
7383 12:26:53.057766 [DutyScan_Calibration_Flow] k_type=1
7384 12:26:53.073328
7385 12:26:53.073966 ==DQS 0 ==
7386 12:26:53.077060 Final DQS duty delay cell = -4
7387 12:26:53.080018 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7388 12:26:53.083710 [-4] MIN Duty = 4844%(X100), DQS PI = 44
7389 12:26:53.086529 [-4] AVG Duty = 4906%(X100)
7390 12:26:53.087171
7391 12:26:53.087715 ==DQS 1 ==
7392 12:26:53.089870 Final DQS duty delay cell = 0
7393 12:26:53.093191 [0] MAX Duty = 5093%(X100), DQS PI = 58
7394 12:26:53.096677 [0] MIN Duty = 4844%(X100), DQS PI = 24
7395 12:26:53.099631 [0] AVG Duty = 4968%(X100)
7396 12:26:53.100068
7397 12:26:53.103127 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7398 12:26:53.103566
7399 12:26:53.106256 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7400 12:26:53.109926 [DutyScan_Calibration_Flow] ====Done====
7401 12:26:53.110348
7402 12:26:53.113016 [DutyScan_Calibration_Flow] k_type=3
7403 12:26:53.130636
7404 12:26:53.131134 ==DQM 0 ==
7405 12:26:53.134356 Final DQM duty delay cell = 0
7406 12:26:53.137612 [0] MAX Duty = 5031%(X100), DQS PI = 24
7407 12:26:53.140653 [0] MIN Duty = 4813%(X100), DQS PI = 54
7408 12:26:53.143897 [0] AVG Duty = 4922%(X100)
7409 12:26:53.144371
7410 12:26:53.144748 ==DQM 1 ==
7411 12:26:53.147141 Final DQM duty delay cell = 0
7412 12:26:53.150821 [0] MAX Duty = 5062%(X100), DQS PI = 34
7413 12:26:53.153964 [0] MIN Duty = 4875%(X100), DQS PI = 24
7414 12:26:53.157050 [0] AVG Duty = 4968%(X100)
7415 12:26:53.157480
7416 12:26:53.160219 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7417 12:26:53.160648
7418 12:26:53.163342 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7419 12:26:53.167261 [DutyScan_Calibration_Flow] ====Done====
7420 12:26:53.167826
7421 12:26:53.170251 [DutyScan_Calibration_Flow] k_type=2
7422 12:26:53.187733
7423 12:26:53.188289 ==DQ 0 ==
7424 12:26:53.191546 Final DQ duty delay cell = 0
7425 12:26:53.194682 [0] MAX Duty = 5093%(X100), DQS PI = 22
7426 12:26:53.197589 [0] MIN Duty = 4938%(X100), DQS PI = 0
7427 12:26:53.198059 [0] AVG Duty = 5015%(X100)
7428 12:26:53.200711
7429 12:26:53.201176 ==DQ 1 ==
7430 12:26:53.204519 Final DQ duty delay cell = 0
7431 12:26:53.207310 [0] MAX Duty = 5125%(X100), DQS PI = 34
7432 12:26:53.210974 [0] MIN Duty = 4938%(X100), DQS PI = 24
7433 12:26:53.211446 [0] AVG Duty = 5031%(X100)
7434 12:26:53.214174
7435 12:26:53.217442 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7436 12:26:53.217912
7437 12:26:53.220871 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7438 12:26:53.223702 [DutyScan_Calibration_Flow] ====Done====
7439 12:26:53.227515 nWR fixed to 30
7440 12:26:53.228063 [ModeRegInit_LP4] CH0 RK0
7441 12:26:53.230660 [ModeRegInit_LP4] CH0 RK1
7442 12:26:53.233732 [ModeRegInit_LP4] CH1 RK0
7443 12:26:53.237047 [ModeRegInit_LP4] CH1 RK1
7444 12:26:53.237517 match AC timing 5
7445 12:26:53.243330 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7446 12:26:53.247164 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7447 12:26:53.250172 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7448 12:26:53.256600 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7449 12:26:53.260359 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7450 12:26:53.260828 [MiockJmeterHQA]
7451 12:26:53.261221
7452 12:26:53.263527 [DramcMiockJmeter] u1RxGatingPI = 0
7453 12:26:53.266825 0 : 4365, 4140
7454 12:26:53.267447 4 : 4253, 4026
7455 12:26:53.269895 8 : 4366, 4140
7456 12:26:53.270369 12 : 4363, 4138
7457 12:26:53.273172 16 : 4363, 4137
7458 12:26:53.273650 20 : 4253, 4027
7459 12:26:53.274028 24 : 4252, 4027
7460 12:26:53.276841 28 : 4252, 4027
7461 12:26:53.277315 32 : 4253, 4027
7462 12:26:53.280047 36 : 4255, 4029
7463 12:26:53.280521 40 : 4363, 4138
7464 12:26:53.283142 44 : 4252, 4027
7465 12:26:53.283618 48 : 4253, 4026
7466 12:26:53.286301 52 : 4252, 4027
7467 12:26:53.286776 56 : 4255, 4029
7468 12:26:53.287195 60 : 4250, 4026
7469 12:26:53.289661 64 : 4361, 4137
7470 12:26:53.290135 68 : 4361, 4137
7471 12:26:53.292938 72 : 4250, 4027
7472 12:26:53.293407 76 : 4250, 4027
7473 12:26:53.296153 80 : 4250, 4027
7474 12:26:53.296237 84 : 4250, 4027
7475 12:26:53.299107 88 : 4253, 4029
7476 12:26:53.299190 92 : 4360, 4138
7477 12:26:53.302084 96 : 4250, 4027
7478 12:26:53.302168 100 : 4250, 4027
7479 12:26:53.302234 104 : 4361, 3888
7480 12:26:53.305718 108 : 4250, 4
7481 12:26:53.305802 112 : 4250, 0
7482 12:26:53.308897 116 : 4252, 0
7483 12:26:53.308981 120 : 4250, 0
7484 12:26:53.309047 124 : 4250, 0
7485 12:26:53.311983 128 : 4250, 0
7486 12:26:53.312067 132 : 4361, 0
7487 12:26:53.315786 136 : 4250, 0
7488 12:26:53.315870 140 : 4360, 0
7489 12:26:53.315936 144 : 4250, 0
7490 12:26:53.318774 148 : 4250, 0
7491 12:26:53.318880 152 : 4250, 0
7492 12:26:53.322291 156 : 4253, 0
7493 12:26:53.322374 160 : 4250, 0
7494 12:26:53.322440 164 : 4250, 0
7495 12:26:53.325842 168 : 4252, 0
7496 12:26:53.325926 172 : 4361, 0
7497 12:26:53.328766 176 : 4250, 0
7498 12:26:53.328850 180 : 4361, 0
7499 12:26:53.328917 184 : 4250, 0
7500 12:26:53.332286 188 : 4250, 0
7501 12:26:53.332389 192 : 4250, 0
7502 12:26:53.332484 196 : 4250, 0
7503 12:26:53.335600 200 : 4250, 0
7504 12:26:53.335684 204 : 4250, 0
7505 12:26:53.338484 208 : 4253, 0
7506 12:26:53.338567 212 : 4250, 0
7507 12:26:53.338634 216 : 4250, 0
7508 12:26:53.342287 220 : 4253, 0
7509 12:26:53.342370 224 : 4361, 0
7510 12:26:53.345378 228 : 4360, 0
7511 12:26:53.345461 232 : 4363, 0
7512 12:26:53.345528 236 : 4250, 1391
7513 12:26:53.348356 240 : 4253, 4029
7514 12:26:53.348440 244 : 4250, 4026
7515 12:26:53.351674 248 : 4250, 4027
7516 12:26:53.351757 252 : 4361, 4137
7517 12:26:53.355485 256 : 4250, 4026
7518 12:26:53.355568 260 : 4250, 4027
7519 12:26:53.358583 264 : 4361, 4137
7520 12:26:53.358666 268 : 4250, 4027
7521 12:26:53.361768 272 : 4250, 4027
7522 12:26:53.361852 276 : 4363, 4139
7523 12:26:53.365091 280 : 4250, 4026
7524 12:26:53.365174 284 : 4250, 4027
7525 12:26:53.368224 288 : 4250, 4027
7526 12:26:53.368311 292 : 4253, 4029
7527 12:26:53.371383 296 : 4250, 4027
7528 12:26:53.371474 300 : 4250, 4027
7529 12:26:53.371540 304 : 4361, 4137
7530 12:26:53.375177 308 : 4250, 4026
7531 12:26:53.375264 312 : 4250, 4027
7532 12:26:53.378278 316 : 4361, 4137
7533 12:26:53.378361 320 : 4250, 4027
7534 12:26:53.381318 324 : 4250, 4027
7535 12:26:53.381420 328 : 4363, 4139
7536 12:26:53.384608 332 : 4250, 4027
7537 12:26:53.384708 336 : 4250, 4027
7538 12:26:53.388354 340 : 4250, 4027
7539 12:26:53.388428 344 : 4253, 4029
7540 12:26:53.391525 348 : 4250, 4027
7541 12:26:53.391608 352 : 4250, 4025
7542 12:26:53.394715 356 : 4361, 2794
7543 12:26:53.394853 360 : 4250, 0
7544 12:26:53.394938
7545 12:26:53.397826 MIOCK jitter meter ch=0
7546 12:26:53.397908
7547 12:26:53.401600 1T = (360-108) = 252 dly cells
7548 12:26:53.404180 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7549 12:26:53.404295 ==
7550 12:26:53.407816 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 12:26:53.414479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 12:26:53.414589 ==
7553 12:26:53.417594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 12:26:53.424293 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 12:26:53.427284 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 12:26:53.433719 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 12:26:53.442281 [CA 0] Center 43 (13~74) winsize 62
7558 12:26:53.445392 [CA 1] Center 43 (13~74) winsize 62
7559 12:26:53.448557 [CA 2] Center 39 (10~68) winsize 59
7560 12:26:53.452193 [CA 3] Center 39 (10~68) winsize 59
7561 12:26:53.455344 [CA 4] Center 36 (7~66) winsize 60
7562 12:26:53.458484 [CA 5] Center 36 (7~66) winsize 60
7563 12:26:53.458567
7564 12:26:53.461542 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7565 12:26:53.465500
7566 12:26:53.468623 [CATrainingPosCal] consider 1 rank data
7567 12:26:53.468712 u2DelayCellTimex100 = 258/100 ps
7568 12:26:53.475349 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7569 12:26:53.478441 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7570 12:26:53.482139 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7571 12:26:53.485448 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7572 12:26:53.488615 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7573 12:26:53.491653 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7574 12:26:53.492108
7575 12:26:53.495315 CA PerBit enable=1, Macro0, CA PI delay=36
7576 12:26:53.498365
7577 12:26:53.498786 [CBTSetCACLKResult] CA Dly = 36
7578 12:26:53.501505 CS Dly: 11 (0~42)
7579 12:26:53.504469 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 12:26:53.511287 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 12:26:53.511737 ==
7582 12:26:53.514774 Dram Type= 6, Freq= 0, CH_0, rank 1
7583 12:26:53.518210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 12:26:53.518664 ==
7585 12:26:53.521538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7586 12:26:53.528212 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7587 12:26:53.531198 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7588 12:26:53.537648 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7589 12:26:53.546374 [CA 0] Center 43 (13~74) winsize 62
7590 12:26:53.549858 [CA 1] Center 43 (13~74) winsize 62
7591 12:26:53.552943 [CA 2] Center 39 (10~68) winsize 59
7592 12:26:53.556519 [CA 3] Center 39 (10~68) winsize 59
7593 12:26:53.559866 [CA 4] Center 36 (6~66) winsize 61
7594 12:26:53.563057 [CA 5] Center 36 (6~66) winsize 61
7595 12:26:53.563526
7596 12:26:53.566117 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7597 12:26:53.566548
7598 12:26:53.573055 [CATrainingPosCal] consider 2 rank data
7599 12:26:53.573488 u2DelayCellTimex100 = 258/100 ps
7600 12:26:53.579383 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7601 12:26:53.582547 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 12:26:53.586295 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7603 12:26:53.589477 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7604 12:26:53.592701 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7605 12:26:53.595902 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7606 12:26:53.596439
7607 12:26:53.599597 CA PerBit enable=1, Macro0, CA PI delay=36
7608 12:26:53.600026
7609 12:26:53.602724 [CBTSetCACLKResult] CA Dly = 36
7610 12:26:53.605803 CS Dly: 11 (0~43)
7611 12:26:53.609391 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7612 12:26:53.612528 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7613 12:26:53.613022
7614 12:26:53.615806 ----->DramcWriteLeveling(PI) begin...
7615 12:26:53.619687 ==
7616 12:26:53.622213 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 12:26:53.625726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 12:26:53.626161 ==
7619 12:26:53.629076 Write leveling (Byte 0): 36 => 36
7620 12:26:53.632095 Write leveling (Byte 1): 28 => 28
7621 12:26:53.635545 DramcWriteLeveling(PI) end<-----
7622 12:26:53.635979
7623 12:26:53.636325 ==
7624 12:26:53.638709 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 12:26:53.641975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 12:26:53.642061 ==
7627 12:26:53.644955 [Gating] SW mode calibration
7628 12:26:53.651999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7629 12:26:53.658203 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7630 12:26:53.661952 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 12:26:53.664832 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:26:53.671588 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 12:26:53.674675 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 12:26:53.677919 1 4 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7635 12:26:53.684392 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7636 12:26:53.688167 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7637 12:26:53.691256 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 12:26:53.697629 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 12:26:53.700650 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 12:26:53.704487 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 12:26:53.710767 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7642 12:26:53.713815 1 5 16 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7643 12:26:53.717579 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7644 12:26:53.723969 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7645 12:26:53.727608 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 12:26:53.730446 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 12:26:53.737289 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 12:26:53.740734 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 12:26:53.743725 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7650 12:26:53.750373 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7651 12:26:53.753850 1 6 20 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7652 12:26:53.756906 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7653 12:26:53.763902 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 12:26:53.766761 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 12:26:53.770360 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 12:26:53.777128 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 12:26:53.780316 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 12:26:53.783360 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7659 12:26:53.790352 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7660 12:26:53.793723 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7661 12:26:53.796884 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 12:26:53.803358 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 12:26:53.806870 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 12:26:53.809891 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 12:26:53.816748 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 12:26:53.819861 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 12:26:53.822931 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 12:26:53.829812 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:26:53.832965 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:26:53.836940 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:26:53.843002 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:26:53.846461 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:26:53.849834 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 12:26:53.856098 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7675 12:26:53.859716 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7676 12:26:53.862628 Total UI for P1: 0, mck2ui 16
7677 12:26:53.866115 best dqsien dly found for B0: ( 1, 9, 16)
7678 12:26:53.869610 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7679 12:26:53.876228 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7680 12:26:53.879391 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 12:26:53.882519 Total UI for P1: 0, mck2ui 16
7682 12:26:53.886117 best dqsien dly found for B1: ( 1, 9, 24)
7683 12:26:53.889445 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7684 12:26:53.892508 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7685 12:26:53.892951
7686 12:26:53.895718 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7687 12:26:53.898978 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7688 12:26:53.902645 [Gating] SW calibration Done
7689 12:26:53.903126 ==
7690 12:26:53.905692 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 12:26:53.912632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 12:26:53.913077 ==
7693 12:26:53.913607 RX Vref Scan: 0
7694 12:26:53.914029
7695 12:26:53.915790 RX Vref 0 -> 0, step: 1
7696 12:26:53.916230
7697 12:26:53.918900 RX Delay 0 -> 252, step: 8
7698 12:26:53.922509 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7699 12:26:53.925630 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7700 12:26:53.928726 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7701 12:26:53.931975 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7702 12:26:53.938731 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7703 12:26:53.941747 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7704 12:26:53.945541 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7705 12:26:53.948717 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7706 12:26:53.952277 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7707 12:26:53.958685 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7708 12:26:53.961749 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7709 12:26:53.965430 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7710 12:26:53.968574 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7711 12:26:53.975276 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7712 12:26:53.978764 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7713 12:26:53.981534 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7714 12:26:53.982012 ==
7715 12:26:53.985193 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 12:26:53.988274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 12:26:53.988815 ==
7718 12:26:53.991990 DQS Delay:
7719 12:26:53.992546 DQS0 = 0, DQS1 = 0
7720 12:26:53.995023 DQM Delay:
7721 12:26:53.995467 DQM0 = 128, DQM1 = 123
7722 12:26:53.998045 DQ Delay:
7723 12:26:54.001164 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7724 12:26:54.004234 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =139
7725 12:26:54.008146 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7726 12:26:54.011281 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7727 12:26:54.011746
7728 12:26:54.012182
7729 12:26:54.012595 ==
7730 12:26:54.014339 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 12:26:54.017438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 12:26:54.017887 ==
7733 12:26:54.018336
7734 12:26:54.021168
7735 12:26:54.021613 TX Vref Scan disable
7736 12:26:54.024307 == TX Byte 0 ==
7737 12:26:54.027932 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7738 12:26:54.031035 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7739 12:26:54.034179 == TX Byte 1 ==
7740 12:26:54.037308 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7741 12:26:54.041014 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7742 12:26:54.041440 ==
7743 12:26:54.044206 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 12:26:54.051078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 12:26:54.051503 ==
7746 12:26:54.064948
7747 12:26:54.068212 TX Vref early break, caculate TX vref
7748 12:26:54.071196 TX Vref=16, minBit 8, minWin=21, winSum=358
7749 12:26:54.074929 TX Vref=18, minBit 11, minWin=21, winSum=373
7750 12:26:54.078051 TX Vref=20, minBit 8, minWin=22, winSum=378
7751 12:26:54.080925 TX Vref=22, minBit 10, minWin=23, winSum=390
7752 12:26:54.087911 TX Vref=24, minBit 4, minWin=24, winSum=400
7753 12:26:54.090712 TX Vref=26, minBit 8, minWin=24, winSum=408
7754 12:26:54.094275 TX Vref=28, minBit 2, minWin=25, winSum=405
7755 12:26:54.097253 TX Vref=30, minBit 8, minWin=24, winSum=405
7756 12:26:54.101010 TX Vref=32, minBit 8, minWin=23, winSum=395
7757 12:26:54.104198 TX Vref=34, minBit 9, minWin=22, winSum=389
7758 12:26:54.110567 TX Vref=36, minBit 8, minWin=21, winSum=370
7759 12:26:54.113599 [TxChooseVref] Worse bit 2, Min win 25, Win sum 405, Final Vref 28
7760 12:26:54.114130
7761 12:26:54.116606 Final TX Range 0 Vref 28
7762 12:26:54.116714
7763 12:26:54.116807 ==
7764 12:26:54.120235 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 12:26:54.123343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 12:26:54.126424 ==
7767 12:26:54.126506
7768 12:26:54.126571
7769 12:26:54.126631 TX Vref Scan disable
7770 12:26:54.133750 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7771 12:26:54.133834 == TX Byte 0 ==
7772 12:26:54.136831 u2DelayCellOfst[0]=11 cells (3 PI)
7773 12:26:54.140337 u2DelayCellOfst[1]=18 cells (5 PI)
7774 12:26:54.143934 u2DelayCellOfst[2]=7 cells (2 PI)
7775 12:26:54.147114 u2DelayCellOfst[3]=11 cells (3 PI)
7776 12:26:54.150198 u2DelayCellOfst[4]=3 cells (1 PI)
7777 12:26:54.154017 u2DelayCellOfst[5]=0 cells (0 PI)
7778 12:26:54.157239 u2DelayCellOfst[6]=18 cells (5 PI)
7779 12:26:54.160348 u2DelayCellOfst[7]=15 cells (4 PI)
7780 12:26:54.163531 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7781 12:26:54.166675 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7782 12:26:54.170410 == TX Byte 1 ==
7783 12:26:54.173402 u2DelayCellOfst[8]=0 cells (0 PI)
7784 12:26:54.176792 u2DelayCellOfst[9]=3 cells (1 PI)
7785 12:26:54.180417 u2DelayCellOfst[10]=7 cells (2 PI)
7786 12:26:54.183834 u2DelayCellOfst[11]=7 cells (2 PI)
7787 12:26:54.186544 u2DelayCellOfst[12]=15 cells (4 PI)
7788 12:26:54.190163 u2DelayCellOfst[13]=11 cells (3 PI)
7789 12:26:54.190518 u2DelayCellOfst[14]=15 cells (4 PI)
7790 12:26:54.193730 u2DelayCellOfst[15]=11 cells (3 PI)
7791 12:26:54.200186 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7792 12:26:54.203198 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7793 12:26:54.206577 DramC Write-DBI on
7794 12:26:54.207093 ==
7795 12:26:54.210127 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 12:26:54.213209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 12:26:54.213681 ==
7798 12:26:54.214050
7799 12:26:54.214395
7800 12:26:54.216289 TX Vref Scan disable
7801 12:26:54.216757 == TX Byte 0 ==
7802 12:26:54.222941 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7803 12:26:54.223422 == TX Byte 1 ==
7804 12:26:54.226368 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7805 12:26:54.229827 DramC Write-DBI off
7806 12:26:54.230299
7807 12:26:54.230671 [DATLAT]
7808 12:26:54.233082 Freq=1600, CH0 RK0
7809 12:26:54.233596
7810 12:26:54.233980 DATLAT Default: 0xf
7811 12:26:54.235976 0, 0xFFFF, sum = 0
7812 12:26:54.239691 1, 0xFFFF, sum = 0
7813 12:26:54.240177 2, 0xFFFF, sum = 0
7814 12:26:54.242767 3, 0xFFFF, sum = 0
7815 12:26:54.243306 4, 0xFFFF, sum = 0
7816 12:26:54.246331 5, 0xFFFF, sum = 0
7817 12:26:54.246937 6, 0xFFFF, sum = 0
7818 12:26:54.249447 7, 0xFFFF, sum = 0
7819 12:26:54.249927 8, 0xFFFF, sum = 0
7820 12:26:54.252511 9, 0xFFFF, sum = 0
7821 12:26:54.252964 10, 0xFFFF, sum = 0
7822 12:26:54.256240 11, 0xFFFF, sum = 0
7823 12:26:54.256765 12, 0xFFFF, sum = 0
7824 12:26:54.259348 13, 0xFFFF, sum = 0
7825 12:26:54.259854 14, 0x0, sum = 1
7826 12:26:54.262396 15, 0x0, sum = 2
7827 12:26:54.262822 16, 0x0, sum = 3
7828 12:26:54.265575 17, 0x0, sum = 4
7829 12:26:54.265998 best_step = 15
7830 12:26:54.266331
7831 12:26:54.266641 ==
7832 12:26:54.269200 Dram Type= 6, Freq= 0, CH_0, rank 0
7833 12:26:54.276105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7834 12:26:54.276633 ==
7835 12:26:54.277010 RX Vref Scan: 1
7836 12:26:54.277396
7837 12:26:54.279317 Set Vref Range= 24 -> 127
7838 12:26:54.279780
7839 12:26:54.282519 RX Vref 24 -> 127, step: 1
7840 12:26:54.283069
7841 12:26:54.286105 RX Delay 11 -> 252, step: 4
7842 12:26:54.286612
7843 12:26:54.288697 Set Vref, RX VrefLevel [Byte0]: 24
7844 12:26:54.291974 [Byte1]: 24
7845 12:26:54.292458
7846 12:26:54.295552 Set Vref, RX VrefLevel [Byte0]: 25
7847 12:26:54.298686 [Byte1]: 25
7848 12:26:54.299188
7849 12:26:54.302333 Set Vref, RX VrefLevel [Byte0]: 26
7850 12:26:54.305163 [Byte1]: 26
7851 12:26:54.308831
7852 12:26:54.309300 Set Vref, RX VrefLevel [Byte0]: 27
7853 12:26:54.311725 [Byte1]: 27
7854 12:26:54.315947
7855 12:26:54.316417 Set Vref, RX VrefLevel [Byte0]: 28
7856 12:26:54.319683 [Byte1]: 28
7857 12:26:54.323451
7858 12:26:54.327250 Set Vref, RX VrefLevel [Byte0]: 29
7859 12:26:54.327812 [Byte1]: 29
7860 12:26:54.331468
7861 12:26:54.331932 Set Vref, RX VrefLevel [Byte0]: 30
7862 12:26:54.334640 [Byte1]: 30
7863 12:26:54.339011
7864 12:26:54.339479 Set Vref, RX VrefLevel [Byte0]: 31
7865 12:26:54.342588 [Byte1]: 31
7866 12:26:54.346318
7867 12:26:54.346783 Set Vref, RX VrefLevel [Byte0]: 32
7868 12:26:54.350154 [Byte1]: 32
7869 12:26:54.354522
7870 12:26:54.355016 Set Vref, RX VrefLevel [Byte0]: 33
7871 12:26:54.357621 [Byte1]: 33
7872 12:26:54.361940
7873 12:26:54.362410 Set Vref, RX VrefLevel [Byte0]: 34
7874 12:26:54.365147 [Byte1]: 34
7875 12:26:54.369535
7876 12:26:54.370007 Set Vref, RX VrefLevel [Byte0]: 35
7877 12:26:54.372503 [Byte1]: 35
7878 12:26:54.377431
7879 12:26:54.377973 Set Vref, RX VrefLevel [Byte0]: 36
7880 12:26:54.380569 [Byte1]: 36
7881 12:26:54.384798
7882 12:26:54.385270 Set Vref, RX VrefLevel [Byte0]: 37
7883 12:26:54.388012 [Byte1]: 37
7884 12:26:54.392965
7885 12:26:54.393609 Set Vref, RX VrefLevel [Byte0]: 38
7886 12:26:54.395777 [Byte1]: 38
7887 12:26:54.400029
7888 12:26:54.400518 Set Vref, RX VrefLevel [Byte0]: 39
7889 12:26:54.403003 [Byte1]: 39
7890 12:26:54.407688
7891 12:26:54.408161 Set Vref, RX VrefLevel [Byte0]: 40
7892 12:26:54.410603 [Byte1]: 40
7893 12:26:54.414998
7894 12:26:54.415469 Set Vref, RX VrefLevel [Byte0]: 41
7895 12:26:54.418558 [Byte1]: 41
7896 12:26:54.422859
7897 12:26:54.425753 Set Vref, RX VrefLevel [Byte0]: 42
7898 12:26:54.428927 [Byte1]: 42
7899 12:26:54.429571
7900 12:26:54.432609 Set Vref, RX VrefLevel [Byte0]: 43
7901 12:26:54.435784 [Byte1]: 43
7902 12:26:54.436467
7903 12:26:54.438970 Set Vref, RX VrefLevel [Byte0]: 44
7904 12:26:54.442052 [Byte1]: 44
7905 12:26:54.446106
7906 12:26:54.446681 Set Vref, RX VrefLevel [Byte0]: 45
7907 12:26:54.448774 [Byte1]: 45
7908 12:26:54.453140
7909 12:26:54.453613 Set Vref, RX VrefLevel [Byte0]: 46
7910 12:26:54.459855 [Byte1]: 46
7911 12:26:54.460478
7912 12:26:54.463101 Set Vref, RX VrefLevel [Byte0]: 47
7913 12:26:54.466041 [Byte1]: 47
7914 12:26:54.466599
7915 12:26:54.469240 Set Vref, RX VrefLevel [Byte0]: 48
7916 12:26:54.473162 [Byte1]: 48
7917 12:26:54.476314
7918 12:26:54.476733 Set Vref, RX VrefLevel [Byte0]: 49
7919 12:26:54.479328 [Byte1]: 49
7920 12:26:54.484000
7921 12:26:54.484525 Set Vref, RX VrefLevel [Byte0]: 50
7922 12:26:54.486898 [Byte1]: 50
7923 12:26:54.491237
7924 12:26:54.491657 Set Vref, RX VrefLevel [Byte0]: 51
7925 12:26:54.495135 [Byte1]: 51
7926 12:26:54.498568
7927 12:26:54.499084 Set Vref, RX VrefLevel [Byte0]: 52
7928 12:26:54.502036 [Byte1]: 52
7929 12:26:54.506299
7930 12:26:54.506961 Set Vref, RX VrefLevel [Byte0]: 53
7931 12:26:54.509970 [Byte1]: 53
7932 12:26:54.514274
7933 12:26:54.514826 Set Vref, RX VrefLevel [Byte0]: 54
7934 12:26:54.517123 [Byte1]: 54
7935 12:26:54.521941
7936 12:26:54.522403 Set Vref, RX VrefLevel [Byte0]: 55
7937 12:26:54.524951 [Byte1]: 55
7938 12:26:54.529242
7939 12:26:54.529707 Set Vref, RX VrefLevel [Byte0]: 56
7940 12:26:54.532585 [Byte1]: 56
7941 12:26:54.536976
7942 12:26:54.537529 Set Vref, RX VrefLevel [Byte0]: 57
7943 12:26:54.540221 [Byte1]: 57
7944 12:26:54.544823
7945 12:26:54.545405 Set Vref, RX VrefLevel [Byte0]: 58
7946 12:26:54.547670 [Byte1]: 58
7947 12:26:54.552012
7948 12:26:54.552478 Set Vref, RX VrefLevel [Byte0]: 59
7949 12:26:54.558799 [Byte1]: 59
7950 12:26:54.559320
7951 12:26:54.561768 Set Vref, RX VrefLevel [Byte0]: 60
7952 12:26:54.565560 [Byte1]: 60
7953 12:26:54.566031
7954 12:26:54.568698 Set Vref, RX VrefLevel [Byte0]: 61
7955 12:26:54.571889 [Byte1]: 61
7956 12:26:54.572355
7957 12:26:54.574956 Set Vref, RX VrefLevel [Byte0]: 62
7958 12:26:54.578190 [Byte1]: 62
7959 12:26:54.582498
7960 12:26:54.583067 Set Vref, RX VrefLevel [Byte0]: 63
7961 12:26:54.586204 [Byte1]: 63
7962 12:26:54.590199
7963 12:26:54.590680 Set Vref, RX VrefLevel [Byte0]: 64
7964 12:26:54.593337 [Byte1]: 64
7965 12:26:54.597607
7966 12:26:54.598169 Set Vref, RX VrefLevel [Byte0]: 65
7967 12:26:54.601144 [Byte1]: 65
7968 12:26:54.605436
7969 12:26:54.605902 Set Vref, RX VrefLevel [Byte0]: 66
7970 12:26:54.608514 [Byte1]: 66
7971 12:26:54.613045
7972 12:26:54.613622 Set Vref, RX VrefLevel [Byte0]: 67
7973 12:26:54.616459 [Byte1]: 67
7974 12:26:54.620643
7975 12:26:54.621112 Set Vref, RX VrefLevel [Byte0]: 68
7976 12:26:54.623703 [Byte1]: 68
7977 12:26:54.628386
7978 12:26:54.628969 Set Vref, RX VrefLevel [Byte0]: 69
7979 12:26:54.631172 [Byte1]: 69
7980 12:26:54.635534
7981 12:26:54.636200 Set Vref, RX VrefLevel [Byte0]: 70
7982 12:26:54.639140 [Byte1]: 70
7983 12:26:54.643614
7984 12:26:54.644085 Set Vref, RX VrefLevel [Byte0]: 71
7985 12:26:54.646712 [Byte1]: 71
7986 12:26:54.651153
7987 12:26:54.651638 Set Vref, RX VrefLevel [Byte0]: 72
7988 12:26:54.657207 [Byte1]: 72
7989 12:26:54.657681
7990 12:26:54.660797 Set Vref, RX VrefLevel [Byte0]: 73
7991 12:26:54.663785 [Byte1]: 73
7992 12:26:54.664259
7993 12:26:54.667532 Set Vref, RX VrefLevel [Byte0]: 74
7994 12:26:54.670672 [Byte1]: 74
7995 12:26:54.673787
7996 12:26:54.674213 Set Vref, RX VrefLevel [Byte0]: 75
7997 12:26:54.676884 [Byte1]: 75
7998 12:26:54.681235
7999 12:26:54.681664 Set Vref, RX VrefLevel [Byte0]: 76
8000 12:26:54.684997 [Byte1]: 76
8001 12:26:54.689275
8002 12:26:54.689728 Set Vref, RX VrefLevel [Byte0]: 77
8003 12:26:54.692429 [Byte1]: 77
8004 12:26:54.697023
8005 12:26:54.697479 Final RX Vref Byte 0 = 64 to rank0
8006 12:26:54.700129 Final RX Vref Byte 1 = 59 to rank0
8007 12:26:54.703132 Final RX Vref Byte 0 = 64 to rank1
8008 12:26:54.706820 Final RX Vref Byte 1 = 59 to rank1==
8009 12:26:54.709875 Dram Type= 6, Freq= 0, CH_0, rank 0
8010 12:26:54.716193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 12:26:54.716764 ==
8012 12:26:54.717153 DQS Delay:
8013 12:26:54.719645 DQS0 = 0, DQS1 = 0
8014 12:26:54.720163 DQM Delay:
8015 12:26:54.720531 DQM0 = 126, DQM1 = 119
8016 12:26:54.722779 DQ Delay:
8017 12:26:54.725845 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8018 12:26:54.729467 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8019 12:26:54.732937 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8020 12:26:54.735956 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8021 12:26:54.736593
8022 12:26:54.737141
8023 12:26:54.737611
8024 12:26:54.739580 [DramC_TX_OE_Calibration] TA2
8025 12:26:54.742585 Original DQ_B0 (3 6) =30, OEN = 27
8026 12:26:54.745648 Original DQ_B1 (3 6) =30, OEN = 27
8027 12:26:54.749243 24, 0x0, End_B0=24 End_B1=24
8028 12:26:54.752496 25, 0x0, End_B0=25 End_B1=25
8029 12:26:54.753048 26, 0x0, End_B0=26 End_B1=26
8030 12:26:54.755637 27, 0x0, End_B0=27 End_B1=27
8031 12:26:54.759390 28, 0x0, End_B0=28 End_B1=28
8032 12:26:54.762433 29, 0x0, End_B0=29 End_B1=29
8033 12:26:54.763156 30, 0x0, End_B0=30 End_B1=30
8034 12:26:54.765861 31, 0x4545, End_B0=30 End_B1=30
8035 12:26:54.769037 Byte0 end_step=30 best_step=27
8036 12:26:54.772199 Byte1 end_step=30 best_step=27
8037 12:26:54.775374 Byte0 TX OE(2T, 0.5T) = (3, 3)
8038 12:26:54.779069 Byte1 TX OE(2T, 0.5T) = (3, 3)
8039 12:26:54.779699
8040 12:26:54.780307
8041 12:26:54.785477 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8042 12:26:54.788411 CH0 RK0: MR19=303, MR18=1212
8043 12:26:54.794986 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
8044 12:26:54.795392
8045 12:26:54.798722 ----->DramcWriteLeveling(PI) begin...
8046 12:26:54.799178 ==
8047 12:26:54.801945 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 12:26:54.805006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 12:26:54.805413 ==
8050 12:26:54.808752 Write leveling (Byte 0): 33 => 33
8051 12:26:54.811880 Write leveling (Byte 1): 28 => 28
8052 12:26:54.814907 DramcWriteLeveling(PI) end<-----
8053 12:26:54.815295
8054 12:26:54.815567 ==
8055 12:26:54.818100 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 12:26:54.825076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 12:26:54.825507 ==
8058 12:26:54.825890 [Gating] SW mode calibration
8059 12:26:54.834765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 12:26:54.838374 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8061 12:26:54.841264 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 12:26:54.848453 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 12:26:54.851541 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 12:26:54.854554 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8065 12:26:54.861365 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8066 12:26:54.864499 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 12:26:54.868164 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 12:26:54.874767 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 12:26:54.877785 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 12:26:54.880957 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 12:26:54.887642 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8072 12:26:54.890787 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
8073 12:26:54.894434 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8074 12:26:54.900654 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8075 12:26:54.904346 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 12:26:54.907519 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 12:26:54.913770 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 12:26:54.917633 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 12:26:54.920832 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8080 12:26:54.927024 1 6 12 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
8081 12:26:54.930188 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8082 12:26:54.934028 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 12:26:54.940521 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 12:26:54.943305 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 12:26:54.946870 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 12:26:54.953527 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 12:26:54.956558 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 12:26:54.959774 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 12:26:54.966375 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 12:26:54.970034 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 12:26:54.973053 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 12:26:54.979804 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:26:54.983001 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:26:54.986819 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:26:54.993213 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:26:54.996335 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:26:55.000130 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:26:55.006284 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:26:55.009834 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:26:55.013002 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:26:55.019358 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:26:55.023031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:26:55.029231 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 12:26:55.032994 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 12:26:55.036127 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8106 12:26:55.039325 Total UI for P1: 0, mck2ui 16
8107 12:26:55.042317 best dqsien dly found for B0: ( 1, 9, 10)
8108 12:26:55.046046 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 12:26:55.052515 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 12:26:55.055324 Total UI for P1: 0, mck2ui 16
8111 12:26:55.058881 best dqsien dly found for B1: ( 1, 9, 20)
8112 12:26:55.062466 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8113 12:26:55.065350 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8114 12:26:55.065949
8115 12:26:55.068759 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8116 12:26:55.072129 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8117 12:26:55.075769 [Gating] SW calibration Done
8118 12:26:55.076202 ==
8119 12:26:55.078692 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 12:26:55.082337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 12:26:55.085252 ==
8122 12:26:55.085845 RX Vref Scan: 0
8123 12:26:55.086200
8124 12:26:55.088919 RX Vref 0 -> 0, step: 1
8125 12:26:55.089346
8126 12:26:55.089682 RX Delay 0 -> 252, step: 8
8127 12:26:55.095398 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8128 12:26:55.098674 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8129 12:26:55.101976 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8130 12:26:55.104954 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8131 12:26:55.108508 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8132 12:26:55.115427 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8133 12:26:55.118621 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8134 12:26:55.121593 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8135 12:26:55.124842 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8136 12:26:55.128688 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8137 12:26:55.134802 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8138 12:26:55.138117 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8139 12:26:55.141800 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8140 12:26:55.144904 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8141 12:26:55.151173 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8142 12:26:55.154908 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8143 12:26:55.155336 ==
8144 12:26:55.157688 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 12:26:55.161411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 12:26:55.162069 ==
8147 12:26:55.164539 DQS Delay:
8148 12:26:55.164967 DQS0 = 0, DQS1 = 0
8149 12:26:55.165305 DQM Delay:
8150 12:26:55.167544 DQM0 = 128, DQM1 = 122
8151 12:26:55.168041 DQ Delay:
8152 12:26:55.171059 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8153 12:26:55.177648 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8154 12:26:55.181410 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8155 12:26:55.184202 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8156 12:26:55.184683
8157 12:26:55.185107
8158 12:26:55.185437 ==
8159 12:26:55.187579 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 12:26:55.190944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 12:26:55.191369 ==
8162 12:26:55.191707
8163 12:26:55.192023
8164 12:26:55.193819 TX Vref Scan disable
8165 12:26:55.197548 == TX Byte 0 ==
8166 12:26:55.200681 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8167 12:26:55.203663 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8168 12:26:55.206702 == TX Byte 1 ==
8169 12:26:55.210588 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8170 12:26:55.213653 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8171 12:26:55.214228 ==
8172 12:26:55.216722 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 12:26:55.223621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 12:26:55.224064 ==
8175 12:26:55.236807
8176 12:26:55.239975 TX Vref early break, caculate TX vref
8177 12:26:55.243089 TX Vref=16, minBit 0, minWin=22, winSum=364
8178 12:26:55.246186 TX Vref=18, minBit 0, minWin=22, winSum=371
8179 12:26:55.249825 TX Vref=20, minBit 1, minWin=22, winSum=377
8180 12:26:55.253194 TX Vref=22, minBit 9, minWin=23, winSum=390
8181 12:26:55.256388 TX Vref=24, minBit 7, minWin=24, winSum=399
8182 12:26:55.263156 TX Vref=26, minBit 8, minWin=24, winSum=408
8183 12:26:55.266504 TX Vref=28, minBit 8, minWin=24, winSum=405
8184 12:26:55.269409 TX Vref=30, minBit 8, minWin=23, winSum=401
8185 12:26:55.273210 TX Vref=32, minBit 8, minWin=23, winSum=396
8186 12:26:55.276300 TX Vref=34, minBit 8, minWin=22, winSum=388
8187 12:26:55.282816 TX Vref=36, minBit 8, minWin=22, winSum=379
8188 12:26:55.285895 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 26
8189 12:26:55.286318
8190 12:26:55.289382 Final TX Range 0 Vref 26
8191 12:26:55.289805
8192 12:26:55.290142 ==
8193 12:26:55.292429 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 12:26:55.296091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 12:26:55.298957 ==
8196 12:26:55.299379
8197 12:26:55.299711
8198 12:26:55.300020 TX Vref Scan disable
8199 12:26:55.305907 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8200 12:26:55.306490 == TX Byte 0 ==
8201 12:26:55.309817 u2DelayCellOfst[0]=15 cells (4 PI)
8202 12:26:55.312776 u2DelayCellOfst[1]=18 cells (5 PI)
8203 12:26:55.315892 u2DelayCellOfst[2]=7 cells (2 PI)
8204 12:26:55.319334 u2DelayCellOfst[3]=11 cells (3 PI)
8205 12:26:55.322158 u2DelayCellOfst[4]=7 cells (2 PI)
8206 12:26:55.325319 u2DelayCellOfst[5]=0 cells (0 PI)
8207 12:26:55.328482 u2DelayCellOfst[6]=18 cells (5 PI)
8208 12:26:55.332223 u2DelayCellOfst[7]=18 cells (5 PI)
8209 12:26:55.335299 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8210 12:26:55.338486 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8211 12:26:55.341666 == TX Byte 1 ==
8212 12:26:55.344782 u2DelayCellOfst[8]=0 cells (0 PI)
8213 12:26:55.348707 u2DelayCellOfst[9]=0 cells (0 PI)
8214 12:26:55.351749 u2DelayCellOfst[10]=7 cells (2 PI)
8215 12:26:55.354821 u2DelayCellOfst[11]=7 cells (2 PI)
8216 12:26:55.357996 u2DelayCellOfst[12]=15 cells (4 PI)
8217 12:26:55.361231 u2DelayCellOfst[13]=15 cells (4 PI)
8218 12:26:55.365028 u2DelayCellOfst[14]=18 cells (5 PI)
8219 12:26:55.368194 u2DelayCellOfst[15]=11 cells (3 PI)
8220 12:26:55.371481 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8221 12:26:55.374813 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8222 12:26:55.377674 DramC Write-DBI on
8223 12:26:55.377934 ==
8224 12:26:55.380887 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 12:26:55.384579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 12:26:55.384919 ==
8227 12:26:55.385200
8228 12:26:55.385463
8229 12:26:55.387753 TX Vref Scan disable
8230 12:26:55.391353 == TX Byte 0 ==
8231 12:26:55.394206 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8232 12:26:55.394693 == TX Byte 1 ==
8233 12:26:55.401343 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8234 12:26:55.401776 DramC Write-DBI off
8235 12:26:55.402117
8236 12:26:55.402592 [DATLAT]
8237 12:26:55.404327 Freq=1600, CH0 RK1
8238 12:26:55.404898
8239 12:26:55.407917 DATLAT Default: 0xf
8240 12:26:55.408538 0, 0xFFFF, sum = 0
8241 12:26:55.410961 1, 0xFFFF, sum = 0
8242 12:26:55.411507 2, 0xFFFF, sum = 0
8243 12:26:55.414124 3, 0xFFFF, sum = 0
8244 12:26:55.414799 4, 0xFFFF, sum = 0
8245 12:26:55.417319 5, 0xFFFF, sum = 0
8246 12:26:55.418023 6, 0xFFFF, sum = 0
8247 12:26:55.420980 7, 0xFFFF, sum = 0
8248 12:26:55.421636 8, 0xFFFF, sum = 0
8249 12:26:55.424205 9, 0xFFFF, sum = 0
8250 12:26:55.424742 10, 0xFFFF, sum = 0
8251 12:26:55.427549 11, 0xFFFF, sum = 0
8252 12:26:55.430587 12, 0xFFFF, sum = 0
8253 12:26:55.431053 13, 0xCFFF, sum = 0
8254 12:26:55.434061 14, 0x0, sum = 1
8255 12:26:55.434567 15, 0x0, sum = 2
8256 12:26:55.435124 16, 0x0, sum = 3
8257 12:26:55.437295 17, 0x0, sum = 4
8258 12:26:55.437721 best_step = 15
8259 12:26:55.438057
8260 12:26:55.440292 ==
8261 12:26:55.440712 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 12:26:55.447386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 12:26:55.447828 ==
8264 12:26:55.448206 RX Vref Scan: 0
8265 12:26:55.448594
8266 12:26:55.450504 RX Vref 0 -> 0, step: 1
8267 12:26:55.450984
8268 12:26:55.453735 RX Delay 3 -> 252, step: 4
8269 12:26:55.456758 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8270 12:26:55.460559 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8271 12:26:55.466667 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8272 12:26:55.469958 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8273 12:26:55.473646 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8274 12:26:55.476446 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8275 12:26:55.483449 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8276 12:26:55.486501 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8277 12:26:55.489520 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8278 12:26:55.493221 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8279 12:26:55.496313 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8280 12:26:55.502786 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8281 12:26:55.506437 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8282 12:26:55.509553 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8283 12:26:55.512992 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8284 12:26:55.516560 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8285 12:26:55.519301 ==
8286 12:26:55.522918 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 12:26:55.525782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 12:26:55.526212 ==
8289 12:26:55.526615 DQS Delay:
8290 12:26:55.529645 DQS0 = 0, DQS1 = 0
8291 12:26:55.530060 DQM Delay:
8292 12:26:55.532702 DQM0 = 124, DQM1 = 118
8293 12:26:55.533182 DQ Delay:
8294 12:26:55.535901 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8295 12:26:55.539424 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =134
8296 12:26:55.542656 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8297 12:26:55.545821 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8298 12:26:55.546536
8299 12:26:55.547115
8300 12:26:55.547591
8301 12:26:55.548898 [DramC_TX_OE_Calibration] TA2
8302 12:26:55.552840 Original DQ_B0 (3 6) =30, OEN = 27
8303 12:26:55.556105 Original DQ_B1 (3 6) =30, OEN = 27
8304 12:26:55.559157 24, 0x0, End_B0=24 End_B1=24
8305 12:26:55.562164 25, 0x0, End_B0=25 End_B1=25
8306 12:26:55.565360 26, 0x0, End_B0=26 End_B1=26
8307 12:26:55.565973 27, 0x0, End_B0=27 End_B1=27
8308 12:26:55.569022 28, 0x0, End_B0=28 End_B1=28
8309 12:26:55.572384 29, 0x0, End_B0=29 End_B1=29
8310 12:26:55.575615 30, 0x0, End_B0=30 End_B1=30
8311 12:26:55.578663 31, 0x4141, End_B0=30 End_B1=30
8312 12:26:55.579202 Byte0 end_step=30 best_step=27
8313 12:26:55.581901 Byte1 end_step=30 best_step=27
8314 12:26:55.585481 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 12:26:55.588639 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 12:26:55.589063
8317 12:26:55.589397
8318 12:26:55.595172 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8319 12:26:55.598289 CH0 RK1: MR19=303, MR18=210F
8320 12:26:55.605474 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8321 12:26:55.608512 [RxdqsGatingPostProcess] freq 1600
8322 12:26:55.615075 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 12:26:55.618761 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 12:26:55.619295 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 12:26:55.621713 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 12:26:55.624850 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 12:26:55.628215 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 12:26:55.631922 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 12:26:55.634920 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 12:26:55.637989 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 12:26:55.641252 Pre-setting of DQS Precalculation
8332 12:26:55.648107 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 12:26:55.648545 ==
8334 12:26:55.651236 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 12:26:55.654387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 12:26:55.654822 ==
8337 12:26:55.661346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 12:26:55.664498 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 12:26:55.667606 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 12:26:55.674581 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 12:26:55.682748 [CA 0] Center 42 (13~71) winsize 59
8342 12:26:55.685861 [CA 1] Center 42 (13~72) winsize 60
8343 12:26:55.689488 [CA 2] Center 38 (9~67) winsize 59
8344 12:26:55.692623 [CA 3] Center 37 (8~67) winsize 60
8345 12:26:55.695870 [CA 4] Center 38 (9~67) winsize 59
8346 12:26:55.699302 [CA 5] Center 37 (8~66) winsize 59
8347 12:26:55.699438
8348 12:26:55.702217 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 12:26:55.702299
8350 12:26:55.708924 [CATrainingPosCal] consider 1 rank data
8351 12:26:55.709064 u2DelayCellTimex100 = 258/100 ps
8352 12:26:55.715679 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8353 12:26:55.718704 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8354 12:26:55.722336 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8355 12:26:55.725370 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8356 12:26:55.728988 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8357 12:26:55.732202 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8358 12:26:55.732284
8359 12:26:55.735097 CA PerBit enable=1, Macro0, CA PI delay=37
8360 12:26:55.735204
8361 12:26:55.738680 [CBTSetCACLKResult] CA Dly = 37
8362 12:26:55.741759 CS Dly: 9 (0~40)
8363 12:26:55.744995 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 12:26:55.748593 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 12:26:55.748703 ==
8366 12:26:55.751828 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 12:26:55.758771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 12:26:55.758894 ==
8369 12:26:55.761785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 12:26:55.769116 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 12:26:55.771796 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 12:26:55.778052 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 12:26:55.785487 [CA 0] Center 42 (13~71) winsize 59
8374 12:26:55.789299 [CA 1] Center 42 (12~72) winsize 61
8375 12:26:55.792411 [CA 2] Center 37 (8~67) winsize 60
8376 12:26:55.795533 [CA 3] Center 36 (7~66) winsize 60
8377 12:26:55.798644 [CA 4] Center 38 (9~68) winsize 60
8378 12:26:55.802426 [CA 5] Center 37 (7~67) winsize 61
8379 12:26:55.802551
8380 12:26:55.805432 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 12:26:55.805513
8382 12:26:55.811970 [CATrainingPosCal] consider 2 rank data
8383 12:26:55.812052 u2DelayCellTimex100 = 258/100 ps
8384 12:26:55.818693 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8385 12:26:55.821838 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8386 12:26:55.825815 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8387 12:26:55.828717 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8388 12:26:55.831646 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8389 12:26:55.835165 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8390 12:26:55.835247
8391 12:26:55.838342 CA PerBit enable=1, Macro0, CA PI delay=37
8392 12:26:55.838430
8393 12:26:55.841952 [CBTSetCACLKResult] CA Dly = 37
8394 12:26:55.844875 CS Dly: 10 (0~43)
8395 12:26:55.848363 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 12:26:55.851375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 12:26:55.851477
8398 12:26:55.855230 ----->DramcWriteLeveling(PI) begin...
8399 12:26:55.855698 ==
8400 12:26:55.858468 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 12:26:55.865246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 12:26:55.865725 ==
8403 12:26:55.868487 Write leveling (Byte 0): 23 => 23
8404 12:26:55.871650 Write leveling (Byte 1): 29 => 29
8405 12:26:55.874815 DramcWriteLeveling(PI) end<-----
8406 12:26:55.875270
8407 12:26:55.875596 ==
8408 12:26:55.878588 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 12:26:55.881653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 12:26:55.882170 ==
8411 12:26:55.884724 [Gating] SW mode calibration
8412 12:26:55.891037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 12:26:55.897775 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 12:26:55.901573 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 12:26:55.904757 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 12:26:55.911365 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 12:26:55.914566 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 12:26:55.918131 1 4 16 | B1->B0 | 3333 3232 | 0 1 | (0 0) (0 0)
8419 12:26:55.924571 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 12:26:55.927738 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 12:26:55.930999 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 12:26:55.937508 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 12:26:55.941078 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 12:26:55.944103 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 12:26:55.950994 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
8426 12:26:55.954150 1 5 16 | B1->B0 | 2727 2626 | 0 1 | (1 0) (1 0)
8427 12:26:55.957118 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 12:26:55.963962 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 12:26:55.967224 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 12:26:55.970817 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 12:26:55.977309 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 12:26:55.980374 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 12:26:55.983473 1 6 12 | B1->B0 | 2727 2424 | 1 0 | (0 0) (0 0)
8434 12:26:55.990293 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 12:26:55.993394 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 12:26:55.997397 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 12:26:56.004025 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 12:26:56.006886 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 12:26:56.010305 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 12:26:56.013968 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 12:26:56.020635 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 12:26:56.023446 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8443 12:26:56.026483 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:26:56.033135 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:26:56.037164 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:26:56.039954 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:26:56.046373 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:26:56.049653 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:26:56.053315 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:26:56.060030 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 12:26:56.063172 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:26:56.066281 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:26:56.072976 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:26:56.076082 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:26:56.079279 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 12:26:56.085848 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 12:26:56.089099 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 12:26:56.092307 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 12:26:56.099270 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8460 12:26:56.102294 Total UI for P1: 0, mck2ui 16
8461 12:26:56.106119 best dqsien dly found for B0: ( 1, 9, 14)
8462 12:26:56.109204 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 12:26:56.112271 Total UI for P1: 0, mck2ui 16
8464 12:26:56.115956 best dqsien dly found for B1: ( 1, 9, 16)
8465 12:26:56.119160 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8466 12:26:56.122317 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8467 12:26:56.122772
8468 12:26:56.125599 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8469 12:26:56.132101 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8470 12:26:56.132567 [Gating] SW calibration Done
8471 12:26:56.135667 ==
8472 12:26:56.138623 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 12:26:56.142288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 12:26:56.142705 ==
8475 12:26:56.143129 RX Vref Scan: 0
8476 12:26:56.143448
8477 12:26:56.145274 RX Vref 0 -> 0, step: 1
8478 12:26:56.145914
8479 12:26:56.149028 RX Delay 0 -> 252, step: 8
8480 12:26:56.151660 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8481 12:26:56.155428 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8482 12:26:56.158688 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8483 12:26:56.165335 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8484 12:26:56.168511 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8485 12:26:56.171690 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8486 12:26:56.175407 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8487 12:26:56.178242 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8488 12:26:56.185360 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8489 12:26:56.188376 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8490 12:26:56.191455 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8491 12:26:56.195325 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8492 12:26:56.201739 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8493 12:26:56.205010 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8494 12:26:56.208145 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8495 12:26:56.211191 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8496 12:26:56.211614 ==
8497 12:26:56.214334 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 12:26:56.221199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 12:26:56.221708 ==
8500 12:26:56.222049 DQS Delay:
8501 12:26:56.222362 DQS0 = 0, DQS1 = 0
8502 12:26:56.224392 DQM Delay:
8503 12:26:56.224814 DQM0 = 131, DQM1 = 126
8504 12:26:56.228261 DQ Delay:
8505 12:26:56.231306 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8506 12:26:56.234442 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8507 12:26:56.237900 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8508 12:26:56.240992 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8509 12:26:56.241417
8510 12:26:56.241747
8511 12:26:56.242054 ==
8512 12:26:56.244007 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 12:26:56.247664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 12:26:56.250663 ==
8515 12:26:56.251167
8516 12:26:56.251676
8517 12:26:56.252013 TX Vref Scan disable
8518 12:26:56.254265 == TX Byte 0 ==
8519 12:26:56.257337 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8520 12:26:56.260963 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8521 12:26:56.263926 == TX Byte 1 ==
8522 12:26:56.267470 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8523 12:26:56.273804 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8524 12:26:56.274373 ==
8525 12:26:56.277424 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 12:26:56.280353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 12:26:56.280871 ==
8528 12:26:56.293584
8529 12:26:56.296420 TX Vref early break, caculate TX vref
8530 12:26:56.299569 TX Vref=16, minBit 8, minWin=20, winSum=353
8531 12:26:56.302686 TX Vref=18, minBit 9, minWin=21, winSum=365
8532 12:26:56.306610 TX Vref=20, minBit 9, minWin=22, winSum=374
8533 12:26:56.309570 TX Vref=22, minBit 1, minWin=23, winSum=384
8534 12:26:56.312767 TX Vref=24, minBit 0, minWin=24, winSum=395
8535 12:26:56.319293 TX Vref=26, minBit 0, minWin=24, winSum=403
8536 12:26:56.322921 TX Vref=28, minBit 6, minWin=24, winSum=409
8537 12:26:56.326178 TX Vref=30, minBit 0, minWin=23, winSum=405
8538 12:26:56.329361 TX Vref=32, minBit 6, minWin=23, winSum=395
8539 12:26:56.332710 TX Vref=34, minBit 0, minWin=22, winSum=384
8540 12:26:56.339467 [TxChooseVref] Worse bit 6, Min win 24, Win sum 409, Final Vref 28
8541 12:26:56.340043
8542 12:26:56.342524 Final TX Range 0 Vref 28
8543 12:26:56.343049
8544 12:26:56.343432 ==
8545 12:26:56.345513 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 12:26:56.349433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 12:26:56.349949 ==
8548 12:26:56.350340
8549 12:26:56.352149
8550 12:26:56.352619 TX Vref Scan disable
8551 12:26:56.358306 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8552 12:26:56.358989 == TX Byte 0 ==
8553 12:26:56.362217 u2DelayCellOfst[0]=18 cells (5 PI)
8554 12:26:56.365273 u2DelayCellOfst[1]=15 cells (4 PI)
8555 12:26:56.368635 u2DelayCellOfst[2]=0 cells (0 PI)
8556 12:26:56.371688 u2DelayCellOfst[3]=3 cells (1 PI)
8557 12:26:56.375218 u2DelayCellOfst[4]=7 cells (2 PI)
8558 12:26:56.378487 u2DelayCellOfst[5]=26 cells (7 PI)
8559 12:26:56.381733 u2DelayCellOfst[6]=22 cells (6 PI)
8560 12:26:56.385436 u2DelayCellOfst[7]=3 cells (1 PI)
8561 12:26:56.388640 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8562 12:26:56.391690 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8563 12:26:56.394730 == TX Byte 1 ==
8564 12:26:56.398331 u2DelayCellOfst[8]=0 cells (0 PI)
8565 12:26:56.401386 u2DelayCellOfst[9]=11 cells (3 PI)
8566 12:26:56.404691 u2DelayCellOfst[10]=18 cells (5 PI)
8567 12:26:56.407876 u2DelayCellOfst[11]=11 cells (3 PI)
8568 12:26:56.410951 u2DelayCellOfst[12]=18 cells (5 PI)
8569 12:26:56.414765 u2DelayCellOfst[13]=22 cells (6 PI)
8570 12:26:56.418007 u2DelayCellOfst[14]=22 cells (6 PI)
8571 12:26:56.418430 u2DelayCellOfst[15]=22 cells (6 PI)
8572 12:26:56.424251 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8573 12:26:56.427771 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8574 12:26:56.431068 DramC Write-DBI on
8575 12:26:56.431606 ==
8576 12:26:56.434083 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 12:26:56.437863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 12:26:56.438404 ==
8579 12:26:56.438782
8580 12:26:56.439191
8581 12:26:56.440967 TX Vref Scan disable
8582 12:26:56.441703 == TX Byte 0 ==
8583 12:26:56.447339 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8584 12:26:56.447814 == TX Byte 1 ==
8585 12:26:56.454293 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8586 12:26:56.454785 DramC Write-DBI off
8587 12:26:56.455203
8588 12:26:56.455555 [DATLAT]
8589 12:26:56.457241 Freq=1600, CH1 RK0
8590 12:26:56.457857
8591 12:26:56.460616 DATLAT Default: 0xf
8592 12:26:56.461108 0, 0xFFFF, sum = 0
8593 12:26:56.463596 1, 0xFFFF, sum = 0
8594 12:26:56.464071 2, 0xFFFF, sum = 0
8595 12:26:56.467134 3, 0xFFFF, sum = 0
8596 12:26:56.467604 4, 0xFFFF, sum = 0
8597 12:26:56.470218 5, 0xFFFF, sum = 0
8598 12:26:56.470888 6, 0xFFFF, sum = 0
8599 12:26:56.473851 7, 0xFFFF, sum = 0
8600 12:26:56.474324 8, 0xFFFF, sum = 0
8601 12:26:56.477228 9, 0xFFFF, sum = 0
8602 12:26:56.477752 10, 0xFFFF, sum = 0
8603 12:26:56.480298 11, 0xFFFF, sum = 0
8604 12:26:56.480949 12, 0xFFFF, sum = 0
8605 12:26:56.483350 13, 0x8FFF, sum = 0
8606 12:26:56.483803 14, 0x0, sum = 1
8607 12:26:56.486642 15, 0x0, sum = 2
8608 12:26:56.487136 16, 0x0, sum = 3
8609 12:26:56.490461 17, 0x0, sum = 4
8610 12:26:56.490982 best_step = 15
8611 12:26:56.491378
8612 12:26:56.491732 ==
8613 12:26:56.493482 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 12:26:56.499654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 12:26:56.500084 ==
8616 12:26:56.500422 RX Vref Scan: 1
8617 12:26:56.500735
8618 12:26:56.503471 Set Vref Range= 24 -> 127
8619 12:26:56.503891
8620 12:26:56.506446 RX Vref 24 -> 127, step: 1
8621 12:26:56.506886
8622 12:26:56.509730 RX Delay 11 -> 252, step: 4
8623 12:26:56.510228
8624 12:26:56.512955 Set Vref, RX VrefLevel [Byte0]: 24
8625 12:26:56.516863 [Byte1]: 24
8626 12:26:56.517391
8627 12:26:56.519724 Set Vref, RX VrefLevel [Byte0]: 25
8628 12:26:56.522739 [Byte1]: 25
8629 12:26:56.523222
8630 12:26:56.526568 Set Vref, RX VrefLevel [Byte0]: 26
8631 12:26:56.529414 [Byte1]: 26
8632 12:26:56.533246
8633 12:26:56.533754 Set Vref, RX VrefLevel [Byte0]: 27
8634 12:26:56.536460 [Byte1]: 27
8635 12:26:56.540803
8636 12:26:56.541362 Set Vref, RX VrefLevel [Byte0]: 28
8637 12:26:56.543845 [Byte1]: 28
8638 12:26:56.548118
8639 12:26:56.548581 Set Vref, RX VrefLevel [Byte0]: 29
8640 12:26:56.551387 [Byte1]: 29
8641 12:26:56.555728
8642 12:26:56.556293 Set Vref, RX VrefLevel [Byte0]: 30
8643 12:26:56.559184 [Byte1]: 30
8644 12:26:56.563372
8645 12:26:56.563839 Set Vref, RX VrefLevel [Byte0]: 31
8646 12:26:56.566526 [Byte1]: 31
8647 12:26:56.571310
8648 12:26:56.571785 Set Vref, RX VrefLevel [Byte0]: 32
8649 12:26:56.574263 [Byte1]: 32
8650 12:26:56.578442
8651 12:26:56.578943 Set Vref, RX VrefLevel [Byte0]: 33
8652 12:26:56.582174 [Byte1]: 33
8653 12:26:56.586378
8654 12:26:56.587043 Set Vref, RX VrefLevel [Byte0]: 34
8655 12:26:56.589978 [Byte1]: 34
8656 12:26:56.594252
8657 12:26:56.594823 Set Vref, RX VrefLevel [Byte0]: 35
8658 12:26:56.597424 [Byte1]: 35
8659 12:26:56.601738
8660 12:26:56.602309 Set Vref, RX VrefLevel [Byte0]: 36
8661 12:26:56.604961 [Byte1]: 36
8662 12:26:56.609185
8663 12:26:56.609760 Set Vref, RX VrefLevel [Byte0]: 37
8664 12:26:56.612374 [Byte1]: 37
8665 12:26:56.616953
8666 12:26:56.617522 Set Vref, RX VrefLevel [Byte0]: 38
8667 12:26:56.619877 [Byte1]: 38
8668 12:26:56.624647
8669 12:26:56.625115 Set Vref, RX VrefLevel [Byte0]: 39
8670 12:26:56.627538 [Byte1]: 39
8671 12:26:56.631790
8672 12:26:56.632254 Set Vref, RX VrefLevel [Byte0]: 40
8673 12:26:56.635304 [Byte1]: 40
8674 12:26:56.639750
8675 12:26:56.640216 Set Vref, RX VrefLevel [Byte0]: 41
8676 12:26:56.642799 [Byte1]: 41
8677 12:26:56.647177
8678 12:26:56.647760 Set Vref, RX VrefLevel [Byte0]: 42
8679 12:26:56.650309 [Byte1]: 42
8680 12:26:56.654938
8681 12:26:56.655400 Set Vref, RX VrefLevel [Byte0]: 43
8682 12:26:56.657943 [Byte1]: 43
8683 12:26:56.662672
8684 12:26:56.663181 Set Vref, RX VrefLevel [Byte0]: 44
8685 12:26:56.666177 [Byte1]: 44
8686 12:26:56.669844
8687 12:26:56.670308 Set Vref, RX VrefLevel [Byte0]: 45
8688 12:26:56.673551 [Byte1]: 45
8689 12:26:56.677688
8690 12:26:56.678153 Set Vref, RX VrefLevel [Byte0]: 46
8691 12:26:56.680623 [Byte1]: 46
8692 12:26:56.685132
8693 12:26:56.685214 Set Vref, RX VrefLevel [Byte0]: 47
8694 12:26:56.688111 [Byte1]: 47
8695 12:26:56.692293
8696 12:26:56.692375 Set Vref, RX VrefLevel [Byte0]: 48
8697 12:26:56.696109 [Byte1]: 48
8698 12:26:56.700697
8699 12:26:56.701206 Set Vref, RX VrefLevel [Byte0]: 49
8700 12:26:56.703817 [Byte1]: 49
8701 12:26:56.708376
8702 12:26:56.708949 Set Vref, RX VrefLevel [Byte0]: 50
8703 12:26:56.711295 [Byte1]: 50
8704 12:26:56.715513
8705 12:26:56.715980 Set Vref, RX VrefLevel [Byte0]: 51
8706 12:26:56.719188 [Byte1]: 51
8707 12:26:56.723344
8708 12:26:56.723810 Set Vref, RX VrefLevel [Byte0]: 52
8709 12:26:56.726448 [Byte1]: 52
8710 12:26:56.731079
8711 12:26:56.731761 Set Vref, RX VrefLevel [Byte0]: 53
8712 12:26:56.734206 [Byte1]: 53
8713 12:26:56.739049
8714 12:26:56.739627 Set Vref, RX VrefLevel [Byte0]: 54
8715 12:26:56.742026 [Byte1]: 54
8716 12:26:56.746309
8717 12:26:56.746779 Set Vref, RX VrefLevel [Byte0]: 55
8718 12:26:56.749606 [Byte1]: 55
8719 12:26:56.754090
8720 12:26:56.754554 Set Vref, RX VrefLevel [Byte0]: 56
8721 12:26:56.757144 [Byte1]: 56
8722 12:26:56.761757
8723 12:26:56.762332 Set Vref, RX VrefLevel [Byte0]: 57
8724 12:26:56.764619 [Byte1]: 57
8725 12:26:56.768974
8726 12:26:56.769442 Set Vref, RX VrefLevel [Byte0]: 58
8727 12:26:56.772447 [Byte1]: 58
8728 12:26:56.776662
8729 12:26:56.777255 Set Vref, RX VrefLevel [Byte0]: 59
8730 12:26:56.780150 [Byte1]: 59
8731 12:26:56.784252
8732 12:26:56.784742 Set Vref, RX VrefLevel [Byte0]: 60
8733 12:26:56.787825 [Byte1]: 60
8734 12:26:56.791771
8735 12:26:56.792337 Set Vref, RX VrefLevel [Byte0]: 61
8736 12:26:56.795270 [Byte1]: 61
8737 12:26:56.799238
8738 12:26:56.799705 Set Vref, RX VrefLevel [Byte0]: 62
8739 12:26:56.802583 [Byte1]: 62
8740 12:26:56.806917
8741 12:26:56.807478 Set Vref, RX VrefLevel [Byte0]: 63
8742 12:26:56.810556 [Byte1]: 63
8743 12:26:56.814650
8744 12:26:56.815275 Set Vref, RX VrefLevel [Byte0]: 64
8745 12:26:56.818263 [Byte1]: 64
8746 12:26:56.822147
8747 12:26:56.823007 Set Vref, RX VrefLevel [Byte0]: 65
8748 12:26:56.825634 [Byte1]: 65
8749 12:26:56.829958
8750 12:26:56.830426 Set Vref, RX VrefLevel [Byte0]: 66
8751 12:26:56.833189 [Byte1]: 66
8752 12:26:56.837794
8753 12:26:56.838260 Set Vref, RX VrefLevel [Byte0]: 67
8754 12:26:56.840979 [Byte1]: 67
8755 12:26:56.845141
8756 12:26:56.845607 Set Vref, RX VrefLevel [Byte0]: 68
8757 12:26:56.848262 [Byte1]: 68
8758 12:26:56.852717
8759 12:26:56.853184 Set Vref, RX VrefLevel [Byte0]: 69
8760 12:26:56.855916 [Byte1]: 69
8761 12:26:56.860371
8762 12:26:56.860838 Set Vref, RX VrefLevel [Byte0]: 70
8763 12:26:56.863404 [Byte1]: 70
8764 12:26:56.867807
8765 12:26:56.868280 Set Vref, RX VrefLevel [Byte0]: 71
8766 12:26:56.870781 [Byte1]: 71
8767 12:26:56.875374
8768 12:26:56.876008 Final RX Vref Byte 0 = 59 to rank0
8769 12:26:56.879171 Final RX Vref Byte 1 = 53 to rank0
8770 12:26:56.882033 Final RX Vref Byte 0 = 59 to rank1
8771 12:26:56.885059 Final RX Vref Byte 1 = 53 to rank1==
8772 12:26:56.888721 Dram Type= 6, Freq= 0, CH_1, rank 0
8773 12:26:56.895100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 12:26:56.895685 ==
8775 12:26:56.896193 DQS Delay:
8776 12:26:56.898575 DQS0 = 0, DQS1 = 0
8777 12:26:56.899129 DQM Delay:
8778 12:26:56.899550 DQM0 = 131, DQM1 = 123
8779 12:26:56.901681 DQ Delay:
8780 12:26:56.905128 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8781 12:26:56.908592 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8782 12:26:56.911529 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8783 12:26:56.915090 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8784 12:26:56.915520
8785 12:26:56.915858
8786 12:26:56.916170
8787 12:26:56.918059 [DramC_TX_OE_Calibration] TA2
8788 12:26:56.921870 Original DQ_B0 (3 6) =30, OEN = 27
8789 12:26:56.925040 Original DQ_B1 (3 6) =30, OEN = 27
8790 12:26:56.928084 24, 0x0, End_B0=24 End_B1=24
8791 12:26:56.931249 25, 0x0, End_B0=25 End_B1=25
8792 12:26:56.931803 26, 0x0, End_B0=26 End_B1=26
8793 12:26:56.934785 27, 0x0, End_B0=27 End_B1=27
8794 12:26:56.937957 28, 0x0, End_B0=28 End_B1=28
8795 12:26:56.941392 29, 0x0, End_B0=29 End_B1=29
8796 12:26:56.941829 30, 0x0, End_B0=30 End_B1=30
8797 12:26:56.944419 31, 0x4545, End_B0=30 End_B1=30
8798 12:26:56.948070 Byte0 end_step=30 best_step=27
8799 12:26:56.951108 Byte1 end_step=30 best_step=27
8800 12:26:56.954894 Byte0 TX OE(2T, 0.5T) = (3, 3)
8801 12:26:56.958093 Byte1 TX OE(2T, 0.5T) = (3, 3)
8802 12:26:56.958723
8803 12:26:56.959212
8804 12:26:56.964447 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8805 12:26:56.967405 CH1 RK0: MR19=303, MR18=70C
8806 12:26:56.974429 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8807 12:26:56.975020
8808 12:26:56.977617 ----->DramcWriteLeveling(PI) begin...
8809 12:26:56.978303 ==
8810 12:26:56.980799 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 12:26:56.984448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 12:26:56.985009 ==
8813 12:26:56.987611 Write leveling (Byte 0): 23 => 23
8814 12:26:56.990676 Write leveling (Byte 1): 28 => 28
8815 12:26:56.994165 DramcWriteLeveling(PI) end<-----
8816 12:26:56.994685
8817 12:26:56.995241 ==
8818 12:26:56.997446 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 12:26:57.000538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 12:26:57.003934 ==
8821 12:26:57.004376 [Gating] SW mode calibration
8822 12:26:57.010922 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8823 12:26:57.017381 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8824 12:26:57.020913 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 12:26:57.026934 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 12:26:57.030699 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8827 12:26:57.033626 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8828 12:26:57.040471 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 12:26:57.043573 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 12:26:57.047319 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:26:57.053369 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:26:57.057137 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 12:26:57.060200 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8834 12:26:57.066645 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
8835 12:26:57.070292 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
8836 12:26:57.073378 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 12:26:57.080381 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 12:26:57.083641 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:26:57.086818 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:26:57.093235 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:26:57.096978 1 6 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8842 12:26:57.099883 1 6 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8843 12:26:57.106523 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8844 12:26:57.109478 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 12:26:57.113281 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 12:26:57.119895 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:26:57.122928 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:26:57.126381 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:26:57.133183 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8850 12:26:57.136331 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8851 12:26:57.139525 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 12:26:57.145881 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 12:26:57.149043 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:26:57.152769 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:26:57.159419 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:26:57.162612 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:26:57.165701 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:26:57.172618 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:26:57.175705 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:26:57.178858 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:26:57.185499 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:26:57.188740 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:26:57.192425 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:26:57.198672 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:26:57.202495 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:26:57.205479 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8867 12:26:57.212040 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8868 12:26:57.212524 Total UI for P1: 0, mck2ui 16
8869 12:26:57.218805 best dqsien dly found for B0: ( 1, 9, 8)
8870 12:26:57.222228 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 12:26:57.225264 Total UI for P1: 0, mck2ui 16
8872 12:26:57.228700 best dqsien dly found for B1: ( 1, 9, 10)
8873 12:26:57.231816 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8874 12:26:57.235320 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8875 12:26:57.235798
8876 12:26:57.238357 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8877 12:26:57.242170 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8878 12:26:57.245207 [Gating] SW calibration Done
8879 12:26:57.245749 ==
8880 12:26:57.248321 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 12:26:57.251790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 12:26:57.254976 ==
8883 12:26:57.255456 RX Vref Scan: 0
8884 12:26:57.255833
8885 12:26:57.257991 RX Vref 0 -> 0, step: 1
8886 12:26:57.258512
8887 12:26:57.258960 RX Delay 0 -> 252, step: 8
8888 12:26:57.265047 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8889 12:26:57.267970 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8890 12:26:57.271799 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8891 12:26:57.275060 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8892 12:26:57.281223 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8893 12:26:57.285086 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8894 12:26:57.288303 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8895 12:26:57.291461 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8896 12:26:57.294610 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8897 12:26:57.301097 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8898 12:26:57.304670 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8899 12:26:57.307878 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8900 12:26:57.310897 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8901 12:26:57.314035 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8902 12:26:57.320779 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8903 12:26:57.324215 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8904 12:26:57.324816 ==
8905 12:26:57.327519 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 12:26:57.330693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 12:26:57.331259 ==
8908 12:26:57.334116 DQS Delay:
8909 12:26:57.334577 DQS0 = 0, DQS1 = 0
8910 12:26:57.335043 DQM Delay:
8911 12:26:57.337354 DQM0 = 132, DQM1 = 128
8912 12:26:57.337979 DQ Delay:
8913 12:26:57.340794 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8914 12:26:57.343795 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8915 12:26:57.350505 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8916 12:26:57.353613 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8917 12:26:57.354224
8918 12:26:57.354709
8919 12:26:57.355219 ==
8920 12:26:57.357261 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 12:26:57.360374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 12:26:57.360901 ==
8923 12:26:57.361351
8924 12:26:57.361686
8925 12:26:57.364085 TX Vref Scan disable
8926 12:26:57.367188 == TX Byte 0 ==
8927 12:26:57.370239 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8928 12:26:57.373802 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8929 12:26:57.377126 == TX Byte 1 ==
8930 12:26:57.380495 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8931 12:26:57.383451 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8932 12:26:57.383886 ==
8933 12:26:57.387220 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 12:26:57.390315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 12:26:57.393407 ==
8936 12:26:57.404710
8937 12:26:57.408781 TX Vref early break, caculate TX vref
8938 12:26:57.411974 TX Vref=16, minBit 0, minWin=22, winSum=378
8939 12:26:57.414920 TX Vref=18, minBit 0, minWin=22, winSum=388
8940 12:26:57.418188 TX Vref=20, minBit 0, minWin=23, winSum=396
8941 12:26:57.421374 TX Vref=22, minBit 0, minWin=23, winSum=404
8942 12:26:57.424943 TX Vref=24, minBit 6, minWin=24, winSum=414
8943 12:26:57.432032 TX Vref=26, minBit 1, minWin=25, winSum=420
8944 12:26:57.434584 TX Vref=28, minBit 0, minWin=25, winSum=421
8945 12:26:57.438402 TX Vref=30, minBit 0, minWin=24, winSum=413
8946 12:26:57.441168 TX Vref=32, minBit 5, minWin=24, winSum=409
8947 12:26:57.444893 TX Vref=34, minBit 1, minWin=22, winSum=398
8948 12:26:57.450935 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8949 12:26:57.451445
8950 12:26:57.454514 Final TX Range 0 Vref 28
8951 12:26:57.455072
8952 12:26:57.455421 ==
8953 12:26:57.457512 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 12:26:57.461256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 12:26:57.461784 ==
8956 12:26:57.462130
8957 12:26:57.462451
8958 12:26:57.464015 TX Vref Scan disable
8959 12:26:57.471227 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8960 12:26:57.471752 == TX Byte 0 ==
8961 12:26:57.474203 u2DelayCellOfst[0]=18 cells (5 PI)
8962 12:26:57.477129 u2DelayCellOfst[1]=15 cells (4 PI)
8963 12:26:57.481025 u2DelayCellOfst[2]=0 cells (0 PI)
8964 12:26:57.483736 u2DelayCellOfst[3]=7 cells (2 PI)
8965 12:26:57.487411 u2DelayCellOfst[4]=7 cells (2 PI)
8966 12:26:57.490418 u2DelayCellOfst[5]=22 cells (6 PI)
8967 12:26:57.493672 u2DelayCellOfst[6]=22 cells (6 PI)
8968 12:26:57.497427 u2DelayCellOfst[7]=7 cells (2 PI)
8969 12:26:57.500631 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8970 12:26:57.504164 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8971 12:26:57.507175 == TX Byte 1 ==
8972 12:26:57.510398 u2DelayCellOfst[8]=0 cells (0 PI)
8973 12:26:57.513302 u2DelayCellOfst[9]=7 cells (2 PI)
8974 12:26:57.517213 u2DelayCellOfst[10]=15 cells (4 PI)
8975 12:26:57.517643 u2DelayCellOfst[11]=7 cells (2 PI)
8976 12:26:57.520553 u2DelayCellOfst[12]=18 cells (5 PI)
8977 12:26:57.523574 u2DelayCellOfst[13]=18 cells (5 PI)
8978 12:26:57.526648 u2DelayCellOfst[14]=22 cells (6 PI)
8979 12:26:57.530256 u2DelayCellOfst[15]=22 cells (6 PI)
8980 12:26:57.536513 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8981 12:26:57.540646 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8982 12:26:57.541178 DramC Write-DBI on
8983 12:26:57.543534 ==
8984 12:26:57.546368 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 12:26:57.549616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 12:26:57.550095 ==
8987 12:26:57.550447
8988 12:26:57.550770
8989 12:26:57.553177 TX Vref Scan disable
8990 12:26:57.553608 == TX Byte 0 ==
8991 12:26:57.559707 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8992 12:26:57.560152 == TX Byte 1 ==
8993 12:26:57.562674 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8994 12:26:57.566216 DramC Write-DBI off
8995 12:26:57.566709
8996 12:26:57.567145 [DATLAT]
8997 12:26:57.569531 Freq=1600, CH1 RK1
8998 12:26:57.570068
8999 12:26:57.570412 DATLAT Default: 0xf
9000 12:26:57.573316 0, 0xFFFF, sum = 0
9001 12:26:57.573849 1, 0xFFFF, sum = 0
9002 12:26:57.576121 2, 0xFFFF, sum = 0
9003 12:26:57.576627 3, 0xFFFF, sum = 0
9004 12:26:57.579320 4, 0xFFFF, sum = 0
9005 12:26:57.582285 5, 0xFFFF, sum = 0
9006 12:26:57.582722 6, 0xFFFF, sum = 0
9007 12:26:57.585868 7, 0xFFFF, sum = 0
9008 12:26:57.586302 8, 0xFFFF, sum = 0
9009 12:26:57.588996 9, 0xFFFF, sum = 0
9010 12:26:57.589437 10, 0xFFFF, sum = 0
9011 12:26:57.592983 11, 0xFFFF, sum = 0
9012 12:26:57.593523 12, 0xFFFF, sum = 0
9013 12:26:57.595813 13, 0x8FFF, sum = 0
9014 12:26:57.596247 14, 0x0, sum = 1
9015 12:26:57.598932 15, 0x0, sum = 2
9016 12:26:57.599365 16, 0x0, sum = 3
9017 12:26:57.602131 17, 0x0, sum = 4
9018 12:26:57.602610 best_step = 15
9019 12:26:57.603164
9020 12:26:57.603630 ==
9021 12:26:57.605652 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 12:26:57.612186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 12:26:57.612828 ==
9024 12:26:57.613320 RX Vref Scan: 0
9025 12:26:57.613788
9026 12:26:57.615272 RX Vref 0 -> 0, step: 1
9027 12:26:57.615704
9028 12:26:57.619049 RX Delay 11 -> 252, step: 4
9029 12:26:57.622520 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9030 12:26:57.625460 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9031 12:26:57.628606 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9032 12:26:57.635361 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9033 12:26:57.638431 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9034 12:26:57.641859 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9035 12:26:57.645359 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9036 12:26:57.648295 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9037 12:26:57.654789 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9038 12:26:57.658358 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9039 12:26:57.661317 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9040 12:26:57.664996 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9041 12:26:57.671085 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9042 12:26:57.674583 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9043 12:26:57.677652 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9044 12:26:57.681837 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9045 12:26:57.682312 ==
9046 12:26:57.684632 Dram Type= 6, Freq= 0, CH_1, rank 1
9047 12:26:57.691644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9048 12:26:57.692226 ==
9049 12:26:57.692610 DQS Delay:
9050 12:26:57.694647 DQS0 = 0, DQS1 = 0
9051 12:26:57.695158 DQM Delay:
9052 12:26:57.695538 DQM0 = 129, DQM1 = 125
9053 12:26:57.697991 DQ Delay:
9054 12:26:57.701536 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9055 12:26:57.704699 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
9056 12:26:57.707700 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9057 12:26:57.711457 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9058 12:26:57.711928
9059 12:26:57.712299
9060 12:26:57.712710
9061 12:26:57.714701 [DramC_TX_OE_Calibration] TA2
9062 12:26:57.717636 Original DQ_B0 (3 6) =30, OEN = 27
9063 12:26:57.721129 Original DQ_B1 (3 6) =30, OEN = 27
9064 12:26:57.724065 24, 0x0, End_B0=24 End_B1=24
9065 12:26:57.724543 25, 0x0, End_B0=25 End_B1=25
9066 12:26:57.727304 26, 0x0, End_B0=26 End_B1=26
9067 12:26:57.731273 27, 0x0, End_B0=27 End_B1=27
9068 12:26:57.734523 28, 0x0, End_B0=28 End_B1=28
9069 12:26:57.737365 29, 0x0, End_B0=29 End_B1=29
9070 12:26:57.737853 30, 0x0, End_B0=30 End_B1=30
9071 12:26:57.741027 31, 0x4141, End_B0=30 End_B1=30
9072 12:26:57.744077 Byte0 end_step=30 best_step=27
9073 12:26:57.747300 Byte1 end_step=30 best_step=27
9074 12:26:57.750371 Byte0 TX OE(2T, 0.5T) = (3, 3)
9075 12:26:57.753545 Byte1 TX OE(2T, 0.5T) = (3, 3)
9076 12:26:57.754028
9077 12:26:57.754640
9078 12:26:57.760416 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9079 12:26:57.764313 CH1 RK1: MR19=303, MR18=101C
9080 12:26:57.770425 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9081 12:26:57.773694 [RxdqsGatingPostProcess] freq 1600
9082 12:26:57.780764 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9083 12:26:57.781354 best DQS0 dly(2T, 0.5T) = (1, 1)
9084 12:26:57.783468 best DQS1 dly(2T, 0.5T) = (1, 1)
9085 12:26:57.787209 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9086 12:26:57.790093 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9087 12:26:57.793749 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 12:26:57.796854 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 12:26:57.799789 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 12:26:57.803320 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 12:26:57.806485 Pre-setting of DQS Precalculation
9092 12:26:57.810157 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9093 12:26:57.819801 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9094 12:26:57.826637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 12:26:57.827263
9096 12:26:57.827756
9097 12:26:57.829868 [Calibration Summary] 3200 Mbps
9098 12:26:57.830449 CH 0, Rank 0
9099 12:26:57.833020 SW Impedance : PASS
9100 12:26:57.833602 DUTY Scan : NO K
9101 12:26:57.835972 ZQ Calibration : PASS
9102 12:26:57.839951 Jitter Meter : NO K
9103 12:26:57.840531 CBT Training : PASS
9104 12:26:57.842771 Write leveling : PASS
9105 12:26:57.846657 RX DQS gating : PASS
9106 12:26:57.847296 RX DQ/DQS(RDDQC) : PASS
9107 12:26:57.849245 TX DQ/DQS : PASS
9108 12:26:57.852767 RX DATLAT : PASS
9109 12:26:57.853401 RX DQ/DQS(Engine): PASS
9110 12:26:57.855950 TX OE : PASS
9111 12:26:57.856417 All Pass.
9112 12:26:57.856852
9113 12:26:57.859020 CH 0, Rank 1
9114 12:26:57.859632 SW Impedance : PASS
9115 12:26:57.862673 DUTY Scan : NO K
9116 12:26:57.865846 ZQ Calibration : PASS
9117 12:26:57.866531 Jitter Meter : NO K
9118 12:26:57.869131 CBT Training : PASS
9119 12:26:57.872817 Write leveling : PASS
9120 12:26:57.873432 RX DQS gating : PASS
9121 12:26:57.875604 RX DQ/DQS(RDDQC) : PASS
9122 12:26:57.879043 TX DQ/DQS : PASS
9123 12:26:57.879649 RX DATLAT : PASS
9124 12:26:57.882097 RX DQ/DQS(Engine): PASS
9125 12:26:57.882626 TX OE : PASS
9126 12:26:57.885513 All Pass.
9127 12:26:57.885993
9128 12:26:57.886368 CH 1, Rank 0
9129 12:26:57.888805 SW Impedance : PASS
9130 12:26:57.892007 DUTY Scan : NO K
9131 12:26:57.892472 ZQ Calibration : PASS
9132 12:26:57.895579 Jitter Meter : NO K
9133 12:26:57.896072 CBT Training : PASS
9134 12:26:57.898470 Write leveling : PASS
9135 12:26:57.902293 RX DQS gating : PASS
9136 12:26:57.903102 RX DQ/DQS(RDDQC) : PASS
9137 12:26:57.905779 TX DQ/DQS : PASS
9138 12:26:57.908835 RX DATLAT : PASS
9139 12:26:57.909396 RX DQ/DQS(Engine): PASS
9140 12:26:57.911947 TX OE : PASS
9141 12:26:57.912450 All Pass.
9142 12:26:57.912827
9143 12:26:57.914930 CH 1, Rank 1
9144 12:26:57.915394 SW Impedance : PASS
9145 12:26:57.918483 DUTY Scan : NO K
9146 12:26:57.921702 ZQ Calibration : PASS
9147 12:26:57.922166 Jitter Meter : NO K
9148 12:26:57.924903 CBT Training : PASS
9149 12:26:57.928068 Write leveling : PASS
9150 12:26:57.928600 RX DQS gating : PASS
9151 12:26:57.932136 RX DQ/DQS(RDDQC) : PASS
9152 12:26:57.934975 TX DQ/DQS : PASS
9153 12:26:57.935447 RX DATLAT : PASS
9154 12:26:57.938164 RX DQ/DQS(Engine): PASS
9155 12:26:57.941503 TX OE : PASS
9156 12:26:57.942062 All Pass.
9157 12:26:57.942433
9158 12:26:57.942777 DramC Write-DBI on
9159 12:26:57.944540 PER_BANK_REFRESH: Hybrid Mode
9160 12:26:57.948206 TX_TRACKING: ON
9161 12:26:57.954484 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9162 12:26:57.964651 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9163 12:26:57.971068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9164 12:26:57.974787 [FAST_K] Save calibration result to emmc
9165 12:26:57.978102 sync common calibartion params.
9166 12:26:57.981005 sync cbt_mode0:1, 1:1
9167 12:26:57.981500 dram_init: ddr_geometry: 2
9168 12:26:57.984827 dram_init: ddr_geometry: 2
9169 12:26:57.987945 dram_init: ddr_geometry: 2
9170 12:26:57.990951 0:dram_rank_size:100000000
9171 12:26:57.991528 1:dram_rank_size:100000000
9172 12:26:57.997836 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9173 12:26:58.001340 DFS_SHUFFLE_HW_MODE: ON
9174 12:26:58.004190 dramc_set_vcore_voltage set vcore to 725000
9175 12:26:58.004659 Read voltage for 1600, 0
9176 12:26:58.007691 Vio18 = 0
9177 12:26:58.008338 Vcore = 725000
9178 12:26:58.008726 Vdram = 0
9179 12:26:58.011490 Vddq = 0
9180 12:26:58.011954 Vmddr = 0
9181 12:26:58.014301 switch to 3200 Mbps bootup
9182 12:26:58.014922 [DramcRunTimeConfig]
9183 12:26:58.017308 PHYPLL
9184 12:26:58.017799 DPM_CONTROL_AFTERK: ON
9185 12:26:58.021029 PER_BANK_REFRESH: ON
9186 12:26:58.024072 REFRESH_OVERHEAD_REDUCTION: ON
9187 12:26:58.024566 CMD_PICG_NEW_MODE: OFF
9188 12:26:58.027182 XRTWTW_NEW_MODE: ON
9189 12:26:58.027680 XRTRTR_NEW_MODE: ON
9190 12:26:58.030975 TX_TRACKING: ON
9191 12:26:58.031444 RDSEL_TRACKING: OFF
9192 12:26:58.034458 DQS Precalculation for DVFS: ON
9193 12:26:58.037381 RX_TRACKING: OFF
9194 12:26:58.037849 HW_GATING DBG: ON
9195 12:26:58.040703 ZQCS_ENABLE_LP4: ON
9196 12:26:58.041268 RX_PICG_NEW_MODE: ON
9197 12:26:58.044357 TX_PICG_NEW_MODE: ON
9198 12:26:58.044960 ENABLE_RX_DCM_DPHY: ON
9199 12:26:58.047604 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9200 12:26:58.050587 DUMMY_READ_FOR_TRACKING: OFF
9201 12:26:58.053580 !!! SPM_CONTROL_AFTERK: OFF
9202 12:26:58.057383 !!! SPM could not control APHY
9203 12:26:58.057923 IMPEDANCE_TRACKING: ON
9204 12:26:58.060576 TEMP_SENSOR: ON
9205 12:26:58.061045 HW_SAVE_FOR_SR: OFF
9206 12:26:58.063626 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9207 12:26:58.066758 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9208 12:26:58.070173 Read ODT Tracking: ON
9209 12:26:58.073643 Refresh Rate DeBounce: ON
9210 12:26:58.074186 DFS_NO_QUEUE_FLUSH: ON
9211 12:26:58.076749 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9212 12:26:58.080169 ENABLE_DFS_RUNTIME_MRW: OFF
9213 12:26:58.083868 DDR_RESERVE_NEW_MODE: ON
9214 12:26:58.084441 MR_CBT_SWITCH_FREQ: ON
9215 12:26:58.086961 =========================
9216 12:26:58.105517 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9217 12:26:58.108494 dram_init: ddr_geometry: 2
9218 12:26:58.127509 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9219 12:26:58.130747 dram_init: dram init end (result: 0)
9220 12:26:58.137825 DRAM-K: Full calibration passed in 24582 msecs
9221 12:26:58.140650 MRC: failed to locate region type 0.
9222 12:26:58.141118 DRAM rank0 size:0x100000000,
9223 12:26:58.143935 DRAM rank1 size=0x100000000
9224 12:26:58.153937 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9225 12:26:58.160439 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9226 12:26:58.166880 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9227 12:26:58.176887 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9228 12:26:58.177420 DRAM rank0 size:0x100000000,
9229 12:26:58.179851 DRAM rank1 size=0x100000000
9230 12:26:58.180270 CBMEM:
9231 12:26:58.183687 IMD: root @ 0xfffff000 254 entries.
9232 12:26:58.186817 IMD: root @ 0xffffec00 62 entries.
9233 12:26:58.189958 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9234 12:26:58.196852 WARNING: RO_VPD is uninitialized or empty.
9235 12:26:58.200498 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9236 12:26:58.207781 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9237 12:26:58.220314 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9238 12:26:58.231385 BS: romstage times (exec / console): total (unknown) / 24048 ms
9239 12:26:58.231825
9240 12:26:58.232224
9241 12:26:58.241245 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9242 12:26:58.245218 ARM64: Exception handlers installed.
9243 12:26:58.248186 ARM64: Testing exception
9244 12:26:58.251425 ARM64: Done test exception
9245 12:26:58.251891 Enumerating buses...
9246 12:26:58.254532 Show all devs... Before device enumeration.
9247 12:26:58.257655 Root Device: enabled 1
9248 12:26:58.261294 CPU_CLUSTER: 0: enabled 1
9249 12:26:58.261857 CPU: 00: enabled 1
9250 12:26:58.264432 Compare with tree...
9251 12:26:58.264851 Root Device: enabled 1
9252 12:26:58.268146 CPU_CLUSTER: 0: enabled 1
9253 12:26:58.271465 CPU: 00: enabled 1
9254 12:26:58.271912 Root Device scanning...
9255 12:26:58.274577 scan_static_bus for Root Device
9256 12:26:58.277752 CPU_CLUSTER: 0 enabled
9257 12:26:58.280770 scan_static_bus for Root Device done
9258 12:26:58.284734 scan_bus: bus Root Device finished in 8 msecs
9259 12:26:58.285157 done
9260 12:26:58.290920 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9261 12:26:58.294397 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9262 12:26:58.300854 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9263 12:26:58.303927 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9264 12:26:58.307755 Allocating resources...
9265 12:26:58.310903 Reading resources...
9266 12:26:58.314152 Root Device read_resources bus 0 link: 0
9267 12:26:58.317654 DRAM rank0 size:0x100000000,
9268 12:26:58.318085 DRAM rank1 size=0x100000000
9269 12:26:58.320657 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9270 12:26:58.324353 CPU: 00 missing read_resources
9271 12:26:58.330784 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9272 12:26:58.333677 Root Device read_resources bus 0 link: 0 done
9273 12:26:58.337320 Done reading resources.
9274 12:26:58.340327 Show resources in subtree (Root Device)...After reading.
9275 12:26:58.344212 Root Device child on link 0 CPU_CLUSTER: 0
9276 12:26:58.346955 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 12:26:58.357122 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 12:26:58.357652 CPU: 00
9279 12:26:58.360291 Root Device assign_resources, bus 0 link: 0
9280 12:26:58.363296 CPU_CLUSTER: 0 missing set_resources
9281 12:26:58.369975 Root Device assign_resources, bus 0 link: 0 done
9282 12:26:58.370399 Done setting resources.
9283 12:26:58.376352 Show resources in subtree (Root Device)...After assigning values.
9284 12:26:58.380393 Root Device child on link 0 CPU_CLUSTER: 0
9285 12:26:58.383300 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 12:26:58.393403 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 12:26:58.394072 CPU: 00
9288 12:26:58.396269 Done allocating resources.
9289 12:26:58.402975 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9290 12:26:58.403468 Enabling resources...
9291 12:26:58.406055 done.
9292 12:26:58.410001 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9293 12:26:58.413038 Initializing devices...
9294 12:26:58.413522 Root Device init
9295 12:26:58.416140 init hardware done!
9296 12:26:58.416584 0x00000018: ctrlr->caps
9297 12:26:58.419366 52.000 MHz: ctrlr->f_max
9298 12:26:58.422516 0.400 MHz: ctrlr->f_min
9299 12:26:58.426103 0x40ff8080: ctrlr->voltages
9300 12:26:58.426552 sclk: 390625
9301 12:26:58.426944 Bus Width = 1
9302 12:26:58.428876 sclk: 390625
9303 12:26:58.429336 Bus Width = 1
9304 12:26:58.432572 Early init status = 3
9305 12:26:58.435542 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9306 12:26:58.439231 in-header: 03 fc 00 00 01 00 00 00
9307 12:26:58.442190 in-data: 00
9308 12:26:58.445234 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9309 12:26:58.450287 in-header: 03 fd 00 00 00 00 00 00
9310 12:26:58.453771 in-data:
9311 12:26:58.457021 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9312 12:26:58.460852 in-header: 03 fc 00 00 01 00 00 00
9313 12:26:58.464601 in-data: 00
9314 12:26:58.467773 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9315 12:26:58.473238 in-header: 03 fd 00 00 00 00 00 00
9316 12:26:58.476240 in-data:
9317 12:26:58.479473 [SSUSB] Setting up USB HOST controller...
9318 12:26:58.483297 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9319 12:26:58.486359 [SSUSB] phy power-on done.
9320 12:26:58.489524 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9321 12:26:58.496270 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9322 12:26:58.499499 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9323 12:26:58.506394 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9324 12:26:58.512530 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9325 12:26:58.519369 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9326 12:26:58.525430 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9327 12:26:58.532501 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9328 12:26:58.536055 SPM: binary array size = 0x9dc
9329 12:26:58.539068 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9330 12:26:58.545448 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9331 12:26:58.551934 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9332 12:26:58.558646 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9333 12:26:58.562428 configure_display: Starting display init
9334 12:26:58.596623 anx7625_power_on_init: Init interface.
9335 12:26:58.599711 anx7625_disable_pd_protocol: Disabled PD feature.
9336 12:26:58.602511 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9337 12:26:58.630745 anx7625_start_dp_work: Secure OCM version=00
9338 12:26:58.633643 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9339 12:26:58.648864 sp_tx_get_edid_block: EDID Block = 1
9340 12:26:58.751852 Extracted contents:
9341 12:26:58.754744 header: 00 ff ff ff ff ff ff 00
9342 12:26:58.758226 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9343 12:26:58.761516 version: 01 04
9344 12:26:58.764566 basic params: 95 1f 11 78 0a
9345 12:26:58.767639 chroma info: 76 90 94 55 54 90 27 21 50 54
9346 12:26:58.771450 established: 00 00 00
9347 12:26:58.778042 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9348 12:26:58.784255 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9349 12:26:58.787864 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 12:26:58.794721 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9351 12:26:58.800848 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9352 12:26:58.804272 extensions: 00
9353 12:26:58.804732 checksum: fb
9354 12:26:58.805096
9355 12:26:58.810685 Manufacturer: IVO Model 57d Serial Number 0
9356 12:26:58.811179 Made week 0 of 2020
9357 12:26:58.813817 EDID version: 1.4
9358 12:26:58.814273 Digital display
9359 12:26:58.817562 6 bits per primary color channel
9360 12:26:58.820844 DisplayPort interface
9361 12:26:58.821318 Maximum image size: 31 cm x 17 cm
9362 12:26:58.823549 Gamma: 220%
9363 12:26:58.824004 Check DPMS levels
9364 12:26:58.830220 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9365 12:26:58.834043 First detailed timing is preferred timing
9366 12:26:58.837051 Established timings supported:
9367 12:26:58.837507 Standard timings supported:
9368 12:26:58.840192 Detailed timings
9369 12:26:58.843297 Hex of detail: 383680a07038204018303c0035ae10000019
9370 12:26:58.849911 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9371 12:26:58.853910 0780 0798 07c8 0820 hborder 0
9372 12:26:58.856624 0438 043b 0447 0458 vborder 0
9373 12:26:58.860265 -hsync -vsync
9374 12:26:58.860684 Did detailed timing
9375 12:26:58.866930 Hex of detail: 000000000000000000000000000000000000
9376 12:26:58.869833 Manufacturer-specified data, tag 0
9377 12:26:58.873042 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9378 12:26:58.876872 ASCII string: InfoVision
9379 12:26:58.880171 Hex of detail: 000000fe00523134304e574635205248200a
9380 12:26:58.882968 ASCII string: R140NWF5 RH
9381 12:26:58.883380 Checksum
9382 12:26:58.886582 Checksum: 0xfb (valid)
9383 12:26:58.889610 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9384 12:26:58.893054 DSI data_rate: 832800000 bps
9385 12:26:58.899890 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9386 12:26:58.903068 anx7625_parse_edid: pixelclock(138800).
9387 12:26:58.906110 hactive(1920), hsync(48), hfp(24), hbp(88)
9388 12:26:58.909781 vactive(1080), vsync(12), vfp(3), vbp(17)
9389 12:26:58.913009 anx7625_dsi_config: config dsi.
9390 12:26:58.919366 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9391 12:26:58.933528 anx7625_dsi_config: success to config DSI
9392 12:26:58.936911 anx7625_dp_start: MIPI phy setup OK.
9393 12:26:58.940085 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9394 12:26:58.943172 mtk_ddp_mode_set invalid vrefresh 60
9395 12:26:58.946796 main_disp_path_setup
9396 12:26:58.947227 ovl_layer_smi_id_en
9397 12:26:58.949996 ovl_layer_smi_id_en
9398 12:26:58.950407 ccorr_config
9399 12:26:58.950734 aal_config
9400 12:26:58.953068 gamma_config
9401 12:26:58.953480 postmask_config
9402 12:26:58.956639 dither_config
9403 12:26:58.960044 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9404 12:26:58.966895 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9405 12:26:58.969852 Root Device init finished in 553 msecs
9406 12:26:58.972920 CPU_CLUSTER: 0 init
9407 12:26:58.979616 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9408 12:26:58.986487 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9409 12:26:58.987027 APU_MBOX 0x190000b0 = 0x10001
9410 12:26:58.989568 APU_MBOX 0x190001b0 = 0x10001
9411 12:26:58.993102 APU_MBOX 0x190005b0 = 0x10001
9412 12:26:58.996088 APU_MBOX 0x190006b0 = 0x10001
9413 12:26:59.002636 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9414 12:26:59.012524 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9415 12:26:59.024588 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9416 12:26:59.031572 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9417 12:26:59.043073 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9418 12:26:59.052406 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9419 12:26:59.055386 CPU_CLUSTER: 0 init finished in 81 msecs
9420 12:26:59.058565 Devices initialized
9421 12:26:59.062472 Show all devs... After init.
9422 12:26:59.062939 Root Device: enabled 1
9423 12:26:59.065482 CPU_CLUSTER: 0: enabled 1
9424 12:26:59.068640 CPU: 00: enabled 1
9425 12:26:59.072282 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9426 12:26:59.075347 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9427 12:26:59.078377 ELOG: NV offset 0x57f000 size 0x1000
9428 12:26:59.085468 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9429 12:26:59.091658 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9430 12:26:59.095276 ELOG: Event(17) added with size 13 at 2023-06-06 12:27:04 UTC
9431 12:26:59.102067 out: cmd=0x121: 03 db 21 01 00 00 00 00
9432 12:26:59.105028 in-header: 03 46 00 00 2c 00 00 00
9433 12:26:59.114650 in-data: 18 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9434 12:26:59.121640 ELOG: Event(A1) added with size 10 at 2023-06-06 12:27:04 UTC
9435 12:26:59.127870 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9436 12:26:59.134387 ELOG: Event(A0) added with size 9 at 2023-06-06 12:27:04 UTC
9437 12:26:59.138056 elog_add_boot_reason: Logged dev mode boot
9438 12:26:59.144745 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9439 12:26:59.145234 Finalize devices...
9440 12:26:59.147989 Devices finalized
9441 12:26:59.151088 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9442 12:26:59.154179 Writing coreboot table at 0xffe64000
9443 12:26:59.158067 0. 000000000010a000-0000000000113fff: RAMSTAGE
9444 12:26:59.164192 1. 0000000040000000-00000000400fffff: RAM
9445 12:26:59.167449 2. 0000000040100000-000000004032afff: RAMSTAGE
9446 12:26:59.170910 3. 000000004032b000-00000000545fffff: RAM
9447 12:26:59.173974 4. 0000000054600000-000000005465ffff: BL31
9448 12:26:59.177465 5. 0000000054660000-00000000ffe63fff: RAM
9449 12:26:59.183875 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9450 12:26:59.187563 7. 0000000100000000-000000023fffffff: RAM
9451 12:26:59.191034 Passing 5 GPIOs to payload:
9452 12:26:59.193945 NAME | PORT | POLARITY | VALUE
9453 12:26:59.200807 EC in RW | 0x000000aa | low | undefined
9454 12:26:59.203992 EC interrupt | 0x00000005 | low | undefined
9455 12:26:59.207032 TPM interrupt | 0x000000ab | high | undefined
9456 12:26:59.213583 SD card detect | 0x00000011 | high | undefined
9457 12:26:59.217141 speaker enable | 0x00000093 | high | undefined
9458 12:26:59.220114 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9459 12:26:59.223781 in-header: 03 f9 00 00 02 00 00 00
9460 12:26:59.226937 in-data: 02 00
9461 12:26:59.230552 ADC[4]: Raw value=893341 ID=7
9462 12:26:59.233621 ADC[3]: Raw value=213440 ID=1
9463 12:26:59.234085 RAM Code: 0x71
9464 12:26:59.236988 ADC[6]: Raw value=74722 ID=0
9465 12:26:59.240068 ADC[5]: Raw value=212330 ID=1
9466 12:26:59.240544 SKU Code: 0x1
9467 12:26:59.246994 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9468 12:26:59.247858 coreboot table: 964 bytes.
9469 12:26:59.250093 IMD ROOT 0. 0xfffff000 0x00001000
9470 12:26:59.253324 IMD SMALL 1. 0xffffe000 0x00001000
9471 12:26:59.256387 RO MCACHE 2. 0xffffc000 0x00001104
9472 12:26:59.260229 CONSOLE 3. 0xfff7c000 0x00080000
9473 12:26:59.263374 FMAP 4. 0xfff7b000 0x00000452
9474 12:26:59.266377 TIME STAMP 5. 0xfff7a000 0x00000910
9475 12:26:59.269590 VBOOT WORK 6. 0xfff66000 0x00014000
9476 12:26:59.272727 RAMOOPS 7. 0xffe66000 0x00100000
9477 12:26:59.276519 COREBOOT 8. 0xffe64000 0x00002000
9478 12:26:59.279638 IMD small region:
9479 12:26:59.283042 IMD ROOT 0. 0xffffec00 0x00000400
9480 12:26:59.286706 VPD 1. 0xffffeba0 0x0000004c
9481 12:26:59.289513 MMC STATUS 2. 0xffffeb80 0x00000004
9482 12:26:59.296054 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9483 12:26:59.296480 Probing TPM: done!
9484 12:26:59.303079 Connected to device vid:did:rid of 1ae0:0028:00
9485 12:26:59.309315 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9486 12:26:59.313045 Initialized TPM device CR50 revision 0
9487 12:26:59.316244 Checking cr50 for pending updates
9488 12:26:59.321634 Reading cr50 TPM mode
9489 12:26:59.330225 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9490 12:26:59.337060 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9491 12:26:59.376877 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9492 12:26:59.380474 Checking segment from ROM address 0x40100000
9493 12:26:59.386613 Checking segment from ROM address 0x4010001c
9494 12:26:59.390241 Loading segment from ROM address 0x40100000
9495 12:26:59.390922 code (compression=0)
9496 12:26:59.399940 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9497 12:26:59.406583 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9498 12:26:59.407077 it's not compressed!
9499 12:26:59.413593 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9500 12:26:59.420070 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9501 12:26:59.437413 Loading segment from ROM address 0x4010001c
9502 12:26:59.437843 Entry Point 0x80000000
9503 12:26:59.441170 Loaded segments
9504 12:26:59.444124 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9505 12:26:59.450825 Jumping to boot code at 0x80000000(0xffe64000)
9506 12:26:59.457234 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9507 12:26:59.464278 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9508 12:26:59.471870 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9509 12:26:59.475298 Checking segment from ROM address 0x40100000
9510 12:26:59.478895 Checking segment from ROM address 0x4010001c
9511 12:26:59.485250 Loading segment from ROM address 0x40100000
9512 12:26:59.485678 code (compression=1)
9513 12:26:59.492112 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9514 12:26:59.501764 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9515 12:26:59.502284 using LZMA
9516 12:26:59.510439 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9517 12:26:59.517222 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9518 12:26:59.520170 Loading segment from ROM address 0x4010001c
9519 12:26:59.520747 Entry Point 0x54601000
9520 12:26:59.523541 Loaded segments
9521 12:26:59.526518 NOTICE: MT8192 bl31_setup
9522 12:26:59.533607 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9523 12:26:59.537408 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9524 12:26:59.540571 WARNING: region 0:
9525 12:26:59.543738 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 12:26:59.544326 WARNING: region 1:
9527 12:26:59.550308 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9528 12:26:59.553880 WARNING: region 2:
9529 12:26:59.556984 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9530 12:26:59.560208 WARNING: region 3:
9531 12:26:59.563917 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 12:26:59.566969 WARNING: region 4:
9533 12:26:59.573880 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9534 12:26:59.574329 WARNING: region 5:
9535 12:26:59.576974 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 12:26:59.580246 WARNING: region 6:
9537 12:26:59.583386 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 12:26:59.587285 WARNING: region 7:
9539 12:26:59.590393 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 12:26:59.597075 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9541 12:26:59.600309 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9542 12:26:59.603487 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9543 12:26:59.609994 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9544 12:26:59.613571 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9545 12:26:59.620235 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9546 12:26:59.623151 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9547 12:26:59.626656 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9548 12:26:59.633134 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9549 12:26:59.636481 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9550 12:26:59.640047 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9551 12:26:59.646784 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9552 12:26:59.649857 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9553 12:26:59.656606 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9554 12:26:59.659515 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9555 12:26:59.663393 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9556 12:26:59.669581 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9557 12:26:59.673333 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9558 12:26:59.679632 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9559 12:26:59.683294 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9560 12:26:59.686372 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9561 12:26:59.692969 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9562 12:26:59.696632 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9563 12:26:59.699651 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9564 12:26:59.706465 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9565 12:26:59.709625 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9566 12:26:59.716344 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9567 12:26:59.719539 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9568 12:26:59.726122 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9569 12:26:59.729236 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9570 12:26:59.732715 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9571 12:26:59.739122 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9572 12:26:59.742600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9573 12:26:59.746445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9574 12:26:59.749161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9575 12:26:59.755611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9576 12:26:59.759212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9577 12:26:59.762204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9578 12:26:59.765710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9579 12:26:59.772675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9580 12:26:59.775844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9581 12:26:59.779063 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9582 12:26:59.782260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9583 12:26:59.788983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9584 12:26:59.792665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9585 12:26:59.795521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9586 12:26:59.802361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9587 12:26:59.805319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9588 12:26:59.808608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9589 12:26:59.815386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9590 12:26:59.818973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9591 12:26:59.825094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9592 12:26:59.828970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9593 12:26:59.832241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9594 12:26:59.838585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9595 12:26:59.842082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9596 12:26:59.848615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9597 12:26:59.852083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9598 12:26:59.858727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9599 12:26:59.862229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9600 12:26:59.865217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9601 12:26:59.872265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9602 12:26:59.875109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9603 12:26:59.882016 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9604 12:26:59.885129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9605 12:26:59.891694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9606 12:26:59.895243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9607 12:26:59.901584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9608 12:26:59.905332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9609 12:26:59.908423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9610 12:26:59.915189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9611 12:26:59.918289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9612 12:26:59.925012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9613 12:26:59.928206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9614 12:26:59.934917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9615 12:26:59.938530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9616 12:26:59.941533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9617 12:26:59.948222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9618 12:26:59.951335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9619 12:26:59.958399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9620 12:26:59.961246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9621 12:26:59.968245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9622 12:26:59.971736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9623 12:26:59.978092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9624 12:26:59.981142 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9625 12:26:59.985111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9626 12:26:59.991136 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9627 12:26:59.994924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9628 12:27:00.001046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9629 12:27:00.004811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9630 12:27:00.011210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9631 12:27:00.014260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9632 12:27:00.021291 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9633 12:27:00.024481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9634 12:27:00.027424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9635 12:27:00.034261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9636 12:27:00.037449 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9637 12:27:00.041130 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9638 12:27:00.047515 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9639 12:27:00.050572 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9640 12:27:00.054153 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9641 12:27:00.060907 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9642 12:27:00.064197 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9643 12:27:00.067461 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9644 12:27:00.074035 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9645 12:27:00.077608 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9646 12:27:00.083687 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9647 12:27:00.087702 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9648 12:27:00.090617 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9649 12:27:00.097061 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9650 12:27:00.100247 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9651 12:27:00.107314 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9652 12:27:00.110437 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9653 12:27:00.116960 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9654 12:27:00.120578 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9655 12:27:00.123728 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9656 12:27:00.126863 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9657 12:27:00.133528 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9658 12:27:00.137131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9659 12:27:00.140118 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9660 12:27:00.146691 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9661 12:27:00.150499 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9662 12:27:00.153539 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9663 12:27:00.157412 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9664 12:27:00.163348 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9665 12:27:00.166579 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9666 12:27:00.173479 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9667 12:27:00.176523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9668 12:27:00.180010 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9669 12:27:00.186784 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9670 12:27:00.189956 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9671 12:27:00.196745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9672 12:27:00.199796 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9673 12:27:00.202873 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9674 12:27:00.209888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9675 12:27:00.213001 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9676 12:27:00.219929 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9677 12:27:00.222954 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9678 12:27:00.226178 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9679 12:27:00.232694 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9680 12:27:00.236080 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9681 12:27:00.242923 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9682 12:27:00.245988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9683 12:27:00.249096 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9684 12:27:00.256100 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9685 12:27:00.259261 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9686 12:27:00.266012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9687 12:27:00.269335 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9688 12:27:00.272629 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9689 12:27:00.279536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9690 12:27:00.282388 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9691 12:27:00.285982 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9692 12:27:00.292621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9693 12:27:00.295671 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9694 12:27:00.302500 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9695 12:27:00.305445 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9696 12:27:00.312165 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9697 12:27:00.315267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9698 12:27:00.318778 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9699 12:27:00.325132 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9700 12:27:00.328748 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9701 12:27:00.335105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9702 12:27:00.338342 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9703 12:27:00.341879 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9704 12:27:00.348729 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9705 12:27:00.351688 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9706 12:27:00.357885 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9707 12:27:00.361690 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9708 12:27:00.364846 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9709 12:27:00.371609 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9710 12:27:00.374927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9711 12:27:00.381717 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9712 12:27:00.384487 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9713 12:27:00.387518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9714 12:27:00.394071 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9715 12:27:00.397670 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9716 12:27:00.403940 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9717 12:27:00.407843 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9718 12:27:00.410705 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9719 12:27:00.417365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9720 12:27:00.420691 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9721 12:27:00.427473 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9722 12:27:00.430595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9723 12:27:00.433615 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9724 12:27:00.440594 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9725 12:27:00.443783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9726 12:27:00.450459 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9727 12:27:00.453634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9728 12:27:00.456895 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9729 12:27:00.463806 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9730 12:27:00.466871 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9731 12:27:00.473168 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9732 12:27:00.476977 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9733 12:27:00.483131 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9734 12:27:00.487074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9735 12:27:00.489815 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9736 12:27:00.496443 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9737 12:27:00.499600 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9738 12:27:00.506799 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9739 12:27:00.510051 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9740 12:27:00.516166 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9741 12:27:00.519387 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9742 12:27:00.522993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9743 12:27:00.529176 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9744 12:27:00.532968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9745 12:27:00.539630 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9746 12:27:00.542659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9747 12:27:00.549036 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9748 12:27:00.552575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9749 12:27:00.556161 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9750 12:27:00.562526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9751 12:27:00.565714 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9752 12:27:00.572636 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9753 12:27:00.575862 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9754 12:27:00.578936 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9755 12:27:00.585684 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9756 12:27:00.588888 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9757 12:27:00.595621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9758 12:27:00.598738 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9759 12:27:00.605188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9760 12:27:00.608641 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9761 12:27:00.612064 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9762 12:27:00.618720 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9763 12:27:00.621826 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9764 12:27:00.628658 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9765 12:27:00.631690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9766 12:27:00.638550 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9767 12:27:00.641630 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9768 12:27:00.644809 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9769 12:27:00.651808 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9770 12:27:00.654718 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9771 12:27:00.657744 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9772 12:27:00.661455 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9773 12:27:00.667787 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9774 12:27:00.670952 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9775 12:27:00.674622 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9776 12:27:00.680842 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9777 12:27:00.684416 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9778 12:27:00.687473 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9779 12:27:00.694023 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9780 12:27:00.697204 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9781 12:27:00.704281 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9782 12:27:00.707211 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9783 12:27:00.710767 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9784 12:27:00.717157 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9785 12:27:00.720752 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9786 12:27:00.727598 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9787 12:27:00.730593 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9788 12:27:00.733614 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9789 12:27:00.740386 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9790 12:27:00.743437 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9791 12:27:00.747141 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9792 12:27:00.753418 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9793 12:27:00.756546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9794 12:27:00.763420 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9795 12:27:00.766479 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9796 12:27:00.769718 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9797 12:27:00.776830 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9798 12:27:00.779926 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9799 12:27:00.783097 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9800 12:27:00.789743 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9801 12:27:00.792876 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9802 12:27:00.799248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9803 12:27:00.803278 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9804 12:27:00.805963 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9805 12:27:00.812996 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9806 12:27:00.815780 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9807 12:27:00.822790 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9808 12:27:00.825810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9809 12:27:00.828646 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9810 12:27:00.832403 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9811 12:27:00.835417 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9812 12:27:00.842216 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9813 12:27:00.845215 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9814 12:27:00.848987 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9815 12:27:00.852039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9816 12:27:00.858718 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9817 12:27:00.861925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9818 12:27:00.864973 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9819 12:27:00.868669 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9820 12:27:00.874902 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9821 12:27:00.878054 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9822 12:27:00.884916 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9823 12:27:00.888049 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9824 12:27:00.891618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9825 12:27:00.897983 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9826 12:27:00.901122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9827 12:27:00.908139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9828 12:27:00.911179 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9829 12:27:00.914354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9830 12:27:00.921383 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9831 12:27:00.924503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9832 12:27:00.930814 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9833 12:27:00.934210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9834 12:27:00.940971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9835 12:27:00.944118 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9836 12:27:00.950862 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9837 12:27:00.953930 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9838 12:27:00.957424 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9839 12:27:00.964107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9840 12:27:00.967279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9841 12:27:00.973872 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9842 12:27:00.977065 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9843 12:27:00.980260 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9844 12:27:00.987163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9845 12:27:00.990252 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9846 12:27:00.996510 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9847 12:27:01.000306 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9848 12:27:01.006479 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9849 12:27:01.010169 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9850 12:27:01.013390 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9851 12:27:01.019738 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9852 12:27:01.022994 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9853 12:27:01.029539 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9854 12:27:01.033019 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9855 12:27:01.036744 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9856 12:27:01.043098 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9857 12:27:01.046240 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9858 12:27:01.052883 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9859 12:27:01.055939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9860 12:27:01.062953 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9861 12:27:01.066024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9862 12:27:01.069566 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9863 12:27:01.076065 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9864 12:27:01.079028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9865 12:27:01.085864 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9866 12:27:01.089062 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9867 12:27:01.095234 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9868 12:27:01.099034 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9869 12:27:01.102151 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9870 12:27:01.108938 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9871 12:27:01.112090 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9872 12:27:01.118350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9873 12:27:01.122143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9874 12:27:01.125443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9875 12:27:01.131584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9876 12:27:01.135365 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9877 12:27:01.142115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9878 12:27:01.145384 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9879 12:27:01.148482 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9880 12:27:01.155093 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9881 12:27:01.158094 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9882 12:27:01.164639 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9883 12:27:01.168254 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9884 12:27:01.175069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9885 12:27:01.177988 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9886 12:27:01.181440 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9887 12:27:01.188127 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9888 12:27:01.191259 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9889 12:27:01.198071 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9890 12:27:01.201218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9891 12:27:01.207522 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9892 12:27:01.211322 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9893 12:27:01.214592 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9894 12:27:01.220951 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9895 12:27:01.224738 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9896 12:27:01.231133 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9897 12:27:01.234342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9898 12:27:01.240679 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9899 12:27:01.244321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9900 12:27:01.247346 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9901 12:27:01.254169 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9902 12:27:01.257553 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9903 12:27:01.264033 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9904 12:27:01.267091 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9905 12:27:01.273796 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9906 12:27:01.277141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9907 12:27:01.283782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9908 12:27:01.286792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9909 12:27:01.290277 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9910 12:27:01.296825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9911 12:27:01.300009 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9912 12:27:01.306429 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9913 12:27:01.310183 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9914 12:27:01.316464 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9915 12:27:01.319714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9916 12:27:01.326687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9917 12:27:01.329836 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9918 12:27:01.332932 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9919 12:27:01.339278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9920 12:27:01.342961 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9921 12:27:01.349699 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9922 12:27:01.352752 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9923 12:27:01.359037 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9924 12:27:01.362348 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9925 12:27:01.368644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9926 12:27:01.372283 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9927 12:27:01.375544 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9928 12:27:01.382113 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9929 12:27:01.385679 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9930 12:27:01.392282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9931 12:27:01.395578 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9932 12:27:01.401703 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9933 12:27:01.405303 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9934 12:27:01.412168 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9935 12:27:01.415246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9936 12:27:01.418308 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9937 12:27:01.425293 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9938 12:27:01.428337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9939 12:27:01.435213 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9940 12:27:01.438286 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9941 12:27:01.445170 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9942 12:27:01.448323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9943 12:27:01.451414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9944 12:27:01.457909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9945 12:27:01.461173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9946 12:27:01.468000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9947 12:27:01.471048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9948 12:27:01.477510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9949 12:27:01.481238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9950 12:27:01.487786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9951 12:27:01.490704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9952 12:27:01.497267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9953 12:27:01.500866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9954 12:27:01.507525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9955 12:27:01.510286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9956 12:27:01.517172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9957 12:27:01.520398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9958 12:27:01.526694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9959 12:27:01.530565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9960 12:27:01.536863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9961 12:27:01.540069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9962 12:27:01.546446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9963 12:27:01.550191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9964 12:27:01.556586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9965 12:27:01.560202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9966 12:27:01.566388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9967 12:27:01.569547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9968 12:27:01.576404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9969 12:27:01.579521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9970 12:27:01.586126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9971 12:27:01.589573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9972 12:27:01.596416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9973 12:27:01.603038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9974 12:27:01.606044 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9975 12:27:01.606127 INFO: [APUAPC] vio 0
9976 12:27:01.613523 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9977 12:27:01.616607 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9978 12:27:01.620060 INFO: [APUAPC] D0_APC_0: 0x400510
9979 12:27:01.623076 INFO: [APUAPC] D0_APC_1: 0x0
9980 12:27:01.626632 INFO: [APUAPC] D0_APC_2: 0x1540
9981 12:27:01.629675 INFO: [APUAPC] D0_APC_3: 0x0
9982 12:27:01.632900 INFO: [APUAPC] D1_APC_0: 0xffffffff
9983 12:27:01.636079 INFO: [APUAPC] D1_APC_1: 0xffffffff
9984 12:27:01.639814 INFO: [APUAPC] D1_APC_2: 0x3fffff
9985 12:27:01.642956 INFO: [APUAPC] D1_APC_3: 0x0
9986 12:27:01.646113 INFO: [APUAPC] D2_APC_0: 0xffffffff
9987 12:27:01.649492 INFO: [APUAPC] D2_APC_1: 0xffffffff
9988 12:27:01.653095 INFO: [APUAPC] D2_APC_2: 0x3fffff
9989 12:27:01.656245 INFO: [APUAPC] D2_APC_3: 0x0
9990 12:27:01.659437 INFO: [APUAPC] D3_APC_0: 0xffffffff
9991 12:27:01.662582 INFO: [APUAPC] D3_APC_1: 0xffffffff
9992 12:27:01.666219 INFO: [APUAPC] D3_APC_2: 0x3fffff
9993 12:27:01.669396 INFO: [APUAPC] D3_APC_3: 0x0
9994 12:27:01.672618 INFO: [APUAPC] D4_APC_0: 0xffffffff
9995 12:27:01.675784 INFO: [APUAPC] D4_APC_1: 0xffffffff
9996 12:27:01.679468 INFO: [APUAPC] D4_APC_2: 0x3fffff
9997 12:27:01.682547 INFO: [APUAPC] D4_APC_3: 0x0
9998 12:27:01.685610 INFO: [APUAPC] D5_APC_0: 0xffffffff
9999 12:27:01.689334 INFO: [APUAPC] D5_APC_1: 0xffffffff
10000 12:27:01.692266 INFO: [APUAPC] D5_APC_2: 0x3fffff
10001 12:27:01.695920 INFO: [APUAPC] D5_APC_3: 0x0
10002 12:27:01.699068 INFO: [APUAPC] D6_APC_0: 0xffffffff
10003 12:27:01.702607 INFO: [APUAPC] D6_APC_1: 0xffffffff
10004 12:27:01.705646 INFO: [APUAPC] D6_APC_2: 0x3fffff
10005 12:27:01.705729 INFO: [APUAPC] D6_APC_3: 0x0
10006 12:27:01.712360 INFO: [APUAPC] D7_APC_0: 0xffffffff
10007 12:27:01.716025 INFO: [APUAPC] D7_APC_1: 0xffffffff
10008 12:27:01.718826 INFO: [APUAPC] D7_APC_2: 0x3fffff
10009 12:27:01.718948 INFO: [APUAPC] D7_APC_3: 0x0
10010 12:27:01.722372 INFO: [APUAPC] D8_APC_0: 0xffffffff
10011 12:27:01.728905 INFO: [APUAPC] D8_APC_1: 0xffffffff
10012 12:27:01.732048 INFO: [APUAPC] D8_APC_2: 0x3fffff
10013 12:27:01.732129 INFO: [APUAPC] D8_APC_3: 0x0
10014 12:27:01.735074 INFO: [APUAPC] D9_APC_0: 0xffffffff
10015 12:27:01.738831 INFO: [APUAPC] D9_APC_1: 0xffffffff
10016 12:27:01.741891 INFO: [APUAPC] D9_APC_2: 0x3fffff
10017 12:27:01.745057 INFO: [APUAPC] D9_APC_3: 0x0
10018 12:27:01.748305 INFO: [APUAPC] D10_APC_0: 0xffffffff
10019 12:27:01.752064 INFO: [APUAPC] D10_APC_1: 0xffffffff
10020 12:27:01.755092 INFO: [APUAPC] D10_APC_2: 0x3fffff
10021 12:27:01.758103 INFO: [APUAPC] D10_APC_3: 0x0
10022 12:27:01.761944 INFO: [APUAPC] D11_APC_0: 0xffffffff
10023 12:27:01.768130 INFO: [APUAPC] D11_APC_1: 0xffffffff
10024 12:27:01.771813 INFO: [APUAPC] D11_APC_2: 0x3fffff
10025 12:27:01.771897 INFO: [APUAPC] D11_APC_3: 0x0
10026 12:27:01.778173 INFO: [APUAPC] D12_APC_0: 0xffffffff
10027 12:27:01.781288 INFO: [APUAPC] D12_APC_1: 0xffffffff
10028 12:27:01.785021 INFO: [APUAPC] D12_APC_2: 0x3fffff
10029 12:27:01.785103 INFO: [APUAPC] D12_APC_3: 0x0
10030 12:27:01.791719 INFO: [APUAPC] D13_APC_0: 0xffffffff
10031 12:27:01.794891 INFO: [APUAPC] D13_APC_1: 0xffffffff
10032 12:27:01.798068 INFO: [APUAPC] D13_APC_2: 0x3fffff
10033 12:27:01.801062 INFO: [APUAPC] D13_APC_3: 0x0
10034 12:27:01.804360 INFO: [APUAPC] D14_APC_0: 0xffffffff
10035 12:27:01.808130 INFO: [APUAPC] D14_APC_1: 0xffffffff
10036 12:27:01.811055 INFO: [APUAPC] D14_APC_2: 0x3fffff
10037 12:27:01.814723 INFO: [APUAPC] D14_APC_3: 0x0
10038 12:27:01.817818 INFO: [APUAPC] D15_APC_0: 0xffffffff
10039 12:27:01.820887 INFO: [APUAPC] D15_APC_1: 0xffffffff
10040 12:27:01.824482 INFO: [APUAPC] D15_APC_2: 0x3fffff
10041 12:27:01.827565 INFO: [APUAPC] D15_APC_3: 0x0
10042 12:27:01.827727 INFO: [APUAPC] APC_CON: 0x4
10043 12:27:01.831045 INFO: [NOCDAPC] D0_APC_0: 0x0
10044 12:27:01.834195 INFO: [NOCDAPC] D0_APC_1: 0x0
10045 12:27:01.837783 INFO: [NOCDAPC] D1_APC_0: 0x0
10046 12:27:01.840654 INFO: [NOCDAPC] D1_APC_1: 0xfff
10047 12:27:01.844536 INFO: [NOCDAPC] D2_APC_0: 0x0
10048 12:27:01.847750 INFO: [NOCDAPC] D2_APC_1: 0xfff
10049 12:27:01.851038 INFO: [NOCDAPC] D3_APC_0: 0x0
10050 12:27:01.854114 INFO: [NOCDAPC] D3_APC_1: 0xfff
10051 12:27:01.857561 INFO: [NOCDAPC] D4_APC_0: 0x0
10052 12:27:01.860695 INFO: [NOCDAPC] D4_APC_1: 0xfff
10053 12:27:01.860798 INFO: [NOCDAPC] D5_APC_0: 0x0
10054 12:27:01.863897 INFO: [NOCDAPC] D5_APC_1: 0xfff
10055 12:27:01.867043 INFO: [NOCDAPC] D6_APC_0: 0x0
10056 12:27:01.870612 INFO: [NOCDAPC] D6_APC_1: 0xfff
10057 12:27:01.873583 INFO: [NOCDAPC] D7_APC_0: 0x0
10058 12:27:01.877336 INFO: [NOCDAPC] D7_APC_1: 0xfff
10059 12:27:01.880337 INFO: [NOCDAPC] D8_APC_0: 0x0
10060 12:27:01.883553 INFO: [NOCDAPC] D8_APC_1: 0xfff
10061 12:27:01.886775 INFO: [NOCDAPC] D9_APC_0: 0x0
10062 12:27:01.890596 INFO: [NOCDAPC] D9_APC_1: 0xfff
10063 12:27:01.893698 INFO: [NOCDAPC] D10_APC_0: 0x0
10064 12:27:01.896684 INFO: [NOCDAPC] D10_APC_1: 0xfff
10065 12:27:01.896807 INFO: [NOCDAPC] D11_APC_0: 0x0
10066 12:27:01.900584 INFO: [NOCDAPC] D11_APC_1: 0xfff
10067 12:27:01.903576 INFO: [NOCDAPC] D12_APC_0: 0x0
10068 12:27:01.907165 INFO: [NOCDAPC] D12_APC_1: 0xfff
10069 12:27:01.910328 INFO: [NOCDAPC] D13_APC_0: 0x0
10070 12:27:01.913406 INFO: [NOCDAPC] D13_APC_1: 0xfff
10071 12:27:01.917123 INFO: [NOCDAPC] D14_APC_0: 0x0
10072 12:27:01.920233 INFO: [NOCDAPC] D14_APC_1: 0xfff
10073 12:27:01.923283 INFO: [NOCDAPC] D15_APC_0: 0x0
10074 12:27:01.926909 INFO: [NOCDAPC] D15_APC_1: 0xfff
10075 12:27:01.930033 INFO: [NOCDAPC] APC_CON: 0x4
10076 12:27:01.933678 INFO: [APUAPC] set_apusys_apc done
10077 12:27:01.936564 INFO: [DEVAPC] devapc_init done
10078 12:27:01.940286 INFO: GICv3 without legacy support detected.
10079 12:27:01.943316 INFO: ARM GICv3 driver initialized in EL3
10080 12:27:01.946655 INFO: Maximum SPI INTID supported: 639
10081 12:27:01.953112 INFO: BL31: Initializing runtime services
10082 12:27:01.956791 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10083 12:27:01.960034 INFO: SPM: enable CPC mode
10084 12:27:01.966707 INFO: mcdi ready for mcusys-off-idle and system suspend
10085 12:27:01.969883 INFO: BL31: Preparing for EL3 exit to normal world
10086 12:27:01.973165 INFO: Entry point address = 0x80000000
10087 12:27:01.976206 INFO: SPSR = 0x8
10088 12:27:01.981747
10089 12:27:01.982172
10090 12:27:01.982582
10091 12:27:01.985007 Starting depthcharge on Spherion...
10092 12:27:01.985431
10093 12:27:01.985854 Wipe memory regions:
10094 12:27:01.986215
10095 12:27:01.988877 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10096 12:27:01.989378 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10097 12:27:01.989781 Setting prompt string to ['asurada:']
10098 12:27:01.991179 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10099 12:27:01.991864 [0x00000040000000, 0x00000054600000)
10100 12:27:02.110885
10101 12:27:02.111373 [0x00000054660000, 0x00000080000000)
10102 12:27:02.370989
10103 12:27:02.371136 [0x000000821a7280, 0x000000ffe64000)
10104 12:27:03.116150
10105 12:27:03.116670 [0x00000100000000, 0x00000240000000)
10106 12:27:05.006165
10107 12:27:05.009786 Initializing XHCI USB controller at 0x11200000.
10108 12:27:06.047973
10109 12:27:06.050802 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10110 12:27:06.051283
10111 12:27:06.051633
10112 12:27:06.051959
10113 12:27:06.052694 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10115 12:27:06.153878 asurada: tftpboot 192.168.201.1 10605797/tftp-deploy-r9s28fa7/kernel/image.itb 10605797/tftp-deploy-r9s28fa7/kernel/cmdline
10116 12:27:06.154033 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10117 12:27:06.154124 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10118 12:27:06.158388 tftpboot 192.168.201.1 10605797/tftp-deploy-r9s28fa7/kernel/image.itp-deploy-r9s28fa7/kernel/cmdline
10119 12:27:06.158474
10120 12:27:06.158539 Waiting for link
10121 12:27:06.318539
10122 12:27:06.318717 R8152: Initializing
10123 12:27:06.318819
10124 12:27:06.321685 Version 6 (ocp_data = 5c30)
10125 12:27:06.321785
10126 12:27:06.324856 R8152: Done initializing
10127 12:27:06.324960
10128 12:27:06.325055 Adding net device
10129 12:27:08.227233
10130 12:27:08.227805 done.
10131 12:27:08.228195
10132 12:27:08.228548 MAC: 00:24:32:30:78:ff
10133 12:27:08.228885
10134 12:27:08.230354 Sending DHCP discover... done.
10135 12:27:08.230740
10136 12:27:08.233615 Waiting for reply... done.
10137 12:27:08.234091
10138 12:27:08.236892 Sending DHCP request... done.
10139 12:27:08.237363
10140 12:27:11.122733 Waiting for reply... done.
10141 12:27:11.123130
10142 12:27:11.123336 My ip is 192.168.201.21
10143 12:27:11.123520
10144 12:27:11.125883 The DHCP server ip is 192.168.201.1
10145 12:27:11.126074
10146 12:27:11.132560 TFTP server IP predefined by user: 192.168.201.1
10147 12:27:11.132736
10148 12:27:11.138712 Bootfile predefined by user: 10605797/tftp-deploy-r9s28fa7/kernel/image.itb
10149 12:27:11.138867
10150 12:27:11.142490 Sending tftp read request... done.
10151 12:27:11.142628
10152 12:27:11.146232 Waiting for the transfer...
10153 12:27:11.146353
10154 12:27:11.773019 00000000 ################################################################
10155 12:27:11.773594
10156 12:27:12.440882 00080000 ################################################################
10157 12:27:12.441494
10158 12:27:13.025070 00100000 ################################################################
10159 12:27:13.025226
10160 12:27:13.618658 00180000 ################################################################
10161 12:27:13.618812
10162 12:27:14.185126 00200000 ################################################################
10163 12:27:14.185275
10164 12:27:14.821143 00280000 ################################################################
10165 12:27:14.821866
10166 12:27:15.506442 00300000 ################################################################
10167 12:27:15.507040
10168 12:27:16.099682 00380000 ################################################################
10169 12:27:16.099890
10170 12:27:16.676877 00400000 ################################################################
10171 12:27:16.677016
10172 12:27:17.261398 00480000 ################################################################
10173 12:27:17.261541
10174 12:27:17.869337 00500000 ################################################################
10175 12:27:17.869471
10176 12:27:18.439821 00580000 ################################################################
10177 12:27:18.439959
10178 12:27:19.047748 00600000 ################################################################
10179 12:27:19.047889
10180 12:27:19.612075 00680000 ################################################################
10181 12:27:19.612238
10182 12:27:20.181723 00700000 ################################################################
10183 12:27:20.181870
10184 12:27:20.742389 00780000 ################################################################
10185 12:27:20.742543
10186 12:27:21.281723 00800000 ################################################################
10187 12:27:21.281874
10188 12:27:21.934889 00880000 ################################################################
10189 12:27:21.935046
10190 12:27:22.466785 00900000 ################################################################
10191 12:27:22.466944
10192 12:27:22.996282 00980000 ################################################################
10193 12:27:22.996522
10194 12:27:23.523501 00a00000 ################################################################
10195 12:27:23.523648
10196 12:27:24.056833 00a80000 ################################################################
10197 12:27:24.056985
10198 12:27:24.592492 00b00000 ################################################################
10199 12:27:24.592677
10200 12:27:25.127074 00b80000 ################################################################
10201 12:27:25.127234
10202 12:27:25.661426 00c00000 ################################################################
10203 12:27:25.661621
10204 12:27:26.203882 00c80000 ################################################################
10205 12:27:26.204033
10206 12:27:26.734282 00d00000 ################################################################
10207 12:27:26.734464
10208 12:27:27.271857 00d80000 ################################################################
10209 12:27:27.272012
10210 12:27:27.788819 00e00000 ################################################################
10211 12:27:27.789022
10212 12:27:28.329742 00e80000 ################################################################
10213 12:27:28.329918
10214 12:27:28.846078 00f00000 ################################################################
10215 12:27:28.846227
10216 12:27:29.365970 00f80000 ################################################################
10217 12:27:29.366120
10218 12:27:29.886260 01000000 ################################################################
10219 12:27:29.886441
10220 12:27:30.412562 01080000 ################################################################
10221 12:27:30.412730
10222 12:27:30.957747 01100000 ################################################################
10223 12:27:30.957929
10224 12:27:31.491358 01180000 ################################################################
10225 12:27:31.491558
10226 12:27:32.021452 01200000 ################################################################
10227 12:27:32.021604
10228 12:27:32.550617 01280000 ################################################################
10229 12:27:32.550781
10230 12:27:33.091352 01300000 ################################################################
10231 12:27:33.091503
10232 12:27:33.635011 01380000 ################################################################
10233 12:27:33.635190
10234 12:27:34.242746 01400000 ################################################################
10235 12:27:34.242932
10236 12:27:34.772254 01480000 ################################################################
10237 12:27:34.772406
10238 12:27:35.303065 01500000 ################################################################
10239 12:27:35.303245
10240 12:27:35.837828 01580000 ################################################################
10241 12:27:35.837988
10242 12:27:36.407702 01600000 ################################################################
10243 12:27:36.407897
10244 12:27:36.933807 01680000 ################################################################
10245 12:27:36.933974
10246 12:27:37.479831 01700000 ################################################################
10247 12:27:37.480014
10248 12:27:38.006954 01780000 ################################################################
10249 12:27:38.007107
10250 12:27:38.536627 01800000 ################################################################
10251 12:27:38.536823
10252 12:27:39.083053 01880000 ################################################################
10253 12:27:39.083240
10254 12:27:39.629454 01900000 ################################################################
10255 12:27:39.629632
10256 12:27:40.148623 01980000 ################################################################
10257 12:27:40.148805
10258 12:27:40.669878 01a00000 ################################################################ done.
10259 12:27:40.670065
10260 12:27:40.672900 The bootfile was 27779158 bytes long.
10261 12:27:40.673021
10262 12:27:40.676358 Sending tftp read request... done.
10263 12:27:40.676471
10264 12:27:40.676595 Waiting for the transfer...
10265 12:27:40.676699
10266 12:27:40.679535 00000000 # done.
10267 12:27:40.679647
10268 12:27:40.685880 Command line loaded dynamically from TFTP file: 10605797/tftp-deploy-r9s28fa7/kernel/cmdline
10269 12:27:40.685988
10270 12:27:40.705595 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10271 12:27:40.705722
10272 12:27:40.708769 Loading FIT.
10273 12:27:40.708879
10274 12:27:40.712423 Image ramdisk-1 has 17643449 bytes.
10275 12:27:40.712534
10276 12:27:40.712638 Image fdt-1 has 46924 bytes.
10277 12:27:40.715539
10278 12:27:40.715647 Image kernel-1 has 10086749 bytes.
10279 12:27:40.715747
10280 12:27:40.725411 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10281 12:27:40.725530
10282 12:27:40.742230 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10283 12:27:40.745226
10284 12:27:40.749020 Choosing best match conf-1 for compat google,spherion-rev2.
10285 12:27:40.753043
10286 12:27:40.757065 Connected to device vid:did:rid of 1ae0:0028:00
10287 12:27:40.764586
10288 12:27:40.767921 tpm_get_response: command 0x17b, return code 0x0
10289 12:27:40.768031
10290 12:27:40.770740 ec_init: CrosEC protocol v3 supported (256, 248)
10291 12:27:40.774885
10292 12:27:40.778010 tpm_cleanup: add release locality here.
10293 12:27:40.778130
10294 12:27:40.778228 Shutting down all USB controllers.
10295 12:27:40.781515
10296 12:27:40.781621 Removing current net device
10297 12:27:40.781717
10298 12:27:40.788143 Exiting depthcharge with code 4 at timestamp: 68132249
10299 12:27:40.788227
10300 12:27:40.791646 LZMA decompressing kernel-1 to 0x821a6718
10301 12:27:40.791724
10302 12:27:40.794844 LZMA decompressing kernel-1 to 0x40000000
10303 12:27:42.061668
10304 12:27:42.061851 jumping to kernel
10305 12:27:42.062541 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10306 12:27:42.062691 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10307 12:27:42.062801 Setting prompt string to ['Linux version [0-9]']
10308 12:27:42.062896 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10309 12:27:42.062979 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10310 12:27:42.143768
10311 12:27:42.146812 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10312 12:27:42.150143 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10313 12:27:42.150233 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10314 12:27:42.150319 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10315 12:27:42.150394 Using line separator: #'\n'#
10316 12:27:42.150456 No login prompt set.
10317 12:27:42.150520 Parsing kernel messages
10318 12:27:42.150577 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10319 12:27:42.150687 [login-action] Waiting for messages, (timeout 00:03:45)
10320 12:27:42.170088 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10321 12:27:42.173072 [ 0.000000] random: crng init done
10322 12:27:42.176813 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10323 12:27:42.180052 [ 0.000000] efi: UEFI not found.
10324 12:27:42.190034 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10325 12:27:42.196470 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10326 12:27:42.206377 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10327 12:27:42.216302 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10328 12:27:42.222629 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10329 12:27:42.226326 [ 0.000000] printk: bootconsole [mtk8250] enabled
10330 12:27:42.234956 [ 0.000000] NUMA: No NUMA configuration found
10331 12:27:42.241774 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10332 12:27:42.247974 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10333 12:27:42.248093 [ 0.000000] Zone ranges:
10334 12:27:42.254987 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10335 12:27:42.257677 [ 0.000000] DMA32 empty
10336 12:27:42.264373 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10337 12:27:42.267821 [ 0.000000] Movable zone start for each node
10338 12:27:42.271354 [ 0.000000] Early memory node ranges
10339 12:27:42.277855 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10340 12:27:42.284062 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10341 12:27:42.290602 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10342 12:27:42.297411 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10343 12:27:42.303960 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10344 12:27:42.310799 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10345 12:27:42.367331 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10346 12:27:42.373866 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10347 12:27:42.379986 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10348 12:27:42.383492 [ 0.000000] psci: probing for conduit method from DT.
10349 12:27:42.389992 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10350 12:27:42.393344 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10351 12:27:42.400163 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10352 12:27:42.403295 [ 0.000000] psci: SMC Calling Convention v1.2
10353 12:27:42.410071 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10354 12:27:42.413061 [ 0.000000] Detected VIPT I-cache on CPU0
10355 12:27:42.419767 [ 0.000000] CPU features: detected: GIC system register CPU interface
10356 12:27:42.426692 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10357 12:27:42.432967 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10358 12:27:42.439893 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10359 12:27:42.449610 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10360 12:27:42.455880 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10361 12:27:42.459629 [ 0.000000] alternatives: applying boot alternatives
10362 12:27:42.465879 [ 0.000000] Fallback order for Node 0: 0
10363 12:27:42.472606 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10364 12:27:42.475536 [ 0.000000] Policy zone: Normal
10365 12:27:42.495788 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10366 12:27:42.505411 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10367 12:27:42.517559 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10368 12:27:42.527804 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10369 12:27:42.534040 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10370 12:27:42.537835 <6>[ 0.000000] software IO TLB: area num 8.
10371 12:27:42.594410 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10372 12:27:42.743835 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10373 12:27:42.749977 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10374 12:27:42.757172 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10375 12:27:42.760304 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10376 12:27:42.766611 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10377 12:27:42.773431 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10378 12:27:42.776454 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10379 12:27:42.786346 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10380 12:27:42.793239 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10381 12:27:42.799770 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10382 12:27:42.806113 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10383 12:27:42.809500 <6>[ 0.000000] GICv3: 608 SPIs implemented
10384 12:27:42.812488 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10385 12:27:42.819516 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10386 12:27:42.822528 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10387 12:27:42.829140 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10388 12:27:42.842680 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10389 12:27:42.856000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10390 12:27:42.862136 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10391 12:27:42.870315 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10392 12:27:42.883627 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10393 12:27:42.889738 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10394 12:27:42.896570 <6>[ 0.009177] Console: colour dummy device 80x25
10395 12:27:42.906725 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10396 12:27:42.913234 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10397 12:27:42.916539 <6>[ 0.029221] LSM: Security Framework initializing
10398 12:27:42.922813 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 12:27:42.932801 <6>[ 0.041989] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 12:27:42.942496 <6>[ 0.051420] cblist_init_generic: Setting adjustable number of callback queues.
10401 12:27:42.949420 <6>[ 0.058920] cblist_init_generic: Setting shift to 3 and lim to 1.
10402 12:27:42.952609 <6>[ 0.065297] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 12:27:42.959258 <6>[ 0.071703] rcu: Hierarchical SRCU implementation.
10404 12:27:42.965976 <6>[ 0.076716] rcu: Max phase no-delay instances is 1000.
10405 12:27:42.972327 <6>[ 0.083734] EFI services will not be available.
10406 12:27:42.975442 <6>[ 0.088735] smp: Bringing up secondary CPUs ...
10407 12:27:42.983443 <6>[ 0.093787] Detected VIPT I-cache on CPU1
10408 12:27:42.990518 <6>[ 0.093859] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10409 12:27:42.996690 <6>[ 0.093891] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10410 12:27:42.999839 <6>[ 0.094231] Detected VIPT I-cache on CPU2
10411 12:27:43.010282 <6>[ 0.094279] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10412 12:27:43.016687 <6>[ 0.094294] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10413 12:27:43.019797 <6>[ 0.094552] Detected VIPT I-cache on CPU3
10414 12:27:43.026722 <6>[ 0.094597] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10415 12:27:43.033020 <6>[ 0.094611] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10416 12:27:43.039444 <6>[ 0.094914] CPU features: detected: Spectre-v4
10417 12:27:43.042857 <6>[ 0.094921] CPU features: detected: Spectre-BHB
10418 12:27:43.046354 <6>[ 0.094927] Detected PIPT I-cache on CPU4
10419 12:27:43.052950 <6>[ 0.094985] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10420 12:27:43.062821 <6>[ 0.095001] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10421 12:27:43.065847 <6>[ 0.095291] Detected PIPT I-cache on CPU5
10422 12:27:43.072495 <6>[ 0.095355] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10423 12:27:43.078813 <6>[ 0.095371] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10424 12:27:43.082606 <6>[ 0.095654] Detected PIPT I-cache on CPU6
10425 12:27:43.092058 <6>[ 0.095720] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10426 12:27:43.098887 <6>[ 0.095736] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10427 12:27:43.102090 <6>[ 0.096034] Detected PIPT I-cache on CPU7
10428 12:27:43.108822 <6>[ 0.096099] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10429 12:27:43.115510 <6>[ 0.096115] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10430 12:27:43.118655 <6>[ 0.096162] smp: Brought up 1 node, 8 CPUs
10431 12:27:43.125515 <6>[ 0.237450] SMP: Total of 8 processors activated.
10432 12:27:43.131940 <6>[ 0.242371] CPU features: detected: 32-bit EL0 Support
10433 12:27:43.138551 <6>[ 0.247735] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10434 12:27:43.145166 <6>[ 0.256535] CPU features: detected: Common not Private translations
10435 12:27:43.151773 <6>[ 0.263011] CPU features: detected: CRC32 instructions
10436 12:27:43.158269 <6>[ 0.268362] CPU features: detected: RCpc load-acquire (LDAPR)
10437 12:27:43.161411 <6>[ 0.274359] CPU features: detected: LSE atomic instructions
10438 12:27:43.168323 <6>[ 0.280140] CPU features: detected: Privileged Access Never
10439 12:27:43.174757 <6>[ 0.285956] CPU features: detected: RAS Extension Support
10440 12:27:43.181494 <6>[ 0.291565] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10441 12:27:43.184681 <6>[ 0.298788] CPU: All CPU(s) started at EL2
10442 12:27:43.190929 <6>[ 0.303131] alternatives: applying system-wide alternatives
10443 12:27:43.201286 <6>[ 0.313835] devtmpfs: initialized
10444 12:27:43.216771 <6>[ 0.322692] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10445 12:27:43.223942 <6>[ 0.332654] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10446 12:27:43.230000 <6>[ 0.340694] pinctrl core: initialized pinctrl subsystem
10447 12:27:43.233040 <6>[ 0.347365] DMI not present or invalid.
10448 12:27:43.239698 <6>[ 0.351773] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10449 12:27:43.249689 <6>[ 0.358644] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10450 12:27:43.256265 <6>[ 0.366222] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10451 12:27:43.266426 <6>[ 0.374437] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10452 12:27:43.269473 <6>[ 0.382679] audit: initializing netlink subsys (disabled)
10453 12:27:43.279415 <5>[ 0.388372] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10454 12:27:43.285786 <6>[ 0.389080] thermal_sys: Registered thermal governor 'step_wise'
10455 12:27:43.292795 <6>[ 0.396337] thermal_sys: Registered thermal governor 'power_allocator'
10456 12:27:43.295903 <6>[ 0.402589] cpuidle: using governor menu
10457 12:27:43.302291 <6>[ 0.413548] NET: Registered PF_QIPCRTR protocol family
10458 12:27:43.309197 <6>[ 0.419036] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10459 12:27:43.315975 <6>[ 0.426138] ASID allocator initialised with 32768 entries
10460 12:27:43.319148 <6>[ 0.432717] Serial: AMBA PL011 UART driver
10461 12:27:43.329166 <4>[ 0.441381] Trying to register duplicate clock ID: 134
10462 12:27:43.382804 <6>[ 0.498617] KASLR enabled
10463 12:27:43.396963 <6>[ 0.506310] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10464 12:27:43.403808 <6>[ 0.513322] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10465 12:27:43.410488 <6>[ 0.519813] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10466 12:27:43.417046 <6>[ 0.526816] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10467 12:27:43.423257 <6>[ 0.533302] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10468 12:27:43.429979 <6>[ 0.540307] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10469 12:27:43.436325 <6>[ 0.546795] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10470 12:27:43.443302 <6>[ 0.553796] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10471 12:27:43.446577 <6>[ 0.561270] ACPI: Interpreter disabled.
10472 12:27:43.455192 <6>[ 0.567692] iommu: Default domain type: Translated
10473 12:27:43.461658 <6>[ 0.572804] iommu: DMA domain TLB invalidation policy: strict mode
10474 12:27:43.465249 <5>[ 0.579469] SCSI subsystem initialized
10475 12:27:43.471896 <6>[ 0.583705] usbcore: registered new interface driver usbfs
10476 12:27:43.478173 <6>[ 0.589437] usbcore: registered new interface driver hub
10477 12:27:43.481270 <6>[ 0.594991] usbcore: registered new device driver usb
10478 12:27:43.488567 <6>[ 0.601092] pps_core: LinuxPPS API ver. 1 registered
10479 12:27:43.498526 <6>[ 0.606287] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10480 12:27:43.501538 <6>[ 0.615627] PTP clock support registered
10481 12:27:43.505312 <6>[ 0.619868] EDAC MC: Ver: 3.0.0
10482 12:27:43.512318 <6>[ 0.625055] FPGA manager framework
10483 12:27:43.519378 <6>[ 0.628733] Advanced Linux Sound Architecture Driver Initialized.
10484 12:27:43.522433 <6>[ 0.635502] vgaarb: loaded
10485 12:27:43.528975 <6>[ 0.638673] clocksource: Switched to clocksource arch_sys_counter
10486 12:27:43.532540 <5>[ 0.645116] VFS: Disk quotas dquot_6.6.0
10487 12:27:43.538849 <6>[ 0.649305] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10488 12:27:43.542023 <6>[ 0.656494] pnp: PnP ACPI: disabled
10489 12:27:43.550800 <6>[ 0.663210] NET: Registered PF_INET protocol family
10490 12:27:43.560195 <6>[ 0.668799] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10491 12:27:43.572099 <6>[ 0.681106] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10492 12:27:43.581711 <6>[ 0.689917] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10493 12:27:43.588377 <6>[ 0.697889] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10494 12:27:43.598177 <6>[ 0.706589] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10495 12:27:43.604449 <6>[ 0.716323] TCP: Hash tables configured (established 65536 bind 65536)
10496 12:27:43.611194 <6>[ 0.723188] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10497 12:27:43.620815 <6>[ 0.730389] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 12:27:43.627520 <6>[ 0.738090] NET: Registered PF_UNIX/PF_LOCAL protocol family
10499 12:27:43.634055 <6>[ 0.744190] RPC: Registered named UNIX socket transport module.
10500 12:27:43.637630 <6>[ 0.750339] RPC: Registered udp transport module.
10501 12:27:43.643970 <6>[ 0.755270] RPC: Registered tcp transport module.
10502 12:27:43.650439 <6>[ 0.760202] RPC: Registered tcp NFSv4.1 backchannel transport module.
10503 12:27:43.654235 <6>[ 0.766868] PCI: CLS 0 bytes, default 64
10504 12:27:43.657264 <6>[ 0.771243] Unpacking initramfs...
10505 12:27:43.667224 <6>[ 0.775066] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10506 12:27:43.673921 <6>[ 0.783736] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10507 12:27:43.680322 <6>[ 0.792591] kvm [1]: IPA Size Limit: 40 bits
10508 12:27:43.683792 <6>[ 0.797119] kvm [1]: GICv3: no GICV resource entry
10509 12:27:43.690372 <6>[ 0.802138] kvm [1]: disabling GICv2 emulation
10510 12:27:43.697062 <6>[ 0.806821] kvm [1]: GIC system register CPU interface enabled
10511 12:27:43.700094 <6>[ 0.812988] kvm [1]: vgic interrupt IRQ18
10512 12:27:43.703670 <6>[ 0.817347] kvm [1]: VHE mode initialized successfully
10513 12:27:43.711085 <5>[ 0.823778] Initialise system trusted keyrings
10514 12:27:43.717942 <6>[ 0.828593] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10515 12:27:43.725779 <6>[ 0.838583] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10516 12:27:43.732543 <5>[ 0.845001] NFS: Registering the id_resolver key type
10517 12:27:43.736223 <5>[ 0.850304] Key type id_resolver registered
10518 12:27:43.742270 <5>[ 0.854718] Key type id_legacy registered
10519 12:27:43.749185 <6>[ 0.859000] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10520 12:27:43.755529 <6>[ 0.865920] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10521 12:27:43.762323 <6>[ 0.873688] 9p: Installing v9fs 9p2000 file system support
10522 12:27:43.798438 <5>[ 0.910999] Key type asymmetric registered
10523 12:27:43.801696 <5>[ 0.915332] Asymmetric key parser 'x509' registered
10524 12:27:43.811438 <6>[ 0.920478] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10525 12:27:43.815176 <6>[ 0.928093] io scheduler mq-deadline registered
10526 12:27:43.818254 <6>[ 0.932854] io scheduler kyber registered
10527 12:27:43.837229 <6>[ 0.949631] EINJ: ACPI disabled.
10528 12:27:43.869194 <4>[ 0.974930] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 12:27:43.879177 <4>[ 0.985564] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 12:27:43.893571 <6>[ 1.005814] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10531 12:27:43.901181 <6>[ 1.013738] printk: console [ttyS0] disabled
10532 12:27:43.928974 <6>[ 1.038388] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10533 12:27:43.935692 <6>[ 1.047873] printk: console [ttyS0] enabled
10534 12:27:43.939377 <6>[ 1.047873] printk: console [ttyS0] enabled
10535 12:27:43.945467 <6>[ 1.056790] printk: bootconsole [mtk8250] disabled
10536 12:27:43.949036 <6>[ 1.056790] printk: bootconsole [mtk8250] disabled
10537 12:27:43.955411 <6>[ 1.067810] SuperH (H)SCI(F) driver initialized
10538 12:27:43.958504 <6>[ 1.073076] msm_serial: driver initialized
10539 12:27:43.972420 <6>[ 1.081917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10540 12:27:43.982803 <6>[ 1.090463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10541 12:27:43.988988 <6>[ 1.099003] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10542 12:27:43.999118 <6>[ 1.107629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10543 12:27:44.009220 <6>[ 1.116335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10544 12:27:44.015315 <6>[ 1.125048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10545 12:27:44.025427 <6>[ 1.133588] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10546 12:27:44.031670 <6>[ 1.142408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10547 12:27:44.042057 <6>[ 1.150950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10548 12:27:44.053838 <6>[ 1.166273] loop: module loaded
10549 12:27:44.060073 <6>[ 1.172139] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10550 12:27:44.083026 <4>[ 1.195338] mtk-pmic-keys: Failed to locate of_node [id: -1]
10551 12:27:44.089053 <6>[ 1.201981] megasas: 07.719.03.00-rc1
10552 12:27:44.099092 <6>[ 1.211582] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10553 12:27:44.105395 <6>[ 1.218055] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10554 12:27:44.121925 <6>[ 1.234051] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10555 12:27:44.181009 <6>[ 1.287355] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10556 12:27:44.391117 <6>[ 1.503826] Freeing initrd memory: 17224K
10557 12:27:44.401457 <6>[ 1.514145] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10558 12:27:44.412542 <6>[ 1.524882] tun: Universal TUN/TAP device driver, 1.6
10559 12:27:44.415582 <6>[ 1.530931] thunder_xcv, ver 1.0
10560 12:27:44.419294 <6>[ 1.534425] thunder_bgx, ver 1.0
10561 12:27:44.422456 <6>[ 1.537925] nicpf, ver 1.0
10562 12:27:44.432771 <6>[ 1.541923] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10563 12:27:44.435742 <6>[ 1.549399] hns3: Copyright (c) 2017 Huawei Corporation.
10564 12:27:44.442610 <6>[ 1.554987] hclge is initializing
10565 12:27:44.445547 <6>[ 1.558558] e1000: Intel(R) PRO/1000 Network Driver
10566 12:27:44.452559 <6>[ 1.563688] e1000: Copyright (c) 1999-2006 Intel Corporation.
10567 12:27:44.455452 <6>[ 1.569701] e1000e: Intel(R) PRO/1000 Network Driver
10568 12:27:44.462290 <6>[ 1.574916] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10569 12:27:44.469190 <6>[ 1.581101] igb: Intel(R) Gigabit Ethernet Network Driver
10570 12:27:44.475815 <6>[ 1.586750] igb: Copyright (c) 2007-2014 Intel Corporation.
10571 12:27:44.482097 <6>[ 1.592586] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10572 12:27:44.488942 <6>[ 1.599104] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10573 12:27:44.492052 <6>[ 1.605562] sky2: driver version 1.30
10574 12:27:44.498902 <6>[ 1.610554] VFIO - User Level meta-driver version: 0.3
10575 12:27:44.506381 <6>[ 1.618746] usbcore: registered new interface driver usb-storage
10576 12:27:44.512834 <6>[ 1.625193] usbcore: registered new device driver onboard-usb-hub
10577 12:27:44.521397 <6>[ 1.634258] mt6397-rtc mt6359-rtc: registered as rtc0
10578 12:27:44.531409 <6>[ 1.639725] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:27:50 UTC (1686054470)
10579 12:27:44.535237 <6>[ 1.649276] i2c_dev: i2c /dev entries driver
10580 12:27:44.551167 <6>[ 1.660858] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10581 12:27:44.558510 <6>[ 1.671025] sdhci: Secure Digital Host Controller Interface driver
10582 12:27:44.565310 <6>[ 1.677463] sdhci: Copyright(c) Pierre Ossman
10583 12:27:44.571519 <6>[ 1.682855] Synopsys Designware Multimedia Card Interface Driver
10584 12:27:44.574704 <6>[ 1.689454] mmc0: CQHCI version 5.10
10585 12:27:44.581121 <6>[ 1.689999] sdhci-pltfm: SDHCI platform and OF driver helper
10586 12:27:44.588530 <6>[ 1.701296] ledtrig-cpu: registered to indicate activity on CPUs
10587 12:27:44.599279 <6>[ 1.708620] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 12:27:44.602988 <6>[ 1.716023] usbcore: registered new interface driver usbhid
10589 12:27:44.609151 <6>[ 1.721855] usbhid: USB HID core driver
10590 12:27:44.616003 <6>[ 1.726094] spi_master spi0: will run message pump with realtime priority
10591 12:27:44.664031 <6>[ 1.770186] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10592 12:27:44.684106 <6>[ 1.786052] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10593 12:27:44.686987 <6>[ 1.799629] mmc0: Command Queue Engine enabled
10594 12:27:44.694369 <6>[ 1.801072] cros-ec-spi spi0.0: Chrome EC device registered
10595 12:27:44.697477 <6>[ 1.804380] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 12:27:44.705044 <6>[ 1.817568] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 12:27:44.718792 <6>[ 1.828186] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10598 12:27:44.725267 <6>[ 1.830096] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10599 12:27:44.731874 <6>[ 1.839638] NET: Registered PF_PACKET protocol family
10600 12:27:44.735649 <6>[ 1.844855] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 12:27:44.742477 <6>[ 1.848853] 9pnet: Installing 9P2000 support
10602 12:27:44.745599 <6>[ 1.854611] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10603 12:27:44.751813 <5>[ 1.858522] Key type dns_resolver registered
10604 12:27:44.758508 <6>[ 1.864339] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10605 12:27:44.762078 <6>[ 1.868804] registered taskstats version 1
10606 12:27:44.765417 <5>[ 1.879119] Loading compiled-in X.509 certificates
10607 12:27:44.800380 <4>[ 1.906589] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 12:27:44.810435 <4>[ 1.917281] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 12:27:44.820851 <3>[ 1.930042] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10610 12:27:44.833046 <6>[ 1.945492] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10611 12:27:44.839290 <6>[ 1.952317] xhci-mtk 11200000.usb: xHCI Host Controller
10612 12:27:44.849400 <6>[ 1.957821] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10613 12:27:44.856332 <6>[ 1.965678] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10614 12:27:44.862490 <6>[ 1.975121] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10615 12:27:44.869635 <6>[ 1.981313] xhci-mtk 11200000.usb: xHCI Host Controller
10616 12:27:44.875982 <6>[ 1.986811] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10617 12:27:44.882732 <6>[ 1.994468] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10618 12:27:44.890021 <6>[ 2.002354] hub 1-0:1.0: USB hub found
10619 12:27:44.892876 <6>[ 2.006387] hub 1-0:1.0: 1 port detected
10620 12:27:44.902838 <6>[ 2.010751] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10621 12:27:44.906051 <6>[ 2.019575] hub 2-0:1.0: USB hub found
10622 12:27:44.909634 <6>[ 2.023612] hub 2-0:1.0: 1 port detected
10623 12:27:44.918265 <6>[ 2.030634] mtk-msdc 11f70000.mmc: Got CD GPIO
10624 12:27:44.936930 <6>[ 2.046003] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10625 12:27:44.943460 <6>[ 2.054049] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10626 12:27:44.953435 <4>[ 2.062031] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10627 12:27:44.963059 <6>[ 2.071699] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10628 12:27:44.970044 <6>[ 2.079779] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10629 12:27:44.976545 <6>[ 2.087816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10630 12:27:44.986518 <6>[ 2.095734] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10631 12:27:44.993268 <6>[ 2.103554] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10632 12:27:45.003131 <6>[ 2.111376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10633 12:27:45.013230 <6>[ 2.122062] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10634 12:27:45.019844 <6>[ 2.130430] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10635 12:27:45.029554 <6>[ 2.138786] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10636 12:27:45.036530 <6>[ 2.147131] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10637 12:27:45.046279 <6>[ 2.155474] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10638 12:27:45.052613 <6>[ 2.163818] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10639 12:27:45.062728 <6>[ 2.172161] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10640 12:27:45.072802 <6>[ 2.180504] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10641 12:27:45.079061 <6>[ 2.188848] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10642 12:27:45.089529 <6>[ 2.197192] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10643 12:27:45.095777 <6>[ 2.205535] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10644 12:27:45.105619 <6>[ 2.213879] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10645 12:27:45.112998 <6>[ 2.222222] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10646 12:27:45.122183 <6>[ 2.230565] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10647 12:27:45.129270 <6>[ 2.238915] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10648 12:27:45.135332 <6>[ 2.247812] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10649 12:27:45.142877 <6>[ 2.255271] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10650 12:27:45.149371 <6>[ 2.262312] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10651 12:27:45.160193 <6>[ 2.269449] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10652 12:27:45.166498 <6>[ 2.276754] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10653 12:27:45.176029 <6>[ 2.283671] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10654 12:27:45.182813 <6>[ 2.292812] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10655 12:27:45.193187 <6>[ 2.301939] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10656 12:27:45.202888 <6>[ 2.311243] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10657 12:27:45.212591 <6>[ 2.320717] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10658 12:27:45.222296 <6>[ 2.330192] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10659 12:27:45.232271 <6>[ 2.339318] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10660 12:27:45.238741 <6>[ 2.348793] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10661 12:27:45.248711 <6>[ 2.357919] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10662 12:27:45.259176 <6>[ 2.367221] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10663 12:27:45.268523 <6>[ 2.377387] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10664 12:27:45.279660 <6>[ 2.389366] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10665 12:27:45.286322 <6>[ 2.399336] Trying to probe devices needed for running init ...
10666 12:27:45.317320 <6>[ 2.426920] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 12:27:45.470344 <6>[ 2.582974] hub 1-1:1.0: USB hub found
10668 12:27:45.473449 <6>[ 2.587327] hub 1-1:1.0: 4 ports detected
10669 12:27:45.597876 <6>[ 2.707298] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10670 12:27:45.624366 <6>[ 2.737344] hub 2-1:1.0: USB hub found
10671 12:27:45.628309 <6>[ 2.741751] hub 2-1:1.0: 3 ports detected
10672 12:27:45.793480 <6>[ 2.902989] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10673 12:27:45.926046 <6>[ 3.038954] hub 1-1.4:1.0: USB hub found
10674 12:27:45.929195 <6>[ 3.043628] hub 1-1.4:1.0: 2 ports detected
10675 12:27:46.009692 <6>[ 3.119183] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10676 12:27:46.225316 <6>[ 3.334942] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10677 12:27:46.417513 <6>[ 3.526942] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10678 12:27:57.582199 <6>[ 14.699569] ALSA device list:
10679 12:27:57.588430 <6>[ 14.702829] No soundcards found.
10680 12:27:57.600926 <6>[ 14.715219] Freeing unused kernel memory: 8384K
10681 12:27:57.604676 <6>[ 14.720150] Run /init as init process
10682 12:27:57.615307 Loading, please wait...
10683 12:27:57.634767 Starting version 247.3-7+deb11u2
10684 12:27:57.945341 <6>[ 15.056501] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10685 12:27:57.956815 <6>[ 15.071112] remoteproc remoteproc0: scp is available
10686 12:27:57.966963 <4>[ 15.076984] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10687 12:27:57.973471 <6>[ 15.087286] remoteproc remoteproc0: powering up scp
10688 12:27:57.983421 <4>[ 15.092585] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10689 12:27:57.990112 <3>[ 15.102426] remoteproc remoteproc0: request_firmware failed: -2
10690 12:27:57.996807 <6>[ 15.109789] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10691 12:27:58.006657 <3>[ 15.113798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 12:27:58.016575 <6>[ 15.117432] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10693 12:27:58.023264 <3>[ 15.125532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 12:27:58.032675 <6>[ 15.134169] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10695 12:27:58.039499 <3>[ 15.151041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 12:27:58.063435 <3>[ 15.174469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 12:27:58.070353 <3>[ 15.182632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 12:27:58.080258 <3>[ 15.191008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 12:27:58.083320 <6>[ 15.191909] mc: Linux media interface: v0.10
10700 12:27:58.093756 <4>[ 15.192506] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10701 12:27:58.099763 <4>[ 15.192661] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10702 12:27:58.106352 <3>[ 15.199165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 12:27:58.116698 <6>[ 15.220855] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10704 12:27:58.123304 <3>[ 15.226463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 12:27:58.129447 <3>[ 15.235935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 12:27:58.136416 <6>[ 15.243652] usbcore: registered new interface driver r8152
10707 12:27:58.146298 <3>[ 15.250453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 12:27:58.153099 <6>[ 15.255593] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10709 12:27:58.156227 <6>[ 15.255600] pci_bus 0000:00: root bus resource [bus 00-ff]
10710 12:27:58.166316 <6>[ 15.255608] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10711 12:27:58.176571 <6>[ 15.255613] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10712 12:27:58.179741 <6>[ 15.255645] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10713 12:27:58.189827 <6>[ 15.255663] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10714 12:27:58.193562 <6>[ 15.255742] pci 0000:00:00.0: supports D1 D2
10715 12:27:58.200361 <6>[ 15.255745] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10716 12:27:58.206403 <6>[ 15.257496] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10717 12:27:58.216185 <3>[ 15.264225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 12:27:58.226347 <4>[ 15.267750] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10719 12:27:58.229481 <4>[ 15.267750] Fallback method does not support PEC.
10720 12:27:58.236207 <6>[ 15.271214] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10721 12:27:58.243385 <3>[ 15.276811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 12:27:58.252949 <3>[ 15.276873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 12:27:58.259723 <6>[ 15.284113] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10724 12:27:58.269539 <3>[ 15.284836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10725 12:27:58.275806 <3>[ 15.293852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 12:27:58.285907 <6>[ 15.298384] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10727 12:27:58.292602 <6>[ 15.300128] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10728 12:27:58.302735 <3>[ 15.307588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 12:27:58.308767 <3>[ 15.307866] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10730 12:27:58.318574 <6>[ 15.311004] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10731 12:27:58.328838 <6>[ 15.311253] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10732 12:27:58.335020 <6>[ 15.312680] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10733 12:27:58.344988 <3>[ 15.318998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 12:27:58.348795 <6>[ 15.327430] pci 0000:01:00.0: supports D1 D2
10735 12:27:58.355165 <6>[ 15.327626] usbcore: registered new interface driver cdc_ether
10736 12:27:58.361691 <6>[ 15.329117] videodev: Linux video capture interface: v2.00
10737 12:27:58.368609 <3>[ 15.335371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 12:27:58.374987 <6>[ 15.335823] usbcore: registered new interface driver r8153_ecm
10739 12:27:58.381351 <6>[ 15.338996] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10740 12:27:58.388315 <6>[ 15.349175] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10741 12:27:58.398473 <3>[ 15.355337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 12:27:58.401711 <6>[ 15.355992] Bluetooth: Core ver 2.22
10743 12:27:58.407886 <6>[ 15.356050] NET: Registered PF_BLUETOOTH protocol family
10744 12:27:58.414927 <6>[ 15.356053] Bluetooth: HCI device and connection manager initialized
10745 12:27:58.418071 <6>[ 15.356070] Bluetooth: HCI socket layer initialized
10746 12:27:58.424720 <6>[ 15.356076] Bluetooth: L2CAP socket layer initialized
10747 12:27:58.427664 <6>[ 15.356086] Bluetooth: SCO socket layer initialized
10748 12:27:58.437857 <4>[ 15.370015] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10749 12:27:58.444515 <6>[ 15.374828] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10750 12:27:58.454037 <4>[ 15.378995] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10751 12:27:58.461010 <6>[ 15.387800] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10752 12:27:58.467660 <6>[ 15.388950] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10753 12:27:58.480548 <6>[ 15.390394] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10754 12:27:58.487377 <6>[ 15.390525] usbcore: registered new interface driver uvcvideo
10755 12:27:58.493748 <6>[ 15.406003] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10756 12:27:58.500464 <6>[ 15.412630] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10757 12:27:58.506888 <6>[ 15.421634] usbcore: registered new interface driver btusb
10758 12:27:58.517201 <4>[ 15.422044] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10759 12:27:58.523551 <3>[ 15.422059] Bluetooth: hci0: Failed to load firmware file (-2)
10760 12:27:58.529744 <3>[ 15.422063] Bluetooth: hci0: Failed to set up firmware (-2)
10761 12:27:58.540217 <4>[ 15.422071] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10762 12:27:58.546798 <6>[ 15.429510] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10763 12:27:58.552880 <6>[ 15.458894] r8152 2-1.3:1.0 eth0: v1.12.13
10764 12:27:58.559643 <6>[ 15.464171] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10765 12:27:58.566464 <6>[ 15.476431] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10766 12:27:58.572661 <6>[ 15.480515] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10767 12:27:58.579388 <6>[ 15.693274] pci 0000:00:00.0: PCI bridge to [bus 01]
10768 12:27:58.586332 <6>[ 15.698498] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10769 12:27:58.592692 <6>[ 15.706694] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10770 12:27:58.599705 <6>[ 15.713953] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10771 12:27:58.606497 <6>[ 15.720426] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10772 12:27:58.625849 <5>[ 15.736583] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10773 12:27:58.645684 <5>[ 15.756668] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10774 12:27:58.652384 <4>[ 15.763598] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10775 12:27:58.658910 <6>[ 15.772483] cfg80211: failed to load regulatory.db
10776 12:27:58.704146 <6>[ 15.815059] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10777 12:27:58.710439 <6>[ 15.822655] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10778 12:27:58.735411 <6>[ 15.849449] mt7921e 0000:01:00.0: ASIC revision: 79610010
10779 12:27:58.842637 <4>[ 15.950398] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:27:58.856765 Begin: Loading essential drivers ... done.
10781 12:27:58.859827 Begin: Running /scripts/init-premount ... done.
10782 12:27:58.866333 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10783 12:27:58.876506 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10784 12:27:58.879522 Device /sys/class/net/enx0024323078ff found
10785 12:27:58.879608 done.
10786 12:27:58.961393 <4>[ 16.069369] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 12:27:58.972377 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10788 12:27:59.081368 <4>[ 16.188776] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 12:27:59.196889 <4>[ 16.304546] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 12:27:59.312584 <4>[ 16.420508] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 12:27:59.428567 <4>[ 16.536375] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 12:27:59.544489 <4>[ 16.652412] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 12:27:59.660345 <4>[ 16.768255] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 12:27:59.776761 <4>[ 16.884273] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 12:27:59.892331 <4>[ 17.000256] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 12:27:59.995638 <6>[ 17.109766] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10797 12:28:00.001763 <3>[ 17.114129] mt7921e 0000:01:00.0: hardware init failed
10798 12:28:00.025395 IP-Config: no response after 2 secs - giving up
10799 12:28:00.063833 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10800 12:28:01.165192 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10801 12:28:01.171488 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10802 12:28:01.178183 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10803 12:28:01.184992 host : mt8192-asurada-spherion-r0-cbg-8
10804 12:28:01.191712 domain : lava-rack
10805 12:28:01.197849 rootserver: 192.168.201.1 rootpath:
10806 12:28:01.197986 filename :
10807 12:28:01.238367 done.
10808 12:28:01.245938 Begin: Running /scripts/nfs-bottom ... done.
10809 12:28:01.263992 Begin: Running /scripts/init-bottom ... done.
10810 12:28:02.392242 <6>[ 19.506861] NET: Registered PF_INET6 protocol family
10811 12:28:02.399160 <6>[ 19.513718] Segment Routing with IPv6
10812 12:28:02.402190 <6>[ 19.517740] In-situ OAM (IOAM) with IPv6
10813 12:28:02.520618 <30>[ 19.615648] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10814 12:28:02.524042 <30>[ 19.639411] systemd[1]: Detected architecture arm64.
10815 12:28:02.543776
10816 12:28:02.547459 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10817 12:28:02.547586
10818 12:28:02.562575 <30>[ 19.677069] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10819 12:28:03.112505 <30>[ 20.223911] systemd[1]: Queued start job for default target Graphical Interface.
10820 12:28:03.137589 <30>[ 20.252026] systemd[1]: Created slice system-getty.slice.
10821 12:28:03.143901 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10822 12:28:03.160890 <30>[ 20.275706] systemd[1]: Created slice system-modprobe.slice.
10823 12:28:03.167796 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10824 12:28:03.185417 <30>[ 20.299768] systemd[1]: Created slice system-serial\x2dgetty.slice.
10825 12:28:03.194978 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10826 12:28:03.208836 <30>[ 20.323370] systemd[1]: Created slice User and Session Slice.
10827 12:28:03.215418 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10828 12:28:03.236411 <30>[ 20.347503] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10829 12:28:03.245883 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10830 12:28:03.263617 <30>[ 20.375107] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10831 12:28:03.270416 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10832 12:28:03.290939 <30>[ 20.399051] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10833 12:28:03.297766 <30>[ 20.411086] systemd[1]: Reached target Local Encrypted Volumes.
10834 12:28:03.303855 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10835 12:28:03.320737 <30>[ 20.435312] systemd[1]: Reached target Paths.
10836 12:28:03.323761 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10837 12:28:03.339923 <30>[ 20.454982] systemd[1]: Reached target Remote File Systems.
10838 12:28:03.346989 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10839 12:28:03.360338 <30>[ 20.474964] systemd[1]: Reached target Slices.
10840 12:28:03.363453 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10841 12:28:03.380572 <30>[ 20.494944] systemd[1]: Reached target Swap.
10842 12:28:03.383716 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10843 12:28:03.404022 <30>[ 20.515308] systemd[1]: Listening on initctl Compatibility Named Pipe.
10844 12:28:03.410708 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10845 12:28:03.417124 <30>[ 20.530866] systemd[1]: Listening on Journal Audit Socket.
10846 12:28:03.423380 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10847 12:28:03.437456 <30>[ 20.552128] systemd[1]: Listening on Journal Socket (/dev/log).
10848 12:28:03.444293 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10849 12:28:03.460785 <30>[ 20.575753] systemd[1]: Listening on Journal Socket.
10850 12:28:03.467693 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10851 12:28:03.484661 <30>[ 20.596347] systemd[1]: Listening on Network Service Netlink Socket.
10852 12:28:03.491244 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10853 12:28:03.507286 <30>[ 20.621927] systemd[1]: Listening on udev Control Socket.
10854 12:28:03.513396 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10855 12:28:03.528311 <30>[ 20.643177] systemd[1]: Listening on udev Kernel Socket.
10856 12:28:03.535194 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10857 12:28:03.580555 <30>[ 20.695244] systemd[1]: Mounting Huge Pages File System...
10858 12:28:03.587412 Mounting [0;1;39mHuge Pages File System[0m...
10859 12:28:03.602531 <30>[ 20.717588] systemd[1]: Mounting POSIX Message Queue File System...
10860 12:28:03.609516 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10861 12:28:03.626393 <30>[ 20.741271] systemd[1]: Mounting Kernel Debug File System...
10862 12:28:03.633382 Mounting [0;1;39mKernel Debug File System[0m...
10863 12:28:03.651992 <30>[ 20.763229] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10864 12:28:03.672329 <30>[ 20.783757] systemd[1]: Starting Create list of static device nodes for the current kernel...
10865 12:28:03.678677 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10866 12:28:03.699433 <30>[ 20.813800] systemd[1]: Starting Load Kernel Module configfs...
10867 12:28:03.705648 Starting [0;1;39mLoad Kernel Module configfs[0m...
10868 12:28:03.748489 <30>[ 20.863533] systemd[1]: Starting Load Kernel Module drm...
10869 12:28:03.755132 Starting [0;1;39mLoad Kernel Module drm[0m...
10870 12:28:03.771364 <30>[ 20.885814] systemd[1]: Starting Load Kernel Module fuse...
10871 12:28:03.777465 Starting [0;1;39mLoad Kernel Module fuse[0m...
10872 12:28:03.809678 <6>[ 20.924647] fuse: init (API version 7.37)
10873 12:28:03.819714 <30>[ 20.925787] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10874 12:28:03.844935 <30>[ 20.959578] systemd[1]: Starting Journal Service...
10875 12:28:03.847908 Starting [0;1;39mJournal Service[0m...
10876 12:28:03.872425 <30>[ 20.987552] systemd[1]: Starting Load Kernel Modules...
10877 12:28:03.879230 Starting [0;1;39mLoad Kernel Modules[0m...
10878 12:28:03.897700 <30>[ 21.009552] systemd[1]: Starting Remount Root and Kernel File Systems...
10879 12:28:03.904711 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10880 12:28:03.919784 <30>[ 21.034384] systemd[1]: Starting Coldplug All udev Devices...
10881 12:28:03.926064 Starting [0;1;39mColdplug All udev Devices[0m...
10882 12:28:03.943705 <30>[ 21.058103] systemd[1]: Mounted Huge Pages File System.
10883 12:28:03.949953 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10884 12:28:03.964361 <30>[ 21.079349] systemd[1]: Mounted POSIX Message Queue File System.
10885 12:28:03.971405 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10886 12:28:03.988732 <30>[ 21.103389] systemd[1]: Mounted Kernel Debug File System.
10887 12:28:03.995194 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10888 12:28:04.015737 <3>[ 21.127453] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:28:04.025970 <30>[ 21.127840] systemd[1]: Finished Create list of static device nodes for the current kernel.
10890 12:28:04.032269 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10891 12:28:04.049814 <3>[ 21.161595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 12:28:04.056419 <30>[ 21.171472] systemd[1]: modprobe@configfs.service: Succeeded.
10893 12:28:04.063307 <30>[ 21.178118] systemd[1]: Finished Load Kernel Module configfs.
10894 12:28:04.069698 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10895 12:28:04.085861 <30>[ 21.199853] systemd[1]: modprobe@drm.service: Succeeded.
10896 12:28:04.092239 <30>[ 21.206061] systemd[1]: Finished Load Kernel Module drm.
10897 12:28:04.101899 <3>[ 21.207401] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 12:28:04.105159 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10899 12:28:04.121490 <30>[ 21.235902] systemd[1]: modprobe@fuse.service: Succeeded.
10900 12:28:04.127893 <30>[ 21.242176] systemd[1]: Finished Load Kernel Module fuse.
10901 12:28:04.137547 <3>[ 21.243481] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 12:28:04.143849 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10903 12:28:04.161213 <30>[ 21.276196] systemd[1]: Finished Load Kernel Modules.
10904 12:28:04.171404 <3>[ 21.279483] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 12:28:04.177653 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10906 12:28:04.197194 <30>[ 21.308186] systemd[1]: Finished Remount Root and Kernel File Systems.
10907 12:28:04.203615 <3>[ 21.311874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 12:28:04.209824 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10909 12:28:04.235199 <3>[ 21.347011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 12:28:04.266638 <3>[ 21.378400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 12:28:04.273086 <30>[ 21.379334] systemd[1]: Mounting FUSE Control File System...
10912 12:28:04.280034 Mounting [0;1;39mFUSE Control File System[0m...
10913 12:28:04.296942 <3>[ 21.408334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 12:28:04.303572 <30>[ 21.409476] systemd[1]: Mounting Kernel Configuration File System...
10915 12:28:04.309836 Mounting [0;1;39mKernel Configuration File System[0m...
10916 12:28:04.325650 <3>[ 21.437283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 12:28:04.340930 <30>[ 21.452175] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10918 12:28:04.351004 <30>[ 21.461178] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10919 12:28:04.369276 <30>[ 21.483604] systemd[1]: Starting Load/Save Random Seed...
10920 12:28:04.375424 Starting [0;1;39mLoad/Save Random Seed[0m...
10921 12:28:04.391726 <30>[ 21.506364] systemd[1]: Starting Apply Kernel Variables...
10922 12:28:04.397908 Starting [0;1;39mApply Kernel Variables[0m...
10923 12:28:04.416167 <30>[ 21.531042] systemd[1]: Starting Create System Users...
10924 12:28:04.422868 Starting [0;1;39mCreate System Users[0m...
10925 12:28:04.437732 <30>[ 21.552654] systemd[1]: Started Journal Service.
10926 12:28:04.444569 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10927 12:28:04.457952 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10928 12:28:04.482347 <4>[ 21.587440] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10929 12:28:04.492713 <3>[ 21.603138] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10930 12:28:04.499109 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10931 12:28:04.514234 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10932 12:28:04.532831 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10933 12:28:04.544457 See 'systemctl status systemd-udev-trigger.service' for details.
10934 12:28:04.580983 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10935 12:28:04.631858 <46>[ 21.743604] systemd-journald[294]: Received client request to flush runtime journal.
10936 12:28:04.800376 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10937 12:28:05.871534 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10938 12:28:05.908581 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10939 12:28:06.165573 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10940 12:28:06.237694 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10941 12:28:06.252799 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10942 12:28:06.268270 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10943 12:28:06.312499 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10944 12:28:06.335889 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10945 12:28:06.499868 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10946 12:28:06.557379 Starting [0;1;39mNetwork Service[0m...
10947 12:28:06.599711 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10948 12:28:06.681547 Starting [0;1;39mNetwork Time Synchronization[0m...
10949 12:28:06.704772 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10950 12:28:06.872385 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10951 12:28:06.897461 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10952 12:28:06.944760 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10953 12:28:07.122401 <6>[ 24.237879] remoteproc remoteproc0: powering up scp
10954 12:28:07.159896 <4>[ 24.271927] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10955 12:28:07.166311 <3>[ 24.281810] remoteproc remoteproc0: request_firmware failed: -2
10956 12:28:07.176455 <3>[ 24.287992] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10957 12:28:07.211570 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10958 12:28:07.305783 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10959 12:28:07.322787 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10960 12:28:07.336562 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10961 12:28:07.405962 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10962 12:28:07.419927 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10963 12:28:07.439806 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 12:28:07.446105 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10965 12:28:07.453130 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10966 12:28:08.168353 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10967 12:28:08.505217 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10968 12:28:08.525962 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10969 12:28:08.546318 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 12:28:08.559787 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 12:28:08.581209 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 12:28:08.595828 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10973 12:28:08.612075 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10974 12:28:08.631667 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10975 12:28:08.656526 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10976 12:28:08.688728 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10977 12:28:08.748941 Starting [0;1;39mUser Login Management[0m...
10978 12:28:08.888823 Starting [0;1;39mNetwork Name Resolution[0m...
10979 12:28:08.912849 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10980 12:28:08.991535 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10981 12:28:09.042428 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10982 12:28:09.065146 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10983 12:28:09.549088 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10984 12:28:09.568682 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10985 12:28:09.590971 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10986 12:28:09.628340 Starting [0;1;39mPermit User Sessions[0m...
10987 12:28:09.660838 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10988 12:28:09.716443 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10989 12:28:09.734956 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10990 12:28:09.752128 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10991 12:28:09.768087 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10992 12:28:09.784034 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10993 12:28:09.824398 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10994 12:28:09.862131 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10995 12:28:09.941695
10996 12:28:09.941866
10997 12:28:09.944774 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10998 12:28:09.944879
10999 12:28:09.948106 debian-bullseye-arm64 login: root (automatic login)
11000 12:28:09.948185
11001 12:28:09.948249
11002 12:28:10.297240 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11003 12:28:10.297393
11004 12:28:10.304000 The programs included with the Debian GNU/Linux system are free software;
11005 12:28:10.310367 the exact distribution terms for each program are described in the
11006 12:28:10.313492 individual files in /usr/share/doc/*/copyright.
11007 12:28:10.313575
11008 12:28:10.319663 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11009 12:28:10.322719 permitted by applicable law.
11010 12:28:10.386216 Matched prompt #10: / #
11012 12:28:10.386481 Setting prompt string to ['/ #']
11013 12:28:10.386582 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11015 12:28:10.386788 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11016 12:28:10.386890 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
11017 12:28:10.386966 Setting prompt string to ['/ #']
11018 12:28:10.387032 Forcing a shell prompt, looking for ['/ #']
11020 12:28:10.437226 / #
11021 12:28:10.437356 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11022 12:28:10.437438 Waiting using forced prompt support (timeout 00:02:30)
11023 12:28:10.442091
11024 12:28:10.442359 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 12:28:10.442452 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11027 12:28:10.542777 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n'
11028 12:28:10.547738 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605797/extract-nfsrootfs-5u1tpd2n'
11030 12:28:10.648218 / # export NFS_SERVER_IP='192.168.201.1'
11031 12:28:10.653095 export NFS_SERVER_IP='192.168.201.1'
11032 12:28:10.653416 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11033 12:28:10.653543 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
11034 12:28:10.653662 end: 2 depthcharge-action (duration 00:01:43) [common]
11035 12:28:10.653787 start: 3 lava-test-retry (timeout 00:01:00) [common]
11036 12:28:10.653908 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11037 12:28:10.654013 Using namespace: common
11039 12:28:10.754355 / # #
11040 12:28:10.754566 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11041 12:28:10.759779 #
11042 12:28:10.760047 Using /lava-10605797
11044 12:28:10.860342 / # export SHELL=/bin/sh
11045 12:28:10.865475 export SHELL=/bin/sh
11047 12:28:10.966030 / # . /lava-10605797/environment
11048 12:28:10.971545 . /lava-10605797/environment
11050 12:28:11.076244 / # /lava-10605797/bin/lava-test-runner /lava-10605797/0
11051 12:28:11.076412 Test shell timeout: 10s (minimum of the action and connection timeout)
11052 12:28:11.081129 /lava-10605797/bin/lava-test-runner /lava-10605797/0
11053 12:28:11.315670 + export TESTRUN_ID=0_dmesg
11054 12:28:11.319032 + cd /lava-10605797/0/tests/0_dmesg
11055 12:28:11.322203 + cat uuid
11056 12:28:11.333390 + UUID=10605797_1.<8>[ 28.446034] <LAVA_SIGNAL_STARTRUN 0_dmesg 10605797_1.6.2.3.1>
11057 12:28:11.333474 6.2.3.1
11058 12:28:11.333543 + set +x
11059 12:28:11.333779 Received signal: <STARTRUN> 0_dmesg 10605797_1.6.2.3.1
11060 12:28:11.333854 Starting test lava.0_dmesg (10605797_1.6.2.3.1)
11061 12:28:11.333942 Skipping test definition patterns.
11062 12:28:11.339830 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11063 12:28:11.432722 <8>[ 28.545355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11064 12:28:11.433032 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11066 12:28:11.503144 <8>[ 28.615873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11067 12:28:11.503446 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11069 12:28:11.574265 <8>[ 28.686272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11070 12:28:11.574579 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11072 12:28:11.577452 + set +x
11073 12:28:11.580676 <8>[ 28.695748] <LAVA_SIGNAL_ENDRUN 0_dmesg 10605797_1.6.2.3.1>
11074 12:28:11.580931 Received signal: <ENDRUN> 0_dmesg 10605797_1.6.2.3.1
11075 12:28:11.581018 Ending use of test pattern.
11076 12:28:11.581083 Ending test lava.0_dmesg (10605797_1.6.2.3.1), duration 0.25
11078 12:28:11.586425 <LAVA_TEST_RUNNER EXIT>
11079 12:28:11.586678 ok: lava_test_shell seems to have completed
11080 12:28:11.586784 alert: pass
crit: pass
emerg: pass
11081 12:28:11.586932 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11082 12:28:11.587037 end: 3 lava-test-retry (duration 00:00:01) [common]
11083 12:28:11.587120 start: 4 lava-test-retry (timeout 00:01:00) [common]
11084 12:28:11.587202 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11085 12:28:11.587267 Using namespace: common
11087 12:28:11.687570 / # #
11088 12:28:11.687744 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11089 12:28:11.687861 Using /lava-10605797
11091 12:28:11.788168 export SHELL=/bin/sh
11092 12:28:11.788386 #
11094 12:28:11.888874 / # export SHELL=/bin/sh. /lava-10605797/environment
11095 12:28:11.889079
11097 12:28:11.989605 / # . /lava-10605797/environment/lava-10605797/bin/lava-test-runner /lava-10605797/1
11098 12:28:11.989759 Test shell timeout: 10s (minimum of the action and connection timeout)
11099 12:28:11.989880
11100 12:28:11.994778 / # /lava-10605797/bin/lava-test-runner /lava-10605797/1
11101 12:28:12.118885 + export TESTRUN_ID=1_bootrr
11102 12:28:12.122390 + cd /lava-10605797/1/tests/1_bootrr
11103 12:28:12.125436 + cat uuid
11104 12:28:12.139511 + UUID=10605797_<8>[ 29.251759] <LAVA_SIGNAL_STARTRUN 1_bootrr 10605797_1.6.2.3.5>
11105 12:28:12.139613 1.6.2.3.5
11106 12:28:12.139686 + set +x
11107 12:28:12.139924 Received signal: <STARTRUN> 1_bootrr 10605797_1.6.2.3.5
11108 12:28:12.139992 Starting test lava.1_bootrr (10605797_1.6.2.3.5)
11109 12:28:12.140074 Skipping test definition patterns.
11110 12:28:12.152146 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10605797/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11111 12:28:12.155772 + cd /opt/bootrr/libexec/bootrr
11112 12:28:12.155895 + sh helpers/bootrr-auto
11113 12:28:12.218343 /lava-10605797/1/../bin/lava-test-case
11114 12:28:12.250352 <8>[ 29.362730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11115 12:28:12.250679 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11117 12:28:12.297030 /lava-10605797/1/../bin/lava-test-case
11118 12:28:12.325789 <8>[ 29.438423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11119 12:28:12.326107 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11121 12:28:12.350390 /lava-10605797/1/../bin/lava-test-case
11122 12:28:12.382067 <8>[ 29.494705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11123 12:28:12.382404 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11125 12:28:12.436490 /lava-10605797/1/../bin/lava-test-case
11126 12:28:12.467533 <8>[ 29.579793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11127 12:28:12.467857 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11129 12:28:12.503763 /lava-10605797/1/../bin/lava-test-case
11130 12:28:12.535596 <8>[ 29.647886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11131 12:28:12.535924 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11133 12:28:12.569781 /lava-10605797/1/../bin/lava-test-case
11134 12:28:12.599311 <8>[ 29.711881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11135 12:28:12.599593 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11137 12:28:12.634596 /lava-10605797/1/../bin/lava-test-case
11138 12:28:12.663083 <8>[ 29.775716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11139 12:28:12.663361 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11141 12:28:12.698708 /lava-10605797/1/../bin/lava-test-case
11142 12:28:12.728037 <8>[ 29.840693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11143 12:28:12.728340 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11145 12:28:12.757055 /lava-10605797/1/../bin/lava-test-case
11146 12:28:12.784271 <8>[ 29.896422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11147 12:28:12.784550 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11149 12:28:12.823301 /lava-10605797/1/../bin/lava-test-case
11150 12:28:12.849590 <8>[ 29.962303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11151 12:28:12.849892 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11153 12:28:12.872095 /lava-10605797/1/../bin/lava-test-case
11154 12:28:12.899238 <8>[ 30.011729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11155 12:28:12.899515 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11157 12:28:12.937280 /lava-10605797/1/../bin/lava-test-case
11158 12:28:12.968079 <8>[ 30.080844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11159 12:28:12.968378 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11161 12:28:13.002727 /lava-10605797/1/../bin/lava-test-case
11162 12:28:13.033294 <8>[ 30.146046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11163 12:28:13.033601 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11165 12:28:13.075830 /lava-10605797/1/../bin/lava-test-case
11166 12:28:13.103166 <8>[ 30.215710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11167 12:28:13.103474 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11169 12:28:13.143330 /lava-10605797/1/../bin/lava-test-case
11170 12:28:13.171167 <8>[ 30.283705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11171 12:28:13.171484 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11173 12:28:13.197065 /lava-10605797/1/../bin/lava-test-case
11174 12:28:13.228826 <8>[ 30.341244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11175 12:28:13.229136 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11177 12:28:13.265987 /lava-10605797/1/../bin/lava-test-case
11178 12:28:13.295491 <8>[ 30.407999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11179 12:28:13.295758 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11181 12:28:13.318467 /lava-10605797/1/../bin/lava-test-case
11182 12:28:13.347275 <8>[ 30.459554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11183 12:28:13.347551 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11185 12:28:13.383798 /lava-10605797/1/../bin/lava-test-case
11186 12:28:13.416967 <8>[ 30.529302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11187 12:28:13.417255 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11189 12:28:13.445547 /lava-10605797/1/../bin/lava-test-case
11190 12:28:13.474663 <8>[ 30.587396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11191 12:28:13.474979 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11193 12:28:13.513640 /lava-10605797/1/../bin/lava-test-case
11194 12:28:13.544701 <8>[ 30.657429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11195 12:28:13.544985 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11197 12:28:13.567111 /lava-10605797/1/../bin/lava-test-case
11198 12:28:13.598937 <8>[ 30.711210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11199 12:28:13.599224 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11201 12:28:13.637302 /lava-10605797/1/../bin/lava-test-case
11202 12:28:13.667440 <8>[ 30.779546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11203 12:28:13.667727 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11205 12:28:13.688508 /lava-10605797/1/../bin/lava-test-case
11206 12:28:13.720731 <8>[ 30.833122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11207 12:28:13.721037 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11209 12:28:13.757044 /lava-10605797/1/../bin/lava-test-case
11210 12:28:13.789308 <8>[ 30.901997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11211 12:28:13.789603 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11213 12:28:13.830236 /lava-10605797/1/../bin/lava-test-case
11214 12:28:13.858170 <8>[ 30.970775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11215 12:28:13.858439 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11217 12:28:13.882103 /lava-10605797/1/../bin/lava-test-case
11218 12:28:13.914984 <8>[ 31.027867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11219 12:28:13.915316 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11221 12:28:13.955205 /lava-10605797/1/../bin/lava-test-case
11222 12:28:13.985801 <8>[ 31.098374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11223 12:28:13.986099 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11225 12:28:14.007791 /lava-10605797/1/../bin/lava-test-case
11226 12:28:14.036420 <8>[ 31.148570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11227 12:28:14.036733 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11229 12:28:14.077700 /lava-10605797/1/../bin/lava-test-case
11230 12:28:14.108577 <8>[ 31.221334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11231 12:28:14.108889 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11233 12:28:14.155380 /lava-10605797/1/../bin/lava-test-case
11234 12:28:14.183121 <8>[ 31.295773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11235 12:28:14.183400 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11237 12:28:14.221520 /lava-10605797/1/../bin/lava-test-case
11238 12:28:14.254142 <8>[ 31.366530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11239 12:28:14.254468 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11241 12:28:14.290749 /lava-10605797/1/../bin/lava-test-case
11242 12:28:14.323710 <8>[ 31.436517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11243 12:28:14.323985 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11245 12:28:14.345801 /lava-10605797/1/../bin/lava-test-case
11246 12:28:14.373802 <8>[ 31.486630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11247 12:28:14.374073 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11249 12:28:14.409943 /lava-10605797/1/../bin/lava-test-case
11250 12:28:14.442157 <8>[ 31.554627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11251 12:28:14.442430 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11253 12:28:14.486020 /lava-10605797/1/../bin/lava-test-case
11254 12:28:14.518931 <8>[ 31.631721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11255 12:28:14.519211 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11257 12:28:14.542807 /lava-10605797/1/../bin/lava-test-case
11258 12:28:14.573858 <8>[ 31.686593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11259 12:28:14.574161 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11261 12:28:14.616238 /lava-10605797/1/../bin/lava-test-case
11262 12:28:14.650016 <8>[ 31.762743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11263 12:28:14.650314 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11265 12:28:14.673108 /lava-10605797/1/../bin/lava-test-case
11266 12:28:14.701907 <8>[ 31.814529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11267 12:28:14.702217 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11269 12:28:14.736351 /lava-10605797/1/../bin/lava-test-case
11270 12:28:14.767003 <8>[ 31.879621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11271 12:28:14.767279 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11273 12:28:14.790437 /lava-10605797/1/../bin/lava-test-case
11274 12:28:14.826597 <8>[ 31.939691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11275 12:28:14.826928 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11277 12:28:14.868972 /lava-10605797/1/../bin/lava-test-case
11278 12:28:14.897524 <8>[ 32.010005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11279 12:28:14.897941 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11281 12:28:14.917171 /lava-10605797/1/../bin/lava-test-case
11282 12:28:14.946226 <8>[ 32.058881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11283 12:28:14.946548 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11285 12:28:14.981890 /lava-10605797/1/../bin/lava-test-case
11286 12:28:15.009566 <8>[ 32.122342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11287 12:28:15.009847 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11289 12:28:15.033646 /lava-10605797/1/../bin/lava-test-case
11290 12:28:15.061507 <8>[ 32.174002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11291 12:28:15.061805 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11293 12:28:15.095734 /lava-10605797/1/../bin/lava-test-case
11294 12:28:15.125408 <8>[ 32.237943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11295 12:28:15.125697 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11297 12:28:15.148169 /lava-10605797/1/../bin/lava-test-case
11298 12:28:15.176528 <8>[ 32.289337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11299 12:28:15.176806 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11301 12:28:15.222553 /lava-10605797/1/../bin/lava-test-case
11302 12:28:15.251165 <8>[ 32.364004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11303 12:28:15.251445 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11305 12:28:15.272916 /lava-10605797/1/../bin/lava-test-case
11306 12:28:15.301150 <8>[ 32.413733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11307 12:28:15.301417 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11309 12:28:15.336470 /lava-10605797/1/../bin/lava-test-case
11310 12:28:15.366457 <8>[ 32.478959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11311 12:28:15.366741 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11313 12:28:15.404179 /lava-10605797/1/../bin/lava-test-case
11314 12:28:15.433192 <8>[ 32.545828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11315 12:28:15.433468 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11317 12:28:16.479056 /lava-10605797/1/../bin/lava-test-case
11318 12:28:16.507292 <8>[ 33.620400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11319 12:28:16.507574 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11321 12:28:17.546259 /lava-10605797/1/../bin/lava-test-case
11322 12:28:17.581202 <8>[ 34.693991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11323 12:28:17.581947 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11324 12:28:17.582418 Bad test result: blocked
11325 12:28:17.611810 /lava-10605797/1/../bin/lava-test-case
11326 12:28:17.648339 <8>[ 34.760759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11327 12:28:17.649109 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11329 12:28:17.688224 /lava-10605797/1/../bin/lava-test-case
11330 12:28:17.725862 <8>[ 34.838428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11331 12:28:17.726823 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11333 12:28:17.768084 /lava-10605797/1/../bin/lava-test-case
11334 12:28:17.805068 <8>[ 34.917468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11335 12:28:17.805978 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11337 12:28:17.847242 /lava-10605797/1/../bin/lava-test-case
11338 12:28:17.886046 <8>[ 34.999050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11339 12:28:17.886987 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11341 12:28:17.935258 /lava-10605797/1/../bin/lava-test-case
11342 12:28:17.971541 <8>[ 35.084521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11343 12:28:17.972408 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11345 12:28:18.013951 /lava-10605797/1/../bin/lava-test-case
11346 12:28:18.048154 <8>[ 35.161141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11347 12:28:18.048880 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11349 12:28:18.075284 /lava-10605797/1/../bin/lava-test-case
11350 12:28:18.114938 <8>[ 35.227902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11351 12:28:18.115651 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11353 12:28:18.161863 /lava-10605797/1/../bin/lava-test-case
11354 12:28:18.193945 <8>[ 35.307192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11355 12:28:18.194254 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11357 12:28:18.234439 /lava-10605797/1/../bin/lava-test-case
11358 12:28:18.268983 <8>[ 35.382225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11359 12:28:18.269292 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11361 12:28:18.296986 /lava-10605797/1/../bin/lava-test-case
11362 12:28:18.334567 <8>[ 35.447502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11363 12:28:18.335355 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11365 12:28:18.381352 /lava-10605797/1/../bin/lava-test-case
11366 12:28:18.420839 <8>[ 35.533676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11367 12:28:18.421604 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11369 12:28:18.450885 /lava-10605797/1/../bin/lava-test-case
11370 12:28:18.486102 <8>[ 35.598511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11371 12:28:18.486996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11373 12:28:18.531787 /lava-10605797/1/../bin/lava-test-case
11374 12:28:18.568933 <8>[ 35.681643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11375 12:28:18.569663 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11377 12:28:18.595435 /lava-10605797/1/../bin/lava-test-case
11378 12:28:18.631400 <8>[ 35.744570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11379 12:28:18.632283 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11381 12:28:18.681788 /lava-10605797/1/../bin/lava-test-case
11382 12:28:18.714754 <8>[ 35.827863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11383 12:28:18.715102 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11385 12:28:18.752776 /lava-10605797/1/../bin/lava-test-case
11386 12:28:18.786940 <8>[ 35.900201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11387 12:28:18.787241 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11389 12:28:18.826405 /lava-10605797/1/../bin/lava-test-case
11390 12:28:18.857664 <8>[ 35.971114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11391 12:28:18.857998 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11393 12:28:18.895044 /lava-10605797/1/../bin/lava-test-case
11394 12:28:18.922542 <8>[ 36.035420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11395 12:28:18.922833 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11397 12:28:18.962338 /lava-10605797/1/../bin/lava-test-case
11398 12:28:18.992482 <8>[ 36.105633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11399 12:28:18.992773 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11401 12:28:19.036534 /lava-10605797/1/../bin/lava-test-case
11402 12:28:19.066286 <8>[ 36.179379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11403 12:28:19.066575 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11405 12:28:19.104660 /lava-10605797/1/../bin/lava-test-case
11406 12:28:19.131327 <8>[ 36.244474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11407 12:28:19.131623 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11409 12:28:19.165455 /lava-10605797/1/../bin/lava-test-case
11410 12:28:19.192290 <8>[ 36.305406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11411 12:28:19.192554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11413 12:28:19.227095 /lava-10605797/1/../bin/lava-test-case
11414 12:28:19.256427 <8>[ 36.369921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11415 12:28:19.256698 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11417 12:28:19.290205 /lava-10605797/1/../bin/lava-test-case
11418 12:28:19.318944 <8>[ 36.432355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11419 12:28:19.319209 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11421 12:28:19.357314 /lava-10605797/1/../bin/lava-test-case
11422 12:28:19.385649 <8>[ 36.499023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11423 12:28:19.385924 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11425 12:28:19.423027 /lava-10605797/1/../bin/lava-test-case
11426 12:28:19.452599 <8>[ 36.565917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11427 12:28:19.452886 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11429 12:28:19.485316 /lava-10605797/1/../bin/lava-test-case
11430 12:28:19.513402 <8>[ 36.626518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11431 12:28:19.513684 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11433 12:28:19.551062 /lava-10605797/1/../bin/lava-test-case
11434 12:28:19.578030 <8>[ 36.691481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11435 12:28:19.578305 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11437 12:28:19.611901 /lava-10605797/1/../bin/lava-test-case
11438 12:28:19.643650 <8>[ 36.756611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11439 12:28:19.643931 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11441 12:28:19.674203 /lava-10605797/1/../bin/lava-test-case
11442 12:28:19.706549 <8>[ 36.820224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11443 12:28:19.706867 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11445 12:28:19.740708 /lava-10605797/1/../bin/lava-test-case
11446 12:28:19.765571 <8>[ 36.878968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11447 12:28:19.765872 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11449 12:28:19.790526 /lava-10605797/1/../bin/lava-test-case
11450 12:28:19.823996 <8>[ 36.937104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11451 12:28:19.824300 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11453 12:28:19.862945 /lava-10605797/1/../bin/lava-test-case
11454 12:28:19.895629 <8>[ 37.009038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11455 12:28:19.896188 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11457 12:28:19.917505 /lava-10605797/1/../bin/lava-test-case
11458 12:28:19.949288 <8>[ 37.062715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11459 12:28:19.949613 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11461 12:28:19.985078 /lava-10605797/1/../bin/lava-test-case
11462 12:28:20.017523 <8>[ 37.130713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11463 12:28:20.017808 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11465 12:28:20.048544 /lava-10605797/1/../bin/lava-test-case
11466 12:28:20.078333 <8>[ 37.191731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11467 12:28:20.078621 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11469 12:28:20.114055 /lava-10605797/1/../bin/lava-test-case
11470 12:28:20.145202 <8>[ 37.258873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11471 12:28:20.145489 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11473 12:28:20.165659 /lava-10605797/1/../bin/lava-test-case
11474 12:28:20.191032 <8>[ 37.304688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11475 12:28:20.191300 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11477 12:28:20.224365 /lava-10605797/1/../bin/lava-test-case
11478 12:28:20.250491 <8>[ 37.364037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11479 12:28:20.250804 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11481 12:28:20.270627 /lava-10605797/1/../bin/lava-test-case
11482 12:28:20.300755 <8>[ 37.414047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11483 12:28:20.301052 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11485 12:28:20.332250 /lava-10605797/1/../bin/lava-test-case
11486 12:28:20.359139 <8>[ 37.472718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11487 12:28:20.359463 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11489 12:28:20.406204 /lava-10605797/1/../bin/lava-test-case
11490 12:28:20.436566 <8>[ 37.549570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11491 12:28:20.437404 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11493 12:28:20.461593 /lava-10605797/1/../bin/lava-test-case
11494 12:28:20.492824 <8>[ 37.605949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11495 12:28:20.493610 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11497 12:28:20.535130 /lava-10605797/1/../bin/lava-test-case
11498 12:28:20.569962 <8>[ 37.682721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11499 12:28:20.570669 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11501 12:28:20.593091 /lava-10605797/1/../bin/lava-test-case
11502 12:28:20.624616 <8>[ 37.737989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11503 12:28:20.624925 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11505 12:28:20.661232 /lava-10605797/1/../bin/lava-test-case
11506 12:28:20.689855 <8>[ 37.802898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11507 12:28:20.690345 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11509 12:28:20.719236 /lava-10605797/1/../bin/lava-test-case
11510 12:28:20.756773 <8>[ 37.870371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11511 12:28:20.757210 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11513 12:28:21.810781 /lava-10605797/1/../bin/lava-test-case
11514 12:28:21.843217 <8>[ 38.956554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11515 12:28:21.843503 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11517 12:28:21.865019 /lava-10605797/1/../bin/lava-test-case
11518 12:28:21.898672 <8>[ 39.011999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11519 12:28:21.899007 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11521 12:28:22.947520 /lava-10605797/1/../bin/lava-test-case
11522 12:28:22.979708 <8>[ 40.093668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11523 12:28:22.980016 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11525 12:28:23.000757 /lava-10605797/1/../bin/lava-test-case
11526 12:28:23.027781 <8>[ 40.141658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11527 12:28:23.028069 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11529 12:28:24.071219 /lava-10605797/1/../bin/lava-test-case
11530 12:28:24.100543 <8>[ 41.214365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11531 12:28:24.100895 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11533 12:28:24.124145 /lava-10605797/1/../bin/lava-test-case
11534 12:28:24.148986 <8>[ 41.262563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11535 12:28:24.149308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11537 12:28:25.189757 /lava-10605797/1/../bin/lava-test-case
11538 12:28:25.227858 <8>[ 42.342068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11539 12:28:25.228204 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11541 12:28:25.252444 /lava-10605797/1/../bin/lava-test-case
11542 12:28:25.281557 <8>[ 42.395407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11543 12:28:25.281907 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11545 12:28:26.332660 /lava-10605797/1/../bin/lava-test-case
11546 12:28:26.364884 <8>[ 43.479207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11547 12:28:26.365205 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11549 12:28:26.388631 /lava-10605797/1/../bin/lava-test-case
11550 12:28:26.416371 <8>[ 43.530736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11551 12:28:26.416639 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11553 12:28:27.469476 /lava-10605797/1/../bin/lava-test-case
11554 12:28:27.501691 <8>[ 44.615813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11555 12:28:27.502022 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11557 12:28:27.523815 /lava-10605797/1/../bin/lava-test-case
11558 12:28:27.550055 <8>[ 44.663917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11559 12:28:27.550341 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11561 12:28:28.598310 /lava-10605797/1/../bin/lava-test-case
11562 12:28:28.634485 <8>[ 45.748604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11563 12:28:28.634813 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11565 12:28:28.655347 /lava-10605797/1/../bin/lava-test-case
11566 12:28:28.684454 <8>[ 45.799041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11567 12:28:28.684751 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11569 12:28:28.707769 /lava-10605797/1/../bin/lava-test-case
11570 12:28:28.734379 <8>[ 45.849020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11571 12:28:28.734644 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11573 12:28:29.034138 <6>[ 46.155024] vpu: disabling
11574 12:28:29.037303 <6>[ 46.158085] vproc2: disabling
11575 12:28:29.040324 <6>[ 46.161363] vproc1: disabling
11576 12:28:29.043577 <6>[ 46.164630] vaud18: disabling
11577 12:28:29.050594 <6>[ 46.168035] vsram_others: disabling
11578 12:28:29.053777 <6>[ 46.171915] va09: disabling
11579 12:28:29.056829 <6>[ 46.175021] vsram_md: disabling
11580 12:28:29.059979 <6>[ 46.178505] Vgpu: disabling
11581 12:28:29.777757 /lava-10605797/1/../bin/lava-test-case
11582 12:28:29.807488 <8>[ 46.922100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11583 12:28:29.807772 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11585 12:28:29.834783 /lava-10605797/1/../bin/lava-test-case
11586 12:28:29.864812 <8>[ 46.979407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11587 12:28:29.865091 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11589 12:28:29.901396 /lava-10605797/1/../bin/lava-test-case
11590 12:28:29.931264 <8>[ 47.045774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11591 12:28:29.931555 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11593 12:28:29.953573 /lava-10605797/1/../bin/lava-test-case
11594 12:28:29.983475 <8>[ 47.098329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11595 12:28:29.983750 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11597 12:28:30.021040 /lava-10605797/1/../bin/lava-test-case
11598 12:28:30.052204 <8>[ 47.166474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11599 12:28:30.052508 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11601 12:28:30.087944 /lava-10605797/1/../bin/lava-test-case
11602 12:28:30.118393 <8>[ 47.232774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11603 12:28:30.118696 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11605 12:28:30.160338 /lava-10605797/1/../bin/lava-test-case
11606 12:28:30.189784 <8>[ 47.304420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11607 12:28:30.190077 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11609 12:28:30.212670 /lava-10605797/1/../bin/lava-test-case
11610 12:28:30.240312 <8>[ 47.354773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11611 12:28:30.240607 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11613 12:28:30.275681 /lava-10605797/1/../bin/lava-test-case
11614 12:28:30.306120 <8>[ 47.420828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11615 12:28:30.306396 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11617 12:28:30.342533 /lava-10605797/1/../bin/lava-test-case
11618 12:28:30.374173 <8>[ 47.488699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11619 12:28:30.374455 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11621 12:28:30.399700 /lava-10605797/1/../bin/lava-test-case
11622 12:28:30.429021 <8>[ 47.543909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11623 12:28:30.429312 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11625 12:28:30.471079 /lava-10605797/1/../bin/lava-test-case
11626 12:28:30.498248 <8>[ 47.612618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11627 12:28:30.498519 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11629 12:28:30.522557 /lava-10605797/1/../bin/lava-test-case
11630 12:28:30.553847 <8>[ 47.668180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11631 12:28:30.554128 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11633 12:28:30.590629 /lava-10605797/1/../bin/lava-test-case
11634 12:28:30.616650 <8>[ 47.731434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11635 12:28:30.616919 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11637 12:28:30.641151 /lava-10605797/1/../bin/lava-test-case
11638 12:28:30.677799 <8>[ 47.792421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11639 12:28:30.678069 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11641 12:28:30.717359 /lava-10605797/1/../bin/lava-test-case
11642 12:28:30.748417 <8>[ 47.863182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11643 12:28:30.748717 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11645 12:28:30.780260 /lava-10605797/1/../bin/lava-test-case
11646 12:28:30.811995 <8>[ 47.926336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11647 12:28:30.812277 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11649 12:28:30.852758 /lava-10605797/1/../bin/lava-test-case
11650 12:28:30.883856 <8>[ 47.998412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11651 12:28:30.884127 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11653 12:28:30.908311 /lava-10605797/1/../bin/lava-test-case
11654 12:28:30.944465 <8>[ 48.058851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11655 12:28:30.944746 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11657 12:28:30.984162 /lava-10605797/1/../bin/lava-test-case
11658 12:28:31.019341 <8>[ 48.134106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11659 12:28:31.019603 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11661 12:28:31.044378 /lava-10605797/1/../bin/lava-test-case
11662 12:28:31.071258 <8>[ 48.186195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11663 12:28:31.071530 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11665 12:28:32.129847 /lava-10605797/1/../bin/lava-test-case
11666 12:28:32.157967 <8>[ 49.272461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11667 12:28:32.158282 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11669 12:28:33.205203 /lava-10605797/1/../bin/lava-test-case
11670 12:28:33.238339 <8>[ 50.353356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11671 12:28:33.238668 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11673 12:28:33.259360 /lava-10605797/1/../bin/lava-test-case
11674 12:28:33.286448 <8>[ 50.401520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11675 12:28:33.286737 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11677 12:28:33.326050 /lava-10605797/1/../bin/lava-test-case
11678 12:28:33.352760 <8>[ 50.467992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11679 12:28:33.353059 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11681 12:28:33.373860 /lava-10605797/1/../bin/lava-test-case
11682 12:28:33.401205 <8>[ 50.515832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11683 12:28:33.401531 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11685 12:28:33.435813 /lava-10605797/1/../bin/lava-test-case
11686 12:28:33.464549 <8>[ 50.579201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11687 12:28:33.464853 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11689 12:28:33.486272 /lava-10605797/1/../bin/lava-test-case
11690 12:28:33.514652 <8>[ 50.629794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11691 12:28:33.514958 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11693 12:28:33.560301 /lava-10605797/1/../bin/lava-test-case
11694 12:28:33.592137 <8>[ 50.706962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11695 12:28:33.592458 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11697 12:28:33.612073 /lava-10605797/1/../bin/lava-test-case
11698 12:28:33.640334 <8>[ 50.755275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11699 12:28:33.640601 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11701 12:28:33.673911 /lava-10605797/1/../bin/lava-test-case
11702 12:28:33.701289 <8>[ 50.816427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11703 12:28:33.701623 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11705 12:28:33.723250 /lava-10605797/1/../bin/lava-test-case
11706 12:28:33.752884 <8>[ 50.868078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11707 12:28:33.753169 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11709 12:28:33.786681 /lava-10605797/1/../bin/lava-test-case
11710 12:28:33.815273 <8>[ 50.930341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11711 12:28:33.815557 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11713 12:28:33.839383 /lava-10605797/1/../bin/lava-test-case
11714 12:28:33.870379 <8>[ 50.985373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11715 12:28:33.870681 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11717 12:28:33.912247 /lava-10605797/1/../bin/lava-test-case
11718 12:28:33.939067 <8>[ 51.054116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11719 12:28:33.939379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11721 12:28:33.960254 /lava-10605797/1/../bin/lava-test-case
11722 12:28:33.987061 <8>[ 51.102211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11723 12:28:33.987365 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11725 12:28:34.020617 /lava-10605797/1/../bin/lava-test-case
11726 12:28:34.048172 <8>[ 51.163185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11727 12:28:34.048480 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11729 12:28:34.069826 /lava-10605797/1/../bin/lava-test-case
11730 12:28:34.097782 <8>[ 51.212660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11731 12:28:34.098068 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11733 12:28:34.132648 /lava-10605797/1/../bin/lava-test-case
11734 12:28:34.160949 <8>[ 51.275867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11735 12:28:34.161237 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11737 12:28:34.182374 /lava-10605797/1/../bin/lava-test-case
11738 12:28:34.218135 <8>[ 51.332968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11739 12:28:34.218473 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11741 12:28:34.255783 /lava-10605797/1/../bin/lava-test-case
11742 12:28:34.288018 <8>[ 51.402687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11743 12:28:34.288345 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11745 12:28:34.309190 /lava-10605797/1/../bin/lava-test-case
11746 12:28:34.337962 <8>[ 51.453174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11747 12:28:34.338262 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11749 12:28:34.374654 /lava-10605797/1/../bin/lava-test-case
11750 12:28:34.406813 <8>[ 51.521909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11751 12:28:34.407173 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11753 12:28:35.442347 /lava-10605797/1/../bin/lava-test-case
11754 12:28:35.475781 <8>[ 52.591154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11755 12:28:35.476106 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11757 12:28:36.512161 /lava-10605797/1/../bin/lava-test-case
11758 12:28:36.537925 <8>[ 53.653502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11759 12:28:36.538201 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11760 12:28:36.538288 Bad test result: blocked
11761 12:28:36.561228 /lava-10605797/1/../bin/lava-test-case
11762 12:28:36.589629 <8>[ 53.704722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11763 12:28:36.589948 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11765 12:28:37.634111 /lava-10605797/1/../bin/lava-test-case
11766 12:28:37.662608 <8>[ 54.778365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11767 12:28:37.662915 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11769 12:28:37.686983 /lava-10605797/1/../bin/lava-test-case
11770 12:28:37.712207 <8>[ 54.827881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11771 12:28:37.712482 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11773 12:28:37.743669 /lava-10605797/1/../bin/lava-test-case
11774 12:28:37.770902 <8>[ 54.886058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11775 12:28:37.771190 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11777 12:28:37.808037 /lava-10605797/1/../bin/lava-test-case
11778 12:28:37.836989 <8>[ 54.952335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11779 12:28:37.837269 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11781 12:28:37.858963 /lava-10605797/1/../bin/lava-test-case
11782 12:28:37.883377 <8>[ 54.999040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11783 12:28:37.883664 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11785 12:28:37.917485 /lava-10605797/1/../bin/lava-test-case
11786 12:28:37.945423 <8>[ 55.060616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11787 12:28:37.945737 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11789 12:28:37.972576 /lava-10605797/1/../bin/lava-test-case
11790 12:28:37.998700 <8>[ 55.114036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11791 12:28:37.998991 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11793 12:28:39.040723 /lava-10605797/1/../bin/lava-test-case
11794 12:28:39.073919 <8>[ 56.189180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11795 12:28:39.074225 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11797 12:28:39.097100 /lava-10605797/1/../bin/lava-test-case
11798 12:28:39.121508 <8>[ 56.237396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11799 12:28:39.121857 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11801 12:28:40.163321 /lava-10605797/1/../bin/lava-test-case
11802 12:28:40.192221 <8>[ 57.308006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11803 12:28:40.192590 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11805 12:28:40.216326 /lava-10605797/1/../bin/lava-test-case
11806 12:28:40.245976 <8>[ 57.361966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11807 12:28:40.246302 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11809 12:28:41.294703 /lava-10605797/1/../bin/lava-test-case
11810 12:28:41.326419 <8>[ 58.442193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11811 12:28:41.326759 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11813 12:28:41.349361 /lava-10605797/1/../bin/lava-test-case
11814 12:28:41.373728 <8>[ 58.489482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11815 12:28:41.374069 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11817 12:28:42.415628 /lava-10605797/1/../bin/lava-test-case
11818 12:28:42.444214 <8>[ 59.560053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11819 12:28:42.444571 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11821 12:28:42.475284 /lava-10605797/1/../bin/lava-test-case
11822 12:28:42.513709 <8>[ 59.629875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11823 12:28:42.514029 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11825 12:28:42.550965 /lava-10605797/1/../bin/lava-test-case
11826 12:28:42.583994 <8>[ 59.699708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11827 12:28:42.584336 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11829 12:28:42.626555 /lava-10605797/1/../bin/lava-test-case
11830 12:28:42.660333 <8>[ 59.776349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11831 12:28:42.660667 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11833 12:28:42.685413 /lava-10605797/1/../bin/lava-test-case
11834 12:28:42.716989 <8>[ 59.832813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11835 12:28:42.717325 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11837 12:28:42.763136 /lava-10605797/1/../bin/lava-test-case
11838 12:28:42.799637 <8>[ 59.915532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11839 12:28:42.799997 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11841 12:28:42.824160 /lava-10605797/1/../bin/lava-test-case
11842 12:28:42.850231 <8>[ 59.966404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11843 12:28:42.850551 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11845 12:28:42.884645 /lava-10605797/1/../bin/lava-test-case
11846 12:28:42.912329 <8>[ 60.028448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11847 12:28:42.912672 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11849 12:28:42.937528 /lava-10605797/1/../bin/lava-test-case
11850 12:28:42.965187 <8>[ 60.080890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11851 12:28:42.965510 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11853 12:28:44.011156 /lava-10605797/1/../bin/lava-test-case
11854 12:28:44.042407 <8>[ 61.158529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11855 12:28:44.042729 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11857 12:28:44.050736 + <8>[ 61.170417] <LAVA_SIGNAL_ENDRUN 1_bootrr 10605797_1.6.2.3.5>
11858 12:28:44.051023 Received signal: <ENDRUN> 1_bootrr 10605797_1.6.2.3.5
11859 12:28:44.051105 Ending use of test pattern.
11860 12:28:44.051171 Ending test lava.1_bootrr (10605797_1.6.2.3.5), duration 31.91
11862 12:28:44.053822 set +x
11863 12:28:44.058059 <LAVA_TEST_RUNNER EXIT>
11864 12:28:44.058307 ok: lava_test_shell seems to have completed
11865 12:28:44.059505 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11866 12:28:44.059656 end: 4.1 lava-test-shell (duration 00:00:32) [common]
11867 12:28:44.059764 end: 4 lava-test-retry (duration 00:00:32) [common]
11868 12:28:44.059858 start: 5 finalize (timeout 00:07:08) [common]
11869 12:28:44.059952 start: 5.1 power-off (timeout 00:00:30) [common]
11870 12:28:44.060107 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11871 12:28:44.137894 >> Command sent successfully.
11872 12:28:44.140457 Returned 0 in 0 seconds
11873 12:28:44.240833 end: 5.1 power-off (duration 00:00:00) [common]
11875 12:28:44.241159 start: 5.2 read-feedback (timeout 00:07:08) [common]
11876 12:28:44.241421 Listened to connection for namespace 'common' for up to 1s
11877 12:28:45.242392 Finalising connection for namespace 'common'
11878 12:28:45.242556 Disconnecting from shell: Finalise
11879 12:28:45.242639 / #
11880 12:28:45.343000 end: 5.2 read-feedback (duration 00:00:01) [common]
11881 12:28:45.343163 end: 5 finalize (duration 00:00:01) [common]
11882 12:28:45.343281 Cleaning after the job
11883 12:28:45.343376 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/ramdisk
11884 12:28:45.345494 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/kernel
11885 12:28:45.355897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/dtb
11886 12:28:45.356056 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/nfsrootfs
11887 12:28:45.409081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605797/tftp-deploy-r9s28fa7/modules
11888 12:28:45.414822 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605797
11889 12:28:45.718416 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605797
11890 12:28:45.718600 Job finished correctly