Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 12:28:42.026862 lava-dispatcher, installed at version: 2023.05.1
2 12:28:42.027091 start: 0 validate
3 12:28:42.027228 Start time: 2023-06-06 12:28:42.027221+00:00 (UTC)
4 12:28:42.027365 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:28:42.027501 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:28:42.315126 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:28:42.315372 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:28:42.606485 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:28:42.606690 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:28:42.893001 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:28:42.893185 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:28:43.184657 validate duration: 1.16
14 12:28:43.184935 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:28:43.185043 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:28:43.185166 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:28:43.185331 Not decompressing ramdisk as can be used compressed.
18 12:28:43.185449 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 12:28:43.185545 saving as /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/ramdisk/rootfs.cpio.gz
20 12:28:43.185641 total size: 34405874 (32MB)
21 12:28:43.187328 progress 0% (0MB)
22 12:28:43.196510 progress 5% (1MB)
23 12:28:43.205937 progress 10% (3MB)
24 12:28:43.214883 progress 15% (4MB)
25 12:28:43.223954 progress 20% (6MB)
26 12:28:43.233052 progress 25% (8MB)
27 12:28:43.241959 progress 30% (9MB)
28 12:28:43.250943 progress 35% (11MB)
29 12:28:43.259955 progress 40% (13MB)
30 12:28:43.268875 progress 45% (14MB)
31 12:28:43.277840 progress 50% (16MB)
32 12:28:43.287048 progress 55% (18MB)
33 12:28:43.295885 progress 60% (19MB)
34 12:28:43.305046 progress 65% (21MB)
35 12:28:43.314176 progress 70% (22MB)
36 12:28:43.323409 progress 75% (24MB)
37 12:28:43.332446 progress 80% (26MB)
38 12:28:43.341498 progress 85% (27MB)
39 12:28:43.350384 progress 90% (29MB)
40 12:28:43.359599 progress 95% (31MB)
41 12:28:43.368458 progress 100% (32MB)
42 12:28:43.368760 32MB downloaded in 0.18s (179.19MB/s)
43 12:28:43.368924 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:28:43.369333 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:28:43.369456 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:28:43.369560 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:28:43.369698 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:28:43.369795 saving as /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/kernel/Image
50 12:28:43.369859 total size: 45746688 (43MB)
51 12:28:43.369923 No compression specified
52 12:28:43.371499 progress 0% (0MB)
53 12:28:43.383109 progress 5% (2MB)
54 12:28:43.395115 progress 10% (4MB)
55 12:28:43.407352 progress 15% (6MB)
56 12:28:43.419525 progress 20% (8MB)
57 12:28:43.431710 progress 25% (10MB)
58 12:28:43.443618 progress 30% (13MB)
59 12:28:43.455433 progress 35% (15MB)
60 12:28:43.467421 progress 40% (17MB)
61 12:28:43.479275 progress 45% (19MB)
62 12:28:43.491264 progress 50% (21MB)
63 12:28:43.503138 progress 55% (24MB)
64 12:28:43.515651 progress 60% (26MB)
65 12:28:43.527897 progress 65% (28MB)
66 12:28:43.540040 progress 70% (30MB)
67 12:28:43.552235 progress 75% (32MB)
68 12:28:43.564098 progress 80% (34MB)
69 12:28:43.576568 progress 85% (37MB)
70 12:28:43.589148 progress 90% (39MB)
71 12:28:43.601298 progress 95% (41MB)
72 12:28:43.612935 progress 100% (43MB)
73 12:28:43.613113 43MB downloaded in 0.24s (179.35MB/s)
74 12:28:43.613292 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:28:43.613545 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:28:43.613648 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:28:43.613737 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:28:43.613875 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:28:43.613947 saving as /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/dtb/mt8192-asurada-spherion-r0.dtb
81 12:28:43.614010 total size: 46924 (0MB)
82 12:28:43.614084 No compression specified
83 12:28:43.615353 progress 69% (0MB)
84 12:28:43.615642 progress 100% (0MB)
85 12:28:43.615816 0MB downloaded in 0.00s (24.82MB/s)
86 12:28:43.615985 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:28:43.616224 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:28:43.616323 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:28:43.616445 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:28:43.616595 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:28:43.616692 saving as /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/modules/modules.tar
93 12:28:43.616787 total size: 8539116 (8MB)
94 12:28:43.616886 Using unxz to decompress xz
95 12:28:43.621033 progress 0% (0MB)
96 12:28:43.642760 progress 5% (0MB)
97 12:28:43.668437 progress 10% (0MB)
98 12:28:43.692521 progress 15% (1MB)
99 12:28:43.721845 progress 20% (1MB)
100 12:28:43.749838 progress 25% (2MB)
101 12:28:43.775913 progress 30% (2MB)
102 12:28:43.802574 progress 35% (2MB)
103 12:28:43.828651 progress 40% (3MB)
104 12:28:43.853200 progress 45% (3MB)
105 12:28:43.879327 progress 50% (4MB)
106 12:28:43.904049 progress 55% (4MB)
107 12:28:43.930389 progress 60% (4MB)
108 12:28:43.957087 progress 65% (5MB)
109 12:28:43.983699 progress 70% (5MB)
110 12:28:44.010975 progress 75% (6MB)
111 12:28:44.042605 progress 80% (6MB)
112 12:28:44.065973 progress 85% (6MB)
113 12:28:44.091448 progress 90% (7MB)
114 12:28:44.116603 progress 95% (7MB)
115 12:28:44.142815 progress 100% (8MB)
116 12:28:44.148950 8MB downloaded in 0.53s (15.30MB/s)
117 12:28:44.149266 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:28:44.149548 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:28:44.149657 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:28:44.149756 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:28:44.149852 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:28:44.149941 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:28:44.150302 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757
125 12:28:44.150479 makedir: /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin
126 12:28:44.150626 makedir: /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/tests
127 12:28:44.150758 makedir: /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/results
128 12:28:44.150913 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-add-keys
129 12:28:44.151094 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-add-sources
130 12:28:44.151267 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-background-process-start
131 12:28:44.151482 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-background-process-stop
132 12:28:44.151614 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-common-functions
133 12:28:44.151737 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-echo-ipv4
134 12:28:44.151889 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-install-packages
135 12:28:44.152055 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-installed-packages
136 12:28:44.152183 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-os-build
137 12:28:44.152321 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-probe-channel
138 12:28:44.152458 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-probe-ip
139 12:28:44.152588 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-target-ip
140 12:28:44.152711 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-target-mac
141 12:28:44.152870 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-target-storage
142 12:28:44.153074 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-case
143 12:28:44.153234 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-event
144 12:28:44.153410 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-feedback
145 12:28:44.153614 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-raise
146 12:28:44.153771 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-reference
147 12:28:44.153939 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-runner
148 12:28:44.154097 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-set
149 12:28:44.154305 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-test-shell
150 12:28:44.154479 Updating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-install-packages (oe)
151 12:28:44.154647 Updating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/bin/lava-installed-packages (oe)
152 12:28:44.154788 Creating /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/environment
153 12:28:44.154946 LAVA metadata
154 12:28:44.155081 - LAVA_JOB_ID=10605794
155 12:28:44.155201 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:28:44.155360 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:28:44.155511 skipped lava-vland-overlay
158 12:28:44.155618 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:28:44.155740 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:28:44.155831 skipped lava-multinode-overlay
161 12:28:44.155963 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:28:44.156148 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:28:44.156269 Loading test definitions
164 12:28:44.156402 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:28:44.156528 Using /lava-10605794 at stage 0
166 12:28:44.156992 uuid=10605794_1.5.2.3.1 testdef=None
167 12:28:44.157104 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:28:44.157230 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:28:44.157987 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:28:44.158364 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:28:44.159144 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:28:44.159469 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:28:44.160131 runner path: /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/0/tests/0_cros-ec test_uuid 10605794_1.5.2.3.1
176 12:28:44.160321 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:28:44.160678 Creating lava-test-runner.conf files
179 12:28:44.160772 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605794/lava-overlay-gk9m3757/lava-10605794/0 for stage 0
180 12:28:44.160903 - 0_cros-ec
181 12:28:44.161034 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:28:44.161164 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:28:44.170118 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:28:44.170292 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:28:44.170425 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:28:44.170560 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:28:44.170695 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:28:45.207193 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:28:45.207676 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:28:45.207863 extracting modules file /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605794/extract-overlay-ramdisk-i6guqfxb/ramdisk
191 12:28:45.443545 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:28:45.443722 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:28:45.443819 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605794/compress-overlay-3uw7t876/overlay-1.5.2.4.tar.gz to ramdisk
194 12:28:45.443892 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605794/compress-overlay-3uw7t876/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605794/extract-overlay-ramdisk-i6guqfxb/ramdisk
195 12:28:45.450609 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:28:45.450734 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:28:45.450834 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:28:45.450926 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:28:45.451010 Building ramdisk /var/lib/lava/dispatcher/tmp/10605794/extract-overlay-ramdisk-i6guqfxb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605794/extract-overlay-ramdisk-i6guqfxb/ramdisk
200 12:28:46.458543 >> 269476 blocks
201 12:28:51.375568 rename /var/lib/lava/dispatcher/tmp/10605794/extract-overlay-ramdisk-i6guqfxb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/ramdisk/ramdisk.cpio.gz
202 12:28:51.376043 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 12:28:51.376235 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 12:28:51.376399 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 12:28:51.376572 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/kernel/Image'
206 12:29:04.495172 Returned 0 in 13 seconds
207 12:29:04.595774 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/kernel/image.itb
208 12:29:05.317785 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:29:05.318144 output: Created: Tue Jun 6 13:29:05 2023
210 12:29:05.318226 output: Image 0 (kernel-1)
211 12:29:05.318297 output: Description:
212 12:29:05.318365 output: Created: Tue Jun 6 13:29:05 2023
213 12:29:05.318427 output: Type: Kernel Image
214 12:29:05.318487 output: Compression: lzma compressed
215 12:29:05.318551 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
216 12:29:05.318612 output: Architecture: AArch64
217 12:29:05.318672 output: OS: Linux
218 12:29:05.318734 output: Load Address: 0x00000000
219 12:29:05.318795 output: Entry Point: 0x00000000
220 12:29:05.318852 output: Hash algo: crc32
221 12:29:05.318907 output: Hash value: a26c3f91
222 12:29:05.318962 output: Image 1 (fdt-1)
223 12:29:05.319020 output: Description: mt8192-asurada-spherion-r0
224 12:29:05.319077 output: Created: Tue Jun 6 13:29:05 2023
225 12:29:05.319132 output: Type: Flat Device Tree
226 12:29:05.319187 output: Compression: uncompressed
227 12:29:05.319242 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:29:05.319300 output: Architecture: AArch64
229 12:29:05.319368 output: Hash algo: crc32
230 12:29:05.319427 output: Hash value: 1df858fa
231 12:29:05.319485 output: Image 2 (ramdisk-1)
232 12:29:05.319541 output: Description: unavailable
233 12:29:05.319596 output: Created: Tue Jun 6 13:29:05 2023
234 12:29:05.319651 output: Type: RAMDisk Image
235 12:29:05.319705 output: Compression: Unknown Compression
236 12:29:05.319763 output: Data Size: 47376913 Bytes = 46266.52 KiB = 45.18 MiB
237 12:29:05.319818 output: Architecture: AArch64
238 12:29:05.319871 output: OS: Linux
239 12:29:05.319925 output: Load Address: unavailable
240 12:29:05.319983 output: Entry Point: unavailable
241 12:29:05.320039 output: Hash algo: crc32
242 12:29:05.320093 output: Hash value: 9a0d908e
243 12:29:05.320147 output: Default Configuration: 'conf-1'
244 12:29:05.320201 output: Configuration 0 (conf-1)
245 12:29:05.320257 output: Description: mt8192-asurada-spherion-r0
246 12:29:05.320311 output: Kernel: kernel-1
247 12:29:05.320366 output: Init Ramdisk: ramdisk-1
248 12:29:05.320419 output: FDT: fdt-1
249 12:29:05.320476 output: Loadables: kernel-1
250 12:29:05.320532 output:
251 12:29:05.320731 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:29:05.320832 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:29:05.320942 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 12:29:05.321038 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 12:29:05.321122 No LXC device requested
256 12:29:05.321204 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:29:05.321290 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 12:29:05.321372 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:29:05.321446 Checking files for TFTP limit of 4294967296 bytes.
260 12:29:05.321946 end: 1 tftp-deploy (duration 00:00:22) [common]
261 12:29:05.322057 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:29:05.322152 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:29:05.322282 substitutions:
264 12:29:05.322353 - {DTB}: 10605794/tftp-deploy-_yyx4mc8/dtb/mt8192-asurada-spherion-r0.dtb
265 12:29:05.322422 - {INITRD}: 10605794/tftp-deploy-_yyx4mc8/ramdisk/ramdisk.cpio.gz
266 12:29:05.322486 - {KERNEL}: 10605794/tftp-deploy-_yyx4mc8/kernel/Image
267 12:29:05.322546 - {LAVA_MAC}: None
268 12:29:05.322605 - {PRESEED_CONFIG}: None
269 12:29:05.322666 - {PRESEED_LOCAL}: None
270 12:29:05.322723 - {RAMDISK}: 10605794/tftp-deploy-_yyx4mc8/ramdisk/ramdisk.cpio.gz
271 12:29:05.322780 - {ROOT_PART}: None
272 12:29:05.322836 - {ROOT}: None
273 12:29:05.322895 - {SERVER_IP}: 192.168.201.1
274 12:29:05.322952 - {TEE}: None
275 12:29:05.323007 Parsed boot commands:
276 12:29:05.323064 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:29:05.323246 Parsed boot commands: tftpboot 192.168.201.1 10605794/tftp-deploy-_yyx4mc8/kernel/image.itb 10605794/tftp-deploy-_yyx4mc8/kernel/cmdline
278 12:29:05.323337 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:29:05.323440 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:29:05.323533 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:29:05.323619 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:29:05.323693 Not connected, no need to disconnect.
283 12:29:05.323769 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:29:05.323853 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:29:05.323926 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 12:29:05.327174 Setting prompt string to ['lava-test: # ']
287 12:29:05.327568 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:29:05.327706 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:29:05.327824 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:29:05.327944 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:29:05.328269 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 12:29:10.472539 >> Command sent successfully.
293 12:29:10.474964 Returned 0 in 5 seconds
294 12:29:10.575343 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:29:10.575976 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:29:10.576092 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:29:10.576201 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:29:10.576283 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:29:10.576374 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:29:10.576753 [Enter `^Ec?' for help]
302 12:29:10.749309
303 12:29:10.749468
304 12:29:10.749576 F0: 102B 0000
305 12:29:10.749661
306 12:29:10.749741 F3: 1001 0000 [0200]
307 12:29:10.752729
308 12:29:10.752816 F3: 1001 0000
309 12:29:10.752927
310 12:29:10.753024 F7: 102D 0000
311 12:29:10.753118
312 12:29:10.755899 F1: 0000 0000
313 12:29:10.756010
314 12:29:10.756095 V0: 0000 0000 [0001]
315 12:29:10.756197
316 12:29:10.759732 00: 0007 8000
317 12:29:10.759838
318 12:29:10.759946 01: 0000 0000
319 12:29:10.760042
320 12:29:10.762931 BP: 0C00 0209 [0000]
321 12:29:10.763005
322 12:29:10.763112 G0: 1182 0000
323 12:29:10.763211
324 12:29:10.766761 EC: 0000 0021 [4000]
325 12:29:10.766838
326 12:29:10.766938 S7: 0000 0000 [0000]
327 12:29:10.767042
328 12:29:10.770007 CC: 0000 0000 [0001]
329 12:29:10.770111
330 12:29:10.770218 T0: 0000 0040 [010F]
331 12:29:10.770320
332 12:29:10.770420 Jump to BL
333 12:29:10.770498
334 12:29:10.796281
335 12:29:10.796377
336 12:29:10.796466
337 12:29:10.803646 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:29:10.806760 ARM64: Exception handlers installed.
339 12:29:10.810501 ARM64: Testing exception
340 12:29:10.813486 ARM64: Done test exception
341 12:29:10.820570 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:29:10.830715 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:29:10.837253 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:29:10.847253 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:29:10.853842 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:29:10.863935 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:29:10.874339 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:29:10.881045 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:29:10.899523 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:29:10.902725 WDT: Last reset was cold boot
351 12:29:10.906100 SPI1(PAD0) initialized at 2873684 Hz
352 12:29:10.909320 SPI5(PAD0) initialized at 992727 Hz
353 12:29:10.912625 VBOOT: Loading verstage.
354 12:29:10.919057 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:29:10.922837 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:29:10.925885 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:29:10.929233 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:29:10.936884 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:29:10.943540 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:29:10.954253 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 12:29:10.954350
362 12:29:10.954425
363 12:29:10.964115 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:29:10.967290 ARM64: Exception handlers installed.
365 12:29:10.970489 ARM64: Testing exception
366 12:29:10.970587 ARM64: Done test exception
367 12:29:10.977604 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:29:10.980941 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:29:10.996240 Probing TPM: . done!
370 12:29:10.996328 TPM ready after 0 ms
371 12:29:11.003259 Connected to device vid:did:rid of 1ae0:0028:00
372 12:29:11.010225 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:29:11.068613 Initialized TPM device CR50 revision 0
374 12:29:11.080291 tlcl_send_startup: Startup return code is 0
375 12:29:11.080422 TPM: setup succeeded
376 12:29:11.091645 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:29:11.100103 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:29:11.112324 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:29:11.122394 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:29:11.125614 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:29:11.130050 in-header: 03 07 00 00 08 00 00 00
382 12:29:11.133212 in-data: aa e4 47 04 13 02 00 00
383 12:29:11.137036 Chrome EC: UHEPI supported
384 12:29:11.144605 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:29:11.148045 in-header: 03 ad 00 00 08 00 00 00
386 12:29:11.151925 in-data: 00 20 20 08 00 00 00 00
387 12:29:11.152032 Phase 1
388 12:29:11.155274 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:29:11.162537 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:29:11.166619 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:29:11.169932 Recovery requested (1009000e)
392 12:29:11.179034 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:29:11.184916 tlcl_extend: response is 0
394 12:29:11.195453 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:29:11.200805 tlcl_extend: response is 0
396 12:29:11.208284 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:29:11.228152 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 12:29:11.234349 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:29:11.234436
400 12:29:11.234504
401 12:29:11.245679 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:29:11.249479 ARM64: Exception handlers installed.
403 12:29:11.249595 ARM64: Testing exception
404 12:29:11.252659 ARM64: Done test exception
405 12:29:11.273966 pmic_efuse_setting: Set efuses in 11 msecs
406 12:29:11.277060 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:29:11.284317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:29:11.287596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:29:11.290793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:29:11.298179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:29:11.301485 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:29:11.308813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:29:11.312247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:29:11.316253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:29:11.319385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:29:11.327081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:29:11.330403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:29:11.334447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:29:11.337726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:29:11.345169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:29:11.353261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:29:11.356402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:29:11.364229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:29:11.367506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:29:11.374951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:29:11.378954 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:29:11.385656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:29:11.389525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:29:11.396920 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:29:11.401069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:29:11.408278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:29:11.411673 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:29:11.419521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:29:11.422907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:29:11.426613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:29:11.434145 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:29:11.437416 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:29:11.440769 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:29:11.448194 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:29:11.451864 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:29:11.455470 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:29:11.463009 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:29:11.466862 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:29:11.474323 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:29:11.477573 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:29:11.481579 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:29:11.485302 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:29:11.488543 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:29:11.495729 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:29:11.499879 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:29:11.503276 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:29:11.507310 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:29:11.510856 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:29:11.514602 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:29:11.521973 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:29:11.525195 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:29:11.529248 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:29:11.536667 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:29:11.543988 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:29:11.551422 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:29:11.558719 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:29:11.566207 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:29:11.569765 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:29:11.577023 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:29:11.580528 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:29:11.587861 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
467 12:29:11.591886 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:29:11.595887 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:29:11.599839 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:29:11.610851 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 12:29:11.620250 [RTC]rtc_get_frequency_meter,154: input=23, output=977
472 12:29:11.630145 [RTC]rtc_get_frequency_meter,154: input=19, output=885
473 12:29:11.639961 [RTC]rtc_get_frequency_meter,154: input=17, output=838
474 12:29:11.648731 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 12:29:11.658673 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 12:29:11.668454 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 12:29:11.672305 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 12:29:11.675975 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 12:29:11.683323 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:29:11.687126 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:29:11.690871 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:29:11.693950 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:29:11.697573 ADC[4]: Raw value=901328 ID=7
484 12:29:11.701343 ADC[3]: Raw value=213336 ID=1
485 12:29:11.701423 RAM Code: 0x71
486 12:29:11.705192 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:29:11.709143 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:29:11.719915 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:29:11.723922 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:29:11.727148 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:29:11.731144 in-header: 03 07 00 00 08 00 00 00
492 12:29:11.735099 in-data: aa e4 47 04 13 02 00 00
493 12:29:11.739076 Chrome EC: UHEPI supported
494 12:29:11.745719 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:29:11.749727 in-header: 03 ed 00 00 08 00 00 00
496 12:29:11.752946 in-data: 80 20 60 08 00 00 00 00
497 12:29:11.756924 MRC: failed to locate region type 0.
498 12:29:11.764327 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:29:11.764439 DRAM-K: Running full calibration
500 12:29:11.771628 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:29:11.775655 header.status = 0x0
502 12:29:11.775736 header.version = 0x6 (expected: 0x6)
503 12:29:11.779297 header.size = 0xd00 (expected: 0xd00)
504 12:29:11.782801 header.flags = 0x0
505 12:29:11.789719 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:29:11.806436 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
507 12:29:11.814068 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:29:11.814179 dram_init: ddr_geometry: 2
509 12:29:11.817974 [EMI] MDL number = 2
510 12:29:11.822005 [EMI] Get MDL freq = 0
511 12:29:11.822079 dram_init: ddr_type: 0
512 12:29:11.825397 is_discrete_lpddr4: 1
513 12:29:11.825468 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:29:11.829455
515 12:29:11.829529
516 12:29:11.829616 [Bian_co] ETT version 0.0.0.1
517 12:29:11.836560 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:29:11.836634
519 12:29:11.839830 dramc_set_vcore_voltage set vcore to 650000
520 12:29:11.839931 Read voltage for 800, 4
521 12:29:11.843729 Vio18 = 0
522 12:29:11.843807 Vcore = 650000
523 12:29:11.843872 Vdram = 0
524 12:29:11.843932 Vddq = 0
525 12:29:11.847604 Vmddr = 0
526 12:29:11.847681 dram_init: config_dvfs: 1
527 12:29:11.854882 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:29:11.858904 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:29:11.862314 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 12:29:11.865480 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 12:29:11.868757 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 12:29:11.872701 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 12:29:11.875919 MEM_TYPE=3, freq_sel=18
534 12:29:11.879274 sv_algorithm_assistance_LP4_1600
535 12:29:11.882438 ============ PULL DRAM RESETB DOWN ============
536 12:29:11.888886 ========== PULL DRAM RESETB DOWN end =========
537 12:29:11.892163 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:29:11.895926 ===================================
539 12:29:11.899138 LPDDR4 DRAM CONFIGURATION
540 12:29:11.902127 ===================================
541 12:29:11.902240 EX_ROW_EN[0] = 0x0
542 12:29:11.905472 EX_ROW_EN[1] = 0x0
543 12:29:11.905549 LP4Y_EN = 0x0
544 12:29:11.909062 WORK_FSP = 0x0
545 12:29:11.909147 WL = 0x2
546 12:29:11.912288 RL = 0x2
547 12:29:11.912373 BL = 0x2
548 12:29:11.915977 RPST = 0x0
549 12:29:11.916061 RD_PRE = 0x0
550 12:29:11.919060 WR_PRE = 0x1
551 12:29:11.919171 WR_PST = 0x0
552 12:29:11.922189 DBI_WR = 0x0
553 12:29:11.922275 DBI_RD = 0x0
554 12:29:11.925591 OTF = 0x1
555 12:29:11.928858 ===================================
556 12:29:11.932181 ===================================
557 12:29:11.932269 ANA top config
558 12:29:11.935498 ===================================
559 12:29:11.938810 DLL_ASYNC_EN = 0
560 12:29:11.942028 ALL_SLAVE_EN = 1
561 12:29:11.945911 NEW_RANK_MODE = 1
562 12:29:11.946021 DLL_IDLE_MODE = 1
563 12:29:11.949166 LP45_APHY_COMB_EN = 1
564 12:29:11.952479 TX_ODT_DIS = 1
565 12:29:11.955944 NEW_8X_MODE = 1
566 12:29:11.959289 ===================================
567 12:29:11.962487 ===================================
568 12:29:11.965809 data_rate = 1600
569 12:29:11.965895 CKR = 1
570 12:29:11.968960 DQ_P2S_RATIO = 8
571 12:29:11.972810 ===================================
572 12:29:11.975595 CA_P2S_RATIO = 8
573 12:29:11.978969 DQ_CA_OPEN = 0
574 12:29:11.982297 DQ_SEMI_OPEN = 0
575 12:29:11.985607 CA_SEMI_OPEN = 0
576 12:29:11.985710 CA_FULL_RATE = 0
577 12:29:11.989484 DQ_CKDIV4_EN = 1
578 12:29:11.992447 CA_CKDIV4_EN = 1
579 12:29:11.995741 CA_PREDIV_EN = 0
580 12:29:11.999083 PH8_DLY = 0
581 12:29:11.999187 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:29:12.002822 DQ_AAMCK_DIV = 4
583 12:29:12.005890 CA_AAMCK_DIV = 4
584 12:29:12.009214 CA_ADMCK_DIV = 4
585 12:29:12.012345 DQ_TRACK_CA_EN = 0
586 12:29:12.015701 CA_PICK = 800
587 12:29:12.018995 CA_MCKIO = 800
588 12:29:12.019075 MCKIO_SEMI = 0
589 12:29:12.022816 PLL_FREQ = 3068
590 12:29:12.026631 DQ_UI_PI_RATIO = 32
591 12:29:12.030639 CA_UI_PI_RATIO = 0
592 12:29:12.033852 ===================================
593 12:29:12.033934 ===================================
594 12:29:12.037789 memory_type:LPDDR4
595 12:29:12.041068 GP_NUM : 10
596 12:29:12.041150 SRAM_EN : 1
597 12:29:12.045097 MD32_EN : 0
598 12:29:12.048448 ===================================
599 12:29:12.048528 [ANA_INIT] >>>>>>>>>>>>>>
600 12:29:12.052907 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:29:12.056132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:29:12.060127 ===================================
603 12:29:12.063480 data_rate = 1600,PCW = 0X7600
604 12:29:12.066878 ===================================
605 12:29:12.069941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:29:12.073196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:29:12.079808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:29:12.083137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:29:12.086450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:29:12.089702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:29:12.093583 [ANA_INIT] flow start
612 12:29:12.096636 [ANA_INIT] PLL >>>>>>>>
613 12:29:12.096710 [ANA_INIT] PLL <<<<<<<<
614 12:29:12.099929 [ANA_INIT] MIDPI >>>>>>>>
615 12:29:12.103226 [ANA_INIT] MIDPI <<<<<<<<
616 12:29:12.106423 [ANA_INIT] DLL >>>>>>>>
617 12:29:12.106504 [ANA_INIT] flow end
618 12:29:12.109728 ============ LP4 DIFF to SE enter ============
619 12:29:12.116792 ============ LP4 DIFF to SE exit ============
620 12:29:12.116874 [ANA_INIT] <<<<<<<<<<<<<
621 12:29:12.119862 [Flow] Enable top DCM control >>>>>
622 12:29:12.123108 [Flow] Enable top DCM control <<<<<
623 12:29:12.126842 Enable DLL master slave shuffle
624 12:29:12.133514 ==============================================================
625 12:29:12.133607 Gating Mode config
626 12:29:12.139955 ==============================================================
627 12:29:12.140037 Config description:
628 12:29:12.150566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:29:12.156980 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:29:12.163482 SELPH_MODE 0: By rank 1: By Phase
631 12:29:12.166709 ==============================================================
632 12:29:12.170662 GAT_TRACK_EN = 1
633 12:29:12.173323 RX_GATING_MODE = 2
634 12:29:12.176585 RX_GATING_TRACK_MODE = 2
635 12:29:12.179996 SELPH_MODE = 1
636 12:29:12.183282 PICG_EARLY_EN = 1
637 12:29:12.186514 VALID_LAT_VALUE = 1
638 12:29:12.193129 ==============================================================
639 12:29:12.197038 Enter into Gating configuration >>>>
640 12:29:12.200288 Exit from Gating configuration <<<<
641 12:29:12.203393 Enter into DVFS_PRE_config >>>>>
642 12:29:12.213377 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:29:12.216708 Exit from DVFS_PRE_config <<<<<
644 12:29:12.220322 Enter into PICG configuration >>>>
645 12:29:12.223637 Exit from PICG configuration <<<<
646 12:29:12.223752 [RX_INPUT] configuration >>>>>
647 12:29:12.226700 [RX_INPUT] configuration <<<<<
648 12:29:12.233493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:29:12.236720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:29:12.244464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:29:12.250488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:29:12.257105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:29:12.264220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:29:12.267504 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:29:12.270766 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:29:12.274099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:29:12.280697 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:29:12.283981 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:29:12.287254 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:29:12.291184 ===================================
661 12:29:12.293872 LPDDR4 DRAM CONFIGURATION
662 12:29:12.297147 ===================================
663 12:29:12.297224 EX_ROW_EN[0] = 0x0
664 12:29:12.301122 EX_ROW_EN[1] = 0x0
665 12:29:12.304468 LP4Y_EN = 0x0
666 12:29:12.304539 WORK_FSP = 0x0
667 12:29:12.307760 WL = 0x2
668 12:29:12.307828 RL = 0x2
669 12:29:12.310399 BL = 0x2
670 12:29:12.310472 RPST = 0x0
671 12:29:12.313746 RD_PRE = 0x0
672 12:29:12.313818 WR_PRE = 0x1
673 12:29:12.317090 WR_PST = 0x0
674 12:29:12.317166 DBI_WR = 0x0
675 12:29:12.320375 DBI_RD = 0x0
676 12:29:12.320444 OTF = 0x1
677 12:29:12.323774 ===================================
678 12:29:12.327775 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:29:12.333914 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:29:12.337484 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:29:12.340770 ===================================
682 12:29:12.343891 LPDDR4 DRAM CONFIGURATION
683 12:29:12.347036 ===================================
684 12:29:12.347111 EX_ROW_EN[0] = 0x10
685 12:29:12.350789 EX_ROW_EN[1] = 0x0
686 12:29:12.354054 LP4Y_EN = 0x0
687 12:29:12.354136 WORK_FSP = 0x0
688 12:29:12.357341 WL = 0x2
689 12:29:12.357423 RL = 0x2
690 12:29:12.360637 BL = 0x2
691 12:29:12.360718 RPST = 0x0
692 12:29:12.363831 RD_PRE = 0x0
693 12:29:12.363905 WR_PRE = 0x1
694 12:29:12.367029 WR_PST = 0x0
695 12:29:12.367113 DBI_WR = 0x0
696 12:29:12.370266 DBI_RD = 0x0
697 12:29:12.370340 OTF = 0x1
698 12:29:12.373569 ===================================
699 12:29:12.380098 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:29:12.384718 nWR fixed to 40
701 12:29:12.387924 [ModeRegInit_LP4] CH0 RK0
702 12:29:12.387997 [ModeRegInit_LP4] CH0 RK1
703 12:29:12.391353 [ModeRegInit_LP4] CH1 RK0
704 12:29:12.394634 [ModeRegInit_LP4] CH1 RK1
705 12:29:12.394720 match AC timing 13
706 12:29:12.401146 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:29:12.404479 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:29:12.407854 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:29:12.414279 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:29:12.417536 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:29:12.417633 [EMI DOE] emi_dcm 0
712 12:29:12.424201 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:29:12.424301 ==
714 12:29:12.427518 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:29:12.430938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:29:12.431020 ==
717 12:29:12.438102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:29:12.441168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:29:12.451915 [CA 0] Center 37 (7~68) winsize 62
720 12:29:12.455061 [CA 1] Center 37 (6~68) winsize 63
721 12:29:12.458273 [CA 2] Center 35 (5~66) winsize 62
722 12:29:12.462001 [CA 3] Center 34 (4~65) winsize 62
723 12:29:12.465294 [CA 4] Center 34 (3~65) winsize 63
724 12:29:12.468580 [CA 5] Center 33 (3~64) winsize 62
725 12:29:12.468665
726 12:29:12.471762 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:29:12.471847
728 12:29:12.475509 [CATrainingPosCal] consider 1 rank data
729 12:29:12.478757 u2DelayCellTimex100 = 270/100 ps
730 12:29:12.481977 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:29:12.485217 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 12:29:12.491924 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 12:29:12.495240 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:29:12.498576 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 12:29:12.501861 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:29:12.501950
737 12:29:12.505146 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:29:12.505230
739 12:29:12.508452 [CBTSetCACLKResult] CA Dly = 33
740 12:29:12.508536 CS Dly: 5 (0~36)
741 12:29:12.508604 ==
742 12:29:12.512302 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:29:12.518690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:29:12.518776 ==
745 12:29:12.522004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:29:12.528624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:29:12.537875 [CA 0] Center 37 (6~68) winsize 63
748 12:29:12.541336 [CA 1] Center 37 (6~68) winsize 63
749 12:29:12.544512 [CA 2] Center 35 (4~66) winsize 63
750 12:29:12.548334 [CA 3] Center 35 (4~66) winsize 63
751 12:29:12.551555 [CA 4] Center 34 (4~65) winsize 62
752 12:29:12.554555 [CA 5] Center 33 (3~64) winsize 62
753 12:29:12.554640
754 12:29:12.558379 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:29:12.558465
756 12:29:12.561749 [CATrainingPosCal] consider 2 rank data
757 12:29:12.564940 u2DelayCellTimex100 = 270/100 ps
758 12:29:12.568088 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:29:12.571260 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 12:29:12.578279 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 12:29:12.581307 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:29:12.584691 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
763 12:29:12.588010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:29:12.588094
765 12:29:12.591289 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:29:12.591398
767 12:29:12.594628 [CBTSetCACLKResult] CA Dly = 33
768 12:29:12.594712 CS Dly: 5 (0~37)
769 12:29:12.594780
770 12:29:12.597903 ----->DramcWriteLeveling(PI) begin...
771 12:29:12.601218 ==
772 12:29:12.605086 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:29:12.609109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:29:12.609195 ==
775 12:29:12.612428 Write leveling (Byte 0): 29 => 29
776 12:29:12.612513 Write leveling (Byte 1): 29 => 29
777 12:29:12.616361 DramcWriteLeveling(PI) end<-----
778 12:29:12.616445
779 12:29:12.616513 ==
780 12:29:12.619354 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:29:12.623136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:29:12.626380 ==
783 12:29:12.626464 [Gating] SW mode calibration
784 12:29:12.633656 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:29:12.640891 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:29:12.644224 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:29:12.647469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 12:29:12.653942 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 12:29:12.657222 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:29:12.660385 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:29:12.667352 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:29:12.670517 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:29:12.673782 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:29:12.680922 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:29:12.684030 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:29:12.687290 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:29:12.691146 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:29:12.697093 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:29:12.701029 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:29:12.704207 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:29:12.710729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:29:12.714058 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:29:12.717348 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:29:12.723794 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 12:29:12.727594 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 12:29:12.730880 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:29:12.737392 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:29:12.741057 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:29:12.744424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:29:12.750978 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:29:12.754405 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:29:12.757527 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
813 12:29:12.764203 0 9 12 | B1->B0 | 2726 2f2f | 1 0 | (0 0) (0 0)
814 12:29:12.767384 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
815 12:29:12.770984 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:29:12.774131 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:29:12.781170 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:29:12.784323 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:29:12.787496 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:29:12.794757 0 10 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
821 12:29:12.797974 0 10 12 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
822 12:29:12.801382 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:29:12.807999 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:29:12.811212 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:29:12.814588 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:29:12.821169 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:29:12.824566 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:29:12.827961 0 11 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
829 12:29:12.834425 0 11 12 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
830 12:29:12.837848 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:29:12.841124 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:29:12.847608 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:29:12.850993 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:29:12.854252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:29:12.857764 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:29:12.864556 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 12:29:12.867877 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:29:12.871221 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:29:12.877428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:29:12.881126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:29:12.884297 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:29:12.890927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:29:12.894159 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:29:12.898051 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:29:12.904806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:29:12.908009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:29:12.911336 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:29:12.917976 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:29:12.921233 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:29:12.924455 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:29:12.927851 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:29:12.934374 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:29:12.937584 Total UI for P1: 0, mck2ui 16
854 12:29:12.940860 best dqsien dly found for B0: ( 0, 14, 6)
855 12:29:12.944151 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:29:12.947437 Total UI for P1: 0, mck2ui 16
857 12:29:12.950928 best dqsien dly found for B1: ( 0, 14, 8)
858 12:29:12.954202 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 12:29:12.957532 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:29:12.957614
861 12:29:12.960905 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 12:29:12.964154 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:29:12.967950 [Gating] SW calibration Done
864 12:29:12.968025 ==
865 12:29:12.970648 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:29:12.977944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:29:12.978023 ==
868 12:29:12.978089 RX Vref Scan: 0
869 12:29:12.978151
870 12:29:12.980714 RX Vref 0 -> 0, step: 1
871 12:29:12.980783
872 12:29:12.984633 RX Delay -130 -> 252, step: 16
873 12:29:12.987786 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 12:29:12.990883 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 12:29:12.994717 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 12:29:12.997781 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 12:29:13.004014 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 12:29:13.007914 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 12:29:13.011186 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 12:29:13.014619 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 12:29:13.017934 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 12:29:13.024581 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 12:29:13.027917 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 12:29:13.031234 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 12:29:13.034550 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 12:29:13.037853 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 12:29:13.044223 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 12:29:13.047525 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 12:29:13.047679 ==
890 12:29:13.050873 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:29:13.054155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:29:13.054345 ==
893 12:29:13.058088 DQS Delay:
894 12:29:13.058205 DQS0 = 0, DQS1 = 0
895 12:29:13.058303 DQM Delay:
896 12:29:13.060902 DQM0 = 86, DQM1 = 78
897 12:29:13.061018 DQ Delay:
898 12:29:13.064946 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 12:29:13.068198 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 12:29:13.070874 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 12:29:13.074187 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
902 12:29:13.074275
903 12:29:13.074371
904 12:29:13.074462 ==
905 12:29:13.077495 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:29:13.084322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:29:13.084416 ==
908 12:29:13.084483
909 12:29:13.084544
910 12:29:13.084603 TX Vref Scan disable
911 12:29:13.088285 == TX Byte 0 ==
912 12:29:13.091603 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 12:29:13.094785 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 12:29:13.097839 == TX Byte 1 ==
915 12:29:13.101416 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 12:29:13.107695 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 12:29:13.107776 ==
918 12:29:13.111332 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:29:13.114279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:29:13.114360 ==
921 12:29:13.127229 TX Vref=22, minBit 3, minWin=27, winSum=439
922 12:29:13.130543 TX Vref=24, minBit 3, minWin=27, winSum=443
923 12:29:13.133886 TX Vref=26, minBit 5, minWin=27, winSum=444
924 12:29:13.137139 TX Vref=28, minBit 3, minWin=27, winSum=451
925 12:29:13.140408 TX Vref=30, minBit 0, minWin=28, winSum=453
926 12:29:13.143641 TX Vref=32, minBit 2, minWin=28, winSum=452
927 12:29:13.150030 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
928 12:29:13.150105
929 12:29:13.154019 Final TX Range 1 Vref 30
930 12:29:13.154087
931 12:29:13.154149 ==
932 12:29:13.156736 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:29:13.160657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:29:13.160739 ==
935 12:29:13.160805
936 12:29:13.163322
937 12:29:13.163399 TX Vref Scan disable
938 12:29:13.166680 == TX Byte 0 ==
939 12:29:13.170433 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 12:29:13.173877 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 12:29:13.177092 == TX Byte 1 ==
942 12:29:13.180304 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 12:29:13.183742 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 12:29:13.187033
945 12:29:13.187147 [DATLAT]
946 12:29:13.187244 Freq=800, CH0 RK0
947 12:29:13.187336
948 12:29:13.190351 DATLAT Default: 0xa
949 12:29:13.190462 0, 0xFFFF, sum = 0
950 12:29:13.193620 1, 0xFFFF, sum = 0
951 12:29:13.193733 2, 0xFFFF, sum = 0
952 12:29:13.196849 3, 0xFFFF, sum = 0
953 12:29:13.196969 4, 0xFFFF, sum = 0
954 12:29:13.200273 5, 0xFFFF, sum = 0
955 12:29:13.200384 6, 0xFFFF, sum = 0
956 12:29:13.203425 7, 0xFFFF, sum = 0
957 12:29:13.206752 8, 0xFFFF, sum = 0
958 12:29:13.206867 9, 0x0, sum = 1
959 12:29:13.206970 10, 0x0, sum = 2
960 12:29:13.210316 11, 0x0, sum = 3
961 12:29:13.210434 12, 0x0, sum = 4
962 12:29:13.213249 best_step = 10
963 12:29:13.213361
964 12:29:13.213457 ==
965 12:29:13.216997 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:29:13.220127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:29:13.220240 ==
968 12:29:13.223730 RX Vref Scan: 1
969 12:29:13.223840
970 12:29:13.223939 Set Vref Range= 32 -> 127
971 12:29:13.224032
972 12:29:13.227157 RX Vref 32 -> 127, step: 1
973 12:29:13.227274
974 12:29:13.230240 RX Delay -95 -> 252, step: 8
975 12:29:13.230357
976 12:29:13.233436 Set Vref, RX VrefLevel [Byte0]: 32
977 12:29:13.236646 [Byte1]: 32
978 12:29:13.236725
979 12:29:13.240623 Set Vref, RX VrefLevel [Byte0]: 33
980 12:29:13.244009 [Byte1]: 33
981 12:29:13.247226
982 12:29:13.247321 Set Vref, RX VrefLevel [Byte0]: 34
983 12:29:13.250451 [Byte1]: 34
984 12:29:13.255088
985 12:29:13.255164 Set Vref, RX VrefLevel [Byte0]: 35
986 12:29:13.258403 [Byte1]: 35
987 12:29:13.262350
988 12:29:13.262427 Set Vref, RX VrefLevel [Byte0]: 36
989 12:29:13.265713 [Byte1]: 36
990 12:29:13.270237
991 12:29:13.270315 Set Vref, RX VrefLevel [Byte0]: 37
992 12:29:13.273704 [Byte1]: 37
993 12:29:13.277552
994 12:29:13.277633 Set Vref, RX VrefLevel [Byte0]: 38
995 12:29:13.281053 [Byte1]: 38
996 12:29:13.285585
997 12:29:13.285669 Set Vref, RX VrefLevel [Byte0]: 39
998 12:29:13.288958 [Byte1]: 39
999 12:29:13.292949
1000 12:29:13.296246 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:29:13.296336 [Byte1]: 40
1002 12:29:13.300256
1003 12:29:13.300337 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:29:13.303599 [Byte1]: 41
1005 12:29:13.308313
1006 12:29:13.308397 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:29:13.311503 [Byte1]: 42
1008 12:29:13.315268
1009 12:29:13.315391 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:29:13.318537 [Byte1]: 43
1011 12:29:13.323104
1012 12:29:13.323221 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:29:13.326782 [Byte1]: 44
1014 12:29:13.331124
1015 12:29:13.331209 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:29:13.334247 [Byte1]: 45
1017 12:29:13.338534
1018 12:29:13.338620 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:29:13.341709 [Byte1]: 46
1020 12:29:13.346228
1021 12:29:13.346313 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:29:13.349407 [Byte1]: 47
1023 12:29:13.353703
1024 12:29:13.353813 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:29:13.356969 [Byte1]: 48
1026 12:29:13.360845
1027 12:29:13.360953 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:29:13.364221 [Byte1]: 49
1029 12:29:13.368966
1030 12:29:13.369081 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:29:13.372310 [Byte1]: 50
1032 12:29:13.376160
1033 12:29:13.376272 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:29:13.379498 [Byte1]: 51
1035 12:29:13.384193
1036 12:29:13.384315 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:29:13.387407 [Byte1]: 52
1038 12:29:13.391312
1039 12:29:13.391435 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:29:13.394705 [Byte1]: 53
1041 12:29:13.399221
1042 12:29:13.399337 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:29:13.402516 [Byte1]: 54
1044 12:29:13.406538
1045 12:29:13.406662 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:29:13.409844 [Byte1]: 55
1047 12:29:13.414325
1048 12:29:13.414439 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:29:13.417570 [Byte1]: 56
1050 12:29:13.422165
1051 12:29:13.422293 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:29:13.425458 [Byte1]: 57
1053 12:29:13.429309
1054 12:29:13.429410 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:29:13.433066 [Byte1]: 58
1056 12:29:13.436868
1057 12:29:13.436979 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:29:13.440195 [Byte1]: 59
1059 12:29:13.444733
1060 12:29:13.444845 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:29:13.448063 [Byte1]: 60
1062 12:29:13.452225
1063 12:29:13.452341 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:29:13.455543 [Byte1]: 61
1065 12:29:13.460084
1066 12:29:13.460202 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:29:13.463166 [Byte1]: 62
1068 12:29:13.467106
1069 12:29:13.467238 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:29:13.470487 [Byte1]: 63
1071 12:29:13.475238
1072 12:29:13.475354 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:29:13.478690 [Byte1]: 64
1074 12:29:13.482683
1075 12:29:13.482789 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:29:13.485935 [Byte1]: 65
1077 12:29:13.490165
1078 12:29:13.490277 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:29:13.493577 [Byte1]: 66
1080 12:29:13.497722
1081 12:29:13.497834 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:29:13.501134 [Byte1]: 67
1083 12:29:13.505283
1084 12:29:13.505391 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:29:13.508623 [Byte1]: 68
1086 12:29:13.513161
1087 12:29:13.513267 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:29:13.516413 [Byte1]: 69
1089 12:29:13.520474
1090 12:29:13.520574 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:29:13.523771 [Byte1]: 70
1092 12:29:13.528234
1093 12:29:13.528354 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:29:13.531428 [Byte1]: 71
1095 12:29:13.535427
1096 12:29:13.535530 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:29:13.539224 [Byte1]: 72
1098 12:29:13.543542
1099 12:29:13.543646 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:29:13.546915 [Byte1]: 73
1101 12:29:13.550649
1102 12:29:13.550752 Set Vref, RX VrefLevel [Byte0]: 74
1103 12:29:13.554445 [Byte1]: 74
1104 12:29:13.558432
1105 12:29:13.558542 Set Vref, RX VrefLevel [Byte0]: 75
1106 12:29:13.561708 [Byte1]: 75
1107 12:29:13.566308
1108 12:29:13.566419 Final RX Vref Byte 0 = 60 to rank0
1109 12:29:13.569551 Final RX Vref Byte 1 = 58 to rank0
1110 12:29:13.572855 Final RX Vref Byte 0 = 60 to rank1
1111 12:29:13.576079 Final RX Vref Byte 1 = 58 to rank1==
1112 12:29:13.579368 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 12:29:13.586026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 12:29:13.586127 ==
1115 12:29:13.586224 DQS Delay:
1116 12:29:13.586331 DQS0 = 0, DQS1 = 0
1117 12:29:13.589248 DQM Delay:
1118 12:29:13.589358 DQM0 = 87, DQM1 = 79
1119 12:29:13.593125 DQ Delay:
1120 12:29:13.596370 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1121 12:29:13.596474 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1122 12:29:13.599668 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1123 12:29:13.606213 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1124 12:29:13.606316
1125 12:29:13.606409
1126 12:29:13.612794 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1127 12:29:13.615979 CH0 RK0: MR19=606, MR18=270E
1128 12:29:13.622553 CH0_RK0: MR19=0x606, MR18=0x270E, DQSOSC=400, MR23=63, INC=92, DEC=61
1129 12:29:13.622669
1130 12:29:13.625934 ----->DramcWriteLeveling(PI) begin...
1131 12:29:13.626041 ==
1132 12:29:13.629126 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 12:29:13.632883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 12:29:13.632975 ==
1135 12:29:13.636206 Write leveling (Byte 0): 32 => 32
1136 12:29:13.639649 Write leveling (Byte 1): 28 => 28
1137 12:29:13.642695 DramcWriteLeveling(PI) end<-----
1138 12:29:13.642770
1139 12:29:13.642835 ==
1140 12:29:13.645948 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 12:29:13.649244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 12:29:13.649331 ==
1143 12:29:13.652991 [Gating] SW mode calibration
1144 12:29:13.659320 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 12:29:13.666547 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 12:29:13.669060 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 12:29:13.672374 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1148 12:29:13.679620 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1149 12:29:13.682877 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1150 12:29:13.726648 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:29:13.727283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:29:13.727550 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:29:13.727623 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:29:13.727694 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:29:13.727769 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:29:13.727833 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:29:13.727908 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:29:13.727977 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:29:13.728051 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:29:13.770634 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:29:13.770934 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:29:13.771010 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1163 12:29:13.771084 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1164 12:29:13.771145 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1165 12:29:13.771218 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:29:13.771298 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:29:13.771381 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:29:13.771444 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:29:13.771531 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:29:13.814938 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:29:13.815272 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:29:13.815377 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
1173 12:29:13.815447 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1174 12:29:13.815520 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 12:29:13.815598 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 12:29:13.815661 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 12:29:13.815733 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 12:29:13.815804 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 12:29:13.816367 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1180 12:29:13.818947 0 10 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
1181 12:29:13.822192 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1182 12:29:13.828997 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:29:13.832207 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:29:13.835465 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:29:13.842386 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:29:13.845606 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:29:13.849042 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
1188 12:29:13.852368 0 11 8 | B1->B0 | 2c2c 3e3e | 0 0 | (0 0) (0 0)
1189 12:29:13.859909 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1190 12:29:13.863606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:29:13.866694 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 12:29:13.870647 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 12:29:13.877126 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 12:29:13.880231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 12:29:13.884052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1196 12:29:13.890216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1197 12:29:13.893549 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1198 12:29:13.896880 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:29:13.903497 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:29:13.906909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:29:13.910135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:29:13.916821 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:29:13.920130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:29:13.923498 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:29:13.930302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:29:13.933562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:29:13.936770 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:29:13.943309 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:29:13.946678 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:29:13.949875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:29:13.956565 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1212 12:29:13.959830 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1213 12:29:13.963665 Total UI for P1: 0, mck2ui 16
1214 12:29:13.966661 best dqsien dly found for B0: ( 0, 14, 4)
1215 12:29:13.969923 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 12:29:13.973090 Total UI for P1: 0, mck2ui 16
1217 12:29:13.976959 best dqsien dly found for B1: ( 0, 14, 8)
1218 12:29:13.980148 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1219 12:29:13.983299 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1220 12:29:13.983403
1221 12:29:13.986988 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1222 12:29:13.990300 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1223 12:29:13.993580 [Gating] SW calibration Done
1224 12:29:13.993657 ==
1225 12:29:13.996941 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 12:29:14.000254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 12:29:14.003581 ==
1228 12:29:14.003664 RX Vref Scan: 0
1229 12:29:14.003728
1230 12:29:14.006951 RX Vref 0 -> 0, step: 1
1231 12:29:14.007035
1232 12:29:14.010179 RX Delay -130 -> 252, step: 16
1233 12:29:14.013506 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1234 12:29:14.016753 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1235 12:29:14.020088 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1236 12:29:14.023302 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1237 12:29:14.029914 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1238 12:29:14.033286 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1239 12:29:14.036557 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1240 12:29:14.039941 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1241 12:29:14.043223 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1242 12:29:14.049869 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1243 12:29:14.053197 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1244 12:29:14.056551 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1245 12:29:14.059915 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1246 12:29:14.063171 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1247 12:29:14.070178 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1248 12:29:14.073234 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1249 12:29:14.073340 ==
1250 12:29:14.076357 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 12:29:14.079659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 12:29:14.079736 ==
1253 12:29:14.082924 DQS Delay:
1254 12:29:14.083025 DQS0 = 0, DQS1 = 0
1255 12:29:14.083126 DQM Delay:
1256 12:29:14.086785 DQM0 = 83, DQM1 = 75
1257 12:29:14.086889 DQ Delay:
1258 12:29:14.090043 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1259 12:29:14.093235 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1260 12:29:14.096475 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1261 12:29:14.099911 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1262 12:29:14.099987
1263 12:29:14.100068
1264 12:29:14.100151 ==
1265 12:29:14.103203 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 12:29:14.109906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 12:29:14.110011 ==
1268 12:29:14.110101
1269 12:29:14.110181
1270 12:29:14.110258 TX Vref Scan disable
1271 12:29:14.113237 == TX Byte 0 ==
1272 12:29:14.116934 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1273 12:29:14.120207 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1274 12:29:14.123633 == TX Byte 1 ==
1275 12:29:14.126913 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1276 12:29:14.130154 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1277 12:29:14.133495 ==
1278 12:29:14.136829 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 12:29:14.140118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 12:29:14.140221 ==
1281 12:29:14.152590 TX Vref=22, minBit 3, minWin=27, winSum=444
1282 12:29:14.155921 TX Vref=24, minBit 9, minWin=27, winSum=449
1283 12:29:14.159256 TX Vref=26, minBit 9, minWin=27, winSum=451
1284 12:29:14.162543 TX Vref=28, minBit 9, minWin=27, winSum=451
1285 12:29:14.165901 TX Vref=30, minBit 5, minWin=28, winSum=455
1286 12:29:14.172673 TX Vref=32, minBit 4, minWin=28, winSum=457
1287 12:29:14.175919 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 32
1288 12:29:14.176024
1289 12:29:14.179604 Final TX Range 1 Vref 32
1290 12:29:14.179688
1291 12:29:14.179773 ==
1292 12:29:14.182833 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 12:29:14.186270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 12:29:14.186380 ==
1295 12:29:14.186476
1296 12:29:14.189610
1297 12:29:14.189717 TX Vref Scan disable
1298 12:29:14.192785 == TX Byte 0 ==
1299 12:29:14.196034 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1300 12:29:14.199237 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1301 12:29:14.202554 == TX Byte 1 ==
1302 12:29:14.205912 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1303 12:29:14.209924 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1304 12:29:14.213275
1305 12:29:14.213374 [DATLAT]
1306 12:29:14.213468 Freq=800, CH0 RK1
1307 12:29:14.213557
1308 12:29:14.216555 DATLAT Default: 0xa
1309 12:29:14.216650 0, 0xFFFF, sum = 0
1310 12:29:14.219683 1, 0xFFFF, sum = 0
1311 12:29:14.219760 2, 0xFFFF, sum = 0
1312 12:29:14.222908 3, 0xFFFF, sum = 0
1313 12:29:14.223007 4, 0xFFFF, sum = 0
1314 12:29:14.226262 5, 0xFFFF, sum = 0
1315 12:29:14.226357 6, 0xFFFF, sum = 0
1316 12:29:14.229399 7, 0xFFFF, sum = 0
1317 12:29:14.229497 8, 0xFFFF, sum = 0
1318 12:29:14.233212 9, 0x0, sum = 1
1319 12:29:14.233282 10, 0x0, sum = 2
1320 12:29:14.236532 11, 0x0, sum = 3
1321 12:29:14.236603 12, 0x0, sum = 4
1322 12:29:14.240000 best_step = 10
1323 12:29:14.240067
1324 12:29:14.240130 ==
1325 12:29:14.243278 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 12:29:14.246666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 12:29:14.246735 ==
1328 12:29:14.249860 RX Vref Scan: 0
1329 12:29:14.249956
1330 12:29:14.250044 RX Vref 0 -> 0, step: 1
1331 12:29:14.250134
1332 12:29:14.253337 RX Delay -95 -> 252, step: 8
1333 12:29:14.259936 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1334 12:29:14.263238 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1335 12:29:14.266409 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1336 12:29:14.269608 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1337 12:29:14.272874 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1338 12:29:14.279666 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1339 12:29:14.283329 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1340 12:29:14.286414 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1341 12:29:14.289757 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1342 12:29:14.293048 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1343 12:29:14.299456 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1344 12:29:14.302777 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1345 12:29:14.306024 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1346 12:29:14.309925 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1347 12:29:14.313198 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1348 12:29:14.319843 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1349 12:29:14.319943 ==
1350 12:29:14.323156 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 12:29:14.326412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 12:29:14.326483 ==
1353 12:29:14.326551 DQS Delay:
1354 12:29:14.329838 DQS0 = 0, DQS1 = 0
1355 12:29:14.329933 DQM Delay:
1356 12:29:14.333045 DQM0 = 87, DQM1 = 78
1357 12:29:14.333141 DQ Delay:
1358 12:29:14.336340 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1359 12:29:14.339663 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1360 12:29:14.342933 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1361 12:29:14.346188 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1362 12:29:14.346260
1363 12:29:14.346321
1364 12:29:14.352827 [DQSOSCAuto] RK1, (LSB)MR18= 0x321d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1365 12:29:14.356166 CH0 RK1: MR19=606, MR18=321D
1366 12:29:14.362931 CH0_RK1: MR19=0x606, MR18=0x321D, DQSOSC=397, MR23=63, INC=93, DEC=62
1367 12:29:14.366197 [RxdqsGatingPostProcess] freq 800
1368 12:29:14.373374 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 12:29:14.373480 Pre-setting of DQS Precalculation
1370 12:29:14.379952 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1371 12:29:14.380057 ==
1372 12:29:14.383201 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 12:29:14.386517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 12:29:14.386616 ==
1375 12:29:14.392825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 12:29:14.399419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 12:29:14.407864 [CA 0] Center 36 (6~67) winsize 62
1378 12:29:14.411183 [CA 1] Center 36 (6~66) winsize 61
1379 12:29:14.414492 [CA 2] Center 34 (4~64) winsize 61
1380 12:29:14.417821 [CA 3] Center 33 (3~64) winsize 62
1381 12:29:14.421186 [CA 4] Center 34 (4~65) winsize 62
1382 12:29:14.424465 [CA 5] Center 33 (3~64) winsize 62
1383 12:29:14.424557
1384 12:29:14.427774 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1385 12:29:14.427875
1386 12:29:14.430986 [CATrainingPosCal] consider 1 rank data
1387 12:29:14.434691 u2DelayCellTimex100 = 270/100 ps
1388 12:29:14.437987 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 12:29:14.441336 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1390 12:29:14.447912 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1391 12:29:14.451188 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1392 12:29:14.454500 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 12:29:14.457711 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 12:29:14.457818
1395 12:29:14.461084 CA PerBit enable=1, Macro0, CA PI delay=33
1396 12:29:14.461196
1397 12:29:14.464263 [CBTSetCACLKResult] CA Dly = 33
1398 12:29:14.464367 CS Dly: 4 (0~35)
1399 12:29:14.464470 ==
1400 12:29:14.467521 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 12:29:14.474587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 12:29:14.474673 ==
1403 12:29:14.477904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 12:29:14.484416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 12:29:14.493497 [CA 0] Center 36 (6~66) winsize 61
1406 12:29:14.497156 [CA 1] Center 36 (6~66) winsize 61
1407 12:29:14.500457 [CA 2] Center 34 (4~64) winsize 61
1408 12:29:14.503729 [CA 3] Center 33 (3~64) winsize 62
1409 12:29:14.506973 [CA 4] Center 34 (3~65) winsize 63
1410 12:29:14.510172 [CA 5] Center 33 (3~64) winsize 62
1411 12:29:14.510277
1412 12:29:14.513535 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1413 12:29:14.513641
1414 12:29:14.516812 [CATrainingPosCal] consider 2 rank data
1415 12:29:14.520884 u2DelayCellTimex100 = 270/100 ps
1416 12:29:14.524698 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1417 12:29:14.528252 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1418 12:29:14.532216 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1419 12:29:14.535359 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1420 12:29:14.539288 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1421 12:29:14.542521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 12:29:14.542637
1423 12:29:14.546716 CA PerBit enable=1, Macro0, CA PI delay=33
1424 12:29:14.546806
1425 12:29:14.550094 [CBTSetCACLKResult] CA Dly = 33
1426 12:29:14.550199 CS Dly: 5 (0~38)
1427 12:29:14.550292
1428 12:29:14.554150 ----->DramcWriteLeveling(PI) begin...
1429 12:29:14.554258 ==
1430 12:29:14.557532 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 12:29:14.563817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 12:29:14.563934 ==
1433 12:29:14.567206 Write leveling (Byte 0): 28 => 28
1434 12:29:14.570663 Write leveling (Byte 1): 29 => 29
1435 12:29:14.570767 DramcWriteLeveling(PI) end<-----
1436 12:29:14.570864
1437 12:29:14.574142 ==
1438 12:29:14.577235 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 12:29:14.580741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 12:29:14.580847 ==
1441 12:29:14.583554 [Gating] SW mode calibration
1442 12:29:14.590701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 12:29:14.594071 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 12:29:14.600542 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1445 12:29:14.603955 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1446 12:29:14.607312 0 6 8 | B1->B0 | 2423 2323 | 1 0 | (1 0) (1 0)
1447 12:29:14.614237 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:29:14.617013 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:29:14.620457 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:29:14.627241 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:29:14.630718 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:29:14.633962 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:29:14.640499 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1454 12:29:14.643775 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:29:14.647088 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1456 12:29:14.653922 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1457 12:29:14.656901 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1458 12:29:14.660174 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1459 12:29:14.663684 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1460 12:29:14.670460 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1461 12:29:14.674066 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 12:29:14.677346 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1463 12:29:14.684019 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:29:14.687163 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:29:14.690511 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:29:14.697186 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:29:14.700484 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:29:14.703611 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1469 12:29:14.710744 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:29:14.713891 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1471 12:29:14.717190 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1472 12:29:14.723964 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 12:29:14.727282 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 12:29:14.730782 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 12:29:14.737273 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1476 12:29:14.740466 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 12:29:14.743787 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1478 12:29:14.750239 0 10 8 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (1 1)
1479 12:29:14.753532 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:29:14.757460 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:29:14.760792 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1482 12:29:14.767401 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:29:14.770727 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:29:14.773985 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:29:14.780393 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:29:14.783709 0 11 8 | B1->B0 | 3636 3333 | 0 1 | (0 0) (0 0)
1487 12:29:14.786876 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 12:29:14.793509 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 12:29:14.796949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 12:29:14.800117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 12:29:14.807225 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 12:29:14.810414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 12:29:14.813813 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:29:14.820519 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:29:14.823727 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:29:14.826981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:29:14.833533 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:29:14.836930 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:29:14.840151 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:29:14.847399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:29:14.850685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:29:14.853990 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:29:14.860574 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:29:14.863830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:29:14.867173 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:29:14.870503 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:29:14.877272 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:29:14.880713 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:29:14.883913 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:29:14.890454 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1511 12:29:14.893850 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 12:29:14.897206 Total UI for P1: 0, mck2ui 16
1513 12:29:14.900590 best dqsien dly found for B0: ( 0, 14, 8)
1514 12:29:14.903920 Total UI for P1: 0, mck2ui 16
1515 12:29:14.907098 best dqsien dly found for B1: ( 0, 14, 8)
1516 12:29:14.910299 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1517 12:29:14.913620 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1518 12:29:14.913712
1519 12:29:14.916817 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1520 12:29:14.920160 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1521 12:29:14.923375 [Gating] SW calibration Done
1522 12:29:14.923451 ==
1523 12:29:14.926574 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 12:29:14.929969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 12:29:14.933201 ==
1526 12:29:14.933275 RX Vref Scan: 0
1527 12:29:14.933342
1528 12:29:14.936569 RX Vref 0 -> 0, step: 1
1529 12:29:14.936640
1530 12:29:14.939879 RX Delay -130 -> 252, step: 16
1531 12:29:14.943220 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1532 12:29:14.946658 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1533 12:29:14.950001 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1534 12:29:14.953343 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1535 12:29:14.960229 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1536 12:29:14.962933 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1537 12:29:14.966175 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1538 12:29:14.970202 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1539 12:29:14.972936 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1540 12:29:14.979716 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1541 12:29:14.983002 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1542 12:29:14.986203 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1543 12:29:14.989547 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1544 12:29:14.992984 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1545 12:29:15.000103 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1546 12:29:15.002847 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1547 12:29:15.002939 ==
1548 12:29:15.006334 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 12:29:15.009530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 12:29:15.009649 ==
1551 12:29:15.012820 DQS Delay:
1552 12:29:15.012924 DQS0 = 0, DQS1 = 0
1553 12:29:15.013017 DQM Delay:
1554 12:29:15.015930 DQM0 = 84, DQM1 = 76
1555 12:29:15.016047 DQ Delay:
1556 12:29:15.019698 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1557 12:29:15.022882 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1558 12:29:15.026252 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1559 12:29:15.029594 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1560 12:29:15.029695
1561 12:29:15.029796
1562 12:29:15.029891 ==
1563 12:29:15.032815 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 12:29:15.039541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 12:29:15.039652 ==
1566 12:29:15.039754
1567 12:29:15.039847
1568 12:29:15.039937 TX Vref Scan disable
1569 12:29:15.042931 == TX Byte 0 ==
1570 12:29:15.046259 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1571 12:29:15.053409 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1572 12:29:15.053519 == TX Byte 1 ==
1573 12:29:15.056785 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1574 12:29:15.063226 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1575 12:29:15.063337 ==
1576 12:29:15.066453 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 12:29:15.069788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 12:29:15.069893 ==
1579 12:29:15.082364 TX Vref=22, minBit 10, minWin=26, winSum=435
1580 12:29:15.085708 TX Vref=24, minBit 11, minWin=26, winSum=438
1581 12:29:15.089059 TX Vref=26, minBit 0, minWin=27, winSum=442
1582 12:29:15.092313 TX Vref=28, minBit 11, minWin=27, winSum=450
1583 12:29:15.095650 TX Vref=30, minBit 0, minWin=28, winSum=454
1584 12:29:15.102262 TX Vref=32, minBit 0, minWin=27, winSum=451
1585 12:29:15.106175 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1586 12:29:15.106286
1587 12:29:15.109691 Final TX Range 1 Vref 30
1588 12:29:15.109801
1589 12:29:15.109897 ==
1590 12:29:15.112901 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 12:29:15.116144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 12:29:15.116256 ==
1593 12:29:15.116352
1594 12:29:15.116443
1595 12:29:15.119305 TX Vref Scan disable
1596 12:29:15.122580 == TX Byte 0 ==
1597 12:29:15.125885 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1598 12:29:15.129245 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1599 12:29:15.132694 == TX Byte 1 ==
1600 12:29:15.135795 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 12:29:15.139218 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 12:29:15.139327
1603 12:29:15.143079 [DATLAT]
1604 12:29:15.143183 Freq=800, CH1 RK0
1605 12:29:15.143277
1606 12:29:15.146233 DATLAT Default: 0xa
1607 12:29:15.146307 0, 0xFFFF, sum = 0
1608 12:29:15.149462 1, 0xFFFF, sum = 0
1609 12:29:15.149537 2, 0xFFFF, sum = 0
1610 12:29:15.152853 3, 0xFFFF, sum = 0
1611 12:29:15.152927 4, 0xFFFF, sum = 0
1612 12:29:15.156190 5, 0xFFFF, sum = 0
1613 12:29:15.156292 6, 0xFFFF, sum = 0
1614 12:29:15.159550 7, 0xFFFF, sum = 0
1615 12:29:15.159625 8, 0xFFFF, sum = 0
1616 12:29:15.162758 9, 0x0, sum = 1
1617 12:29:15.162868 10, 0x0, sum = 2
1618 12:29:15.166010 11, 0x0, sum = 3
1619 12:29:15.166090 12, 0x0, sum = 4
1620 12:29:15.169235 best_step = 10
1621 12:29:15.169314
1622 12:29:15.169378 ==
1623 12:29:15.172395 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 12:29:15.175739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 12:29:15.175840 ==
1626 12:29:15.179107 RX Vref Scan: 1
1627 12:29:15.179205
1628 12:29:15.179299 Set Vref Range= 32 -> 127
1629 12:29:15.179389
1630 12:29:15.182527 RX Vref 32 -> 127, step: 1
1631 12:29:15.182617
1632 12:29:15.185837 RX Delay -111 -> 252, step: 8
1633 12:29:15.185940
1634 12:29:15.189207 Set Vref, RX VrefLevel [Byte0]: 32
1635 12:29:15.192440 [Byte1]: 32
1636 12:29:15.192515
1637 12:29:15.195637 Set Vref, RX VrefLevel [Byte0]: 33
1638 12:29:15.199032 [Byte1]: 33
1639 12:29:15.202942
1640 12:29:15.203016 Set Vref, RX VrefLevel [Byte0]: 34
1641 12:29:15.206202 [Byte1]: 34
1642 12:29:15.210732
1643 12:29:15.210810 Set Vref, RX VrefLevel [Byte0]: 35
1644 12:29:15.213875 [Byte1]: 35
1645 12:29:15.217985
1646 12:29:15.218096 Set Vref, RX VrefLevel [Byte0]: 36
1647 12:29:15.221162 [Byte1]: 36
1648 12:29:15.225814
1649 12:29:15.225893 Set Vref, RX VrefLevel [Byte0]: 37
1650 12:29:15.228990 [Byte1]: 37
1651 12:29:15.233670
1652 12:29:15.233750 Set Vref, RX VrefLevel [Byte0]: 38
1653 12:29:15.237043 [Byte1]: 38
1654 12:29:15.240880
1655 12:29:15.240988 Set Vref, RX VrefLevel [Byte0]: 39
1656 12:29:15.244688 [Byte1]: 39
1657 12:29:15.248657
1658 12:29:15.248761 Set Vref, RX VrefLevel [Byte0]: 40
1659 12:29:15.251931 [Byte1]: 40
1660 12:29:15.256510
1661 12:29:15.256615 Set Vref, RX VrefLevel [Byte0]: 41
1662 12:29:15.259909 [Byte1]: 41
1663 12:29:15.263960
1664 12:29:15.264073 Set Vref, RX VrefLevel [Byte0]: 42
1665 12:29:15.267336 [Byte1]: 42
1666 12:29:15.271941
1667 12:29:15.272047 Set Vref, RX VrefLevel [Byte0]: 43
1668 12:29:15.275174 [Byte1]: 43
1669 12:29:15.279032
1670 12:29:15.279136 Set Vref, RX VrefLevel [Byte0]: 44
1671 12:29:15.282439 [Byte1]: 44
1672 12:29:15.287203
1673 12:29:15.287309 Set Vref, RX VrefLevel [Byte0]: 45
1674 12:29:15.290577 [Byte1]: 45
1675 12:29:15.294545
1676 12:29:15.294624 Set Vref, RX VrefLevel [Byte0]: 46
1677 12:29:15.297908 [Byte1]: 46
1678 12:29:15.302088
1679 12:29:15.302194 Set Vref, RX VrefLevel [Byte0]: 47
1680 12:29:15.305471 [Byte1]: 47
1681 12:29:15.309978
1682 12:29:15.310085 Set Vref, RX VrefLevel [Byte0]: 48
1683 12:29:15.313180 [Byte1]: 48
1684 12:29:15.317660
1685 12:29:15.317768 Set Vref, RX VrefLevel [Byte0]: 49
1686 12:29:15.320879 [Byte1]: 49
1687 12:29:15.325184
1688 12:29:15.325292 Set Vref, RX VrefLevel [Byte0]: 50
1689 12:29:15.328417 [Byte1]: 50
1690 12:29:15.332925
1691 12:29:15.333027 Set Vref, RX VrefLevel [Byte0]: 51
1692 12:29:15.336274 [Byte1]: 51
1693 12:29:15.340263
1694 12:29:15.340347 Set Vref, RX VrefLevel [Byte0]: 52
1695 12:29:15.344033 [Byte1]: 52
1696 12:29:15.347898
1697 12:29:15.351101 Set Vref, RX VrefLevel [Byte0]: 53
1698 12:29:15.354507 [Byte1]: 53
1699 12:29:15.354589
1700 12:29:15.357770 Set Vref, RX VrefLevel [Byte0]: 54
1701 12:29:15.361024 [Byte1]: 54
1702 12:29:15.361113
1703 12:29:15.364878 Set Vref, RX VrefLevel [Byte0]: 55
1704 12:29:15.368149 [Byte1]: 55
1705 12:29:15.368294
1706 12:29:15.371494 Set Vref, RX VrefLevel [Byte0]: 56
1707 12:29:15.374839 [Byte1]: 56
1708 12:29:15.378531
1709 12:29:15.378616 Set Vref, RX VrefLevel [Byte0]: 57
1710 12:29:15.381746 [Byte1]: 57
1711 12:29:15.386510
1712 12:29:15.386594 Set Vref, RX VrefLevel [Byte0]: 58
1713 12:29:15.389821 [Byte1]: 58
1714 12:29:15.393751
1715 12:29:15.393835 Set Vref, RX VrefLevel [Byte0]: 59
1716 12:29:15.397224 [Byte1]: 59
1717 12:29:15.401887
1718 12:29:15.401962 Set Vref, RX VrefLevel [Byte0]: 60
1719 12:29:15.405181 [Byte1]: 60
1720 12:29:15.409099
1721 12:29:15.409184 Set Vref, RX VrefLevel [Byte0]: 61
1722 12:29:15.412512 [Byte1]: 61
1723 12:29:15.417081
1724 12:29:15.417167 Set Vref, RX VrefLevel [Byte0]: 62
1725 12:29:15.420312 [Byte1]: 62
1726 12:29:15.424690
1727 12:29:15.424769 Set Vref, RX VrefLevel [Byte0]: 63
1728 12:29:15.427878 [Byte1]: 63
1729 12:29:15.432466
1730 12:29:15.432555 Set Vref, RX VrefLevel [Byte0]: 64
1731 12:29:15.435486 [Byte1]: 64
1732 12:29:15.439999
1733 12:29:15.440089 Set Vref, RX VrefLevel [Byte0]: 65
1734 12:29:15.443156 [Byte1]: 65
1735 12:29:15.447858
1736 12:29:15.447943 Set Vref, RX VrefLevel [Byte0]: 66
1737 12:29:15.451100 [Byte1]: 66
1738 12:29:15.455056
1739 12:29:15.455147 Set Vref, RX VrefLevel [Byte0]: 67
1740 12:29:15.458272 [Byte1]: 67
1741 12:29:15.462821
1742 12:29:15.462931 Set Vref, RX VrefLevel [Byte0]: 68
1743 12:29:15.466163 [Byte1]: 68
1744 12:29:15.470154
1745 12:29:15.470232 Set Vref, RX VrefLevel [Byte0]: 69
1746 12:29:15.473452 [Byte1]: 69
1747 12:29:15.478153
1748 12:29:15.478262 Set Vref, RX VrefLevel [Byte0]: 70
1749 12:29:15.484197 [Byte1]: 70
1750 12:29:15.484283
1751 12:29:15.487636 Set Vref, RX VrefLevel [Byte0]: 71
1752 12:29:15.490959 [Byte1]: 71
1753 12:29:15.491058
1754 12:29:15.494257 Set Vref, RX VrefLevel [Byte0]: 72
1755 12:29:15.497545 [Byte1]: 72
1756 12:29:15.500912
1757 12:29:15.500984 Set Vref, RX VrefLevel [Byte0]: 73
1758 12:29:15.504175 [Byte1]: 73
1759 12:29:15.508887
1760 12:29:15.508990 Set Vref, RX VrefLevel [Byte0]: 74
1761 12:29:15.512228 [Byte1]: 74
1762 12:29:15.516101
1763 12:29:15.516208 Set Vref, RX VrefLevel [Byte0]: 75
1764 12:29:15.519433 [Byte1]: 75
1765 12:29:15.523847
1766 12:29:15.523955 Set Vref, RX VrefLevel [Byte0]: 76
1767 12:29:15.527092 [Byte1]: 76
1768 12:29:15.531571
1769 12:29:15.531675 Set Vref, RX VrefLevel [Byte0]: 77
1770 12:29:15.534819 [Byte1]: 77
1771 12:29:15.539317
1772 12:29:15.539406 Set Vref, RX VrefLevel [Byte0]: 78
1773 12:29:15.542471 [Byte1]: 78
1774 12:29:15.547199
1775 12:29:15.547301 Set Vref, RX VrefLevel [Byte0]: 79
1776 12:29:15.550535 [Byte1]: 79
1777 12:29:15.554405
1778 12:29:15.554484 Set Vref, RX VrefLevel [Byte0]: 80
1779 12:29:15.557527 [Byte1]: 80
1780 12:29:15.562159
1781 12:29:15.562245 Final RX Vref Byte 0 = 66 to rank0
1782 12:29:15.565523 Final RX Vref Byte 1 = 59 to rank0
1783 12:29:15.568850 Final RX Vref Byte 0 = 66 to rank1
1784 12:29:15.572253 Final RX Vref Byte 1 = 59 to rank1==
1785 12:29:15.575524 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 12:29:15.582139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 12:29:15.582221 ==
1788 12:29:15.582287 DQS Delay:
1789 12:29:15.582350 DQS0 = 0, DQS1 = 0
1790 12:29:15.585528 DQM Delay:
1791 12:29:15.585601 DQM0 = 84, DQM1 = 74
1792 12:29:15.588835 DQ Delay:
1793 12:29:15.592193 DQ0 =92, DQ1 =76, DQ2 =76, DQ3 =84
1794 12:29:15.592277 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1795 12:29:15.595555 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1796 12:29:15.602146 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1797 12:29:15.602256
1798 12:29:15.602359
1799 12:29:15.608875 [DQSOSCAuto] RK0, (LSB)MR18= 0x29fe, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1800 12:29:15.612153 CH1 RK0: MR19=605, MR18=29FE
1801 12:29:15.618928 CH1_RK0: MR19=0x605, MR18=0x29FE, DQSOSC=399, MR23=63, INC=92, DEC=61
1802 12:29:15.619051
1803 12:29:15.622161 ----->DramcWriteLeveling(PI) begin...
1804 12:29:15.622274 ==
1805 12:29:15.625522 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 12:29:15.628781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 12:29:15.628874 ==
1808 12:29:15.632020 Write leveling (Byte 0): 28 => 28
1809 12:29:15.635241 Write leveling (Byte 1): 28 => 28
1810 12:29:15.639189 DramcWriteLeveling(PI) end<-----
1811 12:29:15.639272
1812 12:29:15.639346 ==
1813 12:29:15.642205 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 12:29:15.645523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 12:29:15.645626 ==
1816 12:29:15.649146 [Gating] SW mode calibration
1817 12:29:15.655593 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 12:29:15.662443 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 12:29:15.665651 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1820 12:29:15.668986 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 12:29:15.675669 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:29:15.678951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:29:15.682247 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:29:15.689056 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:29:15.692274 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:29:15.695642 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:29:15.702252 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:29:15.705511 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:29:15.708951 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:29:15.715541 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1831 12:29:15.718926 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1832 12:29:15.722258 0 7 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1833 12:29:15.725494 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1834 12:29:15.732086 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:29:15.735409 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1836 12:29:15.738645 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1837 12:29:15.745148 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 12:29:15.748872 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:29:15.752019 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:29:15.758941 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:29:15.762262 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:29:15.765424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:29:15.771919 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:29:15.775099 0 9 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1845 12:29:15.778446 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
1846 12:29:15.785211 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1847 12:29:15.788535 0 9 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1848 12:29:15.791936 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 12:29:15.798461 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1850 12:29:15.801810 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:29:15.805278 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 12:29:15.811874 0 10 4 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (1 0)
1853 12:29:15.815176 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1854 12:29:15.819175 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1855 12:29:15.822442 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:29:15.828665 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1857 12:29:15.831842 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1858 12:29:15.835564 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:29:15.842060 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1860 12:29:15.845394 0 11 4 | B1->B0 | 2c2c 3535 | 0 0 | (0 0) (0 0)
1861 12:29:15.848645 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1862 12:29:15.855666 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:29:15.858659 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:29:15.862565 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:29:15.868990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:29:15.872200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:29:15.875409 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:29:15.882099 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1869 12:29:15.885364 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:29:15.889198 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:29:15.895245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:29:15.898605 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:29:15.902456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:29:15.909063 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:29:15.912283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:29:15.915516 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:29:15.918891 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:29:15.925579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:29:15.929059 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:29:15.932087 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:29:15.939154 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:29:15.942343 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:29:15.945515 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:29:15.952178 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1885 12:29:15.955566 Total UI for P1: 0, mck2ui 16
1886 12:29:15.958769 best dqsien dly found for B0: ( 0, 14, 2)
1887 12:29:15.962315 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 12:29:15.965402 Total UI for P1: 0, mck2ui 16
1889 12:29:15.968889 best dqsien dly found for B1: ( 0, 14, 4)
1890 12:29:15.972092 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1891 12:29:15.975772 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1892 12:29:15.975878
1893 12:29:15.978894 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1894 12:29:15.981995 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 12:29:15.985299 [Gating] SW calibration Done
1896 12:29:15.985411 ==
1897 12:29:15.989192 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 12:29:15.992533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 12:29:15.992634 ==
1900 12:29:15.995931 RX Vref Scan: 0
1901 12:29:15.996019
1902 12:29:15.999277 RX Vref 0 -> 0, step: 1
1903 12:29:15.999380
1904 12:29:15.999448 RX Delay -130 -> 252, step: 16
1905 12:29:16.005677 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1906 12:29:16.008840 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1907 12:29:16.012095 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1908 12:29:16.015439 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1909 12:29:16.018739 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1910 12:29:16.025343 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1911 12:29:16.028672 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1912 12:29:16.031992 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1913 12:29:16.035988 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1914 12:29:16.038523 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1915 12:29:16.045119 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1916 12:29:16.048900 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1917 12:29:16.052381 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1918 12:29:16.055670 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1919 12:29:16.062183 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1920 12:29:16.065360 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1921 12:29:16.065467 ==
1922 12:29:16.068501 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 12:29:16.072233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 12:29:16.072314 ==
1925 12:29:16.072381 DQS Delay:
1926 12:29:16.075387 DQS0 = 0, DQS1 = 0
1927 12:29:16.075464 DQM Delay:
1928 12:29:16.078400 DQM0 = 79, DQM1 = 78
1929 12:29:16.078513 DQ Delay:
1930 12:29:16.082078 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1931 12:29:16.085134 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1932 12:29:16.088988 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1933 12:29:16.092073 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1934 12:29:16.092158
1935 12:29:16.092225
1936 12:29:16.092288 ==
1937 12:29:16.095665 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 12:29:16.099077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 12:29:16.102262 ==
1940 12:29:16.102336
1941 12:29:16.102400
1942 12:29:16.102459 TX Vref Scan disable
1943 12:29:16.105556 == TX Byte 0 ==
1944 12:29:16.108766 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1945 12:29:16.112110 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1946 12:29:16.115355 == TX Byte 1 ==
1947 12:29:16.118697 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1948 12:29:16.122116 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1949 12:29:16.125381 ==
1950 12:29:16.125457 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 12:29:16.131960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 12:29:16.132034 ==
1953 12:29:16.143897 TX Vref=22, minBit 0, minWin=27, winSum=442
1954 12:29:16.147115 TX Vref=24, minBit 1, minWin=27, winSum=444
1955 12:29:16.150356 TX Vref=26, minBit 1, minWin=27, winSum=445
1956 12:29:16.153683 TX Vref=28, minBit 12, minWin=27, winSum=448
1957 12:29:16.156951 TX Vref=30, minBit 0, minWin=28, winSum=450
1958 12:29:16.160333 TX Vref=32, minBit 0, minWin=28, winSum=453
1959 12:29:16.166905 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1960 12:29:16.166989
1961 12:29:16.170899 Final TX Range 1 Vref 32
1962 12:29:16.170986
1963 12:29:16.171059 ==
1964 12:29:16.174102 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 12:29:16.177311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 12:29:16.177393 ==
1967 12:29:16.177462
1968 12:29:16.180578
1969 12:29:16.180652 TX Vref Scan disable
1970 12:29:16.183794 == TX Byte 0 ==
1971 12:29:16.187489 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 12:29:16.190741 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 12:29:16.193957 == TX Byte 1 ==
1974 12:29:16.197104 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 12:29:16.200782 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 12:29:16.204099
1977 12:29:16.204184 [DATLAT]
1978 12:29:16.204268 Freq=800, CH1 RK1
1979 12:29:16.204379
1980 12:29:16.207462 DATLAT Default: 0xa
1981 12:29:16.207550 0, 0xFFFF, sum = 0
1982 12:29:16.210903 1, 0xFFFF, sum = 0
1983 12:29:16.211017 2, 0xFFFF, sum = 0
1984 12:29:16.214242 3, 0xFFFF, sum = 0
1985 12:29:16.214372 4, 0xFFFF, sum = 0
1986 12:29:16.217382 5, 0xFFFF, sum = 0
1987 12:29:16.217493 6, 0xFFFF, sum = 0
1988 12:29:16.220682 7, 0xFFFF, sum = 0
1989 12:29:16.220770 8, 0xFFFF, sum = 0
1990 12:29:16.224036 9, 0x0, sum = 1
1991 12:29:16.224116 10, 0x0, sum = 2
1992 12:29:16.227422 11, 0x0, sum = 3
1993 12:29:16.227500 12, 0x0, sum = 4
1994 12:29:16.230671 best_step = 10
1995 12:29:16.230754
1996 12:29:16.230819 ==
1997 12:29:16.234077 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 12:29:16.237368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 12:29:16.237472 ==
2000 12:29:16.240661 RX Vref Scan: 0
2001 12:29:16.240737
2002 12:29:16.240807 RX Vref 0 -> 0, step: 1
2003 12:29:16.240869
2004 12:29:16.244002 RX Delay -95 -> 252, step: 8
2005 12:29:16.250681 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2006 12:29:16.254076 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2007 12:29:16.257359 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2008 12:29:16.260847 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2009 12:29:16.263652 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2010 12:29:16.270306 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2011 12:29:16.273662 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2012 12:29:16.277675 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2013 12:29:16.280766 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2014 12:29:16.284050 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2015 12:29:16.290492 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2016 12:29:16.294298 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2017 12:29:16.297418 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2018 12:29:16.300383 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2019 12:29:16.304185 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2020 12:29:16.310496 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2021 12:29:16.310580 ==
2022 12:29:16.313670 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 12:29:16.317155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 12:29:16.317265 ==
2025 12:29:16.317361 DQS Delay:
2026 12:29:16.320517 DQS0 = 0, DQS1 = 0
2027 12:29:16.320626 DQM Delay:
2028 12:29:16.323851 DQM0 = 79, DQM1 = 75
2029 12:29:16.323936 DQ Delay:
2030 12:29:16.327227 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =80
2031 12:29:16.330415 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =72
2032 12:29:16.334011 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2033 12:29:16.337390 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2034 12:29:16.337496
2035 12:29:16.337591
2036 12:29:16.344096 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2037 12:29:16.347417 CH1 RK1: MR19=606, MR18=1F29
2038 12:29:16.353887 CH1_RK1: MR19=0x606, MR18=0x1F29, DQSOSC=399, MR23=63, INC=92, DEC=61
2039 12:29:16.357215 [RxdqsGatingPostProcess] freq 800
2040 12:29:16.363878 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2041 12:29:16.363987 Pre-setting of DQS Precalculation
2042 12:29:16.370520 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2043 12:29:16.377449 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2044 12:29:16.384368 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2045 12:29:16.384452
2046 12:29:16.384520
2047 12:29:16.387665 [Calibration Summary] 1600 Mbps
2048 12:29:16.390914 CH 0, Rank 0
2049 12:29:16.390999 SW Impedance : PASS
2050 12:29:16.394219 DUTY Scan : NO K
2051 12:29:16.394303 ZQ Calibration : PASS
2052 12:29:16.397460 Jitter Meter : NO K
2053 12:29:16.400668 CBT Training : PASS
2054 12:29:16.400751 Write leveling : PASS
2055 12:29:16.404516 RX DQS gating : PASS
2056 12:29:16.407760 RX DQ/DQS(RDDQC) : PASS
2057 12:29:16.407843 TX DQ/DQS : PASS
2058 12:29:16.410824 RX DATLAT : PASS
2059 12:29:16.414147 RX DQ/DQS(Engine): PASS
2060 12:29:16.414231 TX OE : NO K
2061 12:29:16.417313 All Pass.
2062 12:29:16.417396
2063 12:29:16.417463 CH 0, Rank 1
2064 12:29:16.421212 SW Impedance : PASS
2065 12:29:16.421296 DUTY Scan : NO K
2066 12:29:16.424355 ZQ Calibration : PASS
2067 12:29:16.427674 Jitter Meter : NO K
2068 12:29:16.427758 CBT Training : PASS
2069 12:29:16.430981 Write leveling : PASS
2070 12:29:16.434328 RX DQS gating : PASS
2071 12:29:16.434412 RX DQ/DQS(RDDQC) : PASS
2072 12:29:16.437720 TX DQ/DQS : PASS
2073 12:29:16.437805 RX DATLAT : PASS
2074 12:29:16.441091 RX DQ/DQS(Engine): PASS
2075 12:29:16.443803 TX OE : NO K
2076 12:29:16.443919 All Pass.
2077 12:29:16.444023
2078 12:29:16.444091 CH 1, Rank 0
2079 12:29:16.447803 SW Impedance : PASS
2080 12:29:16.450488 DUTY Scan : NO K
2081 12:29:16.450571 ZQ Calibration : PASS
2082 12:29:16.453898 Jitter Meter : NO K
2083 12:29:16.457251 CBT Training : PASS
2084 12:29:16.457335 Write leveling : PASS
2085 12:29:16.460649 RX DQS gating : PASS
2086 12:29:16.463895 RX DQ/DQS(RDDQC) : PASS
2087 12:29:16.463980 TX DQ/DQS : PASS
2088 12:29:16.467239 RX DATLAT : PASS
2089 12:29:16.470584 RX DQ/DQS(Engine): PASS
2090 12:29:16.470668 TX OE : NO K
2091 12:29:16.470735 All Pass.
2092 12:29:16.473988
2093 12:29:16.474072 CH 1, Rank 1
2094 12:29:16.477304 SW Impedance : PASS
2095 12:29:16.477388 DUTY Scan : NO K
2096 12:29:16.480776 ZQ Calibration : PASS
2097 12:29:16.484166 Jitter Meter : NO K
2098 12:29:16.484250 CBT Training : PASS
2099 12:29:16.487279 Write leveling : PASS
2100 12:29:16.487372 RX DQS gating : PASS
2101 12:29:16.490624 RX DQ/DQS(RDDQC) : PASS
2102 12:29:16.493797 TX DQ/DQS : PASS
2103 12:29:16.493907 RX DATLAT : PASS
2104 12:29:16.497090 RX DQ/DQS(Engine): PASS
2105 12:29:16.500393 TX OE : NO K
2106 12:29:16.500503 All Pass.
2107 12:29:16.500598
2108 12:29:16.503726 DramC Write-DBI off
2109 12:29:16.503811 PER_BANK_REFRESH: Hybrid Mode
2110 12:29:16.507173 TX_TRACKING: ON
2111 12:29:16.510861 [GetDramInforAfterCalByMRR] Vendor 6.
2112 12:29:16.514059 [GetDramInforAfterCalByMRR] Revision 606.
2113 12:29:16.517169 [GetDramInforAfterCalByMRR] Revision 2 0.
2114 12:29:16.517254 MR0 0x3b3b
2115 12:29:16.520298 MR8 0x5151
2116 12:29:16.523897 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 12:29:16.523981
2118 12:29:16.524052 MR0 0x3b3b
2119 12:29:16.527089 MR8 0x5151
2120 12:29:16.530347 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 12:29:16.530459
2122 12:29:16.537200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2123 12:29:16.540520 [FAST_K] Save calibration result to emmc
2124 12:29:16.547132 [FAST_K] Save calibration result to emmc
2125 12:29:16.547240 dram_init: config_dvfs: 1
2126 12:29:16.550641 dramc_set_vcore_voltage set vcore to 662500
2127 12:29:16.554007 Read voltage for 1200, 2
2128 12:29:16.554111 Vio18 = 0
2129 12:29:16.557352 Vcore = 662500
2130 12:29:16.557454 Vdram = 0
2131 12:29:16.557556 Vddq = 0
2132 12:29:16.560519 Vmddr = 0
2133 12:29:16.563997 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2134 12:29:16.570314 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2135 12:29:16.570415 MEM_TYPE=3, freq_sel=15
2136 12:29:16.573638 sv_algorithm_assistance_LP4_1600
2137 12:29:16.580817 ============ PULL DRAM RESETB DOWN ============
2138 12:29:16.584121 ========== PULL DRAM RESETB DOWN end =========
2139 12:29:16.587341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 12:29:16.590761 ===================================
2141 12:29:16.594122 LPDDR4 DRAM CONFIGURATION
2142 12:29:16.597248 ===================================
2143 12:29:16.597361 EX_ROW_EN[0] = 0x0
2144 12:29:16.600470 EX_ROW_EN[1] = 0x0
2145 12:29:16.603900 LP4Y_EN = 0x0
2146 12:29:16.603978 WORK_FSP = 0x0
2147 12:29:16.607302 WL = 0x4
2148 12:29:16.607398 RL = 0x4
2149 12:29:16.610634 BL = 0x2
2150 12:29:16.610737 RPST = 0x0
2151 12:29:16.613810 RD_PRE = 0x0
2152 12:29:16.613914 WR_PRE = 0x1
2153 12:29:16.617006 WR_PST = 0x0
2154 12:29:16.617106 DBI_WR = 0x0
2155 12:29:16.620300 DBI_RD = 0x0
2156 12:29:16.620408 OTF = 0x1
2157 12:29:16.623993 ===================================
2158 12:29:16.627153 ===================================
2159 12:29:16.630441 ANA top config
2160 12:29:16.633849 ===================================
2161 12:29:16.633954 DLL_ASYNC_EN = 0
2162 12:29:16.636935 ALL_SLAVE_EN = 0
2163 12:29:16.640834 NEW_RANK_MODE = 1
2164 12:29:16.643539 DLL_IDLE_MODE = 1
2165 12:29:16.643649 LP45_APHY_COMB_EN = 1
2166 12:29:16.646792 TX_ODT_DIS = 1
2167 12:29:16.650108 NEW_8X_MODE = 1
2168 12:29:16.653418 ===================================
2169 12:29:16.656661 ===================================
2170 12:29:16.660055 data_rate = 2400
2171 12:29:16.663365 CKR = 1
2172 12:29:16.666741 DQ_P2S_RATIO = 8
2173 12:29:16.670065 ===================================
2174 12:29:16.670170 CA_P2S_RATIO = 8
2175 12:29:16.673278 DQ_CA_OPEN = 0
2176 12:29:16.676629 DQ_SEMI_OPEN = 0
2177 12:29:16.680514 CA_SEMI_OPEN = 0
2178 12:29:16.683873 CA_FULL_RATE = 0
2179 12:29:16.687069 DQ_CKDIV4_EN = 0
2180 12:29:16.687181 CA_CKDIV4_EN = 0
2181 12:29:16.690344 CA_PREDIV_EN = 0
2182 12:29:16.693795 PH8_DLY = 17
2183 12:29:16.697270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2184 12:29:16.700478 DQ_AAMCK_DIV = 4
2185 12:29:16.700592 CA_AAMCK_DIV = 4
2186 12:29:16.703505 CA_ADMCK_DIV = 4
2187 12:29:16.706778 DQ_TRACK_CA_EN = 0
2188 12:29:16.710158 CA_PICK = 1200
2189 12:29:16.713465 CA_MCKIO = 1200
2190 12:29:16.716950 MCKIO_SEMI = 0
2191 12:29:16.720185 PLL_FREQ = 2366
2192 12:29:16.723441 DQ_UI_PI_RATIO = 32
2193 12:29:16.723553 CA_UI_PI_RATIO = 0
2194 12:29:16.726648 ===================================
2195 12:29:16.730450 ===================================
2196 12:29:16.733724 memory_type:LPDDR4
2197 12:29:16.736921 GP_NUM : 10
2198 12:29:16.737003 SRAM_EN : 1
2199 12:29:16.740239 MD32_EN : 0
2200 12:29:16.743531 ===================================
2201 12:29:16.746823 [ANA_INIT] >>>>>>>>>>>>>>
2202 12:29:16.750115 <<<<<< [CONFIGURE PHASE]: ANA_TX
2203 12:29:16.753613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2204 12:29:16.756847 ===================================
2205 12:29:16.756922 data_rate = 2400,PCW = 0X5b00
2206 12:29:16.760065 ===================================
2207 12:29:16.763404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2208 12:29:16.770010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 12:29:16.776720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 12:29:16.779964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2211 12:29:16.783176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2212 12:29:16.786546 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2213 12:29:16.789913 [ANA_INIT] flow start
2214 12:29:16.790015 [ANA_INIT] PLL >>>>>>>>
2215 12:29:16.793245 [ANA_INIT] PLL <<<<<<<<
2216 12:29:16.796533 [ANA_INIT] MIDPI >>>>>>>>
2217 12:29:16.799857 [ANA_INIT] MIDPI <<<<<<<<
2218 12:29:16.799945 [ANA_INIT] DLL >>>>>>>>
2219 12:29:16.803167 [ANA_INIT] DLL <<<<<<<<
2220 12:29:16.803272 [ANA_INIT] flow end
2221 12:29:16.810368 ============ LP4 DIFF to SE enter ============
2222 12:29:16.813660 ============ LP4 DIFF to SE exit ============
2223 12:29:16.816837 [ANA_INIT] <<<<<<<<<<<<<
2224 12:29:16.820197 [Flow] Enable top DCM control >>>>>
2225 12:29:16.823523 [Flow] Enable top DCM control <<<<<
2226 12:29:16.823618 Enable DLL master slave shuffle
2227 12:29:16.830101 ==============================================================
2228 12:29:16.833224 Gating Mode config
2229 12:29:16.836939 ==============================================================
2230 12:29:16.840265 Config description:
2231 12:29:16.849829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2232 12:29:16.856530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2233 12:29:16.859882 SELPH_MODE 0: By rank 1: By Phase
2234 12:29:16.866596 ==============================================================
2235 12:29:16.869928 GAT_TRACK_EN = 1
2236 12:29:16.873238 RX_GATING_MODE = 2
2237 12:29:16.876453 RX_GATING_TRACK_MODE = 2
2238 12:29:16.879772 SELPH_MODE = 1
2239 12:29:16.879849 PICG_EARLY_EN = 1
2240 12:29:16.883475 VALID_LAT_VALUE = 1
2241 12:29:16.890264 ==============================================================
2242 12:29:16.893386 Enter into Gating configuration >>>>
2243 12:29:16.896517 Exit from Gating configuration <<<<
2244 12:29:16.899902 Enter into DVFS_PRE_config >>>>>
2245 12:29:16.909903 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2246 12:29:16.913043 Exit from DVFS_PRE_config <<<<<
2247 12:29:16.916367 Enter into PICG configuration >>>>
2248 12:29:16.919677 Exit from PICG configuration <<<<
2249 12:29:16.923005 [RX_INPUT] configuration >>>>>
2250 12:29:16.926319 [RX_INPUT] configuration <<<<<
2251 12:29:16.930142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2252 12:29:16.936480 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2253 12:29:16.943277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 12:29:16.949869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 12:29:16.956445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 12:29:16.959814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 12:29:16.966537 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2258 12:29:16.969855 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2259 12:29:16.973124 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2260 12:29:16.976561 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2261 12:29:16.979936 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2262 12:29:16.986731 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 12:29:16.989854 ===================================
2264 12:29:16.993170 LPDDR4 DRAM CONFIGURATION
2265 12:29:16.996417 ===================================
2266 12:29:16.996521 EX_ROW_EN[0] = 0x0
2267 12:29:16.999744 EX_ROW_EN[1] = 0x0
2268 12:29:16.999827 LP4Y_EN = 0x0
2269 12:29:17.003077 WORK_FSP = 0x0
2270 12:29:17.003161 WL = 0x4
2271 12:29:17.006305 RL = 0x4
2272 12:29:17.006388 BL = 0x2
2273 12:29:17.009556 RPST = 0x0
2274 12:29:17.009639 RD_PRE = 0x0
2275 12:29:17.013424 WR_PRE = 0x1
2276 12:29:17.013507 WR_PST = 0x0
2277 12:29:17.016497 DBI_WR = 0x0
2278 12:29:17.016581 DBI_RD = 0x0
2279 12:29:17.019747 OTF = 0x1
2280 12:29:17.022890 ===================================
2281 12:29:17.026213 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2282 12:29:17.029469 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2283 12:29:17.036697 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 12:29:17.039948 ===================================
2285 12:29:17.040033 LPDDR4 DRAM CONFIGURATION
2286 12:29:17.043052 ===================================
2287 12:29:17.046150 EX_ROW_EN[0] = 0x10
2288 12:29:17.050021 EX_ROW_EN[1] = 0x0
2289 12:29:17.050103 LP4Y_EN = 0x0
2290 12:29:17.053230 WORK_FSP = 0x0
2291 12:29:17.053357 WL = 0x4
2292 12:29:17.056524 RL = 0x4
2293 12:29:17.056599 BL = 0x2
2294 12:29:17.059751 RPST = 0x0
2295 12:29:17.059852 RD_PRE = 0x0
2296 12:29:17.063019 WR_PRE = 0x1
2297 12:29:17.063117 WR_PST = 0x0
2298 12:29:17.066230 DBI_WR = 0x0
2299 12:29:17.066319 DBI_RD = 0x0
2300 12:29:17.069557 OTF = 0x1
2301 12:29:17.072843 ===================================
2302 12:29:17.079570 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2303 12:29:17.079651 ==
2304 12:29:17.082893 Dram Type= 6, Freq= 0, CH_0, rank 0
2305 12:29:17.086079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2306 12:29:17.086159 ==
2307 12:29:17.089481 [Duty_Offset_Calibration]
2308 12:29:17.089556 B0:3 B1:-1 CA:1
2309 12:29:17.089623
2310 12:29:17.092669 [DutyScan_Calibration_Flow] k_type=0
2311 12:29:17.102529
2312 12:29:17.102605 ==CLK 0==
2313 12:29:17.105808 Final CLK duty delay cell = -4
2314 12:29:17.109145 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2315 12:29:17.112411 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2316 12:29:17.115744 [-4] AVG Duty = 4953%(X100)
2317 12:29:17.115819
2318 12:29:17.118878 CH0 CLK Duty spec in!! Max-Min= 156%
2319 12:29:17.122661 [DutyScan_Calibration_Flow] ====Done====
2320 12:29:17.122744
2321 12:29:17.125867 [DutyScan_Calibration_Flow] k_type=1
2322 12:29:17.141266
2323 12:29:17.141350 ==DQS 0 ==
2324 12:29:17.144499 Final DQS duty delay cell = 0
2325 12:29:17.147646 [0] MAX Duty = 5156%(X100), DQS PI = 46
2326 12:29:17.151469 [0] MIN Duty = 5000%(X100), DQS PI = 12
2327 12:29:17.154663 [0] AVG Duty = 5078%(X100)
2328 12:29:17.154747
2329 12:29:17.154813 ==DQS 1 ==
2330 12:29:17.157863 Final DQS duty delay cell = -4
2331 12:29:17.161075 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2332 12:29:17.164280 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2333 12:29:17.168153 [-4] AVG Duty = 5046%(X100)
2334 12:29:17.168236
2335 12:29:17.171573 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2336 12:29:17.171664
2337 12:29:17.174258 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2338 12:29:17.177605 [DutyScan_Calibration_Flow] ====Done====
2339 12:29:17.177682
2340 12:29:17.180895 [DutyScan_Calibration_Flow] k_type=3
2341 12:29:17.197784
2342 12:29:17.197879 ==DQM 0 ==
2343 12:29:17.201109 Final DQM duty delay cell = 0
2344 12:29:17.204911 [0] MAX Duty = 5000%(X100), DQS PI = 48
2345 12:29:17.208251 [0] MIN Duty = 4875%(X100), DQS PI = 4
2346 12:29:17.208334 [0] AVG Duty = 4937%(X100)
2347 12:29:17.208409
2348 12:29:17.211526 ==DQM 1 ==
2349 12:29:17.214859 Final DQM duty delay cell = 0
2350 12:29:17.218212 [0] MAX Duty = 5124%(X100), DQS PI = 32
2351 12:29:17.221553 [0] MIN Duty = 4969%(X100), DQS PI = 10
2352 12:29:17.221632 [0] AVG Duty = 5046%(X100)
2353 12:29:17.224911
2354 12:29:17.228062 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2355 12:29:17.228143
2356 12:29:17.231231 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2357 12:29:17.234621 [DutyScan_Calibration_Flow] ====Done====
2358 12:29:17.234699
2359 12:29:17.237898 [DutyScan_Calibration_Flow] k_type=2
2360 12:29:17.253952
2361 12:29:17.254054 ==DQ 0 ==
2362 12:29:17.257172 Final DQ duty delay cell = -4
2363 12:29:17.260677 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2364 12:29:17.263798 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2365 12:29:17.266846 [-4] AVG Duty = 4968%(X100)
2366 12:29:17.266933
2367 12:29:17.267057 ==DQ 1 ==
2368 12:29:17.270603 Final DQ duty delay cell = 0
2369 12:29:17.273907 [0] MAX Duty = 5031%(X100), DQS PI = 26
2370 12:29:17.277271 [0] MIN Duty = 4907%(X100), DQS PI = 46
2371 12:29:17.277361 [0] AVG Duty = 4969%(X100)
2372 12:29:17.280618
2373 12:29:17.283908 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2374 12:29:17.283996
2375 12:29:17.287242 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2376 12:29:17.290448 [DutyScan_Calibration_Flow] ====Done====
2377 12:29:17.290525 ==
2378 12:29:17.293769 Dram Type= 6, Freq= 0, CH_1, rank 0
2379 12:29:17.297067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 12:29:17.297161 ==
2381 12:29:17.300351 [Duty_Offset_Calibration]
2382 12:29:17.300438 B0:1 B1:1 CA:2
2383 12:29:17.300534
2384 12:29:17.303517 [DutyScan_Calibration_Flow] k_type=0
2385 12:29:17.314217
2386 12:29:17.314324 ==CLK 0==
2387 12:29:17.317595 Final CLK duty delay cell = 0
2388 12:29:17.320894 [0] MAX Duty = 5156%(X100), DQS PI = 24
2389 12:29:17.324121 [0] MIN Duty = 4969%(X100), DQS PI = 42
2390 12:29:17.324201 [0] AVG Duty = 5062%(X100)
2391 12:29:17.327618
2392 12:29:17.330789 CH1 CLK Duty spec in!! Max-Min= 187%
2393 12:29:17.333912 [DutyScan_Calibration_Flow] ====Done====
2394 12:29:17.333990
2395 12:29:17.337278 [DutyScan_Calibration_Flow] k_type=1
2396 12:29:17.353112
2397 12:29:17.353221 ==DQS 0 ==
2398 12:29:17.356595 Final DQS duty delay cell = 0
2399 12:29:17.359783 [0] MAX Duty = 5031%(X100), DQS PI = 18
2400 12:29:17.363635 [0] MIN Duty = 4844%(X100), DQS PI = 50
2401 12:29:17.366727 [0] AVG Duty = 4937%(X100)
2402 12:29:17.366815
2403 12:29:17.366883 ==DQS 1 ==
2404 12:29:17.369838 Final DQS duty delay cell = 0
2405 12:29:17.373106 [0] MAX Duty = 5062%(X100), DQS PI = 36
2406 12:29:17.376874 [0] MIN Duty = 4907%(X100), DQS PI = 16
2407 12:29:17.380169 [0] AVG Duty = 4984%(X100)
2408 12:29:17.380248
2409 12:29:17.383611 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2410 12:29:17.383690
2411 12:29:17.386885 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2412 12:29:17.390205 [DutyScan_Calibration_Flow] ====Done====
2413 12:29:17.390290
2414 12:29:17.393491 [DutyScan_Calibration_Flow] k_type=3
2415 12:29:17.409861
2416 12:29:17.409947 ==DQM 0 ==
2417 12:29:17.413206 Final DQM duty delay cell = 0
2418 12:29:17.416420 [0] MAX Duty = 5093%(X100), DQS PI = 18
2419 12:29:17.419935 [0] MIN Duty = 4876%(X100), DQS PI = 50
2420 12:29:17.420012 [0] AVG Duty = 4984%(X100)
2421 12:29:17.423206
2422 12:29:17.423281 ==DQM 1 ==
2423 12:29:17.426511 Final DQM duty delay cell = 0
2424 12:29:17.429800 [0] MAX Duty = 5156%(X100), DQS PI = 62
2425 12:29:17.433078 [0] MIN Duty = 4938%(X100), DQS PI = 22
2426 12:29:17.433159 [0] AVG Duty = 5047%(X100)
2427 12:29:17.436857
2428 12:29:17.440100 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2429 12:29:17.440176
2430 12:29:17.443455 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2431 12:29:17.446756 [DutyScan_Calibration_Flow] ====Done====
2432 12:29:17.446830
2433 12:29:17.449972 [DutyScan_Calibration_Flow] k_type=2
2434 12:29:17.466472
2435 12:29:17.466557 ==DQ 0 ==
2436 12:29:17.469670 Final DQ duty delay cell = 0
2437 12:29:17.473415 [0] MAX Duty = 5124%(X100), DQS PI = 18
2438 12:29:17.476688 [0] MIN Duty = 4907%(X100), DQS PI = 50
2439 12:29:17.476775 [0] AVG Duty = 5015%(X100)
2440 12:29:17.476847
2441 12:29:17.479875 ==DQ 1 ==
2442 12:29:17.483169 Final DQ duty delay cell = 0
2443 12:29:17.486571 [0] MAX Duty = 5093%(X100), DQS PI = 10
2444 12:29:17.489968 [0] MIN Duty = 5031%(X100), DQS PI = 2
2445 12:29:17.490040 [0] AVG Duty = 5062%(X100)
2446 12:29:17.490103
2447 12:29:17.493266 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2448 12:29:17.493339
2449 12:29:17.496686 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2450 12:29:17.503311 [DutyScan_Calibration_Flow] ====Done====
2451 12:29:17.506693 nWR fixed to 30
2452 12:29:17.506765 [ModeRegInit_LP4] CH0 RK0
2453 12:29:17.509881 [ModeRegInit_LP4] CH0 RK1
2454 12:29:17.513098 [ModeRegInit_LP4] CH1 RK0
2455 12:29:17.513170 [ModeRegInit_LP4] CH1 RK1
2456 12:29:17.516315 match AC timing 7
2457 12:29:17.520252 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2458 12:29:17.523590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2459 12:29:17.530033 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2460 12:29:17.533379 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2461 12:29:17.539919 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2462 12:29:17.539995 ==
2463 12:29:17.543606 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 12:29:17.546883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 12:29:17.546974 ==
2466 12:29:17.553307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 12:29:17.556655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2468 12:29:17.566295 [CA 0] Center 40 (10~71) winsize 62
2469 12:29:17.569523 [CA 1] Center 39 (9~70) winsize 62
2470 12:29:17.573005 [CA 2] Center 36 (6~67) winsize 62
2471 12:29:17.576240 [CA 3] Center 35 (5~66) winsize 62
2472 12:29:17.579496 [CA 4] Center 34 (4~65) winsize 62
2473 12:29:17.582776 [CA 5] Center 34 (4~64) winsize 61
2474 12:29:17.582918
2475 12:29:17.586690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2476 12:29:17.586779
2477 12:29:17.589322 [CATrainingPosCal] consider 1 rank data
2478 12:29:17.592732 u2DelayCellTimex100 = 270/100 ps
2479 12:29:17.596172 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2480 12:29:17.602777 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2481 12:29:17.606685 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2482 12:29:17.609909 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2483 12:29:17.613153 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2484 12:29:17.616509 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2485 12:29:17.616612
2486 12:29:17.619718 CA PerBit enable=1, Macro0, CA PI delay=34
2487 12:29:17.619824
2488 12:29:17.622904 [CBTSetCACLKResult] CA Dly = 34
2489 12:29:17.623005 CS Dly: 7 (0~38)
2490 12:29:17.623095 ==
2491 12:29:17.626298 Dram Type= 6, Freq= 0, CH_0, rank 1
2492 12:29:17.632860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 12:29:17.632945 ==
2494 12:29:17.636668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 12:29:17.643258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2496 12:29:17.652419 [CA 0] Center 39 (9~70) winsize 62
2497 12:29:17.655726 [CA 1] Center 40 (10~70) winsize 61
2498 12:29:17.658976 [CA 2] Center 36 (6~67) winsize 62
2499 12:29:17.662292 [CA 3] Center 35 (5~66) winsize 62
2500 12:29:17.665697 [CA 4] Center 34 (4~65) winsize 62
2501 12:29:17.668876 [CA 5] Center 34 (4~64) winsize 61
2502 12:29:17.668960
2503 12:29:17.672631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 12:29:17.672717
2505 12:29:17.675845 [CATrainingPosCal] consider 2 rank data
2506 12:29:17.679061 u2DelayCellTimex100 = 270/100 ps
2507 12:29:17.682198 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2508 12:29:17.688842 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2509 12:29:17.692237 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2510 12:29:17.695585 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2511 12:29:17.698924 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2512 12:29:17.702169 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2513 12:29:17.702256
2514 12:29:17.705391 CA PerBit enable=1, Macro0, CA PI delay=34
2515 12:29:17.705478
2516 12:29:17.708699 [CBTSetCACLKResult] CA Dly = 34
2517 12:29:17.708785 CS Dly: 8 (0~41)
2518 12:29:17.712076
2519 12:29:17.715231 ----->DramcWriteLeveling(PI) begin...
2520 12:29:17.715344 ==
2521 12:29:17.719240 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 12:29:17.721870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 12:29:17.721962 ==
2524 12:29:17.725818 Write leveling (Byte 0): 31 => 31
2525 12:29:17.729223 Write leveling (Byte 1): 32 => 32
2526 12:29:17.731867 DramcWriteLeveling(PI) end<-----
2527 12:29:17.731953
2528 12:29:17.732057 ==
2529 12:29:17.735885 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 12:29:17.739150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 12:29:17.739237 ==
2532 12:29:17.742434 [Gating] SW mode calibration
2533 12:29:17.749208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2534 12:29:17.755563 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2535 12:29:17.758919 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:29:17.762319 0 15 4 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2537 12:29:17.768911 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 12:29:17.772114 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 12:29:17.775274 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 12:29:17.779112 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 12:29:17.785333 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 12:29:17.788652 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 12:29:17.791885 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
2544 12:29:17.798514 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2545 12:29:17.801845 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 12:29:17.805146 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 12:29:17.812342 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 12:29:17.815536 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:29:17.818873 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:29:17.825489 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:29:17.828794 1 1 0 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
2552 12:29:17.832120 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2553 12:29:17.838940 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 12:29:17.842176 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 12:29:17.845502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 12:29:17.852229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:29:17.855505 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:29:17.858606 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:29:17.862630 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2560 12:29:17.868675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 12:29:17.872063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:29:17.878938 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:29:17.882085 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:29:17.885310 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:29:17.888484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:29:17.895532 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:29:17.898834 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:29:17.902093 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:29:17.908794 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:29:17.911998 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:29:17.915167 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:29:17.921832 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:29:17.925055 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:29:17.928575 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:29:17.935118 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2576 12:29:17.939113 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 12:29:17.942376 Total UI for P1: 0, mck2ui 16
2578 12:29:17.945511 best dqsien dly found for B0: ( 1, 4, 0)
2579 12:29:17.948930 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 12:29:17.951815 Total UI for P1: 0, mck2ui 16
2581 12:29:17.955707 best dqsien dly found for B1: ( 1, 4, 2)
2582 12:29:17.958914 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2583 12:29:17.961933 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2584 12:29:17.962030
2585 12:29:17.965790 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2586 12:29:17.968951 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2587 12:29:17.971763 [Gating] SW calibration Done
2588 12:29:17.971866 ==
2589 12:29:17.975042 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 12:29:17.981990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 12:29:17.982085 ==
2592 12:29:17.982171 RX Vref Scan: 0
2593 12:29:17.982252
2594 12:29:17.985252 RX Vref 0 -> 0, step: 1
2595 12:29:17.985358
2596 12:29:17.988876 RX Delay -40 -> 252, step: 8
2597 12:29:17.991977 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2598 12:29:17.995168 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2599 12:29:17.998286 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2600 12:29:18.001600 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2601 12:29:18.008838 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2602 12:29:18.011629 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2603 12:29:18.015497 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2604 12:29:18.018776 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2605 12:29:18.022013 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2606 12:29:18.028653 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2607 12:29:18.031908 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2608 12:29:18.035284 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2609 12:29:18.038414 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2610 12:29:18.041761 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2611 12:29:18.048310 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2612 12:29:18.051655 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2613 12:29:18.051730 ==
2614 12:29:18.055009 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 12:29:18.058458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 12:29:18.058534 ==
2617 12:29:18.061700 DQS Delay:
2618 12:29:18.061777 DQS0 = 0, DQS1 = 0
2619 12:29:18.061840 DQM Delay:
2620 12:29:18.064921 DQM0 = 115, DQM1 = 107
2621 12:29:18.065034 DQ Delay:
2622 12:29:18.068789 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2623 12:29:18.071926 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2624 12:29:18.075199 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2625 12:29:18.081975 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2626 12:29:18.082054
2627 12:29:18.082118
2628 12:29:18.082179 ==
2629 12:29:18.085332 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 12:29:18.088432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 12:29:18.088505 ==
2632 12:29:18.088568
2633 12:29:18.088626
2634 12:29:18.091658 TX Vref Scan disable
2635 12:29:18.091727 == TX Byte 0 ==
2636 12:29:18.098562 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2637 12:29:18.101774 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2638 12:29:18.101853 == TX Byte 1 ==
2639 12:29:18.108194 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2640 12:29:18.112196 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2641 12:29:18.112269 ==
2642 12:29:18.115500 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 12:29:18.118144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 12:29:18.118219 ==
2645 12:29:18.130716 TX Vref=22, minBit 7, minWin=24, winSum=413
2646 12:29:18.134025 TX Vref=24, minBit 7, minWin=25, winSum=421
2647 12:29:18.137280 TX Vref=26, minBit 1, minWin=26, winSum=425
2648 12:29:18.141091 TX Vref=28, minBit 5, minWin=26, winSum=430
2649 12:29:18.144368 TX Vref=30, minBit 0, minWin=26, winSum=429
2650 12:29:18.150692 TX Vref=32, minBit 12, minWin=25, winSum=427
2651 12:29:18.154177 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2652 12:29:18.154258
2653 12:29:18.157451 Final TX Range 1 Vref 28
2654 12:29:18.157554
2655 12:29:18.157647 ==
2656 12:29:18.160777 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 12:29:18.164093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 12:29:18.164173 ==
2659 12:29:18.167230
2660 12:29:18.167310
2661 12:29:18.167396 TX Vref Scan disable
2662 12:29:18.170447 == TX Byte 0 ==
2663 12:29:18.173786 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2664 12:29:18.177640 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2665 12:29:18.180948 == TX Byte 1 ==
2666 12:29:18.184250 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2667 12:29:18.187566 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2668 12:29:18.187643
2669 12:29:18.190766 [DATLAT]
2670 12:29:18.190867 Freq=1200, CH0 RK0
2671 12:29:18.190958
2672 12:29:18.193958 DATLAT Default: 0xd
2673 12:29:18.194029 0, 0xFFFF, sum = 0
2674 12:29:18.197113 1, 0xFFFF, sum = 0
2675 12:29:18.197197 2, 0xFFFF, sum = 0
2676 12:29:18.200774 3, 0xFFFF, sum = 0
2677 12:29:18.200859 4, 0xFFFF, sum = 0
2678 12:29:18.203957 5, 0xFFFF, sum = 0
2679 12:29:18.204042 6, 0xFFFF, sum = 0
2680 12:29:18.207323 7, 0xFFFF, sum = 0
2681 12:29:18.211021 8, 0xFFFF, sum = 0
2682 12:29:18.211104 9, 0xFFFF, sum = 0
2683 12:29:18.214417 10, 0xFFFF, sum = 0
2684 12:29:18.214501 11, 0xFFFF, sum = 0
2685 12:29:18.217736 12, 0x0, sum = 1
2686 12:29:18.217820 13, 0x0, sum = 2
2687 12:29:18.220992 14, 0x0, sum = 3
2688 12:29:18.221076 15, 0x0, sum = 4
2689 12:29:18.221144 best_step = 13
2690 12:29:18.221204
2691 12:29:18.224202 ==
2692 12:29:18.224285 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 12:29:18.230899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 12:29:18.230983 ==
2695 12:29:18.231049 RX Vref Scan: 1
2696 12:29:18.231112
2697 12:29:18.234217 Set Vref Range= 32 -> 127
2698 12:29:18.234300
2699 12:29:18.237523 RX Vref 32 -> 127, step: 1
2700 12:29:18.237606
2701 12:29:18.240777 RX Delay -21 -> 252, step: 4
2702 12:29:18.240860
2703 12:29:18.244128 Set Vref, RX VrefLevel [Byte0]: 32
2704 12:29:18.247415 [Byte1]: 32
2705 12:29:18.247498
2706 12:29:18.250617 Set Vref, RX VrefLevel [Byte0]: 33
2707 12:29:18.254487 [Byte1]: 33
2708 12:29:18.254570
2709 12:29:18.257821 Set Vref, RX VrefLevel [Byte0]: 34
2710 12:29:18.261163 [Byte1]: 34
2711 12:29:18.265125
2712 12:29:18.265235 Set Vref, RX VrefLevel [Byte0]: 35
2713 12:29:18.268343 [Byte1]: 35
2714 12:29:18.272768
2715 12:29:18.272865 Set Vref, RX VrefLevel [Byte0]: 36
2716 12:29:18.276215 [Byte1]: 36
2717 12:29:18.280668
2718 12:29:18.280751 Set Vref, RX VrefLevel [Byte0]: 37
2719 12:29:18.284033 [Byte1]: 37
2720 12:29:18.288630
2721 12:29:18.288717 Set Vref, RX VrefLevel [Byte0]: 38
2722 12:29:18.291971 [Byte1]: 38
2723 12:29:18.297037
2724 12:29:18.297152 Set Vref, RX VrefLevel [Byte0]: 39
2725 12:29:18.300194 [Byte1]: 39
2726 12:29:18.304622
2727 12:29:18.307650 Set Vref, RX VrefLevel [Byte0]: 40
2728 12:29:18.310908 [Byte1]: 40
2729 12:29:18.311006
2730 12:29:18.314757 Set Vref, RX VrefLevel [Byte0]: 41
2731 12:29:18.317985 [Byte1]: 41
2732 12:29:18.318089
2733 12:29:18.321295 Set Vref, RX VrefLevel [Byte0]: 42
2734 12:29:18.324531 [Byte1]: 42
2735 12:29:18.328495
2736 12:29:18.328584 Set Vref, RX VrefLevel [Byte0]: 43
2737 12:29:18.331941 [Byte1]: 43
2738 12:29:18.336425
2739 12:29:18.336516 Set Vref, RX VrefLevel [Byte0]: 44
2740 12:29:18.339774 [Byte1]: 44
2741 12:29:18.344472
2742 12:29:18.344583 Set Vref, RX VrefLevel [Byte0]: 45
2743 12:29:18.347817 [Byte1]: 45
2744 12:29:18.352492
2745 12:29:18.352575 Set Vref, RX VrefLevel [Byte0]: 46
2746 12:29:18.355584 [Byte1]: 46
2747 12:29:18.359963
2748 12:29:18.360046 Set Vref, RX VrefLevel [Byte0]: 47
2749 12:29:18.363299 [Byte1]: 47
2750 12:29:18.368058
2751 12:29:18.368140 Set Vref, RX VrefLevel [Byte0]: 48
2752 12:29:18.374507 [Byte1]: 48
2753 12:29:18.374592
2754 12:29:18.377827 Set Vref, RX VrefLevel [Byte0]: 49
2755 12:29:18.381143 [Byte1]: 49
2756 12:29:18.381226
2757 12:29:18.384362 Set Vref, RX VrefLevel [Byte0]: 50
2758 12:29:18.387597 [Byte1]: 50
2759 12:29:18.391606
2760 12:29:18.391688 Set Vref, RX VrefLevel [Byte0]: 51
2761 12:29:18.394934 [Byte1]: 51
2762 12:29:18.400255
2763 12:29:18.400339 Set Vref, RX VrefLevel [Byte0]: 52
2764 12:29:18.403223 [Byte1]: 52
2765 12:29:18.407666
2766 12:29:18.407756 Set Vref, RX VrefLevel [Byte0]: 53
2767 12:29:18.410809 [Byte1]: 53
2768 12:29:18.415448
2769 12:29:18.415533 Set Vref, RX VrefLevel [Byte0]: 54
2770 12:29:18.419257 [Byte1]: 54
2771 12:29:18.423236
2772 12:29:18.423367 Set Vref, RX VrefLevel [Byte0]: 55
2773 12:29:18.427151 [Byte1]: 55
2774 12:29:18.431693
2775 12:29:18.431779 Set Vref, RX VrefLevel [Byte0]: 56
2776 12:29:18.435133 [Byte1]: 56
2777 12:29:18.439588
2778 12:29:18.439667 Set Vref, RX VrefLevel [Byte0]: 57
2779 12:29:18.442946 [Byte1]: 57
2780 12:29:18.447635
2781 12:29:18.447715 Set Vref, RX VrefLevel [Byte0]: 58
2782 12:29:18.450901 [Byte1]: 58
2783 12:29:18.455437
2784 12:29:18.455519 Set Vref, RX VrefLevel [Byte0]: 59
2785 12:29:18.458689 [Byte1]: 59
2786 12:29:18.463126
2787 12:29:18.463236 Set Vref, RX VrefLevel [Byte0]: 60
2788 12:29:18.466331 [Byte1]: 60
2789 12:29:18.470956
2790 12:29:18.471073 Set Vref, RX VrefLevel [Byte0]: 61
2791 12:29:18.474354 [Byte1]: 61
2792 12:29:18.478974
2793 12:29:18.479078 Set Vref, RX VrefLevel [Byte0]: 62
2794 12:29:18.482337 [Byte1]: 62
2795 12:29:18.486866
2796 12:29:18.486965 Set Vref, RX VrefLevel [Byte0]: 63
2797 12:29:18.489952 [Byte1]: 63
2798 12:29:18.495293
2799 12:29:18.495390 Set Vref, RX VrefLevel [Byte0]: 64
2800 12:29:18.498593 [Byte1]: 64
2801 12:29:18.502630
2802 12:29:18.502735 Set Vref, RX VrefLevel [Byte0]: 65
2803 12:29:18.505961 [Byte1]: 65
2804 12:29:18.510937
2805 12:29:18.511038 Set Vref, RX VrefLevel [Byte0]: 66
2806 12:29:18.514164 [Byte1]: 66
2807 12:29:18.518489
2808 12:29:18.518559 Set Vref, RX VrefLevel [Byte0]: 67
2809 12:29:18.522372 [Byte1]: 67
2810 12:29:18.526951
2811 12:29:18.527036 Set Vref, RX VrefLevel [Byte0]: 68
2812 12:29:18.529606 [Byte1]: 68
2813 12:29:18.534261
2814 12:29:18.534370 Set Vref, RX VrefLevel [Byte0]: 69
2815 12:29:18.537614 [Byte1]: 69
2816 12:29:18.542315
2817 12:29:18.542389 Set Vref, RX VrefLevel [Byte0]: 70
2818 12:29:18.545694 [Byte1]: 70
2819 12:29:18.550362
2820 12:29:18.550464 Final RX Vref Byte 0 = 53 to rank0
2821 12:29:18.553763 Final RX Vref Byte 1 = 51 to rank0
2822 12:29:18.557100 Final RX Vref Byte 0 = 53 to rank1
2823 12:29:18.560416 Final RX Vref Byte 1 = 51 to rank1==
2824 12:29:18.563674 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 12:29:18.570095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 12:29:18.570184 ==
2827 12:29:18.570281 DQS Delay:
2828 12:29:18.573316 DQS0 = 0, DQS1 = 0
2829 12:29:18.573398 DQM Delay:
2830 12:29:18.573482 DQM0 = 114, DQM1 = 105
2831 12:29:18.576601 DQ Delay:
2832 12:29:18.579898 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2833 12:29:18.583307 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2834 12:29:18.586594 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2835 12:29:18.590575 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2836 12:29:18.590654
2837 12:29:18.590737
2838 12:29:18.596983 [DQSOSCAuto] RK0, (LSB)MR18= 0xef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2839 12:29:18.600307 CH0 RK0: MR19=403, MR18=EF
2840 12:29:18.606903 CH0_RK0: MR19=0x403, MR18=0xEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2841 12:29:18.606991
2842 12:29:18.610200 ----->DramcWriteLeveling(PI) begin...
2843 12:29:18.610276 ==
2844 12:29:18.613275 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 12:29:18.616483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 12:29:18.616562 ==
2847 12:29:18.620297 Write leveling (Byte 0): 33 => 33
2848 12:29:18.623515 Write leveling (Byte 1): 29 => 29
2849 12:29:18.626808 DramcWriteLeveling(PI) end<-----
2850 12:29:18.626923
2851 12:29:18.627019 ==
2852 12:29:18.629773 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 12:29:18.633753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 12:29:18.636869 ==
2855 12:29:18.636978 [Gating] SW mode calibration
2856 12:29:18.646843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 12:29:18.650292 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 12:29:18.653572 0 15 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
2859 12:29:18.660322 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2860 12:29:18.663668 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:29:18.666945 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:29:18.673209 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:29:18.677251 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:29:18.679903 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 12:29:18.686519 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2866 12:29:18.689867 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2867 12:29:18.693236 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2868 12:29:18.700415 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:29:18.703768 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:29:18.706903 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:29:18.710239 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:29:18.716861 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2873 12:29:18.720046 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2874 12:29:18.723712 1 1 0 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
2875 12:29:18.730142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:29:18.733428 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:29:18.737091 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:29:18.743527 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:29:18.746962 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:29:18.750241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:29:18.756912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 12:29:18.760167 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2883 12:29:18.763518 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 12:29:18.770124 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:29:18.773574 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:29:18.777279 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:29:18.780620 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:29:18.786858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:29:18.790190 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:29:18.793616 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:29:18.800221 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:29:18.803438 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:29:18.806751 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:29:18.813462 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:29:18.816753 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:29:18.820567 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:29:18.827290 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 12:29:18.830412 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 12:29:18.833661 Total UI for P1: 0, mck2ui 16
2900 12:29:18.836805 best dqsien dly found for B0: ( 1, 3, 28)
2901 12:29:18.840534 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2902 12:29:18.847106 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 12:29:18.847221 Total UI for P1: 0, mck2ui 16
2904 12:29:18.853586 best dqsien dly found for B1: ( 1, 4, 2)
2905 12:29:18.856927 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2906 12:29:18.860281 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2907 12:29:18.860383
2908 12:29:18.863705 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2909 12:29:18.866929 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2910 12:29:18.870192 [Gating] SW calibration Done
2911 12:29:18.870296 ==
2912 12:29:18.873523 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 12:29:18.876949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 12:29:18.877034 ==
2915 12:29:18.880211 RX Vref Scan: 0
2916 12:29:18.880296
2917 12:29:18.880363 RX Vref 0 -> 0, step: 1
2918 12:29:18.880432
2919 12:29:18.884018 RX Delay -40 -> 252, step: 8
2920 12:29:18.887231 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2921 12:29:18.890666 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2922 12:29:18.897300 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 12:29:18.900603 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2924 12:29:18.903956 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 12:29:18.907129 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2926 12:29:18.910262 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2927 12:29:18.916951 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 12:29:18.920263 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2929 12:29:18.923603 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 12:29:18.927368 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 12:29:18.930563 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2932 12:29:18.937072 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2933 12:29:18.940242 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2934 12:29:18.944194 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 12:29:18.947441 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 12:29:18.947515 ==
2937 12:29:18.950715 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 12:29:18.953967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 12:29:18.957226 ==
2940 12:29:18.957327 DQS Delay:
2941 12:29:18.957420 DQS0 = 0, DQS1 = 0
2942 12:29:18.960532 DQM Delay:
2943 12:29:18.960645 DQM0 = 115, DQM1 = 106
2944 12:29:18.963898 DQ Delay:
2945 12:29:18.967179 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2946 12:29:18.970366 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2947 12:29:18.974150 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2948 12:29:18.977486 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2949 12:29:18.977596
2950 12:29:18.977688
2951 12:29:18.977785 ==
2952 12:29:18.980671 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 12:29:18.984024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 12:29:18.984126 ==
2955 12:29:18.984218
2956 12:29:18.984315
2957 12:29:18.987252 TX Vref Scan disable
2958 12:29:18.990511 == TX Byte 0 ==
2959 12:29:18.993883 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2960 12:29:18.997412 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2961 12:29:19.000671 == TX Byte 1 ==
2962 12:29:19.003989 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2963 12:29:19.007155 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2964 12:29:19.007256 ==
2965 12:29:19.010833 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 12:29:19.013961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 12:29:19.017264 ==
2968 12:29:19.027295 TX Vref=22, minBit 0, minWin=25, winSum=419
2969 12:29:19.030683 TX Vref=24, minBit 1, minWin=25, winSum=425
2970 12:29:19.034363 TX Vref=26, minBit 0, minWin=26, winSum=426
2971 12:29:19.037476 TX Vref=28, minBit 3, minWin=26, winSum=436
2972 12:29:19.040631 TX Vref=30, minBit 3, minWin=26, winSum=433
2973 12:29:19.044346 TX Vref=32, minBit 3, minWin=26, winSum=434
2974 12:29:19.050953 [TxChooseVref] Worse bit 3, Min win 26, Win sum 436, Final Vref 28
2975 12:29:19.051060
2976 12:29:19.054143 Final TX Range 1 Vref 28
2977 12:29:19.054245
2978 12:29:19.054346 ==
2979 12:29:19.057356 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 12:29:19.060850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 12:29:19.060957 ==
2982 12:29:19.061062
2983 12:29:19.061153
2984 12:29:19.064185 TX Vref Scan disable
2985 12:29:19.067607 == TX Byte 0 ==
2986 12:29:19.070838 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2987 12:29:19.074165 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2988 12:29:19.077489 == TX Byte 1 ==
2989 12:29:19.080795 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2990 12:29:19.084078 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2991 12:29:19.084188
2992 12:29:19.087321 [DATLAT]
2993 12:29:19.087408 Freq=1200, CH0 RK1
2994 12:29:19.087472
2995 12:29:19.090556 DATLAT Default: 0xd
2996 12:29:19.090624 0, 0xFFFF, sum = 0
2997 12:29:19.094468 1, 0xFFFF, sum = 0
2998 12:29:19.094540 2, 0xFFFF, sum = 0
2999 12:29:19.097224 3, 0xFFFF, sum = 0
3000 12:29:19.097324 4, 0xFFFF, sum = 0
3001 12:29:19.100493 5, 0xFFFF, sum = 0
3002 12:29:19.103762 6, 0xFFFF, sum = 0
3003 12:29:19.103836 7, 0xFFFF, sum = 0
3004 12:29:19.106996 8, 0xFFFF, sum = 0
3005 12:29:19.107063 9, 0xFFFF, sum = 0
3006 12:29:19.110310 10, 0xFFFF, sum = 0
3007 12:29:19.110378 11, 0xFFFF, sum = 0
3008 12:29:19.114306 12, 0x0, sum = 1
3009 12:29:19.114382 13, 0x0, sum = 2
3010 12:29:19.117410 14, 0x0, sum = 3
3011 12:29:19.117503 15, 0x0, sum = 4
3012 12:29:19.117567 best_step = 13
3013 12:29:19.117630
3014 12:29:19.120658 ==
3015 12:29:19.123901 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:29:19.127222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:29:19.127318 ==
3018 12:29:19.127418 RX Vref Scan: 0
3019 12:29:19.127506
3020 12:29:19.130474 RX Vref 0 -> 0, step: 1
3021 12:29:19.130543
3022 12:29:19.133775 RX Delay -21 -> 252, step: 4
3023 12:29:19.137053 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3024 12:29:19.143904 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3025 12:29:19.147815 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3026 12:29:19.150991 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3027 12:29:19.154214 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3028 12:29:19.157511 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3029 12:29:19.160774 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3030 12:29:19.167970 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3031 12:29:19.171237 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3032 12:29:19.174478 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3033 12:29:19.177671 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3034 12:29:19.181048 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 12:29:19.187466 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3036 12:29:19.190809 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3037 12:29:19.194185 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3038 12:29:19.197363 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3039 12:29:19.197472 ==
3040 12:29:19.200762 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 12:29:19.204681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 12:29:19.207955 ==
3043 12:29:19.208072 DQS Delay:
3044 12:29:19.208140 DQS0 = 0, DQS1 = 0
3045 12:29:19.211191 DQM Delay:
3046 12:29:19.211298 DQM0 = 114, DQM1 = 104
3047 12:29:19.214523 DQ Delay:
3048 12:29:19.217879 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3049 12:29:19.220951 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3050 12:29:19.224262 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3051 12:29:19.227660 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3052 12:29:19.227734
3053 12:29:19.227798
3054 12:29:19.234189 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3055 12:29:19.237462 CH0 RK1: MR19=403, MR18=3F4
3056 12:29:19.244259 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3057 12:29:19.247453 [RxdqsGatingPostProcess] freq 1200
3058 12:29:19.254446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 12:29:19.254560 best DQS0 dly(2T, 0.5T) = (0, 12)
3060 12:29:19.257681 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 12:29:19.260880 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3062 12:29:19.264525 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 12:29:19.267840 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 12:29:19.271265 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 12:29:19.274649 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 12:29:19.277873 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 12:29:19.281113 Pre-setting of DQS Precalculation
3068 12:29:19.284509 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 12:29:19.284584 ==
3070 12:29:19.287825 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 12:29:19.294301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 12:29:19.294411 ==
3073 12:29:19.297591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 12:29:19.304151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 12:29:19.313355 [CA 0] Center 38 (8~68) winsize 61
3076 12:29:19.315995 [CA 1] Center 38 (8~68) winsize 61
3077 12:29:19.319323 [CA 2] Center 35 (5~65) winsize 61
3078 12:29:19.322673 [CA 3] Center 34 (4~65) winsize 62
3079 12:29:19.326042 [CA 4] Center 34 (4~65) winsize 62
3080 12:29:19.329972 [CA 5] Center 34 (4~64) winsize 61
3081 12:29:19.330051
3082 12:29:19.333244 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 12:29:19.333335
3084 12:29:19.335914 [CATrainingPosCal] consider 1 rank data
3085 12:29:19.339269 u2DelayCellTimex100 = 270/100 ps
3086 12:29:19.343208 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3087 12:29:19.349427 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 12:29:19.352488 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3089 12:29:19.356361 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3090 12:29:19.359707 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 12:29:19.362859 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3092 12:29:19.362968
3093 12:29:19.366039 CA PerBit enable=1, Macro0, CA PI delay=34
3094 12:29:19.366143
3095 12:29:19.369339 [CBTSetCACLKResult] CA Dly = 34
3096 12:29:19.372703 CS Dly: 6 (0~37)
3097 12:29:19.372810 ==
3098 12:29:19.376035 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 12:29:19.379232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 12:29:19.379334 ==
3101 12:29:19.382552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 12:29:19.388939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 12:29:19.398276 [CA 0] Center 38 (8~68) winsize 61
3104 12:29:19.402225 [CA 1] Center 38 (9~68) winsize 60
3105 12:29:19.405381 [CA 2] Center 34 (4~65) winsize 62
3106 12:29:19.408627 [CA 3] Center 34 (4~65) winsize 62
3107 12:29:19.411952 [CA 4] Center 34 (4~65) winsize 62
3108 12:29:19.415209 [CA 5] Center 33 (3~63) winsize 61
3109 12:29:19.415285
3110 12:29:19.418547 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 12:29:19.418623
3112 12:29:19.421909 [CATrainingPosCal] consider 2 rank data
3113 12:29:19.425172 u2DelayCellTimex100 = 270/100 ps
3114 12:29:19.428472 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3115 12:29:19.431664 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3116 12:29:19.438985 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 12:29:19.441689 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3118 12:29:19.444987 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 12:29:19.449067 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3120 12:29:19.449146
3121 12:29:19.452120 CA PerBit enable=1, Macro0, CA PI delay=33
3122 12:29:19.452227
3123 12:29:19.455136 [CBTSetCACLKResult] CA Dly = 33
3124 12:29:19.455240 CS Dly: 7 (0~40)
3125 12:29:19.455332
3126 12:29:19.458294 ----->DramcWriteLeveling(PI) begin...
3127 12:29:19.462137 ==
3128 12:29:19.462258 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 12:29:19.468604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 12:29:19.468691 ==
3131 12:29:19.471974 Write leveling (Byte 0): 26 => 26
3132 12:29:19.475187 Write leveling (Byte 1): 27 => 27
3133 12:29:19.478546 DramcWriteLeveling(PI) end<-----
3134 12:29:19.478633
3135 12:29:19.478700 ==
3136 12:29:19.481830 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 12:29:19.485105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 12:29:19.485183 ==
3139 12:29:19.488397 [Gating] SW mode calibration
3140 12:29:19.494924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 12:29:19.501559 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 12:29:19.504803 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3143 12:29:19.508197 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:29:19.511953 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:29:19.518522 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:29:19.521794 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 12:29:19.525113 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 12:29:19.531887 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 12:29:19.534980 0 15 28 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3150 12:29:19.538276 1 0 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3151 12:29:19.544932 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:29:19.548242 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:29:19.551438 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:29:19.558426 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 12:29:19.561670 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 12:29:19.564844 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 12:29:19.571451 1 0 28 | B1->B0 | 2a2a 2424 | 0 0 | (1 1) (1 1)
3158 12:29:19.574691 1 1 0 | B1->B0 | 4242 2e2e | 0 0 | (0 0) (0 0)
3159 12:29:19.577965 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:29:19.584603 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:29:19.588516 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:29:19.591180 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:29:19.598310 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 12:29:19.601681 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:29:19.604932 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3166 12:29:19.611562 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 12:29:19.614846 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:29:19.618138 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:29:19.621593 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:29:19.628173 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:29:19.631294 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:29:19.634589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:29:19.641434 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:29:19.644971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:29:19.647914 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:29:19.654678 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:29:19.657872 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:29:19.661562 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:29:19.667901 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:29:19.671127 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:29:19.675039 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3182 12:29:19.681446 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3183 12:29:19.684924 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:29:19.688183 Total UI for P1: 0, mck2ui 16
3185 12:29:19.691510 best dqsien dly found for B0: ( 1, 3, 30)
3186 12:29:19.694782 Total UI for P1: 0, mck2ui 16
3187 12:29:19.698098 best dqsien dly found for B1: ( 1, 3, 30)
3188 12:29:19.701423 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3189 12:29:19.704806 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3190 12:29:19.704886
3191 12:29:19.708027 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 12:29:19.711411 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3193 12:29:19.715293 [Gating] SW calibration Done
3194 12:29:19.715405 ==
3195 12:29:19.717823 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 12:29:19.721771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 12:29:19.721873 ==
3198 12:29:19.724477 RX Vref Scan: 0
3199 12:29:19.724559
3200 12:29:19.727944 RX Vref 0 -> 0, step: 1
3201 12:29:19.728036
3202 12:29:19.728133 RX Delay -40 -> 252, step: 8
3203 12:29:19.734456 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3204 12:29:19.737875 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 12:29:19.741152 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 12:29:19.744448 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3207 12:29:19.748517 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 12:29:19.754597 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3209 12:29:19.757878 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3210 12:29:19.761247 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3211 12:29:19.764470 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3212 12:29:19.768096 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3213 12:29:19.774502 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3214 12:29:19.777682 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3215 12:29:19.781738 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3216 12:29:19.784820 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
3217 12:29:19.788119 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 12:29:19.794719 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3219 12:29:19.794904 ==
3220 12:29:19.798023 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 12:29:19.801270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 12:29:19.801384 ==
3223 12:29:19.801481 DQS Delay:
3224 12:29:19.804587 DQS0 = 0, DQS1 = 0
3225 12:29:19.804672 DQM Delay:
3226 12:29:19.808065 DQM0 = 116, DQM1 = 109
3227 12:29:19.808149 DQ Delay:
3228 12:29:19.811418 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3229 12:29:19.814682 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3230 12:29:19.818036 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3231 12:29:19.821427 DQ12 =123, DQ13 =119, DQ14 =111, DQ15 =111
3232 12:29:19.821540
3233 12:29:19.821636
3234 12:29:19.824537 ==
3235 12:29:19.824622 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 12:29:19.831178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 12:29:19.831289 ==
3238 12:29:19.831388
3239 12:29:19.831454
3240 12:29:19.834390 TX Vref Scan disable
3241 12:29:19.834465 == TX Byte 0 ==
3242 12:29:19.837672 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3243 12:29:19.844348 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3244 12:29:19.844453 == TX Byte 1 ==
3245 12:29:19.848257 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3246 12:29:19.854774 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3247 12:29:19.854864 ==
3248 12:29:19.858083 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 12:29:19.861340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 12:29:19.861416 ==
3251 12:29:19.872720 TX Vref=22, minBit 8, minWin=24, winSum=410
3252 12:29:19.876482 TX Vref=24, minBit 1, minWin=24, winSum=411
3253 12:29:19.879647 TX Vref=26, minBit 0, minWin=26, winSum=418
3254 12:29:19.882806 TX Vref=28, minBit 1, minWin=26, winSum=429
3255 12:29:19.886083 TX Vref=30, minBit 1, minWin=26, winSum=427
3256 12:29:19.889340 TX Vref=32, minBit 11, minWin=25, winSum=425
3257 12:29:19.896515 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3258 12:29:19.896630
3259 12:29:19.899868 Final TX Range 1 Vref 28
3260 12:29:19.899948
3261 12:29:19.900013 ==
3262 12:29:19.903194 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 12:29:19.906429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 12:29:19.906539 ==
3265 12:29:19.906639
3266 12:29:19.909812
3267 12:29:19.909914 TX Vref Scan disable
3268 12:29:19.913160 == TX Byte 0 ==
3269 12:29:19.916399 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 12:29:19.919618 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 12:29:19.922988 == TX Byte 1 ==
3272 12:29:19.926259 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3273 12:29:19.929401 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3274 12:29:19.929478
3275 12:29:19.933214 [DATLAT]
3276 12:29:19.933300 Freq=1200, CH1 RK0
3277 12:29:19.933377
3278 12:29:19.936423 DATLAT Default: 0xd
3279 12:29:19.936498 0, 0xFFFF, sum = 0
3280 12:29:19.939789 1, 0xFFFF, sum = 0
3281 12:29:19.939867 2, 0xFFFF, sum = 0
3282 12:29:19.943117 3, 0xFFFF, sum = 0
3283 12:29:19.943235 4, 0xFFFF, sum = 0
3284 12:29:19.946388 5, 0xFFFF, sum = 0
3285 12:29:19.946487 6, 0xFFFF, sum = 0
3286 12:29:19.949631 7, 0xFFFF, sum = 0
3287 12:29:19.949705 8, 0xFFFF, sum = 0
3288 12:29:19.952857 9, 0xFFFF, sum = 0
3289 12:29:19.956781 10, 0xFFFF, sum = 0
3290 12:29:19.956862 11, 0xFFFF, sum = 0
3291 12:29:19.959527 12, 0x0, sum = 1
3292 12:29:19.959601 13, 0x0, sum = 2
3293 12:29:19.959665 14, 0x0, sum = 3
3294 12:29:19.962868 15, 0x0, sum = 4
3295 12:29:19.962946 best_step = 13
3296 12:29:19.963009
3297 12:29:19.966196 ==
3298 12:29:19.966272 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:29:19.973180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:29:19.973266 ==
3301 12:29:19.973331 RX Vref Scan: 1
3302 12:29:19.973393
3303 12:29:19.976368 Set Vref Range= 32 -> 127
3304 12:29:19.976451
3305 12:29:19.979470 RX Vref 32 -> 127, step: 1
3306 12:29:19.979552
3307 12:29:19.983427 RX Delay -21 -> 252, step: 4
3308 12:29:19.983508
3309 12:29:19.986771 Set Vref, RX VrefLevel [Byte0]: 32
3310 12:29:19.989887 [Byte1]: 32
3311 12:29:19.989968
3312 12:29:19.993125 Set Vref, RX VrefLevel [Byte0]: 33
3313 12:29:19.996459 [Byte1]: 33
3314 12:29:19.996549
3315 12:29:19.999701 Set Vref, RX VrefLevel [Byte0]: 34
3316 12:29:20.002963 [Byte1]: 34
3317 12:29:20.006831
3318 12:29:20.006946 Set Vref, RX VrefLevel [Byte0]: 35
3319 12:29:20.010124 [Byte1]: 35
3320 12:29:20.014776
3321 12:29:20.014883 Set Vref, RX VrefLevel [Byte0]: 36
3322 12:29:20.018193 [Byte1]: 36
3323 12:29:20.022913
3324 12:29:20.023018 Set Vref, RX VrefLevel [Byte0]: 37
3325 12:29:20.026199 [Byte1]: 37
3326 12:29:20.030898
3327 12:29:20.030979 Set Vref, RX VrefLevel [Byte0]: 38
3328 12:29:20.034067 [Byte1]: 38
3329 12:29:20.038606
3330 12:29:20.038718 Set Vref, RX VrefLevel [Byte0]: 39
3331 12:29:20.041761 [Byte1]: 39
3332 12:29:20.046925
3333 12:29:20.047040 Set Vref, RX VrefLevel [Byte0]: 40
3334 12:29:20.050195 [Byte1]: 40
3335 12:29:20.054873
3336 12:29:20.054980 Set Vref, RX VrefLevel [Byte0]: 41
3337 12:29:20.057919 [Byte1]: 41
3338 12:29:20.062579
3339 12:29:20.062677 Set Vref, RX VrefLevel [Byte0]: 42
3340 12:29:20.065853 [Byte1]: 42
3341 12:29:20.070503
3342 12:29:20.070606 Set Vref, RX VrefLevel [Byte0]: 43
3343 12:29:20.073877 [Byte1]: 43
3344 12:29:20.078362
3345 12:29:20.078449 Set Vref, RX VrefLevel [Byte0]: 44
3346 12:29:20.081496 [Byte1]: 44
3347 12:29:20.086625
3348 12:29:20.086709 Set Vref, RX VrefLevel [Byte0]: 45
3349 12:29:20.089848 [Byte1]: 45
3350 12:29:20.094213
3351 12:29:20.094320 Set Vref, RX VrefLevel [Byte0]: 46
3352 12:29:20.097578 [Byte1]: 46
3353 12:29:20.102239
3354 12:29:20.102340 Set Vref, RX VrefLevel [Byte0]: 47
3355 12:29:20.105482 [Byte1]: 47
3356 12:29:20.110085
3357 12:29:20.110183 Set Vref, RX VrefLevel [Byte0]: 48
3358 12:29:20.113276 [Byte1]: 48
3359 12:29:20.117893
3360 12:29:20.117997 Set Vref, RX VrefLevel [Byte0]: 49
3361 12:29:20.121325 [Byte1]: 49
3362 12:29:20.125922
3363 12:29:20.125994 Set Vref, RX VrefLevel [Byte0]: 50
3364 12:29:20.129282 [Byte1]: 50
3365 12:29:20.133834
3366 12:29:20.133915 Set Vref, RX VrefLevel [Byte0]: 51
3367 12:29:20.137099 [Byte1]: 51
3368 12:29:20.141624
3369 12:29:20.141705 Set Vref, RX VrefLevel [Byte0]: 52
3370 12:29:20.144970 [Byte1]: 52
3371 12:29:20.149567
3372 12:29:20.149646 Set Vref, RX VrefLevel [Byte0]: 53
3373 12:29:20.152854 [Byte1]: 53
3374 12:29:20.157349
3375 12:29:20.157463 Set Vref, RX VrefLevel [Byte0]: 54
3376 12:29:20.160659 [Byte1]: 54
3377 12:29:20.165162
3378 12:29:20.165268 Set Vref, RX VrefLevel [Byte0]: 55
3379 12:29:20.168484 [Byte1]: 55
3380 12:29:20.173713
3381 12:29:20.173816 Set Vref, RX VrefLevel [Byte0]: 56
3382 12:29:20.176975 [Byte1]: 56
3383 12:29:20.181620
3384 12:29:20.181700 Set Vref, RX VrefLevel [Byte0]: 57
3385 12:29:20.184818 [Byte1]: 57
3386 12:29:20.189203
3387 12:29:20.189283 Set Vref, RX VrefLevel [Byte0]: 58
3388 12:29:20.192410 [Byte1]: 58
3389 12:29:20.197463
3390 12:29:20.197544 Set Vref, RX VrefLevel [Byte0]: 59
3391 12:29:20.200495 [Byte1]: 59
3392 12:29:20.205043
3393 12:29:20.205124 Set Vref, RX VrefLevel [Byte0]: 60
3394 12:29:20.208180 [Byte1]: 60
3395 12:29:20.212849
3396 12:29:20.212942 Set Vref, RX VrefLevel [Byte0]: 61
3397 12:29:20.216180 [Byte1]: 61
3398 12:29:20.220875
3399 12:29:20.220960 Set Vref, RX VrefLevel [Byte0]: 62
3400 12:29:20.224188 [Byte1]: 62
3401 12:29:20.228989
3402 12:29:20.229065 Set Vref, RX VrefLevel [Byte0]: 63
3403 12:29:20.232172 [Byte1]: 63
3404 12:29:20.236830
3405 12:29:20.236941 Set Vref, RX VrefLevel [Byte0]: 64
3406 12:29:20.240237 [Byte1]: 64
3407 12:29:20.244833
3408 12:29:20.244923 Set Vref, RX VrefLevel [Byte0]: 65
3409 12:29:20.248123 [Byte1]: 65
3410 12:29:20.252914
3411 12:29:20.252989 Set Vref, RX VrefLevel [Byte0]: 66
3412 12:29:20.256207 [Byte1]: 66
3413 12:29:20.260271
3414 12:29:20.260353 Set Vref, RX VrefLevel [Byte0]: 67
3415 12:29:20.263665 [Byte1]: 67
3416 12:29:20.268195
3417 12:29:20.268297 Set Vref, RX VrefLevel [Byte0]: 68
3418 12:29:20.272128 [Byte1]: 68
3419 12:29:20.276666
3420 12:29:20.276776 Set Vref, RX VrefLevel [Byte0]: 69
3421 12:29:20.280088 [Byte1]: 69
3422 12:29:20.284601
3423 12:29:20.284703 Set Vref, RX VrefLevel [Byte0]: 70
3424 12:29:20.287821 [Byte1]: 70
3425 12:29:20.292399
3426 12:29:20.292511 Set Vref, RX VrefLevel [Byte0]: 71
3427 12:29:20.298488 [Byte1]: 71
3428 12:29:20.298572
3429 12:29:20.301743 Set Vref, RX VrefLevel [Byte0]: 72
3430 12:29:20.305546 [Byte1]: 72
3431 12:29:20.305624
3432 12:29:20.308765 Final RX Vref Byte 0 = 58 to rank0
3433 12:29:20.312038 Final RX Vref Byte 1 = 49 to rank0
3434 12:29:20.315243 Final RX Vref Byte 0 = 58 to rank1
3435 12:29:20.318645 Final RX Vref Byte 1 = 49 to rank1==
3436 12:29:20.321910 Dram Type= 6, Freq= 0, CH_1, rank 0
3437 12:29:20.325199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 12:29:20.325284 ==
3439 12:29:20.328614 DQS Delay:
3440 12:29:20.328706 DQS0 = 0, DQS1 = 0
3441 12:29:20.331866 DQM Delay:
3442 12:29:20.331978 DQM0 = 116, DQM1 = 108
3443 12:29:20.332079 DQ Delay:
3444 12:29:20.338479 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3445 12:29:20.341810 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3446 12:29:20.345206 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3447 12:29:20.348552 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =112
3448 12:29:20.348636
3449 12:29:20.348702
3450 12:29:20.355519 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3451 12:29:20.358783 CH1 RK0: MR19=303, MR18=FCE0
3452 12:29:20.365598 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3453 12:29:20.365689
3454 12:29:20.368212 ----->DramcWriteLeveling(PI) begin...
3455 12:29:20.368288 ==
3456 12:29:20.372141 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 12:29:20.375345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 12:29:20.375432 ==
3459 12:29:20.378680 Write leveling (Byte 0): 25 => 25
3460 12:29:20.382030 Write leveling (Byte 1): 27 => 27
3461 12:29:20.385348 DramcWriteLeveling(PI) end<-----
3462 12:29:20.385477
3463 12:29:20.385584 ==
3464 12:29:20.388476 Dram Type= 6, Freq= 0, CH_1, rank 1
3465 12:29:20.391781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 12:29:20.394923 ==
3467 12:29:20.395046 [Gating] SW mode calibration
3468 12:29:20.401849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3469 12:29:20.408344 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3470 12:29:20.411650 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3471 12:29:20.418766 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 12:29:20.422163 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 12:29:20.424793 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 12:29:20.431493 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3475 12:29:20.434903 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 12:29:20.438122 0 15 24 | B1->B0 | 3232 2626 | 0 0 | (0 0) (1 0)
3477 12:29:20.444922 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
3478 12:29:20.448205 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 12:29:20.451549 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 12:29:20.458677 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3481 12:29:20.461416 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 12:29:20.465278 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 12:29:20.471907 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3484 12:29:20.475178 1 0 24 | B1->B0 | 2626 4141 | 0 0 | (0 0) (0 0)
3485 12:29:20.478354 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3486 12:29:20.481574 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 12:29:20.488196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 12:29:20.491556 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 12:29:20.494715 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 12:29:20.501517 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 12:29:20.504608 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3492 12:29:20.507863 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3493 12:29:20.514860 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3494 12:29:20.518002 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:29:20.521306 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:29:20.527904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:29:20.531217 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:29:20.534491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:29:20.541011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:29:20.544954 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:29:20.548123 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 12:29:20.554741 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:29:20.558067 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 12:29:20.561270 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 12:29:20.567876 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 12:29:20.571235 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 12:29:20.574527 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3508 12:29:20.581071 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3509 12:29:20.584298 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3510 12:29:20.587567 Total UI for P1: 0, mck2ui 16
3511 12:29:20.591606 best dqsien dly found for B0: ( 1, 3, 22)
3512 12:29:20.594208 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 12:29:20.597486 Total UI for P1: 0, mck2ui 16
3514 12:29:20.600819 best dqsien dly found for B1: ( 1, 3, 28)
3515 12:29:20.604653 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3516 12:29:20.607882 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3517 12:29:20.607987
3518 12:29:20.611003 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3519 12:29:20.617935 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3520 12:29:20.618043 [Gating] SW calibration Done
3521 12:29:20.621238 ==
3522 12:29:20.621323 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 12:29:20.627719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 12:29:20.627813 ==
3525 12:29:20.627882 RX Vref Scan: 0
3526 12:29:20.627945
3527 12:29:20.630864 RX Vref 0 -> 0, step: 1
3528 12:29:20.630968
3529 12:29:20.634148 RX Delay -40 -> 252, step: 8
3530 12:29:20.637599 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3531 12:29:20.640898 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3532 12:29:20.644112 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3533 12:29:20.650905 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3534 12:29:20.654283 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3535 12:29:20.657509 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3536 12:29:20.660847 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3537 12:29:20.664101 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3538 12:29:20.670551 iDelay=192, Bit 8, Center 95 (24 ~ 167) 144
3539 12:29:20.673861 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3540 12:29:20.677279 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3541 12:29:20.681080 iDelay=192, Bit 11, Center 99 (32 ~ 167) 136
3542 12:29:20.684341 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3543 12:29:20.690904 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3544 12:29:20.694255 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3545 12:29:20.697477 iDelay=192, Bit 15, Center 115 (48 ~ 183) 136
3546 12:29:20.697583 ==
3547 12:29:20.700794 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 12:29:20.704130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 12:29:20.704233 ==
3550 12:29:20.707480 DQS Delay:
3551 12:29:20.707556 DQS0 = 0, DQS1 = 0
3552 12:29:20.710781 DQM Delay:
3553 12:29:20.710886 DQM0 = 112, DQM1 = 108
3554 12:29:20.710979 DQ Delay:
3555 12:29:20.713967 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3556 12:29:20.720814 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3557 12:29:20.723989 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3558 12:29:20.727306 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
3559 12:29:20.727409
3560 12:29:20.727504
3561 12:29:20.727594 ==
3562 12:29:20.730547 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 12:29:20.734451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 12:29:20.734536 ==
3565 12:29:20.734603
3566 12:29:20.734665
3567 12:29:20.737229 TX Vref Scan disable
3568 12:29:20.737313 == TX Byte 0 ==
3569 12:29:20.743880 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3570 12:29:20.747212 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3571 12:29:20.747296 == TX Byte 1 ==
3572 12:29:20.753831 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3573 12:29:20.757210 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3574 12:29:20.757294 ==
3575 12:29:20.760504 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 12:29:20.763807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 12:29:20.763891 ==
3578 12:29:20.776882 TX Vref=22, minBit 3, minWin=25, winSum=415
3579 12:29:20.780063 TX Vref=24, minBit 2, minWin=25, winSum=418
3580 12:29:20.783434 TX Vref=26, minBit 1, minWin=25, winSum=428
3581 12:29:20.786737 TX Vref=28, minBit 9, minWin=26, winSum=431
3582 12:29:20.789846 TX Vref=30, minBit 11, minWin=26, winSum=433
3583 12:29:20.796479 TX Vref=32, minBit 1, minWin=26, winSum=431
3584 12:29:20.799847 [TxChooseVref] Worse bit 11, Min win 26, Win sum 433, Final Vref 30
3585 12:29:20.799931
3586 12:29:20.803151 Final TX Range 1 Vref 30
3587 12:29:20.803228
3588 12:29:20.803294 ==
3589 12:29:20.806464 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 12:29:20.809727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 12:29:20.812878 ==
3592 12:29:20.812961
3593 12:29:20.813085
3594 12:29:20.813190 TX Vref Scan disable
3595 12:29:20.816863 == TX Byte 0 ==
3596 12:29:20.820129 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3597 12:29:20.826527 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3598 12:29:20.826643 == TX Byte 1 ==
3599 12:29:20.829843 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3600 12:29:20.836667 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3601 12:29:20.836792
3602 12:29:20.836879 [DATLAT]
3603 12:29:20.836960 Freq=1200, CH1 RK1
3604 12:29:20.837051
3605 12:29:20.839718 DATLAT Default: 0xd
3606 12:29:20.839798 0, 0xFFFF, sum = 0
3607 12:29:20.842947 1, 0xFFFF, sum = 0
3608 12:29:20.846305 2, 0xFFFF, sum = 0
3609 12:29:20.846430 3, 0xFFFF, sum = 0
3610 12:29:20.849680 4, 0xFFFF, sum = 0
3611 12:29:20.849806 5, 0xFFFF, sum = 0
3612 12:29:20.852917 6, 0xFFFF, sum = 0
3613 12:29:20.853000 7, 0xFFFF, sum = 0
3614 12:29:20.856124 8, 0xFFFF, sum = 0
3615 12:29:20.856241 9, 0xFFFF, sum = 0
3616 12:29:20.859433 10, 0xFFFF, sum = 0
3617 12:29:20.859511 11, 0xFFFF, sum = 0
3618 12:29:20.862842 12, 0x0, sum = 1
3619 12:29:20.862940 13, 0x0, sum = 2
3620 12:29:20.866219 14, 0x0, sum = 3
3621 12:29:20.866311 15, 0x0, sum = 4
3622 12:29:20.869443 best_step = 13
3623 12:29:20.869593
3624 12:29:20.869726 ==
3625 12:29:20.872942 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 12:29:20.876166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 12:29:20.876248 ==
3628 12:29:20.876340 RX Vref Scan: 0
3629 12:29:20.879394
3630 12:29:20.879476 RX Vref 0 -> 0, step: 1
3631 12:29:20.879543
3632 12:29:20.882653 RX Delay -21 -> 252, step: 4
3633 12:29:20.889463 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3634 12:29:20.892786 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3635 12:29:20.896080 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3636 12:29:20.899389 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3637 12:29:20.902592 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3638 12:29:20.905940 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3639 12:29:20.912695 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3640 12:29:20.915844 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3641 12:29:20.919029 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3642 12:29:20.922818 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3643 12:29:20.925894 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3644 12:29:20.932471 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3645 12:29:20.936245 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3646 12:29:20.939528 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3647 12:29:20.942666 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3648 12:29:20.949246 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3649 12:29:20.949353 ==
3650 12:29:20.952520 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 12:29:20.955917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 12:29:20.956021 ==
3653 12:29:20.956139 DQS Delay:
3654 12:29:20.959258 DQS0 = 0, DQS1 = 0
3655 12:29:20.959364 DQM Delay:
3656 12:29:20.962545 DQM0 = 113, DQM1 = 108
3657 12:29:20.962647 DQ Delay:
3658 12:29:20.965969 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3659 12:29:20.969265 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3660 12:29:20.972539 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3661 12:29:20.975945 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =116
3662 12:29:20.976029
3663 12:29:20.976097
3664 12:29:20.985629 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3665 12:29:20.988839 CH1 RK1: MR19=303, MR18=F8FF
3666 12:29:20.992200 CH1_RK1: MR19=0x303, MR18=0xF8FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3667 12:29:20.995537 [RxdqsGatingPostProcess] freq 1200
3668 12:29:21.002158 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3669 12:29:21.005374 best DQS0 dly(2T, 0.5T) = (0, 11)
3670 12:29:21.009234 best DQS1 dly(2T, 0.5T) = (0, 11)
3671 12:29:21.012524 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3672 12:29:21.015820 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3673 12:29:21.018987 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 12:29:21.022155 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 12:29:21.025333 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 12:29:21.029011 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 12:29:21.032158 Pre-setting of DQS Precalculation
3678 12:29:21.035367 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3679 12:29:21.041818 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3680 12:29:21.048932 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3681 12:29:21.049043
3682 12:29:21.052215
3683 12:29:21.052359 [Calibration Summary] 2400 Mbps
3684 12:29:21.055480 CH 0, Rank 0
3685 12:29:21.055589 SW Impedance : PASS
3686 12:29:21.058864 DUTY Scan : NO K
3687 12:29:21.062173 ZQ Calibration : PASS
3688 12:29:21.062343 Jitter Meter : NO K
3689 12:29:21.065513 CBT Training : PASS
3690 12:29:21.068793 Write leveling : PASS
3691 12:29:21.068948 RX DQS gating : PASS
3692 12:29:21.072080 RX DQ/DQS(RDDQC) : PASS
3693 12:29:21.075197 TX DQ/DQS : PASS
3694 12:29:21.075334 RX DATLAT : PASS
3695 12:29:21.078559 RX DQ/DQS(Engine): PASS
3696 12:29:21.081812 TX OE : NO K
3697 12:29:21.081955 All Pass.
3698 12:29:21.082069
3699 12:29:21.082162 CH 0, Rank 1
3700 12:29:21.085245 SW Impedance : PASS
3701 12:29:21.088376 DUTY Scan : NO K
3702 12:29:21.088550 ZQ Calibration : PASS
3703 12:29:21.091733 Jitter Meter : NO K
3704 12:29:21.095058 CBT Training : PASS
3705 12:29:21.095234 Write leveling : PASS
3706 12:29:21.098389 RX DQS gating : PASS
3707 12:29:21.098500 RX DQ/DQS(RDDQC) : PASS
3708 12:29:21.101827 TX DQ/DQS : PASS
3709 12:29:21.105290 RX DATLAT : PASS
3710 12:29:21.105443 RX DQ/DQS(Engine): PASS
3711 12:29:21.130558 TX OE : NO K
3712 12:29:21.130692 All Pass.
3713 12:29:21.130796
3714 12:29:21.131089 CH 1, Rank 0
3715 12:29:21.131191 SW Impedance : PASS
3716 12:29:21.131284 DUTY Scan : NO K
3717 12:29:21.131382 ZQ Calibration : PASS
3718 12:29:21.131472 Jitter Meter : NO K
3719 12:29:21.131561 CBT Training : PASS
3720 12:29:21.131659 Write leveling : PASS
3721 12:29:21.131748 RX DQS gating : PASS
3722 12:29:21.131850 RX DQ/DQS(RDDQC) : PASS
3723 12:29:21.131955 TX DQ/DQS : PASS
3724 12:29:21.132056 RX DATLAT : PASS
3725 12:29:21.135014 RX DQ/DQS(Engine): PASS
3726 12:29:21.138201 TX OE : NO K
3727 12:29:21.138314 All Pass.
3728 12:29:21.138413
3729 12:29:21.138509 CH 1, Rank 1
3730 12:29:21.141414 SW Impedance : PASS
3731 12:29:21.144633 DUTY Scan : NO K
3732 12:29:21.144750 ZQ Calibration : PASS
3733 12:29:21.148014 Jitter Meter : NO K
3734 12:29:21.148103 CBT Training : PASS
3735 12:29:21.151643 Write leveling : PASS
3736 12:29:21.154843 RX DQS gating : PASS
3737 12:29:21.154953 RX DQ/DQS(RDDQC) : PASS
3738 12:29:21.158161 TX DQ/DQS : PASS
3739 12:29:21.161440 RX DATLAT : PASS
3740 12:29:21.161545 RX DQ/DQS(Engine): PASS
3741 12:29:21.164700 TX OE : NO K
3742 12:29:21.164812 All Pass.
3743 12:29:21.164915
3744 12:29:21.168065 DramC Write-DBI off
3745 12:29:21.171517 PER_BANK_REFRESH: Hybrid Mode
3746 12:29:21.171605 TX_TRACKING: ON
3747 12:29:21.181465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3748 12:29:21.184741 [FAST_K] Save calibration result to emmc
3749 12:29:21.188118 dramc_set_vcore_voltage set vcore to 650000
3750 12:29:21.191286 Read voltage for 600, 5
3751 12:29:21.191392 Vio18 = 0
3752 12:29:21.191460 Vcore = 650000
3753 12:29:21.194506 Vdram = 0
3754 12:29:21.194583 Vddq = 0
3755 12:29:21.194646 Vmddr = 0
3756 12:29:21.201186 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3757 12:29:21.204408 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3758 12:29:21.207738 MEM_TYPE=3, freq_sel=19
3759 12:29:21.211004 sv_algorithm_assistance_LP4_1600
3760 12:29:21.214819 ============ PULL DRAM RESETB DOWN ============
3761 12:29:21.217903 ========== PULL DRAM RESETB DOWN end =========
3762 12:29:21.224519 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3763 12:29:21.227836 ===================================
3764 12:29:21.231107 LPDDR4 DRAM CONFIGURATION
3765 12:29:21.234346 ===================================
3766 12:29:21.234448 EX_ROW_EN[0] = 0x0
3767 12:29:21.237493 EX_ROW_EN[1] = 0x0
3768 12:29:21.237591 LP4Y_EN = 0x0
3769 12:29:21.241293 WORK_FSP = 0x0
3770 12:29:21.241391 WL = 0x2
3771 12:29:21.244552 RL = 0x2
3772 12:29:21.244650 BL = 0x2
3773 12:29:21.247796 RPST = 0x0
3774 12:29:21.247900 RD_PRE = 0x0
3775 12:29:21.251068 WR_PRE = 0x1
3776 12:29:21.251171 WR_PST = 0x0
3777 12:29:21.254367 DBI_WR = 0x0
3778 12:29:21.254468 DBI_RD = 0x0
3779 12:29:21.257475 OTF = 0x1
3780 12:29:21.260739 ===================================
3781 12:29:21.264033 ===================================
3782 12:29:21.264174 ANA top config
3783 12:29:21.268007 ===================================
3784 12:29:21.270670 DLL_ASYNC_EN = 0
3785 12:29:21.273979 ALL_SLAVE_EN = 1
3786 12:29:21.277825 NEW_RANK_MODE = 1
3787 12:29:21.277944 DLL_IDLE_MODE = 1
3788 12:29:21.281130 LP45_APHY_COMB_EN = 1
3789 12:29:21.284501 TX_ODT_DIS = 1
3790 12:29:21.287851 NEW_8X_MODE = 1
3791 12:29:21.290961 ===================================
3792 12:29:21.294241 ===================================
3793 12:29:21.297361 data_rate = 1200
3794 12:29:21.300497 CKR = 1
3795 12:29:21.300658 DQ_P2S_RATIO = 8
3796 12:29:21.304442 ===================================
3797 12:29:21.308398 CA_P2S_RATIO = 8
3798 12:29:21.311081 DQ_CA_OPEN = 0
3799 12:29:21.314262 DQ_SEMI_OPEN = 0
3800 12:29:21.317372 CA_SEMI_OPEN = 0
3801 12:29:21.317457 CA_FULL_RATE = 0
3802 12:29:21.321174 DQ_CKDIV4_EN = 1
3803 12:29:21.324406 CA_CKDIV4_EN = 1
3804 12:29:21.327741 CA_PREDIV_EN = 0
3805 12:29:21.331026 PH8_DLY = 0
3806 12:29:21.334248 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3807 12:29:21.334359 DQ_AAMCK_DIV = 4
3808 12:29:21.337332 CA_AAMCK_DIV = 4
3809 12:29:21.340435 CA_ADMCK_DIV = 4
3810 12:29:21.343739 DQ_TRACK_CA_EN = 0
3811 12:29:21.347399 CA_PICK = 600
3812 12:29:21.350657 CA_MCKIO = 600
3813 12:29:21.353811 MCKIO_SEMI = 0
3814 12:29:21.353916 PLL_FREQ = 2288
3815 12:29:21.357091 DQ_UI_PI_RATIO = 32
3816 12:29:21.360385 CA_UI_PI_RATIO = 0
3817 12:29:21.364175 ===================================
3818 12:29:21.367520 ===================================
3819 12:29:21.370926 memory_type:LPDDR4
3820 12:29:21.371014 GP_NUM : 10
3821 12:29:21.374236 SRAM_EN : 1
3822 12:29:21.377614 MD32_EN : 0
3823 12:29:21.380873 ===================================
3824 12:29:21.380958 [ANA_INIT] >>>>>>>>>>>>>>
3825 12:29:21.384219 <<<<<< [CONFIGURE PHASE]: ANA_TX
3826 12:29:21.387682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3827 12:29:21.390834 ===================================
3828 12:29:21.394179 data_rate = 1200,PCW = 0X5800
3829 12:29:21.396943 ===================================
3830 12:29:21.400724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3831 12:29:21.407305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 12:29:21.410687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3833 12:29:21.417110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3834 12:29:21.420356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3835 12:29:21.423663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3836 12:29:21.426908 [ANA_INIT] flow start
3837 12:29:21.426993 [ANA_INIT] PLL >>>>>>>>
3838 12:29:21.430139 [ANA_INIT] PLL <<<<<<<<
3839 12:29:21.433540 [ANA_INIT] MIDPI >>>>>>>>
3840 12:29:21.433624 [ANA_INIT] MIDPI <<<<<<<<
3841 12:29:21.436823 [ANA_INIT] DLL >>>>>>>>
3842 12:29:21.440133 [ANA_INIT] flow end
3843 12:29:21.443346 ============ LP4 DIFF to SE enter ============
3844 12:29:21.446644 ============ LP4 DIFF to SE exit ============
3845 12:29:21.450525 [ANA_INIT] <<<<<<<<<<<<<
3846 12:29:21.453689 [Flow] Enable top DCM control >>>>>
3847 12:29:21.456796 [Flow] Enable top DCM control <<<<<
3848 12:29:21.460034 Enable DLL master slave shuffle
3849 12:29:21.463314 ==============================================================
3850 12:29:21.466694 Gating Mode config
3851 12:29:21.473694 ==============================================================
3852 12:29:21.473824 Config description:
3853 12:29:21.483814 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3854 12:29:21.489703 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3855 12:29:21.493670 SELPH_MODE 0: By rank 1: By Phase
3856 12:29:21.500184 ==============================================================
3857 12:29:21.503303 GAT_TRACK_EN = 1
3858 12:29:21.506574 RX_GATING_MODE = 2
3859 12:29:21.509893 RX_GATING_TRACK_MODE = 2
3860 12:29:21.513200 SELPH_MODE = 1
3861 12:29:21.516402 PICG_EARLY_EN = 1
3862 12:29:21.519671 VALID_LAT_VALUE = 1
3863 12:29:21.523151 ==============================================================
3864 12:29:21.526486 Enter into Gating configuration >>>>
3865 12:29:21.529643 Exit from Gating configuration <<<<
3866 12:29:21.532943 Enter into DVFS_PRE_config >>>>>
3867 12:29:21.546823 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3868 12:29:21.546968 Exit from DVFS_PRE_config <<<<<
3869 12:29:21.549924 Enter into PICG configuration >>>>
3870 12:29:21.553314 Exit from PICG configuration <<<<
3871 12:29:21.556530 [RX_INPUT] configuration >>>>>
3872 12:29:21.559754 [RX_INPUT] configuration <<<<<
3873 12:29:21.565927 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3874 12:29:21.569812 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3875 12:29:21.576352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3876 12:29:21.582841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3877 12:29:21.589490 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3878 12:29:21.596083 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3879 12:29:21.599515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3880 12:29:21.602786 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3881 12:29:21.606093 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3882 12:29:21.612533 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3883 12:29:21.615843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3884 12:29:21.619046 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 12:29:21.622361 ===================================
3886 12:29:21.626231 LPDDR4 DRAM CONFIGURATION
3887 12:29:21.628917 ===================================
3888 12:29:21.632242 EX_ROW_EN[0] = 0x0
3889 12:29:21.632320 EX_ROW_EN[1] = 0x0
3890 12:29:21.636030 LP4Y_EN = 0x0
3891 12:29:21.636105 WORK_FSP = 0x0
3892 12:29:21.639180 WL = 0x2
3893 12:29:21.639299 RL = 0x2
3894 12:29:21.642490 BL = 0x2
3895 12:29:21.642565 RPST = 0x0
3896 12:29:21.645896 RD_PRE = 0x0
3897 12:29:21.645987 WR_PRE = 0x1
3898 12:29:21.649219 WR_PST = 0x0
3899 12:29:21.649304 DBI_WR = 0x0
3900 12:29:21.652369 DBI_RD = 0x0
3901 12:29:21.652456 OTF = 0x1
3902 12:29:21.655553 ===================================
3903 12:29:21.658747 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3904 12:29:21.665681 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3905 12:29:21.668885 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 12:29:21.672092 ===================================
3907 12:29:21.675277 LPDDR4 DRAM CONFIGURATION
3908 12:29:21.678605 ===================================
3909 12:29:21.678692 EX_ROW_EN[0] = 0x10
3910 12:29:21.682464 EX_ROW_EN[1] = 0x0
3911 12:29:21.685826 LP4Y_EN = 0x0
3912 12:29:21.685902 WORK_FSP = 0x0
3913 12:29:21.689129 WL = 0x2
3914 12:29:21.689212 RL = 0x2
3915 12:29:21.691974 BL = 0x2
3916 12:29:21.692054 RPST = 0x0
3917 12:29:21.695761 RD_PRE = 0x0
3918 12:29:21.695834 WR_PRE = 0x1
3919 12:29:21.699040 WR_PST = 0x0
3920 12:29:21.699141 DBI_WR = 0x0
3921 12:29:21.701823 DBI_RD = 0x0
3922 12:29:21.701896 OTF = 0x1
3923 12:29:21.705655 ===================================
3924 12:29:21.712355 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3925 12:29:21.716205 nWR fixed to 30
3926 12:29:21.720102 [ModeRegInit_LP4] CH0 RK0
3927 12:29:21.720191 [ModeRegInit_LP4] CH0 RK1
3928 12:29:21.723338 [ModeRegInit_LP4] CH1 RK0
3929 12:29:21.726676 [ModeRegInit_LP4] CH1 RK1
3930 12:29:21.726759 match AC timing 17
3931 12:29:21.733175 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3932 12:29:21.736502 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3933 12:29:21.739714 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3934 12:29:21.746112 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3935 12:29:21.749412 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3936 12:29:21.749504 ==
3937 12:29:21.752865 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 12:29:21.756144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 12:29:21.756218 ==
3940 12:29:21.763227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 12:29:21.769428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3942 12:29:21.773196 [CA 0] Center 36 (6~67) winsize 62
3943 12:29:21.776373 [CA 1] Center 36 (6~66) winsize 61
3944 12:29:21.779790 [CA 2] Center 34 (4~65) winsize 62
3945 12:29:21.783029 [CA 3] Center 34 (4~64) winsize 61
3946 12:29:21.786410 [CA 4] Center 33 (3~64) winsize 62
3947 12:29:21.789681 [CA 5] Center 33 (3~64) winsize 62
3948 12:29:21.789754
3949 12:29:21.792948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3950 12:29:21.793020
3951 12:29:21.796251 [CATrainingPosCal] consider 1 rank data
3952 12:29:21.799462 u2DelayCellTimex100 = 270/100 ps
3953 12:29:21.802879 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 12:29:21.806190 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3955 12:29:21.809400 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 12:29:21.812635 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3957 12:29:21.815831 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 12:29:21.819116 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 12:29:21.822945
3960 12:29:21.826203 CA PerBit enable=1, Macro0, CA PI delay=33
3961 12:29:21.826298
3962 12:29:21.829524 [CBTSetCACLKResult] CA Dly = 33
3963 12:29:21.829599 CS Dly: 5 (0~36)
3964 12:29:21.829667 ==
3965 12:29:21.833108 Dram Type= 6, Freq= 0, CH_0, rank 1
3966 12:29:21.835696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 12:29:21.835770 ==
3968 12:29:21.842702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 12:29:21.849183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3970 12:29:21.852358 [CA 0] Center 36 (6~66) winsize 61
3971 12:29:21.855696 [CA 1] Center 36 (6~66) winsize 61
3972 12:29:21.858922 [CA 2] Center 35 (5~65) winsize 61
3973 12:29:21.862092 [CA 3] Center 34 (4~65) winsize 62
3974 12:29:21.865482 [CA 4] Center 33 (3~64) winsize 62
3975 12:29:21.869361 [CA 5] Center 33 (3~64) winsize 62
3976 12:29:21.869437
3977 12:29:21.872463 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3978 12:29:21.872547
3979 12:29:21.875544 [CATrainingPosCal] consider 2 rank data
3980 12:29:21.878759 u2DelayCellTimex100 = 270/100 ps
3981 12:29:21.882056 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3982 12:29:21.885389 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3983 12:29:21.888595 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3984 12:29:21.895153 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3985 12:29:21.898520 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 12:29:21.901967 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3987 12:29:21.902068
3988 12:29:21.905152 CA PerBit enable=1, Macro0, CA PI delay=33
3989 12:29:21.905240
3990 12:29:21.908481 [CBTSetCACLKResult] CA Dly = 33
3991 12:29:21.908554 CS Dly: 5 (0~36)
3992 12:29:21.908617
3993 12:29:21.911881 ----->DramcWriteLeveling(PI) begin...
3994 12:29:21.911954 ==
3995 12:29:21.915212 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 12:29:21.921865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 12:29:21.921945 ==
3998 12:29:21.925014 Write leveling (Byte 0): 32 => 32
3999 12:29:21.928310 Write leveling (Byte 1): 28 => 28
4000 12:29:21.932216 DramcWriteLeveling(PI) end<-----
4001 12:29:21.932322
4002 12:29:21.932415 ==
4003 12:29:21.934855 Dram Type= 6, Freq= 0, CH_0, rank 0
4004 12:29:21.938819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4005 12:29:21.938897 ==
4006 12:29:21.942146 [Gating] SW mode calibration
4007 12:29:21.948164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4008 12:29:21.951418 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4009 12:29:21.958085 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 12:29:21.961382 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 12:29:21.964781 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 12:29:21.971277 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4013 12:29:21.974423 0 9 16 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4014 12:29:21.977833 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 12:29:21.984864 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 12:29:21.988067 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 12:29:21.991310 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 12:29:21.997786 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 12:29:22.001195 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 12:29:22.004611 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 12:29:22.011229 0 10 16 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
4022 12:29:22.014606 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4023 12:29:22.017883 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 12:29:22.024488 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:29:22.027837 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 12:29:22.030967 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 12:29:22.037420 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 12:29:22.040892 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4029 12:29:22.044189 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4030 12:29:22.050858 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:29:22.053985 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:29:22.057061 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:29:22.063834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:29:22.067178 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:29:22.070432 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:29:22.077018 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:29:22.080229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:29:22.083635 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:29:22.090549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:29:22.093926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:29:22.097158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 12:29:22.103968 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 12:29:22.107078 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 12:29:22.110518 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:29:22.117207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4046 12:29:22.117386 Total UI for P1: 0, mck2ui 16
4047 12:29:22.123157 best dqsien dly found for B0: ( 0, 13, 14)
4048 12:29:22.126488 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 12:29:22.129962 Total UI for P1: 0, mck2ui 16
4050 12:29:22.133717 best dqsien dly found for B1: ( 0, 13, 16)
4051 12:29:22.136934 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4052 12:29:22.140156 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4053 12:29:22.140312
4054 12:29:22.143173 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4055 12:29:22.147178 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4056 12:29:22.149862 [Gating] SW calibration Done
4057 12:29:22.149988 ==
4058 12:29:22.153160 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 12:29:22.160119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 12:29:22.160281 ==
4061 12:29:22.160370 RX Vref Scan: 0
4062 12:29:22.160473
4063 12:29:22.163386 RX Vref 0 -> 0, step: 1
4064 12:29:22.163531
4065 12:29:22.166673 RX Delay -230 -> 252, step: 16
4066 12:29:22.169970 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4067 12:29:22.173400 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4068 12:29:22.176540 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4069 12:29:22.183579 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4070 12:29:22.186667 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4071 12:29:22.189793 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4072 12:29:22.192848 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4073 12:29:22.196753 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4074 12:29:22.203127 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4075 12:29:22.206483 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4076 12:29:22.209788 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4077 12:29:22.213196 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4078 12:29:22.219784 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4079 12:29:22.223114 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4080 12:29:22.226494 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4081 12:29:22.229234 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4082 12:29:22.233097 ==
4083 12:29:22.233199 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 12:29:22.239738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 12:29:22.239823 ==
4086 12:29:22.239892 DQS Delay:
4087 12:29:22.242923 DQS0 = 0, DQS1 = 0
4088 12:29:22.243036 DQM Delay:
4089 12:29:22.246252 DQM0 = 41, DQM1 = 32
4090 12:29:22.246351 DQ Delay:
4091 12:29:22.249502 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4092 12:29:22.252795 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4093 12:29:22.256048 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4094 12:29:22.259187 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4095 12:29:22.259296
4096 12:29:22.259391
4097 12:29:22.259456 ==
4098 12:29:22.262458 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 12:29:22.265661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 12:29:22.265746 ==
4101 12:29:22.265813
4102 12:29:22.265875
4103 12:29:22.269451 TX Vref Scan disable
4104 12:29:22.272767 == TX Byte 0 ==
4105 12:29:22.276117 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4106 12:29:22.279253 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4107 12:29:22.282354 == TX Byte 1 ==
4108 12:29:22.285534 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4109 12:29:22.289375 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4110 12:29:22.289479 ==
4111 12:29:22.292597 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 12:29:22.298996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 12:29:22.299082 ==
4114 12:29:22.299150
4115 12:29:22.299251
4116 12:29:22.299341 TX Vref Scan disable
4117 12:29:22.303616 == TX Byte 0 ==
4118 12:29:22.306829 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4119 12:29:22.313463 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4120 12:29:22.313567 == TX Byte 1 ==
4121 12:29:22.316293 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4122 12:29:22.322913 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4123 12:29:22.323015
4124 12:29:22.323117 [DATLAT]
4125 12:29:22.323207 Freq=600, CH0 RK0
4126 12:29:22.323296
4127 12:29:22.326317 DATLAT Default: 0x9
4128 12:29:22.326419 0, 0xFFFF, sum = 0
4129 12:29:22.329519 1, 0xFFFF, sum = 0
4130 12:29:22.332793 2, 0xFFFF, sum = 0
4131 12:29:22.332913 3, 0xFFFF, sum = 0
4132 12:29:22.336028 4, 0xFFFF, sum = 0
4133 12:29:22.336141 5, 0xFFFF, sum = 0
4134 12:29:22.339318 6, 0xFFFF, sum = 0
4135 12:29:22.339425 7, 0xFFFF, sum = 0
4136 12:29:22.342792 8, 0x0, sum = 1
4137 12:29:22.342904 9, 0x0, sum = 2
4138 12:29:22.343002 10, 0x0, sum = 3
4139 12:29:22.345981 11, 0x0, sum = 4
4140 12:29:22.346093 best_step = 9
4141 12:29:22.346189
4142 12:29:22.346282 ==
4143 12:29:22.349839 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 12:29:22.356313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 12:29:22.356423 ==
4146 12:29:22.356525 RX Vref Scan: 1
4147 12:29:22.356619
4148 12:29:22.359549 RX Vref 0 -> 0, step: 1
4149 12:29:22.359659
4150 12:29:22.362928 RX Delay -195 -> 252, step: 8
4151 12:29:22.363012
4152 12:29:22.366121 Set Vref, RX VrefLevel [Byte0]: 53
4153 12:29:22.369339 [Byte1]: 51
4154 12:29:22.369449
4155 12:29:22.372499 Final RX Vref Byte 0 = 53 to rank0
4156 12:29:22.375842 Final RX Vref Byte 1 = 51 to rank0
4157 12:29:22.379107 Final RX Vref Byte 0 = 53 to rank1
4158 12:29:22.382381 Final RX Vref Byte 1 = 51 to rank1==
4159 12:29:22.385638 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 12:29:22.389513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 12:29:22.389616 ==
4162 12:29:22.392694 DQS Delay:
4163 12:29:22.392800 DQS0 = 0, DQS1 = 0
4164 12:29:22.395915 DQM Delay:
4165 12:29:22.396015 DQM0 = 42, DQM1 = 33
4166 12:29:22.396111 DQ Delay:
4167 12:29:22.399064 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4168 12:29:22.402787 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4169 12:29:22.405928 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4170 12:29:22.409164 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4171 12:29:22.409266
4172 12:29:22.409360
4173 12:29:22.419179 [DQSOSCAuto] RK0, (LSB)MR18= 0x4220, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4174 12:29:22.422497 CH0 RK0: MR19=808, MR18=4220
4175 12:29:22.429277 CH0_RK0: MR19=0x808, MR18=0x4220, DQSOSC=397, MR23=63, INC=166, DEC=110
4176 12:29:22.429379
4177 12:29:22.432486 ----->DramcWriteLeveling(PI) begin...
4178 12:29:22.432572 ==
4179 12:29:22.435756 Dram Type= 6, Freq= 0, CH_0, rank 1
4180 12:29:22.438948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 12:29:22.439055 ==
4182 12:29:22.442153 Write leveling (Byte 0): 32 => 32
4183 12:29:22.445435 Write leveling (Byte 1): 29 => 29
4184 12:29:22.448740 DramcWriteLeveling(PI) end<-----
4185 12:29:22.448851
4186 12:29:22.448949 ==
4187 12:29:22.451875 Dram Type= 6, Freq= 0, CH_0, rank 1
4188 12:29:22.455113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 12:29:22.455223 ==
4190 12:29:22.458450 [Gating] SW mode calibration
4191 12:29:22.465696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4192 12:29:22.471672 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4193 12:29:22.474926 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 12:29:22.478799 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4195 12:29:22.484792 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 12:29:22.488687 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4197 12:29:22.491879 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
4198 12:29:22.498515 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 12:29:22.501627 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 12:29:22.504718 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 12:29:22.511879 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 12:29:22.515097 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 12:29:22.517814 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 12:29:22.524454 0 10 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
4205 12:29:22.527707 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4206 12:29:22.531137 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 12:29:22.538145 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 12:29:22.541448 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 12:29:22.544804 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 12:29:22.551433 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 12:29:22.554515 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 12:29:22.557862 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4213 12:29:22.564202 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4214 12:29:22.567511 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4215 12:29:22.570846 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:29:22.577429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:29:22.580745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:29:22.584000 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:29:22.591073 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:29:22.594199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:29:22.597450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 12:29:22.603774 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:29:22.607008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 12:29:22.610734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:29:22.617404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 12:29:22.620360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 12:29:22.623710 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:29:22.630158 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4229 12:29:22.634135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 12:29:22.637387 Total UI for P1: 0, mck2ui 16
4231 12:29:22.640211 best dqsien dly found for B0: ( 0, 13, 12)
4232 12:29:22.644135 Total UI for P1: 0, mck2ui 16
4233 12:29:22.647286 best dqsien dly found for B1: ( 0, 13, 14)
4234 12:29:22.650484 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4235 12:29:22.653826 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4236 12:29:22.653937
4237 12:29:22.657108 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4238 12:29:22.660450 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4239 12:29:22.663672 [Gating] SW calibration Done
4240 12:29:22.663783 ==
4241 12:29:22.666876 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 12:29:22.670221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 12:29:22.674004 ==
4244 12:29:22.674113 RX Vref Scan: 0
4245 12:29:22.674210
4246 12:29:22.677341 RX Vref 0 -> 0, step: 1
4247 12:29:22.677450
4248 12:29:22.680508 RX Delay -230 -> 252, step: 16
4249 12:29:22.683891 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4250 12:29:22.687130 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4251 12:29:22.690340 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4252 12:29:22.697067 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4253 12:29:22.700293 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4254 12:29:22.703510 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4255 12:29:22.706750 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4256 12:29:22.709854 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4257 12:29:22.716922 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4258 12:29:22.720126 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4259 12:29:22.723261 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4260 12:29:22.727031 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4261 12:29:22.733701 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4262 12:29:22.736914 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4263 12:29:22.740306 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4264 12:29:22.743554 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4265 12:29:22.743638 ==
4266 12:29:22.746938 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 12:29:22.753572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 12:29:22.753656 ==
4269 12:29:22.753723 DQS Delay:
4270 12:29:22.756867 DQS0 = 0, DQS1 = 0
4271 12:29:22.756950 DQM Delay:
4272 12:29:22.757016 DQM0 = 41, DQM1 = 33
4273 12:29:22.760231 DQ Delay:
4274 12:29:22.763476 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4275 12:29:22.766776 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4276 12:29:22.769835 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4277 12:29:22.773146 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4278 12:29:22.773234
4279 12:29:22.773305
4280 12:29:22.773411 ==
4281 12:29:22.776314 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 12:29:22.779676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 12:29:22.779752 ==
4284 12:29:22.779820
4285 12:29:22.779902
4286 12:29:22.783520 TX Vref Scan disable
4287 12:29:22.786896 == TX Byte 0 ==
4288 12:29:22.790143 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4289 12:29:22.793370 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4290 12:29:22.796635 == TX Byte 1 ==
4291 12:29:22.799962 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4292 12:29:22.803186 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4293 12:29:22.803289 ==
4294 12:29:22.806527 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 12:29:22.809758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 12:29:22.812995 ==
4297 12:29:22.813071
4298 12:29:22.813135
4299 12:29:22.813196 TX Vref Scan disable
4300 12:29:22.816653 == TX Byte 0 ==
4301 12:29:22.819815 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4302 12:29:22.827001 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4303 12:29:22.827109 == TX Byte 1 ==
4304 12:29:22.830267 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4305 12:29:22.836854 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4306 12:29:22.836959
4307 12:29:22.837052 [DATLAT]
4308 12:29:22.837141 Freq=600, CH0 RK1
4309 12:29:22.837232
4310 12:29:22.839991 DATLAT Default: 0x9
4311 12:29:22.840068 0, 0xFFFF, sum = 0
4312 12:29:22.843201 1, 0xFFFF, sum = 0
4313 12:29:22.843311 2, 0xFFFF, sum = 0
4314 12:29:22.846459 3, 0xFFFF, sum = 0
4315 12:29:22.849804 4, 0xFFFF, sum = 0
4316 12:29:22.849916 5, 0xFFFF, sum = 0
4317 12:29:22.853172 6, 0xFFFF, sum = 0
4318 12:29:22.853283 7, 0xFFFF, sum = 0
4319 12:29:22.856536 8, 0x0, sum = 1
4320 12:29:22.856639 9, 0x0, sum = 2
4321 12:29:22.856732 10, 0x0, sum = 3
4322 12:29:22.859833 11, 0x0, sum = 4
4323 12:29:22.859910 best_step = 9
4324 12:29:22.859973
4325 12:29:22.860035 ==
4326 12:29:22.863171 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 12:29:22.869771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 12:29:22.869885 ==
4329 12:29:22.869983 RX Vref Scan: 0
4330 12:29:22.870079
4331 12:29:22.873002 RX Vref 0 -> 0, step: 1
4332 12:29:22.873098
4333 12:29:22.876213 RX Delay -195 -> 252, step: 8
4334 12:29:22.879491 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4335 12:29:22.886274 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4336 12:29:22.889570 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4337 12:29:22.892943 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4338 12:29:22.896121 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4339 12:29:22.902835 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4340 12:29:22.906129 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4341 12:29:22.910027 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4342 12:29:22.913326 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4343 12:29:22.915918 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4344 12:29:22.922982 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4345 12:29:22.926126 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4346 12:29:22.929421 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4347 12:29:22.932866 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4348 12:29:22.939374 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4349 12:29:22.942849 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4350 12:29:22.942923 ==
4351 12:29:22.946171 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 12:29:22.949439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 12:29:22.949517 ==
4354 12:29:22.952742 DQS Delay:
4355 12:29:22.952817 DQS0 = 0, DQS1 = 0
4356 12:29:22.956062 DQM Delay:
4357 12:29:22.956139 DQM0 = 39, DQM1 = 33
4358 12:29:22.956203 DQ Delay:
4359 12:29:22.959380 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4360 12:29:22.962670 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4361 12:29:22.965903 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4362 12:29:22.969177 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4363 12:29:22.969277
4364 12:29:22.969373
4365 12:29:22.979137 [DQSOSCAuto] RK1, (LSB)MR18= 0x4528, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4366 12:29:22.982396 CH0 RK1: MR19=808, MR18=4528
4367 12:29:22.989026 CH0_RK1: MR19=0x808, MR18=0x4528, DQSOSC=396, MR23=63, INC=167, DEC=111
4368 12:29:22.989147 [RxdqsGatingPostProcess] freq 600
4369 12:29:22.995787 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4370 12:29:22.998968 Pre-setting of DQS Precalculation
4371 12:29:23.002074 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4372 12:29:23.005405 ==
4373 12:29:23.008761 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 12:29:23.012148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 12:29:23.012256 ==
4376 12:29:23.015286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 12:29:23.021813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4378 12:29:23.026106 [CA 0] Center 35 (5~65) winsize 61
4379 12:29:23.029223 [CA 1] Center 35 (5~65) winsize 61
4380 12:29:23.032349 [CA 2] Center 34 (4~65) winsize 62
4381 12:29:23.035741 [CA 3] Center 33 (3~64) winsize 62
4382 12:29:23.039524 [CA 4] Center 34 (3~65) winsize 63
4383 12:29:23.042918 [CA 5] Center 33 (3~64) winsize 62
4384 12:29:23.042998
4385 12:29:23.046246 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4386 12:29:23.046353
4387 12:29:23.048870 [CATrainingPosCal] consider 1 rank data
4388 12:29:23.052838 u2DelayCellTimex100 = 270/100 ps
4389 12:29:23.056155 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4390 12:29:23.058891 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4391 12:29:23.065686 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 12:29:23.068951 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4393 12:29:23.072230 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4394 12:29:23.075462 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 12:29:23.075576
4396 12:29:23.078858 CA PerBit enable=1, Macro0, CA PI delay=33
4397 12:29:23.078964
4398 12:29:23.082163 [CBTSetCACLKResult] CA Dly = 33
4399 12:29:23.082269 CS Dly: 4 (0~35)
4400 12:29:23.085976 ==
4401 12:29:23.086085 Dram Type= 6, Freq= 0, CH_1, rank 1
4402 12:29:23.092637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 12:29:23.092745 ==
4404 12:29:23.095925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4405 12:29:23.102465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4406 12:29:23.105658 [CA 0] Center 35 (5~66) winsize 62
4407 12:29:23.109542 [CA 1] Center 35 (5~66) winsize 62
4408 12:29:23.112818 [CA 2] Center 34 (4~65) winsize 62
4409 12:29:23.116151 [CA 3] Center 34 (3~65) winsize 63
4410 12:29:23.119209 [CA 4] Center 34 (3~65) winsize 63
4411 12:29:23.122472 [CA 5] Center 33 (3~64) winsize 62
4412 12:29:23.122578
4413 12:29:23.125707 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4414 12:29:23.125807
4415 12:29:23.128845 [CATrainingPosCal] consider 2 rank data
4416 12:29:23.132198 u2DelayCellTimex100 = 270/100 ps
4417 12:29:23.135850 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4418 12:29:23.142592 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4419 12:29:23.145829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 12:29:23.149160 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 12:29:23.152547 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4422 12:29:23.155854 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 12:29:23.155939
4424 12:29:23.159268 CA PerBit enable=1, Macro0, CA PI delay=33
4425 12:29:23.159381
4426 12:29:23.162541 [CBTSetCACLKResult] CA Dly = 33
4427 12:29:23.162632 CS Dly: 4 (0~35)
4428 12:29:23.165910
4429 12:29:23.169106 ----->DramcWriteLeveling(PI) begin...
4430 12:29:23.169192 ==
4431 12:29:23.171936 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 12:29:23.175270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 12:29:23.175388 ==
4434 12:29:23.178707 Write leveling (Byte 0): 29 => 29
4435 12:29:23.181962 Write leveling (Byte 1): 30 => 30
4436 12:29:23.185255 DramcWriteLeveling(PI) end<-----
4437 12:29:23.185333
4438 12:29:23.185412 ==
4439 12:29:23.189099 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 12:29:23.192208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 12:29:23.192313 ==
4442 12:29:23.195734 [Gating] SW mode calibration
4443 12:29:23.202255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4444 12:29:23.208778 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4445 12:29:23.212059 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4446 12:29:23.215266 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4447 12:29:23.221917 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4448 12:29:23.225138 0 9 12 | B1->B0 | 3535 3232 | 1 1 | (1 1) (1 1)
4449 12:29:23.228384 0 9 16 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
4450 12:29:23.234651 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 12:29:23.237874 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 12:29:23.241156 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 12:29:23.248489 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4454 12:29:23.251689 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 12:29:23.254902 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 12:29:23.261544 0 10 12 | B1->B0 | 2626 2828 | 0 1 | (0 0) (0 0)
4457 12:29:23.264963 0 10 16 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
4458 12:29:23.268137 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 12:29:23.274791 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 12:29:23.277953 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 12:29:23.281336 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 12:29:23.287991 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 12:29:23.291219 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 12:29:23.294465 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 12:29:23.301222 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4466 12:29:23.304540 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:29:23.307877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:29:23.311154 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:29:23.317693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:29:23.320939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:29:23.324192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:29:23.331219 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:29:23.334502 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:29:23.337595 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:29:23.344673 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:29:23.347221 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:29:23.350599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:29:23.357082 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:29:23.360459 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:29:23.363905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4481 12:29:23.367154 Total UI for P1: 0, mck2ui 16
4482 12:29:23.370427 best dqsien dly found for B0: ( 0, 13, 10)
4483 12:29:23.377075 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 12:29:23.380423 Total UI for P1: 0, mck2ui 16
4485 12:29:23.383711 best dqsien dly found for B1: ( 0, 13, 12)
4486 12:29:23.387036 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4487 12:29:23.390366 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4488 12:29:23.390449
4489 12:29:23.393700 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4490 12:29:23.396856 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4491 12:29:23.400190 [Gating] SW calibration Done
4492 12:29:23.400274 ==
4493 12:29:23.403385 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 12:29:23.406751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 12:29:23.406828 ==
4496 12:29:23.410050 RX Vref Scan: 0
4497 12:29:23.410124
4498 12:29:23.413393 RX Vref 0 -> 0, step: 1
4499 12:29:23.413488
4500 12:29:23.416818 RX Delay -230 -> 252, step: 16
4501 12:29:23.419981 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4502 12:29:23.423763 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4503 12:29:23.426964 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4504 12:29:23.430241 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4505 12:29:23.436715 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4506 12:29:23.439939 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4507 12:29:23.443222 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4508 12:29:23.446916 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4509 12:29:23.453362 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4510 12:29:23.456669 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4511 12:29:23.459851 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4512 12:29:23.463078 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4513 12:29:23.469615 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4514 12:29:23.472951 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4515 12:29:23.476275 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4516 12:29:23.479613 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4517 12:29:23.479692 ==
4518 12:29:23.482898 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 12:29:23.489440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 12:29:23.489528 ==
4521 12:29:23.489593 DQS Delay:
4522 12:29:23.492711 DQS0 = 0, DQS1 = 0
4523 12:29:23.492800 DQM Delay:
4524 12:29:23.492865 DQM0 = 45, DQM1 = 36
4525 12:29:23.496015 DQ Delay:
4526 12:29:23.499868 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4527 12:29:23.503190 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4528 12:29:23.506398 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4529 12:29:23.509791 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4530 12:29:23.509899
4531 12:29:23.510002
4532 12:29:23.510092 ==
4533 12:29:23.513107 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 12:29:23.516513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 12:29:23.516629 ==
4536 12:29:23.516736
4537 12:29:23.516833
4538 12:29:23.519840 TX Vref Scan disable
4539 12:29:23.519912 == TX Byte 0 ==
4540 12:29:23.526333 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4541 12:29:23.529519 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4542 12:29:23.529606 == TX Byte 1 ==
4543 12:29:23.536081 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 12:29:23.539287 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 12:29:23.539392 ==
4546 12:29:23.542605 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 12:29:23.545912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 12:29:23.545987 ==
4549 12:29:23.546056
4550 12:29:23.549663
4551 12:29:23.549773 TX Vref Scan disable
4552 12:29:23.552827 == TX Byte 0 ==
4553 12:29:23.556002 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4554 12:29:23.562435 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4555 12:29:23.562528 == TX Byte 1 ==
4556 12:29:23.565777 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4557 12:29:23.572407 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4558 12:29:23.572487
4559 12:29:23.572562 [DATLAT]
4560 12:29:23.572640 Freq=600, CH1 RK0
4561 12:29:23.572708
4562 12:29:23.575669 DATLAT Default: 0x9
4563 12:29:23.575761 0, 0xFFFF, sum = 0
4564 12:29:23.579027 1, 0xFFFF, sum = 0
4565 12:29:23.582517 2, 0xFFFF, sum = 0
4566 12:29:23.582634 3, 0xFFFF, sum = 0
4567 12:29:23.585743 4, 0xFFFF, sum = 0
4568 12:29:23.585854 5, 0xFFFF, sum = 0
4569 12:29:23.588982 6, 0xFFFF, sum = 0
4570 12:29:23.589057 7, 0xFFFF, sum = 0
4571 12:29:23.592999 8, 0x0, sum = 1
4572 12:29:23.593101 9, 0x0, sum = 2
4573 12:29:23.593194 10, 0x0, sum = 3
4574 12:29:23.595598 11, 0x0, sum = 4
4575 12:29:23.595668 best_step = 9
4576 12:29:23.595729
4577 12:29:23.595796 ==
4578 12:29:23.599510 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 12:29:23.606156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 12:29:23.606246 ==
4581 12:29:23.606312 RX Vref Scan: 1
4582 12:29:23.606385
4583 12:29:23.609366 RX Vref 0 -> 0, step: 1
4584 12:29:23.609466
4585 12:29:23.612721 RX Delay -195 -> 252, step: 8
4586 12:29:23.612801
4587 12:29:23.615941 Set Vref, RX VrefLevel [Byte0]: 58
4588 12:29:23.619255 [Byte1]: 49
4589 12:29:23.619365
4590 12:29:23.622652 Final RX Vref Byte 0 = 58 to rank0
4591 12:29:23.625945 Final RX Vref Byte 1 = 49 to rank0
4592 12:29:23.629144 Final RX Vref Byte 0 = 58 to rank1
4593 12:29:23.632321 Final RX Vref Byte 1 = 49 to rank1==
4594 12:29:23.635522 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 12:29:23.638815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 12:29:23.638891 ==
4597 12:29:23.642064 DQS Delay:
4598 12:29:23.642144 DQS0 = 0, DQS1 = 0
4599 12:29:23.645863 DQM Delay:
4600 12:29:23.645938 DQM0 = 41, DQM1 = 32
4601 12:29:23.646001 DQ Delay:
4602 12:29:23.649187 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4603 12:29:23.652446 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =36
4604 12:29:23.655576 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4605 12:29:23.658697 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4606 12:29:23.658800
4607 12:29:23.658879
4608 12:29:23.669035 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4609 12:29:23.672299 CH1 RK0: MR19=808, MR18=3E04
4610 12:29:23.678791 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4611 12:29:23.678886
4612 12:29:23.682072 ----->DramcWriteLeveling(PI) begin...
4613 12:29:23.682156 ==
4614 12:29:23.685471 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 12:29:23.688789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 12:29:23.688909 ==
4617 12:29:23.692110 Write leveling (Byte 0): 31 => 31
4618 12:29:23.695367 Write leveling (Byte 1): 31 => 31
4619 12:29:23.698766 DramcWriteLeveling(PI) end<-----
4620 12:29:23.698875
4621 12:29:23.698968 ==
4622 12:29:23.702017 Dram Type= 6, Freq= 0, CH_1, rank 1
4623 12:29:23.705320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 12:29:23.705420 ==
4625 12:29:23.708592 [Gating] SW mode calibration
4626 12:29:23.715145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4627 12:29:23.721715 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4628 12:29:23.724969 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 12:29:23.728372 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4630 12:29:23.735390 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (0 1)
4631 12:29:23.738649 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (1 1)
4632 12:29:23.741774 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4633 12:29:23.748817 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 12:29:23.751952 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4635 12:29:23.755244 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4636 12:29:23.761569 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 12:29:23.764727 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4638 12:29:23.768583 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4639 12:29:23.775200 0 10 12 | B1->B0 | 2e2e 3b3b | 0 0 | (1 1) (0 0)
4640 12:29:23.778354 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4641 12:29:23.781645 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 12:29:23.788238 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 12:29:23.791433 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 12:29:23.794867 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 12:29:23.798023 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 12:29:23.805344 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 12:29:23.808640 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4648 12:29:23.811917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4649 12:29:23.818377 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:29:23.821596 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:29:23.824864 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:29:23.831475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:29:23.834812 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:29:23.838242 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:29:23.845029 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:29:23.848185 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:29:23.851298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:29:23.857852 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:29:23.861892 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:29:23.864937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:29:23.871326 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 12:29:23.874722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4663 12:29:23.877940 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4664 12:29:23.884933 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 12:29:23.885039 Total UI for P1: 0, mck2ui 16
4666 12:29:23.891442 best dqsien dly found for B0: ( 0, 13, 10)
4667 12:29:23.891531 Total UI for P1: 0, mck2ui 16
4668 12:29:23.898130 best dqsien dly found for B1: ( 0, 13, 12)
4669 12:29:23.901386 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4670 12:29:23.904741 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4671 12:29:23.904853
4672 12:29:23.908093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4673 12:29:23.911491 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4674 12:29:23.914817 [Gating] SW calibration Done
4675 12:29:23.914923 ==
4676 12:29:23.918195 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 12:29:23.921423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 12:29:23.921530 ==
4679 12:29:23.924713 RX Vref Scan: 0
4680 12:29:23.924819
4681 12:29:23.924910 RX Vref 0 -> 0, step: 1
4682 12:29:23.924973
4683 12:29:23.927923 RX Delay -230 -> 252, step: 16
4684 12:29:23.934577 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4685 12:29:23.937873 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4686 12:29:23.941258 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4687 12:29:23.944537 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4688 12:29:23.947752 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4689 12:29:23.954321 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4690 12:29:23.957508 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4691 12:29:23.960835 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4692 12:29:23.964139 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4693 12:29:23.967320 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4694 12:29:23.974292 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4695 12:29:23.977334 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4696 12:29:23.980711 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4697 12:29:23.984604 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4698 12:29:23.991001 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4699 12:29:23.994402 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4700 12:29:23.994503 ==
4701 12:29:23.997680 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 12:29:24.000928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 12:29:24.001032 ==
4704 12:29:24.004136 DQS Delay:
4705 12:29:24.004223 DQS0 = 0, DQS1 = 0
4706 12:29:24.007378 DQM Delay:
4707 12:29:24.007460 DQM0 = 40, DQM1 = 35
4708 12:29:24.007534 DQ Delay:
4709 12:29:24.010773 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4710 12:29:24.014019 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4711 12:29:24.017401 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4712 12:29:24.020719 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4713 12:29:24.020822
4714 12:29:24.020921
4715 12:29:24.021010 ==
4716 12:29:24.024198 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 12:29:24.030614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 12:29:24.030708 ==
4719 12:29:24.030782
4720 12:29:24.030851
4721 12:29:24.030917 TX Vref Scan disable
4722 12:29:24.034624 == TX Byte 0 ==
4723 12:29:24.037826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 12:29:24.044497 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 12:29:24.044581 == TX Byte 1 ==
4726 12:29:24.047770 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4727 12:29:24.054625 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4728 12:29:24.054710 ==
4729 12:29:24.057953 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 12:29:24.061173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 12:29:24.061257 ==
4732 12:29:24.061324
4733 12:29:24.061385
4734 12:29:24.064298 TX Vref Scan disable
4735 12:29:24.067649 == TX Byte 0 ==
4736 12:29:24.070809 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4737 12:29:24.074598 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4738 12:29:24.077801 == TX Byte 1 ==
4739 12:29:24.081020 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 12:29:24.084242 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 12:29:24.084345
4742 12:29:24.084439 [DATLAT]
4743 12:29:24.087681 Freq=600, CH1 RK1
4744 12:29:24.087764
4745 12:29:24.090807 DATLAT Default: 0x9
4746 12:29:24.090904 0, 0xFFFF, sum = 0
4747 12:29:24.094118 1, 0xFFFF, sum = 0
4748 12:29:24.094204 2, 0xFFFF, sum = 0
4749 12:29:24.097385 3, 0xFFFF, sum = 0
4750 12:29:24.097470 4, 0xFFFF, sum = 0
4751 12:29:24.100608 5, 0xFFFF, sum = 0
4752 12:29:24.100691 6, 0xFFFF, sum = 0
4753 12:29:24.103842 7, 0xFFFF, sum = 0
4754 12:29:24.103925 8, 0x0, sum = 1
4755 12:29:24.107074 9, 0x0, sum = 2
4756 12:29:24.107180 10, 0x0, sum = 3
4757 12:29:24.110410 11, 0x0, sum = 4
4758 12:29:24.110528 best_step = 9
4759 12:29:24.110621
4760 12:29:24.110725 ==
4761 12:29:24.113729 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 12:29:24.116880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 12:29:24.116959 ==
4764 12:29:24.120230 RX Vref Scan: 0
4765 12:29:24.120304
4766 12:29:24.123509 RX Vref 0 -> 0, step: 1
4767 12:29:24.123589
4768 12:29:24.123659 RX Delay -179 -> 252, step: 8
4769 12:29:24.131361 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4770 12:29:24.135220 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4771 12:29:24.138565 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4772 12:29:24.141895 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4773 12:29:24.148467 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4774 12:29:24.151810 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4775 12:29:24.155003 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4776 12:29:24.158184 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4777 12:29:24.161513 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4778 12:29:24.167975 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4779 12:29:24.172396 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4780 12:29:24.174614 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4781 12:29:24.177736 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4782 12:29:24.184516 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4783 12:29:24.187748 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4784 12:29:24.191644 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4785 12:29:24.191748 ==
4786 12:29:24.194872 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 12:29:24.201483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 12:29:24.201569 ==
4789 12:29:24.201637 DQS Delay:
4790 12:29:24.201699 DQS0 = 0, DQS1 = 0
4791 12:29:24.204705 DQM Delay:
4792 12:29:24.204779 DQM0 = 38, DQM1 = 33
4793 12:29:24.207966 DQ Delay:
4794 12:29:24.211385 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4795 12:29:24.211460 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4796 12:29:24.214739 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4797 12:29:24.221331 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4798 12:29:24.221411
4799 12:29:24.221477
4800 12:29:24.227939 [DQSOSCAuto] RK1, (LSB)MR18= 0x3341, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4801 12:29:24.231294 CH1 RK1: MR19=808, MR18=3341
4802 12:29:24.237918 CH1_RK1: MR19=0x808, MR18=0x3341, DQSOSC=397, MR23=63, INC=166, DEC=110
4803 12:29:24.241163 [RxdqsGatingPostProcess] freq 600
4804 12:29:24.244423 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4805 12:29:24.247833 Pre-setting of DQS Precalculation
4806 12:29:24.254457 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4807 12:29:24.261285 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4808 12:29:24.267850 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4809 12:29:24.267973
4810 12:29:24.268078
4811 12:29:24.271166 [Calibration Summary] 1200 Mbps
4812 12:29:24.271270 CH 0, Rank 0
4813 12:29:24.274422 SW Impedance : PASS
4814 12:29:24.277688 DUTY Scan : NO K
4815 12:29:24.277772 ZQ Calibration : PASS
4816 12:29:24.281042 Jitter Meter : NO K
4817 12:29:24.284246 CBT Training : PASS
4818 12:29:24.284329 Write leveling : PASS
4819 12:29:24.287327 RX DQS gating : PASS
4820 12:29:24.287430 RX DQ/DQS(RDDQC) : PASS
4821 12:29:24.291069 TX DQ/DQS : PASS
4822 12:29:24.294372 RX DATLAT : PASS
4823 12:29:24.294455 RX DQ/DQS(Engine): PASS
4824 12:29:24.297471 TX OE : NO K
4825 12:29:24.297568 All Pass.
4826 12:29:24.297635
4827 12:29:24.300705 CH 0, Rank 1
4828 12:29:24.300801 SW Impedance : PASS
4829 12:29:24.303950 DUTY Scan : NO K
4830 12:29:24.307290 ZQ Calibration : PASS
4831 12:29:24.307406 Jitter Meter : NO K
4832 12:29:24.310571 CBT Training : PASS
4833 12:29:24.313985 Write leveling : PASS
4834 12:29:24.314076 RX DQS gating : PASS
4835 12:29:24.317281 RX DQ/DQS(RDDQC) : PASS
4836 12:29:24.320627 TX DQ/DQS : PASS
4837 12:29:24.320710 RX DATLAT : PASS
4838 12:29:24.324064 RX DQ/DQS(Engine): PASS
4839 12:29:24.327224 TX OE : NO K
4840 12:29:24.327328 All Pass.
4841 12:29:24.327438
4842 12:29:24.327528 CH 1, Rank 0
4843 12:29:24.330623 SW Impedance : PASS
4844 12:29:24.333752 DUTY Scan : NO K
4845 12:29:24.333839 ZQ Calibration : PASS
4846 12:29:24.337032 Jitter Meter : NO K
4847 12:29:24.340362 CBT Training : PASS
4848 12:29:24.340453 Write leveling : PASS
4849 12:29:24.343763 RX DQS gating : PASS
4850 12:29:24.343840 RX DQ/DQS(RDDQC) : PASS
4851 12:29:24.346955 TX DQ/DQS : PASS
4852 12:29:24.350274 RX DATLAT : PASS
4853 12:29:24.350357 RX DQ/DQS(Engine): PASS
4854 12:29:24.353639 TX OE : NO K
4855 12:29:24.353721 All Pass.
4856 12:29:24.353788
4857 12:29:24.356844 CH 1, Rank 1
4858 12:29:24.356936 SW Impedance : PASS
4859 12:29:24.360732 DUTY Scan : NO K
4860 12:29:24.364065 ZQ Calibration : PASS
4861 12:29:24.364155 Jitter Meter : NO K
4862 12:29:24.367306 CBT Training : PASS
4863 12:29:24.370443 Write leveling : PASS
4864 12:29:24.370530 RX DQS gating : PASS
4865 12:29:24.373822 RX DQ/DQS(RDDQC) : PASS
4866 12:29:24.377044 TX DQ/DQS : PASS
4867 12:29:24.377137 RX DATLAT : PASS
4868 12:29:24.380243 RX DQ/DQS(Engine): PASS
4869 12:29:24.383598 TX OE : NO K
4870 12:29:24.383699 All Pass.
4871 12:29:24.383789
4872 12:29:24.383877 DramC Write-DBI off
4873 12:29:24.386845 PER_BANK_REFRESH: Hybrid Mode
4874 12:29:24.389993 TX_TRACKING: ON
4875 12:29:24.396944 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4876 12:29:24.400302 [FAST_K] Save calibration result to emmc
4877 12:29:24.406718 dramc_set_vcore_voltage set vcore to 662500
4878 12:29:24.406817 Read voltage for 933, 3
4879 12:29:24.409827 Vio18 = 0
4880 12:29:24.409919 Vcore = 662500
4881 12:29:24.410020 Vdram = 0
4882 12:29:24.413129 Vddq = 0
4883 12:29:24.413216 Vmddr = 0
4884 12:29:24.416422 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4885 12:29:24.422996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4886 12:29:24.426364 MEM_TYPE=3, freq_sel=17
4887 12:29:24.429650 sv_algorithm_assistance_LP4_1600
4888 12:29:24.433475 ============ PULL DRAM RESETB DOWN ============
4889 12:29:24.436233 ========== PULL DRAM RESETB DOWN end =========
4890 12:29:24.440158 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4891 12:29:24.442796 ===================================
4892 12:29:24.446176 LPDDR4 DRAM CONFIGURATION
4893 12:29:24.449390 ===================================
4894 12:29:24.452751 EX_ROW_EN[0] = 0x0
4895 12:29:24.452841 EX_ROW_EN[1] = 0x0
4896 12:29:24.456174 LP4Y_EN = 0x0
4897 12:29:24.456278 WORK_FSP = 0x0
4898 12:29:24.459401 WL = 0x3
4899 12:29:24.459509 RL = 0x3
4900 12:29:24.463217 BL = 0x2
4901 12:29:24.463326 RPST = 0x0
4902 12:29:24.466515 RD_PRE = 0x0
4903 12:29:24.469794 WR_PRE = 0x1
4904 12:29:24.469891 WR_PST = 0x0
4905 12:29:24.472911 DBI_WR = 0x0
4906 12:29:24.473017 DBI_RD = 0x0
4907 12:29:24.476150 OTF = 0x1
4908 12:29:24.479480 ===================================
4909 12:29:24.482590 ===================================
4910 12:29:24.482668 ANA top config
4911 12:29:24.486457 ===================================
4912 12:29:24.489814 DLL_ASYNC_EN = 0
4913 12:29:24.493101 ALL_SLAVE_EN = 1
4914 12:29:24.493184 NEW_RANK_MODE = 1
4915 12:29:24.496248 DLL_IDLE_MODE = 1
4916 12:29:24.499345 LP45_APHY_COMB_EN = 1
4917 12:29:24.502571 TX_ODT_DIS = 1
4918 12:29:24.502651 NEW_8X_MODE = 1
4919 12:29:24.505863 ===================================
4920 12:29:24.509199 ===================================
4921 12:29:24.512994 data_rate = 1866
4922 12:29:24.516250 CKR = 1
4923 12:29:24.519492 DQ_P2S_RATIO = 8
4924 12:29:24.522889 ===================================
4925 12:29:24.526254 CA_P2S_RATIO = 8
4926 12:29:24.529622 DQ_CA_OPEN = 0
4927 12:29:24.529710 DQ_SEMI_OPEN = 0
4928 12:29:24.532944 CA_SEMI_OPEN = 0
4929 12:29:24.536212 CA_FULL_RATE = 0
4930 12:29:24.539518 DQ_CKDIV4_EN = 1
4931 12:29:24.543001 CA_CKDIV4_EN = 1
4932 12:29:24.546294 CA_PREDIV_EN = 0
4933 12:29:24.546418 PH8_DLY = 0
4934 12:29:24.549491 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4935 12:29:24.552844 DQ_AAMCK_DIV = 4
4936 12:29:24.556242 CA_AAMCK_DIV = 4
4937 12:29:24.559486 CA_ADMCK_DIV = 4
4938 12:29:24.562839 DQ_TRACK_CA_EN = 0
4939 12:29:24.562928 CA_PICK = 933
4940 12:29:24.566222 CA_MCKIO = 933
4941 12:29:24.569492 MCKIO_SEMI = 0
4942 12:29:24.572778 PLL_FREQ = 3732
4943 12:29:24.576025 DQ_UI_PI_RATIO = 32
4944 12:29:24.579144 CA_UI_PI_RATIO = 0
4945 12:29:24.582375 ===================================
4946 12:29:24.585586 ===================================
4947 12:29:24.588803 memory_type:LPDDR4
4948 12:29:24.588902 GP_NUM : 10
4949 12:29:24.592174 SRAM_EN : 1
4950 12:29:24.592273 MD32_EN : 0
4951 12:29:24.595481 ===================================
4952 12:29:24.598715 [ANA_INIT] >>>>>>>>>>>>>>
4953 12:29:24.602464 <<<<<< [CONFIGURE PHASE]: ANA_TX
4954 12:29:24.605595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4955 12:29:24.608826 ===================================
4956 12:29:24.612698 data_rate = 1866,PCW = 0X8f00
4957 12:29:24.615917 ===================================
4958 12:29:24.619208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4959 12:29:24.622348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4960 12:29:24.629095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4961 12:29:24.632435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4962 12:29:24.638975 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4963 12:29:24.642270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4964 12:29:24.642346 [ANA_INIT] flow start
4965 12:29:24.645659 [ANA_INIT] PLL >>>>>>>>
4966 12:29:24.649091 [ANA_INIT] PLL <<<<<<<<
4967 12:29:24.649174 [ANA_INIT] MIDPI >>>>>>>>
4968 12:29:24.652268 [ANA_INIT] MIDPI <<<<<<<<
4969 12:29:24.655646 [ANA_INIT] DLL >>>>>>>>
4970 12:29:24.655723 [ANA_INIT] flow end
4971 12:29:24.658999 ============ LP4 DIFF to SE enter ============
4972 12:29:24.665556 ============ LP4 DIFF to SE exit ============
4973 12:29:24.665651 [ANA_INIT] <<<<<<<<<<<<<
4974 12:29:24.668807 [Flow] Enable top DCM control >>>>>
4975 12:29:24.672275 [Flow] Enable top DCM control <<<<<
4976 12:29:24.675572 Enable DLL master slave shuffle
4977 12:29:24.682091 ==============================================================
4978 12:29:24.682211 Gating Mode config
4979 12:29:24.688792 ==============================================================
4980 12:29:24.691899 Config description:
4981 12:29:24.701701 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4982 12:29:24.708582 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4983 12:29:24.711778 SELPH_MODE 0: By rank 1: By Phase
4984 12:29:24.718271 ==============================================================
4985 12:29:24.721644 GAT_TRACK_EN = 1
4986 12:29:24.725279 RX_GATING_MODE = 2
4987 12:29:24.725359 RX_GATING_TRACK_MODE = 2
4988 12:29:24.728678 SELPH_MODE = 1
4989 12:29:24.731894 PICG_EARLY_EN = 1
4990 12:29:24.735164 VALID_LAT_VALUE = 1
4991 12:29:24.741744 ==============================================================
4992 12:29:24.745100 Enter into Gating configuration >>>>
4993 12:29:24.748512 Exit from Gating configuration <<<<
4994 12:29:24.751874 Enter into DVFS_PRE_config >>>>>
4995 12:29:24.761689 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4996 12:29:24.764773 Exit from DVFS_PRE_config <<<<<
4997 12:29:24.768054 Enter into PICG configuration >>>>
4998 12:29:24.771335 Exit from PICG configuration <<<<
4999 12:29:24.775214 [RX_INPUT] configuration >>>>>
5000 12:29:24.778471 [RX_INPUT] configuration <<<<<
5001 12:29:24.781755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5002 12:29:24.788313 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5003 12:29:24.795197 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 12:29:24.801874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 12:29:24.805131 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 12:29:24.811332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 12:29:24.814506 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5008 12:29:24.821554 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5009 12:29:24.824673 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5010 12:29:24.827907 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5011 12:29:24.831068 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5012 12:29:24.838014 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 12:29:24.841356 ===================================
5014 12:29:24.844714 LPDDR4 DRAM CONFIGURATION
5015 12:29:24.844805 ===================================
5016 12:29:24.847882 EX_ROW_EN[0] = 0x0
5017 12:29:24.851238 EX_ROW_EN[1] = 0x0
5018 12:29:24.851380 LP4Y_EN = 0x0
5019 12:29:24.854489 WORK_FSP = 0x0
5020 12:29:24.854571 WL = 0x3
5021 12:29:24.857797 RL = 0x3
5022 12:29:24.857874 BL = 0x2
5023 12:29:24.861219 RPST = 0x0
5024 12:29:24.861304 RD_PRE = 0x0
5025 12:29:24.864462 WR_PRE = 0x1
5026 12:29:24.864537 WR_PST = 0x0
5027 12:29:24.867600 DBI_WR = 0x0
5028 12:29:24.867674 DBI_RD = 0x0
5029 12:29:24.870751 OTF = 0x1
5030 12:29:24.874174 ===================================
5031 12:29:24.877487 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5032 12:29:24.880865 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5033 12:29:24.887451 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 12:29:24.891184 ===================================
5035 12:29:24.891301 LPDDR4 DRAM CONFIGURATION
5036 12:29:24.894415 ===================================
5037 12:29:24.897734 EX_ROW_EN[0] = 0x10
5038 12:29:24.901012 EX_ROW_EN[1] = 0x0
5039 12:29:24.901117 LP4Y_EN = 0x0
5040 12:29:24.904199 WORK_FSP = 0x0
5041 12:29:24.904274 WL = 0x3
5042 12:29:24.907455 RL = 0x3
5043 12:29:24.907542 BL = 0x2
5044 12:29:24.910615 RPST = 0x0
5045 12:29:24.910699 RD_PRE = 0x0
5046 12:29:24.914300 WR_PRE = 0x1
5047 12:29:24.914402 WR_PST = 0x0
5048 12:29:24.917412 DBI_WR = 0x0
5049 12:29:24.917502 DBI_RD = 0x0
5050 12:29:24.920613 OTF = 0x1
5051 12:29:24.924329 ===================================
5052 12:29:24.930885 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5053 12:29:24.934071 nWR fixed to 30
5054 12:29:24.937487 [ModeRegInit_LP4] CH0 RK0
5055 12:29:24.937570 [ModeRegInit_LP4] CH0 RK1
5056 12:29:24.940885 [ModeRegInit_LP4] CH1 RK0
5057 12:29:24.944155 [ModeRegInit_LP4] CH1 RK1
5058 12:29:24.944230 match AC timing 9
5059 12:29:24.950829 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5060 12:29:24.954151 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5061 12:29:24.957512 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5062 12:29:24.964198 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5063 12:29:24.967464 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5064 12:29:24.967580 ==
5065 12:29:24.970739 Dram Type= 6, Freq= 0, CH_0, rank 0
5066 12:29:24.973925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 12:29:24.974001 ==
5068 12:29:24.980444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 12:29:24.987115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5070 12:29:24.990562 [CA 0] Center 38 (8~69) winsize 62
5071 12:29:24.993728 [CA 1] Center 38 (7~69) winsize 63
5072 12:29:24.996952 [CA 2] Center 35 (5~66) winsize 62
5073 12:29:25.000170 [CA 3] Center 35 (5~66) winsize 62
5074 12:29:25.003449 [CA 4] Center 34 (4~65) winsize 62
5075 12:29:25.006665 [CA 5] Center 34 (4~64) winsize 61
5076 12:29:25.006748
5077 12:29:25.010453 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5078 12:29:25.010536
5079 12:29:25.013847 [CATrainingPosCal] consider 1 rank data
5080 12:29:25.017089 u2DelayCellTimex100 = 270/100 ps
5081 12:29:25.020298 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5082 12:29:25.023466 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5083 12:29:25.026685 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5084 12:29:25.029830 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5085 12:29:25.033853 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5086 12:29:25.036971 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5087 12:29:25.037048
5088 12:29:25.043558 CA PerBit enable=1, Macro0, CA PI delay=34
5089 12:29:25.043646
5090 12:29:25.046909 [CBTSetCACLKResult] CA Dly = 34
5091 12:29:25.046995 CS Dly: 6 (0~37)
5092 12:29:25.047078 ==
5093 12:29:25.049601 Dram Type= 6, Freq= 0, CH_0, rank 1
5094 12:29:25.053596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 12:29:25.053670 ==
5096 12:29:25.059668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 12:29:25.066866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5098 12:29:25.069637 [CA 0] Center 38 (8~69) winsize 62
5099 12:29:25.073511 [CA 1] Center 38 (8~69) winsize 62
5100 12:29:25.076147 [CA 2] Center 35 (5~66) winsize 62
5101 12:29:25.079923 [CA 3] Center 35 (5~66) winsize 62
5102 12:29:25.083183 [CA 4] Center 34 (3~65) winsize 63
5103 12:29:25.086535 [CA 5] Center 33 (3~64) winsize 62
5104 12:29:25.086619
5105 12:29:25.089819 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5106 12:29:25.089892
5107 12:29:25.093151 [CATrainingPosCal] consider 2 rank data
5108 12:29:25.096372 u2DelayCellTimex100 = 270/100 ps
5109 12:29:25.099507 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5110 12:29:25.102609 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5111 12:29:25.106389 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5112 12:29:25.109558 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5113 12:29:25.112809 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5114 12:29:25.119451 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5115 12:29:25.119545
5116 12:29:25.122659 CA PerBit enable=1, Macro0, CA PI delay=34
5117 12:29:25.122742
5118 12:29:25.126214 [CBTSetCACLKResult] CA Dly = 34
5119 12:29:25.126329 CS Dly: 7 (0~39)
5120 12:29:25.126426
5121 12:29:25.129470 ----->DramcWriteLeveling(PI) begin...
5122 12:29:25.129571 ==
5123 12:29:25.132719 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 12:29:25.139075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 12:29:25.139185 ==
5126 12:29:25.142453 Write leveling (Byte 0): 29 => 29
5127 12:29:25.142557 Write leveling (Byte 1): 29 => 29
5128 12:29:25.145786 DramcWriteLeveling(PI) end<-----
5129 12:29:25.145896
5130 12:29:25.145991 ==
5131 12:29:25.149087 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 12:29:25.155789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 12:29:25.155875 ==
5134 12:29:25.159238 [Gating] SW mode calibration
5135 12:29:25.165768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5136 12:29:25.169047 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5137 12:29:25.175646 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5138 12:29:25.178985 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5139 12:29:25.182104 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 12:29:25.189289 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 12:29:25.192578 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 12:29:25.195836 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 12:29:25.202648 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 12:29:25.205724 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5145 12:29:25.208872 0 15 0 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
5146 12:29:25.215410 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5147 12:29:25.218796 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 12:29:25.222095 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 12:29:25.228683 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 12:29:25.232351 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 12:29:25.235631 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 12:29:25.241931 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5153 12:29:25.245145 1 0 0 | B1->B0 | 3333 4040 | 1 1 | (0 0) (0 0)
5154 12:29:25.248383 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5155 12:29:25.255135 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 12:29:25.258415 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 12:29:25.261770 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 12:29:25.268270 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 12:29:25.271571 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 12:29:25.274789 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5161 12:29:25.281898 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5162 12:29:25.285142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5163 12:29:25.288317 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:29:25.291435 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:29:25.298120 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:29:25.301277 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:29:25.304586 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:29:25.311765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:29:25.315020 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:29:25.318189 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:29:25.324798 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 12:29:25.328047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 12:29:25.331279 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 12:29:25.338122 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 12:29:25.341416 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:29:25.344583 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5177 12:29:25.350987 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5178 12:29:25.354120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 12:29:25.357479 Total UI for P1: 0, mck2ui 16
5180 12:29:25.360818 best dqsien dly found for B0: ( 1, 2, 30)
5181 12:29:25.364156 Total UI for P1: 0, mck2ui 16
5182 12:29:25.367524 best dqsien dly found for B1: ( 1, 3, 0)
5183 12:29:25.370852 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5184 12:29:25.374132 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5185 12:29:25.374215
5186 12:29:25.377241 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5187 12:29:25.381243 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5188 12:29:25.384342 [Gating] SW calibration Done
5189 12:29:25.384454 ==
5190 12:29:25.387592 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 12:29:25.394112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 12:29:25.394212 ==
5193 12:29:25.394289 RX Vref Scan: 0
5194 12:29:25.394353
5195 12:29:25.397491 RX Vref 0 -> 0, step: 1
5196 12:29:25.397574
5197 12:29:25.400816 RX Delay -80 -> 252, step: 8
5198 12:29:25.404070 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5199 12:29:25.407202 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5200 12:29:25.410552 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5201 12:29:25.413856 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5202 12:29:25.417177 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5203 12:29:25.423764 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5204 12:29:25.427585 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5205 12:29:25.430814 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5206 12:29:25.434103 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5207 12:29:25.437321 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5208 12:29:25.443701 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5209 12:29:25.446935 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5210 12:29:25.450733 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5211 12:29:25.453944 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5212 12:29:25.457243 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5213 12:29:25.460595 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5214 12:29:25.463993 ==
5215 12:29:25.464071 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 12:29:25.470591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 12:29:25.470668 ==
5218 12:29:25.470732 DQS Delay:
5219 12:29:25.473850 DQS0 = 0, DQS1 = 0
5220 12:29:25.473922 DQM Delay:
5221 12:29:25.477293 DQM0 = 98, DQM1 = 88
5222 12:29:25.477419 DQ Delay:
5223 12:29:25.480719 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5224 12:29:25.484020 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5225 12:29:25.487336 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5226 12:29:25.490518 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5227 12:29:25.490623
5228 12:29:25.490690
5229 12:29:25.490752 ==
5230 12:29:25.493794 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 12:29:25.497079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 12:29:25.497172 ==
5233 12:29:25.497248
5234 12:29:25.497310
5235 12:29:25.500295 TX Vref Scan disable
5236 12:29:25.503571 == TX Byte 0 ==
5237 12:29:25.506845 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5238 12:29:25.510065 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5239 12:29:25.513501 == TX Byte 1 ==
5240 12:29:25.516912 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5241 12:29:25.520114 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5242 12:29:25.520197 ==
5243 12:29:25.523290 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 12:29:25.529843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 12:29:25.529934 ==
5246 12:29:25.530002
5247 12:29:25.530064
5248 12:29:25.530130 TX Vref Scan disable
5249 12:29:25.533697 == TX Byte 0 ==
5250 12:29:25.536948 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5251 12:29:25.543478 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5252 12:29:25.543587 == TX Byte 1 ==
5253 12:29:25.546812 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5254 12:29:25.553842 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5255 12:29:25.553932
5256 12:29:25.554011 [DATLAT]
5257 12:29:25.554076 Freq=933, CH0 RK0
5258 12:29:25.554145
5259 12:29:25.557092 DATLAT Default: 0xd
5260 12:29:25.557201 0, 0xFFFF, sum = 0
5261 12:29:25.560497 1, 0xFFFF, sum = 0
5262 12:29:25.563816 2, 0xFFFF, sum = 0
5263 12:29:25.563939 3, 0xFFFF, sum = 0
5264 12:29:25.567069 4, 0xFFFF, sum = 0
5265 12:29:25.567170 5, 0xFFFF, sum = 0
5266 12:29:25.570573 6, 0xFFFF, sum = 0
5267 12:29:25.570658 7, 0xFFFF, sum = 0
5268 12:29:25.573867 8, 0xFFFF, sum = 0
5269 12:29:25.573954 9, 0xFFFF, sum = 0
5270 12:29:25.576575 10, 0x0, sum = 1
5271 12:29:25.576659 11, 0x0, sum = 2
5272 12:29:25.580002 12, 0x0, sum = 3
5273 12:29:25.580087 13, 0x0, sum = 4
5274 12:29:25.580164 best_step = 11
5275 12:29:25.583164
5276 12:29:25.583272 ==
5277 12:29:25.587126 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 12:29:25.589903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 12:29:25.589997 ==
5280 12:29:25.590063 RX Vref Scan: 1
5281 12:29:25.590126
5282 12:29:25.593240 RX Vref 0 -> 0, step: 1
5283 12:29:25.593329
5284 12:29:25.596504 RX Delay -61 -> 252, step: 4
5285 12:29:25.596595
5286 12:29:25.599864 Set Vref, RX VrefLevel [Byte0]: 53
5287 12:29:25.603151 [Byte1]: 51
5288 12:29:25.603256
5289 12:29:25.606477 Final RX Vref Byte 0 = 53 to rank0
5290 12:29:25.609787 Final RX Vref Byte 1 = 51 to rank0
5291 12:29:25.613121 Final RX Vref Byte 0 = 53 to rank1
5292 12:29:25.616836 Final RX Vref Byte 1 = 51 to rank1==
5293 12:29:25.620113 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 12:29:25.623459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 12:29:25.626710 ==
5296 12:29:25.626830 DQS Delay:
5297 12:29:25.626935 DQS0 = 0, DQS1 = 0
5298 12:29:25.629957 DQM Delay:
5299 12:29:25.630075 DQM0 = 96, DQM1 = 87
5300 12:29:25.633234 DQ Delay:
5301 12:29:25.636361 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5302 12:29:25.639520 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5303 12:29:25.642859 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =82
5304 12:29:25.646204 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5305 12:29:25.646281
5306 12:29:25.646366
5307 12:29:25.653264 [DQSOSCAuto] RK0, (LSB)MR18= 0x1500, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5308 12:29:25.656358 CH0 RK0: MR19=505, MR18=1500
5309 12:29:25.662683 CH0_RK0: MR19=0x505, MR18=0x1500, DQSOSC=415, MR23=63, INC=62, DEC=41
5310 12:29:25.662765
5311 12:29:25.666489 ----->DramcWriteLeveling(PI) begin...
5312 12:29:25.666607 ==
5313 12:29:25.669241 Dram Type= 6, Freq= 0, CH_0, rank 1
5314 12:29:25.672423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 12:29:25.672543 ==
5316 12:29:25.675689 Write leveling (Byte 0): 31 => 31
5317 12:29:25.679604 Write leveling (Byte 1): 31 => 31
5318 12:29:25.682891 DramcWriteLeveling(PI) end<-----
5319 12:29:25.682998
5320 12:29:25.683101 ==
5321 12:29:25.686247 Dram Type= 6, Freq= 0, CH_0, rank 1
5322 12:29:25.689525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 12:29:25.689626 ==
5324 12:29:25.692804 [Gating] SW mode calibration
5325 12:29:25.699299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5326 12:29:25.705457 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5327 12:29:25.709250 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5328 12:29:25.715834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 12:29:25.719090 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 12:29:25.722399 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 12:29:25.728792 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 12:29:25.731901 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 12:29:25.735741 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5334 12:29:25.742199 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5335 12:29:25.745558 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5336 12:29:25.749030 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5337 12:29:25.755388 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 12:29:25.758680 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 12:29:25.761936 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 12:29:25.768646 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 12:29:25.772499 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 12:29:25.775166 0 15 28 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)
5343 12:29:25.779103 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5344 12:29:25.785745 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 12:29:25.788498 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:29:25.792320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 12:29:25.798847 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 12:29:25.801432 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 12:29:25.808357 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 12:29:25.811471 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 12:29:25.815183 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5352 12:29:25.818366 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:29:25.825117 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:29:25.828555 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:29:25.831820 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:29:25.838260 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:29:25.841438 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:29:25.844618 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:29:25.851765 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:29:25.855126 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:29:25.858467 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:29:25.864864 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:29:25.868113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:29:25.871290 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:29:25.877552 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:29:25.881372 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5367 12:29:25.884837 Total UI for P1: 0, mck2ui 16
5368 12:29:25.888060 best dqsien dly found for B0: ( 1, 2, 26)
5369 12:29:25.891527 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5370 12:29:25.897597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 12:29:25.897679 Total UI for P1: 0, mck2ui 16
5372 12:29:25.904886 best dqsien dly found for B1: ( 1, 2, 30)
5373 12:29:25.908182 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5374 12:29:25.911433 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5375 12:29:25.911514
5376 12:29:25.914785 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5377 12:29:25.918015 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5378 12:29:25.921286 [Gating] SW calibration Done
5379 12:29:25.921371 ==
5380 12:29:25.924488 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 12:29:25.927828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 12:29:25.927921 ==
5383 12:29:25.931041 RX Vref Scan: 0
5384 12:29:25.931124
5385 12:29:25.931199 RX Vref 0 -> 0, step: 1
5386 12:29:25.931261
5387 12:29:25.934448 RX Delay -80 -> 252, step: 8
5388 12:29:25.938037 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5389 12:29:25.944177 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5390 12:29:25.947492 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5391 12:29:25.950717 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5392 12:29:25.953886 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5393 12:29:25.957105 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5394 12:29:25.960439 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5395 12:29:25.966936 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5396 12:29:25.970779 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5397 12:29:25.974136 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5398 12:29:25.977296 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5399 12:29:25.980705 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5400 12:29:25.987146 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5401 12:29:25.990355 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5402 12:29:25.993641 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5403 12:29:25.996858 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5404 12:29:25.996965 ==
5405 12:29:26.000109 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 12:29:26.003382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 12:29:26.006853 ==
5408 12:29:26.006925 DQS Delay:
5409 12:29:26.006989 DQS0 = 0, DQS1 = 0
5410 12:29:26.010150 DQM Delay:
5411 12:29:26.010226 DQM0 = 96, DQM1 = 87
5412 12:29:26.013443 DQ Delay:
5413 12:29:26.013544 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5414 12:29:26.016775 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =103
5415 12:29:26.020034 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5416 12:29:26.023308 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5417 12:29:26.027080
5418 12:29:26.027154
5419 12:29:26.027256 ==
5420 12:29:26.030360 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 12:29:26.033752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 12:29:26.033829 ==
5423 12:29:26.033930
5424 12:29:26.034031
5425 12:29:26.037151 TX Vref Scan disable
5426 12:29:26.037227 == TX Byte 0 ==
5427 12:29:26.043693 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5428 12:29:26.046801 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5429 12:29:26.046880 == TX Byte 1 ==
5430 12:29:26.053259 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5431 12:29:26.057004 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5432 12:29:26.057082 ==
5433 12:29:26.060552 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 12:29:26.063666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 12:29:26.063772 ==
5436 12:29:26.063867
5437 12:29:26.063961
5438 12:29:26.066977 TX Vref Scan disable
5439 12:29:26.070162 == TX Byte 0 ==
5440 12:29:26.073243 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5441 12:29:26.076378 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5442 12:29:26.080193 == TX Byte 1 ==
5443 12:29:26.083421 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5444 12:29:26.086594 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5445 12:29:26.086698
5446 12:29:26.089902 [DATLAT]
5447 12:29:26.090009 Freq=933, CH0 RK1
5448 12:29:26.090104
5449 12:29:26.093051 DATLAT Default: 0xb
5450 12:29:26.093149 0, 0xFFFF, sum = 0
5451 12:29:26.096403 1, 0xFFFF, sum = 0
5452 12:29:26.096501 2, 0xFFFF, sum = 0
5453 12:29:26.099758 3, 0xFFFF, sum = 0
5454 12:29:26.099857 4, 0xFFFF, sum = 0
5455 12:29:26.103195 5, 0xFFFF, sum = 0
5456 12:29:26.103297 6, 0xFFFF, sum = 0
5457 12:29:26.106428 7, 0xFFFF, sum = 0
5458 12:29:26.106542 8, 0xFFFF, sum = 0
5459 12:29:26.109856 9, 0xFFFF, sum = 0
5460 12:29:26.109963 10, 0x0, sum = 1
5461 12:29:26.113161 11, 0x0, sum = 2
5462 12:29:26.113265 12, 0x0, sum = 3
5463 12:29:26.116454 13, 0x0, sum = 4
5464 12:29:26.116554 best_step = 11
5465 12:29:26.116646
5466 12:29:26.116737 ==
5467 12:29:26.119884 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 12:29:26.126520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 12:29:26.126621 ==
5470 12:29:26.126714 RX Vref Scan: 0
5471 12:29:26.126802
5472 12:29:26.129734 RX Vref 0 -> 0, step: 1
5473 12:29:26.129834
5474 12:29:26.132972 RX Delay -61 -> 252, step: 4
5475 12:29:26.136332 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5476 12:29:26.139806 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5477 12:29:26.146163 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5478 12:29:26.149357 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5479 12:29:26.153258 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5480 12:29:26.156496 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5481 12:29:26.159873 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5482 12:29:26.162890 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5483 12:29:26.169444 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5484 12:29:26.172770 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5485 12:29:26.175975 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5486 12:29:26.179853 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5487 12:29:26.183081 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5488 12:29:26.186281 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5489 12:29:26.192791 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5490 12:29:26.196026 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5491 12:29:26.196129 ==
5492 12:29:26.199407 Dram Type= 6, Freq= 0, CH_0, rank 1
5493 12:29:26.202679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 12:29:26.202791 ==
5495 12:29:26.206006 DQS Delay:
5496 12:29:26.206107 DQS0 = 0, DQS1 = 0
5497 12:29:26.206199 DQM Delay:
5498 12:29:26.209240 DQM0 = 95, DQM1 = 87
5499 12:29:26.209325 DQ Delay:
5500 12:29:26.212592 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5501 12:29:26.215889 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5502 12:29:26.219054 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5503 12:29:26.222355 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5504 12:29:26.222466
5505 12:29:26.222562
5506 12:29:26.232714 [DQSOSCAuto] RK1, (LSB)MR18= 0x1705, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5507 12:29:26.232802 CH0 RK1: MR19=505, MR18=1705
5508 12:29:26.239328 CH0_RK1: MR19=0x505, MR18=0x1705, DQSOSC=414, MR23=63, INC=63, DEC=42
5509 12:29:26.242605 [RxdqsGatingPostProcess] freq 933
5510 12:29:26.249077 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5511 12:29:26.252892 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 12:29:26.256112 best DQS1 dly(2T, 0.5T) = (0, 11)
5513 12:29:26.259404 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 12:29:26.262750 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5515 12:29:26.266002 best DQS0 dly(2T, 0.5T) = (0, 10)
5516 12:29:26.269291 best DQS1 dly(2T, 0.5T) = (0, 10)
5517 12:29:26.272593 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5518 12:29:26.275905 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5519 12:29:26.275979 Pre-setting of DQS Precalculation
5520 12:29:26.282210 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5521 12:29:26.282294 ==
5522 12:29:26.285514 Dram Type= 6, Freq= 0, CH_1, rank 0
5523 12:29:26.288852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 12:29:26.288937 ==
5525 12:29:26.295342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 12:29:26.302025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5527 12:29:26.305805 [CA 0] Center 37 (7~67) winsize 61
5528 12:29:26.309198 [CA 1] Center 36 (6~67) winsize 62
5529 12:29:26.311861 [CA 2] Center 34 (4~65) winsize 62
5530 12:29:26.315795 [CA 3] Center 33 (3~64) winsize 62
5531 12:29:26.319164 [CA 4] Center 34 (4~65) winsize 62
5532 12:29:26.322279 [CA 5] Center 33 (3~64) winsize 62
5533 12:29:26.322353
5534 12:29:26.325739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5535 12:29:26.325812
5536 12:29:26.328988 [CATrainingPosCal] consider 1 rank data
5537 12:29:26.332195 u2DelayCellTimex100 = 270/100 ps
5538 12:29:26.335529 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5539 12:29:26.338859 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5540 12:29:26.342056 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5541 12:29:26.345380 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 12:29:26.348796 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5543 12:29:26.352144 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5544 12:29:26.355333
5545 12:29:26.358653 CA PerBit enable=1, Macro0, CA PI delay=33
5546 12:29:26.358762
5547 12:29:26.361747 [CBTSetCACLKResult] CA Dly = 33
5548 12:29:26.361856 CS Dly: 4 (0~35)
5549 12:29:26.361951 ==
5550 12:29:26.364829 Dram Type= 6, Freq= 0, CH_1, rank 1
5551 12:29:26.368231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 12:29:26.368352 ==
5553 12:29:26.374775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 12:29:26.381585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5555 12:29:26.385363 [CA 0] Center 36 (6~67) winsize 62
5556 12:29:26.388618 [CA 1] Center 37 (7~67) winsize 61
5557 12:29:26.391849 [CA 2] Center 34 (3~65) winsize 63
5558 12:29:26.394905 [CA 3] Center 33 (3~64) winsize 62
5559 12:29:26.398736 [CA 4] Center 33 (3~64) winsize 62
5560 12:29:26.401829 [CA 5] Center 32 (2~63) winsize 62
5561 12:29:26.401905
5562 12:29:26.405202 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5563 12:29:26.405277
5564 12:29:26.408563 [CATrainingPosCal] consider 2 rank data
5565 12:29:26.411872 u2DelayCellTimex100 = 270/100 ps
5566 12:29:26.415223 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5567 12:29:26.418550 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5568 12:29:26.421858 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 12:29:26.425268 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 12:29:26.428622 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 12:29:26.432024 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5572 12:29:26.435230
5573 12:29:26.438431 CA PerBit enable=1, Macro0, CA PI delay=33
5574 12:29:26.438507
5575 12:29:26.441808 [CBTSetCACLKResult] CA Dly = 33
5576 12:29:26.441881 CS Dly: 5 (0~38)
5577 12:29:26.441948
5578 12:29:26.445042 ----->DramcWriteLeveling(PI) begin...
5579 12:29:26.445116 ==
5580 12:29:26.448459 Dram Type= 6, Freq= 0, CH_1, rank 0
5581 12:29:26.451753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5582 12:29:26.454985 ==
5583 12:29:26.455060 Write leveling (Byte 0): 23 => 23
5584 12:29:26.458315 Write leveling (Byte 1): 30 => 30
5585 12:29:26.461602 DramcWriteLeveling(PI) end<-----
5586 12:29:26.461679
5587 12:29:26.461743 ==
5588 12:29:26.464684 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 12:29:26.471569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 12:29:26.471647 ==
5591 12:29:26.471716 [Gating] SW mode calibration
5592 12:29:26.481366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5593 12:29:26.484730 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5594 12:29:26.491144 0 14 0 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
5595 12:29:26.495095 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 12:29:26.498294 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 12:29:26.501698 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 12:29:26.508220 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 12:29:26.511460 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 12:29:26.514920 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5601 12:29:26.521629 0 14 28 | B1->B0 | 3030 2e2e | 1 1 | (1 0) (1 0)
5602 12:29:26.525036 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5603 12:29:26.528197 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 12:29:26.534828 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 12:29:26.538140 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 12:29:26.541375 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 12:29:26.548027 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 12:29:26.551236 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 12:29:26.554640 0 15 28 | B1->B0 | 2f2f 2d2d | 1 1 | (0 0) (0 0)
5610 12:29:26.561178 1 0 0 | B1->B0 | 4444 3f3f | 0 0 | (0 0) (0 0)
5611 12:29:26.564429 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:29:26.567787 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:29:26.574305 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:29:26.577561 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 12:29:26.580747 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 12:29:26.587329 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 12:29:26.590623 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5618 12:29:26.593908 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:29:26.600893 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:29:26.604042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:29:26.607299 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:29:26.613728 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:29:26.616987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:29:26.620837 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:29:26.626917 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:29:26.630166 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:29:26.633547 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:29:26.640170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:29:26.643493 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:29:26.646814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:29:26.653418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:29:26.657339 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5633 12:29:26.660492 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5634 12:29:26.667092 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5635 12:29:26.667201 Total UI for P1: 0, mck2ui 16
5636 12:29:26.673703 best dqsien dly found for B0: ( 1, 2, 26)
5637 12:29:26.676899 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 12:29:26.680112 Total UI for P1: 0, mck2ui 16
5639 12:29:26.683395 best dqsien dly found for B1: ( 1, 2, 28)
5640 12:29:26.686579 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5641 12:29:26.689880 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5642 12:29:26.689991
5643 12:29:26.693212 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5644 12:29:26.696609 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5645 12:29:26.700381 [Gating] SW calibration Done
5646 12:29:26.700485 ==
5647 12:29:26.703613 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 12:29:26.706644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 12:29:26.706757 ==
5650 12:29:26.709816 RX Vref Scan: 0
5651 12:29:26.709936
5652 12:29:26.713596 RX Vref 0 -> 0, step: 1
5653 12:29:26.713714
5654 12:29:26.713809 RX Delay -80 -> 252, step: 8
5655 12:29:26.720024 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5656 12:29:26.723455 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5657 12:29:26.726756 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5658 12:29:26.730054 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5659 12:29:26.733235 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5660 12:29:26.736619 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5661 12:29:26.743047 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5662 12:29:26.746373 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5663 12:29:26.749704 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5664 12:29:26.752891 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5665 12:29:26.756194 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5666 12:29:26.763325 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5667 12:29:26.766515 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5668 12:29:26.769731 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5669 12:29:26.773011 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5670 12:29:26.776436 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5671 12:29:26.776520 ==
5672 12:29:26.779628 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 12:29:26.786206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 12:29:26.786318 ==
5675 12:29:26.786428 DQS Delay:
5676 12:29:26.789369 DQS0 = 0, DQS1 = 0
5677 12:29:26.789474 DQM Delay:
5678 12:29:26.789571 DQM0 = 95, DQM1 = 88
5679 12:29:26.793287 DQ Delay:
5680 12:29:26.796492 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5681 12:29:26.799830 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5682 12:29:26.803122 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5683 12:29:26.806075 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5684 12:29:26.806164
5685 12:29:26.806259
5686 12:29:26.806349 ==
5687 12:29:26.809928 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 12:29:26.813189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 12:29:26.813274 ==
5690 12:29:26.813342
5691 12:29:26.813403
5692 12:29:26.816268 TX Vref Scan disable
5693 12:29:26.819370 == TX Byte 0 ==
5694 12:29:26.822647 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5695 12:29:26.825902 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5696 12:29:26.829833 == TX Byte 1 ==
5697 12:29:26.833181 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5698 12:29:26.836490 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5699 12:29:26.836574 ==
5700 12:29:26.839905 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:29:26.843126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:29:26.843234 ==
5703 12:29:26.846400
5704 12:29:26.846503
5705 12:29:26.846597 TX Vref Scan disable
5706 12:29:26.849824 == TX Byte 0 ==
5707 12:29:26.853227 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5708 12:29:26.856476 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5709 12:29:26.859750 == TX Byte 1 ==
5710 12:29:26.862963 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5711 12:29:26.869335 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5712 12:29:26.869419
5713 12:29:26.869498 [DATLAT]
5714 12:29:26.869566 Freq=933, CH1 RK0
5715 12:29:26.869629
5716 12:29:26.872738 DATLAT Default: 0xd
5717 12:29:26.872826 0, 0xFFFF, sum = 0
5718 12:29:26.876677 1, 0xFFFF, sum = 0
5719 12:29:26.876760 2, 0xFFFF, sum = 0
5720 12:29:26.879815 3, 0xFFFF, sum = 0
5721 12:29:26.883216 4, 0xFFFF, sum = 0
5722 12:29:26.883339 5, 0xFFFF, sum = 0
5723 12:29:26.886455 6, 0xFFFF, sum = 0
5724 12:29:26.886538 7, 0xFFFF, sum = 0
5725 12:29:26.889644 8, 0xFFFF, sum = 0
5726 12:29:26.889768 9, 0xFFFF, sum = 0
5727 12:29:26.892777 10, 0x0, sum = 1
5728 12:29:26.892881 11, 0x0, sum = 2
5729 12:29:26.892953 12, 0x0, sum = 3
5730 12:29:26.896040 13, 0x0, sum = 4
5731 12:29:26.896126 best_step = 11
5732 12:29:26.896239
5733 12:29:26.899309 ==
5734 12:29:26.899411 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 12:29:26.906001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:29:26.906124 ==
5737 12:29:26.906227 RX Vref Scan: 1
5738 12:29:26.906325
5739 12:29:26.909810 RX Vref 0 -> 0, step: 1
5740 12:29:26.909901
5741 12:29:26.912957 RX Delay -61 -> 252, step: 4
5742 12:29:26.913064
5743 12:29:26.916249 Set Vref, RX VrefLevel [Byte0]: 58
5744 12:29:26.919486 [Byte1]: 49
5745 12:29:26.919572
5746 12:29:26.922699 Final RX Vref Byte 0 = 58 to rank0
5747 12:29:26.926485 Final RX Vref Byte 1 = 49 to rank0
5748 12:29:26.929253 Final RX Vref Byte 0 = 58 to rank1
5749 12:29:26.932678 Final RX Vref Byte 1 = 49 to rank1==
5750 12:29:26.935919 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 12:29:26.939896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 12:29:26.939973 ==
5753 12:29:26.942611 DQS Delay:
5754 12:29:26.942723 DQS0 = 0, DQS1 = 0
5755 12:29:26.946475 DQM Delay:
5756 12:29:26.946554 DQM0 = 98, DQM1 = 90
5757 12:29:26.946641 DQ Delay:
5758 12:29:26.949788 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =98
5759 12:29:26.953071 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5760 12:29:26.956506 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =86
5761 12:29:26.959899 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5762 12:29:26.960008
5763 12:29:26.960102
5764 12:29:26.969059 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5765 12:29:26.972903 CH1 RK0: MR19=504, MR18=17F4
5766 12:29:26.979434 CH1_RK0: MR19=0x504, MR18=0x17F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5767 12:29:26.979544
5768 12:29:26.982866 ----->DramcWriteLeveling(PI) begin...
5769 12:29:26.982968 ==
5770 12:29:26.986024 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 12:29:26.989326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 12:29:26.989436 ==
5773 12:29:26.992505 Write leveling (Byte 0): 23 => 23
5774 12:29:26.996332 Write leveling (Byte 1): 25 => 25
5775 12:29:26.999569 DramcWriteLeveling(PI) end<-----
5776 12:29:26.999683
5777 12:29:26.999784 ==
5778 12:29:27.002932 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 12:29:27.006287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 12:29:27.006394 ==
5781 12:29:27.009551 [Gating] SW mode calibration
5782 12:29:27.015826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5783 12:29:27.022755 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5784 12:29:27.025951 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 12:29:27.029149 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 12:29:27.035683 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 12:29:27.038931 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 12:29:27.042205 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 12:29:27.049171 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5790 12:29:27.052501 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
5791 12:29:27.055859 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 12:29:27.062450 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 12:29:27.065784 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 12:29:27.069121 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 12:29:27.075482 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 12:29:27.078725 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5797 12:29:27.081959 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 12:29:27.088500 0 15 24 | B1->B0 | 2c2c 3b3b | 0 0 | (1 1) (0 0)
5799 12:29:27.091874 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5800 12:29:27.095205 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 12:29:27.102280 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 12:29:27.105363 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:29:27.108738 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 12:29:27.115121 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 12:29:27.118872 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5806 12:29:27.122166 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5807 12:29:27.128396 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:29:27.131766 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:29:27.135025 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:29:27.141462 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:29:27.145311 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:29:27.148631 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:29:27.155151 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:29:27.158792 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:29:27.161852 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:29:27.165281 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:29:27.171879 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:29:27.174662 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:29:27.178584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:29:27.184988 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:29:27.188216 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:29:27.191557 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5823 12:29:27.198218 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 12:29:27.201433 Total UI for P1: 0, mck2ui 16
5825 12:29:27.204748 best dqsien dly found for B0: ( 1, 2, 24)
5826 12:29:27.204841 Total UI for P1: 0, mck2ui 16
5827 12:29:27.211197 best dqsien dly found for B1: ( 1, 2, 24)
5828 12:29:27.214422 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5829 12:29:27.217729 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5830 12:29:27.217809
5831 12:29:27.221596 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5832 12:29:27.224807 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5833 12:29:27.227956 [Gating] SW calibration Done
5834 12:29:27.228044 ==
5835 12:29:27.231170 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 12:29:27.234362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 12:29:27.234445 ==
5838 12:29:27.237567 RX Vref Scan: 0
5839 12:29:27.237687
5840 12:29:27.237792 RX Vref 0 -> 0, step: 1
5841 12:29:27.241369
5842 12:29:27.241484 RX Delay -80 -> 252, step: 8
5843 12:29:27.247964 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5844 12:29:27.251274 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5845 12:29:27.254712 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5846 12:29:27.257996 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5847 12:29:27.261408 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5848 12:29:27.264615 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5849 12:29:27.271171 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5850 12:29:27.274430 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5851 12:29:27.277839 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5852 12:29:27.281011 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5853 12:29:27.284338 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5854 12:29:27.287476 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5855 12:29:27.294087 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5856 12:29:27.297384 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5857 12:29:27.300713 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5858 12:29:27.303982 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5859 12:29:27.304072 ==
5860 12:29:27.307177 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 12:29:27.311004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 12:29:27.314278 ==
5863 12:29:27.314363 DQS Delay:
5864 12:29:27.314429 DQS0 = 0, DQS1 = 0
5865 12:29:27.317499 DQM Delay:
5866 12:29:27.317583 DQM0 = 94, DQM1 = 89
5867 12:29:27.320821 DQ Delay:
5868 12:29:27.320902 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5869 12:29:27.324110 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5870 12:29:27.327308 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5871 12:29:27.330412 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5872 12:29:27.333692
5873 12:29:27.333776
5874 12:29:27.333847 ==
5875 12:29:27.337304 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 12:29:27.340614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 12:29:27.340706 ==
5878 12:29:27.340780
5879 12:29:27.340849
5880 12:29:27.343824 TX Vref Scan disable
5881 12:29:27.343917 == TX Byte 0 ==
5882 12:29:27.350227 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5883 12:29:27.353552 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5884 12:29:27.353638 == TX Byte 1 ==
5885 12:29:27.360327 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5886 12:29:27.363562 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5887 12:29:27.363649 ==
5888 12:29:27.366842 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 12:29:27.370122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 12:29:27.370209 ==
5891 12:29:27.370281
5892 12:29:27.370353
5893 12:29:27.373397 TX Vref Scan disable
5894 12:29:27.377352 == TX Byte 0 ==
5895 12:29:27.380087 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5896 12:29:27.383407 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5897 12:29:27.386667 == TX Byte 1 ==
5898 12:29:27.389910 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5899 12:29:27.393762 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5900 12:29:27.393849
5901 12:29:27.397123 [DATLAT]
5902 12:29:27.397200 Freq=933, CH1 RK1
5903 12:29:27.397279
5904 12:29:27.400395 DATLAT Default: 0xb
5905 12:29:27.400474 0, 0xFFFF, sum = 0
5906 12:29:27.403914 1, 0xFFFF, sum = 0
5907 12:29:27.403999 2, 0xFFFF, sum = 0
5908 12:29:27.406599 3, 0xFFFF, sum = 0
5909 12:29:27.406677 4, 0xFFFF, sum = 0
5910 12:29:27.410480 5, 0xFFFF, sum = 0
5911 12:29:27.410562 6, 0xFFFF, sum = 0
5912 12:29:27.413727 7, 0xFFFF, sum = 0
5913 12:29:27.413811 8, 0xFFFF, sum = 0
5914 12:29:27.416854 9, 0xFFFF, sum = 0
5915 12:29:27.416930 10, 0x0, sum = 1
5916 12:29:27.419894 11, 0x0, sum = 2
5917 12:29:27.419970 12, 0x0, sum = 3
5918 12:29:27.423266 13, 0x0, sum = 4
5919 12:29:27.423374 best_step = 11
5920 12:29:27.423448
5921 12:29:27.423519 ==
5922 12:29:27.426648 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 12:29:27.433514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 12:29:27.433600 ==
5925 12:29:27.433666 RX Vref Scan: 0
5926 12:29:27.433729
5927 12:29:27.436779 RX Vref 0 -> 0, step: 1
5928 12:29:27.436862
5929 12:29:27.440023 RX Delay -61 -> 252, step: 4
5930 12:29:27.443249 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5931 12:29:27.446486 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5932 12:29:27.453374 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5933 12:29:27.456729 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5934 12:29:27.460111 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5935 12:29:27.463372 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5936 12:29:27.466748 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5937 12:29:27.470024 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5938 12:29:27.476641 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5939 12:29:27.479973 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5940 12:29:27.483152 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5941 12:29:27.486421 iDelay=199, Bit 11, Center 86 (-1 ~ 174) 176
5942 12:29:27.489834 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5943 12:29:27.496220 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5944 12:29:27.499458 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5945 12:29:27.503436 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5946 12:29:27.503523 ==
5947 12:29:27.506302 Dram Type= 6, Freq= 0, CH_1, rank 1
5948 12:29:27.509646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5949 12:29:27.509737 ==
5950 12:29:27.513017 DQS Delay:
5951 12:29:27.513110 DQS0 = 0, DQS1 = 0
5952 12:29:27.516219 DQM Delay:
5953 12:29:27.516314 DQM0 = 96, DQM1 = 90
5954 12:29:27.516387 DQ Delay:
5955 12:29:27.519472 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5956 12:29:27.523311 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =92
5957 12:29:27.526642 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =86
5958 12:29:27.529926 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =98
5959 12:29:27.530045
5960 12:29:27.530140
5961 12:29:27.539589 [DQSOSCAuto] RK1, (LSB)MR18= 0xf18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5962 12:29:27.542828 CH1 RK1: MR19=505, MR18=F18
5963 12:29:27.546026 CH1_RK1: MR19=0x505, MR18=0xF18, DQSOSC=414, MR23=63, INC=63, DEC=42
5964 12:29:27.549429 [RxdqsGatingPostProcess] freq 933
5965 12:29:27.555860 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5966 12:29:27.559269 best DQS0 dly(2T, 0.5T) = (0, 10)
5967 12:29:27.562707 best DQS1 dly(2T, 0.5T) = (0, 10)
5968 12:29:27.566075 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5969 12:29:27.569474 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5970 12:29:27.572792 best DQS0 dly(2T, 0.5T) = (0, 10)
5971 12:29:27.576175 best DQS1 dly(2T, 0.5T) = (0, 10)
5972 12:29:27.579438 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5973 12:29:27.582799 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5974 12:29:27.586081 Pre-setting of DQS Precalculation
5975 12:29:27.589367 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5976 12:29:27.596002 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5977 12:29:27.602469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5978 12:29:27.602551
5979 12:29:27.602630
5980 12:29:27.605792 [Calibration Summary] 1866 Mbps
5981 12:29:27.608986 CH 0, Rank 0
5982 12:29:27.609060 SW Impedance : PASS
5983 12:29:27.612853 DUTY Scan : NO K
5984 12:29:27.616170 ZQ Calibration : PASS
5985 12:29:27.616261 Jitter Meter : NO K
5986 12:29:27.619453 CBT Training : PASS
5987 12:29:27.622636 Write leveling : PASS
5988 12:29:27.622746 RX DQS gating : PASS
5989 12:29:27.625927 RX DQ/DQS(RDDQC) : PASS
5990 12:29:27.629198 TX DQ/DQS : PASS
5991 12:29:27.629274 RX DATLAT : PASS
5992 12:29:27.632456 RX DQ/DQS(Engine): PASS
5993 12:29:27.632531 TX OE : NO K
5994 12:29:27.635725 All Pass.
5995 12:29:27.635801
5996 12:29:27.635865 CH 0, Rank 1
5997 12:29:27.639136 SW Impedance : PASS
5998 12:29:27.642303 DUTY Scan : NO K
5999 12:29:27.642393 ZQ Calibration : PASS
6000 12:29:27.645597 Jitter Meter : NO K
6001 12:29:27.645700 CBT Training : PASS
6002 12:29:27.648802 Write leveling : PASS
6003 12:29:27.652064 RX DQS gating : PASS
6004 12:29:27.652166 RX DQ/DQS(RDDQC) : PASS
6005 12:29:27.655272 TX DQ/DQS : PASS
6006 12:29:27.658676 RX DATLAT : PASS
6007 12:29:27.658784 RX DQ/DQS(Engine): PASS
6008 12:29:27.661983 TX OE : NO K
6009 12:29:27.662087 All Pass.
6010 12:29:27.662185
6011 12:29:27.665229 CH 1, Rank 0
6012 12:29:27.665334 SW Impedance : PASS
6013 12:29:27.668603 DUTY Scan : NO K
6014 12:29:27.672470 ZQ Calibration : PASS
6015 12:29:27.672573 Jitter Meter : NO K
6016 12:29:27.675880 CBT Training : PASS
6017 12:29:27.678555 Write leveling : PASS
6018 12:29:27.678655 RX DQS gating : PASS
6019 12:29:27.682508 RX DQ/DQS(RDDQC) : PASS
6020 12:29:27.685794 TX DQ/DQS : PASS
6021 12:29:27.685921 RX DATLAT : PASS
6022 12:29:27.689008 RX DQ/DQS(Engine): PASS
6023 12:29:27.689126 TX OE : NO K
6024 12:29:27.692372 All Pass.
6025 12:29:27.692459
6026 12:29:27.692545 CH 1, Rank 1
6027 12:29:27.695601 SW Impedance : PASS
6028 12:29:27.698908 DUTY Scan : NO K
6029 12:29:27.698995 ZQ Calibration : PASS
6030 12:29:27.702272 Jitter Meter : NO K
6031 12:29:27.702359 CBT Training : PASS
6032 12:29:27.705369 Write leveling : PASS
6033 12:29:27.708690 RX DQS gating : PASS
6034 12:29:27.708777 RX DQ/DQS(RDDQC) : PASS
6035 12:29:27.711908 TX DQ/DQS : PASS
6036 12:29:27.715362 RX DATLAT : PASS
6037 12:29:27.715447 RX DQ/DQS(Engine): PASS
6038 12:29:27.718611 TX OE : NO K
6039 12:29:27.718801 All Pass.
6040 12:29:27.718931
6041 12:29:27.721950 DramC Write-DBI off
6042 12:29:27.725171 PER_BANK_REFRESH: Hybrid Mode
6043 12:29:27.725298 TX_TRACKING: ON
6044 12:29:27.734790 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6045 12:29:27.738723 [FAST_K] Save calibration result to emmc
6046 12:29:27.741970 dramc_set_vcore_voltage set vcore to 650000
6047 12:29:27.745340 Read voltage for 400, 6
6048 12:29:27.745415 Vio18 = 0
6049 12:29:27.745520 Vcore = 650000
6050 12:29:27.748490 Vdram = 0
6051 12:29:27.748631 Vddq = 0
6052 12:29:27.748816 Vmddr = 0
6053 12:29:27.754821 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6054 12:29:27.757943 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6055 12:29:27.761786 MEM_TYPE=3, freq_sel=20
6056 12:29:27.764971 sv_algorithm_assistance_LP4_800
6057 12:29:27.768252 ============ PULL DRAM RESETB DOWN ============
6058 12:29:27.774839 ========== PULL DRAM RESETB DOWN end =========
6059 12:29:27.778135 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6060 12:29:27.781360 ===================================
6061 12:29:27.784635 LPDDR4 DRAM CONFIGURATION
6062 12:29:27.787933 ===================================
6063 12:29:27.788016 EX_ROW_EN[0] = 0x0
6064 12:29:27.791676 EX_ROW_EN[1] = 0x0
6065 12:29:27.791757 LP4Y_EN = 0x0
6066 12:29:27.794373 WORK_FSP = 0x0
6067 12:29:27.794486 WL = 0x2
6068 12:29:27.797682 RL = 0x2
6069 12:29:27.797788 BL = 0x2
6070 12:29:27.801028 RPST = 0x0
6071 12:29:27.801103 RD_PRE = 0x0
6072 12:29:27.805011 WR_PRE = 0x1
6073 12:29:27.808136 WR_PST = 0x0
6074 12:29:27.808265 DBI_WR = 0x0
6075 12:29:27.811435 DBI_RD = 0x0
6076 12:29:27.811546 OTF = 0x1
6077 12:29:27.814652 ===================================
6078 12:29:27.817856 ===================================
6079 12:29:27.817966 ANA top config
6080 12:29:27.821213 ===================================
6081 12:29:27.824658 DLL_ASYNC_EN = 0
6082 12:29:27.827907 ALL_SLAVE_EN = 1
6083 12:29:27.831225 NEW_RANK_MODE = 1
6084 12:29:27.834578 DLL_IDLE_MODE = 1
6085 12:29:27.834653 LP45_APHY_COMB_EN = 1
6086 12:29:27.837765 TX_ODT_DIS = 1
6087 12:29:27.841244 NEW_8X_MODE = 1
6088 12:29:27.844448 ===================================
6089 12:29:27.847219 ===================================
6090 12:29:27.850933 data_rate = 800
6091 12:29:27.854178 CKR = 1
6092 12:29:27.854276 DQ_P2S_RATIO = 4
6093 12:29:27.857477 ===================================
6094 12:29:27.860782 CA_P2S_RATIO = 4
6095 12:29:27.863915 DQ_CA_OPEN = 0
6096 12:29:27.867191 DQ_SEMI_OPEN = 1
6097 12:29:27.870443 CA_SEMI_OPEN = 1
6098 12:29:27.873817 CA_FULL_RATE = 0
6099 12:29:27.873893 DQ_CKDIV4_EN = 0
6100 12:29:27.877110 CA_CKDIV4_EN = 1
6101 12:29:27.880434 CA_PREDIV_EN = 0
6102 12:29:27.883699 PH8_DLY = 0
6103 12:29:27.887580 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6104 12:29:27.890826 DQ_AAMCK_DIV = 0
6105 12:29:27.890929 CA_AAMCK_DIV = 0
6106 12:29:27.894116 CA_ADMCK_DIV = 4
6107 12:29:27.897295 DQ_TRACK_CA_EN = 0
6108 12:29:27.900786 CA_PICK = 800
6109 12:29:27.904050 CA_MCKIO = 400
6110 12:29:27.907394 MCKIO_SEMI = 400
6111 12:29:27.910820 PLL_FREQ = 3016
6112 12:29:27.914082 DQ_UI_PI_RATIO = 32
6113 12:29:27.914189 CA_UI_PI_RATIO = 32
6114 12:29:27.917242 ===================================
6115 12:29:27.920503 ===================================
6116 12:29:27.923842 memory_type:LPDDR4
6117 12:29:27.927148 GP_NUM : 10
6118 12:29:27.927250 SRAM_EN : 1
6119 12:29:27.930462 MD32_EN : 0
6120 12:29:27.933583 ===================================
6121 12:29:27.936731 [ANA_INIT] >>>>>>>>>>>>>>
6122 12:29:27.940403 <<<<<< [CONFIGURE PHASE]: ANA_TX
6123 12:29:27.943569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6124 12:29:27.946914 ===================================
6125 12:29:27.947022 data_rate = 800,PCW = 0X7400
6126 12:29:27.950288 ===================================
6127 12:29:27.953466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6128 12:29:27.960341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6129 12:29:27.970202 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 12:29:27.976782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6131 12:29:27.980125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6132 12:29:27.983593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6133 12:29:27.986810 [ANA_INIT] flow start
6134 12:29:27.986894 [ANA_INIT] PLL >>>>>>>>
6135 12:29:27.990088 [ANA_INIT] PLL <<<<<<<<
6136 12:29:27.993328 [ANA_INIT] MIDPI >>>>>>>>
6137 12:29:27.993406 [ANA_INIT] MIDPI <<<<<<<<
6138 12:29:27.996589 [ANA_INIT] DLL >>>>>>>>
6139 12:29:28.000580 [ANA_INIT] flow end
6140 12:29:28.003866 ============ LP4 DIFF to SE enter ============
6141 12:29:28.007169 ============ LP4 DIFF to SE exit ============
6142 12:29:28.010572 [ANA_INIT] <<<<<<<<<<<<<
6143 12:29:28.013796 [Flow] Enable top DCM control >>>>>
6144 12:29:28.017130 [Flow] Enable top DCM control <<<<<
6145 12:29:28.020299 Enable DLL master slave shuffle
6146 12:29:28.023488 ==============================================================
6147 12:29:28.026778 Gating Mode config
6148 12:29:28.030171 ==============================================================
6149 12:29:28.033359 Config description:
6150 12:29:28.043847 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6151 12:29:28.050261 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6152 12:29:28.053655 SELPH_MODE 0: By rank 1: By Phase
6153 12:29:28.060129 ==============================================================
6154 12:29:28.063272 GAT_TRACK_EN = 0
6155 12:29:28.066375 RX_GATING_MODE = 2
6156 12:29:28.069704 RX_GATING_TRACK_MODE = 2
6157 12:29:28.073500 SELPH_MODE = 1
6158 12:29:28.076796 PICG_EARLY_EN = 1
6159 12:29:28.080046 VALID_LAT_VALUE = 1
6160 12:29:28.083338 ==============================================================
6161 12:29:28.086655 Enter into Gating configuration >>>>
6162 12:29:28.089925 Exit from Gating configuration <<<<
6163 12:29:28.093368 Enter into DVFS_PRE_config >>>>>
6164 12:29:28.103160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6165 12:29:28.106464 Exit from DVFS_PRE_config <<<<<
6166 12:29:28.109933 Enter into PICG configuration >>>>
6167 12:29:28.113152 Exit from PICG configuration <<<<
6168 12:29:28.116493 [RX_INPUT] configuration >>>>>
6169 12:29:28.119981 [RX_INPUT] configuration <<<<<
6170 12:29:28.126520 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6171 12:29:28.129804 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6172 12:29:28.136194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 12:29:28.142806 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 12:29:28.149348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 12:29:28.156484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 12:29:28.159781 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6177 12:29:28.163039 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6178 12:29:28.166149 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6179 12:29:28.172439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6180 12:29:28.176270 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6181 12:29:28.179644 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 12:29:28.182875 ===================================
6183 12:29:28.186164 LPDDR4 DRAM CONFIGURATION
6184 12:29:28.189506 ===================================
6185 12:29:28.189584 EX_ROW_EN[0] = 0x0
6186 12:29:28.192673 EX_ROW_EN[1] = 0x0
6187 12:29:28.195936 LP4Y_EN = 0x0
6188 12:29:28.196013 WORK_FSP = 0x0
6189 12:29:28.199195 WL = 0x2
6190 12:29:28.199305 RL = 0x2
6191 12:29:28.202538 BL = 0x2
6192 12:29:28.202621 RPST = 0x0
6193 12:29:28.205832 RD_PRE = 0x0
6194 12:29:28.205917 WR_PRE = 0x1
6195 12:29:28.209119 WR_PST = 0x0
6196 12:29:28.209202 DBI_WR = 0x0
6197 12:29:28.212545 DBI_RD = 0x0
6198 12:29:28.212627 OTF = 0x1
6199 12:29:28.215612 ===================================
6200 12:29:28.218912 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6201 12:29:28.225667 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6202 12:29:28.228874 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 12:29:28.232218 ===================================
6204 12:29:28.235515 LPDDR4 DRAM CONFIGURATION
6205 12:29:28.238753 ===================================
6206 12:29:28.238836 EX_ROW_EN[0] = 0x10
6207 12:29:28.242214 EX_ROW_EN[1] = 0x0
6208 12:29:28.245426 LP4Y_EN = 0x0
6209 12:29:28.245509 WORK_FSP = 0x0
6210 12:29:28.248633 WL = 0x2
6211 12:29:28.248715 RL = 0x2
6212 12:29:28.251717 BL = 0x2
6213 12:29:28.251800 RPST = 0x0
6214 12:29:28.255675 RD_PRE = 0x0
6215 12:29:28.255758 WR_PRE = 0x1
6216 12:29:28.258840 WR_PST = 0x0
6217 12:29:28.258923 DBI_WR = 0x0
6218 12:29:28.262114 DBI_RD = 0x0
6219 12:29:28.262197 OTF = 0x1
6220 12:29:28.265413 ===================================
6221 12:29:28.271940 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6222 12:29:28.276323 nWR fixed to 30
6223 12:29:28.279437 [ModeRegInit_LP4] CH0 RK0
6224 12:29:28.279519 [ModeRegInit_LP4] CH0 RK1
6225 12:29:28.282623 [ModeRegInit_LP4] CH1 RK0
6226 12:29:28.286530 [ModeRegInit_LP4] CH1 RK1
6227 12:29:28.286613 match AC timing 19
6228 12:29:28.293017 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6229 12:29:28.296056 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6230 12:29:28.299368 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6231 12:29:28.305922 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6232 12:29:28.309248 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6233 12:29:28.309351 ==
6234 12:29:28.312678 Dram Type= 6, Freq= 0, CH_0, rank 0
6235 12:29:28.315905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 12:29:28.315989 ==
6237 12:29:28.322402 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 12:29:28.329075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6239 12:29:28.332384 [CA 0] Center 36 (8~64) winsize 57
6240 12:29:28.335739 [CA 1] Center 36 (8~64) winsize 57
6241 12:29:28.338930 [CA 2] Center 36 (8~64) winsize 57
6242 12:29:28.342218 [CA 3] Center 36 (8~64) winsize 57
6243 12:29:28.342320 [CA 4] Center 36 (8~64) winsize 57
6244 12:29:28.346178 [CA 5] Center 36 (8~64) winsize 57
6245 12:29:28.346249
6246 12:29:28.352605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6247 12:29:28.352680
6248 12:29:28.355781 [CATrainingPosCal] consider 1 rank data
6249 12:29:28.358963 u2DelayCellTimex100 = 270/100 ps
6250 12:29:28.362193 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:29:28.365564 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:29:28.368910 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:29:28.372221 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:29:28.375474 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 12:29:28.379291 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:29:28.379396
6257 12:29:28.382572 CA PerBit enable=1, Macro0, CA PI delay=36
6258 12:29:28.382659
6259 12:29:28.385755 [CBTSetCACLKResult] CA Dly = 36
6260 12:29:28.389124 CS Dly: 1 (0~32)
6261 12:29:28.389206 ==
6262 12:29:28.392214 Dram Type= 6, Freq= 0, CH_0, rank 1
6263 12:29:28.395728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 12:29:28.395811 ==
6265 12:29:28.402256 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6266 12:29:28.408824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6267 12:29:28.408908 [CA 0] Center 36 (8~64) winsize 57
6268 12:29:28.412206 [CA 1] Center 36 (8~64) winsize 57
6269 12:29:28.415633 [CA 2] Center 36 (8~64) winsize 57
6270 12:29:28.418823 [CA 3] Center 36 (8~64) winsize 57
6271 12:29:28.422131 [CA 4] Center 36 (8~64) winsize 57
6272 12:29:28.425374 [CA 5] Center 36 (8~64) winsize 57
6273 12:29:28.425489
6274 12:29:28.428689 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6275 12:29:28.428776
6276 12:29:28.431965 [CATrainingPosCal] consider 2 rank data
6277 12:29:28.435277 u2DelayCellTimex100 = 270/100 ps
6278 12:29:28.438584 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:29:28.445024 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:29:28.448368 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:29:28.451645 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:29:28.455018 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:29:28.458278 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:29:28.458361
6285 12:29:28.461461 CA PerBit enable=1, Macro0, CA PI delay=36
6286 12:29:28.461560
6287 12:29:28.464718 [CBTSetCACLKResult] CA Dly = 36
6288 12:29:28.467826 CS Dly: 1 (0~32)
6289 12:29:28.467910
6290 12:29:28.471831 ----->DramcWriteLeveling(PI) begin...
6291 12:29:28.471916 ==
6292 12:29:28.474662 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 12:29:28.477999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 12:29:28.478089 ==
6295 12:29:28.481152 Write leveling (Byte 0): 40 => 8
6296 12:29:28.484997 Write leveling (Byte 1): 32 => 0
6297 12:29:28.488123 DramcWriteLeveling(PI) end<-----
6298 12:29:28.488207
6299 12:29:28.488272 ==
6300 12:29:28.491903 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 12:29:28.495126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 12:29:28.495234 ==
6303 12:29:28.498194 [Gating] SW mode calibration
6304 12:29:28.505056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6305 12:29:28.511475 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6306 12:29:28.514823 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6307 12:29:28.518216 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 12:29:28.524893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 12:29:28.528258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 12:29:28.531527 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 12:29:28.538196 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 12:29:28.540945 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 12:29:28.544860 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 12:29:28.551533 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 12:29:28.551638 Total UI for P1: 0, mck2ui 16
6316 12:29:28.554816 best dqsien dly found for B0: ( 0, 14, 24)
6317 12:29:28.558057 Total UI for P1: 0, mck2ui 16
6318 12:29:28.561343 best dqsien dly found for B1: ( 0, 14, 24)
6319 12:29:28.564685 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6320 12:29:28.571016 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6321 12:29:28.571122
6322 12:29:28.574247 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6323 12:29:28.577442 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 12:29:28.580833 [Gating] SW calibration Done
6325 12:29:28.580933 ==
6326 12:29:28.584140 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 12:29:28.587816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 12:29:28.587926 ==
6329 12:29:28.591175 RX Vref Scan: 0
6330 12:29:28.591282
6331 12:29:28.591383 RX Vref 0 -> 0, step: 1
6332 12:29:28.591476
6333 12:29:28.594307 RX Delay -410 -> 252, step: 16
6334 12:29:28.597442 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6335 12:29:28.604314 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6336 12:29:28.607433 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6337 12:29:28.611254 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6338 12:29:28.614550 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6339 12:29:28.620540 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6340 12:29:28.624493 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6341 12:29:28.627169 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6342 12:29:28.631205 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6343 12:29:28.637822 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6344 12:29:28.641078 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6345 12:29:28.643819 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6346 12:29:28.651164 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6347 12:29:28.654391 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6348 12:29:28.657101 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6349 12:29:28.660416 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6350 12:29:28.660497 ==
6351 12:29:28.663739 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 12:29:28.670388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 12:29:28.670496 ==
6354 12:29:28.670591 DQS Delay:
6355 12:29:28.674172 DQS0 = 43, DQS1 = 51
6356 12:29:28.674285 DQM Delay:
6357 12:29:28.677360 DQM0 = 12, DQM1 = 10
6358 12:29:28.677465 DQ Delay:
6359 12:29:28.680606 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6360 12:29:28.683909 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6361 12:29:28.683999 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6362 12:29:28.687190 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6363 12:29:28.690388
6364 12:29:28.690474
6365 12:29:28.690568 ==
6366 12:29:28.693561 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 12:29:28.696765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 12:29:28.696849 ==
6369 12:29:28.696936
6370 12:29:28.697018
6371 12:29:28.700666 TX Vref Scan disable
6372 12:29:28.700753 == TX Byte 0 ==
6373 12:29:28.703933 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 12:29:28.710253 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 12:29:28.710341 == TX Byte 1 ==
6376 12:29:28.714067 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6377 12:29:28.720599 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6378 12:29:28.720712 ==
6379 12:29:28.723955 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 12:29:28.727155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 12:29:28.727260 ==
6382 12:29:28.727359
6383 12:29:28.727447
6384 12:29:28.730359 TX Vref Scan disable
6385 12:29:28.730452 == TX Byte 0 ==
6386 12:29:28.737071 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 12:29:28.740368 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 12:29:28.740454 == TX Byte 1 ==
6389 12:29:28.747189 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6390 12:29:28.750428 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6391 12:29:28.750536
6392 12:29:28.750643 [DATLAT]
6393 12:29:28.753769 Freq=400, CH0 RK0
6394 12:29:28.753848
6395 12:29:28.753949 DATLAT Default: 0xf
6396 12:29:28.757082 0, 0xFFFF, sum = 0
6397 12:29:28.757170 1, 0xFFFF, sum = 0
6398 12:29:28.760416 2, 0xFFFF, sum = 0
6399 12:29:28.760523 3, 0xFFFF, sum = 0
6400 12:29:28.763149 4, 0xFFFF, sum = 0
6401 12:29:28.763258 5, 0xFFFF, sum = 0
6402 12:29:28.767050 6, 0xFFFF, sum = 0
6403 12:29:28.767173 7, 0xFFFF, sum = 0
6404 12:29:28.770284 8, 0xFFFF, sum = 0
6405 12:29:28.770392 9, 0xFFFF, sum = 0
6406 12:29:28.773581 10, 0xFFFF, sum = 0
6407 12:29:28.776823 11, 0xFFFF, sum = 0
6408 12:29:28.776903 12, 0xFFFF, sum = 0
6409 12:29:28.780151 13, 0x0, sum = 1
6410 12:29:28.780233 14, 0x0, sum = 2
6411 12:29:28.780299 15, 0x0, sum = 3
6412 12:29:28.783272 16, 0x0, sum = 4
6413 12:29:28.783412 best_step = 14
6414 12:29:28.783486
6415 12:29:28.786625 ==
6416 12:29:28.786731 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 12:29:28.793467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:29:28.793554 ==
6419 12:29:28.793623 RX Vref Scan: 1
6420 12:29:28.793691
6421 12:29:28.796673 RX Vref 0 -> 0, step: 1
6422 12:29:28.796751
6423 12:29:28.799937 RX Delay -343 -> 252, step: 8
6424 12:29:28.800012
6425 12:29:28.803106 Set Vref, RX VrefLevel [Byte0]: 53
6426 12:29:28.806193 [Byte1]: 51
6427 12:29:28.810035
6428 12:29:28.810115 Final RX Vref Byte 0 = 53 to rank0
6429 12:29:28.813413 Final RX Vref Byte 1 = 51 to rank0
6430 12:29:28.817162 Final RX Vref Byte 0 = 53 to rank1
6431 12:29:28.820316 Final RX Vref Byte 1 = 51 to rank1==
6432 12:29:28.823627 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 12:29:28.830191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 12:29:28.830307 ==
6435 12:29:28.830416 DQS Delay:
6436 12:29:28.830482 DQS0 = 44, DQS1 = 56
6437 12:29:28.833421 DQM Delay:
6438 12:29:28.833537 DQM0 = 11, DQM1 = 11
6439 12:29:28.836739 DQ Delay:
6440 12:29:28.840114 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6441 12:29:28.840234 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6442 12:29:28.843541 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6443 12:29:28.846929 DQ12 =20, DQ13 =12, DQ14 =20, DQ15 =20
6444 12:29:28.847031
6445 12:29:28.847137
6446 12:29:28.856762 [DQSOSCAuto] RK0, (LSB)MR18= 0x804e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6447 12:29:28.860035 CH0 RK0: MR19=C0C, MR18=804E
6448 12:29:28.866570 CH0_RK0: MR19=0xC0C, MR18=0x804E, DQSOSC=393, MR23=63, INC=382, DEC=254
6449 12:29:28.866679 ==
6450 12:29:28.869983 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 12:29:28.873123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 12:29:28.873209 ==
6453 12:29:28.876487 [Gating] SW mode calibration
6454 12:29:28.883498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6455 12:29:28.890160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6456 12:29:28.893349 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6457 12:29:28.896880 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 12:29:28.899792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 12:29:28.906691 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 12:29:28.909924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 12:29:28.913356 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 12:29:28.919699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 12:29:28.922882 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 12:29:28.926044 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 12:29:28.929357 Total UI for P1: 0, mck2ui 16
6466 12:29:28.933258 best dqsien dly found for B0: ( 0, 14, 24)
6467 12:29:28.935914 Total UI for P1: 0, mck2ui 16
6468 12:29:28.939343 best dqsien dly found for B1: ( 0, 14, 24)
6469 12:29:28.942638 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6470 12:29:28.949208 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6471 12:29:28.949301
6472 12:29:28.952488 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6473 12:29:28.955929 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 12:29:28.959773 [Gating] SW calibration Done
6475 12:29:28.959897 ==
6476 12:29:28.962977 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 12:29:28.966262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 12:29:28.966375 ==
6479 12:29:28.966446 RX Vref Scan: 0
6480 12:29:28.969487
6481 12:29:28.969571 RX Vref 0 -> 0, step: 1
6482 12:29:28.969638
6483 12:29:28.972809 RX Delay -410 -> 252, step: 16
6484 12:29:28.976234 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6485 12:29:28.982581 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6486 12:29:28.985716 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6487 12:29:28.989031 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6488 12:29:28.992291 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6489 12:29:28.998879 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6490 12:29:29.002735 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6491 12:29:29.005889 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6492 12:29:29.009239 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6493 12:29:29.015620 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6494 12:29:29.018921 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6495 12:29:29.022026 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6496 12:29:29.028956 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6497 12:29:29.032172 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6498 12:29:29.035333 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6499 12:29:29.038743 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6500 12:29:29.038851 ==
6501 12:29:29.041978 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 12:29:29.048639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 12:29:29.048759 ==
6504 12:29:29.048856 DQS Delay:
6505 12:29:29.051899 DQS0 = 43, DQS1 = 51
6506 12:29:29.052006 DQM Delay:
6507 12:29:29.055123 DQM0 = 12, DQM1 = 10
6508 12:29:29.055223 DQ Delay:
6509 12:29:29.058985 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =8
6510 12:29:29.062379 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6511 12:29:29.062461 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6512 12:29:29.065638 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6513 12:29:29.068860
6514 12:29:29.068970
6515 12:29:29.069064 ==
6516 12:29:29.072014 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 12:29:29.075270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 12:29:29.075384 ==
6519 12:29:29.075454
6520 12:29:29.075517
6521 12:29:29.078581 TX Vref Scan disable
6522 12:29:29.078654 == TX Byte 0 ==
6523 12:29:29.081800 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6524 12:29:29.088417 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6525 12:29:29.088535 == TX Byte 1 ==
6526 12:29:29.091701 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6527 12:29:29.098699 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6528 12:29:29.098814 ==
6529 12:29:29.101988 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 12:29:29.105314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 12:29:29.105421 ==
6532 12:29:29.105513
6533 12:29:29.105610
6534 12:29:29.108500 TX Vref Scan disable
6535 12:29:29.108574 == TX Byte 0 ==
6536 12:29:29.114963 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6537 12:29:29.118792 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6538 12:29:29.118905 == TX Byte 1 ==
6539 12:29:29.125296 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6540 12:29:29.128667 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6541 12:29:29.128772
6542 12:29:29.128843 [DATLAT]
6543 12:29:29.131780 Freq=400, CH0 RK1
6544 12:29:29.131862
6545 12:29:29.131946 DATLAT Default: 0xe
6546 12:29:29.135091 0, 0xFFFF, sum = 0
6547 12:29:29.135230 1, 0xFFFF, sum = 0
6548 12:29:29.138282 2, 0xFFFF, sum = 0
6549 12:29:29.138375 3, 0xFFFF, sum = 0
6550 12:29:29.141698 4, 0xFFFF, sum = 0
6551 12:29:29.141809 5, 0xFFFF, sum = 0
6552 12:29:29.144982 6, 0xFFFF, sum = 0
6553 12:29:29.145062 7, 0xFFFF, sum = 0
6554 12:29:29.148366 8, 0xFFFF, sum = 0
6555 12:29:29.148477 9, 0xFFFF, sum = 0
6556 12:29:29.151760 10, 0xFFFF, sum = 0
6557 12:29:29.151888 11, 0xFFFF, sum = 0
6558 12:29:29.155081 12, 0xFFFF, sum = 0
6559 12:29:29.155162 13, 0x0, sum = 1
6560 12:29:29.158426 14, 0x0, sum = 2
6561 12:29:29.158543 15, 0x0, sum = 3
6562 12:29:29.161844 16, 0x0, sum = 4
6563 12:29:29.161978 best_step = 14
6564 12:29:29.162075
6565 12:29:29.162190 ==
6566 12:29:29.165292 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 12:29:29.171834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 12:29:29.171927 ==
6569 12:29:29.172021 RX Vref Scan: 0
6570 12:29:29.172091
6571 12:29:29.175058 RX Vref 0 -> 0, step: 1
6572 12:29:29.175171
6573 12:29:29.178316 RX Delay -343 -> 252, step: 8
6574 12:29:29.184922 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6575 12:29:29.188243 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6576 12:29:29.191490 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6577 12:29:29.194606 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6578 12:29:29.201645 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6579 12:29:29.204937 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6580 12:29:29.208269 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6581 12:29:29.211412 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6582 12:29:29.218482 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6583 12:29:29.221690 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6584 12:29:29.224770 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6585 12:29:29.227942 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6586 12:29:29.234959 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6587 12:29:29.238335 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6588 12:29:29.241526 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6589 12:29:29.244841 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6590 12:29:29.248177 ==
6591 12:29:29.251571 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 12:29:29.254795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 12:29:29.254871 ==
6594 12:29:29.254938 DQS Delay:
6595 12:29:29.257992 DQS0 = 48, DQS1 = 60
6596 12:29:29.258102 DQM Delay:
6597 12:29:29.261314 DQM0 = 13, DQM1 = 14
6598 12:29:29.261419 DQ Delay:
6599 12:29:29.264701 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6600 12:29:29.268048 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6601 12:29:29.271338 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6602 12:29:29.274593 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6603 12:29:29.274667
6604 12:29:29.274733
6605 12:29:29.281056 [DQSOSCAuto] RK1, (LSB)MR18= 0x9a6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6606 12:29:29.284931 CH0 RK1: MR19=C0C, MR18=9A6D
6607 12:29:29.291377 CH0_RK1: MR19=0xC0C, MR18=0x9A6D, DQSOSC=390, MR23=63, INC=388, DEC=258
6608 12:29:29.294649 [RxdqsGatingPostProcess] freq 400
6609 12:29:29.301161 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6610 12:29:29.301266 best DQS0 dly(2T, 0.5T) = (0, 10)
6611 12:29:29.305001 best DQS1 dly(2T, 0.5T) = (0, 10)
6612 12:29:29.308245 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6613 12:29:29.311644 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6614 12:29:29.314840 best DQS0 dly(2T, 0.5T) = (0, 10)
6615 12:29:29.318005 best DQS1 dly(2T, 0.5T) = (0, 10)
6616 12:29:29.321179 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6617 12:29:29.324466 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6618 12:29:29.328252 Pre-setting of DQS Precalculation
6619 12:29:29.331454 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6620 12:29:29.334591 ==
6621 12:29:29.337858 Dram Type= 6, Freq= 0, CH_1, rank 0
6622 12:29:29.341083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 12:29:29.341160 ==
6624 12:29:29.344897 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 12:29:29.351327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6626 12:29:29.354506 [CA 0] Center 36 (8~64) winsize 57
6627 12:29:29.357910 [CA 1] Center 36 (8~64) winsize 57
6628 12:29:29.361235 [CA 2] Center 36 (8~64) winsize 57
6629 12:29:29.364475 [CA 3] Center 36 (8~64) winsize 57
6630 12:29:29.367835 [CA 4] Center 36 (8~64) winsize 57
6631 12:29:29.371283 [CA 5] Center 36 (8~64) winsize 57
6632 12:29:29.371367
6633 12:29:29.374911 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6634 12:29:29.374983
6635 12:29:29.377879 [CATrainingPosCal] consider 1 rank data
6636 12:29:29.381138 u2DelayCellTimex100 = 270/100 ps
6637 12:29:29.384373 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:29:29.387657 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:29:29.390904 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:29:29.394230 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:29:29.400879 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 12:29:29.403997 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:29:29.404084
6644 12:29:29.407831 CA PerBit enable=1, Macro0, CA PI delay=36
6645 12:29:29.407909
6646 12:29:29.411149 [CBTSetCACLKResult] CA Dly = 36
6647 12:29:29.411248 CS Dly: 1 (0~32)
6648 12:29:29.411340 ==
6649 12:29:29.414528 Dram Type= 6, Freq= 0, CH_1, rank 1
6650 12:29:29.417768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 12:29:29.421087 ==
6652 12:29:29.424199 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6653 12:29:29.430719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6654 12:29:29.434058 [CA 0] Center 36 (8~64) winsize 57
6655 12:29:29.437779 [CA 1] Center 36 (8~64) winsize 57
6656 12:29:29.440926 [CA 2] Center 36 (8~64) winsize 57
6657 12:29:29.444189 [CA 3] Center 36 (8~64) winsize 57
6658 12:29:29.447292 [CA 4] Center 36 (8~64) winsize 57
6659 12:29:29.451017 [CA 5] Center 36 (8~64) winsize 57
6660 12:29:29.451131
6661 12:29:29.454330 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6662 12:29:29.454419
6663 12:29:29.457678 [CATrainingPosCal] consider 2 rank data
6664 12:29:29.461074 u2DelayCellTimex100 = 270/100 ps
6665 12:29:29.464295 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:29:29.467652 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:29:29.471089 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:29:29.474426 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:29:29.477576 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:29:29.480955 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:29:29.481038
6672 12:29:29.487403 CA PerBit enable=1, Macro0, CA PI delay=36
6673 12:29:29.487489
6674 12:29:29.487555 [CBTSetCACLKResult] CA Dly = 36
6675 12:29:29.490748 CS Dly: 1 (0~32)
6676 12:29:29.490831
6677 12:29:29.493936 ----->DramcWriteLeveling(PI) begin...
6678 12:29:29.494020 ==
6679 12:29:29.497090 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 12:29:29.500460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 12:29:29.500579 ==
6682 12:29:29.503809 Write leveling (Byte 0): 40 => 8
6683 12:29:29.506948 Write leveling (Byte 1): 40 => 8
6684 12:29:29.510083 DramcWriteLeveling(PI) end<-----
6685 12:29:29.510194
6686 12:29:29.510286 ==
6687 12:29:29.513456 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 12:29:29.516789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 12:29:29.520078 ==
6690 12:29:29.520192 [Gating] SW mode calibration
6691 12:29:29.530415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6692 12:29:29.533726 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6693 12:29:29.536964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6694 12:29:29.543310 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6695 12:29:29.547216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 12:29:29.550353 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 12:29:29.556820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 12:29:29.560222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 12:29:29.563495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 12:29:29.570128 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 12:29:29.573572 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 12:29:29.576891 Total UI for P1: 0, mck2ui 16
6703 12:29:29.580161 best dqsien dly found for B0: ( 0, 14, 24)
6704 12:29:29.583520 Total UI for P1: 0, mck2ui 16
6705 12:29:29.586944 best dqsien dly found for B1: ( 0, 14, 24)
6706 12:29:29.590093 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6707 12:29:29.593214 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6708 12:29:29.593296
6709 12:29:29.597037 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6710 12:29:29.599745 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 12:29:29.603189 [Gating] SW calibration Done
6712 12:29:29.603272 ==
6713 12:29:29.606578 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 12:29:29.609847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 12:29:29.613040 ==
6716 12:29:29.613123 RX Vref Scan: 0
6717 12:29:29.613189
6718 12:29:29.616823 RX Vref 0 -> 0, step: 1
6719 12:29:29.616914
6720 12:29:29.620051 RX Delay -410 -> 252, step: 16
6721 12:29:29.623305 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6722 12:29:29.626602 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6723 12:29:29.629889 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6724 12:29:29.636306 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6725 12:29:29.639610 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6726 12:29:29.642767 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6727 12:29:29.646658 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6728 12:29:29.653084 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6729 12:29:29.656379 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6730 12:29:29.659578 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6731 12:29:29.662896 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6732 12:29:29.669455 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6733 12:29:29.672850 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6734 12:29:29.675992 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6735 12:29:29.682565 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6736 12:29:29.686347 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6737 12:29:29.686454 ==
6738 12:29:29.689643 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 12:29:29.693016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 12:29:29.693121 ==
6741 12:29:29.696334 DQS Delay:
6742 12:29:29.696439 DQS0 = 51, DQS1 = 59
6743 12:29:29.696531 DQM Delay:
6744 12:29:29.699670 DQM0 = 19, DQM1 = 17
6745 12:29:29.699741 DQ Delay:
6746 12:29:29.702899 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6747 12:29:29.706148 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6748 12:29:29.709558 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6749 12:29:29.712941 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6750 12:29:29.713042
6751 12:29:29.713140
6752 12:29:29.713231 ==
6753 12:29:29.716168 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 12:29:29.719456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 12:29:29.722619 ==
6756 12:29:29.722692
6757 12:29:29.722755
6758 12:29:29.722815 TX Vref Scan disable
6759 12:29:29.725835 == TX Byte 0 ==
6760 12:29:29.729126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 12:29:29.733004 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 12:29:29.736196 == TX Byte 1 ==
6763 12:29:29.739248 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 12:29:29.742574 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 12:29:29.742653 ==
6766 12:29:29.745900 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 12:29:29.752361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 12:29:29.752469 ==
6769 12:29:29.752550
6770 12:29:29.752619
6771 12:29:29.752703 TX Vref Scan disable
6772 12:29:29.756040 == TX Byte 0 ==
6773 12:29:29.759190 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 12:29:29.762358 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 12:29:29.765725 == TX Byte 1 ==
6776 12:29:29.769068 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 12:29:29.772292 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 12:29:29.772403
6779 12:29:29.775674 [DATLAT]
6780 12:29:29.775749 Freq=400, CH1 RK0
6781 12:29:29.775813
6782 12:29:29.778972 DATLAT Default: 0xf
6783 12:29:29.779050 0, 0xFFFF, sum = 0
6784 12:29:29.782308 1, 0xFFFF, sum = 0
6785 12:29:29.782388 2, 0xFFFF, sum = 0
6786 12:29:29.785601 3, 0xFFFF, sum = 0
6787 12:29:29.785683 4, 0xFFFF, sum = 0
6788 12:29:29.789004 5, 0xFFFF, sum = 0
6789 12:29:29.789081 6, 0xFFFF, sum = 0
6790 12:29:29.792352 7, 0xFFFF, sum = 0
6791 12:29:29.792431 8, 0xFFFF, sum = 0
6792 12:29:29.795689 9, 0xFFFF, sum = 0
6793 12:29:29.795772 10, 0xFFFF, sum = 0
6794 12:29:29.798792 11, 0xFFFF, sum = 0
6795 12:29:29.802076 12, 0xFFFF, sum = 0
6796 12:29:29.802178 13, 0x0, sum = 1
6797 12:29:29.805293 14, 0x0, sum = 2
6798 12:29:29.805366 15, 0x0, sum = 3
6799 12:29:29.805429 16, 0x0, sum = 4
6800 12:29:29.808353 best_step = 14
6801 12:29:29.808424
6802 12:29:29.808484 ==
6803 12:29:29.811713 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 12:29:29.815614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:29:29.815690 ==
6806 12:29:29.818866 RX Vref Scan: 1
6807 12:29:29.818936
6808 12:29:29.818997 RX Vref 0 -> 0, step: 1
6809 12:29:29.822063
6810 12:29:29.822137 RX Delay -359 -> 252, step: 8
6811 12:29:29.822198
6812 12:29:29.825418 Set Vref, RX VrefLevel [Byte0]: 58
6813 12:29:29.828592 [Byte1]: 49
6814 12:29:29.833774
6815 12:29:29.833849 Final RX Vref Byte 0 = 58 to rank0
6816 12:29:29.836981 Final RX Vref Byte 1 = 49 to rank0
6817 12:29:29.840394 Final RX Vref Byte 0 = 58 to rank1
6818 12:29:29.844124 Final RX Vref Byte 1 = 49 to rank1==
6819 12:29:29.847314 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 12:29:29.853853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 12:29:29.853936 ==
6822 12:29:29.854002 DQS Delay:
6823 12:29:29.857076 DQS0 = 48, DQS1 = 60
6824 12:29:29.857151 DQM Delay:
6825 12:29:29.857213 DQM0 = 12, DQM1 = 12
6826 12:29:29.860159 DQ Delay:
6827 12:29:29.864055 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6828 12:29:29.864129 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6829 12:29:29.867308 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6830 12:29:29.870484 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6831 12:29:29.870564
6832 12:29:29.873850
6833 12:29:29.880602 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6834 12:29:29.883961 CH1 RK0: MR19=C0C, MR18=8B32
6835 12:29:29.890585 CH1_RK0: MR19=0xC0C, MR18=0x8B32, DQSOSC=392, MR23=63, INC=384, DEC=256
6836 12:29:29.890702 ==
6837 12:29:29.894012 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 12:29:29.897190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 12:29:29.897302 ==
6840 12:29:29.900417 [Gating] SW mode calibration
6841 12:29:29.906977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6842 12:29:29.913422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6843 12:29:29.916772 0 11 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
6844 12:29:29.920182 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6845 12:29:29.926791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 12:29:29.930170 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 12:29:29.933386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 12:29:29.939888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 12:29:29.943299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 12:29:29.946418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 12:29:29.953376 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 12:29:29.953461 Total UI for P1: 0, mck2ui 16
6853 12:29:29.956617 best dqsien dly found for B0: ( 0, 14, 24)
6854 12:29:29.960026 Total UI for P1: 0, mck2ui 16
6855 12:29:29.963151 best dqsien dly found for B1: ( 0, 14, 24)
6856 12:29:29.969596 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6857 12:29:29.972818 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6858 12:29:29.972919
6859 12:29:29.976627 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6860 12:29:29.979996 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 12:29:29.983194 [Gating] SW calibration Done
6862 12:29:29.983295 ==
6863 12:29:29.986449 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 12:29:29.989795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 12:29:29.989895 ==
6866 12:29:29.993219 RX Vref Scan: 0
6867 12:29:29.993316
6868 12:29:29.993414 RX Vref 0 -> 0, step: 1
6869 12:29:29.993502
6870 12:29:29.996474 RX Delay -410 -> 252, step: 16
6871 12:29:29.999730 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6872 12:29:30.006327 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6873 12:29:30.009611 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6874 12:29:30.012895 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6875 12:29:30.016103 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6876 12:29:30.022575 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6877 12:29:30.025953 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6878 12:29:30.029814 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6879 12:29:30.033029 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6880 12:29:30.039822 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6881 12:29:30.042990 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6882 12:29:30.046305 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6883 12:29:30.052625 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6884 12:29:30.055588 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6885 12:29:30.059524 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6886 12:29:30.062794 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6887 12:29:30.062877 ==
6888 12:29:30.066117 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 12:29:30.072364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 12:29:30.072466 ==
6891 12:29:30.072543 DQS Delay:
6892 12:29:30.075623 DQS0 = 43, DQS1 = 59
6893 12:29:30.075717 DQM Delay:
6894 12:29:30.079490 DQM0 = 10, DQM1 = 17
6895 12:29:30.079566 DQ Delay:
6896 12:29:30.082770 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6897 12:29:30.086142 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6898 12:29:30.086230 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6899 12:29:30.089439 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6900 12:29:30.092807
6901 12:29:30.092912
6902 12:29:30.093005 ==
6903 12:29:30.095443 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 12:29:30.098754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 12:29:30.098835 ==
6906 12:29:30.098899
6907 12:29:30.098958
6908 12:29:30.102070 TX Vref Scan disable
6909 12:29:30.102165 == TX Byte 0 ==
6910 12:29:30.105375 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6911 12:29:30.112578 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6912 12:29:30.112656 == TX Byte 1 ==
6913 12:29:30.115903 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6914 12:29:30.122437 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6915 12:29:30.122550 ==
6916 12:29:30.125111 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 12:29:30.129071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 12:29:30.129153 ==
6919 12:29:30.129219
6920 12:29:30.129284
6921 12:29:30.131799 TX Vref Scan disable
6922 12:29:30.131870 == TX Byte 0 ==
6923 12:29:30.138669 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6924 12:29:30.141853 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6925 12:29:30.141957 == TX Byte 1 ==
6926 12:29:30.148418 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6927 12:29:30.151806 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6928 12:29:30.151891
6929 12:29:30.151957 [DATLAT]
6930 12:29:30.155005 Freq=400, CH1 RK1
6931 12:29:30.155093
6932 12:29:30.155189 DATLAT Default: 0xe
6933 12:29:30.158700 0, 0xFFFF, sum = 0
6934 12:29:30.158785 1, 0xFFFF, sum = 0
6935 12:29:30.161824 2, 0xFFFF, sum = 0
6936 12:29:30.161926 3, 0xFFFF, sum = 0
6937 12:29:30.165114 4, 0xFFFF, sum = 0
6938 12:29:30.168524 5, 0xFFFF, sum = 0
6939 12:29:30.168599 6, 0xFFFF, sum = 0
6940 12:29:30.171788 7, 0xFFFF, sum = 0
6941 12:29:30.171862 8, 0xFFFF, sum = 0
6942 12:29:30.174990 9, 0xFFFF, sum = 0
6943 12:29:30.175093 10, 0xFFFF, sum = 0
6944 12:29:30.178137 11, 0xFFFF, sum = 0
6945 12:29:30.178244 12, 0xFFFF, sum = 0
6946 12:29:30.181418 13, 0x0, sum = 1
6947 12:29:30.181521 14, 0x0, sum = 2
6948 12:29:30.184733 15, 0x0, sum = 3
6949 12:29:30.184848 16, 0x0, sum = 4
6950 12:29:30.188120 best_step = 14
6951 12:29:30.188217
6952 12:29:30.188286 ==
6953 12:29:30.191450 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 12:29:30.194714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 12:29:30.194795 ==
6956 12:29:30.194860 RX Vref Scan: 0
6957 12:29:30.194921
6958 12:29:30.198031 RX Vref 0 -> 0, step: 1
6959 12:29:30.198109
6960 12:29:30.201402 RX Delay -359 -> 252, step: 8
6961 12:29:30.208771 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6962 12:29:30.212107 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6963 12:29:30.215461 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6964 12:29:30.218806 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6965 12:29:30.225384 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6966 12:29:30.229216 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6967 12:29:30.232459 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6968 12:29:30.235775 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6969 12:29:30.242288 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6970 12:29:30.245665 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6971 12:29:30.248823 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6972 12:29:30.252180 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6973 12:29:30.258695 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6974 12:29:30.262437 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6975 12:29:30.265623 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6976 12:29:30.272220 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6977 12:29:30.272330 ==
6978 12:29:30.275473 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 12:29:30.278738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 12:29:30.278843 ==
6981 12:29:30.278941 DQS Delay:
6982 12:29:30.282000 DQS0 = 52, DQS1 = 60
6983 12:29:30.282102 DQM Delay:
6984 12:29:30.285205 DQM0 = 13, DQM1 = 13
6985 12:29:30.285313 DQ Delay:
6986 12:29:30.288994 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6987 12:29:30.291671 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6988 12:29:30.295052 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6989 12:29:30.298830 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6990 12:29:30.298903
6991 12:29:30.298965
6992 12:29:30.305383 [DQSOSCAuto] RK1, (LSB)MR18= 0x7084, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6993 12:29:30.308787 CH1 RK1: MR19=C0C, MR18=7084
6994 12:29:30.315403 CH1_RK1: MR19=0xC0C, MR18=0x7084, DQSOSC=393, MR23=63, INC=382, DEC=254
6995 12:29:30.318579 [RxdqsGatingPostProcess] freq 400
6996 12:29:30.325188 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6997 12:29:30.328340 best DQS0 dly(2T, 0.5T) = (0, 10)
6998 12:29:30.328416 best DQS1 dly(2T, 0.5T) = (0, 10)
6999 12:29:30.331640 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7000 12:29:30.334894 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7001 12:29:30.338258 best DQS0 dly(2T, 0.5T) = (0, 10)
7002 12:29:30.341560 best DQS1 dly(2T, 0.5T) = (0, 10)
7003 12:29:30.344880 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7004 12:29:30.348767 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7005 12:29:30.351888 Pre-setting of DQS Precalculation
7006 12:29:30.358443 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7007 12:29:30.365169 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7008 12:29:30.371344 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7009 12:29:30.371439
7010 12:29:30.371505
7011 12:29:30.374610 [Calibration Summary] 800 Mbps
7012 12:29:30.374693 CH 0, Rank 0
7013 12:29:30.377910 SW Impedance : PASS
7014 12:29:30.381211 DUTY Scan : NO K
7015 12:29:30.381313 ZQ Calibration : PASS
7016 12:29:30.385106 Jitter Meter : NO K
7017 12:29:30.388380 CBT Training : PASS
7018 12:29:30.388465 Write leveling : PASS
7019 12:29:30.391648 RX DQS gating : PASS
7020 12:29:30.391732 RX DQ/DQS(RDDQC) : PASS
7021 12:29:30.394972 TX DQ/DQS : PASS
7022 12:29:30.398212 RX DATLAT : PASS
7023 12:29:30.398296 RX DQ/DQS(Engine): PASS
7024 12:29:30.401520 TX OE : NO K
7025 12:29:30.401636 All Pass.
7026 12:29:30.401707
7027 12:29:30.404822 CH 0, Rank 1
7028 12:29:30.404895 SW Impedance : PASS
7029 12:29:30.407965 DUTY Scan : NO K
7030 12:29:30.411175 ZQ Calibration : PASS
7031 12:29:30.411290 Jitter Meter : NO K
7032 12:29:30.414509 CBT Training : PASS
7033 12:29:30.417798 Write leveling : NO K
7034 12:29:30.417907 RX DQS gating : PASS
7035 12:29:30.421136 RX DQ/DQS(RDDQC) : PASS
7036 12:29:30.424350 TX DQ/DQS : PASS
7037 12:29:30.424447 RX DATLAT : PASS
7038 12:29:30.427566 RX DQ/DQS(Engine): PASS
7039 12:29:30.430813 TX OE : NO K
7040 12:29:30.430919 All Pass.
7041 12:29:30.431010
7042 12:29:30.431098 CH 1, Rank 0
7043 12:29:30.434049 SW Impedance : PASS
7044 12:29:30.437381 DUTY Scan : NO K
7045 12:29:30.437462 ZQ Calibration : PASS
7046 12:29:30.441278 Jitter Meter : NO K
7047 12:29:30.444582 CBT Training : PASS
7048 12:29:30.444677 Write leveling : PASS
7049 12:29:30.447851 RX DQS gating : PASS
7050 12:29:30.447962 RX DQ/DQS(RDDQC) : PASS
7051 12:29:30.450951 TX DQ/DQS : PASS
7052 12:29:30.454236 RX DATLAT : PASS
7053 12:29:30.454349 RX DQ/DQS(Engine): PASS
7054 12:29:30.457328 TX OE : NO K
7055 12:29:30.457443 All Pass.
7056 12:29:30.457525
7057 12:29:30.460759 CH 1, Rank 1
7058 12:29:30.460873 SW Impedance : PASS
7059 12:29:30.464072 DUTY Scan : NO K
7060 12:29:30.467300 ZQ Calibration : PASS
7061 12:29:30.467440 Jitter Meter : NO K
7062 12:29:30.470675 CBT Training : PASS
7063 12:29:30.473820 Write leveling : NO K
7064 12:29:30.473922 RX DQS gating : PASS
7065 12:29:30.477484 RX DQ/DQS(RDDQC) : PASS
7066 12:29:30.480607 TX DQ/DQS : PASS
7067 12:29:30.480712 RX DATLAT : PASS
7068 12:29:30.484018 RX DQ/DQS(Engine): PASS
7069 12:29:30.487267 TX OE : NO K
7070 12:29:30.487389 All Pass.
7071 12:29:30.487457
7072 12:29:30.487531 DramC Write-DBI off
7073 12:29:30.490373 PER_BANK_REFRESH: Hybrid Mode
7074 12:29:30.493749 TX_TRACKING: ON
7075 12:29:30.500374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7076 12:29:30.503824 [FAST_K] Save calibration result to emmc
7077 12:29:30.510488 dramc_set_vcore_voltage set vcore to 725000
7078 12:29:30.510573 Read voltage for 1600, 0
7079 12:29:30.513850 Vio18 = 0
7080 12:29:30.513934 Vcore = 725000
7081 12:29:30.514001 Vdram = 0
7082 12:29:30.517125 Vddq = 0
7083 12:29:30.517209 Vmddr = 0
7084 12:29:30.520369 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7085 12:29:30.527478 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7086 12:29:30.530801 MEM_TYPE=3, freq_sel=13
7087 12:29:30.534119 sv_algorithm_assistance_LP4_3733
7088 12:29:30.537396 ============ PULL DRAM RESETB DOWN ============
7089 12:29:30.540698 ========== PULL DRAM RESETB DOWN end =========
7090 12:29:30.544035 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7091 12:29:30.547390 ===================================
7092 12:29:30.550765 LPDDR4 DRAM CONFIGURATION
7093 12:29:30.554024 ===================================
7094 12:29:30.557142 EX_ROW_EN[0] = 0x0
7095 12:29:30.557246 EX_ROW_EN[1] = 0x0
7096 12:29:30.560360 LP4Y_EN = 0x0
7097 12:29:30.560432 WORK_FSP = 0x1
7098 12:29:30.563595 WL = 0x5
7099 12:29:30.563679 RL = 0x5
7100 12:29:30.566890 BL = 0x2
7101 12:29:30.567000 RPST = 0x0
7102 12:29:30.570194 RD_PRE = 0x0
7103 12:29:30.570306 WR_PRE = 0x1
7104 12:29:30.573423 WR_PST = 0x1
7105 12:29:30.576807 DBI_WR = 0x0
7106 12:29:30.576884 DBI_RD = 0x0
7107 12:29:30.580532 OTF = 0x1
7108 12:29:30.583770 ===================================
7109 12:29:30.587134 ===================================
7110 12:29:30.587242 ANA top config
7111 12:29:30.590402 ===================================
7112 12:29:30.593588 DLL_ASYNC_EN = 0
7113 12:29:30.596886 ALL_SLAVE_EN = 0
7114 12:29:30.596970 NEW_RANK_MODE = 1
7115 12:29:30.599975 DLL_IDLE_MODE = 1
7116 12:29:30.603129 LP45_APHY_COMB_EN = 1
7117 12:29:30.607197 TX_ODT_DIS = 0
7118 12:29:30.607307 NEW_8X_MODE = 1
7119 12:29:30.610415 ===================================
7120 12:29:30.613685 ===================================
7121 12:29:30.617032 data_rate = 3200
7122 12:29:30.620281 CKR = 1
7123 12:29:30.623449 DQ_P2S_RATIO = 8
7124 12:29:30.626796 ===================================
7125 12:29:30.630114 CA_P2S_RATIO = 8
7126 12:29:30.633592 DQ_CA_OPEN = 0
7127 12:29:30.633703 DQ_SEMI_OPEN = 0
7128 12:29:30.636711 CA_SEMI_OPEN = 0
7129 12:29:30.640047 CA_FULL_RATE = 0
7130 12:29:30.643370 DQ_CKDIV4_EN = 0
7131 12:29:30.646526 CA_CKDIV4_EN = 0
7132 12:29:30.649778 CA_PREDIV_EN = 0
7133 12:29:30.649891 PH8_DLY = 12
7134 12:29:30.653167 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7135 12:29:30.656518 DQ_AAMCK_DIV = 4
7136 12:29:30.659853 CA_AAMCK_DIV = 4
7137 12:29:30.663173 CA_ADMCK_DIV = 4
7138 12:29:30.666272 DQ_TRACK_CA_EN = 0
7139 12:29:30.669451 CA_PICK = 1600
7140 12:29:30.669553 CA_MCKIO = 1600
7141 12:29:30.672820 MCKIO_SEMI = 0
7142 12:29:30.676096 PLL_FREQ = 3068
7143 12:29:30.679465 DQ_UI_PI_RATIO = 32
7144 12:29:30.683126 CA_UI_PI_RATIO = 0
7145 12:29:30.686385 ===================================
7146 12:29:30.689555 ===================================
7147 12:29:30.692774 memory_type:LPDDR4
7148 12:29:30.692881 GP_NUM : 10
7149 12:29:30.696000 SRAM_EN : 1
7150 12:29:30.696101 MD32_EN : 0
7151 12:29:30.699309 ===================================
7152 12:29:30.702734 [ANA_INIT] >>>>>>>>>>>>>>
7153 12:29:30.706406 <<<<<< [CONFIGURE PHASE]: ANA_TX
7154 12:29:30.709645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7155 12:29:30.712942 ===================================
7156 12:29:30.716199 data_rate = 3200,PCW = 0X7600
7157 12:29:30.719462 ===================================
7158 12:29:30.722769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7159 12:29:30.729504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7160 12:29:30.732890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 12:29:30.739414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7162 12:29:30.742812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7163 12:29:30.746087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7164 12:29:30.746188 [ANA_INIT] flow start
7165 12:29:30.749171 [ANA_INIT] PLL >>>>>>>>
7166 12:29:30.752897 [ANA_INIT] PLL <<<<<<<<
7167 12:29:30.753001 [ANA_INIT] MIDPI >>>>>>>>
7168 12:29:30.756163 [ANA_INIT] MIDPI <<<<<<<<
7169 12:29:30.759531 [ANA_INIT] DLL >>>>>>>>
7170 12:29:30.759633 [ANA_INIT] DLL <<<<<<<<
7171 12:29:30.762815 [ANA_INIT] flow end
7172 12:29:30.765952 ============ LP4 DIFF to SE enter ============
7173 12:29:30.772907 ============ LP4 DIFF to SE exit ============
7174 12:29:30.773010 [ANA_INIT] <<<<<<<<<<<<<
7175 12:29:30.776072 [Flow] Enable top DCM control >>>>>
7176 12:29:30.778889 [Flow] Enable top DCM control <<<<<
7177 12:29:30.782143 Enable DLL master slave shuffle
7178 12:29:30.789345 ==============================================================
7179 12:29:30.789460 Gating Mode config
7180 12:29:30.795853 ==============================================================
7181 12:29:30.799046 Config description:
7182 12:29:30.805921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7183 12:29:30.812539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7184 12:29:30.819027 SELPH_MODE 0: By rank 1: By Phase
7185 12:29:30.825380 ==============================================================
7186 12:29:30.825491 GAT_TRACK_EN = 1
7187 12:29:30.828697 RX_GATING_MODE = 2
7188 12:29:30.832033 RX_GATING_TRACK_MODE = 2
7189 12:29:30.835435 SELPH_MODE = 1
7190 12:29:30.838677 PICG_EARLY_EN = 1
7191 12:29:30.841976 VALID_LAT_VALUE = 1
7192 12:29:30.848469 ==============================================================
7193 12:29:30.851801 Enter into Gating configuration >>>>
7194 12:29:30.855117 Exit from Gating configuration <<<<
7195 12:29:30.858410 Enter into DVFS_PRE_config >>>>>
7196 12:29:30.868375 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7197 12:29:30.871620 Exit from DVFS_PRE_config <<<<<
7198 12:29:30.874821 Enter into PICG configuration >>>>
7199 12:29:30.878610 Exit from PICG configuration <<<<
7200 12:29:30.881977 [RX_INPUT] configuration >>>>>
7201 12:29:30.884650 [RX_INPUT] configuration <<<<<
7202 12:29:30.887952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7203 12:29:30.895039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7204 12:29:30.901486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 12:29:30.907840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 12:29:30.911049 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 12:29:30.918196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 12:29:30.921494 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7209 12:29:30.928009 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7210 12:29:30.931385 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7211 12:29:30.934744 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7212 12:29:30.938081 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7213 12:29:30.944405 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 12:29:30.947804 ===================================
7215 12:29:30.951085 LPDDR4 DRAM CONFIGURATION
7216 12:29:30.954430 ===================================
7217 12:29:30.954541 EX_ROW_EN[0] = 0x0
7218 12:29:30.957705 EX_ROW_EN[1] = 0x0
7219 12:29:30.957813 LP4Y_EN = 0x0
7220 12:29:30.960930 WORK_FSP = 0x1
7221 12:29:30.961037 WL = 0x5
7222 12:29:30.964097 RL = 0x5
7223 12:29:30.964206 BL = 0x2
7224 12:29:30.967579 RPST = 0x0
7225 12:29:30.967681 RD_PRE = 0x0
7226 12:29:30.970876 WR_PRE = 0x1
7227 12:29:30.970987 WR_PST = 0x1
7228 12:29:30.974060 DBI_WR = 0x0
7229 12:29:30.974169 DBI_RD = 0x0
7230 12:29:30.977267 OTF = 0x1
7231 12:29:30.980580 ===================================
7232 12:29:30.983854 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7233 12:29:30.987816 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7234 12:29:30.994328 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 12:29:30.997001 ===================================
7236 12:29:30.997111 LPDDR4 DRAM CONFIGURATION
7237 12:29:31.000806 ===================================
7238 12:29:31.004055 EX_ROW_EN[0] = 0x10
7239 12:29:31.007420 EX_ROW_EN[1] = 0x0
7240 12:29:31.007498 LP4Y_EN = 0x0
7241 12:29:31.010670 WORK_FSP = 0x1
7242 12:29:31.010779 WL = 0x5
7243 12:29:31.014275 RL = 0x5
7244 12:29:31.014386 BL = 0x2
7245 12:29:31.017229 RPST = 0x0
7246 12:29:31.017336 RD_PRE = 0x0
7247 12:29:31.020408 WR_PRE = 0x1
7248 12:29:31.020512 WR_PST = 0x1
7249 12:29:31.023652 DBI_WR = 0x0
7250 12:29:31.023766 DBI_RD = 0x0
7251 12:29:31.026974 OTF = 0x1
7252 12:29:31.030225 ===================================
7253 12:29:31.036944 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7254 12:29:31.037058 ==
7255 12:29:31.040348 Dram Type= 6, Freq= 0, CH_0, rank 0
7256 12:29:31.043709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7257 12:29:31.043818 ==
7258 12:29:31.047110 [Duty_Offset_Calibration]
7259 12:29:31.047216 B0:2 B1:-1 CA:1
7260 12:29:31.047323
7261 12:29:31.050482 [DutyScan_Calibration_Flow] k_type=0
7262 12:29:31.060373
7263 12:29:31.060482 ==CLK 0==
7264 12:29:31.063676 Final CLK duty delay cell = -4
7265 12:29:31.066813 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7266 12:29:31.070174 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7267 12:29:31.073432 [-4] AVG Duty = 4922%(X100)
7268 12:29:31.073549
7269 12:29:31.076803 CH0 CLK Duty spec in!! Max-Min= 156%
7270 12:29:31.080587 [DutyScan_Calibration_Flow] ====Done====
7271 12:29:31.080693
7272 12:29:31.083815 [DutyScan_Calibration_Flow] k_type=1
7273 12:29:31.100038
7274 12:29:31.100160 ==DQS 0 ==
7275 12:29:31.103291 Final DQS duty delay cell = 0
7276 12:29:31.106649 [0] MAX Duty = 5125%(X100), DQS PI = 56
7277 12:29:31.109912 [0] MIN Duty = 5000%(X100), DQS PI = 14
7278 12:29:31.113155 [0] AVG Duty = 5062%(X100)
7279 12:29:31.113259
7280 12:29:31.113352 ==DQS 1 ==
7281 12:29:31.116266 Final DQS duty delay cell = -4
7282 12:29:31.119497 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7283 12:29:31.122704 [-4] MIN Duty = 5000%(X100), DQS PI = 24
7284 12:29:31.126452 [-4] AVG Duty = 5046%(X100)
7285 12:29:31.126526
7286 12:29:31.129629 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7287 12:29:31.129727
7288 12:29:31.132790 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7289 12:29:31.136165 [DutyScan_Calibration_Flow] ====Done====
7290 12:29:31.136266
7291 12:29:31.139463 [DutyScan_Calibration_Flow] k_type=3
7292 12:29:31.157475
7293 12:29:31.157605 ==DQM 0 ==
7294 12:29:31.160746 Final DQM duty delay cell = 0
7295 12:29:31.164099 [0] MAX Duty = 5000%(X100), DQS PI = 20
7296 12:29:31.167373 [0] MIN Duty = 4875%(X100), DQS PI = 4
7297 12:29:31.167447 [0] AVG Duty = 4937%(X100)
7298 12:29:31.170625
7299 12:29:31.170728 ==DQM 1 ==
7300 12:29:31.173988 Final DQM duty delay cell = 0
7301 12:29:31.176635 [0] MAX Duty = 5187%(X100), DQS PI = 56
7302 12:29:31.180546 [0] MIN Duty = 4969%(X100), DQS PI = 18
7303 12:29:31.183890 [0] AVG Duty = 5078%(X100)
7304 12:29:31.183990
7305 12:29:31.187022 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7306 12:29:31.187125
7307 12:29:31.190294 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7308 12:29:31.193604 [DutyScan_Calibration_Flow] ====Done====
7309 12:29:31.193703
7310 12:29:31.196708 [DutyScan_Calibration_Flow] k_type=2
7311 12:29:31.212981
7312 12:29:31.213085 ==DQ 0 ==
7313 12:29:31.216893 Final DQ duty delay cell = -4
7314 12:29:31.220167 [-4] MAX Duty = 5000%(X100), DQS PI = 40
7315 12:29:31.223455 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7316 12:29:31.226547 [-4] AVG Duty = 4922%(X100)
7317 12:29:31.226618
7318 12:29:31.226684 ==DQ 1 ==
7319 12:29:31.229809 Final DQ duty delay cell = 0
7320 12:29:31.233047 [0] MAX Duty = 5031%(X100), DQS PI = 30
7321 12:29:31.236900 [0] MIN Duty = 4907%(X100), DQS PI = 18
7322 12:29:31.240269 [0] AVG Duty = 4969%(X100)
7323 12:29:31.240376
7324 12:29:31.243415 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7325 12:29:31.243521
7326 12:29:31.246783 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7327 12:29:31.250153 [DutyScan_Calibration_Flow] ====Done====
7328 12:29:31.250259 ==
7329 12:29:31.253383 Dram Type= 6, Freq= 0, CH_1, rank 0
7330 12:29:31.256784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7331 12:29:31.256888 ==
7332 12:29:31.260045 [Duty_Offset_Calibration]
7333 12:29:31.260146 B0:1 B1:1 CA:2
7334 12:29:31.260241
7335 12:29:31.263272 [DutyScan_Calibration_Flow] k_type=0
7336 12:29:31.273779
7337 12:29:31.273896 ==CLK 0==
7338 12:29:31.277011 Final CLK duty delay cell = 0
7339 12:29:31.280345 [0] MAX Duty = 5156%(X100), DQS PI = 58
7340 12:29:31.283692 [0] MIN Duty = 4969%(X100), DQS PI = 6
7341 12:29:31.283793 [0] AVG Duty = 5062%(X100)
7342 12:29:31.286896
7343 12:29:31.290629 CH1 CLK Duty spec in!! Max-Min= 187%
7344 12:29:31.293970 [DutyScan_Calibration_Flow] ====Done====
7345 12:29:31.294072
7346 12:29:31.297029 [DutyScan_Calibration_Flow] k_type=1
7347 12:29:31.313101
7348 12:29:31.313206 ==DQS 0 ==
7349 12:29:31.316858 Final DQS duty delay cell = 0
7350 12:29:31.320082 [0] MAX Duty = 5000%(X100), DQS PI = 50
7351 12:29:31.323382 [0] MIN Duty = 4875%(X100), DQS PI = 0
7352 12:29:31.326750 [0] AVG Duty = 4937%(X100)
7353 12:29:31.326851
7354 12:29:31.326942 ==DQS 1 ==
7355 12:29:31.329977 Final DQS duty delay cell = 0
7356 12:29:31.333032 [0] MAX Duty = 5093%(X100), DQS PI = 26
7357 12:29:31.336448 [0] MIN Duty = 4907%(X100), DQS PI = 60
7358 12:29:31.339579 [0] AVG Duty = 5000%(X100)
7359 12:29:31.339679
7360 12:29:31.342845 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7361 12:29:31.342943
7362 12:29:31.346191 CH1 DQS 1 Duty spec in!! Max-Min= 186%
7363 12:29:31.349515 [DutyScan_Calibration_Flow] ====Done====
7364 12:29:31.349614
7365 12:29:31.352767 [DutyScan_Calibration_Flow] k_type=3
7366 12:29:31.370632
7367 12:29:31.370745 ==DQM 0 ==
7368 12:29:31.373190 Final DQM duty delay cell = 0
7369 12:29:31.376967 [0] MAX Duty = 5124%(X100), DQS PI = 52
7370 12:29:31.380276 [0] MIN Duty = 4876%(X100), DQS PI = 18
7371 12:29:31.383427 [0] AVG Duty = 5000%(X100)
7372 12:29:31.383502
7373 12:29:31.383569 ==DQM 1 ==
7374 12:29:31.386875 Final DQM duty delay cell = 0
7375 12:29:31.390136 [0] MAX Duty = 5187%(X100), DQS PI = 28
7376 12:29:31.393342 [0] MIN Duty = 4875%(X100), DQS PI = 52
7377 12:29:31.396632 [0] AVG Duty = 5031%(X100)
7378 12:29:31.396739
7379 12:29:31.399976 CH1 DQM 0 Duty spec in!! Max-Min= 248%
7380 12:29:31.400094
7381 12:29:31.402994 CH1 DQM 1 Duty spec in!! Max-Min= 312%
7382 12:29:31.406265 [DutyScan_Calibration_Flow] ====Done====
7383 12:29:31.406380
7384 12:29:31.409478 [DutyScan_Calibration_Flow] k_type=2
7385 12:29:31.427118
7386 12:29:31.427230 ==DQ 0 ==
7387 12:29:31.430314 Final DQ duty delay cell = 0
7388 12:29:31.433630 [0] MAX Duty = 5125%(X100), DQS PI = 52
7389 12:29:31.436833 [0] MIN Duty = 4969%(X100), DQS PI = 0
7390 12:29:31.436915 [0] AVG Duty = 5047%(X100)
7391 12:29:31.440065
7392 12:29:31.440161 ==DQ 1 ==
7393 12:29:31.444014 Final DQ duty delay cell = 0
7394 12:29:31.447292 [0] MAX Duty = 5124%(X100), DQS PI = 10
7395 12:29:31.449992 [0] MIN Duty = 5031%(X100), DQS PI = 0
7396 12:29:31.450081 [0] AVG Duty = 5077%(X100)
7397 12:29:31.450152
7398 12:29:31.453881 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7399 12:29:31.457216
7400 12:29:31.460557 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7401 12:29:31.463805 [DutyScan_Calibration_Flow] ====Done====
7402 12:29:31.467184 nWR fixed to 30
7403 12:29:31.467307 [ModeRegInit_LP4] CH0 RK0
7404 12:29:31.470565 [ModeRegInit_LP4] CH0 RK1
7405 12:29:31.473261 [ModeRegInit_LP4] CH1 RK0
7406 12:29:31.476607 [ModeRegInit_LP4] CH1 RK1
7407 12:29:31.476725 match AC timing 5
7408 12:29:31.479965 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7409 12:29:31.487004 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7410 12:29:31.489830 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7411 12:29:31.496298 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7412 12:29:31.500223 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7413 12:29:31.500352 [MiockJmeterHQA]
7414 12:29:31.500449
7415 12:29:31.503444 [DramcMiockJmeter] u1RxGatingPI = 0
7416 12:29:31.506744 0 : 4252, 4027
7417 12:29:31.506855 4 : 4252, 4026
7418 12:29:31.506962 8 : 4365, 4140
7419 12:29:31.510048 12 : 4363, 4137
7420 12:29:31.510129 16 : 4252, 4027
7421 12:29:31.513323 20 : 4252, 4027
7422 12:29:31.513449 24 : 4363, 4140
7423 12:29:31.516637 28 : 4363, 4137
7424 12:29:31.516723 32 : 4258, 4030
7425 12:29:31.519949 36 : 4254, 4029
7426 12:29:31.520030 40 : 4366, 4140
7427 12:29:31.520115 44 : 4255, 4030
7428 12:29:31.523026 48 : 4368, 4140
7429 12:29:31.523137 52 : 4257, 4029
7430 12:29:31.526913 56 : 4252, 4027
7431 12:29:31.526992 60 : 4365, 4139
7432 12:29:31.529626 64 : 4368, 4140
7433 12:29:31.529708 68 : 4253, 4029
7434 12:29:31.532897 72 : 4250, 4027
7435 12:29:31.533007 76 : 4255, 4031
7436 12:29:31.533136 80 : 4250, 4027
7437 12:29:31.536244 84 : 4253, 4029
7438 12:29:31.536327 88 : 4254, 4030
7439 12:29:31.539485 92 : 4250, 4027
7440 12:29:31.539581 96 : 4368, 3354
7441 12:29:31.543303 100 : 4252, 0
7442 12:29:31.543399 104 : 4255, 0
7443 12:29:31.543467 108 : 4252, 0
7444 12:29:31.546566 112 : 4250, 0
7445 12:29:31.546644 116 : 4368, 0
7446 12:29:31.549721 120 : 4255, 0
7447 12:29:31.549798 124 : 4360, 0
7448 12:29:31.549865 128 : 4361, 0
7449 12:29:31.553030 132 : 4363, 0
7450 12:29:31.553116 136 : 4253, 0
7451 12:29:31.556319 140 : 4252, 0
7452 12:29:31.556420 144 : 4365, 0
7453 12:29:31.556496 148 : 4363, 0
7454 12:29:31.559722 152 : 4253, 0
7455 12:29:31.559802 156 : 4250, 0
7456 12:29:31.559874 160 : 4253, 0
7457 12:29:31.563083 164 : 4253, 0
7458 12:29:31.563166 168 : 4368, 0
7459 12:29:31.566416 172 : 4255, 0
7460 12:29:31.566495 176 : 4252, 0
7461 12:29:31.566568 180 : 4360, 0
7462 12:29:31.569727 184 : 4250, 0
7463 12:29:31.569808 188 : 4253, 0
7464 12:29:31.573038 192 : 4249, 0
7465 12:29:31.573123 196 : 4257, 0
7466 12:29:31.573193 200 : 4250, 0
7467 12:29:31.576375 204 : 4249, 0
7468 12:29:31.576467 208 : 4254, 0
7469 12:29:31.579641 212 : 4258, 222
7470 12:29:31.579742 216 : 4250, 3896
7471 12:29:31.582859 220 : 4252, 4029
7472 12:29:31.582948 224 : 4252, 4030
7473 12:29:31.583016 228 : 4252, 4029
7474 12:29:31.586035 232 : 4363, 4137
7475 12:29:31.586127 236 : 4252, 4029
7476 12:29:31.589876 240 : 4360, 4137
7477 12:29:31.589974 244 : 4253, 4029
7478 12:29:31.593087 248 : 4363, 4138
7479 12:29:31.593166 252 : 4252, 4030
7480 12:29:31.596274 256 : 4252, 4029
7481 12:29:31.596367 260 : 4253, 4029
7482 12:29:31.599728 264 : 4257, 4032
7483 12:29:31.599816 268 : 4250, 4027
7484 12:29:31.602799 272 : 4250, 4026
7485 12:29:31.602888 276 : 4255, 4030
7486 12:29:31.602957 280 : 4250, 4027
7487 12:29:31.605968 284 : 4254, 4030
7488 12:29:31.606053 288 : 4361, 4137
7489 12:29:31.609233 292 : 4360, 4137
7490 12:29:31.609326 296 : 4253, 4029
7491 12:29:31.612956 300 : 4250, 4027
7492 12:29:31.613068 304 : 4254, 4030
7493 12:29:31.616144 308 : 4253, 4029
7494 12:29:31.616220 312 : 4363, 4140
7495 12:29:31.619337 316 : 4255, 4029
7496 12:29:31.619439 320 : 4363, 4140
7497 12:29:31.622736 324 : 4361, 4137
7498 12:29:31.622844 328 : 4250, 4026
7499 12:29:31.625913 332 : 4253, 2532
7500 12:29:31.626013 336 : 4250, 39
7501 12:29:31.626105
7502 12:29:31.629139 MIOCK jitter meter ch=0
7503 12:29:31.629230
7504 12:29:31.632531 1T = (336-100) = 236 dly cells
7505 12:29:31.635747 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7506 12:29:31.635826 ==
7507 12:29:31.639142 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 12:29:31.645770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 12:29:31.645889 ==
7510 12:29:31.648868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 12:29:31.655330 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 12:29:31.658668 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 12:29:31.665605 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 12:29:31.673462 [CA 0] Center 44 (14~75) winsize 62
7515 12:29:31.677251 [CA 1] Center 44 (13~75) winsize 63
7516 12:29:31.679949 [CA 2] Center 40 (11~69) winsize 59
7517 12:29:31.683311 [CA 3] Center 39 (10~69) winsize 60
7518 12:29:31.686630 [CA 4] Center 38 (8~68) winsize 61
7519 12:29:31.690041 [CA 5] Center 37 (7~67) winsize 61
7520 12:29:31.690150
7521 12:29:31.693831 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 12:29:31.693921
7523 12:29:31.697064 [CATrainingPosCal] consider 1 rank data
7524 12:29:31.700413 u2DelayCellTimex100 = 275/100 ps
7525 12:29:31.703824 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7526 12:29:31.710310 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7527 12:29:31.713520 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7528 12:29:31.716726 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7529 12:29:31.720108 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7530 12:29:31.723307 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7531 12:29:31.723395
7532 12:29:31.726667 CA PerBit enable=1, Macro0, CA PI delay=37
7533 12:29:31.726757
7534 12:29:31.729939 [CBTSetCACLKResult] CA Dly = 37
7535 12:29:31.733637 CS Dly: 10 (0~41)
7536 12:29:31.736831 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 12:29:31.740070 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 12:29:31.740145 ==
7539 12:29:31.743378 Dram Type= 6, Freq= 0, CH_0, rank 1
7540 12:29:31.749904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 12:29:31.749994 ==
7542 12:29:31.753211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 12:29:31.756564 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 12:29:31.763132 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 12:29:31.769909 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 12:29:31.777836 [CA 0] Center 43 (13~74) winsize 62
7547 12:29:31.781096 [CA 1] Center 43 (13~74) winsize 62
7548 12:29:31.784445 [CA 2] Center 39 (10~69) winsize 60
7549 12:29:31.787593 [CA 3] Center 38 (9~68) winsize 60
7550 12:29:31.790810 [CA 4] Center 37 (7~67) winsize 61
7551 12:29:31.793937 [CA 5] Center 36 (6~67) winsize 62
7552 12:29:31.794024
7553 12:29:31.797162 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 12:29:31.797246
7555 12:29:31.800349 [CATrainingPosCal] consider 2 rank data
7556 12:29:31.803704 u2DelayCellTimex100 = 275/100 ps
7557 12:29:31.810913 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7558 12:29:31.814068 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7559 12:29:31.817293 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7560 12:29:31.820538 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7561 12:29:31.823712 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7562 12:29:31.826928 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7563 12:29:31.827004
7564 12:29:31.830192 CA PerBit enable=1, Macro0, CA PI delay=37
7565 12:29:31.830282
7566 12:29:31.833563 [CBTSetCACLKResult] CA Dly = 37
7567 12:29:31.837094 CS Dly: 11 (0~44)
7568 12:29:31.840183 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 12:29:31.843404 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 12:29:31.843483
7571 12:29:31.846575 ----->DramcWriteLeveling(PI) begin...
7572 12:29:31.849915 ==
7573 12:29:31.849994 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 12:29:31.856940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 12:29:31.857047 ==
7576 12:29:31.860237 Write leveling (Byte 0): 34 => 34
7577 12:29:31.863369 Write leveling (Byte 1): 28 => 28
7578 12:29:31.866635 DramcWriteLeveling(PI) end<-----
7579 12:29:31.866710
7580 12:29:31.866774 ==
7581 12:29:31.869954 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 12:29:31.873194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 12:29:31.873273 ==
7584 12:29:31.876557 [Gating] SW mode calibration
7585 12:29:31.883135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7586 12:29:31.889861 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7587 12:29:31.893191 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 12:29:31.896583 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 12:29:31.899858 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 12:29:31.906331 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 12:29:31.909558 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7592 12:29:31.912769 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7593 12:29:31.919587 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 12:29:31.922766 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 12:29:31.926531 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 12:29:31.932898 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 12:29:31.936174 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 12:29:31.939946 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7599 12:29:31.946303 1 5 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7600 12:29:31.949566 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7601 12:29:31.952907 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7602 12:29:31.959479 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:29:31.962748 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:29:31.966612 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 12:29:31.972726 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 12:29:31.975980 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 12:29:31.979263 1 6 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7608 12:29:31.986042 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7609 12:29:31.989264 1 6 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7610 12:29:31.992662 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:29:31.999180 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:29:32.002611 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 12:29:32.005833 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 12:29:32.012945 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 12:29:32.016133 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 12:29:32.019476 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 12:29:32.026230 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7618 12:29:32.029499 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:29:32.032061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:29:32.039171 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:29:32.042508 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:29:32.045694 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:29:32.052038 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:29:32.055264 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:29:32.059150 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:29:32.065653 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:29:32.068704 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:29:32.071971 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:29:32.075260 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:29:32.082477 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 12:29:32.085916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 12:29:32.089190 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 12:29:32.092595 Total UI for P1: 0, mck2ui 16
7634 12:29:32.095310 best dqsien dly found for B0: ( 1, 9, 14)
7635 12:29:32.101953 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 12:29:32.105257 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 12:29:32.108465 Total UI for P1: 0, mck2ui 16
7638 12:29:32.111798 best dqsien dly found for B1: ( 1, 9, 22)
7639 12:29:32.115626 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7640 12:29:32.118929 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7641 12:29:32.119005
7642 12:29:32.122360 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7643 12:29:32.128727 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7644 12:29:32.128812 [Gating] SW calibration Done
7645 12:29:32.128879 ==
7646 12:29:32.131980 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 12:29:32.138320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 12:29:32.138398 ==
7649 12:29:32.138468 RX Vref Scan: 0
7650 12:29:32.138532
7651 12:29:32.141593 RX Vref 0 -> 0, step: 1
7652 12:29:32.141690
7653 12:29:32.144859 RX Delay 0 -> 252, step: 8
7654 12:29:32.148205 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7655 12:29:32.152083 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7656 12:29:32.155266 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7657 12:29:32.158319 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7658 12:29:32.164838 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7659 12:29:32.168708 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7660 12:29:32.171969 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7661 12:29:32.175164 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7662 12:29:32.178371 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7663 12:29:32.185126 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7664 12:29:32.188601 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7665 12:29:32.191869 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7666 12:29:32.195223 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7667 12:29:32.198548 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7668 12:29:32.205145 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7669 12:29:32.208523 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7670 12:29:32.208612 ==
7671 12:29:32.211755 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 12:29:32.215050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 12:29:32.215166 ==
7674 12:29:32.218212 DQS Delay:
7675 12:29:32.218328 DQS0 = 0, DQS1 = 0
7676 12:29:32.218432 DQM Delay:
7677 12:29:32.221384 DQM0 = 131, DQM1 = 123
7678 12:29:32.221460 DQ Delay:
7679 12:29:32.224713 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7680 12:29:32.228020 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7681 12:29:32.234591 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7682 12:29:32.238415 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7683 12:29:32.238500
7684 12:29:32.238573
7685 12:29:32.238641 ==
7686 12:29:32.241713 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 12:29:32.244920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 12:29:32.244995 ==
7689 12:29:32.245059
7690 12:29:32.245119
7691 12:29:32.248141 TX Vref Scan disable
7692 12:29:32.248212 == TX Byte 0 ==
7693 12:29:32.255152 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7694 12:29:32.258359 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7695 12:29:32.258460 == TX Byte 1 ==
7696 12:29:32.264756 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7697 12:29:32.268145 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7698 12:29:32.268236 ==
7699 12:29:32.271354 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 12:29:32.274535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 12:29:32.274644 ==
7702 12:29:32.291005
7703 12:29:32.294243 TX Vref early break, caculate TX vref
7704 12:29:32.297407 TX Vref=16, minBit 4, minWin=21, winSum=360
7705 12:29:32.300753 TX Vref=18, minBit 1, minWin=22, winSum=370
7706 12:29:32.303995 TX Vref=20, minBit 1, minWin=23, winSum=384
7707 12:29:32.307392 TX Vref=22, minBit 1, minWin=23, winSum=388
7708 12:29:32.310773 TX Vref=24, minBit 3, minWin=24, winSum=402
7709 12:29:32.317377 TX Vref=26, minBit 7, minWin=24, winSum=415
7710 12:29:32.320608 TX Vref=28, minBit 4, minWin=24, winSum=419
7711 12:29:32.323885 TX Vref=30, minBit 4, minWin=25, winSum=420
7712 12:29:32.327093 TX Vref=32, minBit 0, minWin=24, winSum=410
7713 12:29:32.330292 TX Vref=34, minBit 4, minWin=24, winSum=401
7714 12:29:32.333770 TX Vref=36, minBit 0, minWin=23, winSum=390
7715 12:29:32.340489 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 30
7716 12:29:32.340568
7717 12:29:32.344183 Final TX Range 0 Vref 30
7718 12:29:32.344267
7719 12:29:32.344349 ==
7720 12:29:32.347607 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 12:29:32.350725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 12:29:32.350806 ==
7723 12:29:32.350939
7724 12:29:32.351037
7725 12:29:32.354043 TX Vref Scan disable
7726 12:29:32.360558 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7727 12:29:32.360645 == TX Byte 0 ==
7728 12:29:32.363870 u2DelayCellOfst[0]=14 cells (4 PI)
7729 12:29:32.366941 u2DelayCellOfst[1]=17 cells (5 PI)
7730 12:29:32.370283 u2DelayCellOfst[2]=10 cells (3 PI)
7731 12:29:32.373660 u2DelayCellOfst[3]=10 cells (3 PI)
7732 12:29:32.376899 u2DelayCellOfst[4]=10 cells (3 PI)
7733 12:29:32.380786 u2DelayCellOfst[5]=0 cells (0 PI)
7734 12:29:32.383494 u2DelayCellOfst[6]=17 cells (5 PI)
7735 12:29:32.387263 u2DelayCellOfst[7]=17 cells (5 PI)
7736 12:29:32.390642 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7737 12:29:32.393861 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7738 12:29:32.397162 == TX Byte 1 ==
7739 12:29:32.400471 u2DelayCellOfst[8]=0 cells (0 PI)
7740 12:29:32.403828 u2DelayCellOfst[9]=0 cells (0 PI)
7741 12:29:32.403913 u2DelayCellOfst[10]=7 cells (2 PI)
7742 12:29:32.407125 u2DelayCellOfst[11]=3 cells (1 PI)
7743 12:29:32.410430 u2DelayCellOfst[12]=14 cells (4 PI)
7744 12:29:32.413745 u2DelayCellOfst[13]=14 cells (4 PI)
7745 12:29:32.417136 u2DelayCellOfst[14]=17 cells (5 PI)
7746 12:29:32.420441 u2DelayCellOfst[15]=14 cells (4 PI)
7747 12:29:32.423869 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7748 12:29:32.430246 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7749 12:29:32.430332 DramC Write-DBI on
7750 12:29:32.430434 ==
7751 12:29:32.433450 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 12:29:32.440024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 12:29:32.440142 ==
7754 12:29:32.440243
7755 12:29:32.440338
7756 12:29:32.440419 TX Vref Scan disable
7757 12:29:32.444640 == TX Byte 0 ==
7758 12:29:32.447896 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7759 12:29:32.451028 == TX Byte 1 ==
7760 12:29:32.454323 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7761 12:29:32.457379 DramC Write-DBI off
7762 12:29:32.457465
7763 12:29:32.457533 [DATLAT]
7764 12:29:32.457596 Freq=1600, CH0 RK0
7765 12:29:32.457678
7766 12:29:32.460760 DATLAT Default: 0xf
7767 12:29:32.460855 0, 0xFFFF, sum = 0
7768 12:29:32.464067 1, 0xFFFF, sum = 0
7769 12:29:32.464224 2, 0xFFFF, sum = 0
7770 12:29:32.467489 3, 0xFFFF, sum = 0
7771 12:29:32.471041 4, 0xFFFF, sum = 0
7772 12:29:32.471198 5, 0xFFFF, sum = 0
7773 12:29:32.474441 6, 0xFFFF, sum = 0
7774 12:29:32.474584 7, 0xFFFF, sum = 0
7775 12:29:32.477662 8, 0xFFFF, sum = 0
7776 12:29:32.477788 9, 0xFFFF, sum = 0
7777 12:29:32.480926 10, 0xFFFF, sum = 0
7778 12:29:32.481033 11, 0xFFFF, sum = 0
7779 12:29:32.484098 12, 0xFFFF, sum = 0
7780 12:29:32.484234 13, 0xFFFF, sum = 0
7781 12:29:32.487282 14, 0x0, sum = 1
7782 12:29:32.487439 15, 0x0, sum = 2
7783 12:29:32.490753 16, 0x0, sum = 3
7784 12:29:32.490893 17, 0x0, sum = 4
7785 12:29:32.494099 best_step = 15
7786 12:29:32.494197
7787 12:29:32.494264 ==
7788 12:29:32.497569 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 12:29:32.500275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 12:29:32.500385 ==
7791 12:29:32.503678 RX Vref Scan: 1
7792 12:29:32.503779
7793 12:29:32.503877 Set Vref Range= 24 -> 127
7794 12:29:32.503973
7795 12:29:32.506967 RX Vref 24 -> 127, step: 1
7796 12:29:32.507052
7797 12:29:32.510230 RX Delay 11 -> 252, step: 4
7798 12:29:32.510334
7799 12:29:32.513623 Set Vref, RX VrefLevel [Byte0]: 24
7800 12:29:32.516994 [Byte1]: 24
7801 12:29:32.517114
7802 12:29:32.520268 Set Vref, RX VrefLevel [Byte0]: 25
7803 12:29:32.523724 [Byte1]: 25
7804 12:29:32.527171
7805 12:29:32.527271 Set Vref, RX VrefLevel [Byte0]: 26
7806 12:29:32.530599 [Byte1]: 26
7807 12:29:32.534397
7808 12:29:32.537692 Set Vref, RX VrefLevel [Byte0]: 27
7809 12:29:32.540912 [Byte1]: 27
7810 12:29:32.541003
7811 12:29:32.544084 Set Vref, RX VrefLevel [Byte0]: 28
7812 12:29:32.547369 [Byte1]: 28
7813 12:29:32.547455
7814 12:29:32.550696 Set Vref, RX VrefLevel [Byte0]: 29
7815 12:29:32.554578 [Byte1]: 29
7816 12:29:32.554663
7817 12:29:32.557751 Set Vref, RX VrefLevel [Byte0]: 30
7818 12:29:32.560931 [Byte1]: 30
7819 12:29:32.564770
7820 12:29:32.564855 Set Vref, RX VrefLevel [Byte0]: 31
7821 12:29:32.568094 [Byte1]: 31
7822 12:29:32.572805
7823 12:29:32.572890 Set Vref, RX VrefLevel [Byte0]: 32
7824 12:29:32.576011 [Byte1]: 32
7825 12:29:32.580097
7826 12:29:32.580174 Set Vref, RX VrefLevel [Byte0]: 33
7827 12:29:32.583448 [Byte1]: 33
7828 12:29:32.587842
7829 12:29:32.587916 Set Vref, RX VrefLevel [Byte0]: 34
7830 12:29:32.590980 [Byte1]: 34
7831 12:29:32.595569
7832 12:29:32.595646 Set Vref, RX VrefLevel [Byte0]: 35
7833 12:29:32.598816 [Byte1]: 35
7834 12:29:32.603481
7835 12:29:32.603561 Set Vref, RX VrefLevel [Byte0]: 36
7836 12:29:32.606149 [Byte1]: 36
7837 12:29:32.610777
7838 12:29:32.610876 Set Vref, RX VrefLevel [Byte0]: 37
7839 12:29:32.614129 [Byte1]: 37
7840 12:29:32.618055
7841 12:29:32.618160 Set Vref, RX VrefLevel [Byte0]: 38
7842 12:29:32.621442 [Byte1]: 38
7843 12:29:32.626257
7844 12:29:32.626384 Set Vref, RX VrefLevel [Byte0]: 39
7845 12:29:32.629478 [Byte1]: 39
7846 12:29:32.633545
7847 12:29:32.633687 Set Vref, RX VrefLevel [Byte0]: 40
7848 12:29:32.636790 [Byte1]: 40
7849 12:29:32.641122
7850 12:29:32.641317 Set Vref, RX VrefLevel [Byte0]: 41
7851 12:29:32.644545 [Byte1]: 41
7852 12:29:32.649173
7853 12:29:32.649421 Set Vref, RX VrefLevel [Byte0]: 42
7854 12:29:32.652589 [Byte1]: 42
7855 12:29:32.656614
7856 12:29:32.656906 Set Vref, RX VrefLevel [Byte0]: 43
7857 12:29:32.660479 [Byte1]: 43
7858 12:29:32.664320
7859 12:29:32.664679 Set Vref, RX VrefLevel [Byte0]: 44
7860 12:29:32.670238 [Byte1]: 44
7861 12:29:32.670323
7862 12:29:32.673470 Set Vref, RX VrefLevel [Byte0]: 45
7863 12:29:32.676757 [Byte1]: 45
7864 12:29:32.676841
7865 12:29:32.680496 Set Vref, RX VrefLevel [Byte0]: 46
7866 12:29:32.683773 [Byte1]: 46
7867 12:29:32.687009
7868 12:29:32.687100 Set Vref, RX VrefLevel [Byte0]: 47
7869 12:29:32.690090 [Byte1]: 47
7870 12:29:32.694435
7871 12:29:32.694543 Set Vref, RX VrefLevel [Byte0]: 48
7872 12:29:32.697828 [Byte1]: 48
7873 12:29:32.701770
7874 12:29:32.701907 Set Vref, RX VrefLevel [Byte0]: 49
7875 12:29:32.705640 [Byte1]: 49
7876 12:29:32.709558
7877 12:29:32.709716 Set Vref, RX VrefLevel [Byte0]: 50
7878 12:29:32.712842 [Byte1]: 50
7879 12:29:32.717452
7880 12:29:32.717639 Set Vref, RX VrefLevel [Byte0]: 51
7881 12:29:32.720757 [Byte1]: 51
7882 12:29:32.724820
7883 12:29:32.725078 Set Vref, RX VrefLevel [Byte0]: 52
7884 12:29:32.728123 [Byte1]: 52
7885 12:29:32.732825
7886 12:29:32.733151 Set Vref, RX VrefLevel [Byte0]: 53
7887 12:29:32.736322 [Byte1]: 53
7888 12:29:32.740322
7889 12:29:32.740740 Set Vref, RX VrefLevel [Byte0]: 54
7890 12:29:32.743454 [Byte1]: 54
7891 12:29:32.748089
7892 12:29:32.748508 Set Vref, RX VrefLevel [Byte0]: 55
7893 12:29:32.751258 [Byte1]: 55
7894 12:29:32.755861
7895 12:29:32.756380 Set Vref, RX VrefLevel [Byte0]: 56
7896 12:29:32.759026 [Byte1]: 56
7897 12:29:32.763108
7898 12:29:32.763639 Set Vref, RX VrefLevel [Byte0]: 57
7899 12:29:32.767018 [Byte1]: 57
7900 12:29:32.770853
7901 12:29:32.771517 Set Vref, RX VrefLevel [Byte0]: 58
7902 12:29:32.774044 [Byte1]: 58
7903 12:29:32.778681
7904 12:29:32.779253 Set Vref, RX VrefLevel [Byte0]: 59
7905 12:29:32.781855 [Byte1]: 59
7906 12:29:32.786305
7907 12:29:32.786891 Set Vref, RX VrefLevel [Byte0]: 60
7908 12:29:32.790200 [Byte1]: 60
7909 12:29:32.793594
7910 12:29:32.794016 Set Vref, RX VrefLevel [Byte0]: 61
7911 12:29:32.796758 [Byte1]: 61
7912 12:29:32.801368
7913 12:29:32.801790 Set Vref, RX VrefLevel [Byte0]: 62
7914 12:29:32.804603 [Byte1]: 62
7915 12:29:32.809184
7916 12:29:32.809652 Set Vref, RX VrefLevel [Byte0]: 63
7917 12:29:32.811924 [Byte1]: 63
7918 12:29:32.816503
7919 12:29:32.817076 Set Vref, RX VrefLevel [Byte0]: 64
7920 12:29:32.819685 [Byte1]: 64
7921 12:29:32.824469
7922 12:29:32.824858 Set Vref, RX VrefLevel [Byte0]: 65
7923 12:29:32.827441 [Byte1]: 65
7924 12:29:32.831483
7925 12:29:32.831905 Set Vref, RX VrefLevel [Byte0]: 66
7926 12:29:32.834896 [Byte1]: 66
7927 12:29:32.839490
7928 12:29:32.839910 Set Vref, RX VrefLevel [Byte0]: 67
7929 12:29:32.842814 [Byte1]: 67
7930 12:29:32.846841
7931 12:29:32.847260 Set Vref, RX VrefLevel [Byte0]: 68
7932 12:29:32.850168 [Byte1]: 68
7933 12:29:32.854595
7934 12:29:32.855016 Set Vref, RX VrefLevel [Byte0]: 69
7935 12:29:32.858001 [Byte1]: 69
7936 12:29:32.862636
7937 12:29:32.863054 Set Vref, RX VrefLevel [Byte0]: 70
7938 12:29:32.865863 [Byte1]: 70
7939 12:29:32.869790
7940 12:29:32.870209 Set Vref, RX VrefLevel [Byte0]: 71
7941 12:29:32.872948 [Byte1]: 71
7942 12:29:32.877506
7943 12:29:32.877982 Set Vref, RX VrefLevel [Byte0]: 72
7944 12:29:32.880753 [Byte1]: 72
7945 12:29:32.885327
7946 12:29:32.885748 Set Vref, RX VrefLevel [Byte0]: 73
7947 12:29:32.888459 [Byte1]: 73
7948 12:29:32.893051
7949 12:29:32.893475 Set Vref, RX VrefLevel [Byte0]: 74
7950 12:29:32.896245 [Byte1]: 74
7951 12:29:32.900201
7952 12:29:32.900833 Set Vref, RX VrefLevel [Byte0]: 75
7953 12:29:32.903991 [Byte1]: 75
7954 12:29:32.907813
7955 12:29:32.908412 Set Vref, RX VrefLevel [Byte0]: 76
7956 12:29:32.911048 [Byte1]: 76
7957 12:29:32.915804
7958 12:29:32.916365 Final RX Vref Byte 0 = 61 to rank0
7959 12:29:32.918972 Final RX Vref Byte 1 = 61 to rank0
7960 12:29:32.922406 Final RX Vref Byte 0 = 61 to rank1
7961 12:29:32.925796 Final RX Vref Byte 1 = 61 to rank1==
7962 12:29:32.929149 Dram Type= 6, Freq= 0, CH_0, rank 0
7963 12:29:32.935235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 12:29:32.935837 ==
7965 12:29:32.936321 DQS Delay:
7966 12:29:32.936781 DQS0 = 0, DQS1 = 0
7967 12:29:32.939240 DQM Delay:
7968 12:29:32.939849 DQM0 = 129, DQM1 = 121
7969 12:29:32.942403 DQ Delay:
7970 12:29:32.945151 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =124
7971 12:29:32.948932 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7972 12:29:32.952184 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7973 12:29:32.955432 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7974 12:29:32.955816
7975 12:29:32.956142
7976 12:29:32.956450
7977 12:29:32.958599 [DramC_TX_OE_Calibration] TA2
7978 12:29:32.961781 Original DQ_B0 (3 6) =30, OEN = 27
7979 12:29:32.965179 Original DQ_B1 (3 6) =30, OEN = 27
7980 12:29:32.968401 24, 0x0, End_B0=24 End_B1=24
7981 12:29:32.968800 25, 0x0, End_B0=25 End_B1=25
7982 12:29:32.971772 26, 0x0, End_B0=26 End_B1=26
7983 12:29:32.975574 27, 0x0, End_B0=27 End_B1=27
7984 12:29:32.978693 28, 0x0, End_B0=28 End_B1=28
7985 12:29:32.979265 29, 0x0, End_B0=29 End_B1=29
7986 12:29:32.981881 30, 0x0, End_B0=30 End_B1=30
7987 12:29:32.985188 31, 0x4141, End_B0=30 End_B1=30
7988 12:29:32.988455 Byte0 end_step=30 best_step=27
7989 12:29:32.992231 Byte1 end_step=30 best_step=27
7990 12:29:32.995333 Byte0 TX OE(2T, 0.5T) = (3, 3)
7991 12:29:32.995821 Byte1 TX OE(2T, 0.5T) = (3, 3)
7992 12:29:32.998508
7993 12:29:32.998947
7994 12:29:33.005295 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7995 12:29:33.008471 CH0 RK0: MR19=303, MR18=1509
7996 12:29:33.015534 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7997 12:29:33.016023
7998 12:29:33.018701 ----->DramcWriteLeveling(PI) begin...
7999 12:29:33.019148 ==
8000 12:29:33.022088 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 12:29:33.025576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 12:29:33.026054 ==
8003 12:29:33.028148 Write leveling (Byte 0): 33 => 33
8004 12:29:33.031427 Write leveling (Byte 1): 27 => 27
8005 12:29:33.034868 DramcWriteLeveling(PI) end<-----
8006 12:29:33.035447
8007 12:29:33.035935 ==
8008 12:29:33.038240 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 12:29:33.041575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 12:29:33.042053 ==
8011 12:29:33.044980 [Gating] SW mode calibration
8012 12:29:33.051514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8013 12:29:33.058094 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8014 12:29:33.061904 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 12:29:33.065118 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 12:29:33.071839 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8017 12:29:33.075078 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8018 12:29:33.078229 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8019 12:29:33.085368 1 4 20 | B1->B0 | 2d2c 3434 | 1 1 | (1 1) (1 1)
8020 12:29:33.088619 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 12:29:33.092005 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 12:29:33.098281 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 12:29:33.101560 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8024 12:29:33.104881 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8025 12:29:33.111485 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8026 12:29:33.114459 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8027 12:29:33.118373 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
8028 12:29:33.124775 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8029 12:29:33.128049 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 12:29:33.131824 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 12:29:33.137822 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8032 12:29:33.141125 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8033 12:29:33.144621 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8034 12:29:33.151714 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8035 12:29:33.155023 1 6 20 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
8036 12:29:33.158299 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 12:29:33.164843 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 12:29:33.168057 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 12:29:33.171231 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 12:29:33.174451 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:29:33.181178 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8042 12:29:33.185020 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8043 12:29:33.188128 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 12:29:33.194574 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8045 12:29:33.197840 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 12:29:33.201120 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 12:29:33.207490 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:29:33.210774 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:29:33.214120 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:29:33.221057 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:29:33.224365 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:29:33.227286 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:29:33.233881 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:29:33.237232 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:29:33.240623 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:29:33.247140 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 12:29:33.250415 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8058 12:29:33.253719 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 12:29:33.256888 Total UI for P1: 0, mck2ui 16
8060 12:29:33.260172 best dqsien dly found for B0: ( 1, 9, 10)
8061 12:29:33.266738 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8062 12:29:33.270210 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8063 12:29:33.273380 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 12:29:33.277196 Total UI for P1: 0, mck2ui 16
8065 12:29:33.280526 best dqsien dly found for B1: ( 1, 9, 20)
8066 12:29:33.283889 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8067 12:29:33.287092 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8068 12:29:33.287176
8069 12:29:33.293605 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8070 12:29:33.296712 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8071 12:29:33.300090 [Gating] SW calibration Done
8072 12:29:33.300195 ==
8073 12:29:33.303249 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:29:33.307261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:29:33.307381 ==
8076 12:29:33.307452 RX Vref Scan: 0
8077 12:29:33.307521
8078 12:29:33.310345 RX Vref 0 -> 0, step: 1
8079 12:29:33.310444
8080 12:29:33.313738 RX Delay 0 -> 252, step: 8
8081 12:29:33.317068 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8082 12:29:33.320285 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8083 12:29:33.326612 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8084 12:29:33.329974 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8085 12:29:33.333179 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8086 12:29:33.336600 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8087 12:29:33.339816 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8088 12:29:33.343292 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8089 12:29:33.349899 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8090 12:29:33.353241 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8091 12:29:33.356693 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8092 12:29:33.359820 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8093 12:29:33.366282 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8094 12:29:33.369585 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8095 12:29:33.372869 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8096 12:29:33.376715 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8097 12:29:33.376798 ==
8098 12:29:33.379817 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 12:29:33.386373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 12:29:33.386482 ==
8101 12:29:33.386577 DQS Delay:
8102 12:29:33.386668 DQS0 = 0, DQS1 = 0
8103 12:29:33.389648 DQM Delay:
8104 12:29:33.389731 DQM0 = 131, DQM1 = 124
8105 12:29:33.392846 DQ Delay:
8106 12:29:33.396091 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8107 12:29:33.399996 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8108 12:29:33.402748 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8109 12:29:33.406019 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8110 12:29:33.406120
8111 12:29:33.406211
8112 12:29:33.406304 ==
8113 12:29:33.409911 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 12:29:33.412978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 12:29:33.413087 ==
8116 12:29:33.416135
8117 12:29:33.416214
8118 12:29:33.416277 TX Vref Scan disable
8119 12:29:33.419498 == TX Byte 0 ==
8120 12:29:33.422748 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8121 12:29:33.426017 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8122 12:29:33.429739 == TX Byte 1 ==
8123 12:29:33.433014 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8124 12:29:33.436278 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8125 12:29:33.436384 ==
8126 12:29:33.439385 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 12:29:33.446094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 12:29:33.446170 ==
8129 12:29:33.460005
8130 12:29:33.463201 TX Vref early break, caculate TX vref
8131 12:29:33.466552 TX Vref=16, minBit 8, minWin=22, winSum=372
8132 12:29:33.469813 TX Vref=18, minBit 1, minWin=23, winSum=382
8133 12:29:33.473099 TX Vref=20, minBit 0, minWin=23, winSum=387
8134 12:29:33.476397 TX Vref=22, minBit 1, minWin=24, winSum=399
8135 12:29:33.479722 TX Vref=24, minBit 9, minWin=24, winSum=405
8136 12:29:33.486793 TX Vref=26, minBit 0, minWin=25, winSum=413
8137 12:29:33.490045 TX Vref=28, minBit 0, minWin=25, winSum=418
8138 12:29:33.493576 TX Vref=30, minBit 0, minWin=25, winSum=413
8139 12:29:33.496115 TX Vref=32, minBit 0, minWin=24, winSum=404
8140 12:29:33.499433 TX Vref=34, minBit 0, minWin=24, winSum=400
8141 12:29:33.503334 TX Vref=36, minBit 13, minWin=22, winSum=390
8142 12:29:33.509876 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8143 12:29:33.509959
8144 12:29:33.513210 Final TX Range 0 Vref 28
8145 12:29:33.513292
8146 12:29:33.513356 ==
8147 12:29:33.516392 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 12:29:33.519543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 12:29:33.519625 ==
8150 12:29:33.519691
8151 12:29:33.519750
8152 12:29:33.522775 TX Vref Scan disable
8153 12:29:33.529598 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8154 12:29:33.529679 == TX Byte 0 ==
8155 12:29:33.532788 u2DelayCellOfst[0]=14 cells (4 PI)
8156 12:29:33.536659 u2DelayCellOfst[1]=17 cells (5 PI)
8157 12:29:33.539818 u2DelayCellOfst[2]=10 cells (3 PI)
8158 12:29:33.543020 u2DelayCellOfst[3]=10 cells (3 PI)
8159 12:29:33.546186 u2DelayCellOfst[4]=10 cells (3 PI)
8160 12:29:33.549523 u2DelayCellOfst[5]=0 cells (0 PI)
8161 12:29:33.552802 u2DelayCellOfst[6]=17 cells (5 PI)
8162 12:29:33.556075 u2DelayCellOfst[7]=17 cells (5 PI)
8163 12:29:33.559417 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8164 12:29:33.562783 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8165 12:29:33.566084 == TX Byte 1 ==
8166 12:29:33.569489 u2DelayCellOfst[8]=0 cells (0 PI)
8167 12:29:33.572803 u2DelayCellOfst[9]=0 cells (0 PI)
8168 12:29:33.572885 u2DelayCellOfst[10]=7 cells (2 PI)
8169 12:29:33.576183 u2DelayCellOfst[11]=0 cells (0 PI)
8170 12:29:33.579517 u2DelayCellOfst[12]=10 cells (3 PI)
8171 12:29:33.582800 u2DelayCellOfst[13]=10 cells (3 PI)
8172 12:29:33.586104 u2DelayCellOfst[14]=14 cells (4 PI)
8173 12:29:33.589266 u2DelayCellOfst[15]=10 cells (3 PI)
8174 12:29:33.595861 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8175 12:29:33.599187 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8176 12:29:33.599270 DramC Write-DBI on
8177 12:29:33.599335 ==
8178 12:29:33.603135 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 12:29:33.609565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 12:29:33.609651 ==
8181 12:29:33.609735
8182 12:29:33.609815
8183 12:29:33.609893 TX Vref Scan disable
8184 12:29:33.613302 == TX Byte 0 ==
8185 12:29:33.616702 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8186 12:29:33.619992 == TX Byte 1 ==
8187 12:29:33.623724 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8188 12:29:33.627104 DramC Write-DBI off
8189 12:29:33.627188
8190 12:29:33.627290 [DATLAT]
8191 12:29:33.627410 Freq=1600, CH0 RK1
8192 12:29:33.627502
8193 12:29:33.630308 DATLAT Default: 0xf
8194 12:29:33.630397 0, 0xFFFF, sum = 0
8195 12:29:33.633073 1, 0xFFFF, sum = 0
8196 12:29:33.636878 2, 0xFFFF, sum = 0
8197 12:29:33.636963 3, 0xFFFF, sum = 0
8198 12:29:33.640325 4, 0xFFFF, sum = 0
8199 12:29:33.640410 5, 0xFFFF, sum = 0
8200 12:29:33.643534 6, 0xFFFF, sum = 0
8201 12:29:33.643619 7, 0xFFFF, sum = 0
8202 12:29:33.646688 8, 0xFFFF, sum = 0
8203 12:29:33.646773 9, 0xFFFF, sum = 0
8204 12:29:33.650069 10, 0xFFFF, sum = 0
8205 12:29:33.650179 11, 0xFFFF, sum = 0
8206 12:29:33.653323 12, 0xFFFF, sum = 0
8207 12:29:33.653406 13, 0xFFFF, sum = 0
8208 12:29:33.656711 14, 0x0, sum = 1
8209 12:29:33.656791 15, 0x0, sum = 2
8210 12:29:33.660003 16, 0x0, sum = 3
8211 12:29:33.660084 17, 0x0, sum = 4
8212 12:29:33.663271 best_step = 15
8213 12:29:33.663406
8214 12:29:33.663503 ==
8215 12:29:33.666377 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 12:29:33.669818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 12:29:33.669925 ==
8218 12:29:33.673046 RX Vref Scan: 0
8219 12:29:33.673164
8220 12:29:33.673268 RX Vref 0 -> 0, step: 1
8221 12:29:33.673365
8222 12:29:33.676576 RX Delay 11 -> 252, step: 4
8223 12:29:33.679716 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8224 12:29:33.686405 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8225 12:29:33.689621 iDelay=191, Bit 2, Center 126 (71 ~ 182) 112
8226 12:29:33.692835 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8227 12:29:33.696255 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8228 12:29:33.699368 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8229 12:29:33.706074 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8230 12:29:33.709389 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8231 12:29:33.712666 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8232 12:29:33.716035 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8233 12:29:33.719331 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8234 12:29:33.726003 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8235 12:29:33.729268 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8236 12:29:33.732473 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8237 12:29:33.735970 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8238 12:29:33.742910 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8239 12:29:33.743324 ==
8240 12:29:33.746087 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 12:29:33.749454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 12:29:33.749872 ==
8243 12:29:33.750187 DQS Delay:
8244 12:29:33.752781 DQS0 = 0, DQS1 = 0
8245 12:29:33.753172 DQM Delay:
8246 12:29:33.756107 DQM0 = 128, DQM1 = 122
8247 12:29:33.756572 DQ Delay:
8248 12:29:33.759550 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8249 12:29:33.762064 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8250 12:29:33.765978 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8251 12:29:33.769521 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8252 12:29:33.772670
8253 12:29:33.773185
8254 12:29:33.773583
8255 12:29:33.773955 [DramC_TX_OE_Calibration] TA2
8256 12:29:33.775970 Original DQ_B0 (3 6) =30, OEN = 27
8257 12:29:33.779433 Original DQ_B1 (3 6) =30, OEN = 27
8258 12:29:33.782609 24, 0x0, End_B0=24 End_B1=24
8259 12:29:33.785724 25, 0x0, End_B0=25 End_B1=25
8260 12:29:33.789137 26, 0x0, End_B0=26 End_B1=26
8261 12:29:33.789642 27, 0x0, End_B0=27 End_B1=27
8262 12:29:33.792445 28, 0x0, End_B0=28 End_B1=28
8263 12:29:33.795715 29, 0x0, End_B0=29 End_B1=29
8264 12:29:33.798882 30, 0x0, End_B0=30 End_B1=30
8265 12:29:33.801987 31, 0x4141, End_B0=30 End_B1=30
8266 12:29:33.802478 Byte0 end_step=30 best_step=27
8267 12:29:33.805426 Byte1 end_step=30 best_step=27
8268 12:29:33.808836 Byte0 TX OE(2T, 0.5T) = (3, 3)
8269 12:29:33.811907 Byte1 TX OE(2T, 0.5T) = (3, 3)
8270 12:29:33.812415
8271 12:29:33.812858
8272 12:29:33.822099 [DQSOSCAuto] RK1, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8273 12:29:33.822652 CH0 RK1: MR19=303, MR18=190E
8274 12:29:33.828756 CH0_RK1: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8275 12:29:33.832003 [RxdqsGatingPostProcess] freq 1600
8276 12:29:33.838609 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8277 12:29:33.841796 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 12:29:33.845057 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 12:29:33.849147 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 12:29:33.852312 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 12:29:33.852703 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 12:29:33.855485 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 12:29:33.858868 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 12:29:33.861540 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 12:29:33.864875 Pre-setting of DQS Precalculation
8286 12:29:33.871425 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8287 12:29:33.871938 ==
8288 12:29:33.874722 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 12:29:33.877956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 12:29:33.878489 ==
8291 12:29:33.885534 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 12:29:33.888060 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 12:29:33.891416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 12:29:33.898070 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 12:29:33.907155 [CA 0] Center 43 (15~72) winsize 58
8296 12:29:33.910387 [CA 1] Center 43 (14~72) winsize 59
8297 12:29:33.913301 [CA 2] Center 38 (10~67) winsize 58
8298 12:29:33.916556 [CA 3] Center 37 (8~67) winsize 60
8299 12:29:33.920231 [CA 4] Center 38 (9~68) winsize 60
8300 12:29:33.923412 [CA 5] Center 37 (9~66) winsize 58
8301 12:29:33.923794
8302 12:29:33.926575 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8303 12:29:33.927029
8304 12:29:33.929929 [CATrainingPosCal] consider 1 rank data
8305 12:29:33.933255 u2DelayCellTimex100 = 275/100 ps
8306 12:29:33.940077 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8307 12:29:33.943272 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8308 12:29:33.946215 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8309 12:29:33.949547 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8310 12:29:33.952834 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8311 12:29:33.956232 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8312 12:29:33.956319
8313 12:29:33.959876 CA PerBit enable=1, Macro0, CA PI delay=37
8314 12:29:33.959957
8315 12:29:33.963199 [CBTSetCACLKResult] CA Dly = 37
8316 12:29:33.966541 CS Dly: 8 (0~39)
8317 12:29:33.969854 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 12:29:33.973149 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 12:29:33.973260 ==
8320 12:29:33.976386 Dram Type= 6, Freq= 0, CH_1, rank 1
8321 12:29:33.979625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 12:29:33.982921 ==
8323 12:29:33.986229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 12:29:33.989520 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 12:29:33.996228 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 12:29:34.002689 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 12:29:34.009871 [CA 0] Center 43 (14~72) winsize 59
8328 12:29:34.013162 [CA 1] Center 43 (14~72) winsize 59
8329 12:29:34.016426 [CA 2] Center 38 (9~67) winsize 59
8330 12:29:34.019895 [CA 3] Center 37 (8~67) winsize 60
8331 12:29:34.023075 [CA 4] Center 38 (9~68) winsize 60
8332 12:29:34.026351 [CA 5] Center 36 (7~66) winsize 60
8333 12:29:34.026449
8334 12:29:34.029740 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8335 12:29:34.029826
8336 12:29:34.032970 [CATrainingPosCal] consider 2 rank data
8337 12:29:34.036169 u2DelayCellTimex100 = 275/100 ps
8338 12:29:34.040075 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8339 12:29:34.046595 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8340 12:29:34.049730 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8341 12:29:34.053140 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8342 12:29:34.056538 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8343 12:29:34.059706 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8344 12:29:34.059785
8345 12:29:34.063083 CA PerBit enable=1, Macro0, CA PI delay=37
8346 12:29:34.063163
8347 12:29:34.066209 [CBTSetCACLKResult] CA Dly = 37
8348 12:29:34.069419 CS Dly: 10 (0~44)
8349 12:29:34.072843 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 12:29:34.076216 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 12:29:34.076296
8352 12:29:34.079503 ----->DramcWriteLeveling(PI) begin...
8353 12:29:34.079585 ==
8354 12:29:34.082899 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 12:29:34.089454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 12:29:34.089541 ==
8357 12:29:34.092850 Write leveling (Byte 0): 24 => 24
8358 12:29:34.092935 Write leveling (Byte 1): 28 => 28
8359 12:29:34.096145 DramcWriteLeveling(PI) end<-----
8360 12:29:34.096230
8361 12:29:34.096315 ==
8362 12:29:34.099514 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 12:29:34.106300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 12:29:34.106385 ==
8365 12:29:34.109475 [Gating] SW mode calibration
8366 12:29:34.116124 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8367 12:29:34.119551 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8368 12:29:34.126051 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 12:29:34.129240 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 12:29:34.132527 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:29:34.139226 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:29:34.142384 1 4 16 | B1->B0 | 2e2e 2928 | 0 1 | (0 0) (0 0)
8373 12:29:34.146297 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 12:29:34.152696 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 12:29:34.155999 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:29:34.159311 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:29:34.165915 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:29:34.169151 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:29:34.172341 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:29:34.178913 1 5 16 | B1->B0 | 2a2a 3030 | 0 0 | (1 0) (1 0)
8381 12:29:34.182107 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 12:29:34.185426 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 12:29:34.188827 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:29:34.195478 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:29:34.198984 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:29:34.202240 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:29:34.209253 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8388 12:29:34.212552 1 6 16 | B1->B0 | 4545 3535 | 0 0 | (0 0) (1 1)
8389 12:29:34.215794 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 12:29:34.222421 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 12:29:34.225688 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:29:34.229036 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:29:34.236185 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:29:34.239318 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:29:34.242558 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:29:34.249218 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 12:29:34.252160 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8398 12:29:34.255999 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:29:34.262049 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:29:34.265883 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:29:34.269088 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:29:34.275567 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:29:34.278652 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:29:34.282470 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:29:34.288446 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:29:34.291840 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:29:34.295494 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:29:34.301742 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:29:34.305139 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:29:34.308633 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:29:34.315086 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8412 12:29:34.318432 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8413 12:29:34.321674 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 12:29:34.325219 Total UI for P1: 0, mck2ui 16
8415 12:29:34.328547 best dqsien dly found for B0: ( 1, 9, 14)
8416 12:29:34.331794 Total UI for P1: 0, mck2ui 16
8417 12:29:34.335139 best dqsien dly found for B1: ( 1, 9, 16)
8418 12:29:34.338816 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8419 12:29:34.341952 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8420 12:29:34.342386
8421 12:29:34.345106 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8422 12:29:34.351882 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8423 12:29:34.352539 [Gating] SW calibration Done
8424 12:29:34.354936 ==
8425 12:29:34.355651 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:29:34.361761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:29:34.362395 ==
8428 12:29:34.362958 RX Vref Scan: 0
8429 12:29:34.363637
8430 12:29:34.365162 RX Vref 0 -> 0, step: 1
8431 12:29:34.365779
8432 12:29:34.368846 RX Delay 0 -> 252, step: 8
8433 12:29:34.371242 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8434 12:29:34.375121 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8435 12:29:34.378137 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8436 12:29:34.384511 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8437 12:29:34.388391 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8438 12:29:34.391123 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8439 12:29:34.394496 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8440 12:29:34.397770 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8441 12:29:34.404333 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8442 12:29:34.407666 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8443 12:29:34.410934 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8444 12:29:34.414164 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8445 12:29:34.418100 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8446 12:29:34.424180 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8447 12:29:34.427310 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8448 12:29:34.431335 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8449 12:29:34.431753 ==
8450 12:29:34.434048 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 12:29:34.437356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 12:29:34.440657 ==
8453 12:29:34.441053 DQS Delay:
8454 12:29:34.441362 DQS0 = 0, DQS1 = 0
8455 12:29:34.444330 DQM Delay:
8456 12:29:34.444782 DQM0 = 134, DQM1 = 127
8457 12:29:34.447683 DQ Delay:
8458 12:29:34.451130 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8459 12:29:34.454034 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8460 12:29:34.457510 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8461 12:29:34.460566 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8462 12:29:34.460865
8463 12:29:34.461104
8464 12:29:34.461326 ==
8465 12:29:34.464358 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 12:29:34.467587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 12:29:34.468031 ==
8468 12:29:34.468465
8469 12:29:34.470996
8470 12:29:34.471418 TX Vref Scan disable
8471 12:29:34.474357 == TX Byte 0 ==
8472 12:29:34.477522 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8473 12:29:34.480629 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8474 12:29:34.483904 == TX Byte 1 ==
8475 12:29:34.487140 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8476 12:29:34.490443 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8477 12:29:34.490806 ==
8478 12:29:34.493595 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 12:29:34.500287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 12:29:34.500822 ==
8481 12:29:34.513650
8482 12:29:34.517049 TX Vref early break, caculate TX vref
8483 12:29:34.520308 TX Vref=16, minBit 8, minWin=21, winSum=362
8484 12:29:34.523658 TX Vref=18, minBit 8, minWin=21, winSum=371
8485 12:29:34.527005 TX Vref=20, minBit 8, minWin=21, winSum=385
8486 12:29:34.529721 TX Vref=22, minBit 8, minWin=23, winSum=394
8487 12:29:34.533605 TX Vref=24, minBit 8, minWin=23, winSum=402
8488 12:29:34.540152 TX Vref=26, minBit 8, minWin=24, winSum=413
8489 12:29:34.543403 TX Vref=28, minBit 11, minWin=25, winSum=418
8490 12:29:34.546632 TX Vref=30, minBit 8, minWin=24, winSum=417
8491 12:29:34.549896 TX Vref=32, minBit 0, minWin=24, winSum=411
8492 12:29:34.553273 TX Vref=34, minBit 8, minWin=23, winSum=400
8493 12:29:34.556373 TX Vref=36, minBit 8, minWin=23, winSum=391
8494 12:29:34.562966 [TxChooseVref] Worse bit 11, Min win 25, Win sum 418, Final Vref 28
8495 12:29:34.563434
8496 12:29:34.566050 Final TX Range 0 Vref 28
8497 12:29:34.566444
8498 12:29:34.566796 ==
8499 12:29:34.569896 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 12:29:34.573173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 12:29:34.573600 ==
8502 12:29:34.576433
8503 12:29:34.576888
8504 12:29:34.577260 TX Vref Scan disable
8505 12:29:34.582926 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8506 12:29:34.583321 == TX Byte 0 ==
8507 12:29:34.586133 u2DelayCellOfst[0]=17 cells (5 PI)
8508 12:29:34.589924 u2DelayCellOfst[1]=10 cells (3 PI)
8509 12:29:34.593309 u2DelayCellOfst[2]=0 cells (0 PI)
8510 12:29:34.596550 u2DelayCellOfst[3]=7 cells (2 PI)
8511 12:29:34.599557 u2DelayCellOfst[4]=7 cells (2 PI)
8512 12:29:34.602797 u2DelayCellOfst[5]=21 cells (6 PI)
8513 12:29:34.606016 u2DelayCellOfst[6]=17 cells (5 PI)
8514 12:29:34.609368 u2DelayCellOfst[7]=7 cells (2 PI)
8515 12:29:34.613330 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8516 12:29:34.616663 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8517 12:29:34.619876 == TX Byte 1 ==
8518 12:29:34.622994 u2DelayCellOfst[8]=0 cells (0 PI)
8519 12:29:34.623324 u2DelayCellOfst[9]=7 cells (2 PI)
8520 12:29:34.626357 u2DelayCellOfst[10]=14 cells (4 PI)
8521 12:29:34.629678 u2DelayCellOfst[11]=7 cells (2 PI)
8522 12:29:34.633023 u2DelayCellOfst[12]=14 cells (4 PI)
8523 12:29:34.636402 u2DelayCellOfst[13]=17 cells (5 PI)
8524 12:29:34.639501 u2DelayCellOfst[14]=17 cells (5 PI)
8525 12:29:34.642817 u2DelayCellOfst[15]=17 cells (5 PI)
8526 12:29:34.649507 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8527 12:29:34.652614 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8528 12:29:34.652937 DramC Write-DBI on
8529 12:29:34.653365 ==
8530 12:29:34.655926 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 12:29:34.663026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 12:29:34.663408 ==
8533 12:29:34.663709
8534 12:29:34.664001
8535 12:29:34.664289 TX Vref Scan disable
8536 12:29:34.667042 == TX Byte 0 ==
8537 12:29:34.670281 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8538 12:29:34.673457 == TX Byte 1 ==
8539 12:29:34.676841 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8540 12:29:34.680133 DramC Write-DBI off
8541 12:29:34.680620
8542 12:29:34.681038 [DATLAT]
8543 12:29:34.681502 Freq=1600, CH1 RK0
8544 12:29:34.681941
8545 12:29:34.683550 DATLAT Default: 0xf
8546 12:29:34.683990 0, 0xFFFF, sum = 0
8547 12:29:34.686623 1, 0xFFFF, sum = 0
8548 12:29:34.689954 2, 0xFFFF, sum = 0
8549 12:29:34.690259 3, 0xFFFF, sum = 0
8550 12:29:34.693053 4, 0xFFFF, sum = 0
8551 12:29:34.693358 5, 0xFFFF, sum = 0
8552 12:29:34.696353 6, 0xFFFF, sum = 0
8553 12:29:34.696678 7, 0xFFFF, sum = 0
8554 12:29:34.699618 8, 0xFFFF, sum = 0
8555 12:29:34.700051 9, 0xFFFF, sum = 0
8556 12:29:34.703710 10, 0xFFFF, sum = 0
8557 12:29:34.704037 11, 0xFFFF, sum = 0
8558 12:29:34.706799 12, 0xFFFF, sum = 0
8559 12:29:34.707199 13, 0xFFFF, sum = 0
8560 12:29:34.710321 14, 0x0, sum = 1
8561 12:29:34.710712 15, 0x0, sum = 2
8562 12:29:34.712864 16, 0x0, sum = 3
8563 12:29:34.713167 17, 0x0, sum = 4
8564 12:29:34.716158 best_step = 15
8565 12:29:34.716472
8566 12:29:34.716760 ==
8567 12:29:34.719518 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 12:29:34.723424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 12:29:34.723720 ==
8570 12:29:34.726775 RX Vref Scan: 1
8571 12:29:34.727159
8572 12:29:34.727498 Set Vref Range= 24 -> 127
8573 12:29:34.727731
8574 12:29:34.729398 RX Vref 24 -> 127, step: 1
8575 12:29:34.729696
8576 12:29:34.732787 RX Delay 11 -> 252, step: 4
8577 12:29:34.733081
8578 12:29:34.736136 Set Vref, RX VrefLevel [Byte0]: 24
8579 12:29:34.739495 [Byte1]: 24
8580 12:29:34.739886
8581 12:29:34.742733 Set Vref, RX VrefLevel [Byte0]: 25
8582 12:29:34.746025 [Byte1]: 25
8583 12:29:34.749846
8584 12:29:34.750144 Set Vref, RX VrefLevel [Byte0]: 26
8585 12:29:34.753286 [Byte1]: 26
8586 12:29:34.757198
8587 12:29:34.757531 Set Vref, RX VrefLevel [Byte0]: 27
8588 12:29:34.760509 [Byte1]: 27
8589 12:29:34.764388
8590 12:29:34.764805 Set Vref, RX VrefLevel [Byte0]: 28
8591 12:29:34.768444 [Byte1]: 28
8592 12:29:34.772361
8593 12:29:34.772673 Set Vref, RX VrefLevel [Byte0]: 29
8594 12:29:34.775601 [Byte1]: 29
8595 12:29:34.780243
8596 12:29:34.780543 Set Vref, RX VrefLevel [Byte0]: 30
8597 12:29:34.783416 [Byte1]: 30
8598 12:29:34.787435
8599 12:29:34.787737 Set Vref, RX VrefLevel [Byte0]: 31
8600 12:29:34.790677 [Byte1]: 31
8601 12:29:34.795227
8602 12:29:34.795599 Set Vref, RX VrefLevel [Byte0]: 32
8603 12:29:34.798336 [Byte1]: 32
8604 12:29:34.802875
8605 12:29:34.803231 Set Vref, RX VrefLevel [Byte0]: 33
8606 12:29:34.806072 [Byte1]: 33
8607 12:29:34.810700
8608 12:29:34.810999 Set Vref, RX VrefLevel [Byte0]: 34
8609 12:29:34.814038 [Byte1]: 34
8610 12:29:34.817973
8611 12:29:34.818293 Set Vref, RX VrefLevel [Byte0]: 35
8612 12:29:34.821403 [Byte1]: 35
8613 12:29:34.826051
8614 12:29:34.826351 Set Vref, RX VrefLevel [Byte0]: 36
8615 12:29:34.828700 [Byte1]: 36
8616 12:29:34.833491
8617 12:29:34.833835 Set Vref, RX VrefLevel [Byte0]: 37
8618 12:29:34.836841 [Byte1]: 37
8619 12:29:34.840695
8620 12:29:34.840907 Set Vref, RX VrefLevel [Byte0]: 38
8621 12:29:34.844071 [Byte1]: 38
8622 12:29:34.848538
8623 12:29:34.848721 Set Vref, RX VrefLevel [Byte0]: 39
8624 12:29:34.851963 [Byte1]: 39
8625 12:29:34.855949
8626 12:29:34.856130 Set Vref, RX VrefLevel [Byte0]: 40
8627 12:29:34.859174 [Byte1]: 40
8628 12:29:34.863324
8629 12:29:34.863536 Set Vref, RX VrefLevel [Byte0]: 41
8630 12:29:34.866659 [Byte1]: 41
8631 12:29:34.871151
8632 12:29:34.871419 Set Vref, RX VrefLevel [Byte0]: 42
8633 12:29:34.874364 [Byte1]: 42
8634 12:29:34.879042
8635 12:29:34.879126 Set Vref, RX VrefLevel [Byte0]: 43
8636 12:29:34.882248 [Byte1]: 43
8637 12:29:34.886256
8638 12:29:34.886354 Set Vref, RX VrefLevel [Byte0]: 44
8639 12:29:34.889722 [Byte1]: 44
8640 12:29:34.893754
8641 12:29:34.893857 Set Vref, RX VrefLevel [Byte0]: 45
8642 12:29:34.897165 [Byte1]: 45
8643 12:29:34.901646
8644 12:29:34.901731 Set Vref, RX VrefLevel [Byte0]: 46
8645 12:29:34.904870 [Byte1]: 46
8646 12:29:34.908960
8647 12:29:34.909043 Set Vref, RX VrefLevel [Byte0]: 47
8648 12:29:34.912178 [Byte1]: 47
8649 12:29:34.916918
8650 12:29:34.917001 Set Vref, RX VrefLevel [Byte0]: 48
8651 12:29:34.920150 [Byte1]: 48
8652 12:29:34.924200
8653 12:29:34.924312 Set Vref, RX VrefLevel [Byte0]: 49
8654 12:29:34.927628 [Byte1]: 49
8655 12:29:34.932274
8656 12:29:34.932377 Set Vref, RX VrefLevel [Byte0]: 50
8657 12:29:34.935085 [Byte1]: 50
8658 12:29:34.939974
8659 12:29:34.940070 Set Vref, RX VrefLevel [Byte0]: 51
8660 12:29:34.943280 [Byte1]: 51
8661 12:29:34.947203
8662 12:29:34.947313 Set Vref, RX VrefLevel [Byte0]: 52
8663 12:29:34.950448 [Byte1]: 52
8664 12:29:34.955100
8665 12:29:34.955183 Set Vref, RX VrefLevel [Byte0]: 53
8666 12:29:34.958431 [Byte1]: 53
8667 12:29:34.962441
8668 12:29:34.962551 Set Vref, RX VrefLevel [Byte0]: 54
8669 12:29:34.965771 [Byte1]: 54
8670 12:29:34.969716
8671 12:29:34.969821 Set Vref, RX VrefLevel [Byte0]: 55
8672 12:29:34.973708 [Byte1]: 55
8673 12:29:34.977592
8674 12:29:34.977674 Set Vref, RX VrefLevel [Byte0]: 56
8675 12:29:34.980939 [Byte1]: 56
8676 12:29:34.985624
8677 12:29:34.985708 Set Vref, RX VrefLevel [Byte0]: 57
8678 12:29:34.988433 [Byte1]: 57
8679 12:29:34.993125
8680 12:29:34.993209 Set Vref, RX VrefLevel [Byte0]: 58
8681 12:29:34.996407 [Byte1]: 58
8682 12:29:35.000433
8683 12:29:35.000552 Set Vref, RX VrefLevel [Byte0]: 59
8684 12:29:35.004027 [Byte1]: 59
8685 12:29:35.008206
8686 12:29:35.008317 Set Vref, RX VrefLevel [Byte0]: 60
8687 12:29:35.011336 [Byte1]: 60
8688 12:29:35.016053
8689 12:29:35.016164 Set Vref, RX VrefLevel [Byte0]: 61
8690 12:29:35.019250 [Byte1]: 61
8691 12:29:35.023202
8692 12:29:35.023316 Set Vref, RX VrefLevel [Byte0]: 62
8693 12:29:35.026601 [Byte1]: 62
8694 12:29:35.031124
8695 12:29:35.031232 Set Vref, RX VrefLevel [Byte0]: 63
8696 12:29:35.034433 [Byte1]: 63
8697 12:29:35.038619
8698 12:29:35.038732 Set Vref, RX VrefLevel [Byte0]: 64
8699 12:29:35.042030 [Byte1]: 64
8700 12:29:35.045977
8701 12:29:35.046080 Set Vref, RX VrefLevel [Byte0]: 65
8702 12:29:35.049987 [Byte1]: 65
8703 12:29:35.053849
8704 12:29:35.053970 Set Vref, RX VrefLevel [Byte0]: 66
8705 12:29:35.057113 [Byte1]: 66
8706 12:29:35.061699
8707 12:29:35.061806 Set Vref, RX VrefLevel [Byte0]: 67
8708 12:29:35.065013 [Byte1]: 67
8709 12:29:35.068942
8710 12:29:35.069056 Set Vref, RX VrefLevel [Byte0]: 68
8711 12:29:35.072242 [Byte1]: 68
8712 12:29:35.076785
8713 12:29:35.076902 Set Vref, RX VrefLevel [Byte0]: 69
8714 12:29:35.080017 [Byte1]: 69
8715 12:29:35.083919
8716 12:29:35.084005 Set Vref, RX VrefLevel [Byte0]: 70
8717 12:29:35.087191 [Byte1]: 70
8718 12:29:35.091635
8719 12:29:35.091749 Set Vref, RX VrefLevel [Byte0]: 71
8720 12:29:35.095120 [Byte1]: 71
8721 12:29:35.099156
8722 12:29:35.099268 Set Vref, RX VrefLevel [Byte0]: 72
8723 12:29:35.102552 [Byte1]: 72
8724 12:29:35.107124
8725 12:29:35.107228 Set Vref, RX VrefLevel [Byte0]: 73
8726 12:29:35.110389 [Byte1]: 73
8727 12:29:35.114793
8728 12:29:35.114902 Set Vref, RX VrefLevel [Byte0]: 74
8729 12:29:35.117962 [Byte1]: 74
8730 12:29:35.121946
8731 12:29:35.125733 Final RX Vref Byte 0 = 64 to rank0
8732 12:29:35.125845 Final RX Vref Byte 1 = 59 to rank0
8733 12:29:35.128594 Final RX Vref Byte 0 = 64 to rank1
8734 12:29:35.132455 Final RX Vref Byte 1 = 59 to rank1==
8735 12:29:35.135892 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 12:29:35.141854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 12:29:35.141973 ==
8738 12:29:35.142074 DQS Delay:
8739 12:29:35.142173 DQS0 = 0, DQS1 = 0
8740 12:29:35.145297 DQM Delay:
8741 12:29:35.145402 DQM0 = 132, DQM1 = 124
8742 12:29:35.148649 DQ Delay:
8743 12:29:35.151902 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132
8744 12:29:35.155384 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8745 12:29:35.158748 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118
8746 12:29:35.162273 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8747 12:29:35.162375
8748 12:29:35.162467
8749 12:29:35.162570
8750 12:29:35.165546 [DramC_TX_OE_Calibration] TA2
8751 12:29:35.168968 Original DQ_B0 (3 6) =30, OEN = 27
8752 12:29:35.172268 Original DQ_B1 (3 6) =30, OEN = 27
8753 12:29:35.175431 24, 0x0, End_B0=24 End_B1=24
8754 12:29:35.175535 25, 0x0, End_B0=25 End_B1=25
8755 12:29:35.178668 26, 0x0, End_B0=26 End_B1=26
8756 12:29:35.181973 27, 0x0, End_B0=27 End_B1=27
8757 12:29:35.185160 28, 0x0, End_B0=28 End_B1=28
8758 12:29:35.188546 29, 0x0, End_B0=29 End_B1=29
8759 12:29:35.188666 30, 0x0, End_B0=30 End_B1=30
8760 12:29:35.191818 31, 0x4545, End_B0=30 End_B1=30
8761 12:29:35.195048 Byte0 end_step=30 best_step=27
8762 12:29:35.198390 Byte1 end_step=30 best_step=27
8763 12:29:35.201798 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 12:29:35.205120 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 12:29:35.205242
8766 12:29:35.205346
8767 12:29:35.211732 [DQSOSCAuto] RK0, (LSB)MR18= 0x1501, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 399 ps
8768 12:29:35.214848 CH1 RK0: MR19=303, MR18=1501
8769 12:29:35.221423 CH1_RK0: MR19=0x303, MR18=0x1501, DQSOSC=399, MR23=63, INC=23, DEC=15
8770 12:29:35.221536
8771 12:29:35.224772 ----->DramcWriteLeveling(PI) begin...
8772 12:29:35.224880 ==
8773 12:29:35.228142 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 12:29:35.231455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 12:29:35.231568 ==
8776 12:29:35.234778 Write leveling (Byte 0): 24 => 24
8777 12:29:35.238217 Write leveling (Byte 1): 25 => 25
8778 12:29:35.241580 DramcWriteLeveling(PI) end<-----
8779 12:29:35.241695
8780 12:29:35.241794 ==
8781 12:29:35.244973 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 12:29:35.248384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 12:29:35.248477 ==
8784 12:29:35.251754 [Gating] SW mode calibration
8785 12:29:35.257785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 12:29:35.264967 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 12:29:35.268396 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 12:29:35.274398 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 12:29:35.277869 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8790 12:29:35.281294 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8791 12:29:35.287914 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 12:29:35.291159 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 12:29:35.294533 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 12:29:35.300960 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 12:29:35.304268 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 12:29:35.307713 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8797 12:29:35.314384 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8798 12:29:35.317702 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8799 12:29:35.320909 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8800 12:29:35.327270 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 12:29:35.330729 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:29:35.334115 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 12:29:35.337265 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 12:29:35.343920 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 12:29:35.347228 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8806 12:29:35.350641 1 6 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8807 12:29:35.357438 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:29:35.360835 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:29:35.364003 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 12:29:35.370652 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 12:29:35.374002 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 12:29:35.377324 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8813 12:29:35.383530 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8814 12:29:35.386754 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8815 12:29:35.389998 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8816 12:29:35.397174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:29:35.399967 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:29:35.403898 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:29:35.410226 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:29:35.413468 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:29:35.416750 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:29:35.423363 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:29:35.426709 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:29:35.429880 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:29:35.437064 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:29:35.439887 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:29:35.443040 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:29:35.449758 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8829 12:29:35.453128 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8830 12:29:35.457071 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8831 12:29:35.463293 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8832 12:29:35.463446 Total UI for P1: 0, mck2ui 16
8833 12:29:35.470105 best dqsien dly found for B0: ( 1, 9, 8)
8834 12:29:35.473501 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 12:29:35.476769 Total UI for P1: 0, mck2ui 16
8836 12:29:35.480081 best dqsien dly found for B1: ( 1, 9, 14)
8837 12:29:35.483397 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8838 12:29:35.486262 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8839 12:29:35.486374
8840 12:29:35.490168 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8841 12:29:35.493458 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8842 12:29:35.496858 [Gating] SW calibration Done
8843 12:29:35.496968 ==
8844 12:29:35.499946 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 12:29:35.503230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 12:29:35.503317 ==
8847 12:29:35.506555 RX Vref Scan: 0
8848 12:29:35.506639
8849 12:29:35.509683 RX Vref 0 -> 0, step: 1
8850 12:29:35.509767
8851 12:29:35.509842 RX Delay 0 -> 252, step: 8
8852 12:29:35.516246 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8853 12:29:35.519583 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8854 12:29:35.522894 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8855 12:29:35.526152 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8856 12:29:35.530018 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8857 12:29:35.536338 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8858 12:29:35.539566 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8859 12:29:35.543258 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8860 12:29:35.546575 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8861 12:29:35.549841 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8862 12:29:35.555957 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8863 12:29:35.559387 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8864 12:29:35.562809 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8865 12:29:35.566140 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8866 12:29:35.572913 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8867 12:29:35.576343 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8868 12:29:35.576430 ==
8869 12:29:35.579770 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 12:29:35.583072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 12:29:35.583180 ==
8872 12:29:35.583290 DQS Delay:
8873 12:29:35.586332 DQS0 = 0, DQS1 = 0
8874 12:29:35.586416 DQM Delay:
8875 12:29:35.589534 DQM0 = 132, DQM1 = 130
8876 12:29:35.589624 DQ Delay:
8877 12:29:35.592785 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8878 12:29:35.596068 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8879 12:29:35.599589 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8880 12:29:35.605979 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8881 12:29:35.606068
8882 12:29:35.606165
8883 12:29:35.606255 ==
8884 12:29:35.609448 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 12:29:35.612574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 12:29:35.612663 ==
8887 12:29:35.612731
8888 12:29:35.612792
8889 12:29:35.616405 TX Vref Scan disable
8890 12:29:35.616479 == TX Byte 0 ==
8891 12:29:35.622832 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8892 12:29:35.626247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 12:29:35.626355 == TX Byte 1 ==
8894 12:29:35.632372 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8895 12:29:35.636245 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8896 12:29:35.636352 ==
8897 12:29:35.639423 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 12:29:35.642632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 12:29:35.642716 ==
8900 12:29:35.658056
8901 12:29:35.661345 TX Vref early break, caculate TX vref
8902 12:29:35.664741 TX Vref=16, minBit 8, minWin=22, winSum=382
8903 12:29:35.668133 TX Vref=18, minBit 0, minWin=24, winSum=399
8904 12:29:35.671556 TX Vref=20, minBit 5, minWin=24, winSum=404
8905 12:29:35.675017 TX Vref=22, minBit 15, minWin=24, winSum=411
8906 12:29:35.678229 TX Vref=24, minBit 9, minWin=25, winSum=419
8907 12:29:35.684911 TX Vref=26, minBit 6, minWin=25, winSum=428
8908 12:29:35.688022 TX Vref=28, minBit 5, minWin=26, winSum=432
8909 12:29:35.691319 TX Vref=30, minBit 0, minWin=25, winSum=427
8910 12:29:35.694706 TX Vref=32, minBit 0, minWin=24, winSum=424
8911 12:29:35.698104 TX Vref=34, minBit 0, minWin=25, winSum=415
8912 12:29:35.701315 TX Vref=36, minBit 0, minWin=24, winSum=411
8913 12:29:35.707930 TX Vref=38, minBit 0, minWin=23, winSum=392
8914 12:29:35.711318 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
8915 12:29:35.711416
8916 12:29:35.714630 Final TX Range 0 Vref 28
8917 12:29:35.714716
8918 12:29:35.714782 ==
8919 12:29:35.717892 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 12:29:35.721031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 12:29:35.724959 ==
8922 12:29:35.725070
8923 12:29:35.725167
8924 12:29:35.725261 TX Vref Scan disable
8925 12:29:35.731141 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8926 12:29:35.731249 == TX Byte 0 ==
8927 12:29:35.734588 u2DelayCellOfst[0]=17 cells (5 PI)
8928 12:29:35.737661 u2DelayCellOfst[1]=14 cells (4 PI)
8929 12:29:35.741586 u2DelayCellOfst[2]=0 cells (0 PI)
8930 12:29:35.744757 u2DelayCellOfst[3]=7 cells (2 PI)
8931 12:29:35.748016 u2DelayCellOfst[4]=7 cells (2 PI)
8932 12:29:35.751281 u2DelayCellOfst[5]=17 cells (5 PI)
8933 12:29:35.754582 u2DelayCellOfst[6]=17 cells (5 PI)
8934 12:29:35.757994 u2DelayCellOfst[7]=3 cells (1 PI)
8935 12:29:35.761341 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8936 12:29:35.764569 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8937 12:29:35.768024 == TX Byte 1 ==
8938 12:29:35.771223 u2DelayCellOfst[8]=0 cells (0 PI)
8939 12:29:35.774523 u2DelayCellOfst[9]=3 cells (1 PI)
8940 12:29:35.777846 u2DelayCellOfst[10]=10 cells (3 PI)
8941 12:29:35.777953 u2DelayCellOfst[11]=3 cells (1 PI)
8942 12:29:35.781213 u2DelayCellOfst[12]=10 cells (3 PI)
8943 12:29:35.784611 u2DelayCellOfst[13]=14 cells (4 PI)
8944 12:29:35.787715 u2DelayCellOfst[14]=14 cells (4 PI)
8945 12:29:35.791078 u2DelayCellOfst[15]=14 cells (4 PI)
8946 12:29:35.797751 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8947 12:29:35.801158 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8948 12:29:35.801282 DramC Write-DBI on
8949 12:29:35.801390 ==
8950 12:29:35.804264 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 12:29:35.811335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 12:29:35.811461 ==
8953 12:29:35.811551
8954 12:29:35.811616
8955 12:29:35.811678 TX Vref Scan disable
8956 12:29:35.815276 == TX Byte 0 ==
8957 12:29:35.818623 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8958 12:29:35.821924 == TX Byte 1 ==
8959 12:29:35.825196 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8960 12:29:35.828478 DramC Write-DBI off
8961 12:29:35.828589
8962 12:29:35.828684 [DATLAT]
8963 12:29:35.828779 Freq=1600, CH1 RK1
8964 12:29:35.828869
8965 12:29:35.831833 DATLAT Default: 0xf
8966 12:29:35.835063 0, 0xFFFF, sum = 0
8967 12:29:35.835168 1, 0xFFFF, sum = 0
8968 12:29:35.838438 2, 0xFFFF, sum = 0
8969 12:29:35.838539 3, 0xFFFF, sum = 0
8970 12:29:35.841929 4, 0xFFFF, sum = 0
8971 12:29:35.842012 5, 0xFFFF, sum = 0
8972 12:29:35.845038 6, 0xFFFF, sum = 0
8973 12:29:35.845127 7, 0xFFFF, sum = 0
8974 12:29:35.848279 8, 0xFFFF, sum = 0
8975 12:29:35.848397 9, 0xFFFF, sum = 0
8976 12:29:35.851510 10, 0xFFFF, sum = 0
8977 12:29:35.851601 11, 0xFFFF, sum = 0
8978 12:29:35.854660 12, 0xFFFF, sum = 0
8979 12:29:35.854775 13, 0xFFFF, sum = 0
8980 12:29:35.858003 14, 0x0, sum = 1
8981 12:29:35.858111 15, 0x0, sum = 2
8982 12:29:35.861385 16, 0x0, sum = 3
8983 12:29:35.861489 17, 0x0, sum = 4
8984 12:29:35.864682 best_step = 15
8985 12:29:35.864770
8986 12:29:35.864834 ==
8987 12:29:35.867887 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 12:29:35.871265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 12:29:35.871387 ==
8990 12:29:35.874505 RX Vref Scan: 0
8991 12:29:35.874607
8992 12:29:35.874698 RX Vref 0 -> 0, step: 1
8993 12:29:35.874786
8994 12:29:35.877751 RX Delay 11 -> 252, step: 4
8995 12:29:35.884517 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8996 12:29:35.887784 iDelay=191, Bit 1, Center 124 (75 ~ 174) 100
8997 12:29:35.890968 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8998 12:29:35.894238 iDelay=191, Bit 3, Center 130 (79 ~ 182) 104
8999 12:29:35.898013 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9000 12:29:35.901229 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9001 12:29:35.907946 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9002 12:29:35.911178 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
9003 12:29:35.914428 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9004 12:29:35.917640 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9005 12:29:35.921076 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9006 12:29:35.927689 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9007 12:29:35.930919 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9008 12:29:35.934311 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9009 12:29:35.937766 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
9010 12:29:35.944418 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9011 12:29:35.944538 ==
9012 12:29:35.947606 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 12:29:35.950756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 12:29:35.950863 ==
9015 12:29:35.950983 DQS Delay:
9016 12:29:35.954080 DQS0 = 0, DQS1 = 0
9017 12:29:35.954200 DQM Delay:
9018 12:29:35.957129 DQM0 = 130, DQM1 = 126
9019 12:29:35.957238 DQ Delay:
9020 12:29:35.960538 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
9021 12:29:35.963832 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9022 12:29:35.967082 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9023 12:29:35.970501 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9024 12:29:35.970579
9025 12:29:35.970655
9026 12:29:35.973774
9027 12:29:35.973881 [DramC_TX_OE_Calibration] TA2
9028 12:29:35.977082 Original DQ_B0 (3 6) =30, OEN = 27
9029 12:29:35.980374 Original DQ_B1 (3 6) =30, OEN = 27
9030 12:29:35.983807 24, 0x0, End_B0=24 End_B1=24
9031 12:29:35.987117 25, 0x0, End_B0=25 End_B1=25
9032 12:29:35.990563 26, 0x0, End_B0=26 End_B1=26
9033 12:29:35.990678 27, 0x0, End_B0=27 End_B1=27
9034 12:29:35.993808 28, 0x0, End_B0=28 End_B1=28
9035 12:29:35.997122 29, 0x0, End_B0=29 End_B1=29
9036 12:29:36.000216 30, 0x0, End_B0=30 End_B1=30
9037 12:29:36.004024 31, 0x4141, End_B0=30 End_B1=30
9038 12:29:36.004138 Byte0 end_step=30 best_step=27
9039 12:29:36.007419 Byte1 end_step=30 best_step=27
9040 12:29:36.010726 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 12:29:36.014024 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 12:29:36.014136
9043 12:29:36.014236
9044 12:29:36.020605 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9045 12:29:36.023631 CH1 RK1: MR19=303, MR18=1016
9046 12:29:36.030179 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9047 12:29:36.033502 [RxdqsGatingPostProcess] freq 1600
9048 12:29:36.039965 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 12:29:36.043290 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 12:29:36.046631 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 12:29:36.046735 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 12:29:36.049919 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 12:29:36.053777 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 12:29:36.057021 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 12:29:36.060199 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 12:29:36.063366 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 12:29:36.066783 Pre-setting of DQS Precalculation
9058 12:29:36.073366 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 12:29:36.080135 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 12:29:36.086616 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 12:29:36.086701
9062 12:29:36.086790
9063 12:29:36.089863 [Calibration Summary] 3200 Mbps
9064 12:29:36.089977 CH 0, Rank 0
9065 12:29:36.093157 SW Impedance : PASS
9066 12:29:36.096457 DUTY Scan : NO K
9067 12:29:36.096542 ZQ Calibration : PASS
9068 12:29:36.099793 Jitter Meter : NO K
9069 12:29:36.099887 CBT Training : PASS
9070 12:29:36.103038 Write leveling : PASS
9071 12:29:36.106296 RX DQS gating : PASS
9072 12:29:36.106380 RX DQ/DQS(RDDQC) : PASS
9073 12:29:36.110024 TX DQ/DQS : PASS
9074 12:29:36.113278 RX DATLAT : PASS
9075 12:29:36.113362 RX DQ/DQS(Engine): PASS
9076 12:29:36.116612 TX OE : PASS
9077 12:29:36.116696 All Pass.
9078 12:29:36.116765
9079 12:29:36.119890 CH 0, Rank 1
9080 12:29:36.119974 SW Impedance : PASS
9081 12:29:36.123161 DUTY Scan : NO K
9082 12:29:36.126361 ZQ Calibration : PASS
9083 12:29:36.126444 Jitter Meter : NO K
9084 12:29:36.129375 CBT Training : PASS
9085 12:29:36.132731 Write leveling : PASS
9086 12:29:36.132820 RX DQS gating : PASS
9087 12:29:36.136740 RX DQ/DQS(RDDQC) : PASS
9088 12:29:36.139789 TX DQ/DQS : PASS
9089 12:29:36.139874 RX DATLAT : PASS
9090 12:29:36.142997 RX DQ/DQS(Engine): PASS
9091 12:29:36.146295 TX OE : PASS
9092 12:29:36.146372 All Pass.
9093 12:29:36.146438
9094 12:29:36.146499 CH 1, Rank 0
9095 12:29:36.149700 SW Impedance : PASS
9096 12:29:36.152929 DUTY Scan : NO K
9097 12:29:36.153002 ZQ Calibration : PASS
9098 12:29:36.156303 Jitter Meter : NO K
9099 12:29:36.156386 CBT Training : PASS
9100 12:29:36.159635 Write leveling : PASS
9101 12:29:36.162809 RX DQS gating : PASS
9102 12:29:36.162892 RX DQ/DQS(RDDQC) : PASS
9103 12:29:36.166663 TX DQ/DQS : PASS
9104 12:29:36.169859 RX DATLAT : PASS
9105 12:29:36.169944 RX DQ/DQS(Engine): PASS
9106 12:29:36.173191 TX OE : PASS
9107 12:29:36.173274 All Pass.
9108 12:29:36.173341
9109 12:29:36.176663 CH 1, Rank 1
9110 12:29:36.176746 SW Impedance : PASS
9111 12:29:36.179846 DUTY Scan : NO K
9112 12:29:36.183219 ZQ Calibration : PASS
9113 12:29:36.183303 Jitter Meter : NO K
9114 12:29:36.186500 CBT Training : PASS
9115 12:29:36.189269 Write leveling : PASS
9116 12:29:36.189353 RX DQS gating : PASS
9117 12:29:36.192680 RX DQ/DQS(RDDQC) : PASS
9118 12:29:36.196040 TX DQ/DQS : PASS
9119 12:29:36.196123 RX DATLAT : PASS
9120 12:29:36.199249 RX DQ/DQS(Engine): PASS
9121 12:29:36.199332 TX OE : PASS
9122 12:29:36.202504 All Pass.
9123 12:29:36.202586
9124 12:29:36.202651 DramC Write-DBI on
9125 12:29:36.206453 PER_BANK_REFRESH: Hybrid Mode
9126 12:29:36.209217 TX_TRACKING: ON
9127 12:29:36.216404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 12:29:36.226216 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 12:29:36.232902 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 12:29:36.236304 [FAST_K] Save calibration result to emmc
9131 12:29:36.239404 sync common calibartion params.
9132 12:29:36.239517 sync cbt_mode0:1, 1:1
9133 12:29:36.242775 dram_init: ddr_geometry: 2
9134 12:29:36.246088 dram_init: ddr_geometry: 2
9135 12:29:36.249162 dram_init: ddr_geometry: 2
9136 12:29:36.249245 0:dram_rank_size:100000000
9137 12:29:36.252493 1:dram_rank_size:100000000
9138 12:29:36.259173 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 12:29:36.259288 DFS_SHUFFLE_HW_MODE: ON
9140 12:29:36.265872 dramc_set_vcore_voltage set vcore to 725000
9141 12:29:36.265955 Read voltage for 1600, 0
9142 12:29:36.269029 Vio18 = 0
9143 12:29:36.269140 Vcore = 725000
9144 12:29:36.269244 Vdram = 0
9145 12:29:36.269347 Vddq = 0
9146 12:29:36.272383 Vmddr = 0
9147 12:29:36.272456 switch to 3200 Mbps bootup
9148 12:29:36.275852 [DramcRunTimeConfig]
9149 12:29:36.275977 PHYPLL
9150 12:29:36.279272 DPM_CONTROL_AFTERK: ON
9151 12:29:36.279363 PER_BANK_REFRESH: ON
9152 12:29:36.282611 REFRESH_OVERHEAD_REDUCTION: ON
9153 12:29:36.285802 CMD_PICG_NEW_MODE: OFF
9154 12:29:36.285885 XRTWTW_NEW_MODE: ON
9155 12:29:36.289088 XRTRTR_NEW_MODE: ON
9156 12:29:36.289170 TX_TRACKING: ON
9157 12:29:36.292591 RDSEL_TRACKING: OFF
9158 12:29:36.296096 DQS Precalculation for DVFS: ON
9159 12:29:36.296202 RX_TRACKING: OFF
9160 12:29:36.298829 HW_GATING DBG: ON
9161 12:29:36.298940 ZQCS_ENABLE_LP4: ON
9162 12:29:36.302169 RX_PICG_NEW_MODE: ON
9163 12:29:36.305649 TX_PICG_NEW_MODE: ON
9164 12:29:36.305734 ENABLE_RX_DCM_DPHY: ON
9165 12:29:36.308833 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 12:29:36.312166 DUMMY_READ_FOR_TRACKING: OFF
9167 12:29:36.315514 !!! SPM_CONTROL_AFTERK: OFF
9168 12:29:36.315629 !!! SPM could not control APHY
9169 12:29:36.318699 IMPEDANCE_TRACKING: ON
9170 12:29:36.318801 TEMP_SENSOR: ON
9171 12:29:36.322610 HW_SAVE_FOR_SR: OFF
9172 12:29:36.326108 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 12:29:36.329263 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 12:29:36.332506 Read ODT Tracking: ON
9175 12:29:36.332593 Refresh Rate DeBounce: ON
9176 12:29:36.335819 DFS_NO_QUEUE_FLUSH: ON
9177 12:29:36.339245 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 12:29:36.342482 ENABLE_DFS_RUNTIME_MRW: OFF
9179 12:29:36.342566 DDR_RESERVE_NEW_MODE: ON
9180 12:29:36.345680 MR_CBT_SWITCH_FREQ: ON
9181 12:29:36.348693 =========================
9182 12:29:36.366690 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 12:29:36.369962 dram_init: ddr_geometry: 2
9184 12:29:36.388635 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 12:29:36.391239 dram_init: dram init end (result: 0)
9186 12:29:36.398162 DRAM-K: Full calibration passed in 24620 msecs
9187 12:29:36.401584 MRC: failed to locate region type 0.
9188 12:29:36.401699 DRAM rank0 size:0x100000000,
9189 12:29:36.404859 DRAM rank1 size=0x100000000
9190 12:29:36.414745 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 12:29:36.421552 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 12:29:36.428201 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 12:29:36.434571 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 12:29:36.437713 DRAM rank0 size:0x100000000,
9195 12:29:36.441093 DRAM rank1 size=0x100000000
9196 12:29:36.441182 CBMEM:
9197 12:29:36.444363 IMD: root @ 0xfffff000 254 entries.
9198 12:29:36.447925 IMD: root @ 0xffffec00 62 entries.
9199 12:29:36.451110 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 12:29:36.454363 WARNING: RO_VPD is uninitialized or empty.
9201 12:29:36.460745 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 12:29:36.468027 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 12:29:36.480662 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9204 12:29:36.492062 BS: romstage times (exec / console): total (unknown) / 24116 ms
9205 12:29:36.492154
9206 12:29:36.492226
9207 12:29:36.502306 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 12:29:36.505497 ARM64: Exception handlers installed.
9209 12:29:36.508753 ARM64: Testing exception
9210 12:29:36.512141 ARM64: Done test exception
9211 12:29:36.512249 Enumerating buses...
9212 12:29:36.515514 Show all devs... Before device enumeration.
9213 12:29:36.518964 Root Device: enabled 1
9214 12:29:36.522161 CPU_CLUSTER: 0: enabled 1
9215 12:29:36.522245 CPU: 00: enabled 1
9216 12:29:36.525628 Compare with tree...
9217 12:29:36.525719 Root Device: enabled 1
9218 12:29:36.528927 CPU_CLUSTER: 0: enabled 1
9219 12:29:36.532178 CPU: 00: enabled 1
9220 12:29:36.532275 Root Device scanning...
9221 12:29:36.535346 scan_static_bus for Root Device
9222 12:29:36.539270 CPU_CLUSTER: 0 enabled
9223 12:29:36.542440 scan_static_bus for Root Device done
9224 12:29:36.545791 scan_bus: bus Root Device finished in 8 msecs
9225 12:29:36.545921 done
9226 12:29:36.552285 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 12:29:36.555511 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 12:29:36.562296 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 12:29:36.565427 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 12:29:36.568752 Allocating resources...
9231 12:29:36.572047 Reading resources...
9232 12:29:36.575269 Root Device read_resources bus 0 link: 0
9233 12:29:36.575434 DRAM rank0 size:0x100000000,
9234 12:29:36.578539 DRAM rank1 size=0x100000000
9235 12:29:36.581591 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 12:29:36.584832 CPU: 00 missing read_resources
9237 12:29:36.591995 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 12:29:36.595130 Root Device read_resources bus 0 link: 0 done
9239 12:29:36.595227 Done reading resources.
9240 12:29:36.601827 Show resources in subtree (Root Device)...After reading.
9241 12:29:36.605243 Root Device child on link 0 CPU_CLUSTER: 0
9242 12:29:36.608446 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 12:29:36.618210 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 12:29:36.618298 CPU: 00
9245 12:29:36.621792 Root Device assign_resources, bus 0 link: 0
9246 12:29:36.625010 CPU_CLUSTER: 0 missing set_resources
9247 12:29:36.631465 Root Device assign_resources, bus 0 link: 0 done
9248 12:29:36.631562 Done setting resources.
9249 12:29:36.638023 Show resources in subtree (Root Device)...After assigning values.
9250 12:29:36.641413 Root Device child on link 0 CPU_CLUSTER: 0
9251 12:29:36.644674 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 12:29:36.654532 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 12:29:36.654626 CPU: 00
9254 12:29:36.657867 Done allocating resources.
9255 12:29:36.664703 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 12:29:36.664809 Enabling resources...
9257 12:29:36.664902 done.
9258 12:29:36.671168 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 12:29:36.671271 Initializing devices...
9260 12:29:36.674496 Root Device init
9261 12:29:36.674579 init hardware done!
9262 12:29:36.678394 0x00000018: ctrlr->caps
9263 12:29:36.680985 52.000 MHz: ctrlr->f_max
9264 12:29:36.681071 0.400 MHz: ctrlr->f_min
9265 12:29:36.684353 0x40ff8080: ctrlr->voltages
9266 12:29:36.688052 sclk: 390625
9267 12:29:36.688139 Bus Width = 1
9268 12:29:36.688207 sclk: 390625
9269 12:29:36.691315 Bus Width = 1
9270 12:29:36.691436 Early init status = 3
9271 12:29:36.697860 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 12:29:36.701174 in-header: 03 fc 00 00 01 00 00 00
9273 12:29:36.704667 in-data: 00
9274 12:29:36.707921 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 12:29:36.712717 in-header: 03 fd 00 00 00 00 00 00
9276 12:29:36.716028 in-data:
9277 12:29:36.719197 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 12:29:36.723875 in-header: 03 fc 00 00 01 00 00 00
9279 12:29:36.727164 in-data: 00
9280 12:29:36.730597 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 12:29:36.735917 in-header: 03 fd 00 00 00 00 00 00
9282 12:29:36.739747 in-data:
9283 12:29:36.742740 [SSUSB] Setting up USB HOST controller...
9284 12:29:36.746113 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 12:29:36.749317 [SSUSB] phy power-on done.
9286 12:29:36.752650 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 12:29:36.759056 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 12:29:36.762383 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 12:29:36.769413 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 12:29:36.775985 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 12:29:36.782759 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 12:29:36.789270 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 12:29:36.795699 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 12:29:36.798899 SPM: binary array size = 0x9dc
9295 12:29:36.802158 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 12:29:36.809342 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 12:29:36.815342 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 12:29:36.818748 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 12:29:36.825186 configure_display: Starting display init
9300 12:29:36.859564 anx7625_power_on_init: Init interface.
9301 12:29:36.862428 anx7625_disable_pd_protocol: Disabled PD feature.
9302 12:29:36.865815 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 12:29:36.893351 anx7625_start_dp_work: Secure OCM version=00
9304 12:29:36.896975 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 12:29:36.911537 sp_tx_get_edid_block: EDID Block = 1
9306 12:29:37.014348 Extracted contents:
9307 12:29:37.017583 header: 00 ff ff ff ff ff ff 00
9308 12:29:37.020806 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 12:29:37.024244 version: 01 04
9310 12:29:37.027526 basic params: 95 1f 11 78 0a
9311 12:29:37.030910 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 12:29:37.034180 established: 00 00 00
9313 12:29:37.040394 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 12:29:37.043828 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 12:29:37.050398 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 12:29:37.057129 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 12:29:37.063757 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 12:29:37.067021 extensions: 00
9319 12:29:37.067128 checksum: fb
9320 12:29:37.067226
9321 12:29:37.070361 Manufacturer: IVO Model 57d Serial Number 0
9322 12:29:37.073795 Made week 0 of 2020
9323 12:29:37.073879 EDID version: 1.4
9324 12:29:37.077088 Digital display
9325 12:29:37.080178 6 bits per primary color channel
9326 12:29:37.080257 DisplayPort interface
9327 12:29:37.083920 Maximum image size: 31 cm x 17 cm
9328 12:29:37.087077 Gamma: 220%
9329 12:29:37.087188 Check DPMS levels
9330 12:29:37.090331 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 12:29:37.097035 First detailed timing is preferred timing
9332 12:29:37.097145 Established timings supported:
9333 12:29:37.100071 Standard timings supported:
9334 12:29:37.103904 Detailed timings
9335 12:29:37.107122 Hex of detail: 383680a07038204018303c0035ae10000019
9336 12:29:37.110362 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 12:29:37.116687 0780 0798 07c8 0820 hborder 0
9338 12:29:37.120046 0438 043b 0447 0458 vborder 0
9339 12:29:37.123233 -hsync -vsync
9340 12:29:37.123340 Did detailed timing
9341 12:29:37.129952 Hex of detail: 000000000000000000000000000000000000
9342 12:29:37.133231 Manufacturer-specified data, tag 0
9343 12:29:37.137060 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 12:29:37.140391 ASCII string: InfoVision
9345 12:29:37.143729 Hex of detail: 000000fe00523134304e574635205248200a
9346 12:29:37.146879 ASCII string: R140NWF5 RH
9347 12:29:37.146997 Checksum
9348 12:29:37.150212 Checksum: 0xfb (valid)
9349 12:29:37.153599 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 12:29:37.156771 DSI data_rate: 832800000 bps
9351 12:29:37.163234 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 12:29:37.166385 anx7625_parse_edid: pixelclock(138800).
9353 12:29:37.169667 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 12:29:37.173038 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 12:29:37.176491 anx7625_dsi_config: config dsi.
9356 12:29:37.182955 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 12:29:37.196396 anx7625_dsi_config: success to config DSI
9358 12:29:37.199818 anx7625_dp_start: MIPI phy setup OK.
9359 12:29:37.203133 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 12:29:37.206397 mtk_ddp_mode_set invalid vrefresh 60
9361 12:29:37.209717 main_disp_path_setup
9362 12:29:37.209807 ovl_layer_smi_id_en
9363 12:29:37.213003 ovl_layer_smi_id_en
9364 12:29:37.213088 ccorr_config
9365 12:29:37.213156 aal_config
9366 12:29:37.216408 gamma_config
9367 12:29:37.216492 postmask_config
9368 12:29:37.216560 dither_config
9369 12:29:37.222819 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 12:29:37.229629 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 12:29:37.233016 Root Device init finished in 555 msecs
9372 12:29:37.233101 CPU_CLUSTER: 0 init
9373 12:29:37.242600 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 12:29:37.245983 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 12:29:37.249820 APU_MBOX 0x190000b0 = 0x10001
9376 12:29:37.253167 APU_MBOX 0x190001b0 = 0x10001
9377 12:29:37.255993 APU_MBOX 0x190005b0 = 0x10001
9378 12:29:37.259280 APU_MBOX 0x190006b0 = 0x10001
9379 12:29:37.262721 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 12:29:37.275270 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9381 12:29:37.287789 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 12:29:37.294063 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 12:29:37.306081 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9384 12:29:37.314708 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 12:29:37.318022 CPU_CLUSTER: 0 init finished in 81 msecs
9386 12:29:37.321256 Devices initialized
9387 12:29:37.324623 Show all devs... After init.
9388 12:29:37.324734 Root Device: enabled 1
9389 12:29:37.328008 CPU_CLUSTER: 0: enabled 1
9390 12:29:37.331275 CPU: 00: enabled 1
9391 12:29:37.334583 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9392 12:29:37.338019 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 12:29:37.341381 ELOG: NV offset 0x57f000 size 0x1000
9394 12:29:37.348200 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9395 12:29:37.354821 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 12:29:37.358128 ELOG: Event(17) added with size 13 at 2023-06-06 12:29:48 UTC
9397 12:29:37.364822 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 12:29:37.368225 in-header: 03 a5 00 00 2c 00 00 00
9399 12:29:37.380859 in-data: ba 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 12:29:37.384607 ELOG: Event(A1) added with size 10 at 2023-06-06 12:29:48 UTC
9401 12:29:37.391085 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9402 12:29:37.397559 ELOG: Event(A0) added with size 9 at 2023-06-06 12:29:48 UTC
9403 12:29:37.400638 elog_add_boot_reason: Logged dev mode boot
9404 12:29:37.407275 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9405 12:29:37.407375 Finalize devices...
9406 12:29:37.410554 Devices finalized
9407 12:29:37.414614 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 12:29:37.417273 Writing coreboot table at 0xffe64000
9409 12:29:37.424173 0. 000000000010a000-0000000000113fff: RAMSTAGE
9410 12:29:37.427359 1. 0000000040000000-00000000400fffff: RAM
9411 12:29:37.430587 2. 0000000040100000-000000004032afff: RAMSTAGE
9412 12:29:37.433815 3. 000000004032b000-00000000545fffff: RAM
9413 12:29:37.437199 4. 0000000054600000-000000005465ffff: BL31
9414 12:29:37.444109 5. 0000000054660000-00000000ffe63fff: RAM
9415 12:29:37.447302 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9416 12:29:37.450804 7. 0000000100000000-000000023fffffff: RAM
9417 12:29:37.454106 Passing 5 GPIOs to payload:
9418 12:29:37.457413 NAME | PORT | POLARITY | VALUE
9419 12:29:37.464221 EC in RW | 0x000000aa | low | undefined
9420 12:29:37.467459 EC interrupt | 0x00000005 | low | undefined
9421 12:29:37.474162 TPM interrupt | 0x000000ab | high | undefined
9422 12:29:37.477460 SD card detect | 0x00000011 | high | undefined
9423 12:29:37.480808 speaker enable | 0x00000093 | high | undefined
9424 12:29:37.483613 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9425 12:29:37.487264 in-header: 03 f9 00 00 02 00 00 00
9426 12:29:37.490520 in-data: 02 00
9427 12:29:37.493781 ADC[4]: Raw value=900221 ID=7
9428 12:29:37.497245 ADC[3]: Raw value=213336 ID=1
9429 12:29:37.497331 RAM Code: 0x71
9430 12:29:37.500421 ADC[6]: Raw value=74557 ID=0
9431 12:29:37.503730 ADC[5]: Raw value=211860 ID=1
9432 12:29:37.503842 SKU Code: 0x1
9433 12:29:37.510919 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9434 12:29:37.511032 coreboot table: 964 bytes.
9435 12:29:37.513569 IMD ROOT 0. 0xfffff000 0x00001000
9436 12:29:37.517556 IMD SMALL 1. 0xffffe000 0x00001000
9437 12:29:37.520272 RO MCACHE 2. 0xffffc000 0x00001104
9438 12:29:37.524155 CONSOLE 3. 0xfff7c000 0x00080000
9439 12:29:37.527375 FMAP 4. 0xfff7b000 0x00000452
9440 12:29:37.530841 TIME STAMP 5. 0xfff7a000 0x00000910
9441 12:29:37.533897 VBOOT WORK 6. 0xfff66000 0x00014000
9442 12:29:37.537183 RAMOOPS 7. 0xffe66000 0x00100000
9443 12:29:37.540582 COREBOOT 8. 0xffe64000 0x00002000
9444 12:29:37.543790 IMD small region:
9445 12:29:37.547145 IMD ROOT 0. 0xffffec00 0x00000400
9446 12:29:37.550444 VPD 1. 0xffffeba0 0x0000004c
9447 12:29:37.553777 MMC STATUS 2. 0xffffeb80 0x00000004
9448 12:29:37.557067 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9449 12:29:37.560406 Probing TPM: done!
9450 12:29:37.563724 Connected to device vid:did:rid of 1ae0:0028:00
9451 12:29:37.575047 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9452 12:29:37.578215 Initialized TPM device CR50 revision 0
9453 12:29:37.581576 Checking cr50 for pending updates
9454 12:29:37.585388 Reading cr50 TPM mode
9455 12:29:37.594260 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9456 12:29:37.600841 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9457 12:29:37.640762 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9458 12:29:37.644408 Checking segment from ROM address 0x40100000
9459 12:29:37.647186 Checking segment from ROM address 0x4010001c
9460 12:29:37.654411 Loading segment from ROM address 0x40100000
9461 12:29:37.654497 code (compression=0)
9462 12:29:37.664406 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9463 12:29:37.671055 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9464 12:29:37.671141 it's not compressed!
9465 12:29:37.677740 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9466 12:29:37.681034 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9467 12:29:37.701509 Loading segment from ROM address 0x4010001c
9468 12:29:37.701604 Entry Point 0x80000000
9469 12:29:37.704739 Loaded segments
9470 12:29:37.707719 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9471 12:29:37.714409 Jumping to boot code at 0x80000000(0xffe64000)
9472 12:29:37.720758 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9473 12:29:37.727552 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9474 12:29:37.735440 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9475 12:29:37.738755 Checking segment from ROM address 0x40100000
9476 12:29:37.741998 Checking segment from ROM address 0x4010001c
9477 12:29:37.749264 Loading segment from ROM address 0x40100000
9478 12:29:37.749347 code (compression=1)
9479 12:29:37.755986 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9480 12:29:37.765835 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9481 12:29:37.765948 using LZMA
9482 12:29:37.773852 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9483 12:29:37.780554 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9484 12:29:37.783805 Loading segment from ROM address 0x4010001c
9485 12:29:37.783915 Entry Point 0x54601000
9486 12:29:37.787066 Loaded segments
9487 12:29:37.790315 NOTICE: MT8192 bl31_setup
9488 12:29:37.797933 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9489 12:29:37.801237 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9490 12:29:37.804630 WARNING: region 0:
9491 12:29:37.807831 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 12:29:37.807914 WARNING: region 1:
9493 12:29:37.814240 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9494 12:29:37.817802 WARNING: region 2:
9495 12:29:37.820855 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9496 12:29:37.823896 WARNING: region 3:
9497 12:29:37.827855 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 12:29:37.831110 WARNING: region 4:
9499 12:29:37.837804 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 12:29:37.837892 WARNING: region 5:
9501 12:29:37.840886 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 12:29:37.844255 WARNING: region 6:
9503 12:29:37.847515 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 12:29:37.850733 WARNING: region 7:
9505 12:29:37.854143 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 12:29:37.860912 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9507 12:29:37.864182 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9508 12:29:37.867513 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9509 12:29:37.874109 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9510 12:29:37.877428 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9511 12:29:37.880820 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9512 12:29:37.887517 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9513 12:29:37.890831 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9514 12:29:37.897764 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9515 12:29:37.900983 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9516 12:29:37.904175 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9517 12:29:37.910760 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9518 12:29:37.914080 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9519 12:29:37.917394 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9520 12:29:37.924264 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9521 12:29:37.927381 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9522 12:29:37.933963 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9523 12:29:37.937344 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9524 12:29:37.940612 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9525 12:29:37.947795 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9526 12:29:37.951030 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9527 12:29:37.954356 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9528 12:29:37.961073 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9529 12:29:37.964371 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9530 12:29:37.970553 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9531 12:29:37.973806 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9532 12:29:37.977825 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9533 12:29:37.984423 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9534 12:29:37.988021 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9535 12:29:37.994401 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9536 12:29:37.997769 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9537 12:29:38.000887 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9538 12:29:38.007839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9539 12:29:38.011140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9540 12:29:38.014490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9541 12:29:38.017741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9542 12:29:38.020962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9543 12:29:38.027568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9544 12:29:38.031277 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9545 12:29:38.034400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9546 12:29:38.038144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9547 12:29:38.044810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9548 12:29:38.048029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9549 12:29:38.051252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9550 12:29:38.058191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9551 12:29:38.061566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9552 12:29:38.064850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9553 12:29:38.068070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9554 12:29:38.074654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9555 12:29:38.077986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9556 12:29:38.084589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9557 12:29:38.087937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9558 12:29:38.091235 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9559 12:29:38.097839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9560 12:29:38.101675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9561 12:29:38.108170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9562 12:29:38.111320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9563 12:29:38.117645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9564 12:29:38.121157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9565 12:29:38.124550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9566 12:29:38.131042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9567 12:29:38.134365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9568 12:29:38.140970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9569 12:29:38.144611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9570 12:29:38.151024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9571 12:29:38.154266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9572 12:29:38.157498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9573 12:29:38.164582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9574 12:29:38.167774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9575 12:29:38.174542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9576 12:29:38.177763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9577 12:29:38.184450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9578 12:29:38.187802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9579 12:29:38.191177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9580 12:29:38.197791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9581 12:29:38.201075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9582 12:29:38.208155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9583 12:29:38.211368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9584 12:29:38.217994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9585 12:29:38.221129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9586 12:29:38.224334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9587 12:29:38.231006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9588 12:29:38.234247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9589 12:29:38.241520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9590 12:29:38.244150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9591 12:29:38.250916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9592 12:29:38.254718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9593 12:29:38.257930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9594 12:29:38.264481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9595 12:29:38.267768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9596 12:29:38.274269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9597 12:29:38.277597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9598 12:29:38.284252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9599 12:29:38.287513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9600 12:29:38.294738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9601 12:29:38.298077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9602 12:29:38.300725 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9603 12:29:38.304097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9604 12:29:38.310730 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9605 12:29:38.314566 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9606 12:29:38.317743 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9607 12:29:38.324183 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9608 12:29:38.327513 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9609 12:29:38.330765 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9610 12:29:38.338139 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9611 12:29:38.341380 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9612 12:29:38.348008 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9613 12:29:38.351182 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9614 12:29:38.354264 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9615 12:29:38.360923 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9616 12:29:38.364753 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9617 12:29:38.371165 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9618 12:29:38.374373 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9619 12:29:38.377569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9620 12:29:38.384229 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9621 12:29:38.387611 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9622 12:29:38.390962 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9623 12:29:38.397694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9624 12:29:38.401528 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9625 12:29:38.404178 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9626 12:29:38.410773 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9627 12:29:38.414619 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9628 12:29:38.417884 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9629 12:29:38.421046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9630 12:29:38.427722 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9631 12:29:38.430872 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9632 12:29:38.434272 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9633 12:29:38.440819 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9634 12:29:38.444139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9635 12:29:38.450698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9636 12:29:38.454058 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9637 12:29:38.458005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9638 12:29:38.463993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9639 12:29:38.467811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9640 12:29:38.474145 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9641 12:29:38.477473 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9642 12:29:38.481174 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9643 12:29:38.487236 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9644 12:29:38.490674 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9645 12:29:38.493985 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9646 12:29:38.500834 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9647 12:29:38.504062 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9648 12:29:38.510841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9649 12:29:38.514209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9650 12:29:38.517689 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9651 12:29:38.524044 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9652 12:29:38.527205 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9653 12:29:38.534313 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9654 12:29:38.537418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9655 12:29:38.540789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9656 12:29:38.547502 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9657 12:29:38.550777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9658 12:29:38.557448 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9659 12:29:38.560919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9660 12:29:38.564214 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9661 12:29:38.570400 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9662 12:29:38.574131 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9663 12:29:38.577552 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9664 12:29:38.584364 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9665 12:29:38.587418 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9666 12:29:38.593853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9667 12:29:38.597173 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9668 12:29:38.600426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9669 12:29:38.607114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9670 12:29:38.610426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9671 12:29:38.616986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9672 12:29:38.620390 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9673 12:29:38.624252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9674 12:29:38.630616 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9675 12:29:38.633976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9676 12:29:38.640717 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9677 12:29:38.644132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9678 12:29:38.646819 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9679 12:29:38.654081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9680 12:29:38.657403 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9681 12:29:38.660693 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9682 12:29:38.666794 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9683 12:29:38.670095 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9684 12:29:38.677183 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9685 12:29:38.680135 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9686 12:29:38.683388 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9687 12:29:38.690240 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9688 12:29:38.693641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9689 12:29:38.699795 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9690 12:29:38.703753 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9691 12:29:38.707087 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9692 12:29:38.713167 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9693 12:29:38.716335 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9694 12:29:38.723541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9695 12:29:38.726961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9696 12:29:38.733367 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9697 12:29:38.736648 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9698 12:29:38.739924 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9699 12:29:38.746426 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9700 12:29:38.749791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9701 12:29:38.756418 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9702 12:29:38.759728 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9703 12:29:38.762936 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9704 12:29:38.769395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9705 12:29:38.772816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9706 12:29:38.779990 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9707 12:29:38.783182 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9708 12:29:38.789394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9709 12:29:38.793024 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9710 12:29:38.796072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9711 12:29:38.802981 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9712 12:29:38.806115 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9713 12:29:38.812908 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9714 12:29:38.816172 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9715 12:29:38.819444 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9716 12:29:38.826077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9717 12:29:38.829469 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9718 12:29:38.836015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9719 12:29:38.839234 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9720 12:29:38.846210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9721 12:29:38.849324 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9722 12:29:38.852435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9723 12:29:38.859188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9724 12:29:38.862446 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9725 12:29:38.869152 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9726 12:29:38.872545 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9727 12:29:38.875913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9728 12:29:38.882405 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9729 12:29:38.885404 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9730 12:29:38.892216 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9731 12:29:38.895911 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9732 12:29:38.902336 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9733 12:29:38.905574 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9734 12:29:38.908696 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9735 12:29:38.915796 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9736 12:29:38.918942 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9737 12:29:38.922134 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9738 12:29:38.925453 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9739 12:29:38.928855 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9740 12:29:38.935450 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9741 12:29:38.938882 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9742 12:29:38.945308 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9743 12:29:38.949137 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9744 12:29:38.952437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9745 12:29:38.958764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9746 12:29:38.962050 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9747 12:29:38.968789 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9748 12:29:38.972200 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9749 12:29:38.975414 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9750 12:29:38.982054 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9751 12:29:38.985391 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9752 12:29:38.988660 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9753 12:29:38.995377 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9754 12:29:38.998551 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9755 12:29:39.001630 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9756 12:29:39.008579 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9757 12:29:39.011837 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9758 12:29:39.018444 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9759 12:29:39.021750 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9760 12:29:39.025100 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9761 12:29:39.031571 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9762 12:29:39.034756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9763 12:29:39.038031 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9764 12:29:39.044765 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9765 12:29:39.048106 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9766 12:29:39.051841 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9767 12:29:39.058403 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9768 12:29:39.061387 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9769 12:29:39.064699 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9770 12:29:39.071471 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9771 12:29:39.074830 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9772 12:29:39.081595 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9773 12:29:39.084931 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9774 12:29:39.088301 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9775 12:29:39.094780 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9776 12:29:39.098085 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9777 12:29:39.101213 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9778 12:29:39.104482 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9779 12:29:39.107704 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9780 12:29:39.114555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9781 12:29:39.118026 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9782 12:29:39.121188 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9783 12:29:39.124450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9784 12:29:39.131134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9785 12:29:39.134321 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9786 12:29:39.137682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9787 12:29:39.144491 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9788 12:29:39.147866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9789 12:29:39.151025 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9790 12:29:39.157921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9791 12:29:39.161082 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9792 12:29:39.167625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9793 12:29:39.171413 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9794 12:29:39.174794 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9795 12:29:39.180733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9796 12:29:39.184115 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9797 12:29:39.190789 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9798 12:29:39.194034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9799 12:29:39.197373 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9800 12:29:39.204367 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9801 12:29:39.207449 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9802 12:29:39.214332 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9803 12:29:39.217400 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9804 12:29:39.220705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9805 12:29:39.227869 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9806 12:29:39.231143 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9807 12:29:39.237776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9808 12:29:39.241026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9809 12:29:39.247830 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9810 12:29:39.251126 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9811 12:29:39.254431 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9812 12:29:39.261490 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9813 12:29:39.264535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9814 12:29:39.271064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9815 12:29:39.274100 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9816 12:29:39.277628 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9817 12:29:39.284313 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9818 12:29:39.287490 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9819 12:29:39.294060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9820 12:29:39.297511 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9821 12:29:39.300812 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9822 12:29:39.307482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9823 12:29:39.310759 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9824 12:29:39.317734 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9825 12:29:39.320812 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9826 12:29:39.327631 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9827 12:29:39.330758 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9828 12:29:39.334110 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9829 12:29:39.340670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9830 12:29:39.343801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9831 12:29:39.351156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9832 12:29:39.354489 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9833 12:29:39.357765 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9834 12:29:39.364289 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9835 12:29:39.367320 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9836 12:29:39.373723 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9837 12:29:39.376965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9838 12:29:39.380210 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9839 12:29:39.387020 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9840 12:29:39.390107 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9841 12:29:39.396733 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9842 12:29:39.400108 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9843 12:29:39.403413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9844 12:29:39.410071 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9845 12:29:39.413238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9846 12:29:39.420544 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9847 12:29:39.423660 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9848 12:29:39.429857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9849 12:29:39.433473 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9850 12:29:39.436449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9851 12:29:39.443470 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9852 12:29:39.446559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9853 12:29:39.453597 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9854 12:29:39.456685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9855 12:29:39.460499 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9856 12:29:39.466302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9857 12:29:39.469678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9858 12:29:39.476831 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9859 12:29:39.480056 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9860 12:29:39.483109 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9861 12:29:39.489682 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9862 12:29:39.493166 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9863 12:29:39.499844 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9864 12:29:39.503103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9865 12:29:39.509626 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9866 12:29:39.512929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9867 12:29:39.516452 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9868 12:29:39.523067 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9869 12:29:39.526017 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9870 12:29:39.532174 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9871 12:29:39.536069 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9872 12:29:39.542237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9873 12:29:39.546104 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9874 12:29:39.552538 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9875 12:29:39.555914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9876 12:29:39.559155 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9877 12:29:39.565536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9878 12:29:39.568895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9879 12:29:39.575664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9880 12:29:39.578746 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9881 12:29:39.585177 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9882 12:29:39.588517 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9883 12:29:39.595159 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9884 12:29:39.598318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9885 12:29:39.601561 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9886 12:29:39.608338 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9887 12:29:39.611529 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9888 12:29:39.618153 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9889 12:29:39.622264 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9890 12:29:39.628812 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9891 12:29:39.632169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9892 12:29:39.635214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9893 12:29:39.641856 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9894 12:29:39.644991 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9895 12:29:39.651747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9896 12:29:39.655036 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9897 12:29:39.662446 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9898 12:29:39.665593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9899 12:29:39.668846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9900 12:29:39.675271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9901 12:29:39.678751 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9902 12:29:39.685218 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9903 12:29:39.688372 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9904 12:29:39.694945 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9905 12:29:39.698203 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9906 12:29:39.704809 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9907 12:29:39.708032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9908 12:29:39.712054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9909 12:29:39.718031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9910 12:29:39.721317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9911 12:29:39.728029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9912 12:29:39.731508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9913 12:29:39.738105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9914 12:29:39.741218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9915 12:29:39.748078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9916 12:29:39.751384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9917 12:29:39.755053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9918 12:29:39.761541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9919 12:29:39.764684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9920 12:29:39.771270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9921 12:29:39.774662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9922 12:29:39.781134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9923 12:29:39.784462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9924 12:29:39.791577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9925 12:29:39.794804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9926 12:29:39.801556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9927 12:29:39.805314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9928 12:29:39.811883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9929 12:29:39.815212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9930 12:29:39.821892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9931 12:29:39.825134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9932 12:29:39.831541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9933 12:29:39.835017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9934 12:29:39.841428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9935 12:29:39.844938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9936 12:29:39.850965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9937 12:29:39.854860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9938 12:29:39.861199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9939 12:29:39.864449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9940 12:29:39.870907 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9941 12:29:39.871332 INFO: [APUAPC] vio 0
9942 12:29:39.878234 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9943 12:29:39.881586 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9944 12:29:39.884949 INFO: [APUAPC] D0_APC_0: 0x400510
9945 12:29:39.888013 INFO: [APUAPC] D0_APC_1: 0x0
9946 12:29:39.891256 INFO: [APUAPC] D0_APC_2: 0x1540
9947 12:29:39.894613 INFO: [APUAPC] D0_APC_3: 0x0
9948 12:29:39.897881 INFO: [APUAPC] D1_APC_0: 0xffffffff
9949 12:29:39.901167 INFO: [APUAPC] D1_APC_1: 0xffffffff
9950 12:29:39.904477 INFO: [APUAPC] D1_APC_2: 0x3fffff
9951 12:29:39.907752 INFO: [APUAPC] D1_APC_3: 0x0
9952 12:29:39.910956 INFO: [APUAPC] D2_APC_0: 0xffffffff
9953 12:29:39.914317 INFO: [APUAPC] D2_APC_1: 0xffffffff
9954 12:29:39.917684 INFO: [APUAPC] D2_APC_2: 0x3fffff
9955 12:29:39.920896 INFO: [APUAPC] D2_APC_3: 0x0
9956 12:29:39.924238 INFO: [APUAPC] D3_APC_0: 0xffffffff
9957 12:29:39.928119 INFO: [APUAPC] D3_APC_1: 0xffffffff
9958 12:29:39.931400 INFO: [APUAPC] D3_APC_2: 0x3fffff
9959 12:29:39.934702 INFO: [APUAPC] D3_APC_3: 0x0
9960 12:29:39.937452 INFO: [APUAPC] D4_APC_0: 0xffffffff
9961 12:29:39.940813 INFO: [APUAPC] D4_APC_1: 0xffffffff
9962 12:29:39.944115 INFO: [APUAPC] D4_APC_2: 0x3fffff
9963 12:29:39.944568 INFO: [APUAPC] D4_APC_3: 0x0
9964 12:29:39.947409 INFO: [APUAPC] D5_APC_0: 0xffffffff
9965 12:29:39.954888 INFO: [APUAPC] D5_APC_1: 0xffffffff
9966 12:29:39.955570 INFO: [APUAPC] D5_APC_2: 0x3fffff
9967 12:29:39.957711 INFO: [APUAPC] D5_APC_3: 0x0
9968 12:29:39.960836 INFO: [APUAPC] D6_APC_0: 0xffffffff
9969 12:29:39.963995 INFO: [APUAPC] D6_APC_1: 0xffffffff
9970 12:29:39.967738 INFO: [APUAPC] D6_APC_2: 0x3fffff
9971 12:29:39.971006 INFO: [APUAPC] D6_APC_3: 0x0
9972 12:29:39.974126 INFO: [APUAPC] D7_APC_0: 0xffffffff
9973 12:29:39.977451 INFO: [APUAPC] D7_APC_1: 0xffffffff
9974 12:29:39.980729 INFO: [APUAPC] D7_APC_2: 0x3fffff
9975 12:29:39.984145 INFO: [APUAPC] D7_APC_3: 0x0
9976 12:29:39.987375 INFO: [APUAPC] D8_APC_0: 0xffffffff
9977 12:29:39.990467 INFO: [APUAPC] D8_APC_1: 0xffffffff
9978 12:29:39.993891 INFO: [APUAPC] D8_APC_2: 0x3fffff
9979 12:29:39.997728 INFO: [APUAPC] D8_APC_3: 0x0
9980 12:29:40.000923 INFO: [APUAPC] D9_APC_0: 0xffffffff
9981 12:29:40.004127 INFO: [APUAPC] D9_APC_1: 0xffffffff
9982 12:29:40.007487 INFO: [APUAPC] D9_APC_2: 0x3fffff
9983 12:29:40.010768 INFO: [APUAPC] D9_APC_3: 0x0
9984 12:29:40.014143 INFO: [APUAPC] D10_APC_0: 0xffffffff
9985 12:29:40.017414 INFO: [APUAPC] D10_APC_1: 0xffffffff
9986 12:29:40.020870 INFO: [APUAPC] D10_APC_2: 0x3fffff
9987 12:29:40.024205 INFO: [APUAPC] D10_APC_3: 0x0
9988 12:29:40.027583 INFO: [APUAPC] D11_APC_0: 0xffffffff
9989 12:29:40.030887 INFO: [APUAPC] D11_APC_1: 0xffffffff
9990 12:29:40.034178 INFO: [APUAPC] D11_APC_2: 0x3fffff
9991 12:29:40.037460 INFO: [APUAPC] D11_APC_3: 0x0
9992 12:29:40.040779 INFO: [APUAPC] D12_APC_0: 0xffffffff
9993 12:29:40.044157 INFO: [APUAPC] D12_APC_1: 0xffffffff
9994 12:29:40.047387 INFO: [APUAPC] D12_APC_2: 0x3fffff
9995 12:29:40.050644 INFO: [APUAPC] D12_APC_3: 0x0
9996 12:29:40.053909 INFO: [APUAPC] D13_APC_0: 0xffffffff
9997 12:29:40.057145 INFO: [APUAPC] D13_APC_1: 0xffffffff
9998 12:29:40.060928 INFO: [APUAPC] D13_APC_2: 0x3fffff
9999 12:29:40.064172 INFO: [APUAPC] D13_APC_3: 0x0
10000 12:29:40.067314 INFO: [APUAPC] D14_APC_0: 0xffffffff
10001 12:29:40.070345 INFO: [APUAPC] D14_APC_1: 0xffffffff
10002 12:29:40.073521 INFO: [APUAPC] D14_APC_2: 0x3fffff
10003 12:29:40.077442 INFO: [APUAPC] D14_APC_3: 0x0
10004 12:29:40.080796 INFO: [APUAPC] D15_APC_0: 0xffffffff
10005 12:29:40.083978 INFO: [APUAPC] D15_APC_1: 0xffffffff
10006 12:29:40.087433 INFO: [APUAPC] D15_APC_2: 0x3fffff
10007 12:29:40.090678 INFO: [APUAPC] D15_APC_3: 0x0
10008 12:29:40.094057 INFO: [APUAPC] APC_CON: 0x4
10009 12:29:40.097432 INFO: [NOCDAPC] D0_APC_0: 0x0
10010 12:29:40.100706 INFO: [NOCDAPC] D0_APC_1: 0x0
10011 12:29:40.104057 INFO: [NOCDAPC] D1_APC_0: 0x0
10012 12:29:40.107211 INFO: [NOCDAPC] D1_APC_1: 0xfff
10013 12:29:40.107869 INFO: [NOCDAPC] D2_APC_0: 0x0
10014 12:29:40.110495 INFO: [NOCDAPC] D2_APC_1: 0xfff
10015 12:29:40.113693 INFO: [NOCDAPC] D3_APC_0: 0x0
10016 12:29:40.116950 INFO: [NOCDAPC] D3_APC_1: 0xfff
10017 12:29:40.120241 INFO: [NOCDAPC] D4_APC_0: 0x0
10018 12:29:40.124182 INFO: [NOCDAPC] D4_APC_1: 0xfff
10019 12:29:40.126790 INFO: [NOCDAPC] D5_APC_0: 0x0
10020 12:29:40.130100 INFO: [NOCDAPC] D5_APC_1: 0xfff
10021 12:29:40.133487 INFO: [NOCDAPC] D6_APC_0: 0x0
10022 12:29:40.136738 INFO: [NOCDAPC] D6_APC_1: 0xfff
10023 12:29:40.140237 INFO: [NOCDAPC] D7_APC_0: 0x0
10024 12:29:40.140682 INFO: [NOCDAPC] D7_APC_1: 0xfff
10025 12:29:40.143755 INFO: [NOCDAPC] D8_APC_0: 0x0
10026 12:29:40.147065 INFO: [NOCDAPC] D8_APC_1: 0xfff
10027 12:29:40.150356 INFO: [NOCDAPC] D9_APC_0: 0x0
10028 12:29:40.153617 INFO: [NOCDAPC] D9_APC_1: 0xfff
10029 12:29:40.156880 INFO: [NOCDAPC] D10_APC_0: 0x0
10030 12:29:40.160065 INFO: [NOCDAPC] D10_APC_1: 0xfff
10031 12:29:40.163234 INFO: [NOCDAPC] D11_APC_0: 0x0
10032 12:29:40.167002 INFO: [NOCDAPC] D11_APC_1: 0xfff
10033 12:29:40.169901 INFO: [NOCDAPC] D12_APC_0: 0x0
10034 12:29:40.173246 INFO: [NOCDAPC] D12_APC_1: 0xfff
10035 12:29:40.176989 INFO: [NOCDAPC] D13_APC_0: 0x0
10036 12:29:40.180312 INFO: [NOCDAPC] D13_APC_1: 0xfff
10037 12:29:40.183702 INFO: [NOCDAPC] D14_APC_0: 0x0
10038 12:29:40.184198 INFO: [NOCDAPC] D14_APC_1: 0xfff
10039 12:29:40.186728 INFO: [NOCDAPC] D15_APC_0: 0x0
10040 12:29:40.190057 INFO: [NOCDAPC] D15_APC_1: 0xfff
10041 12:29:40.193295 INFO: [NOCDAPC] APC_CON: 0x4
10042 12:29:40.196561 INFO: [APUAPC] set_apusys_apc done
10043 12:29:40.199891 INFO: [DEVAPC] devapc_init done
10044 12:29:40.203019 INFO: GICv3 without legacy support detected.
10045 12:29:40.209674 INFO: ARM GICv3 driver initialized in EL3
10046 12:29:40.213064 INFO: Maximum SPI INTID supported: 639
10047 12:29:40.216657 INFO: BL31: Initializing runtime services
10048 12:29:40.223500 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10049 12:29:40.223997 INFO: SPM: enable CPC mode
10050 12:29:40.229998 INFO: mcdi ready for mcusys-off-idle and system suspend
10051 12:29:40.233318 INFO: BL31: Preparing for EL3 exit to normal world
10052 12:29:40.239817 INFO: Entry point address = 0x80000000
10053 12:29:40.240385 INFO: SPSR = 0x8
10054 12:29:40.245840
10055 12:29:40.246389
10056 12:29:40.246866
10057 12:29:40.249210 Starting depthcharge on Spherion...
10058 12:29:40.249757
10059 12:29:40.250254 Wipe memory regions:
10060 12:29:40.250594
10061 12:29:40.253285 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10062 12:29:40.253799 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10063 12:29:40.254392 Setting prompt string to ['asurada:']
10064 12:29:40.254826 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10065 12:29:40.255629 [0x00000040000000, 0x00000054600000)
10066 12:29:40.375280
10067 12:29:40.376027 [0x00000054660000, 0x00000080000000)
10068 12:29:40.634709
10069 12:29:40.634893 [0x000000821a7280, 0x000000ffe64000)
10070 12:29:41.378482
10071 12:29:41.378680 [0x00000100000000, 0x00000240000000)
10072 12:29:43.266540
10073 12:29:43.269550 Initializing XHCI USB controller at 0x11200000.
10074 12:29:44.307614
10075 12:29:44.310807 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10076 12:29:44.311432
10077 12:29:44.311877
10078 12:29:44.312317
10079 12:29:44.313244 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 12:29:44.414253 asurada: tftpboot 192.168.201.1 10605794/tftp-deploy-_yyx4mc8/kernel/image.itb 10605794/tftp-deploy-_yyx4mc8/kernel/cmdline
10082 12:29:44.414431 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 12:29:44.414578 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10084 12:29:44.419082 tftpboot 192.168.201.1 10605794/tftp-deploy-_yyx4mc8/kernel/image.itp-deploy-_yyx4mc8/kernel/cmdline
10085 12:29:44.419190
10086 12:29:44.419283 Waiting for link
10087 12:29:44.579818
10088 12:29:44.580448 R8152: Initializing
10089 12:29:44.580941
10090 12:29:44.582906 Version 6 (ocp_data = 5c30)
10091 12:29:44.583458
10092 12:29:44.586171 R8152: Done initializing
10093 12:29:44.586732
10094 12:29:44.587226 Adding net device
10095 12:29:46.627681
10096 12:29:46.628393 done.
10097 12:29:46.629049
10098 12:29:46.629389 MAC: 00:24:32:30:78:52
10099 12:29:46.629810
10100 12:29:46.631103 Sending DHCP discover... done.
10101 12:29:46.631610
10102 12:29:46.634527 Waiting for reply... done.
10103 12:29:46.635058
10104 12:29:46.637856 Sending DHCP request... done.
10105 12:29:46.638494
10106 12:29:46.647476 Waiting for reply... done.
10107 12:29:46.648116
10108 12:29:46.648769 My ip is 192.168.201.14
10109 12:29:46.649441
10110 12:29:46.650519 The DHCP server ip is 192.168.201.1
10111 12:29:46.650906
10112 12:29:46.657531 TFTP server IP predefined by user: 192.168.201.1
10113 12:29:46.658171
10114 12:29:46.664016 Bootfile predefined by user: 10605794/tftp-deploy-_yyx4mc8/kernel/image.itb
10115 12:29:46.664593
10116 12:29:46.665185 Sending tftp read request... done.
10117 12:29:46.667714
10118 12:29:46.672909 Waiting for the transfer...
10119 12:29:46.673465
10120 12:29:47.260768 00000000 ################################################################
10121 12:29:47.260914
10122 12:29:47.796642 00080000 ################################################################
10123 12:29:47.796788
10124 12:29:48.345578 00100000 ################################################################
10125 12:29:48.346075
10126 12:29:48.902574 00180000 ################################################################
10127 12:29:48.902747
10128 12:29:49.444227 00200000 ################################################################
10129 12:29:49.444400
10130 12:29:49.984374 00280000 ################################################################
10131 12:29:49.984522
10132 12:29:50.524610 00300000 ################################################################
10133 12:29:50.524761
10134 12:29:51.081817 00380000 ################################################################
10135 12:29:51.081970
10136 12:29:51.621378 00400000 ################################################################
10137 12:29:51.621516
10138 12:29:52.167723 00480000 ################################################################
10139 12:29:52.167859
10140 12:29:52.699123 00500000 ################################################################
10141 12:29:52.699288
10142 12:29:53.237026 00580000 ################################################################
10143 12:29:53.237159
10144 12:29:53.772528 00600000 ################################################################
10145 12:29:53.772672
10146 12:29:54.316791 00680000 ################################################################
10147 12:29:54.316935
10148 12:29:54.866167 00700000 ################################################################
10149 12:29:54.866304
10150 12:29:55.416381 00780000 ################################################################
10151 12:29:55.416523
10152 12:29:55.950484 00800000 ################################################################
10153 12:29:55.950637
10154 12:29:56.480876 00880000 ################################################################
10155 12:29:56.481016
10156 12:29:57.028486 00900000 ################################################################
10157 12:29:57.028643
10158 12:29:57.589628 00980000 ################################################################
10159 12:29:57.589779
10160 12:29:58.257286 00a00000 ################################################################
10161 12:29:58.257465
10162 12:29:58.914104 00a80000 ################################################################
10163 12:29:58.914269
10164 12:29:59.446963 00b00000 ################################################################
10165 12:29:59.447104
10166 12:29:59.990396 00b80000 ################################################################
10167 12:29:59.990566
10168 12:30:00.553897 00c00000 ################################################################
10169 12:30:00.554070
10170 12:30:01.117480 00c80000 ################################################################
10171 12:30:01.117651
10172 12:30:01.673711 00d00000 ################################################################
10173 12:30:01.673869
10174 12:30:02.222999 00d80000 ################################################################
10175 12:30:02.223171
10176 12:30:02.756987 00e00000 ################################################################
10177 12:30:02.757220
10178 12:30:03.310209 00e80000 ################################################################
10179 12:30:03.310359
10180 12:30:03.911907 00f00000 ################################################################
10181 12:30:03.912044
10182 12:30:04.464130 00f80000 ################################################################
10183 12:30:04.464278
10184 12:30:05.017430 01000000 ################################################################
10185 12:30:05.017584
10186 12:30:05.568031 01080000 ################################################################
10187 12:30:05.568184
10188 12:30:06.160938 01100000 ################################################################
10189 12:30:06.161087
10190 12:30:06.760059 01180000 ################################################################
10191 12:30:06.760275
10192 12:30:07.365870 01200000 ################################################################
10193 12:30:07.366022
10194 12:30:07.972479 01280000 ################################################################
10195 12:30:07.972630
10196 12:30:08.527581 01300000 ################################################################
10197 12:30:08.527735
10198 12:30:09.085303 01380000 ################################################################
10199 12:30:09.085452
10200 12:30:09.662924 01400000 ################################################################
10201 12:30:09.663093
10202 12:30:10.234306 01480000 ################################################################
10203 12:30:10.234454
10204 12:30:10.789514 01500000 ################################################################
10205 12:30:10.789936
10206 12:30:11.335016 01580000 ################################################################
10207 12:30:11.335196
10208 12:30:11.968644 01600000 ################################################################
10209 12:30:11.968831
10210 12:30:12.522893 01680000 ################################################################
10211 12:30:12.523052
10212 12:30:13.087582 01700000 ################################################################
10213 12:30:13.087744
10214 12:30:13.627545 01780000 ################################################################
10215 12:30:13.627696
10216 12:30:14.170843 01800000 ################################################################
10217 12:30:14.171042
10218 12:30:14.733762 01880000 ################################################################
10219 12:30:14.733911
10220 12:30:15.279968 01900000 ################################################################
10221 12:30:15.280123
10222 12:30:15.823691 01980000 ################################################################
10223 12:30:15.823833
10224 12:30:16.363254 01a00000 ################################################################
10225 12:30:16.363451
10226 12:30:16.904937 01a80000 ################################################################
10227 12:30:16.905072
10228 12:30:17.448607 01b00000 ################################################################
10229 12:30:17.448762
10230 12:30:17.995333 01b80000 ################################################################
10231 12:30:17.995515
10232 12:30:18.540891 01c00000 ################################################################
10233 12:30:18.541036
10234 12:30:19.106142 01c80000 ################################################################
10235 12:30:19.106295
10236 12:30:19.651036 01d00000 ################################################################
10237 12:30:19.651174
10238 12:30:20.185381 01d80000 ################################################################
10239 12:30:20.185543
10240 12:30:20.744820 01e00000 ################################################################
10241 12:30:20.744962
10242 12:30:21.281659 01e80000 ################################################################
10243 12:30:21.281831
10244 12:30:21.821579 01f00000 ################################################################
10245 12:30:21.821736
10246 12:30:22.346802 01f80000 ################################################################
10247 12:30:22.346980
10248 12:30:22.892157 02000000 ################################################################
10249 12:30:22.892330
10250 12:30:23.430550 02080000 ################################################################
10251 12:30:23.430694
10252 12:30:23.966480 02100000 ################################################################
10253 12:30:23.966640
10254 12:30:24.493504 02180000 ################################################################
10255 12:30:24.493648
10256 12:30:25.030262 02200000 ################################################################
10257 12:30:25.030439
10258 12:30:25.577782 02280000 ################################################################
10259 12:30:25.577939
10260 12:30:26.111068 02300000 ################################################################
10261 12:30:26.111246
10262 12:30:26.642983 02380000 ################################################################
10263 12:30:26.643138
10264 12:30:27.190477 02400000 ################################################################
10265 12:30:27.191431
10266 12:30:27.745361 02480000 ################################################################
10267 12:30:27.745513
10268 12:30:28.282397 02500000 ################################################################
10269 12:30:28.282547
10270 12:30:28.826371 02580000 ################################################################
10271 12:30:28.826514
10272 12:30:29.382569 02600000 ################################################################
10273 12:30:29.382721
10274 12:30:29.922764 02680000 ################################################################
10275 12:30:29.922911
10276 12:30:30.481271 02700000 ################################################################
10277 12:30:30.481422
10278 12:30:31.030710 02780000 ################################################################
10279 12:30:31.030925
10280 12:30:31.585462 02800000 ################################################################
10281 12:30:31.585645
10282 12:30:32.117282 02880000 ################################################################
10283 12:30:32.117436
10284 12:30:32.663073 02900000 ################################################################
10285 12:30:32.663242
10286 12:30:33.198215 02980000 ################################################################
10287 12:30:33.198365
10288 12:30:33.737368 02a00000 ################################################################
10289 12:30:33.737522
10290 12:30:34.279685 02a80000 ################################################################
10291 12:30:34.279870
10292 12:30:34.813757 02b00000 ################################################################
10293 12:30:34.813943
10294 12:30:35.342606 02b80000 ################################################################
10295 12:30:35.342759
10296 12:30:35.892362 02c00000 ################################################################
10297 12:30:35.892531
10298 12:30:36.431946 02c80000 ################################################################
10299 12:30:36.432106
10300 12:30:36.959164 02d00000 ################################################################
10301 12:30:36.959345
10302 12:30:37.485147 02d80000 ################################################################
10303 12:30:37.485304
10304 12:30:38.015816 02e00000 ################################################################
10305 12:30:38.015974
10306 12:30:38.551889 02e80000 ################################################################
10307 12:30:38.552103
10308 12:30:39.095122 02f00000 ################################################################
10309 12:30:39.095306
10310 12:30:39.637948 02f80000 ################################################################
10311 12:30:39.638100
10312 12:30:40.173942 03000000 ################################################################
10313 12:30:40.174102
10314 12:30:40.698339 03080000 ################################################################
10315 12:30:40.698519
10316 12:30:41.243006 03100000 ################################################################
10317 12:30:41.243162
10318 12:30:41.776203 03180000 ################################################################
10319 12:30:41.776370
10320 12:30:42.308763 03200000 ################################################################
10321 12:30:42.308907
10322 12:30:42.835479 03280000 ################################################################
10323 12:30:42.835640
10324 12:30:43.378318 03300000 ################################################################
10325 12:30:43.378455
10326 12:30:43.905921 03380000 ################################################################
10327 12:30:43.906085
10328 12:30:44.455492 03400000 ################################################################
10329 12:30:44.455645
10330 12:30:44.979676 03480000 ################################################################
10331 12:30:44.979827
10332 12:30:45.501605 03500000 ################################################################
10333 12:30:45.501777
10334 12:30:46.022800 03580000 ################################################################
10335 12:30:46.022988
10336 12:30:46.564659 03600000 ################################################################
10337 12:30:46.565158
10338 12:30:46.953927 03680000 ############################################# done.
10339 12:30:46.954105
10340 12:30:46.957514 The bootfile was 57512622 bytes long.
10341 12:30:46.957623
10342 12:30:46.960525 Sending tftp read request... done.
10343 12:30:46.960624
10344 12:30:46.960716 Waiting for the transfer...
10345 12:30:46.960869
10346 12:30:46.964038 00000000 # done.
10347 12:30:46.964139
10348 12:30:46.970339 Command line loaded dynamically from TFTP file: 10605794/tftp-deploy-_yyx4mc8/kernel/cmdline
10349 12:30:46.970444
10350 12:30:46.983647 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10351 12:30:46.983753
10352 12:30:46.983849 Loading FIT.
10353 12:30:46.983939
10354 12:30:46.987296 Image ramdisk-1 has 47376913 bytes.
10355 12:30:46.987432
10356 12:30:46.990720 Image fdt-1 has 46924 bytes.
10357 12:30:46.990818
10358 12:30:46.993640 Image kernel-1 has 10086749 bytes.
10359 12:30:46.993739
10360 12:30:47.000565 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10361 12:30:47.000677
10362 12:30:47.020389 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10363 12:30:47.020503
10364 12:30:47.024104 Choosing best match conf-1 for compat google,spherion-rev2.
10365 12:30:47.028656
10366 12:30:47.033107 Connected to device vid:did:rid of 1ae0:0028:00
10367 12:30:47.040599
10368 12:30:47.043681 tpm_get_response: command 0x17b, return code 0x0
10369 12:30:47.043785
10370 12:30:47.047440 ec_init: CrosEC protocol v3 supported (256, 248)
10371 12:30:47.051531
10372 12:30:47.054352 tpm_cleanup: add release locality here.
10373 12:30:47.054454
10374 12:30:47.054550 Shutting down all USB controllers.
10375 12:30:47.057530
10376 12:30:47.057631 Removing current net device
10377 12:30:47.057723
10378 12:30:47.064490 Exiting depthcharge with code 4 at timestamp: 96264765
10379 12:30:47.064594
10380 12:30:47.067694 LZMA decompressing kernel-1 to 0x821a6718
10381 12:30:47.067797
10382 12:30:47.071246 LZMA decompressing kernel-1 to 0x40000000
10383 12:30:48.338015
10384 12:30:48.338739 jumping to kernel
10385 12:30:48.341792 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10386 12:30:48.342601 start: 2.2.5 auto-login-action (timeout 00:03:17) [common]
10387 12:30:48.343208 Setting prompt string to ['Linux version [0-9]']
10388 12:30:48.343831 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10389 12:30:48.344375 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10390 12:30:48.420355
10391 12:30:48.423603 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10392 12:30:48.426962 start: 2.2.5.1 login-action (timeout 00:03:17) [common]
10393 12:30:48.427079 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10394 12:30:48.427196 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10395 12:30:48.427304 Using line separator: #'\n'#
10396 12:30:48.427421 No login prompt set.
10397 12:30:48.427485 Parsing kernel messages
10398 12:30:48.427543 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10399 12:30:48.427654 [login-action] Waiting for messages, (timeout 00:03:17)
10400 12:30:48.446485 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10401 12:30:48.450385 [ 0.000000] random: crng init done
10402 12:30:48.453399 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10403 12:30:48.456558 [ 0.000000] efi: UEFI not found.
10404 12:30:48.466680 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10405 12:30:48.473043 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10406 12:30:48.483563 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10407 12:30:48.493235 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10408 12:30:48.499437 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10409 12:30:48.503139 [ 0.000000] printk: bootconsole [mtk8250] enabled
10410 12:30:48.511752 [ 0.000000] NUMA: No NUMA configuration found
10411 12:30:48.518353 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10412 12:30:48.525094 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10413 12:30:48.525203 [ 0.000000] Zone ranges:
10414 12:30:48.532057 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10415 12:30:48.535192 [ 0.000000] DMA32 empty
10416 12:30:48.541528 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10417 12:30:48.545299 [ 0.000000] Movable zone start for each node
10418 12:30:48.548398 [ 0.000000] Early memory node ranges
10419 12:30:48.554836 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10420 12:30:48.561729 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10421 12:30:48.568192 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10422 12:30:48.574694 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10423 12:30:48.581492 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10424 12:30:48.587838 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10425 12:30:48.644654 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10426 12:30:48.650881 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10427 12:30:48.657789 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10428 12:30:48.661000 [ 0.000000] psci: probing for conduit method from DT.
10429 12:30:48.667268 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10430 12:30:48.671204 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10431 12:30:48.677586 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10432 12:30:48.680751 [ 0.000000] psci: SMC Calling Convention v1.2
10433 12:30:48.687840 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10434 12:30:48.690726 [ 0.000000] Detected VIPT I-cache on CPU0
10435 12:30:48.697879 [ 0.000000] CPU features: detected: GIC system register CPU interface
10436 12:30:48.704924 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10437 12:30:48.711190 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10438 12:30:48.717954 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10439 12:30:48.724360 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10440 12:30:48.730994 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10441 12:30:48.737188 [ 0.000000] alternatives: applying boot alternatives
10442 12:30:48.740899 [ 0.000000] Fallback order for Node 0: 0
10443 12:30:48.751014 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10444 12:30:48.751098 [ 0.000000] Policy zone: Normal
10445 12:30:48.763789 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10446 12:30:48.773864 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10447 12:30:48.785518 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10448 12:30:48.795026 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10449 12:30:48.801855 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10450 12:30:48.805123 <6>[ 0.000000] software IO TLB: area num 8.
10451 12:30:48.861977 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10452 12:30:49.010921 <6>[ 0.000000] Memory: 7926672K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426096K reserved, 32768K cma-reserved)
10453 12:30:49.017842 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10454 12:30:49.024174 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10455 12:30:49.027423 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10456 12:30:49.034598 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10457 12:30:49.041140 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10458 12:30:49.044137 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10459 12:30:49.054504 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10460 12:30:49.060785 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10461 12:30:49.067463 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10462 12:30:49.073904 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10463 12:30:49.077163 <6>[ 0.000000] GICv3: 608 SPIs implemented
10464 12:30:49.081025 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10465 12:30:49.087228 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10466 12:30:49.090463 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10467 12:30:49.097014 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10468 12:30:49.109989 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10469 12:30:49.120127 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10470 12:30:49.129807 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10471 12:30:49.137410 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10472 12:30:49.150744 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10473 12:30:49.157299 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10474 12:30:49.164186 <6>[ 0.009197] Console: colour dummy device 80x25
10475 12:30:49.173727 <6>[ 0.013924] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10476 12:30:49.180187 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10477 12:30:49.184018 <6>[ 0.029273] LSM: Security Framework initializing
10478 12:30:49.190491 <6>[ 0.034213] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10479 12:30:49.200693 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10480 12:30:49.207016 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10481 12:30:49.213911 <6>[ 0.058895] cblist_init_generic: Setting shift to 3 and lim to 1.
10482 12:30:49.220064 <6>[ 0.065233] cblist_init_generic: Setting shift to 3 and lim to 1.
10483 12:30:49.226998 <6>[ 0.071680] rcu: Hierarchical SRCU implementation.
10484 12:30:49.230193 <6>[ 0.076694] rcu: Max phase no-delay instances is 1000.
10485 12:30:49.238427 <6>[ 0.083712] EFI services will not be available.
10486 12:30:49.241533 <6>[ 0.088711] smp: Bringing up secondary CPUs ...
10487 12:30:49.250516 <6>[ 0.093794] Detected VIPT I-cache on CPU1
10488 12:30:49.257544 <6>[ 0.093866] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10489 12:30:49.264286 <6>[ 0.093899] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10490 12:30:49.267275 <6>[ 0.094231] Detected VIPT I-cache on CPU2
10491 12:30:49.274532 <6>[ 0.094278] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10492 12:30:49.283829 <6>[ 0.094293] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10493 12:30:49.287127 <6>[ 0.094544] Detected VIPT I-cache on CPU3
10494 12:30:49.294010 <6>[ 0.094586] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10495 12:30:49.300288 <6>[ 0.094599] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10496 12:30:49.304143 <6>[ 0.094888] CPU features: detected: Spectre-v4
10497 12:30:49.310390 <6>[ 0.094893] CPU features: detected: Spectre-BHB
10498 12:30:49.313730 <6>[ 0.094898] Detected PIPT I-cache on CPU4
10499 12:30:49.320654 <6>[ 0.094949] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10500 12:30:49.326923 <6>[ 0.094965] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10501 12:30:49.334103 <6>[ 0.095257] Detected PIPT I-cache on CPU5
10502 12:30:49.340561 <6>[ 0.095323] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10503 12:30:49.347579 <6>[ 0.095339] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10504 12:30:49.350786 <6>[ 0.095620] Detected PIPT I-cache on CPU6
10505 12:30:49.357038 <6>[ 0.095688] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10506 12:30:49.364103 <6>[ 0.095704] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10507 12:30:49.370291 <6>[ 0.096001] Detected PIPT I-cache on CPU7
10508 12:30:49.377208 <6>[ 0.096065] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10509 12:30:49.383765 <6>[ 0.096081] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10510 12:30:49.386905 <6>[ 0.096128] smp: Brought up 1 node, 8 CPUs
10511 12:30:49.393936 <6>[ 0.237501] SMP: Total of 8 processors activated.
10512 12:30:49.397005 <6>[ 0.242423] CPU features: detected: 32-bit EL0 Support
10513 12:30:49.406928 <6>[ 0.247818] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10514 12:30:49.413179 <6>[ 0.256618] CPU features: detected: Common not Private translations
10515 12:30:49.420134 <6>[ 0.263134] CPU features: detected: CRC32 instructions
10516 12:30:49.423768 <6>[ 0.268518] CPU features: detected: RCpc load-acquire (LDAPR)
10517 12:30:49.430357 <6>[ 0.274478] CPU features: detected: LSE atomic instructions
10518 12:30:49.436743 <6>[ 0.280259] CPU features: detected: Privileged Access Never
10519 12:30:49.443173 <6>[ 0.286075] CPU features: detected: RAS Extension Support
10520 12:30:49.450341 <6>[ 0.291684] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10521 12:30:49.453319 <6>[ 0.298905] CPU: All CPU(s) started at EL2
10522 12:30:49.459782 <6>[ 0.303222] alternatives: applying system-wide alternatives
10523 12:30:49.468705 <6>[ 0.313942] devtmpfs: initialized
10524 12:30:49.484710 <6>[ 0.322893] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10525 12:30:49.491226 <6>[ 0.332856] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10526 12:30:49.498037 <6>[ 0.341071] pinctrl core: initialized pinctrl subsystem
10527 12:30:49.500972 <6>[ 0.347738] DMI not present or invalid.
10528 12:30:49.508064 <6>[ 0.352151] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10529 12:30:49.517620 <6>[ 0.359036] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10530 12:30:49.524123 <6>[ 0.366620] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10531 12:30:49.534159 <6>[ 0.374841] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10532 12:30:49.537151 <6>[ 0.383083] audit: initializing netlink subsys (disabled)
10533 12:30:49.547510 <5>[ 0.388773] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10534 12:30:49.553851 <6>[ 0.389476] thermal_sys: Registered thermal governor 'step_wise'
10535 12:30:49.560866 <6>[ 0.396738] thermal_sys: Registered thermal governor 'power_allocator'
10536 12:30:49.564099 <6>[ 0.402994] cpuidle: using governor menu
10537 12:30:49.570456 <6>[ 0.413954] NET: Registered PF_QIPCRTR protocol family
10538 12:30:49.577328 <6>[ 0.419431] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10539 12:30:49.583566 <6>[ 0.426536] ASID allocator initialised with 32768 entries
10540 12:30:49.587116 <6>[ 0.433127] Serial: AMBA PL011 UART driver
10541 12:30:49.596687 <4>[ 0.441843] Trying to register duplicate clock ID: 134
10542 12:30:49.652842 <6>[ 0.501210] KASLR enabled
10543 12:30:49.667445 <6>[ 0.509002] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10544 12:30:49.673924 <6>[ 0.516014] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10545 12:30:49.680309 <6>[ 0.522502] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10546 12:30:49.687255 <6>[ 0.529505] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10547 12:30:49.693717 <6>[ 0.535992] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10548 12:30:49.700620 <6>[ 0.542997] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10549 12:30:49.707004 <6>[ 0.549483] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10550 12:30:49.713822 <6>[ 0.556490] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10551 12:30:49.717020 <6>[ 0.563993] ACPI: Interpreter disabled.
10552 12:30:49.725287 <6>[ 0.570408] iommu: Default domain type: Translated
10553 12:30:49.732180 <6>[ 0.575518] iommu: DMA domain TLB invalidation policy: strict mode
10554 12:30:49.735261 <5>[ 0.582179] SCSI subsystem initialized
10555 12:30:49.741616 <6>[ 0.586348] usbcore: registered new interface driver usbfs
10556 12:30:49.748638 <6>[ 0.592079] usbcore: registered new interface driver hub
10557 12:30:49.751762 <6>[ 0.597628] usbcore: registered new device driver usb
10558 12:30:49.758715 <6>[ 0.603724] pps_core: LinuxPPS API ver. 1 registered
10559 12:30:49.768330 <6>[ 0.608919] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10560 12:30:49.771696 <6>[ 0.618263] PTP clock support registered
10561 12:30:49.774887 <6>[ 0.622505] EDAC MC: Ver: 3.0.0
10562 12:30:49.782482 <6>[ 0.627661] FPGA manager framework
10563 12:30:49.785800 <6>[ 0.631344] Advanced Linux Sound Architecture Driver Initialized.
10564 12:30:49.789284 <6>[ 0.638125] vgaarb: loaded
10565 12:30:49.796184 <6>[ 0.641289] clocksource: Switched to clocksource arch_sys_counter
10566 12:30:49.802433 <5>[ 0.647709] VFS: Disk quotas dquot_6.6.0
10567 12:30:49.809369 <6>[ 0.651895] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10568 12:30:49.812665 <6>[ 0.659083] pnp: PnP ACPI: disabled
10569 12:30:49.820993 <6>[ 0.665762] NET: Registered PF_INET protocol family
10570 12:30:49.830279 <6>[ 0.671346] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10571 12:30:49.842217 <6>[ 0.683633] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10572 12:30:49.852008 <6>[ 0.692447] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10573 12:30:49.858283 <6>[ 0.700417] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10574 12:30:49.864903 <6>[ 0.709116] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10575 12:30:49.876990 <6>[ 0.718866] TCP: Hash tables configured (established 65536 bind 65536)
10576 12:30:49.883919 <6>[ 0.725724] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10577 12:30:49.890290 <6>[ 0.732922] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10578 12:30:49.896636 <6>[ 0.740623] NET: Registered PF_UNIX/PF_LOCAL protocol family
10579 12:30:49.903605 <6>[ 0.746799] RPC: Registered named UNIX socket transport module.
10580 12:30:49.906725 <6>[ 0.752952] RPC: Registered udp transport module.
10581 12:30:49.913960 <6>[ 0.757882] RPC: Registered tcp transport module.
10582 12:30:49.920067 <6>[ 0.762814] RPC: Registered tcp NFSv4.1 backchannel transport module.
10583 12:30:49.923571 <6>[ 0.769484] PCI: CLS 0 bytes, default 64
10584 12:30:49.926998 <6>[ 0.773833] Unpacking initramfs...
10585 12:30:49.936912 <6>[ 0.777980] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10586 12:30:49.943461 <6>[ 0.786627] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10587 12:30:49.950182 <6>[ 0.795505] kvm [1]: IPA Size Limit: 40 bits
10588 12:30:49.953454 <6>[ 0.800030] kvm [1]: GICv3: no GICV resource entry
10589 12:30:49.960276 <6>[ 0.805052] kvm [1]: disabling GICv2 emulation
10590 12:30:49.967138 <6>[ 0.809749] kvm [1]: GIC system register CPU interface enabled
10591 12:30:49.970502 <6>[ 0.815930] kvm [1]: vgic interrupt IRQ18
10592 12:30:49.976849 <6>[ 0.820294] kvm [1]: VHE mode initialized successfully
10593 12:30:49.980083 <5>[ 0.826813] Initialise system trusted keyrings
10594 12:30:49.986981 <6>[ 0.831626] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10595 12:30:49.996646 <6>[ 0.841721] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10596 12:30:50.002918 <5>[ 0.848164] NFS: Registering the id_resolver key type
10597 12:30:50.006587 <5>[ 0.853474] Key type id_resolver registered
10598 12:30:50.013564 <5>[ 0.857890] Key type id_legacy registered
10599 12:30:50.019949 <6>[ 0.862178] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10600 12:30:50.026332 <6>[ 0.869102] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10601 12:30:50.033257 <6>[ 0.876848] 9p: Installing v9fs 9p2000 file system support
10602 12:30:50.070026 <5>[ 0.915069] Key type asymmetric registered
10603 12:30:50.072809 <5>[ 0.919404] Asymmetric key parser 'x509' registered
10604 12:30:50.083111 <6>[ 0.924544] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10605 12:30:50.086402 <6>[ 0.932157] io scheduler mq-deadline registered
10606 12:30:50.089564 <6>[ 0.936918] io scheduler kyber registered
10607 12:30:50.108557 <6>[ 0.953921] EINJ: ACPI disabled.
10608 12:30:50.140589 <4>[ 0.979253] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 12:30:50.150661 <4>[ 0.989896] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 12:30:50.165565 <6>[ 1.010731] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10611 12:30:50.172968 <6>[ 1.018669] printk: console [ttyS0] disabled
10612 12:30:50.201325 <6>[ 1.043312] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10613 12:30:50.207483 <6>[ 1.052787] printk: console [ttyS0] enabled
10614 12:30:50.211204 <6>[ 1.052787] printk: console [ttyS0] enabled
10615 12:30:50.217648 <6>[ 1.061682] printk: bootconsole [mtk8250] disabled
10616 12:30:50.221339 <6>[ 1.061682] printk: bootconsole [mtk8250] disabled
10617 12:30:50.227828 <6>[ 1.072887] SuperH (H)SCI(F) driver initialized
10618 12:30:50.231012 <6>[ 1.078152] msm_serial: driver initialized
10619 12:30:50.244490 <6>[ 1.087007] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10620 12:30:50.254597 <6>[ 1.095552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10621 12:30:50.261130 <6>[ 1.104094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10622 12:30:50.271461 <6>[ 1.112722] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10623 12:30:50.281257 <6>[ 1.121432] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10624 12:30:50.287459 <6>[ 1.130152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10625 12:30:50.297696 <6>[ 1.138693] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10626 12:30:50.304661 <6>[ 1.147499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10627 12:30:50.314345 <6>[ 1.156043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10628 12:30:50.326187 <6>[ 1.171485] loop: module loaded
10629 12:30:50.332548 <6>[ 1.177506] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10630 12:30:50.355393 <4>[ 1.200737] mtk-pmic-keys: Failed to locate of_node [id: -1]
10631 12:30:50.362254 <6>[ 1.207683] megasas: 07.719.03.00-rc1
10632 12:30:50.372535 <6>[ 1.217433] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10633 12:30:50.379483 <6>[ 1.224691] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10634 12:30:50.396602 <6>[ 1.241328] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10635 12:30:50.456962 <6>[ 1.295500] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10636 12:30:51.956633 <6>[ 2.802358] Freeing initrd memory: 46260K
10637 12:30:51.967231 <6>[ 2.812849] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10638 12:30:51.978276 <6>[ 2.823993] tun: Universal TUN/TAP device driver, 1.6
10639 12:30:51.981477 <6>[ 2.830054] thunder_xcv, ver 1.0
10640 12:30:51.985270 <6>[ 2.833563] thunder_bgx, ver 1.0
10641 12:30:51.988307 <6>[ 2.837053] nicpf, ver 1.0
10642 12:30:51.999212 <6>[ 2.841086] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10643 12:30:52.002288 <6>[ 2.848562] hns3: Copyright (c) 2017 Huawei Corporation.
10644 12:30:52.008823 <6>[ 2.854151] hclge is initializing
10645 12:30:52.012387 <6>[ 2.857735] e1000: Intel(R) PRO/1000 Network Driver
10646 12:30:52.019168 <6>[ 2.862863] e1000: Copyright (c) 1999-2006 Intel Corporation.
10647 12:30:52.022058 <6>[ 2.868876] e1000e: Intel(R) PRO/1000 Network Driver
10648 12:30:52.029093 <6>[ 2.874091] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10649 12:30:52.035472 <6>[ 2.880277] igb: Intel(R) Gigabit Ethernet Network Driver
10650 12:30:52.042316 <6>[ 2.885927] igb: Copyright (c) 2007-2014 Intel Corporation.
10651 12:30:52.048717 <6>[ 2.891764] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10652 12:30:52.055914 <6>[ 2.898282] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10653 12:30:52.058900 <6>[ 2.904741] sky2: driver version 1.30
10654 12:30:52.065354 <6>[ 2.909740] VFIO - User Level meta-driver version: 0.3
10655 12:30:52.073040 <6>[ 2.917989] usbcore: registered new interface driver usb-storage
10656 12:30:52.079653 <6>[ 2.924436] usbcore: registered new device driver onboard-usb-hub
10657 12:30:52.088162 <6>[ 2.933573] mt6397-rtc mt6359-rtc: registered as rtc0
10658 12:30:52.097958 <6>[ 2.939037] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:31:03 UTC (1686054663)
10659 12:30:52.101267 <6>[ 2.948608] i2c_dev: i2c /dev entries driver
10660 12:30:52.118540 <6>[ 2.960347] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10661 12:30:52.125332 <6>[ 2.970616] sdhci: Secure Digital Host Controller Interface driver
10662 12:30:52.132073 <6>[ 2.977054] sdhci: Copyright(c) Pierre Ossman
10663 12:30:52.138151 <6>[ 2.982448] Synopsys Designware Multimedia Card Interface Driver
10664 12:30:52.141886 <6>[ 2.989047] mmc0: CQHCI version 5.10
10665 12:30:52.148655 <6>[ 2.989603] sdhci-pltfm: SDHCI platform and OF driver helper
10666 12:30:52.155823 <6>[ 3.000919] ledtrig-cpu: registered to indicate activity on CPUs
10667 12:30:52.166391 <6>[ 3.008293] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10668 12:30:52.169732 <6>[ 3.015688] usbcore: registered new interface driver usbhid
10669 12:30:52.175715 <6>[ 3.021521] usbhid: USB HID core driver
10670 12:30:52.182709 <6>[ 3.025771] spi_master spi0: will run message pump with realtime priority
10671 12:30:52.224350 <6>[ 3.063441] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10672 12:30:52.242664 <6>[ 3.078422] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10673 12:30:52.245649 <6>[ 3.092001] mmc0: Command Queue Engine enabled
10674 12:30:52.253087 <6>[ 3.096782] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10675 12:30:52.259437 <6>[ 3.104054] mmcblk0: mmc0:0001 DA4128 116 GiB
10676 12:30:52.262627 <6>[ 3.109014] cros-ec-spi spi0.0: Chrome EC device registered
10677 12:30:52.269472 <6>[ 3.113387] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10678 12:30:52.277157 <6>[ 3.122491] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10679 12:30:52.283664 <6>[ 3.128370] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10680 12:30:52.289957 <6>[ 3.134590] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10681 12:30:52.310468 <6>[ 3.152821] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10682 12:30:52.319021 <6>[ 3.164236] NET: Registered PF_PACKET protocol family
10683 12:30:52.325759 <6>[ 3.169670] 9pnet: Installing 9P2000 support
10684 12:30:52.328941 <5>[ 3.174246] Key type dns_resolver registered
10685 12:30:52.331991 <6>[ 3.179313] registered taskstats version 1
10686 12:30:52.339099 <5>[ 3.183719] Loading compiled-in X.509 certificates
10687 12:30:52.374160 <4>[ 3.212879] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10688 12:30:52.384160 <4>[ 3.223609] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10689 12:30:52.394017 <3>[ 3.236566] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10690 12:30:52.406875 <6>[ 3.252358] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10691 12:30:52.413354 <6>[ 3.259226] xhci-mtk 11200000.usb: xHCI Host Controller
10692 12:30:52.420263 <6>[ 3.264767] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10693 12:30:52.430275 <6>[ 3.272724] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10694 12:30:52.436581 <6>[ 3.282203] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10695 12:30:52.443491 <6>[ 3.288295] xhci-mtk 11200000.usb: xHCI Host Controller
10696 12:30:52.450608 <6>[ 3.293781] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10697 12:30:52.456504 <6>[ 3.301434] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10698 12:30:52.463530 <6>[ 3.309366] hub 1-0:1.0: USB hub found
10699 12:30:52.466979 <6>[ 3.313402] hub 1-0:1.0: 1 port detected
10700 12:30:52.476492 <6>[ 3.317754] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10701 12:30:52.479772 <6>[ 3.326600] hub 2-0:1.0: USB hub found
10702 12:30:52.483340 <6>[ 3.330651] hub 2-0:1.0: 1 port detected
10703 12:30:52.492322 <6>[ 3.337911] mtk-msdc 11f70000.mmc: Got CD GPIO
10704 12:30:52.509190 <6>[ 3.351628] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10705 12:30:52.516484 <6>[ 3.359680] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10706 12:30:52.525717 <4>[ 3.367658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10707 12:30:52.535859 <6>[ 3.377320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10708 12:30:52.542386 <6>[ 3.385410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10709 12:30:52.552460 <6>[ 3.393505] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10710 12:30:52.559025 <6>[ 3.401421] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10711 12:30:52.565699 <6>[ 3.409245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10712 12:30:52.575238 <6>[ 3.417068] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10713 12:30:52.585399 <6>[ 3.427773] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10714 12:30:52.595436 <6>[ 3.436170] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10715 12:30:52.601806 <6>[ 3.444522] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10716 12:30:52.612021 <6>[ 3.452866] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10717 12:30:52.618558 <6>[ 3.461209] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10718 12:30:52.628058 <6>[ 3.469552] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10719 12:30:52.634931 <6>[ 3.477896] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10720 12:30:52.644533 <6>[ 3.486249] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10721 12:30:52.651583 <6>[ 3.494593] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10722 12:30:52.661856 <6>[ 3.502936] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10723 12:30:52.668101 <6>[ 3.511280] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10724 12:30:52.677915 <6>[ 3.519622] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10725 12:30:52.684585 <6>[ 3.527966] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10726 12:30:52.694840 <6>[ 3.536309] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10727 12:30:52.700961 <6>[ 3.544654] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10728 12:30:52.708095 <6>[ 3.553529] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10729 12:30:52.715151 <6>[ 3.560948] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10730 12:30:52.722034 <6>[ 3.567981] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10731 12:30:52.732334 <6>[ 3.575077] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10732 12:30:52.739323 <6>[ 3.582375] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10733 12:30:52.748972 <6>[ 3.589292] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10734 12:30:52.756044 <6>[ 3.598440] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10735 12:30:52.766033 <6>[ 3.607567] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10736 12:30:52.775871 <6>[ 3.616869] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10737 12:30:52.786076 <6>[ 3.626345] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10738 12:30:52.795585 <6>[ 3.635819] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10739 12:30:52.805372 <6>[ 3.644946] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10740 12:30:52.812162 <6>[ 3.654422] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10741 12:30:52.821774 <6>[ 3.663549] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10742 12:30:52.832087 <6>[ 3.672852] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10743 12:30:52.841676 <6>[ 3.683019] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10744 12:30:52.852377 <6>[ 3.694518] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10745 12:30:52.875303 <6>[ 3.717898] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10746 12:30:52.903856 <6>[ 3.749616] hub 2-1:1.0: USB hub found
10747 12:30:52.907028 <6>[ 3.754143] hub 2-1:1.0: 3 ports detected
10748 12:30:53.026999 <6>[ 3.869531] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10749 12:30:53.180411 <6>[ 4.025801] hub 1-1:1.0: USB hub found
10750 12:30:53.183595 <6>[ 4.030158] hub 1-1:1.0: 4 ports detected
10751 12:30:53.259703 <6>[ 4.101814] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10752 12:30:53.503442 <6>[ 4.345565] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10753 12:30:53.636510 <6>[ 4.481818] hub 1-1.4:1.0: USB hub found
10754 12:30:53.639646 <6>[ 4.486502] hub 1-1.4:1.0: 2 ports detected
10755 12:30:53.934971 <6>[ 4.777558] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10756 12:30:54.127052 <6>[ 4.969560] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10757 12:31:05.127706 <6>[ 15.978130] ALSA device list:
10758 12:31:05.134118 <6>[ 15.981385] No soundcards found.
10759 12:31:05.146688 <6>[ 15.993802] Freeing unused kernel memory: 8384K
10760 12:31:05.149888 <6>[ 15.998734] Run /init as init process
10761 12:31:05.180755 <6>[ 16.027670] NET: Registered PF_INET6 protocol family
10762 12:31:05.187082 <6>[ 16.034207] Segment Routing with IPv6
10763 12:31:05.190255 <6>[ 16.038204] In-situ OAM (IOAM) with IPv6
10764 12:31:05.225388 <30>[ 16.052926] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10765 12:31:05.228494 <30>[ 16.076922] systemd[1]: Detected architecture arm64.
10766 12:31:05.232304
10767 12:31:05.235452 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10768 12:31:05.235593
10769 12:31:05.250482 <30>[ 16.097740] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10770 12:31:05.387606 <30>[ 16.230972] systemd[1]: Queued start job for default target Graphical Interface.
10771 12:31:05.439245 <30>[ 16.286809] systemd[1]: Created slice system-getty.slice.
10772 12:31:05.446218 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10773 12:31:05.463281 <30>[ 16.310188] systemd[1]: Created slice system-modprobe.slice.
10774 12:31:05.469622 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10775 12:31:05.487679 <30>[ 16.334705] systemd[1]: Created slice system-serial\x2dgetty.slice.
10776 12:31:05.497538 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10777 12:31:05.510904 <30>[ 16.358044] systemd[1]: Created slice User and Session Slice.
10778 12:31:05.517265 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10779 12:31:05.537949 <30>[ 16.381793] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10780 12:31:05.544510 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10781 12:31:05.561684 <30>[ 16.405701] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10782 12:31:05.568510 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10783 12:31:05.588895 <30>[ 16.429637] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10784 12:31:05.595274 <30>[ 16.441657] systemd[1]: Reached target Local Encrypted Volumes.
10785 12:31:05.602131 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10786 12:31:05.618396 <30>[ 16.465919] systemd[1]: Reached target Paths.
10787 12:31:05.622248 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10788 12:31:05.638627 <30>[ 16.485535] systemd[1]: Reached target Remote File Systems.
10789 12:31:05.644966 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10790 12:31:05.658443 <30>[ 16.505537] systemd[1]: Reached target Slices.
10791 12:31:05.661550 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10792 12:31:05.678482 <30>[ 16.525613] systemd[1]: Reached target Swap.
10793 12:31:05.681691 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10794 12:31:05.702101 <30>[ 16.545844] systemd[1]: Listening on initctl Compatibility Named Pipe.
10795 12:31:05.708689 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10796 12:31:05.715458 <30>[ 16.560515] systemd[1]: Listening on Journal Audit Socket.
10797 12:31:05.721960 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10798 12:31:05.734273 <30>[ 16.581834] systemd[1]: Listening on Journal Socket (/dev/log).
10799 12:31:05.741274 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10800 12:31:05.759033 <30>[ 16.606347] systemd[1]: Listening on Journal Socket.
10801 12:31:05.765917 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10802 12:31:05.781822 <30>[ 16.625946] systemd[1]: Listening on Network Service Netlink Socket.
10803 12:31:05.788297 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10804 12:31:05.802897 <30>[ 16.650338] systemd[1]: Listening on udev Control Socket.
10805 12:31:05.809580 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10806 12:31:05.827132 <30>[ 16.674274] systemd[1]: Listening on udev Kernel Socket.
10807 12:31:05.833365 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10808 12:31:05.870635 <30>[ 16.717913] systemd[1]: Mounting Huge Pages File System...
10809 12:31:05.877091 Mounting [0;1;39mHuge Pages File System[0m...
10810 12:31:05.892177 <30>[ 16.739764] systemd[1]: Mounting POSIX Message Queue File System...
10811 12:31:05.899290 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10812 12:31:05.916065 <30>[ 16.763682] systemd[1]: Mounting Kernel Debug File System...
10813 12:31:05.922787 Mounting [0;1;39mKernel Debug File System[0m...
10814 12:31:05.941784 <30>[ 16.785859] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10815 12:31:05.953170 <30>[ 16.796886] systemd[1]: Starting Create list of static device nodes for the current kernel...
10816 12:31:05.959546 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10817 12:31:05.976310 <30>[ 16.823872] systemd[1]: Starting Load Kernel Module configfs...
10818 12:31:05.983140 Starting [0;1;39mLoad Kernel Module configfs[0m...
10819 12:31:06.000818 <30>[ 16.847977] systemd[1]: Starting Load Kernel Module drm...
10820 12:31:06.007108 Starting [0;1;39mLoad Kernel Module drm[0m...
10821 12:31:06.025433 <30>[ 16.869833] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10822 12:31:06.074599 <30>[ 16.922257] systemd[1]: Starting Journal Service...
10823 12:31:06.078513 Starting [0;1;39mJournal Service[0m...
10824 12:31:06.096873 <30>[ 16.944456] systemd[1]: Starting Load Kernel Modules...
10825 12:31:06.103940 Starting [0;1;39mLoad Kernel Modules[0m...
10826 12:31:06.124142 <30>[ 16.968353] systemd[1]: Starting Remount Root and Kernel File Systems...
10827 12:31:06.131099 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10828 12:31:06.149052 <30>[ 16.996338] systemd[1]: Starting Coldplug All udev Devices...
10829 12:31:06.155566 Starting [0;1;39mColdplug All udev Devices[0m...
10830 12:31:06.172981 <30>[ 17.020443] systemd[1]: Mounted Huge Pages File System.
10831 12:31:06.179398 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10832 12:31:06.195160 <30>[ 17.042583] systemd[1]: Started Journal Service.
10833 12:31:06.201726 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10834 12:31:06.216580 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10835 12:31:06.234924 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10836 12:31:06.254865 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10837 12:31:06.271773 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10838 12:31:06.288304 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10839 12:31:06.307361 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10840 12:31:06.327170 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10841 12:31:06.342437 See 'systemctl status systemd-remount-fs.service' for details.
10842 12:31:06.399609 Mounting [0;1;39mKernel Configuration File System[0m...
10843 12:31:06.421320 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10844 12:31:06.439059 <46>[ 17.283156] systemd-journald[179]: Received client request to flush runtime journal.
10845 12:31:06.448190 Starting [0;1;39mLoad/Save Random Seed[0m...
10846 12:31:06.465425 Starting [0;1;39mApply Kernel Variables[0m...
10847 12:31:06.485115 Starting [0;1;39mCreate System Users[0m...
10848 12:31:06.500206 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10849 12:31:06.523120 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10850 12:31:06.535199 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10851 12:31:06.551277 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10852 12:31:06.571339 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10853 12:31:06.587215 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10854 12:31:06.611512 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10855 12:31:06.634061 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10856 12:31:06.647209 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10857 12:31:06.662651 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10858 12:31:06.714708 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10859 12:31:06.738114 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10860 12:31:06.755118 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10861 12:31:06.775186 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10862 12:31:06.835450 Starting [0;1;39mNetwork Service[0m...
10863 12:31:06.857004 Starting [0;1;39mNetwork Time Synchronization[0m...
10864 12:31:06.880844 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10865 12:31:06.920738 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10866 12:31:06.938801 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10867 12:31:06.971243 <6>[ 17.815595] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10868 12:31:06.978117 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10869 12:31:06.984458 <6>[ 17.831656] remoteproc remoteproc0: scp is available
10870 12:31:06.994755 <4>[ 17.837198] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10871 12:31:07.001270 <6>[ 17.847327] remoteproc remoteproc0: powering up scp
10872 12:31:07.011151 <4>[ 17.853987] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10873 12:31:07.017508 <6>[ 17.857449] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10874 12:31:07.024278 <3>[ 17.864959] remoteproc remoteproc0: request_firmware failed: -2
10875 12:31:07.034481 <6>[ 17.871687] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10876 12:31:07.040883 <6>[ 17.878909] usbcore: registered new interface driver r8152
10877 12:31:07.047545 <6>[ 17.886737] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10878 12:31:07.060674 Starting [0;1;39mLoad/<3>[ 17.903591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 12:31:07.070826 Save Screen …o<3>[ 17.912394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 12:31:07.077241 f leds:white:kbd<3>[ 17.921746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 12:31:07.080361 _backlight[0m...
10882 12:31:07.090998 <3>[ 17.935311] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10883 12:31:07.097852 <3>[ 17.943598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 12:31:07.107780 <3>[ 17.951766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 12:31:07.114193 <3>[ 17.960024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 12:31:07.123933 <6>[ 17.964282] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10887 12:31:07.131133 <3>[ 17.968122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 12:31:07.137558 <6>[ 17.972712] usbcore: registered new interface driver cdc_ether
10889 12:31:07.144325 <3>[ 17.981907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10890 12:31:07.153931 <4>[ 17.998118] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10891 12:31:07.160765 <4>[ 17.998118] Fallback method does not support PEC.
10892 12:31:07.174031 <3>[ 18.017258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 12:31:07.180269 <3>[ 18.025659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 12:31:07.190446 <3>[ 18.028891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 12:31:07.196908 <3>[ 18.033797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 12:31:07.204040 <6>[ 18.045540] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10897 12:31:07.210419 Startin<6>[ 18.058062] mc: Linux media interface: v0.10
10898 12:31:07.220523 <3>[ 18.058410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 12:31:07.226794 g [0;1;39mNetwo<4>[ 18.058973] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10900 12:31:07.237740 rk Name Resoluti<4>[ 18.062928] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10901 12:31:07.237998 on[0m...
10902 12:31:07.244237 <6>[ 18.074001] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10903 12:31:07.254190 <3>[ 18.080745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 12:31:07.257440 <6>[ 18.091913] pci_bus 0000:00: root bus resource [bus 00-ff]
10905 12:31:07.267623 <3>[ 18.097130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 12:31:07.273978 <3>[ 18.105236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 12:31:07.284136 <6>[ 18.105530] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10908 12:31:07.291147 <6>[ 18.105539] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10909 12:31:07.297563 <6>[ 18.105584] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10910 12:31:07.307844 <6>[ 18.105602] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10911 12:31:07.311106 <6>[ 18.105680] pci 0000:00:00.0: supports D1 D2
10912 12:31:07.317745 <6>[ 18.105684] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10913 12:31:07.327797 <3>[ 18.105870] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10914 12:31:07.334852 <6>[ 18.106616] videodev: Linux video capture interface: v2.00
10915 12:31:07.341007 <6>[ 18.107703] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10916 12:31:07.348033 <6>[ 18.107823] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10917 12:31:07.354599 <6>[ 18.107852] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10918 12:31:07.364499 <6>[ 18.107872] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10919 12:31:07.371068 <6>[ 18.107889] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10920 12:31:07.374314 <6>[ 18.108001] pci 0000:01:00.0: supports D1 D2
10921 12:31:07.380703 <6>[ 18.108005] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10922 12:31:07.390830 <3>[ 18.110959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 12:31:07.401096 <4>[ 18.122009] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10924 12:31:07.404864 <6>[ 18.125149] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10925 12:31:07.415073 <6>[ 18.125228] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10926 12:31:07.421630 <6>[ 18.125236] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10927 12:31:07.431261 <6>[ 18.125253] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10928 12:31:07.438336 <6>[ 18.125270] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10929 12:31:07.447715 <6>[ 18.125316] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10930 12:31:07.451483 <6>[ 18.125335] pci 0000:00:00.0: PCI bridge to [bus 01]
10931 12:31:07.461370 <6>[ 18.125348] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10932 12:31:07.464362 <6>[ 18.125673] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10933 12:31:07.470958 <6>[ 18.127006] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10934 12:31:07.480875 <3>[ 18.127826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10935 12:31:07.487861 <3>[ 18.127916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 12:31:07.494125 <6>[ 18.128949] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10937 12:31:07.501490 <4>[ 18.135054] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10938 12:31:07.511487 <6>[ 18.138295] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10939 12:31:07.522229 <6>[ 18.138797] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10940 12:31:07.531887 <3>[ 18.146248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 12:31:07.538734 <6>[ 18.223726] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10942 12:31:07.548544 <3>[ 18.257316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 12:31:07.551801 <6>[ 18.275191] r8152 2-1.3:1.0 eth0: v1.12.13
10944 12:31:07.558382 <6>[ 18.275685] usbcore: registered new interface driver r8153_ecm
10945 12:31:07.568458 <5>[ 18.296688] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10946 12:31:07.571803 <6>[ 18.305427] Bluetooth: Core ver 2.22
10947 12:31:07.578182 <6>[ 18.311253] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10948 12:31:07.584592 <6>[ 18.320260] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10949 12:31:07.591995 <5>[ 18.323714] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10950 12:31:07.595778 <6>[ 18.324786] NET: Registered PF_BLUETOOTH protocol family
10951 12:31:07.608752 <6>[ 18.335137] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10952 12:31:07.615179 <6>[ 18.340944] Bluetooth: HCI device and connection manager initialized
10953 12:31:07.622270 <6>[ 18.340972] Bluetooth: HCI socket layer initialized
10954 12:31:07.628667 <6>[ 18.341910] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10955 12:31:07.631948 <6>[ 18.347137] usbcore: registered new interface driver uvcvideo
10956 12:31:07.638852 <6>[ 18.347208] remoteproc remoteproc0: powering up scp
10957 12:31:07.648824 <4>[ 18.347260] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10958 12:31:07.655432 <3>[ 18.347269] remoteproc remoteproc0: request_firmware failed: -2
10959 12:31:07.661806 <3>[ 18.347272] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10960 12:31:07.668725 <6>[ 18.354962] Bluetooth: L2CAP socket layer initialized
10961 12:31:07.672545 <6>[ 18.354979] Bluetooth: SCO socket layer initialized
10962 12:31:07.682343 <3>[ 18.363038] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 12:31:07.688700 <3>[ 18.364006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10964 12:31:07.699119 <3>[ 18.372317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 12:31:07.706018 <6>[ 18.420324] usbcore: registered new interface driver btusb
10966 12:31:07.712491 <4>[ 18.426313] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10967 12:31:07.723357 <4>[ 18.430218] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10968 12:31:07.729829 <6>[ 18.437136] cfg80211: failed to load regulatory.db
10969 12:31:07.736255 <3>[ 18.443585] Bluetooth: hci0: Failed to load firmware file (-2)
10970 12:31:07.740098 <3>[ 18.443601] Bluetooth: hci0: Failed to set up firmware (-2)
10971 12:31:07.750194 <4>[ 18.443610] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10972 12:31:07.760463 <3>[ 18.449734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 12:31:07.767999 <6>[ 18.495838] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10974 12:31:07.777466 <3>[ 18.524333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 12:31:07.780603 <6>[ 18.525183] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10976 12:31:07.787641 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10977 12:31:07.806119 [[0;32m OK [0m] Started [0;1;39mNetwork Nam<6>[ 18.653508] mt7921e 0000:01:00.0: ASIC revision: 79610010
10978 12:31:07.809155 e Resolution[0m.
10979 12:31:07.830114 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10980 12:31:07.848714 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10981 12:31:07.912272 <4>[ 18.753165] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 12:31:08.030541 <4>[ 18.871682] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 12:31:08.037609 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10984 12:31:08.051706 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10985 12:31:08.069526 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10986 12:31:08.082101 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10987 12:31:08.101438 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10988 12:31:08.114067 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10989 12:31:08.130147 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10990 12:31:08.150474 <4>[ 18.991732] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 12:31:08.160686 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10992 12:31:08.174463 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10993 12:31:08.193560 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10994 12:31:08.205956 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10995 12:31:08.222457 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10996 12:31:08.241304 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10997 12:31:08.271002 <4>[ 19.112409] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 12:31:08.299135 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10999 12:31:08.324460 Starting [0;1;39mUser Login Management[0m...
11000 12:31:08.340411 Starting [0;1;39mPermit User Sessions[0m...
11001 12:31:08.358722 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11002 12:31:08.390005 [[0;32m OK [0m] Finished [0<4>[ 19.229248] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11003 12:31:08.393162 ;1;39mPermit User Sessions[0m.
11004 12:31:08.410213 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11005 12:31:08.462849 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11006 12:31:08.481186 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11007 12:31:08.509313 [[0;32m OK [<4>[ 19.351647] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 12:31:08.516564 0m] Reached target [0;1;39mLogin Prompts[0m.
11009 12:31:08.535795 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11010 12:31:08.551226 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11011 12:31:08.566033 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11012 12:31:08.631008 Startin<4>[ 19.472617] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11013 12:31:08.637323 g [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11014 12:31:08.663907 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11015 12:31:08.706837
11016 12:31:08.706986
11017 12:31:08.710586 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11018 12:31:08.710672
11019 12:31:08.713866 debian-bullseye-arm64 login: root (automatic login)
11020 12:31:08.713952
11021 12:31:08.714020
11022 12:31:08.730380 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11023 12:31:08.730510
11024 12:31:08.736961 The programs included with the Debian GNU/Linux system are free software;
11025 12:31:08.753050 the exact distribution terms for each program are described<4>[ 19.593055] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11026 12:31:08.753200 in the
11027 12:31:08.756586 individual files in /usr/share/doc/*/copyright.
11028 12:31:08.756666
11029 12:31:08.763139 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11030 12:31:08.766668 permitted by applicable law.
11031 12:31:08.767179 Matched prompt #10: / #
11033 12:31:08.767464 Setting prompt string to ['/ #']
11034 12:31:08.767562 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11036 12:31:08.767767 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11037 12:31:08.767858 start: 2.2.6 expect-shell-connection (timeout 00:02:57) [common]
11038 12:31:08.767934 Setting prompt string to ['/ #']
11039 12:31:08.767996 Forcing a shell prompt, looking for ['/ #']
11041 12:31:08.818203 / #
11042 12:31:08.818364 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11043 12:31:08.818455 Waiting using forced prompt support (timeout 00:02:30)
11044 12:31:08.823263
11045 12:31:08.823586 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11046 12:31:08.823714 start: 2.2.7 export-device-env (timeout 00:02:56) [common]
11047 12:31:08.823848 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11048 12:31:08.823974 end: 2.2 depthcharge-retry (duration 00:02:04) [common]
11049 12:31:08.824092 end: 2 depthcharge-action (duration 00:02:04) [common]
11050 12:31:08.824214 start: 3 lava-test-retry (timeout 00:05:00) [common]
11051 12:31:08.824337 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11052 12:31:08.824450 Using namespace: common
11054 12:31:08.924834 / # #
11055 12:31:08.925018 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11056 12:31:08.925145 <4>[ 19.711738] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11057 12:31:08.929744 #
11058 12:31:08.930016 Using /lava-10605794
11060 12:31:09.030346 / # export SHELL=/bin/sh
11061 12:31:09.030596 <4>[ 19.832014] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11062 12:31:09.035510 export SHELL=/bin/sh
11064 12:31:09.136011 / # . /lava-10605794/environment
11065 12:31:09.136253 . /lava-10605794/environment<3>[ 19.949802] mt7921e 0000:01:00.0: hardware init failed
11066 12:31:09.136372 <6>[ 19.951852] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11067 12:31:09.136477 <6>[ 19.963203] r8152 2-1.3:1.0 enx002432307852: carrier on
11068 12:31:09.140963
11070 12:31:09.241514 / # /lava-10605794/bin/lava-test-runner /lava-10605794/0
11071 12:31:09.241690 Test shell timeout: 10s (minimum of the action and connection timeout)
11072 12:31:09.246449 /lava-10605794/bin/lava-test-runner /lava-10605794/0
11073 12:31:09.265589 + export TESTRUN_ID=0_cros-ec
11074 12:31:09.272043 +<8>[ 20.118092] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10605794_1.5.2.3.1>
11075 12:31:09.272351 Received signal: <STARTRUN> 0_cros-ec 10605794_1.5.2.3.1
11076 12:31:09.272461 Starting test lava.0_cros-ec (10605794_1.5.2.3.1)
11077 12:31:09.272582 Skipping test definition patterns.
11078 12:31:09.275369 cd /lava-10605794/0/tests/0_cros-ec
11079 12:31:09.278697 + cat uuid
11080 12:31:09.278804 + UUID=10605794_1.5.2.3.1
11081 12:31:09.278897 + set +x
11082 12:31:09.285069 + python3 -m cros.runners.lava_runner -v
11083 12:31:09.974861 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11084 12:31:09.981668 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11085 12:31:09.984694
11086 12:31:09.991382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11087 12:31:09.991677 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11089 12:31:09.998578 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11090 12:31:10.005072 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11091 12:31:10.005176
11092 12:31:10.015086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11093 12:31:10.015391 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11095 12:31:10.021580 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11096 12:31:10.028353 Checks the cros-ec gyros<8>[ 20.873693] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10605794_1.5.2.3.1>
11097 12:31:10.028646 Received signal: <ENDRUN> 0_cros-ec 10605794_1.5.2.3.1
11098 12:31:10.028774 Ending use of test pattern.
11099 12:31:10.028889 Ending test lava.0_cros-ec (10605794_1.5.2.3.1), duration 0.76
11101 12:31:10.031425 cope IIO ABI. ... skipped 'No cros-ec-gyro found'
11102 12:31:10.031550
11103 12:31:10.037708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11104 12:31:10.038007 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11106 12:31:10.044691 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11107 12:31:10.051134 Checks the standard ABI for the main Embedded Controller. ... ok
11108 12:31:10.051242
11109 12:31:10.054234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11110 12:31:10.054484 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11112 12:31:10.060988 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11113 12:31:10.067431 Checks the main Embedded controller character device. ... ok
11114 12:31:10.067516
11115 12:31:10.071019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11116 12:31:10.071269 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11118 12:31:10.077329 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11119 12:31:10.084014 Checks basic comunication with the main Embedded controller. ... ok
11120 12:31:10.084143
11121 12:31:10.090746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11122 12:31:10.091028 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11124 12:31:10.094423 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11125 12:31:10.104255 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11126 12:31:10.104350
11127 12:31:10.107438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11128 12:31:10.107692 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11130 12:31:10.113860 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11131 12:31:10.120460 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11132 12:31:10.120541
11133 12:31:10.127176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11134 12:31:10.127462 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11136 12:31:10.134070 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11137 12:31:10.140305 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11138 12:31:10.140410
11139 12:31:10.147007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11140 12:31:10.147280 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11142 12:31:10.150129 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11143 12:31:10.160367 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11144 12:31:10.160456
11145 12:31:10.163524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11146 12:31:10.163856 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11148 12:31:10.170007 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11149 12:31:10.179990 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11150 12:31:10.180097
11151 12:31:10.183459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11152 12:31:10.183771 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11154 12:31:10.190057 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11155 12:31:10.196177 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11156 12:31:10.196280
11157 12:31:10.202860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11158 12:31:10.203150 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11160 12:31:10.209708 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11161 12:31:10.216090 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11162 12:31:10.216200
11163 12:31:10.223011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11164 12:31:10.223282 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11166 12:31:10.229403 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11167 12:31:10.235877 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11168 12:31:10.235978
11169 12:31:10.242759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11170 12:31:10.243053 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11172 12:31:10.249066 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11173 12:31:10.255521 Check the cros battery ABI. ... skipped 'No BAT found'
11174 12:31:10.255685
11175 12:31:10.262430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11176 12:31:10.262713 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11178 12:31:10.268980 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11179 12:31:10.275303 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11180 12:31:10.275431
11181 12:31:10.282256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11182 12:31:10.282556 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11184 12:31:10.285426 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11185 12:31:10.291677 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11186 12:31:10.295231
11187 12:31:10.298294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11188 12:31:10.298575 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11190 12:31:10.305108 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11191 12:31:10.311899 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11192 12:31:10.311986
11193 12:31:10.318238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11194 12:31:10.318323
11195 12:31:10.318562 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11197 12:31:10.324616 ----------------------------------------------------------------------
11198 12:31:10.328537 Ran 18 tests in 0.010s
11199 12:31:10.328622
11200 12:31:10.328688 OK (skipped=15)
11201 12:31:10.331130 + set +x
11202 12:31:10.331215 <LAVA_TEST_RUNNER EXIT>
11203 12:31:10.331453 ok: lava_test_shell seems to have completed
11204 12:31:10.331629 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11205 12:31:10.331726 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11206 12:31:10.331814 end: 3 lava-test-retry (duration 00:00:02) [common]
11207 12:31:10.331901 start: 4 finalize (timeout 00:07:33) [common]
11208 12:31:10.331991 start: 4.1 power-off (timeout 00:00:30) [common]
11209 12:31:10.332147 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11210 12:31:10.414137 >> Command sent successfully.
11211 12:31:10.417158 Returned 0 in 0 seconds
11212 12:31:10.517630 end: 4.1 power-off (duration 00:00:00) [common]
11214 12:31:10.518091 start: 4.2 read-feedback (timeout 00:07:33) [common]
11215 12:31:10.518395 Listened to connection for namespace 'common' for up to 1s
11216 12:31:11.519313 Finalising connection for namespace 'common'
11217 12:31:11.519504 Disconnecting from shell: Finalise
11218 12:31:11.519592 / #
11219 12:31:11.619905 end: 4.2 read-feedback (duration 00:00:01) [common]
11220 12:31:11.620080 end: 4 finalize (duration 00:00:01) [common]
11221 12:31:11.620197 Cleaning after the job
11222 12:31:11.620299 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/ramdisk
11223 12:31:11.625508 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/kernel
11224 12:31:11.631543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/dtb
11225 12:31:11.631717 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605794/tftp-deploy-_yyx4mc8/modules
11226 12:31:11.637048 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605794
11227 12:31:11.738922 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605794
11228 12:31:11.739105 Job finished correctly